1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Automatically generated error messages for cn63xxp1.
46 * This file is auto generated. Do not edit.
50 * <hr><h2>Error tree for CN63XXP1</h2>
55 * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica];
56 * edge [fontsize=7, font=helvitica];
57 * cvmx_root [label="ROOT|<root>root"];
58 * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"];
59 * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
60 * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"];
61 * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"];
62 * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"];
63 * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"];
64 * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"];
65 * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"];
66 * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"];
67 * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"];
68 * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"];
69 * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<tad0>tad0"];
70 * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"];
71 * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"];
72 * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"];
73 * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"];
74 * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"];
75 * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"];
76 * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"];
77 * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"];
78 * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"];
79 * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"];
80 * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"];
81 * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
82 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"];
83 * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
84 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"];
85 * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
86 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"];
87 * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"];
88 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"];
89 * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"];
90 * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"];
91 * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"];
92 * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"];
93 * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"];
94 * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"];
95 * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
96 * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
97 * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"];
98 * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"];
99 * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"];
100 * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"];
101 * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"];
102 * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"];
103 * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"];
104 * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"];
105 * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"];
106 * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"];
107 * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"];
108 * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"];
109 * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"];
110 * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"];
111 * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"];
112 * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"];
113 * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"];
114 * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"];
115 * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"];
116 * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"];
117 * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"];
118 * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"];
119 * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"];
120 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"];
121 * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
122 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"];
123 * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
124 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"];
125 * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
126 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"];
127 * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"];
128 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"];
129 * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"];
130 * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"];
131 * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"];
132 * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"];
133 * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"];
134 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"];
135 * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"];
136 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"];
137 * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"];
138 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"];
139 * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"];
140 * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"];
141 * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"];
142 * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"];
143 * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"];
144 * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"];
145 * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
146 * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"];
147 * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"];
148 * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"];
149 * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"];
150 * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"];
151 * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"];
152 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"];
153 * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"];
154 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"];
155 * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"];
156 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"];
157 * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"];
158 * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"];
159 * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis];
160 * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis];
161 * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis];
162 * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis];
163 * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis];
164 * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis];
165 * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis];
166 * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis];
167 * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis];
168 * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis];
169 * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis];
170 * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis];
171 * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis];
172 * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis];
173 * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis];
174 * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis];
175 * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"];
179 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
180 #include <asm/octeon/cvmx.h>
181 #include <asm/octeon/cvmx-error.h>
182 #include <asm/octeon/cvmx-error-custom.h>
183 #include <asm/octeon/cvmx-csr-typedefs.h>
186 #include "cvmx-error.h"
187 #include "cvmx-error-custom.h"
190 int cvmx_error_initialize_cn63xxp1(void);
192 int cvmx_error_initialize_cn63xxp1(void)
194 cvmx_error_info_t info;
197 /* CVMX_CIU_INTX_SUM0(0) */
198 info.reg_type = CVMX_ERROR_REGISTER_IO64;
199 info.status_addr = CVMX_CIU_INTX_SUM0(0);
200 info.status_mask = 0;
201 info.enable_addr = 0;
202 info.enable_mask = 0;
204 info.group = CVMX_ERROR_GROUP_INTERNAL;
205 info.group_index = 0;
206 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
207 info.parent.status_addr = 0;
208 info.parent.status_mask = 0;
209 info.func = __cvmx_error_decode;
211 fail |= cvmx_error_add(&info);
213 /* CVMX_MIXX_ISR(0) */
214 info.reg_type = CVMX_ERROR_REGISTER_IO64;
215 info.status_addr = CVMX_MIXX_ISR(0);
216 info.status_mask = 1ull<<0 /* odblovf */;
217 info.enable_addr = CVMX_MIXX_INTENA(0);
218 info.enable_mask = 1ull<<0 /* ovfena */;
220 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
221 info.group_index = 0;
222 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
223 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
224 info.parent.status_mask = 1ull<<62 /* mii */;
225 info.func = __cvmx_error_display;
226 info.user_info = (long)
227 "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
228 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
229 " with a value greater than the remaining #of\n"
230 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
231 " the following occurs:\n"
232 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
233 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
234 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
235 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
236 " and the local interrupt mask bit(OVFENA) is set, than an\n"
237 " interrupt is reported for this event.\n"
238 " SW should keep track of the #I-Ring Entries in use\n"
239 " (ie: cumulative # of ODBELL writes), and ensure that\n"
240 " future ODBELL writes don't exceed the size of the\n"
241 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
242 " SW must reclaim O-Ring Entries by writing to the\n"
243 " MIX_ORCNT[ORCNT]. .\n"
244 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
245 " If it occurs, it's an indication that SW has\n"
246 " overwritten the O-Ring buffer, and the only recourse\n"
248 fail |= cvmx_error_add(&info);
250 info.reg_type = CVMX_ERROR_REGISTER_IO64;
251 info.status_addr = CVMX_MIXX_ISR(0);
252 info.status_mask = 1ull<<1 /* idblovf */;
253 info.enable_addr = CVMX_MIXX_INTENA(0);
254 info.enable_mask = 1ull<<1 /* ivfena */;
256 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
257 info.group_index = 0;
258 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
259 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
260 info.parent.status_mask = 1ull<<62 /* mii */;
261 info.func = __cvmx_error_display;
262 info.user_info = (long)
263 "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
264 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
265 " with a value greater than the remaining #of\n"
266 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
267 " the following occurs:\n"
268 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
269 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
270 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
271 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
272 " and the local interrupt mask bit(IVFENA) is set, than an\n"
273 " interrupt is reported for this event.\n"
274 " SW should keep track of the #I-Ring Entries in use\n"
275 " (ie: cumulative # of IDBELL writes), and ensure that\n"
276 " future IDBELL writes don't exceed the size of the\n"
277 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
278 " SW must reclaim I-Ring Entries by keeping track of the\n"
279 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
280 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
281 " total #packets(not IRing Entries) and SW must further\n"
282 " keep track of the # of I-Ring Entries associated with\n"
283 " each packet as they are processed.\n"
284 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
285 " If it occurs, it's an indication that SW has\n"
286 " overwritten the I-Ring buffer, and the only recourse\n"
288 fail |= cvmx_error_add(&info);
290 info.reg_type = CVMX_ERROR_REGISTER_IO64;
291 info.status_addr = CVMX_MIXX_ISR(0);
292 info.status_mask = 1ull<<4 /* data_drp */;
293 info.enable_addr = CVMX_MIXX_INTENA(0);
294 info.enable_mask = 1ull<<4 /* data_drpena */;
296 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
297 info.group_index = 0;
298 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
299 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
300 info.parent.status_mask = 1ull<<62 /* mii */;
301 info.func = __cvmx_error_display;
302 info.user_info = (long)
303 "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
304 " If this does occur, the DATA_DRP is set and the\n"
305 " CIU_INTx_SUM0,4[MII] bits are set.\n"
306 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
307 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
308 " interrupt is reported for this event.\n";
309 fail |= cvmx_error_add(&info);
311 info.reg_type = CVMX_ERROR_REGISTER_IO64;
312 info.status_addr = CVMX_MIXX_ISR(0);
313 info.status_mask = 1ull<<5 /* irun */;
314 info.enable_addr = CVMX_MIXX_INTENA(0);
315 info.enable_mask = 1ull<<5 /* irunena */;
317 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
318 info.group_index = 0;
319 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
320 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
321 info.parent.status_mask = 1ull<<62 /* mii */;
322 info.func = __cvmx_error_display;
323 info.user_info = (long)
324 "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n"
325 " If SW writes a larger value than what is currently\n"
326 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
327 " underflow condition.\n"
328 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
329 " NOTE: If an IRUN underflow condition is detected,\n"
330 " the integrity of the MIX/AGL HW state has\n"
331 " been compromised. To recover, SW must issue a\n"
332 " software reset sequence (see: MIX_CTL[RESET]\n";
333 fail |= cvmx_error_add(&info);
335 info.reg_type = CVMX_ERROR_REGISTER_IO64;
336 info.status_addr = CVMX_MIXX_ISR(0);
337 info.status_mask = 1ull<<6 /* orun */;
338 info.enable_addr = CVMX_MIXX_INTENA(0);
339 info.enable_mask = 1ull<<6 /* orunena */;
341 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
342 info.group_index = 0;
343 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
344 info.parent.status_addr = CVMX_CIU_INTX_SUM0(0);
345 info.parent.status_mask = 1ull<<62 /* mii */;
346 info.func = __cvmx_error_display;
347 info.user_info = (long)
348 "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n"
349 " If SW writes a larger value than what is currently\n"
350 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
351 " underflow condition.\n"
352 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
353 " NOTE: If an ORUN underflow condition is detected,\n"
354 " the integrity of the MIX/AGL HW state has\n"
355 " been compromised. To recover, SW must issue a\n"
356 " software reset sequence (see: MIX_CTL[RESET]\n";
357 fail |= cvmx_error_add(&info);
359 /* CVMX_CIU_INT_SUM1 */
360 info.reg_type = CVMX_ERROR_REGISTER_IO64;
361 info.status_addr = CVMX_CIU_INT_SUM1;
362 info.status_mask = 0;
363 info.enable_addr = 0;
364 info.enable_mask = 0;
366 info.group = CVMX_ERROR_GROUP_INTERNAL;
367 info.group_index = 0;
368 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
369 info.parent.status_addr = 0;
370 info.parent.status_mask = 0;
371 info.func = __cvmx_error_decode;
373 fail |= cvmx_error_add(&info);
375 /* CVMX_MIXX_ISR(1) */
376 info.reg_type = CVMX_ERROR_REGISTER_IO64;
377 info.status_addr = CVMX_MIXX_ISR(1);
378 info.status_mask = 1ull<<0 /* odblovf */;
379 info.enable_addr = CVMX_MIXX_INTENA(1);
380 info.enable_mask = 1ull<<0 /* ovfena */;
382 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
383 info.group_index = 1;
384 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
385 info.parent.status_addr = CVMX_CIU_INT_SUM1;
386 info.parent.status_mask = 1ull<<18 /* mii1 */;
387 info.func = __cvmx_error_display;
388 info.user_info = (long)
389 "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n"
390 " If SW attempts to write to the MIX_ORING2[ODBELL]\n"
391 " with a value greater than the remaining #of\n"
392 " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n"
393 " the following occurs:\n"
394 " 1) The MIX_ORING2[ODBELL] write is IGNORED\n"
395 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
396 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
397 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
398 " and the local interrupt mask bit(OVFENA) is set, than an\n"
399 " interrupt is reported for this event.\n"
400 " SW should keep track of the #I-Ring Entries in use\n"
401 " (ie: cumulative # of ODBELL writes), and ensure that\n"
402 " future ODBELL writes don't exceed the size of the\n"
403 " O-Ring Buffer (MIX_ORING2[OSIZE]).\n"
404 " SW must reclaim O-Ring Entries by writing to the\n"
405 " MIX_ORCNT[ORCNT]. .\n"
406 " NOTE: There is no recovery from an ODBLOVF Interrupt.\n"
407 " If it occurs, it's an indication that SW has\n"
408 " overwritten the O-Ring buffer, and the only recourse\n"
410 fail |= cvmx_error_add(&info);
412 info.reg_type = CVMX_ERROR_REGISTER_IO64;
413 info.status_addr = CVMX_MIXX_ISR(1);
414 info.status_mask = 1ull<<1 /* idblovf */;
415 info.enable_addr = CVMX_MIXX_INTENA(1);
416 info.enable_mask = 1ull<<1 /* ivfena */;
418 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
419 info.group_index = 1;
420 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
421 info.parent.status_addr = CVMX_CIU_INT_SUM1;
422 info.parent.status_mask = 1ull<<18 /* mii1 */;
423 info.func = __cvmx_error_display;
424 info.user_info = (long)
425 "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n"
426 " If SW attempts to write to the MIX_IRING2[IDBELL]\n"
427 " with a value greater than the remaining #of\n"
428 " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n"
429 " the following occurs:\n"
430 " 1) The MIX_IRING2[IDBELL] write is IGNORED\n"
431 " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n"
432 " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n"
433 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
434 " and the local interrupt mask bit(IVFENA) is set, than an\n"
435 " interrupt is reported for this event.\n"
436 " SW should keep track of the #I-Ring Entries in use\n"
437 " (ie: cumulative # of IDBELL writes), and ensure that\n"
438 " future IDBELL writes don't exceed the size of the\n"
439 " I-Ring Buffer (MIX_IRING2[ISIZE]).\n"
440 " SW must reclaim I-Ring Entries by keeping track of the\n"
441 " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n"
442 " NOTE: The MIX_IRCNT[IRCNT] register represents the\n"
443 " total #packets(not IRing Entries) and SW must further\n"
444 " keep track of the # of I-Ring Entries associated with\n"
445 " each packet as they are processed.\n"
446 " NOTE: There is no recovery from an IDBLOVF Interrupt.\n"
447 " If it occurs, it's an indication that SW has\n"
448 " overwritten the I-Ring buffer, and the only recourse\n"
450 fail |= cvmx_error_add(&info);
452 info.reg_type = CVMX_ERROR_REGISTER_IO64;
453 info.status_addr = CVMX_MIXX_ISR(1);
454 info.status_mask = 1ull<<4 /* data_drp */;
455 info.enable_addr = CVMX_MIXX_INTENA(1);
456 info.enable_mask = 1ull<<4 /* data_drpena */;
458 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
459 info.group_index = 1;
460 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
461 info.parent.status_addr = CVMX_CIU_INT_SUM1;
462 info.parent.status_mask = 1ull<<18 /* mii1 */;
463 info.func = __cvmx_error_display;
464 info.user_info = (long)
465 "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n"
466 " If this does occur, the DATA_DRP is set and the\n"
467 " CIU_INTx_SUM0,4[MII] bits are set.\n"
468 " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n"
469 " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n"
470 " interrupt is reported for this event.\n";
471 fail |= cvmx_error_add(&info);
473 info.reg_type = CVMX_ERROR_REGISTER_IO64;
474 info.status_addr = CVMX_MIXX_ISR(1);
475 info.status_mask = 1ull<<5 /* irun */;
476 info.enable_addr = CVMX_MIXX_INTENA(1);
477 info.enable_mask = 1ull<<5 /* irunena */;
479 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
480 info.group_index = 1;
481 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
482 info.parent.status_addr = CVMX_CIU_INT_SUM1;
483 info.parent.status_mask = 1ull<<18 /* mii1 */;
484 info.func = __cvmx_error_display;
485 info.user_info = (long)
486 "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n"
487 " If SW writes a larger value than what is currently\n"
488 " in the MIX_IRCNT[IRCNT], then HW will report the\n"
489 " underflow condition.\n"
490 " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n"
491 " NOTE: If an IRUN underflow condition is detected,\n"
492 " the integrity of the MIX/AGL HW state has\n"
493 " been compromised. To recover, SW must issue a\n"
494 " software reset sequence (see: MIX_CTL[RESET]\n";
495 fail |= cvmx_error_add(&info);
497 info.reg_type = CVMX_ERROR_REGISTER_IO64;
498 info.status_addr = CVMX_MIXX_ISR(1);
499 info.status_mask = 1ull<<6 /* orun */;
500 info.enable_addr = CVMX_MIXX_INTENA(1);
501 info.enable_mask = 1ull<<6 /* orunena */;
503 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
504 info.group_index = 1;
505 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
506 info.parent.status_addr = CVMX_CIU_INT_SUM1;
507 info.parent.status_mask = 1ull<<18 /* mii1 */;
508 info.func = __cvmx_error_display;
509 info.user_info = (long)
510 "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n"
511 " If SW writes a larger value than what is currently\n"
512 " in the MIX_ORCNT[ORCNT], then HW will report the\n"
513 " underflow condition.\n"
514 " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n"
515 " NOTE: If an ORUN underflow condition is detected,\n"
516 " the integrity of the MIX/AGL HW state has\n"
517 " been compromised. To recover, SW must issue a\n"
518 " software reset sequence (see: MIX_CTL[RESET]\n";
519 fail |= cvmx_error_add(&info);
522 info.reg_type = CVMX_ERROR_REGISTER_IO64;
523 info.status_addr = CVMX_NDF_INT;
524 info.status_mask = 1ull<<2 /* wdog */;
525 info.enable_addr = CVMX_NDF_INT_EN;
526 info.enable_mask = 1ull<<2 /* wdog */;
528 info.group = CVMX_ERROR_GROUP_INTERNAL;
529 info.group_index = 0;
530 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
531 info.parent.status_addr = CVMX_CIU_INT_SUM1;
532 info.parent.status_mask = 1ull<<19 /* nand */;
533 info.func = __cvmx_error_display;
534 info.user_info = (long)
535 "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n";
536 fail |= cvmx_error_add(&info);
538 info.reg_type = CVMX_ERROR_REGISTER_IO64;
539 info.status_addr = CVMX_NDF_INT;
540 info.status_mask = 1ull<<3 /* sm_bad */;
541 info.enable_addr = CVMX_NDF_INT_EN;
542 info.enable_mask = 1ull<<3 /* sm_bad */;
544 info.group = CVMX_ERROR_GROUP_INTERNAL;
545 info.group_index = 0;
546 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
547 info.parent.status_addr = CVMX_CIU_INT_SUM1;
548 info.parent.status_mask = 1ull<<19 /* nand */;
549 info.func = __cvmx_error_display;
550 info.user_info = (long)
551 "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n";
552 fail |= cvmx_error_add(&info);
554 info.reg_type = CVMX_ERROR_REGISTER_IO64;
555 info.status_addr = CVMX_NDF_INT;
556 info.status_mask = 1ull<<4 /* ecc_1bit */;
557 info.enable_addr = CVMX_NDF_INT_EN;
558 info.enable_mask = 1ull<<4 /* ecc_1bit */;
560 info.group = CVMX_ERROR_GROUP_INTERNAL;
561 info.group_index = 0;
562 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
563 info.parent.status_addr = CVMX_CIU_INT_SUM1;
564 info.parent.status_mask = 1ull<<19 /* nand */;
565 info.func = __cvmx_error_display;
566 info.user_info = (long)
567 "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n";
568 fail |= cvmx_error_add(&info);
570 info.reg_type = CVMX_ERROR_REGISTER_IO64;
571 info.status_addr = CVMX_NDF_INT;
572 info.status_mask = 1ull<<5 /* ecc_mult */;
573 info.enable_addr = CVMX_NDF_INT_EN;
574 info.enable_mask = 1ull<<5 /* ecc_mult */;
576 info.group = CVMX_ERROR_GROUP_INTERNAL;
577 info.group_index = 0;
578 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
579 info.parent.status_addr = CVMX_CIU_INT_SUM1;
580 info.parent.status_mask = 1ull<<19 /* nand */;
581 info.func = __cvmx_error_display;
582 info.user_info = (long)
583 "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n";
584 fail |= cvmx_error_add(&info);
586 info.reg_type = CVMX_ERROR_REGISTER_IO64;
587 info.status_addr = CVMX_NDF_INT;
588 info.status_mask = 1ull<<6 /* ovrf */;
589 info.enable_addr = CVMX_NDF_INT_EN;
590 info.enable_mask = 1ull<<6 /* ovrf */;
592 info.group = CVMX_ERROR_GROUP_INTERNAL;
593 info.group_index = 0;
594 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
595 info.parent.status_addr = CVMX_CIU_INT_SUM1;
596 info.parent.status_mask = 1ull<<19 /* nand */;
597 info.func = __cvmx_error_display;
598 info.user_info = (long)
599 "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n"
601 fail |= cvmx_error_add(&info);
603 /* CVMX_CIU_BLOCK_INT */
604 info.reg_type = CVMX_ERROR_REGISTER_IO64;
605 info.status_addr = CVMX_CIU_BLOCK_INT;
606 info.status_mask = 0;
607 info.enable_addr = 0;
608 info.enable_mask = 0;
610 info.group = CVMX_ERROR_GROUP_INTERNAL;
611 info.group_index = 0;
612 info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE;
613 info.parent.status_addr = 0;
614 info.parent.status_mask = 0;
615 info.func = __cvmx_error_decode;
617 fail |= cvmx_error_add(&info);
619 /* CVMX_L2C_INT_REG */
620 info.reg_type = CVMX_ERROR_REGISTER_IO64;
621 info.status_addr = CVMX_L2C_INT_REG;
622 info.status_mask = 1ull<<0 /* holerd */;
623 info.enable_addr = CVMX_L2C_INT_ENA;
624 info.enable_mask = 1ull<<0 /* holerd */;
626 info.group = CVMX_ERROR_GROUP_INTERNAL;
627 info.group_index = 0;
628 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
629 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
630 info.parent.status_mask = 1ull<<16 /* l2c */;
631 info.func = __cvmx_error_display;
632 info.user_info = (long)
633 "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n";
634 fail |= cvmx_error_add(&info);
636 info.reg_type = CVMX_ERROR_REGISTER_IO64;
637 info.status_addr = CVMX_L2C_INT_REG;
638 info.status_mask = 1ull<<1 /* holewr */;
639 info.enable_addr = CVMX_L2C_INT_ENA;
640 info.enable_mask = 1ull<<1 /* holewr */;
642 info.group = CVMX_ERROR_GROUP_INTERNAL;
643 info.group_index = 0;
644 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
645 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
646 info.parent.status_mask = 1ull<<16 /* l2c */;
647 info.func = __cvmx_error_display;
648 info.user_info = (long)
649 "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n";
650 fail |= cvmx_error_add(&info);
652 info.reg_type = CVMX_ERROR_REGISTER_IO64;
653 info.status_addr = CVMX_L2C_INT_REG;
654 info.status_mask = 1ull<<2 /* vrtwr */;
655 info.enable_addr = CVMX_L2C_INT_ENA;
656 info.enable_mask = 1ull<<2 /* vrtwr */;
658 info.group = CVMX_ERROR_GROUP_INTERNAL;
659 info.group_index = 0;
660 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
661 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
662 info.parent.status_mask = 1ull<<16 /* l2c */;
663 info.func = __cvmx_error_display;
664 info.user_info = (long)
665 "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n"
666 " Set when L2C_VRT_MEM blocked a store.\n";
667 fail |= cvmx_error_add(&info);
669 info.reg_type = CVMX_ERROR_REGISTER_IO64;
670 info.status_addr = CVMX_L2C_INT_REG;
671 info.status_mask = 1ull<<3 /* vrtidrng */;
672 info.enable_addr = CVMX_L2C_INT_ENA;
673 info.enable_mask = 1ull<<3 /* vrtidrng */;
675 info.group = CVMX_ERROR_GROUP_INTERNAL;
676 info.group_index = 0;
677 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
678 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
679 info.parent.status_mask = 1ull<<16 /* l2c */;
680 info.func = __cvmx_error_display;
681 info.user_info = (long)
682 "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n"
683 " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n"
685 fail |= cvmx_error_add(&info);
687 info.reg_type = CVMX_ERROR_REGISTER_IO64;
688 info.status_addr = CVMX_L2C_INT_REG;
689 info.status_mask = 1ull<<4 /* vrtadrng */;
690 info.enable_addr = CVMX_L2C_INT_ENA;
691 info.enable_mask = 1ull<<4 /* vrtadrng */;
693 info.group = CVMX_ERROR_GROUP_INTERNAL;
694 info.group_index = 0;
695 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
696 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
697 info.parent.status_mask = 1ull<<16 /* l2c */;
698 info.func = __cvmx_error_display;
699 info.user_info = (long)
700 "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n"
701 " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n"
703 " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n";
704 fail |= cvmx_error_add(&info);
706 info.reg_type = CVMX_ERROR_REGISTER_IO64;
707 info.status_addr = CVMX_L2C_INT_REG;
708 info.status_mask = 1ull<<5 /* vrtpe */;
709 info.enable_addr = CVMX_L2C_INT_ENA;
710 info.enable_mask = 1ull<<5 /* vrtpe */;
712 info.group = CVMX_ERROR_GROUP_INTERNAL;
713 info.group_index = 0;
714 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
715 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
716 info.parent.status_mask = 1ull<<16 /* l2c */;
717 info.func = __cvmx_error_display;
718 info.user_info = (long)
719 "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n"
720 " Whenever an L2C_VRT_MEM read finds a parity error,\n"
721 " that L2C_VRT_MEM cannot cause stores to be blocked.\n"
722 " Software should correct the error.\n";
723 fail |= cvmx_error_add(&info);
725 info.reg_type = CVMX_ERROR_REGISTER_IO64;
726 info.status_addr = CVMX_L2C_INT_REG;
727 info.status_mask = 0;
728 info.enable_addr = 0;
729 info.enable_mask = 0;
731 info.group = CVMX_ERROR_GROUP_INTERNAL;
732 info.group_index = 0;
733 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
734 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
735 info.parent.status_mask = 1ull<<16 /* l2c */;
736 info.func = __cvmx_error_decode;
738 fail |= cvmx_error_add(&info);
740 /* CVMX_L2C_ERR_TDTX(0) */
741 info.reg_type = CVMX_ERROR_REGISTER_IO64;
742 info.status_addr = CVMX_L2C_ERR_TDTX(0);
743 info.status_mask = 1ull<<60 /* vsbe */;
744 info.enable_addr = 0;
745 info.enable_mask = 0;
747 info.group = CVMX_ERROR_GROUP_INTERNAL;
748 info.group_index = 0;
749 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
750 info.parent.status_addr = CVMX_L2C_INT_REG;
751 info.parent.status_mask = 1ull<<16 /* tad0 */;
752 info.func = __cvmx_error_display;
753 info.user_info = (long)
754 "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n";
755 fail |= cvmx_error_add(&info);
757 info.reg_type = CVMX_ERROR_REGISTER_IO64;
758 info.status_addr = CVMX_L2C_ERR_TDTX(0);
759 info.status_mask = 1ull<<61 /* vdbe */;
760 info.enable_addr = 0;
761 info.enable_mask = 0;
763 info.group = CVMX_ERROR_GROUP_INTERNAL;
764 info.group_index = 0;
765 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
766 info.parent.status_addr = CVMX_L2C_INT_REG;
767 info.parent.status_mask = 1ull<<16 /* tad0 */;
768 info.func = __cvmx_error_display;
769 info.user_info = (long)
770 "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n";
771 fail |= cvmx_error_add(&info);
773 info.reg_type = CVMX_ERROR_REGISTER_IO64;
774 info.status_addr = CVMX_L2C_ERR_TDTX(0);
775 info.status_mask = 1ull<<62 /* sbe */;
776 info.enable_addr = 0;
777 info.enable_mask = 0;
779 info.group = CVMX_ERROR_GROUP_INTERNAL;
780 info.group_index = 0;
781 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
782 info.parent.status_addr = CVMX_L2C_INT_REG;
783 info.parent.status_mask = 1ull<<16 /* tad0 */;
784 info.func = __cvmx_error_display;
785 info.user_info = (long)
786 "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n";
787 fail |= cvmx_error_add(&info);
789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
790 info.status_addr = CVMX_L2C_ERR_TDTX(0);
791 info.status_mask = 1ull<<63 /* dbe */;
792 info.enable_addr = 0;
793 info.enable_mask = 0;
795 info.group = CVMX_ERROR_GROUP_INTERNAL;
796 info.group_index = 0;
797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
798 info.parent.status_addr = CVMX_L2C_INT_REG;
799 info.parent.status_mask = 1ull<<16 /* tad0 */;
800 info.func = __cvmx_error_display;
801 info.user_info = (long)
802 "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n";
803 fail |= cvmx_error_add(&info);
805 /* CVMX_L2C_ERR_TTGX(0) */
806 info.reg_type = CVMX_ERROR_REGISTER_IO64;
807 info.status_addr = CVMX_L2C_ERR_TTGX(0);
808 info.status_mask = 1ull<<61 /* noway */;
809 info.enable_addr = 0;
810 info.enable_mask = 0;
812 info.group = CVMX_ERROR_GROUP_INTERNAL;
813 info.group_index = 0;
814 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
815 info.parent.status_addr = CVMX_L2C_INT_REG;
816 info.parent.status_mask = 1ull<<16 /* tad0 */;
817 info.func = __cvmx_error_display;
818 info.user_info = (long)
819 "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n"
820 " L2C sets NOWAY during its processing of a\n"
821 " transaction whenever it needed/wanted to allocate\n"
822 " a WAY in the L2 cache, but was unable to. NOWAY==1\n"
823 " is (generally) not an indication that L2C failed to\n"
824 " complete transactions. Rather, it is a hint of\n"
825 " possible performance degradation. (For example, L2C\n"
826 " must read-modify-write DRAM for every transaction\n"
827 " that updates some, but not all, of the bytes in a\n"
828 " cache block, misses in the L2 cache, and cannot\n"
829 " allocate a WAY.) There is one \"failure\" case where\n"
830 " L2C will set NOWAY: when it cannot leave a block\n"
831 " locked in the L2 cache as part of a LCKL2\n"
833 fail |= cvmx_error_add(&info);
835 info.reg_type = CVMX_ERROR_REGISTER_IO64;
836 info.status_addr = CVMX_L2C_ERR_TTGX(0);
837 info.status_mask = 1ull<<62 /* sbe */;
838 info.enable_addr = 0;
839 info.enable_mask = 0;
841 info.group = CVMX_ERROR_GROUP_INTERNAL;
842 info.group_index = 0;
843 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
844 info.parent.status_addr = CVMX_L2C_INT_REG;
845 info.parent.status_mask = 1ull<<16 /* tad0 */;
846 info.func = __cvmx_error_display;
847 info.user_info = (long)
848 "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n";
849 fail |= cvmx_error_add(&info);
851 info.reg_type = CVMX_ERROR_REGISTER_IO64;
852 info.status_addr = CVMX_L2C_ERR_TTGX(0);
853 info.status_mask = 1ull<<63 /* dbe */;
854 info.enable_addr = 0;
855 info.enable_mask = 0;
857 info.group = CVMX_ERROR_GROUP_INTERNAL;
858 info.group_index = 0;
859 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
860 info.parent.status_addr = CVMX_L2C_INT_REG;
861 info.parent.status_mask = 1ull<<16 /* tad0 */;
862 info.func = __cvmx_error_display;
863 info.user_info = (long)
864 "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n";
865 fail |= cvmx_error_add(&info);
867 /* CVMX_IPD_INT_SUM */
868 info.reg_type = CVMX_ERROR_REGISTER_IO64;
869 info.status_addr = CVMX_IPD_INT_SUM;
870 info.status_mask = 1ull<<0 /* prc_par0 */;
871 info.enable_addr = CVMX_IPD_INT_ENB;
872 info.enable_mask = 1ull<<0 /* prc_par0 */;
874 info.group = CVMX_ERROR_GROUP_INTERNAL;
875 info.group_index = 0;
876 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
877 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
878 info.parent.status_mask = 1ull<<9 /* ipd */;
879 info.func = __cvmx_error_display;
880 info.user_info = (long)
881 "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n"
882 " [31:0] of the PBM memory.\n";
883 fail |= cvmx_error_add(&info);
885 info.reg_type = CVMX_ERROR_REGISTER_IO64;
886 info.status_addr = CVMX_IPD_INT_SUM;
887 info.status_mask = 1ull<<1 /* prc_par1 */;
888 info.enable_addr = CVMX_IPD_INT_ENB;
889 info.enable_mask = 1ull<<1 /* prc_par1 */;
891 info.group = CVMX_ERROR_GROUP_INTERNAL;
892 info.group_index = 0;
893 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
894 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
895 info.parent.status_mask = 1ull<<9 /* ipd */;
896 info.func = __cvmx_error_display;
897 info.user_info = (long)
898 "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n"
899 " [63:32] of the PBM memory.\n";
900 fail |= cvmx_error_add(&info);
902 info.reg_type = CVMX_ERROR_REGISTER_IO64;
903 info.status_addr = CVMX_IPD_INT_SUM;
904 info.status_mask = 1ull<<2 /* prc_par2 */;
905 info.enable_addr = CVMX_IPD_INT_ENB;
906 info.enable_mask = 1ull<<2 /* prc_par2 */;
908 info.group = CVMX_ERROR_GROUP_INTERNAL;
909 info.group_index = 0;
910 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
911 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
912 info.parent.status_mask = 1ull<<9 /* ipd */;
913 info.func = __cvmx_error_display;
914 info.user_info = (long)
915 "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n"
916 " [95:64] of the PBM memory.\n";
917 fail |= cvmx_error_add(&info);
919 info.reg_type = CVMX_ERROR_REGISTER_IO64;
920 info.status_addr = CVMX_IPD_INT_SUM;
921 info.status_mask = 1ull<<3 /* prc_par3 */;
922 info.enable_addr = CVMX_IPD_INT_ENB;
923 info.enable_mask = 1ull<<3 /* prc_par3 */;
925 info.group = CVMX_ERROR_GROUP_INTERNAL;
926 info.group_index = 0;
927 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
928 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
929 info.parent.status_mask = 1ull<<9 /* ipd */;
930 info.func = __cvmx_error_display;
931 info.user_info = (long)
932 "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n"
933 " [127:96] of the PBM memory.\n";
934 fail |= cvmx_error_add(&info);
936 info.reg_type = CVMX_ERROR_REGISTER_IO64;
937 info.status_addr = CVMX_IPD_INT_SUM;
938 info.status_mask = 1ull<<4 /* bp_sub */;
939 info.enable_addr = CVMX_IPD_INT_ENB;
940 info.enable_mask = 1ull<<4 /* bp_sub */;
942 info.group = CVMX_ERROR_GROUP_INTERNAL;
943 info.group_index = 0;
944 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
945 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
946 info.parent.status_mask = 1ull<<9 /* ipd */;
947 info.func = __cvmx_error_display;
948 info.user_info = (long)
949 "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n"
950 " supplied illegal value.\n";
951 fail |= cvmx_error_add(&info);
953 info.reg_type = CVMX_ERROR_REGISTER_IO64;
954 info.status_addr = CVMX_IPD_INT_SUM;
955 info.status_mask = 1ull<<5 /* dc_ovr */;
956 info.enable_addr = CVMX_IPD_INT_ENB;
957 info.enable_mask = 1ull<<5 /* dc_ovr */;
959 info.group = CVMX_ERROR_GROUP_INTERNAL;
960 info.group_index = 0;
961 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
962 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
963 info.parent.status_mask = 1ull<<9 /* ipd */;
964 info.func = __cvmx_error_display;
965 info.user_info = (long)
966 "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n";
967 fail |= cvmx_error_add(&info);
969 info.reg_type = CVMX_ERROR_REGISTER_IO64;
970 info.status_addr = CVMX_IPD_INT_SUM;
971 info.status_mask = 1ull<<6 /* cc_ovr */;
972 info.enable_addr = CVMX_IPD_INT_ENB;
973 info.enable_mask = 1ull<<6 /* cc_ovr */;
975 info.group = CVMX_ERROR_GROUP_INTERNAL;
976 info.group_index = 0;
977 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
978 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
979 info.parent.status_mask = 1ull<<9 /* ipd */;
980 info.func = __cvmx_error_display;
981 info.user_info = (long)
982 "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n";
983 fail |= cvmx_error_add(&info);
985 info.reg_type = CVMX_ERROR_REGISTER_IO64;
986 info.status_addr = CVMX_IPD_INT_SUM;
987 info.status_mask = 1ull<<7 /* c_coll */;
988 info.enable_addr = CVMX_IPD_INT_ENB;
989 info.enable_mask = 1ull<<7 /* c_coll */;
991 info.group = CVMX_ERROR_GROUP_INTERNAL;
992 info.group_index = 0;
993 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
994 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
995 info.parent.status_mask = 1ull<<9 /* ipd */;
996 info.func = __cvmx_error_display;
997 info.user_info = (long)
998 "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n"
1000 fail |= cvmx_error_add(&info);
1002 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1003 info.status_addr = CVMX_IPD_INT_SUM;
1004 info.status_mask = 1ull<<8 /* d_coll */;
1005 info.enable_addr = CVMX_IPD_INT_ENB;
1006 info.enable_mask = 1ull<<8 /* d_coll */;
1008 info.group = CVMX_ERROR_GROUP_INTERNAL;
1009 info.group_index = 0;
1010 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1011 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1012 info.parent.status_mask = 1ull<<9 /* ipd */;
1013 info.func = __cvmx_error_display;
1014 info.user_info = (long)
1015 "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n"
1017 fail |= cvmx_error_add(&info);
1019 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1020 info.status_addr = CVMX_IPD_INT_SUM;
1021 info.status_mask = 1ull<<9 /* bc_ovr */;
1022 info.enable_addr = CVMX_IPD_INT_ENB;
1023 info.enable_mask = 1ull<<9 /* bc_ovr */;
1025 info.group = CVMX_ERROR_GROUP_INTERNAL;
1026 info.group_index = 0;
1027 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1028 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1029 info.parent.status_mask = 1ull<<9 /* ipd */;
1030 info.func = __cvmx_error_display;
1031 info.user_info = (long)
1032 "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n";
1033 fail |= cvmx_error_add(&info);
1035 /* CVMX_POW_ECC_ERR */
1036 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1037 info.status_addr = CVMX_POW_ECC_ERR;
1038 info.status_mask = 1ull<<0 /* sbe */;
1039 info.enable_addr = CVMX_POW_ECC_ERR;
1040 info.enable_mask = 1ull<<2 /* sbe_ie */;
1041 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
1042 info.group = CVMX_ERROR_GROUP_INTERNAL;
1043 info.group_index = 0;
1044 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1045 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1046 info.parent.status_mask = 1ull<<12 /* pow */;
1047 info.func = __cvmx_error_handle_pow_ecc_err_sbe;
1048 info.user_info = (long)
1049 "ERROR POW_ECC_ERR[SBE]: Single bit error\n";
1050 fail |= cvmx_error_add(&info);
1052 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1053 info.status_addr = CVMX_POW_ECC_ERR;
1054 info.status_mask = 1ull<<1 /* dbe */;
1055 info.enable_addr = CVMX_POW_ECC_ERR;
1056 info.enable_mask = 1ull<<3 /* dbe_ie */;
1058 info.group = CVMX_ERROR_GROUP_INTERNAL;
1059 info.group_index = 0;
1060 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1061 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1062 info.parent.status_mask = 1ull<<12 /* pow */;
1063 info.func = __cvmx_error_handle_pow_ecc_err_dbe;
1064 info.user_info = (long)
1065 "ERROR POW_ECC_ERR[DBE]: Double bit error\n";
1066 fail |= cvmx_error_add(&info);
1068 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1069 info.status_addr = CVMX_POW_ECC_ERR;
1070 info.status_mask = 1ull<<12 /* rpe */;
1071 info.enable_addr = CVMX_POW_ECC_ERR;
1072 info.enable_mask = 1ull<<13 /* rpe_ie */;
1074 info.group = CVMX_ERROR_GROUP_INTERNAL;
1075 info.group_index = 0;
1076 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1077 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1078 info.parent.status_mask = 1ull<<12 /* pow */;
1079 info.func = __cvmx_error_handle_pow_ecc_err_rpe;
1080 info.user_info = (long)
1081 "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n";
1082 fail |= cvmx_error_add(&info);
1084 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1085 info.status_addr = CVMX_POW_ECC_ERR;
1086 info.status_mask = 0x1fffull<<16 /* iop */;
1087 info.enable_addr = CVMX_POW_ECC_ERR;
1088 info.enable_mask = 0x1fffull<<32 /* iop_ie */;
1090 info.group = CVMX_ERROR_GROUP_INTERNAL;
1091 info.group_index = 0;
1092 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1093 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1094 info.parent.status_mask = 1ull<<12 /* pow */;
1095 info.func = __cvmx_error_handle_pow_ecc_err_iop;
1096 info.user_info = (long)
1097 "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n";
1098 fail |= cvmx_error_add(&info);
1100 /* CVMX_RAD_REG_ERROR */
1101 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1102 info.status_addr = CVMX_RAD_REG_ERROR;
1103 info.status_mask = 1ull<<0 /* doorbell */;
1104 info.enable_addr = CVMX_RAD_REG_INT_MASK;
1105 info.enable_mask = 1ull<<0 /* doorbell */;
1107 info.group = CVMX_ERROR_GROUP_INTERNAL;
1108 info.group_index = 0;
1109 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1110 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1111 info.parent.status_mask = 1ull<<14 /* rad */;
1112 info.func = __cvmx_error_display;
1113 info.user_info = (long)
1114 "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
1115 fail |= cvmx_error_add(&info);
1117 /* CVMX_PCSX_INTX_REG(0,0) */
1118 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1119 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1120 info.status_mask = 1ull<<2 /* an_err */;
1121 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1122 info.enable_mask = 1ull<<2 /* an_err_en */;
1124 info.group = CVMX_ERROR_GROUP_ETHERNET;
1125 info.group_index = 0;
1126 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1127 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1128 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1129 info.func = __cvmx_error_display;
1130 info.user_info = (long)
1131 "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1132 fail |= cvmx_error_add(&info);
1134 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1135 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1136 info.status_mask = 1ull<<3 /* txfifu */;
1137 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1138 info.enable_mask = 1ull<<3 /* txfifu_en */;
1140 info.group = CVMX_ERROR_GROUP_ETHERNET;
1141 info.group_index = 0;
1142 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1143 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1144 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1145 info.func = __cvmx_error_display;
1146 info.user_info = (long)
1147 "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1149 fail |= cvmx_error_add(&info);
1151 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1152 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1153 info.status_mask = 1ull<<4 /* txfifo */;
1154 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1155 info.enable_mask = 1ull<<4 /* txfifo_en */;
1157 info.group = CVMX_ERROR_GROUP_ETHERNET;
1158 info.group_index = 0;
1159 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1160 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1161 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1162 info.func = __cvmx_error_display;
1163 info.user_info = (long)
1164 "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1166 fail |= cvmx_error_add(&info);
1168 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1169 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1170 info.status_mask = 1ull<<5 /* txbad */;
1171 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1172 info.enable_mask = 1ull<<5 /* txbad_en */;
1174 info.group = CVMX_ERROR_GROUP_ETHERNET;
1175 info.group_index = 0;
1176 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1177 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1178 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1179 info.func = __cvmx_error_display;
1180 info.user_info = (long)
1181 "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1182 " state. Should never be set during normal operation\n";
1183 fail |= cvmx_error_add(&info);
1185 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1186 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1187 info.status_mask = 1ull<<7 /* rxbad */;
1188 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1189 info.enable_mask = 1ull<<7 /* rxbad_en */;
1191 info.group = CVMX_ERROR_GROUP_ETHERNET;
1192 info.group_index = 0;
1193 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1194 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1195 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1196 info.func = __cvmx_error_display;
1197 info.user_info = (long)
1198 "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1199 " state. Should never be set during normal operation\n";
1200 fail |= cvmx_error_add(&info);
1202 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1203 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1204 info.status_mask = 1ull<<8 /* rxlock */;
1205 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1206 info.enable_mask = 1ull<<8 /* rxlock_en */;
1208 info.group = CVMX_ERROR_GROUP_ETHERNET;
1209 info.group_index = 0;
1210 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1211 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1212 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1213 info.func = __cvmx_error_display;
1214 info.user_info = (long)
1215 "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1217 " Cannot fire in loopback1 mode\n";
1218 fail |= cvmx_error_add(&info);
1220 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1221 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1222 info.status_mask = 1ull<<9 /* an_bad */;
1223 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1224 info.enable_mask = 1ull<<9 /* an_bad_en */;
1226 info.group = CVMX_ERROR_GROUP_ETHERNET;
1227 info.group_index = 0;
1228 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1229 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1230 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1231 info.func = __cvmx_error_display;
1232 info.user_info = (long)
1233 "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1234 " state. Should never be set during normal operation\n";
1235 fail |= cvmx_error_add(&info);
1237 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1238 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1239 info.status_mask = 1ull<<10 /* sync_bad */;
1240 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1241 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1243 info.group = CVMX_ERROR_GROUP_ETHERNET;
1244 info.group_index = 0;
1245 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1246 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1247 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1248 info.func = __cvmx_error_display;
1249 info.user_info = (long)
1250 "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1251 " state. Should never be set during normal operation\n";
1252 fail |= cvmx_error_add(&info);
1254 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1255 info.status_addr = CVMX_PCSX_INTX_REG(0,0);
1256 info.status_mask = 1ull<<12 /* dbg_sync */;
1257 info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0);
1258 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1260 info.group = CVMX_ERROR_GROUP_ETHERNET;
1261 info.group_index = 0;
1262 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1263 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1264 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1265 info.func = __cvmx_error_display;
1266 info.user_info = (long)
1267 "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1268 fail |= cvmx_error_add(&info);
1270 /* CVMX_PCSX_INTX_REG(1,0) */
1271 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1272 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1273 info.status_mask = 1ull<<2 /* an_err */;
1274 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1275 info.enable_mask = 1ull<<2 /* an_err_en */;
1277 info.group = CVMX_ERROR_GROUP_ETHERNET;
1278 info.group_index = 1;
1279 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1280 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1281 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1282 info.func = __cvmx_error_display;
1283 info.user_info = (long)
1284 "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1285 fail |= cvmx_error_add(&info);
1287 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1288 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1289 info.status_mask = 1ull<<3 /* txfifu */;
1290 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1291 info.enable_mask = 1ull<<3 /* txfifu_en */;
1293 info.group = CVMX_ERROR_GROUP_ETHERNET;
1294 info.group_index = 1;
1295 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1296 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1297 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1298 info.func = __cvmx_error_display;
1299 info.user_info = (long)
1300 "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1302 fail |= cvmx_error_add(&info);
1304 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1305 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1306 info.status_mask = 1ull<<4 /* txfifo */;
1307 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1308 info.enable_mask = 1ull<<4 /* txfifo_en */;
1310 info.group = CVMX_ERROR_GROUP_ETHERNET;
1311 info.group_index = 1;
1312 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1313 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1314 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1315 info.func = __cvmx_error_display;
1316 info.user_info = (long)
1317 "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1319 fail |= cvmx_error_add(&info);
1321 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1322 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1323 info.status_mask = 1ull<<5 /* txbad */;
1324 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1325 info.enable_mask = 1ull<<5 /* txbad_en */;
1327 info.group = CVMX_ERROR_GROUP_ETHERNET;
1328 info.group_index = 1;
1329 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1330 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1331 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1332 info.func = __cvmx_error_display;
1333 info.user_info = (long)
1334 "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1335 " state. Should never be set during normal operation\n";
1336 fail |= cvmx_error_add(&info);
1338 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1339 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1340 info.status_mask = 1ull<<7 /* rxbad */;
1341 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1342 info.enable_mask = 1ull<<7 /* rxbad_en */;
1344 info.group = CVMX_ERROR_GROUP_ETHERNET;
1345 info.group_index = 1;
1346 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1347 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1348 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1349 info.func = __cvmx_error_display;
1350 info.user_info = (long)
1351 "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1352 " state. Should never be set during normal operation\n";
1353 fail |= cvmx_error_add(&info);
1355 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1356 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1357 info.status_mask = 1ull<<8 /* rxlock */;
1358 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1359 info.enable_mask = 1ull<<8 /* rxlock_en */;
1361 info.group = CVMX_ERROR_GROUP_ETHERNET;
1362 info.group_index = 1;
1363 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1364 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1365 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1366 info.func = __cvmx_error_display;
1367 info.user_info = (long)
1368 "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1370 " Cannot fire in loopback1 mode\n";
1371 fail |= cvmx_error_add(&info);
1373 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1374 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1375 info.status_mask = 1ull<<9 /* an_bad */;
1376 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1377 info.enable_mask = 1ull<<9 /* an_bad_en */;
1379 info.group = CVMX_ERROR_GROUP_ETHERNET;
1380 info.group_index = 1;
1381 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1382 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1383 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1384 info.func = __cvmx_error_display;
1385 info.user_info = (long)
1386 "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1387 " state. Should never be set during normal operation\n";
1388 fail |= cvmx_error_add(&info);
1390 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1391 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1392 info.status_mask = 1ull<<10 /* sync_bad */;
1393 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1394 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1396 info.group = CVMX_ERROR_GROUP_ETHERNET;
1397 info.group_index = 1;
1398 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1399 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1400 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1401 info.func = __cvmx_error_display;
1402 info.user_info = (long)
1403 "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1404 " state. Should never be set during normal operation\n";
1405 fail |= cvmx_error_add(&info);
1407 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1408 info.status_addr = CVMX_PCSX_INTX_REG(1,0);
1409 info.status_mask = 1ull<<12 /* dbg_sync */;
1410 info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0);
1411 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1413 info.group = CVMX_ERROR_GROUP_ETHERNET;
1414 info.group_index = 1;
1415 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1416 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1417 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1418 info.func = __cvmx_error_display;
1419 info.user_info = (long)
1420 "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1421 fail |= cvmx_error_add(&info);
1423 /* CVMX_PCSX_INTX_REG(2,0) */
1424 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1425 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1426 info.status_mask = 1ull<<2 /* an_err */;
1427 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1428 info.enable_mask = 1ull<<2 /* an_err_en */;
1430 info.group = CVMX_ERROR_GROUP_ETHERNET;
1431 info.group_index = 2;
1432 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1433 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1434 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1435 info.func = __cvmx_error_display;
1436 info.user_info = (long)
1437 "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1438 fail |= cvmx_error_add(&info);
1440 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1441 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1442 info.status_mask = 1ull<<3 /* txfifu */;
1443 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1444 info.enable_mask = 1ull<<3 /* txfifu_en */;
1446 info.group = CVMX_ERROR_GROUP_ETHERNET;
1447 info.group_index = 2;
1448 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1449 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1450 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1451 info.func = __cvmx_error_display;
1452 info.user_info = (long)
1453 "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1455 fail |= cvmx_error_add(&info);
1457 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1458 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1459 info.status_mask = 1ull<<4 /* txfifo */;
1460 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1461 info.enable_mask = 1ull<<4 /* txfifo_en */;
1463 info.group = CVMX_ERROR_GROUP_ETHERNET;
1464 info.group_index = 2;
1465 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1466 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1467 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1468 info.func = __cvmx_error_display;
1469 info.user_info = (long)
1470 "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1472 fail |= cvmx_error_add(&info);
1474 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1475 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1476 info.status_mask = 1ull<<5 /* txbad */;
1477 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1478 info.enable_mask = 1ull<<5 /* txbad_en */;
1480 info.group = CVMX_ERROR_GROUP_ETHERNET;
1481 info.group_index = 2;
1482 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1483 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1484 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1485 info.func = __cvmx_error_display;
1486 info.user_info = (long)
1487 "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1488 " state. Should never be set during normal operation\n";
1489 fail |= cvmx_error_add(&info);
1491 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1492 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1493 info.status_mask = 1ull<<7 /* rxbad */;
1494 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1495 info.enable_mask = 1ull<<7 /* rxbad_en */;
1497 info.group = CVMX_ERROR_GROUP_ETHERNET;
1498 info.group_index = 2;
1499 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1500 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1501 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1502 info.func = __cvmx_error_display;
1503 info.user_info = (long)
1504 "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1505 " state. Should never be set during normal operation\n";
1506 fail |= cvmx_error_add(&info);
1508 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1509 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1510 info.status_mask = 1ull<<8 /* rxlock */;
1511 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1512 info.enable_mask = 1ull<<8 /* rxlock_en */;
1514 info.group = CVMX_ERROR_GROUP_ETHERNET;
1515 info.group_index = 2;
1516 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1517 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1518 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1519 info.func = __cvmx_error_display;
1520 info.user_info = (long)
1521 "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1523 " Cannot fire in loopback1 mode\n";
1524 fail |= cvmx_error_add(&info);
1526 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1527 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1528 info.status_mask = 1ull<<9 /* an_bad */;
1529 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1530 info.enable_mask = 1ull<<9 /* an_bad_en */;
1532 info.group = CVMX_ERROR_GROUP_ETHERNET;
1533 info.group_index = 2;
1534 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1535 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1536 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1537 info.func = __cvmx_error_display;
1538 info.user_info = (long)
1539 "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1540 " state. Should never be set during normal operation\n";
1541 fail |= cvmx_error_add(&info);
1543 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1544 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1545 info.status_mask = 1ull<<10 /* sync_bad */;
1546 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1547 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1549 info.group = CVMX_ERROR_GROUP_ETHERNET;
1550 info.group_index = 2;
1551 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1552 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1553 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1554 info.func = __cvmx_error_display;
1555 info.user_info = (long)
1556 "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1557 " state. Should never be set during normal operation\n";
1558 fail |= cvmx_error_add(&info);
1560 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1561 info.status_addr = CVMX_PCSX_INTX_REG(2,0);
1562 info.status_mask = 1ull<<12 /* dbg_sync */;
1563 info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0);
1564 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1566 info.group = CVMX_ERROR_GROUP_ETHERNET;
1567 info.group_index = 2;
1568 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1569 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1570 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1571 info.func = __cvmx_error_display;
1572 info.user_info = (long)
1573 "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1574 fail |= cvmx_error_add(&info);
1576 /* CVMX_PCSX_INTX_REG(3,0) */
1577 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1578 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1579 info.status_mask = 1ull<<2 /* an_err */;
1580 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1581 info.enable_mask = 1ull<<2 /* an_err_en */;
1583 info.group = CVMX_ERROR_GROUP_ETHERNET;
1584 info.group_index = 3;
1585 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1586 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1587 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1588 info.func = __cvmx_error_display;
1589 info.user_info = (long)
1590 "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n";
1591 fail |= cvmx_error_add(&info);
1593 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1594 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1595 info.status_mask = 1ull<<3 /* txfifu */;
1596 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1597 info.enable_mask = 1ull<<3 /* txfifu_en */;
1599 info.group = CVMX_ERROR_GROUP_ETHERNET;
1600 info.group_index = 3;
1601 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1602 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1603 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1604 info.func = __cvmx_error_display;
1605 info.user_info = (long)
1606 "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n"
1608 fail |= cvmx_error_add(&info);
1610 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1611 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1612 info.status_mask = 1ull<<4 /* txfifo */;
1613 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1614 info.enable_mask = 1ull<<4 /* txfifo_en */;
1616 info.group = CVMX_ERROR_GROUP_ETHERNET;
1617 info.group_index = 3;
1618 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1619 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1620 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1621 info.func = __cvmx_error_display;
1622 info.user_info = (long)
1623 "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n"
1625 fail |= cvmx_error_add(&info);
1627 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1628 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1629 info.status_mask = 1ull<<5 /* txbad */;
1630 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1631 info.enable_mask = 1ull<<5 /* txbad_en */;
1633 info.group = CVMX_ERROR_GROUP_ETHERNET;
1634 info.group_index = 3;
1635 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1636 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1637 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1638 info.func = __cvmx_error_display;
1639 info.user_info = (long)
1640 "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n"
1641 " state. Should never be set during normal operation\n";
1642 fail |= cvmx_error_add(&info);
1644 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1645 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1646 info.status_mask = 1ull<<7 /* rxbad */;
1647 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1648 info.enable_mask = 1ull<<7 /* rxbad_en */;
1650 info.group = CVMX_ERROR_GROUP_ETHERNET;
1651 info.group_index = 3;
1652 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1653 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1654 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1655 info.func = __cvmx_error_display;
1656 info.user_info = (long)
1657 "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n"
1658 " state. Should never be set during normal operation\n";
1659 fail |= cvmx_error_add(&info);
1661 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1662 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1663 info.status_mask = 1ull<<8 /* rxlock */;
1664 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1665 info.enable_mask = 1ull<<8 /* rxlock_en */;
1667 info.group = CVMX_ERROR_GROUP_ETHERNET;
1668 info.group_index = 3;
1669 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1670 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1671 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1672 info.func = __cvmx_error_display;
1673 info.user_info = (long)
1674 "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n"
1676 " Cannot fire in loopback1 mode\n";
1677 fail |= cvmx_error_add(&info);
1679 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1680 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1681 info.status_mask = 1ull<<9 /* an_bad */;
1682 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1683 info.enable_mask = 1ull<<9 /* an_bad_en */;
1685 info.group = CVMX_ERROR_GROUP_ETHERNET;
1686 info.group_index = 3;
1687 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1688 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1689 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1690 info.func = __cvmx_error_display;
1691 info.user_info = (long)
1692 "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n"
1693 " state. Should never be set during normal operation\n";
1694 fail |= cvmx_error_add(&info);
1696 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1697 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1698 info.status_mask = 1ull<<10 /* sync_bad */;
1699 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1700 info.enable_mask = 1ull<<10 /* sync_bad_en */;
1702 info.group = CVMX_ERROR_GROUP_ETHERNET;
1703 info.group_index = 3;
1704 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1705 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1706 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1707 info.func = __cvmx_error_display;
1708 info.user_info = (long)
1709 "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n"
1710 " state. Should never be set during normal operation\n";
1711 fail |= cvmx_error_add(&info);
1713 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1714 info.status_addr = CVMX_PCSX_INTX_REG(3,0);
1715 info.status_mask = 1ull<<12 /* dbg_sync */;
1716 info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0);
1717 info.enable_mask = 1ull<<12 /* dbg_sync_en */;
1719 info.group = CVMX_ERROR_GROUP_ETHERNET;
1720 info.group_index = 3;
1721 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1722 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1723 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1724 info.func = __cvmx_error_display;
1725 info.user_info = (long)
1726 "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n";
1727 fail |= cvmx_error_add(&info);
1729 /* CVMX_PCSXX_INT_REG(0) */
1730 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1731 info.status_addr = CVMX_PCSXX_INT_REG(0);
1732 info.status_mask = 1ull<<0 /* txflt */;
1733 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1734 info.enable_mask = 1ull<<0 /* txflt_en */;
1736 info.group = CVMX_ERROR_GROUP_ETHERNET;
1737 info.group_index = 0;
1738 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1739 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1740 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1741 info.func = __cvmx_error_display;
1742 info.user_info = (long)
1743 "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n";
1744 fail |= cvmx_error_add(&info);
1746 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1747 info.status_addr = CVMX_PCSXX_INT_REG(0);
1748 info.status_mask = 1ull<<1 /* rxbad */;
1749 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1750 info.enable_mask = 1ull<<1 /* rxbad_en */;
1752 info.group = CVMX_ERROR_GROUP_ETHERNET;
1753 info.group_index = 0;
1754 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1755 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1756 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1757 info.func = __cvmx_error_display;
1758 info.user_info = (long)
1759 "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n";
1760 fail |= cvmx_error_add(&info);
1762 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1763 info.status_addr = CVMX_PCSXX_INT_REG(0);
1764 info.status_mask = 1ull<<2 /* rxsynbad */;
1765 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1766 info.enable_mask = 1ull<<2 /* rxsynbad_en */;
1768 info.group = CVMX_ERROR_GROUP_ETHERNET;
1769 info.group_index = 0;
1770 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1771 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1772 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1773 info.func = __cvmx_error_display;
1774 info.user_info = (long)
1775 "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n"
1776 " in one of the 4 xaui lanes\n";
1777 fail |= cvmx_error_add(&info);
1779 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1780 info.status_addr = CVMX_PCSXX_INT_REG(0);
1781 info.status_mask = 1ull<<4 /* synlos */;
1782 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1783 info.enable_mask = 1ull<<4 /* synlos_en */;
1785 info.group = CVMX_ERROR_GROUP_ETHERNET;
1786 info.group_index = 0;
1787 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1788 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1789 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1790 info.func = __cvmx_error_display;
1791 info.user_info = (long)
1792 "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n";
1793 fail |= cvmx_error_add(&info);
1795 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1796 info.status_addr = CVMX_PCSXX_INT_REG(0);
1797 info.status_mask = 1ull<<5 /* algnlos */;
1798 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1799 info.enable_mask = 1ull<<5 /* algnlos_en */;
1801 info.group = CVMX_ERROR_GROUP_ETHERNET;
1802 info.group_index = 0;
1803 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1804 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1805 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1806 info.func = __cvmx_error_display;
1807 info.user_info = (long)
1808 "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n";
1809 fail |= cvmx_error_add(&info);
1811 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1812 info.status_addr = CVMX_PCSXX_INT_REG(0);
1813 info.status_mask = 1ull<<6 /* dbg_sync */;
1814 info.enable_addr = CVMX_PCSXX_INT_EN_REG(0);
1815 info.enable_mask = 1ull<<6 /* dbg_sync_en */;
1817 info.group = CVMX_ERROR_GROUP_ETHERNET;
1818 info.group_index = 0;
1819 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1820 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1821 info.parent.status_mask = 1ull<<22 /* asxpcs0 */;
1822 info.func = __cvmx_error_display;
1823 info.user_info = (long)
1824 "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n";
1825 fail |= cvmx_error_add(&info);
1827 /* CVMX_PIP_INT_REG */
1828 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1829 info.status_addr = CVMX_PIP_INT_REG;
1830 info.status_mask = 1ull<<3 /* prtnxa */;
1831 info.enable_addr = CVMX_PIP_INT_EN;
1832 info.enable_mask = 1ull<<3 /* prtnxa */;
1834 info.group = CVMX_ERROR_GROUP_INTERNAL;
1835 info.group_index = 0;
1836 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1837 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1838 info.parent.status_mask = 1ull<<20 /* pip */;
1839 info.func = __cvmx_error_display;
1840 info.user_info = (long)
1841 "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n";
1842 fail |= cvmx_error_add(&info);
1844 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1845 info.status_addr = CVMX_PIP_INT_REG;
1846 info.status_mask = 1ull<<4 /* badtag */;
1847 info.enable_addr = CVMX_PIP_INT_EN;
1848 info.enable_mask = 1ull<<4 /* badtag */;
1850 info.group = CVMX_ERROR_GROUP_INTERNAL;
1851 info.group_index = 0;
1852 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1853 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1854 info.parent.status_mask = 1ull<<20 /* pip */;
1855 info.func = __cvmx_error_display;
1856 info.user_info = (long)
1857 "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n";
1858 fail |= cvmx_error_add(&info);
1860 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1861 info.status_addr = CVMX_PIP_INT_REG;
1862 info.status_mask = 1ull<<5 /* skprunt */;
1863 info.enable_addr = CVMX_PIP_INT_EN;
1864 info.enable_mask = 1ull<<5 /* skprunt */;
1866 info.group = CVMX_ERROR_GROUP_INTERNAL;
1867 info.group_index = 0;
1868 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1869 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1870 info.parent.status_mask = 1ull<<20 /* pip */;
1871 info.func = __cvmx_error_display;
1872 info.user_info = (long)
1873 "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n"
1874 " This interrupt can occur with received PARTIAL\n"
1875 " packets that are truncated to SKIP bytes or\n"
1877 fail |= cvmx_error_add(&info);
1879 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1880 info.status_addr = CVMX_PIP_INT_REG;
1881 info.status_mask = 1ull<<6 /* todoovr */;
1882 info.enable_addr = CVMX_PIP_INT_EN;
1883 info.enable_mask = 1ull<<6 /* todoovr */;
1885 info.group = CVMX_ERROR_GROUP_INTERNAL;
1886 info.group_index = 0;
1887 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1888 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1889 info.parent.status_mask = 1ull<<20 /* pip */;
1890 info.func = __cvmx_error_display;
1891 info.user_info = (long)
1892 "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n";
1893 fail |= cvmx_error_add(&info);
1895 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1896 info.status_addr = CVMX_PIP_INT_REG;
1897 info.status_mask = 1ull<<7 /* feperr */;
1898 info.enable_addr = CVMX_PIP_INT_EN;
1899 info.enable_mask = 1ull<<7 /* feperr */;
1901 info.group = CVMX_ERROR_GROUP_INTERNAL;
1902 info.group_index = 0;
1903 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1904 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1905 info.parent.status_mask = 1ull<<20 /* pip */;
1906 info.func = __cvmx_error_display;
1907 info.user_info = (long)
1908 "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n";
1909 fail |= cvmx_error_add(&info);
1911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1912 info.status_addr = CVMX_PIP_INT_REG;
1913 info.status_mask = 1ull<<8 /* beperr */;
1914 info.enable_addr = CVMX_PIP_INT_EN;
1915 info.enable_mask = 1ull<<8 /* beperr */;
1917 info.group = CVMX_ERROR_GROUP_INTERNAL;
1918 info.group_index = 0;
1919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1920 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1921 info.parent.status_mask = 1ull<<20 /* pip */;
1922 info.func = __cvmx_error_display;
1923 info.user_info = (long)
1924 "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n";
1925 fail |= cvmx_error_add(&info);
1927 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1928 info.status_addr = CVMX_PIP_INT_REG;
1929 info.status_mask = 1ull<<12 /* punyerr */;
1930 info.enable_addr = CVMX_PIP_INT_EN;
1931 info.enable_mask = 1ull<<12 /* punyerr */;
1933 info.group = CVMX_ERROR_GROUP_INTERNAL;
1934 info.group_index = 0;
1935 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1936 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1937 info.parent.status_mask = 1ull<<20 /* pip */;
1938 info.func = __cvmx_error_display;
1939 info.user_info = (long)
1940 "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n"
1941 " stripping in IPD is enable\n";
1942 fail |= cvmx_error_add(&info);
1944 /* CVMX_PKO_REG_ERROR */
1945 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1946 info.status_addr = CVMX_PKO_REG_ERROR;
1947 info.status_mask = 1ull<<0 /* parity */;
1948 info.enable_addr = CVMX_PKO_REG_INT_MASK;
1949 info.enable_mask = 1ull<<0 /* parity */;
1951 info.group = CVMX_ERROR_GROUP_INTERNAL;
1952 info.group_index = 0;
1953 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1954 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1955 info.parent.status_mask = 1ull<<10 /* pko */;
1956 info.func = __cvmx_error_display;
1957 info.user_info = (long)
1958 "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n";
1959 fail |= cvmx_error_add(&info);
1961 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1962 info.status_addr = CVMX_PKO_REG_ERROR;
1963 info.status_mask = 1ull<<1 /* doorbell */;
1964 info.enable_addr = CVMX_PKO_REG_INT_MASK;
1965 info.enable_mask = 1ull<<1 /* doorbell */;
1967 info.group = CVMX_ERROR_GROUP_INTERNAL;
1968 info.group_index = 0;
1969 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1970 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1971 info.parent.status_mask = 1ull<<10 /* pko */;
1972 info.func = __cvmx_error_display;
1973 info.user_info = (long)
1974 "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n";
1975 fail |= cvmx_error_add(&info);
1977 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1978 info.status_addr = CVMX_PKO_REG_ERROR;
1979 info.status_mask = 1ull<<2 /* currzero */;
1980 info.enable_addr = CVMX_PKO_REG_INT_MASK;
1981 info.enable_mask = 1ull<<2 /* currzero */;
1983 info.group = CVMX_ERROR_GROUP_INTERNAL;
1984 info.group_index = 0;
1985 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
1986 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
1987 info.parent.status_mask = 1ull<<10 /* pko */;
1988 info.func = __cvmx_error_display;
1989 info.user_info = (long)
1990 "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n";
1991 fail |= cvmx_error_add(&info);
1993 /* CVMX_PEMX_INT_SUM(0) */
1994 info.reg_type = CVMX_ERROR_REGISTER_IO64;
1995 info.status_addr = CVMX_PEMX_INT_SUM(0);
1996 info.status_mask = 1ull<<1 /* se */;
1997 info.enable_addr = CVMX_PEMX_INT_ENB(0);
1998 info.enable_mask = 1ull<<1 /* se */;
2000 info.group = CVMX_ERROR_GROUP_PCI;
2001 info.group_index = 0;
2002 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2003 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2004 info.parent.status_mask = 1ull<<25 /* pem0 */;
2005 info.func = __cvmx_error_display;
2006 info.user_info = (long)
2007 "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n"
2008 " (cfg_sys_err_rc)\n";
2009 fail |= cvmx_error_add(&info);
2011 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2012 info.status_addr = CVMX_PEMX_INT_SUM(0);
2013 info.status_mask = 1ull<<4 /* up_b1 */;
2014 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2015 info.enable_mask = 1ull<<4 /* up_b1 */;
2017 info.group = CVMX_ERROR_GROUP_PCI;
2018 info.group_index = 0;
2019 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2020 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2021 info.parent.status_mask = 1ull<<25 /* pem0 */;
2022 info.func = __cvmx_error_display;
2023 info.user_info = (long)
2024 "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2026 fail |= cvmx_error_add(&info);
2028 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2029 info.status_addr = CVMX_PEMX_INT_SUM(0);
2030 info.status_mask = 1ull<<5 /* up_b2 */;
2031 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2032 info.enable_mask = 1ull<<5 /* up_b2 */;
2034 info.group = CVMX_ERROR_GROUP_PCI;
2035 info.group_index = 0;
2036 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2037 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2038 info.parent.status_mask = 1ull<<25 /* pem0 */;
2039 info.func = __cvmx_error_display;
2040 info.user_info = (long)
2041 "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2042 fail |= cvmx_error_add(&info);
2044 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2045 info.status_addr = CVMX_PEMX_INT_SUM(0);
2046 info.status_mask = 1ull<<6 /* up_bx */;
2047 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2048 info.enable_mask = 1ull<<6 /* up_bx */;
2050 info.group = CVMX_ERROR_GROUP_PCI;
2051 info.group_index = 0;
2052 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2053 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2054 info.parent.status_mask = 1ull<<25 /* pem0 */;
2055 info.func = __cvmx_error_display;
2056 info.user_info = (long)
2057 "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2058 fail |= cvmx_error_add(&info);
2060 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2061 info.status_addr = CVMX_PEMX_INT_SUM(0);
2062 info.status_mask = 1ull<<7 /* un_b1 */;
2063 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2064 info.enable_mask = 1ull<<7 /* un_b1 */;
2066 info.group = CVMX_ERROR_GROUP_PCI;
2067 info.group_index = 0;
2068 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2069 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2070 info.parent.status_mask = 1ull<<25 /* pem0 */;
2071 info.func = __cvmx_error_display;
2072 info.user_info = (long)
2073 "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2075 fail |= cvmx_error_add(&info);
2077 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2078 info.status_addr = CVMX_PEMX_INT_SUM(0);
2079 info.status_mask = 1ull<<8 /* un_b2 */;
2080 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2081 info.enable_mask = 1ull<<8 /* un_b2 */;
2083 info.group = CVMX_ERROR_GROUP_PCI;
2084 info.group_index = 0;
2085 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2086 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2087 info.parent.status_mask = 1ull<<25 /* pem0 */;
2088 info.func = __cvmx_error_display;
2089 info.user_info = (long)
2090 "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2091 fail |= cvmx_error_add(&info);
2093 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2094 info.status_addr = CVMX_PEMX_INT_SUM(0);
2095 info.status_mask = 1ull<<9 /* un_bx */;
2096 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2097 info.enable_mask = 1ull<<9 /* un_bx */;
2099 info.group = CVMX_ERROR_GROUP_PCI;
2100 info.group_index = 0;
2101 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2102 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2103 info.parent.status_mask = 1ull<<25 /* pem0 */;
2104 info.func = __cvmx_error_display;
2105 info.user_info = (long)
2106 "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2107 fail |= cvmx_error_add(&info);
2109 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2110 info.status_addr = CVMX_PEMX_INT_SUM(0);
2111 info.status_mask = 1ull<<11 /* rdlk */;
2112 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2113 info.enable_mask = 1ull<<11 /* rdlk */;
2115 info.group = CVMX_ERROR_GROUP_PCI;
2116 info.group_index = 0;
2117 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2118 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2119 info.parent.status_mask = 1ull<<25 /* pem0 */;
2120 info.func = __cvmx_error_display;
2121 info.user_info = (long)
2122 "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n";
2123 fail |= cvmx_error_add(&info);
2125 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2126 info.status_addr = CVMX_PEMX_INT_SUM(0);
2127 info.status_mask = 1ull<<12 /* crs_er */;
2128 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2129 info.enable_mask = 1ull<<12 /* crs_er */;
2131 info.group = CVMX_ERROR_GROUP_PCI;
2132 info.group_index = 0;
2133 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2134 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2135 info.parent.status_mask = 1ull<<25 /* pem0 */;
2136 info.func = __cvmx_error_display;
2137 info.user_info = (long)
2138 "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2139 fail |= cvmx_error_add(&info);
2141 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2142 info.status_addr = CVMX_PEMX_INT_SUM(0);
2143 info.status_mask = 1ull<<13 /* crs_dr */;
2144 info.enable_addr = CVMX_PEMX_INT_ENB(0);
2145 info.enable_mask = 1ull<<13 /* crs_dr */;
2147 info.group = CVMX_ERROR_GROUP_PCI;
2148 info.group_index = 0;
2149 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2150 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2151 info.parent.status_mask = 1ull<<25 /* pem0 */;
2152 info.func = __cvmx_error_display;
2153 info.user_info = (long)
2154 "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2155 fail |= cvmx_error_add(&info);
2157 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2158 info.status_addr = CVMX_PEMX_INT_SUM(0);
2159 info.status_mask = 0;
2160 info.enable_addr = 0;
2161 info.enable_mask = 0;
2163 info.group = CVMX_ERROR_GROUP_INTERNAL;
2164 info.group_index = 0;
2165 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2166 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2167 info.parent.status_mask = 1ull<<25 /* pem0 */;
2168 info.func = __cvmx_error_decode;
2170 fail |= cvmx_error_add(&info);
2172 /* CVMX_PEMX_DBG_INFO(0) */
2173 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2174 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2175 info.status_mask = 1ull<<0 /* spoison */;
2176 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2177 info.enable_mask = 1ull<<0 /* spoison */;
2179 info.group = CVMX_ERROR_GROUP_PCI;
2180 info.group_index = 0;
2181 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2182 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2183 info.parent.status_mask = 1ull<<10 /* exc */;
2184 info.func = __cvmx_error_display;
2185 info.user_info = (long)
2186 "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n"
2187 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2188 fail |= cvmx_error_add(&info);
2190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2191 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2192 info.status_mask = 1ull<<2 /* rtlplle */;
2193 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2194 info.enable_mask = 1ull<<2 /* rtlplle */;
2196 info.group = CVMX_ERROR_GROUP_PCI;
2197 info.group_index = 0;
2198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2199 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2200 info.parent.status_mask = 1ull<<10 /* exc */;
2201 info.func = __cvmx_error_display;
2202 info.user_info = (long)
2203 "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n"
2204 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2205 fail |= cvmx_error_add(&info);
2207 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2208 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2209 info.status_mask = 1ull<<3 /* recrce */;
2210 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2211 info.enable_mask = 1ull<<3 /* recrce */;
2213 info.group = CVMX_ERROR_GROUP_PCI;
2214 info.group_index = 0;
2215 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2216 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2217 info.parent.status_mask = 1ull<<10 /* exc */;
2218 info.func = __cvmx_error_display;
2219 info.user_info = (long)
2220 "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n"
2221 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
2222 fail |= cvmx_error_add(&info);
2224 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2225 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2226 info.status_mask = 1ull<<4 /* rpoison */;
2227 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2228 info.enable_mask = 1ull<<4 /* rpoison */;
2230 info.group = CVMX_ERROR_GROUP_PCI;
2231 info.group_index = 0;
2232 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2233 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2234 info.parent.status_mask = 1ull<<10 /* exc */;
2235 info.func = __cvmx_error_display;
2236 info.user_info = (long)
2237 "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n"
2238 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
2239 fail |= cvmx_error_add(&info);
2241 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2242 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2243 info.status_mask = 1ull<<5 /* rcemrc */;
2244 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2245 info.enable_mask = 1ull<<5 /* rcemrc */;
2247 info.group = CVMX_ERROR_GROUP_PCI;
2248 info.group_index = 0;
2249 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2250 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2251 info.parent.status_mask = 1ull<<10 /* exc */;
2252 info.func = __cvmx_error_display;
2253 info.user_info = (long)
2254 "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2255 " pedc_radm_correctable_err\n";
2256 fail |= cvmx_error_add(&info);
2258 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2259 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2260 info.status_mask = 1ull<<6 /* rnfemrc */;
2261 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2262 info.enable_mask = 1ull<<6 /* rnfemrc */;
2264 info.group = CVMX_ERROR_GROUP_PCI;
2265 info.group_index = 0;
2266 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2267 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2268 info.parent.status_mask = 1ull<<10 /* exc */;
2269 info.func = __cvmx_error_display;
2270 info.user_info = (long)
2271 "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
2272 " pedc_radm_nonfatal_err\n";
2273 fail |= cvmx_error_add(&info);
2275 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2276 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2277 info.status_mask = 1ull<<7 /* rfemrc */;
2278 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2279 info.enable_mask = 1ull<<7 /* rfemrc */;
2281 info.group = CVMX_ERROR_GROUP_PCI;
2282 info.group_index = 0;
2283 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2284 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2285 info.parent.status_mask = 1ull<<10 /* exc */;
2286 info.func = __cvmx_error_display;
2287 info.user_info = (long)
2288 "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
2289 " pedc_radm_fatal_err\n"
2290 " Bit set when a message with ERR_FATAL is set.\n";
2291 fail |= cvmx_error_add(&info);
2293 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2294 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2295 info.status_mask = 1ull<<8 /* rpmerc */;
2296 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2297 info.enable_mask = 1ull<<8 /* rpmerc */;
2299 info.group = CVMX_ERROR_GROUP_PCI;
2300 info.group_index = 0;
2301 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2302 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2303 info.parent.status_mask = 1ull<<10 /* exc */;
2304 info.func = __cvmx_error_display;
2305 info.user_info = (long)
2306 "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n"
2307 " pedc_radm_pm_pme\n";
2308 fail |= cvmx_error_add(&info);
2310 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2311 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2312 info.status_mask = 1ull<<9 /* rptamrc */;
2313 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2314 info.enable_mask = 1ull<<9 /* rptamrc */;
2316 info.group = CVMX_ERROR_GROUP_PCI;
2317 info.group_index = 0;
2318 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2319 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2320 info.parent.status_mask = 1ull<<10 /* exc */;
2321 info.func = __cvmx_error_display;
2322 info.user_info = (long)
2323 "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
2325 " pedc_radm_pm_to_ack\n";
2326 fail |= cvmx_error_add(&info);
2328 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2329 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2330 info.status_mask = 1ull<<10 /* rumep */;
2331 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2332 info.enable_mask = 1ull<<10 /* rumep */;
2334 info.group = CVMX_ERROR_GROUP_PCI;
2335 info.group_index = 0;
2336 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2337 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2338 info.parent.status_mask = 1ull<<10 /* exc */;
2339 info.func = __cvmx_error_display;
2340 info.user_info = (long)
2341 "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
2342 " pedc_radm_msg_unlock\n";
2343 fail |= cvmx_error_add(&info);
2345 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2346 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2347 info.status_mask = 1ull<<11 /* rvdm */;
2348 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2349 info.enable_mask = 1ull<<11 /* rvdm */;
2351 info.group = CVMX_ERROR_GROUP_PCI;
2352 info.group_index = 0;
2353 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2354 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2355 info.parent.status_mask = 1ull<<10 /* exc */;
2356 info.func = __cvmx_error_display;
2357 info.user_info = (long)
2358 "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n"
2359 " pedc_radm_vendor_msg\n";
2360 fail |= cvmx_error_add(&info);
2362 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2363 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2364 info.status_mask = 1ull<<12 /* acto */;
2365 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2366 info.enable_mask = 1ull<<12 /* acto */;
2368 info.group = CVMX_ERROR_GROUP_PCI;
2369 info.group_index = 0;
2370 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2371 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2372 info.parent.status_mask = 1ull<<10 /* exc */;
2373 info.func = __cvmx_error_display;
2374 info.user_info = (long)
2375 "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n"
2376 " pedc_radm_cpl_timeout\n";
2377 fail |= cvmx_error_add(&info);
2379 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2380 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2381 info.status_mask = 1ull<<13 /* rte */;
2382 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2383 info.enable_mask = 1ull<<13 /* rte */;
2385 info.group = CVMX_ERROR_GROUP_PCI;
2386 info.group_index = 0;
2387 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2388 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2389 info.parent.status_mask = 1ull<<10 /* exc */;
2390 info.func = __cvmx_error_display;
2391 info.user_info = (long)
2392 "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n"
2393 " xdlh_replay_timeout_err\n"
2394 " This bit is set when the REPLAY_TIMER expires in\n"
2395 " the PCIE core. The probability of this bit being\n"
2396 " set will increase with the traffic load.\n";
2397 fail |= cvmx_error_add(&info);
2399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2400 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2401 info.status_mask = 1ull<<14 /* mre */;
2402 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2403 info.enable_mask = 1ull<<14 /* mre */;
2405 info.group = CVMX_ERROR_GROUP_PCI;
2406 info.group_index = 0;
2407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2408 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2409 info.parent.status_mask = 1ull<<10 /* exc */;
2410 info.func = __cvmx_error_display;
2411 info.user_info = (long)
2412 "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n"
2413 " xdlh_replay_num_rlover_err\n";
2414 fail |= cvmx_error_add(&info);
2416 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2417 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2418 info.status_mask = 1ull<<15 /* rdwdle */;
2419 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2420 info.enable_mask = 1ull<<15 /* rdwdle */;
2422 info.group = CVMX_ERROR_GROUP_PCI;
2423 info.group_index = 0;
2424 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2425 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2426 info.parent.status_mask = 1ull<<10 /* exc */;
2427 info.func = __cvmx_error_display;
2428 info.user_info = (long)
2429 "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
2430 " rdlh_bad_dllp_err\n";
2431 fail |= cvmx_error_add(&info);
2433 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2434 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2435 info.status_mask = 1ull<<16 /* rtwdle */;
2436 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2437 info.enable_mask = 1ull<<16 /* rtwdle */;
2439 info.group = CVMX_ERROR_GROUP_PCI;
2440 info.group_index = 0;
2441 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2442 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2443 info.parent.status_mask = 1ull<<10 /* exc */;
2444 info.func = __cvmx_error_display;
2445 info.user_info = (long)
2446 "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n"
2447 " rdlh_bad_tlp_err\n";
2448 fail |= cvmx_error_add(&info);
2450 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2451 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2452 info.status_mask = 1ull<<17 /* dpeoosd */;
2453 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2454 info.enable_mask = 1ull<<17 /* dpeoosd */;
2456 info.group = CVMX_ERROR_GROUP_PCI;
2457 info.group_index = 0;
2458 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2459 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2460 info.parent.status_mask = 1ull<<10 /* exc */;
2461 info.func = __cvmx_error_display;
2462 info.user_info = (long)
2463 "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
2465 fail |= cvmx_error_add(&info);
2467 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2468 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2469 info.status_mask = 1ull<<18 /* fcpvwt */;
2470 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2471 info.enable_mask = 1ull<<18 /* fcpvwt */;
2473 info.group = CVMX_ERROR_GROUP_PCI;
2474 info.group_index = 0;
2475 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2476 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2477 info.parent.status_mask = 1ull<<10 /* exc */;
2478 info.func = __cvmx_error_display;
2479 info.user_info = (long)
2480 "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
2481 " rtlh_fc_prot_err\n";
2482 fail |= cvmx_error_add(&info);
2484 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2485 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2486 info.status_mask = 1ull<<19 /* rpe */;
2487 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2488 info.enable_mask = 1ull<<19 /* rpe */;
2490 info.group = CVMX_ERROR_GROUP_PCI;
2491 info.group_index = 0;
2492 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2493 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2494 info.parent.status_mask = 1ull<<10 /* exc */;
2495 info.func = __cvmx_error_display;
2496 info.user_info = (long)
2497 "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n"
2498 " (RxStatus = 3b100) or disparity error\n"
2499 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
2502 fail |= cvmx_error_add(&info);
2504 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2505 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2506 info.status_mask = 1ull<<20 /* fcuv */;
2507 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2508 info.enable_mask = 1ull<<20 /* fcuv */;
2510 info.group = CVMX_ERROR_GROUP_PCI;
2511 info.group_index = 0;
2512 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2513 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2514 info.parent.status_mask = 1ull<<10 /* exc */;
2515 info.func = __cvmx_error_display;
2516 info.user_info = (long)
2517 "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n"
2518 " int_xadm_fc_prot_err\n";
2519 fail |= cvmx_error_add(&info);
2521 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2522 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2523 info.status_mask = 1ull<<21 /* rqo */;
2524 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2525 info.enable_mask = 1ull<<21 /* rqo */;
2527 info.group = CVMX_ERROR_GROUP_PCI;
2528 info.group_index = 0;
2529 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2530 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2531 info.parent.status_mask = 1ull<<10 /* exc */;
2532 info.func = __cvmx_error_display;
2533 info.user_info = (long)
2534 "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n"
2535 " flow control advertisements are ignored\n"
2536 " radm_qoverflow\n";
2537 fail |= cvmx_error_add(&info);
2539 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2540 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2541 info.status_mask = 1ull<<22 /* rauc */;
2542 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2543 info.enable_mask = 1ull<<22 /* rauc */;
2545 info.group = CVMX_ERROR_GROUP_PCI;
2546 info.group_index = 0;
2547 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2548 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2549 info.parent.status_mask = 1ull<<10 /* exc */;
2550 info.func = __cvmx_error_display;
2551 info.user_info = (long)
2552 "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n"
2553 " radm_unexp_cpl_err\n";
2554 fail |= cvmx_error_add(&info);
2556 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2557 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2558 info.status_mask = 1ull<<23 /* racur */;
2559 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2560 info.enable_mask = 1ull<<23 /* racur */;
2562 info.group = CVMX_ERROR_GROUP_PCI;
2563 info.group_index = 0;
2564 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2565 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2566 info.parent.status_mask = 1ull<<10 /* exc */;
2567 info.func = __cvmx_error_display;
2568 info.user_info = (long)
2569 "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n"
2570 " radm_rcvd_cpl_ur\n";
2571 fail |= cvmx_error_add(&info);
2573 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2574 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2575 info.status_mask = 1ull<<24 /* racca */;
2576 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2577 info.enable_mask = 1ull<<24 /* racca */;
2579 info.group = CVMX_ERROR_GROUP_PCI;
2580 info.group_index = 0;
2581 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2582 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2583 info.parent.status_mask = 1ull<<10 /* exc */;
2584 info.func = __cvmx_error_display;
2585 info.user_info = (long)
2586 "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n"
2587 " radm_rcvd_cpl_ca\n";
2588 fail |= cvmx_error_add(&info);
2590 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2591 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2592 info.status_mask = 1ull<<25 /* caar */;
2593 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2594 info.enable_mask = 1ull<<25 /* caar */;
2596 info.group = CVMX_ERROR_GROUP_PCI;
2597 info.group_index = 0;
2598 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2599 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2600 info.parent.status_mask = 1ull<<10 /* exc */;
2601 info.func = __cvmx_error_display;
2602 info.user_info = (long)
2603 "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n"
2604 " radm_rcvd_ca_req\n"
2605 " This bit will never be set because Octeon does\n"
2606 " not generate Completer Aborts.\n";
2607 fail |= cvmx_error_add(&info);
2609 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2610 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2611 info.status_mask = 1ull<<26 /* rarwdns */;
2612 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2613 info.enable_mask = 1ull<<26 /* rarwdns */;
2615 info.group = CVMX_ERROR_GROUP_PCI;
2616 info.group_index = 0;
2617 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2618 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2619 info.parent.status_mask = 1ull<<10 /* exc */;
2620 info.func = __cvmx_error_display;
2621 info.user_info = (long)
2622 "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n"
2623 " radm_rcvd_ur_req\n";
2624 fail |= cvmx_error_add(&info);
2626 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2627 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2628 info.status_mask = 1ull<<27 /* ramtlp */;
2629 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2630 info.enable_mask = 1ull<<27 /* ramtlp */;
2632 info.group = CVMX_ERROR_GROUP_PCI;
2633 info.group_index = 0;
2634 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2635 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2636 info.parent.status_mask = 1ull<<10 /* exc */;
2637 info.func = __cvmx_error_display;
2638 info.user_info = (long)
2639 "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n"
2640 " radm_mlf_tlp_err\n";
2641 fail |= cvmx_error_add(&info);
2643 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2644 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2645 info.status_mask = 1ull<<28 /* racpp */;
2646 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2647 info.enable_mask = 1ull<<28 /* racpp */;
2649 info.group = CVMX_ERROR_GROUP_PCI;
2650 info.group_index = 0;
2651 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2652 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2653 info.parent.status_mask = 1ull<<10 /* exc */;
2654 info.func = __cvmx_error_display;
2655 info.user_info = (long)
2656 "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n"
2657 " radm_rcvd_cpl_poisoned\n";
2658 fail |= cvmx_error_add(&info);
2660 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2661 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2662 info.status_mask = 1ull<<29 /* rawwpp */;
2663 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2664 info.enable_mask = 1ull<<29 /* rawwpp */;
2666 info.group = CVMX_ERROR_GROUP_PCI;
2667 info.group_index = 0;
2668 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2669 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2670 info.parent.status_mask = 1ull<<10 /* exc */;
2671 info.func = __cvmx_error_display;
2672 info.user_info = (long)
2673 "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n"
2674 " radm_rcvd_wreq_poisoned\n";
2675 fail |= cvmx_error_add(&info);
2677 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2678 info.status_addr = CVMX_PEMX_DBG_INFO(0);
2679 info.status_mask = 1ull<<30 /* ecrc_e */;
2680 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0);
2681 info.enable_mask = 1ull<<30 /* ecrc_e */;
2683 info.group = CVMX_ERROR_GROUP_PCI;
2684 info.group_index = 0;
2685 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2686 info.parent.status_addr = CVMX_PEMX_INT_SUM(0);
2687 info.parent.status_mask = 1ull<<10 /* exc */;
2688 info.func = __cvmx_error_display;
2689 info.user_info = (long)
2690 "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n"
2692 fail |= cvmx_error_add(&info);
2694 /* CVMX_PEMX_INT_SUM(1) */
2695 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2696 info.status_addr = CVMX_PEMX_INT_SUM(1);
2697 info.status_mask = 1ull<<1 /* se */;
2698 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2699 info.enable_mask = 1ull<<1 /* se */;
2701 info.group = CVMX_ERROR_GROUP_PCI;
2702 info.group_index = 1;
2703 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2704 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2705 info.parent.status_mask = 1ull<<26 /* pem1 */;
2706 info.func = __cvmx_error_display;
2707 info.user_info = (long)
2708 "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n"
2709 " (cfg_sys_err_rc)\n";
2710 fail |= cvmx_error_add(&info);
2712 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2713 info.status_addr = CVMX_PEMX_INT_SUM(1);
2714 info.status_mask = 1ull<<4 /* up_b1 */;
2715 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2716 info.enable_mask = 1ull<<4 /* up_b1 */;
2718 info.group = CVMX_ERROR_GROUP_PCI;
2719 info.group_index = 1;
2720 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2721 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2722 info.parent.status_mask = 1ull<<26 /* pem1 */;
2723 info.func = __cvmx_error_display;
2724 info.user_info = (long)
2725 "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n"
2727 fail |= cvmx_error_add(&info);
2729 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2730 info.status_addr = CVMX_PEMX_INT_SUM(1);
2731 info.status_mask = 1ull<<5 /* up_b2 */;
2732 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2733 info.enable_mask = 1ull<<5 /* up_b2 */;
2735 info.group = CVMX_ERROR_GROUP_PCI;
2736 info.group_index = 1;
2737 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2738 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2739 info.parent.status_mask = 1ull<<26 /* pem1 */;
2740 info.func = __cvmx_error_display;
2741 info.user_info = (long)
2742 "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n";
2743 fail |= cvmx_error_add(&info);
2745 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2746 info.status_addr = CVMX_PEMX_INT_SUM(1);
2747 info.status_mask = 1ull<<6 /* up_bx */;
2748 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2749 info.enable_mask = 1ull<<6 /* up_bx */;
2751 info.group = CVMX_ERROR_GROUP_PCI;
2752 info.group_index = 1;
2753 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2754 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2755 info.parent.status_mask = 1ull<<26 /* pem1 */;
2756 info.func = __cvmx_error_display;
2757 info.user_info = (long)
2758 "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n";
2759 fail |= cvmx_error_add(&info);
2761 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2762 info.status_addr = CVMX_PEMX_INT_SUM(1);
2763 info.status_mask = 1ull<<7 /* un_b1 */;
2764 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2765 info.enable_mask = 1ull<<7 /* un_b1 */;
2767 info.group = CVMX_ERROR_GROUP_PCI;
2768 info.group_index = 1;
2769 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2770 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2771 info.parent.status_mask = 1ull<<26 /* pem1 */;
2772 info.func = __cvmx_error_display;
2773 info.user_info = (long)
2774 "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n"
2776 fail |= cvmx_error_add(&info);
2778 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2779 info.status_addr = CVMX_PEMX_INT_SUM(1);
2780 info.status_mask = 1ull<<8 /* un_b2 */;
2781 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2782 info.enable_mask = 1ull<<8 /* un_b2 */;
2784 info.group = CVMX_ERROR_GROUP_PCI;
2785 info.group_index = 1;
2786 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2787 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2788 info.parent.status_mask = 1ull<<26 /* pem1 */;
2789 info.func = __cvmx_error_display;
2790 info.user_info = (long)
2791 "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n";
2792 fail |= cvmx_error_add(&info);
2794 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2795 info.status_addr = CVMX_PEMX_INT_SUM(1);
2796 info.status_mask = 1ull<<9 /* un_bx */;
2797 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2798 info.enable_mask = 1ull<<9 /* un_bx */;
2800 info.group = CVMX_ERROR_GROUP_PCI;
2801 info.group_index = 1;
2802 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2803 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2804 info.parent.status_mask = 1ull<<26 /* pem1 */;
2805 info.func = __cvmx_error_display;
2806 info.user_info = (long)
2807 "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n";
2808 fail |= cvmx_error_add(&info);
2810 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2811 info.status_addr = CVMX_PEMX_INT_SUM(1);
2812 info.status_mask = 1ull<<11 /* rdlk */;
2813 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2814 info.enable_mask = 1ull<<11 /* rdlk */;
2816 info.group = CVMX_ERROR_GROUP_PCI;
2817 info.group_index = 1;
2818 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2819 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2820 info.parent.status_mask = 1ull<<26 /* pem1 */;
2821 info.func = __cvmx_error_display;
2822 info.user_info = (long)
2823 "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n";
2824 fail |= cvmx_error_add(&info);
2826 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2827 info.status_addr = CVMX_PEMX_INT_SUM(1);
2828 info.status_mask = 1ull<<12 /* crs_er */;
2829 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2830 info.enable_mask = 1ull<<12 /* crs_er */;
2832 info.group = CVMX_ERROR_GROUP_PCI;
2833 info.group_index = 1;
2834 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2835 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2836 info.parent.status_mask = 1ull<<26 /* pem1 */;
2837 info.func = __cvmx_error_display;
2838 info.user_info = (long)
2839 "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n";
2840 fail |= cvmx_error_add(&info);
2842 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2843 info.status_addr = CVMX_PEMX_INT_SUM(1);
2844 info.status_mask = 1ull<<13 /* crs_dr */;
2845 info.enable_addr = CVMX_PEMX_INT_ENB(1);
2846 info.enable_mask = 1ull<<13 /* crs_dr */;
2848 info.group = CVMX_ERROR_GROUP_PCI;
2849 info.group_index = 1;
2850 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2851 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2852 info.parent.status_mask = 1ull<<26 /* pem1 */;
2853 info.func = __cvmx_error_display;
2854 info.user_info = (long)
2855 "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n";
2856 fail |= cvmx_error_add(&info);
2858 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2859 info.status_addr = CVMX_PEMX_INT_SUM(1);
2860 info.status_mask = 0;
2861 info.enable_addr = 0;
2862 info.enable_mask = 0;
2864 info.group = CVMX_ERROR_GROUP_INTERNAL;
2865 info.group_index = 0;
2866 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2867 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
2868 info.parent.status_mask = 1ull<<26 /* pem1 */;
2869 info.func = __cvmx_error_decode;
2871 fail |= cvmx_error_add(&info);
2873 /* CVMX_PEMX_DBG_INFO(1) */
2874 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2875 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2876 info.status_mask = 1ull<<0 /* spoison */;
2877 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2878 info.enable_mask = 1ull<<0 /* spoison */;
2880 info.group = CVMX_ERROR_GROUP_PCI;
2881 info.group_index = 1;
2882 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2883 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2884 info.parent.status_mask = 1ull<<10 /* exc */;
2885 info.func = __cvmx_error_display;
2886 info.user_info = (long)
2887 "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n"
2888 " peai__client0_tlp_ep & peai__client0_tlp_hv\n";
2889 fail |= cvmx_error_add(&info);
2891 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2892 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2893 info.status_mask = 1ull<<2 /* rtlplle */;
2894 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2895 info.enable_mask = 1ull<<2 /* rtlplle */;
2897 info.group = CVMX_ERROR_GROUP_PCI;
2898 info.group_index = 1;
2899 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2900 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2901 info.parent.status_mask = 1ull<<10 /* exc */;
2902 info.func = __cvmx_error_display;
2903 info.user_info = (long)
2904 "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n"
2905 " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n";
2906 fail |= cvmx_error_add(&info);
2908 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2909 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2910 info.status_mask = 1ull<<3 /* recrce */;
2911 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2912 info.enable_mask = 1ull<<3 /* recrce */;
2914 info.group = CVMX_ERROR_GROUP_PCI;
2915 info.group_index = 1;
2916 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2917 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2918 info.parent.status_mask = 1ull<<10 /* exc */;
2919 info.func = __cvmx_error_display;
2920 info.user_info = (long)
2921 "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n"
2922 " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n";
2923 fail |= cvmx_error_add(&info);
2925 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2926 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2927 info.status_mask = 1ull<<4 /* rpoison */;
2928 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2929 info.enable_mask = 1ull<<4 /* rpoison */;
2931 info.group = CVMX_ERROR_GROUP_PCI;
2932 info.group_index = 1;
2933 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2934 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2935 info.parent.status_mask = 1ull<<10 /* exc */;
2936 info.func = __cvmx_error_display;
2937 info.user_info = (long)
2938 "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n"
2939 " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n";
2940 fail |= cvmx_error_add(&info);
2942 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2943 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2944 info.status_mask = 1ull<<5 /* rcemrc */;
2945 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2946 info.enable_mask = 1ull<<5 /* rcemrc */;
2948 info.group = CVMX_ERROR_GROUP_PCI;
2949 info.group_index = 1;
2950 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2951 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2952 info.parent.status_mask = 1ull<<10 /* exc */;
2953 info.func = __cvmx_error_display;
2954 info.user_info = (long)
2955 "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n"
2956 " pedc_radm_correctable_err\n";
2957 fail |= cvmx_error_add(&info);
2959 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2960 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2961 info.status_mask = 1ull<<6 /* rnfemrc */;
2962 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2963 info.enable_mask = 1ull<<6 /* rnfemrc */;
2965 info.group = CVMX_ERROR_GROUP_PCI;
2966 info.group_index = 1;
2967 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2968 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2969 info.parent.status_mask = 1ull<<10 /* exc */;
2970 info.func = __cvmx_error_display;
2971 info.user_info = (long)
2972 "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n"
2973 " pedc_radm_nonfatal_err\n";
2974 fail |= cvmx_error_add(&info);
2976 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2977 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2978 info.status_mask = 1ull<<7 /* rfemrc */;
2979 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2980 info.enable_mask = 1ull<<7 /* rfemrc */;
2982 info.group = CVMX_ERROR_GROUP_PCI;
2983 info.group_index = 1;
2984 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
2985 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
2986 info.parent.status_mask = 1ull<<10 /* exc */;
2987 info.func = __cvmx_error_display;
2988 info.user_info = (long)
2989 "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n"
2990 " pedc_radm_fatal_err\n"
2991 " Bit set when a message with ERR_FATAL is set.\n";
2992 fail |= cvmx_error_add(&info);
2994 info.reg_type = CVMX_ERROR_REGISTER_IO64;
2995 info.status_addr = CVMX_PEMX_DBG_INFO(1);
2996 info.status_mask = 1ull<<8 /* rpmerc */;
2997 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
2998 info.enable_mask = 1ull<<8 /* rpmerc */;
3000 info.group = CVMX_ERROR_GROUP_PCI;
3001 info.group_index = 1;
3002 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3003 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3004 info.parent.status_mask = 1ull<<10 /* exc */;
3005 info.func = __cvmx_error_display;
3006 info.user_info = (long)
3007 "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n"
3008 " pedc_radm_pm_pme\n";
3009 fail |= cvmx_error_add(&info);
3011 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3012 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3013 info.status_mask = 1ull<<9 /* rptamrc */;
3014 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3015 info.enable_mask = 1ull<<9 /* rptamrc */;
3017 info.group = CVMX_ERROR_GROUP_PCI;
3018 info.group_index = 1;
3019 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3020 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3021 info.parent.status_mask = 1ull<<10 /* exc */;
3022 info.func = __cvmx_error_display;
3023 info.user_info = (long)
3024 "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n"
3026 " pedc_radm_pm_to_ack\n";
3027 fail |= cvmx_error_add(&info);
3029 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3030 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3031 info.status_mask = 1ull<<10 /* rumep */;
3032 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3033 info.enable_mask = 1ull<<10 /* rumep */;
3035 info.group = CVMX_ERROR_GROUP_PCI;
3036 info.group_index = 1;
3037 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3038 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3039 info.parent.status_mask = 1ull<<10 /* exc */;
3040 info.func = __cvmx_error_display;
3041 info.user_info = (long)
3042 "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n"
3043 " pedc_radm_msg_unlock\n";
3044 fail |= cvmx_error_add(&info);
3046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3047 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3048 info.status_mask = 1ull<<11 /* rvdm */;
3049 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3050 info.enable_mask = 1ull<<11 /* rvdm */;
3052 info.group = CVMX_ERROR_GROUP_PCI;
3053 info.group_index = 1;
3054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3055 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3056 info.parent.status_mask = 1ull<<10 /* exc */;
3057 info.func = __cvmx_error_display;
3058 info.user_info = (long)
3059 "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n"
3060 " pedc_radm_vendor_msg\n";
3061 fail |= cvmx_error_add(&info);
3063 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3064 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3065 info.status_mask = 1ull<<12 /* acto */;
3066 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3067 info.enable_mask = 1ull<<12 /* acto */;
3069 info.group = CVMX_ERROR_GROUP_PCI;
3070 info.group_index = 1;
3071 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3072 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3073 info.parent.status_mask = 1ull<<10 /* exc */;
3074 info.func = __cvmx_error_display;
3075 info.user_info = (long)
3076 "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n"
3077 " pedc_radm_cpl_timeout\n";
3078 fail |= cvmx_error_add(&info);
3080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3081 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3082 info.status_mask = 1ull<<13 /* rte */;
3083 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3084 info.enable_mask = 1ull<<13 /* rte */;
3086 info.group = CVMX_ERROR_GROUP_PCI;
3087 info.group_index = 1;
3088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3089 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3090 info.parent.status_mask = 1ull<<10 /* exc */;
3091 info.func = __cvmx_error_display;
3092 info.user_info = (long)
3093 "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n"
3094 " xdlh_replay_timeout_err\n"
3095 " This bit is set when the REPLAY_TIMER expires in\n"
3096 " the PCIE core. The probability of this bit being\n"
3097 " set will increase with the traffic load.\n";
3098 fail |= cvmx_error_add(&info);
3100 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3101 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3102 info.status_mask = 1ull<<14 /* mre */;
3103 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3104 info.enable_mask = 1ull<<14 /* mre */;
3106 info.group = CVMX_ERROR_GROUP_PCI;
3107 info.group_index = 1;
3108 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3109 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3110 info.parent.status_mask = 1ull<<10 /* exc */;
3111 info.func = __cvmx_error_display;
3112 info.user_info = (long)
3113 "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n"
3114 " xdlh_replay_num_rlover_err\n";
3115 fail |= cvmx_error_add(&info);
3117 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3118 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3119 info.status_mask = 1ull<<15 /* rdwdle */;
3120 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3121 info.enable_mask = 1ull<<15 /* rdwdle */;
3123 info.group = CVMX_ERROR_GROUP_PCI;
3124 info.group_index = 1;
3125 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3126 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3127 info.parent.status_mask = 1ull<<10 /* exc */;
3128 info.func = __cvmx_error_display;
3129 info.user_info = (long)
3130 "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n"
3131 " rdlh_bad_dllp_err\n";
3132 fail |= cvmx_error_add(&info);
3134 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3135 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3136 info.status_mask = 1ull<<16 /* rtwdle */;
3137 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3138 info.enable_mask = 1ull<<16 /* rtwdle */;
3140 info.group = CVMX_ERROR_GROUP_PCI;
3141 info.group_index = 1;
3142 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3143 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3144 info.parent.status_mask = 1ull<<10 /* exc */;
3145 info.func = __cvmx_error_display;
3146 info.user_info = (long)
3147 "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n"
3148 " rdlh_bad_tlp_err\n";
3149 fail |= cvmx_error_add(&info);
3151 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3152 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3153 info.status_mask = 1ull<<17 /* dpeoosd */;
3154 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3155 info.enable_mask = 1ull<<17 /* dpeoosd */;
3157 info.group = CVMX_ERROR_GROUP_PCI;
3158 info.group_index = 1;
3159 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3160 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3161 info.parent.status_mask = 1ull<<10 /* exc */;
3162 info.func = __cvmx_error_display;
3163 info.user_info = (long)
3164 "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n"
3166 fail |= cvmx_error_add(&info);
3168 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3169 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3170 info.status_mask = 1ull<<18 /* fcpvwt */;
3171 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3172 info.enable_mask = 1ull<<18 /* fcpvwt */;
3174 info.group = CVMX_ERROR_GROUP_PCI;
3175 info.group_index = 1;
3176 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3177 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3178 info.parent.status_mask = 1ull<<10 /* exc */;
3179 info.func = __cvmx_error_display;
3180 info.user_info = (long)
3181 "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n"
3182 " rtlh_fc_prot_err\n";
3183 fail |= cvmx_error_add(&info);
3185 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3186 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3187 info.status_mask = 1ull<<19 /* rpe */;
3188 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3189 info.enable_mask = 1ull<<19 /* rpe */;
3191 info.group = CVMX_ERROR_GROUP_PCI;
3192 info.group_index = 1;
3193 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3194 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3195 info.parent.status_mask = 1ull<<10 /* exc */;
3196 info.func = __cvmx_error_display;
3197 info.user_info = (long)
3198 "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n"
3199 " (RxStatus = 3b100) or disparity error\n"
3200 " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n"
3203 fail |= cvmx_error_add(&info);
3205 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3206 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3207 info.status_mask = 1ull<<20 /* fcuv */;
3208 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3209 info.enable_mask = 1ull<<20 /* fcuv */;
3211 info.group = CVMX_ERROR_GROUP_PCI;
3212 info.group_index = 1;
3213 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3214 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3215 info.parent.status_mask = 1ull<<10 /* exc */;
3216 info.func = __cvmx_error_display;
3217 info.user_info = (long)
3218 "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n"
3219 " int_xadm_fc_prot_err\n";
3220 fail |= cvmx_error_add(&info);
3222 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3223 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3224 info.status_mask = 1ull<<21 /* rqo */;
3225 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3226 info.enable_mask = 1ull<<21 /* rqo */;
3228 info.group = CVMX_ERROR_GROUP_PCI;
3229 info.group_index = 1;
3230 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3231 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3232 info.parent.status_mask = 1ull<<10 /* exc */;
3233 info.func = __cvmx_error_display;
3234 info.user_info = (long)
3235 "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n"
3236 " flow control advertisements are ignored\n"
3237 " radm_qoverflow\n";
3238 fail |= cvmx_error_add(&info);
3240 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3241 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3242 info.status_mask = 1ull<<22 /* rauc */;
3243 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3244 info.enable_mask = 1ull<<22 /* rauc */;
3246 info.group = CVMX_ERROR_GROUP_PCI;
3247 info.group_index = 1;
3248 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3249 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3250 info.parent.status_mask = 1ull<<10 /* exc */;
3251 info.func = __cvmx_error_display;
3252 info.user_info = (long)
3253 "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n"
3254 " radm_unexp_cpl_err\n";
3255 fail |= cvmx_error_add(&info);
3257 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3258 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3259 info.status_mask = 1ull<<23 /* racur */;
3260 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3261 info.enable_mask = 1ull<<23 /* racur */;
3263 info.group = CVMX_ERROR_GROUP_PCI;
3264 info.group_index = 1;
3265 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3266 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3267 info.parent.status_mask = 1ull<<10 /* exc */;
3268 info.func = __cvmx_error_display;
3269 info.user_info = (long)
3270 "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n"
3271 " radm_rcvd_cpl_ur\n";
3272 fail |= cvmx_error_add(&info);
3274 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3275 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3276 info.status_mask = 1ull<<24 /* racca */;
3277 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3278 info.enable_mask = 1ull<<24 /* racca */;
3280 info.group = CVMX_ERROR_GROUP_PCI;
3281 info.group_index = 1;
3282 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3283 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3284 info.parent.status_mask = 1ull<<10 /* exc */;
3285 info.func = __cvmx_error_display;
3286 info.user_info = (long)
3287 "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n"
3288 " radm_rcvd_cpl_ca\n";
3289 fail |= cvmx_error_add(&info);
3291 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3292 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3293 info.status_mask = 1ull<<25 /* caar */;
3294 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3295 info.enable_mask = 1ull<<25 /* caar */;
3297 info.group = CVMX_ERROR_GROUP_PCI;
3298 info.group_index = 1;
3299 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3300 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3301 info.parent.status_mask = 1ull<<10 /* exc */;
3302 info.func = __cvmx_error_display;
3303 info.user_info = (long)
3304 "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n"
3305 " radm_rcvd_ca_req\n"
3306 " This bit will never be set because Octeon does\n"
3307 " not generate Completer Aborts.\n";
3308 fail |= cvmx_error_add(&info);
3310 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3311 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3312 info.status_mask = 1ull<<26 /* rarwdns */;
3313 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3314 info.enable_mask = 1ull<<26 /* rarwdns */;
3316 info.group = CVMX_ERROR_GROUP_PCI;
3317 info.group_index = 1;
3318 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3319 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3320 info.parent.status_mask = 1ull<<10 /* exc */;
3321 info.func = __cvmx_error_display;
3322 info.user_info = (long)
3323 "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n"
3324 " radm_rcvd_ur_req\n";
3325 fail |= cvmx_error_add(&info);
3327 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3328 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3329 info.status_mask = 1ull<<27 /* ramtlp */;
3330 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3331 info.enable_mask = 1ull<<27 /* ramtlp */;
3333 info.group = CVMX_ERROR_GROUP_PCI;
3334 info.group_index = 1;
3335 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3336 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3337 info.parent.status_mask = 1ull<<10 /* exc */;
3338 info.func = __cvmx_error_display;
3339 info.user_info = (long)
3340 "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n"
3341 " radm_mlf_tlp_err\n";
3342 fail |= cvmx_error_add(&info);
3344 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3345 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3346 info.status_mask = 1ull<<28 /* racpp */;
3347 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3348 info.enable_mask = 1ull<<28 /* racpp */;
3350 info.group = CVMX_ERROR_GROUP_PCI;
3351 info.group_index = 1;
3352 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3353 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3354 info.parent.status_mask = 1ull<<10 /* exc */;
3355 info.func = __cvmx_error_display;
3356 info.user_info = (long)
3357 "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n"
3358 " radm_rcvd_cpl_poisoned\n";
3359 fail |= cvmx_error_add(&info);
3361 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3362 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3363 info.status_mask = 1ull<<29 /* rawwpp */;
3364 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3365 info.enable_mask = 1ull<<29 /* rawwpp */;
3367 info.group = CVMX_ERROR_GROUP_PCI;
3368 info.group_index = 1;
3369 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3370 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3371 info.parent.status_mask = 1ull<<10 /* exc */;
3372 info.func = __cvmx_error_display;
3373 info.user_info = (long)
3374 "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n"
3375 " radm_rcvd_wreq_poisoned\n";
3376 fail |= cvmx_error_add(&info);
3378 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3379 info.status_addr = CVMX_PEMX_DBG_INFO(1);
3380 info.status_mask = 1ull<<30 /* ecrc_e */;
3381 info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1);
3382 info.enable_mask = 1ull<<30 /* ecrc_e */;
3384 info.group = CVMX_ERROR_GROUP_PCI;
3385 info.group_index = 1;
3386 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3387 info.parent.status_addr = CVMX_PEMX_INT_SUM(1);
3388 info.parent.status_mask = 1ull<<10 /* exc */;
3389 info.func = __cvmx_error_display;
3390 info.user_info = (long)
3391 "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n"
3393 fail |= cvmx_error_add(&info);
3395 /* CVMX_FPA_INT_SUM */
3396 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3397 info.status_addr = CVMX_FPA_INT_SUM;
3398 info.status_mask = 1ull<<0 /* fed0_sbe */;
3399 info.enable_addr = CVMX_FPA_INT_ENB;
3400 info.enable_mask = 1ull<<0 /* fed0_sbe */;
3402 info.group = CVMX_ERROR_GROUP_INTERNAL;
3403 info.group_index = 0;
3404 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3405 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3406 info.parent.status_mask = 1ull<<5 /* fpa */;
3407 info.func = __cvmx_error_display;
3408 info.user_info = (long)
3409 "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n";
3410 fail |= cvmx_error_add(&info);
3412 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3413 info.status_addr = CVMX_FPA_INT_SUM;
3414 info.status_mask = 1ull<<1 /* fed0_dbe */;
3415 info.enable_addr = CVMX_FPA_INT_ENB;
3416 info.enable_mask = 1ull<<1 /* fed0_dbe */;
3418 info.group = CVMX_ERROR_GROUP_INTERNAL;
3419 info.group_index = 0;
3420 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3421 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3422 info.parent.status_mask = 1ull<<5 /* fpa */;
3423 info.func = __cvmx_error_display;
3424 info.user_info = (long)
3425 "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n";
3426 fail |= cvmx_error_add(&info);
3428 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3429 info.status_addr = CVMX_FPA_INT_SUM;
3430 info.status_mask = 1ull<<2 /* fed1_sbe */;
3431 info.enable_addr = CVMX_FPA_INT_ENB;
3432 info.enable_mask = 1ull<<2 /* fed1_sbe */;
3434 info.group = CVMX_ERROR_GROUP_INTERNAL;
3435 info.group_index = 0;
3436 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3437 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3438 info.parent.status_mask = 1ull<<5 /* fpa */;
3439 info.func = __cvmx_error_display;
3440 info.user_info = (long)
3441 "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n";
3442 fail |= cvmx_error_add(&info);
3444 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3445 info.status_addr = CVMX_FPA_INT_SUM;
3446 info.status_mask = 1ull<<3 /* fed1_dbe */;
3447 info.enable_addr = CVMX_FPA_INT_ENB;
3448 info.enable_mask = 1ull<<3 /* fed1_dbe */;
3450 info.group = CVMX_ERROR_GROUP_INTERNAL;
3451 info.group_index = 0;
3452 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3453 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3454 info.parent.status_mask = 1ull<<5 /* fpa */;
3455 info.func = __cvmx_error_display;
3456 info.user_info = (long)
3457 "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n";
3458 fail |= cvmx_error_add(&info);
3460 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3461 info.status_addr = CVMX_FPA_INT_SUM;
3462 info.status_mask = 1ull<<4 /* q0_und */;
3463 info.enable_addr = CVMX_FPA_INT_ENB;
3464 info.enable_mask = 1ull<<4 /* q0_und */;
3466 info.group = CVMX_ERROR_GROUP_INTERNAL;
3467 info.group_index = 0;
3468 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3469 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3470 info.parent.status_mask = 1ull<<5 /* fpa */;
3471 info.func = __cvmx_error_display;
3472 info.user_info = (long)
3473 "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n"
3475 fail |= cvmx_error_add(&info);
3477 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3478 info.status_addr = CVMX_FPA_INT_SUM;
3479 info.status_mask = 1ull<<5 /* q0_coff */;
3480 info.enable_addr = CVMX_FPA_INT_ENB;
3481 info.enable_mask = 1ull<<5 /* q0_coff */;
3483 info.group = CVMX_ERROR_GROUP_INTERNAL;
3484 info.group_index = 0;
3485 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3486 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3487 info.parent.status_mask = 1ull<<5 /* fpa */;
3488 info.func = __cvmx_error_display;
3489 info.user_info = (long)
3490 "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n"
3491 " the count available is greater than pointers\n"
3492 " present in the FPA.\n";
3493 fail |= cvmx_error_add(&info);
3495 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3496 info.status_addr = CVMX_FPA_INT_SUM;
3497 info.status_mask = 1ull<<6 /* q0_perr */;
3498 info.enable_addr = CVMX_FPA_INT_ENB;
3499 info.enable_mask = 1ull<<6 /* q0_perr */;
3501 info.group = CVMX_ERROR_GROUP_INTERNAL;
3502 info.group_index = 0;
3503 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3504 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3505 info.parent.status_mask = 1ull<<5 /* fpa */;
3506 info.func = __cvmx_error_display;
3507 info.user_info = (long)
3508 "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n"
3509 " the L2C does not have the FPA owner ship bit set.\n";
3510 fail |= cvmx_error_add(&info);
3512 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3513 info.status_addr = CVMX_FPA_INT_SUM;
3514 info.status_mask = 1ull<<7 /* q1_und */;
3515 info.enable_addr = CVMX_FPA_INT_ENB;
3516 info.enable_mask = 1ull<<7 /* q1_und */;
3518 info.group = CVMX_ERROR_GROUP_INTERNAL;
3519 info.group_index = 0;
3520 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3521 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3522 info.parent.status_mask = 1ull<<5 /* fpa */;
3523 info.func = __cvmx_error_display;
3524 info.user_info = (long)
3525 "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n"
3527 fail |= cvmx_error_add(&info);
3529 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3530 info.status_addr = CVMX_FPA_INT_SUM;
3531 info.status_mask = 1ull<<8 /* q1_coff */;
3532 info.enable_addr = CVMX_FPA_INT_ENB;
3533 info.enable_mask = 1ull<<8 /* q1_coff */;
3535 info.group = CVMX_ERROR_GROUP_INTERNAL;
3536 info.group_index = 0;
3537 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3538 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3539 info.parent.status_mask = 1ull<<5 /* fpa */;
3540 info.func = __cvmx_error_display;
3541 info.user_info = (long)
3542 "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n"
3543 " the count available is greater than pointers\n"
3544 " present in the FPA.\n";
3545 fail |= cvmx_error_add(&info);
3547 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3548 info.status_addr = CVMX_FPA_INT_SUM;
3549 info.status_mask = 1ull<<9 /* q1_perr */;
3550 info.enable_addr = CVMX_FPA_INT_ENB;
3551 info.enable_mask = 1ull<<9 /* q1_perr */;
3553 info.group = CVMX_ERROR_GROUP_INTERNAL;
3554 info.group_index = 0;
3555 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3556 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3557 info.parent.status_mask = 1ull<<5 /* fpa */;
3558 info.func = __cvmx_error_display;
3559 info.user_info = (long)
3560 "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n"
3561 " the L2C does not have the FPA owner ship bit set.\n";
3562 fail |= cvmx_error_add(&info);
3564 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3565 info.status_addr = CVMX_FPA_INT_SUM;
3566 info.status_mask = 1ull<<10 /* q2_und */;
3567 info.enable_addr = CVMX_FPA_INT_ENB;
3568 info.enable_mask = 1ull<<10 /* q2_und */;
3570 info.group = CVMX_ERROR_GROUP_INTERNAL;
3571 info.group_index = 0;
3572 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3573 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3574 info.parent.status_mask = 1ull<<5 /* fpa */;
3575 info.func = __cvmx_error_display;
3576 info.user_info = (long)
3577 "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n"
3579 fail |= cvmx_error_add(&info);
3581 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3582 info.status_addr = CVMX_FPA_INT_SUM;
3583 info.status_mask = 1ull<<11 /* q2_coff */;
3584 info.enable_addr = CVMX_FPA_INT_ENB;
3585 info.enable_mask = 1ull<<11 /* q2_coff */;
3587 info.group = CVMX_ERROR_GROUP_INTERNAL;
3588 info.group_index = 0;
3589 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3590 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3591 info.parent.status_mask = 1ull<<5 /* fpa */;
3592 info.func = __cvmx_error_display;
3593 info.user_info = (long)
3594 "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n"
3595 " the count available is greater than than pointers\n"
3596 " present in the FPA.\n";
3597 fail |= cvmx_error_add(&info);
3599 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3600 info.status_addr = CVMX_FPA_INT_SUM;
3601 info.status_mask = 1ull<<12 /* q2_perr */;
3602 info.enable_addr = CVMX_FPA_INT_ENB;
3603 info.enable_mask = 1ull<<12 /* q2_perr */;
3605 info.group = CVMX_ERROR_GROUP_INTERNAL;
3606 info.group_index = 0;
3607 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3608 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3609 info.parent.status_mask = 1ull<<5 /* fpa */;
3610 info.func = __cvmx_error_display;
3611 info.user_info = (long)
3612 "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n"
3613 " the L2C does not have the FPA owner ship bit set.\n";
3614 fail |= cvmx_error_add(&info);
3616 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3617 info.status_addr = CVMX_FPA_INT_SUM;
3618 info.status_mask = 1ull<<13 /* q3_und */;
3619 info.enable_addr = CVMX_FPA_INT_ENB;
3620 info.enable_mask = 1ull<<13 /* q3_und */;
3622 info.group = CVMX_ERROR_GROUP_INTERNAL;
3623 info.group_index = 0;
3624 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3625 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3626 info.parent.status_mask = 1ull<<5 /* fpa */;
3627 info.func = __cvmx_error_display;
3628 info.user_info = (long)
3629 "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n"
3631 fail |= cvmx_error_add(&info);
3633 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3634 info.status_addr = CVMX_FPA_INT_SUM;
3635 info.status_mask = 1ull<<14 /* q3_coff */;
3636 info.enable_addr = CVMX_FPA_INT_ENB;
3637 info.enable_mask = 1ull<<14 /* q3_coff */;
3639 info.group = CVMX_ERROR_GROUP_INTERNAL;
3640 info.group_index = 0;
3641 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3642 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3643 info.parent.status_mask = 1ull<<5 /* fpa */;
3644 info.func = __cvmx_error_display;
3645 info.user_info = (long)
3646 "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n"
3647 " the count available is greater than than pointers\n"
3648 " present in the FPA.\n";
3649 fail |= cvmx_error_add(&info);
3651 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3652 info.status_addr = CVMX_FPA_INT_SUM;
3653 info.status_mask = 1ull<<15 /* q3_perr */;
3654 info.enable_addr = CVMX_FPA_INT_ENB;
3655 info.enable_mask = 1ull<<15 /* q3_perr */;
3657 info.group = CVMX_ERROR_GROUP_INTERNAL;
3658 info.group_index = 0;
3659 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3660 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3661 info.parent.status_mask = 1ull<<5 /* fpa */;
3662 info.func = __cvmx_error_display;
3663 info.user_info = (long)
3664 "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n"
3665 " the L2C does not have the FPA owner ship bit set.\n";
3666 fail |= cvmx_error_add(&info);
3668 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3669 info.status_addr = CVMX_FPA_INT_SUM;
3670 info.status_mask = 1ull<<16 /* q4_und */;
3671 info.enable_addr = CVMX_FPA_INT_ENB;
3672 info.enable_mask = 1ull<<16 /* q4_und */;
3674 info.group = CVMX_ERROR_GROUP_INTERNAL;
3675 info.group_index = 0;
3676 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3677 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3678 info.parent.status_mask = 1ull<<5 /* fpa */;
3679 info.func = __cvmx_error_display;
3680 info.user_info = (long)
3681 "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n"
3683 fail |= cvmx_error_add(&info);
3685 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3686 info.status_addr = CVMX_FPA_INT_SUM;
3687 info.status_mask = 1ull<<17 /* q4_coff */;
3688 info.enable_addr = CVMX_FPA_INT_ENB;
3689 info.enable_mask = 1ull<<17 /* q4_coff */;
3691 info.group = CVMX_ERROR_GROUP_INTERNAL;
3692 info.group_index = 0;
3693 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3694 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3695 info.parent.status_mask = 1ull<<5 /* fpa */;
3696 info.func = __cvmx_error_display;
3697 info.user_info = (long)
3698 "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n"
3699 " the count available is greater than than pointers\n"
3700 " present in the FPA.\n";
3701 fail |= cvmx_error_add(&info);
3703 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3704 info.status_addr = CVMX_FPA_INT_SUM;
3705 info.status_mask = 1ull<<18 /* q4_perr */;
3706 info.enable_addr = CVMX_FPA_INT_ENB;
3707 info.enable_mask = 1ull<<18 /* q4_perr */;
3709 info.group = CVMX_ERROR_GROUP_INTERNAL;
3710 info.group_index = 0;
3711 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3712 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3713 info.parent.status_mask = 1ull<<5 /* fpa */;
3714 info.func = __cvmx_error_display;
3715 info.user_info = (long)
3716 "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n"
3717 " the L2C does not have the FPA owner ship bit set.\n";
3718 fail |= cvmx_error_add(&info);
3720 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3721 info.status_addr = CVMX_FPA_INT_SUM;
3722 info.status_mask = 1ull<<19 /* q5_und */;
3723 info.enable_addr = CVMX_FPA_INT_ENB;
3724 info.enable_mask = 1ull<<19 /* q5_und */;
3726 info.group = CVMX_ERROR_GROUP_INTERNAL;
3727 info.group_index = 0;
3728 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3729 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3730 info.parent.status_mask = 1ull<<5 /* fpa */;
3731 info.func = __cvmx_error_display;
3732 info.user_info = (long)
3733 "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n"
3735 fail |= cvmx_error_add(&info);
3737 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3738 info.status_addr = CVMX_FPA_INT_SUM;
3739 info.status_mask = 1ull<<20 /* q5_coff */;
3740 info.enable_addr = CVMX_FPA_INT_ENB;
3741 info.enable_mask = 1ull<<20 /* q5_coff */;
3743 info.group = CVMX_ERROR_GROUP_INTERNAL;
3744 info.group_index = 0;
3745 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3746 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3747 info.parent.status_mask = 1ull<<5 /* fpa */;
3748 info.func = __cvmx_error_display;
3749 info.user_info = (long)
3750 "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n"
3751 " the count available is greater than than pointers\n"
3752 " present in the FPA.\n";
3753 fail |= cvmx_error_add(&info);
3755 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3756 info.status_addr = CVMX_FPA_INT_SUM;
3757 info.status_mask = 1ull<<21 /* q5_perr */;
3758 info.enable_addr = CVMX_FPA_INT_ENB;
3759 info.enable_mask = 1ull<<21 /* q5_perr */;
3761 info.group = CVMX_ERROR_GROUP_INTERNAL;
3762 info.group_index = 0;
3763 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3764 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3765 info.parent.status_mask = 1ull<<5 /* fpa */;
3766 info.func = __cvmx_error_display;
3767 info.user_info = (long)
3768 "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n"
3769 " the L2C does not have the FPA owner ship bit set.\n";
3770 fail |= cvmx_error_add(&info);
3772 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3773 info.status_addr = CVMX_FPA_INT_SUM;
3774 info.status_mask = 1ull<<22 /* q6_und */;
3775 info.enable_addr = CVMX_FPA_INT_ENB;
3776 info.enable_mask = 1ull<<22 /* q6_und */;
3778 info.group = CVMX_ERROR_GROUP_INTERNAL;
3779 info.group_index = 0;
3780 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3781 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3782 info.parent.status_mask = 1ull<<5 /* fpa */;
3783 info.func = __cvmx_error_display;
3784 info.user_info = (long)
3785 "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n"
3787 fail |= cvmx_error_add(&info);
3789 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3790 info.status_addr = CVMX_FPA_INT_SUM;
3791 info.status_mask = 1ull<<23 /* q6_coff */;
3792 info.enable_addr = CVMX_FPA_INT_ENB;
3793 info.enable_mask = 1ull<<23 /* q6_coff */;
3795 info.group = CVMX_ERROR_GROUP_INTERNAL;
3796 info.group_index = 0;
3797 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3798 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3799 info.parent.status_mask = 1ull<<5 /* fpa */;
3800 info.func = __cvmx_error_display;
3801 info.user_info = (long)
3802 "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n"
3803 " the count available is greater than than pointers\n"
3804 " present in the FPA.\n";
3805 fail |= cvmx_error_add(&info);
3807 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3808 info.status_addr = CVMX_FPA_INT_SUM;
3809 info.status_mask = 1ull<<24 /* q6_perr */;
3810 info.enable_addr = CVMX_FPA_INT_ENB;
3811 info.enable_mask = 1ull<<24 /* q6_perr */;
3813 info.group = CVMX_ERROR_GROUP_INTERNAL;
3814 info.group_index = 0;
3815 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3816 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3817 info.parent.status_mask = 1ull<<5 /* fpa */;
3818 info.func = __cvmx_error_display;
3819 info.user_info = (long)
3820 "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n"
3821 " the L2C does not have the FPA owner ship bit set.\n";
3822 fail |= cvmx_error_add(&info);
3824 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3825 info.status_addr = CVMX_FPA_INT_SUM;
3826 info.status_mask = 1ull<<25 /* q7_und */;
3827 info.enable_addr = CVMX_FPA_INT_ENB;
3828 info.enable_mask = 1ull<<25 /* q7_und */;
3830 info.group = CVMX_ERROR_GROUP_INTERNAL;
3831 info.group_index = 0;
3832 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3833 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3834 info.parent.status_mask = 1ull<<5 /* fpa */;
3835 info.func = __cvmx_error_display;
3836 info.user_info = (long)
3837 "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n"
3839 fail |= cvmx_error_add(&info);
3841 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3842 info.status_addr = CVMX_FPA_INT_SUM;
3843 info.status_mask = 1ull<<26 /* q7_coff */;
3844 info.enable_addr = CVMX_FPA_INT_ENB;
3845 info.enable_mask = 1ull<<26 /* q7_coff */;
3847 info.group = CVMX_ERROR_GROUP_INTERNAL;
3848 info.group_index = 0;
3849 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3850 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3851 info.parent.status_mask = 1ull<<5 /* fpa */;
3852 info.func = __cvmx_error_display;
3853 info.user_info = (long)
3854 "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n"
3855 " the count available is greater than than pointers\n"
3856 " present in the FPA.\n";
3857 fail |= cvmx_error_add(&info);
3859 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3860 info.status_addr = CVMX_FPA_INT_SUM;
3861 info.status_mask = 1ull<<27 /* q7_perr */;
3862 info.enable_addr = CVMX_FPA_INT_ENB;
3863 info.enable_mask = 1ull<<27 /* q7_perr */;
3865 info.group = CVMX_ERROR_GROUP_INTERNAL;
3866 info.group_index = 0;
3867 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3868 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3869 info.parent.status_mask = 1ull<<5 /* fpa */;
3870 info.func = __cvmx_error_display;
3871 info.user_info = (long)
3872 "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n"
3873 " the L2C does not have the FPA owner ship bit set.\n";
3874 fail |= cvmx_error_add(&info);
3876 /* CVMX_UCTLX_INT_REG(0) */
3877 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3878 info.status_addr = CVMX_UCTLX_INT_REG(0);
3879 info.status_mask = 1ull<<0 /* pp_psh_f */;
3880 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3881 info.enable_mask = 1ull<<0 /* pp_psh_f */;
3883 info.group = CVMX_ERROR_GROUP_USB;
3884 info.group_index = 0;
3885 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3886 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3887 info.parent.status_mask = 1ull<<13 /* usb */;
3888 info.func = __cvmx_error_display;
3889 info.user_info = (long)
3890 "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n";
3891 fail |= cvmx_error_add(&info);
3893 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3894 info.status_addr = CVMX_UCTLX_INT_REG(0);
3895 info.status_mask = 1ull<<1 /* er_psh_f */;
3896 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3897 info.enable_mask = 1ull<<1 /* er_psh_f */;
3899 info.group = CVMX_ERROR_GROUP_USB;
3900 info.group_index = 0;
3901 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3902 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3903 info.parent.status_mask = 1ull<<13 /* usb */;
3904 info.func = __cvmx_error_display;
3905 info.user_info = (long)
3906 "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n";
3907 fail |= cvmx_error_add(&info);
3909 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3910 info.status_addr = CVMX_UCTLX_INT_REG(0);
3911 info.status_mask = 1ull<<2 /* or_psh_f */;
3912 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3913 info.enable_mask = 1ull<<2 /* or_psh_f */;
3915 info.group = CVMX_ERROR_GROUP_USB;
3916 info.group_index = 0;
3917 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3918 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3919 info.parent.status_mask = 1ull<<13 /* usb */;
3920 info.func = __cvmx_error_display;
3921 info.user_info = (long)
3922 "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n";
3923 fail |= cvmx_error_add(&info);
3925 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3926 info.status_addr = CVMX_UCTLX_INT_REG(0);
3927 info.status_mask = 1ull<<3 /* cf_psh_f */;
3928 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3929 info.enable_mask = 1ull<<3 /* cf_psh_f */;
3931 info.group = CVMX_ERROR_GROUP_USB;
3932 info.group_index = 0;
3933 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3934 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3935 info.parent.status_mask = 1ull<<13 /* usb */;
3936 info.func = __cvmx_error_display;
3937 info.user_info = (long)
3938 "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n";
3939 fail |= cvmx_error_add(&info);
3941 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3942 info.status_addr = CVMX_UCTLX_INT_REG(0);
3943 info.status_mask = 1ull<<4 /* wb_psh_f */;
3944 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3945 info.enable_mask = 1ull<<4 /* wb_psh_f */;
3947 info.group = CVMX_ERROR_GROUP_USB;
3948 info.group_index = 0;
3949 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3950 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3951 info.parent.status_mask = 1ull<<13 /* usb */;
3952 info.func = __cvmx_error_display;
3953 info.user_info = (long)
3954 "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n";
3955 fail |= cvmx_error_add(&info);
3957 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3958 info.status_addr = CVMX_UCTLX_INT_REG(0);
3959 info.status_mask = 1ull<<5 /* wb_pop_e */;
3960 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3961 info.enable_mask = 1ull<<5 /* wb_pop_e */;
3963 info.group = CVMX_ERROR_GROUP_USB;
3964 info.group_index = 0;
3965 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3966 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3967 info.parent.status_mask = 1ull<<13 /* usb */;
3968 info.func = __cvmx_error_display;
3969 info.user_info = (long)
3970 "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n";
3971 fail |= cvmx_error_add(&info);
3973 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3974 info.status_addr = CVMX_UCTLX_INT_REG(0);
3975 info.status_mask = 1ull<<6 /* oc_ovf_e */;
3976 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3977 info.enable_mask = 1ull<<6 /* oc_ovf_e */;
3979 info.group = CVMX_ERROR_GROUP_USB;
3980 info.group_index = 0;
3981 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
3982 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
3983 info.parent.status_mask = 1ull<<13 /* usb */;
3984 info.func = __cvmx_error_display;
3985 info.user_info = (long)
3986 "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n"
3987 " When the error happenes, the whole NCB system needs\n"
3989 fail |= cvmx_error_add(&info);
3991 info.reg_type = CVMX_ERROR_REGISTER_IO64;
3992 info.status_addr = CVMX_UCTLX_INT_REG(0);
3993 info.status_mask = 1ull<<7 /* ec_ovf_e */;
3994 info.enable_addr = CVMX_UCTLX_INT_ENA(0);
3995 info.enable_mask = 1ull<<7 /* ec_ovf_e */;
3997 info.group = CVMX_ERROR_GROUP_USB;
3998 info.group_index = 0;
3999 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4000 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4001 info.parent.status_mask = 1ull<<13 /* usb */;
4002 info.func = __cvmx_error_display;
4003 info.user_info = (long)
4004 "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n"
4005 " When the error happenes, the whole NCB system needs\n"
4007 fail |= cvmx_error_add(&info);
4009 /* CVMX_MIO_BOOT_ERR */
4010 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4011 info.status_addr = CVMX_MIO_BOOT_ERR;
4012 info.status_mask = 1ull<<0 /* adr_err */;
4013 info.enable_addr = CVMX_MIO_BOOT_INT;
4014 info.enable_mask = 1ull<<0 /* adr_int */;
4016 info.group = CVMX_ERROR_GROUP_INTERNAL;
4017 info.group_index = 0;
4018 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4019 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4020 info.parent.status_mask = 1ull<<0 /* mio */;
4021 info.func = __cvmx_error_display;
4022 info.user_info = (long)
4023 "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n";
4024 fail |= cvmx_error_add(&info);
4026 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4027 info.status_addr = CVMX_MIO_BOOT_ERR;
4028 info.status_mask = 1ull<<1 /* wait_err */;
4029 info.enable_addr = CVMX_MIO_BOOT_INT;
4030 info.enable_mask = 1ull<<1 /* wait_int */;
4032 info.group = CVMX_ERROR_GROUP_INTERNAL;
4033 info.group_index = 0;
4034 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4035 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4036 info.parent.status_mask = 1ull<<0 /* mio */;
4037 info.func = __cvmx_error_display;
4038 info.user_info = (long)
4039 "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n";
4040 fail |= cvmx_error_add(&info);
4042 /* CVMX_MIO_RST_INT */
4043 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4044 info.status_addr = CVMX_MIO_RST_INT;
4045 info.status_mask = 1ull<<0 /* rst_link0 */;
4046 info.enable_addr = CVMX_MIO_RST_INT_EN;
4047 info.enable_mask = 1ull<<0 /* rst_link0 */;
4049 info.group = CVMX_ERROR_GROUP_INTERNAL;
4050 info.group_index = 0;
4051 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4052 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4053 info.parent.status_mask = 1ull<<0 /* mio */;
4054 info.func = __cvmx_error_display;
4055 info.user_info = (long)
4056 "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n"
4057 " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n"
4058 " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n";
4059 fail |= cvmx_error_add(&info);
4061 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4062 info.status_addr = CVMX_MIO_RST_INT;
4063 info.status_mask = 1ull<<1 /* rst_link1 */;
4064 info.enable_addr = CVMX_MIO_RST_INT_EN;
4065 info.enable_mask = 1ull<<1 /* rst_link1 */;
4067 info.group = CVMX_ERROR_GROUP_INTERNAL;
4068 info.group_index = 0;
4069 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4070 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4071 info.parent.status_mask = 1ull<<0 /* mio */;
4072 info.func = __cvmx_error_display;
4073 info.user_info = (long)
4074 "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n"
4075 " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n"
4076 " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n";
4077 fail |= cvmx_error_add(&info);
4079 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4080 info.status_addr = CVMX_MIO_RST_INT;
4081 info.status_mask = 1ull<<8 /* perst0 */;
4082 info.enable_addr = CVMX_MIO_RST_INT_EN;
4083 info.enable_mask = 1ull<<8 /* perst0 */;
4085 info.group = CVMX_ERROR_GROUP_INTERNAL;
4086 info.group_index = 0;
4087 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4088 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4089 info.parent.status_mask = 1ull<<0 /* mio */;
4090 info.func = __cvmx_error_display;
4091 info.user_info = (long)
4092 "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n"
4093 " and MIO_RST_CTL0[RST_CHIP]=0\n";
4094 fail |= cvmx_error_add(&info);
4096 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4097 info.status_addr = CVMX_MIO_RST_INT;
4098 info.status_mask = 1ull<<9 /* perst1 */;
4099 info.enable_addr = CVMX_MIO_RST_INT_EN;
4100 info.enable_mask = 1ull<<9 /* perst1 */;
4102 info.group = CVMX_ERROR_GROUP_INTERNAL;
4103 info.group_index = 0;
4104 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4105 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4106 info.parent.status_mask = 1ull<<0 /* mio */;
4107 info.func = __cvmx_error_display;
4108 info.user_info = (long)
4109 "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n"
4110 " and MIO_RST_CTL1[RST_CHIP]=0\n";
4111 fail |= cvmx_error_add(&info);
4113 /* CVMX_DFM_FNT_STAT */
4114 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4115 info.status_addr = CVMX_DFM_FNT_STAT;
4116 info.status_mask = 1ull<<0 /* sbe_err */;
4117 info.enable_addr = CVMX_DFM_FNT_IENA;
4118 info.enable_mask = 1ull<<0 /* sbe_intena */;
4120 info.group = CVMX_ERROR_GROUP_INTERNAL;
4121 info.group_index = 0;
4122 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4123 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4124 info.parent.status_mask = 1ull<<40 /* dfm */;
4125 info.func = __cvmx_error_display;
4126 info.user_info = (long)
4127 "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n"
4129 " Write of 1 will clear the corresponding error bit\n";
4130 fail |= cvmx_error_add(&info);
4132 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4133 info.status_addr = CVMX_DFM_FNT_STAT;
4134 info.status_mask = 1ull<<1 /* dbe_err */;
4135 info.enable_addr = CVMX_DFM_FNT_IENA;
4136 info.enable_mask = 1ull<<1 /* dbe_intena */;
4138 info.group = CVMX_ERROR_GROUP_INTERNAL;
4139 info.group_index = 0;
4140 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4141 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4142 info.parent.status_mask = 1ull<<40 /* dfm */;
4143 info.func = __cvmx_error_display;
4144 info.user_info = (long)
4145 "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n"
4147 " Write of 1 will clear the corresponding error bit\n";
4148 fail |= cvmx_error_add(&info);
4150 /* CVMX_TIM_REG_ERROR */
4151 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4152 info.status_addr = CVMX_TIM_REG_ERROR;
4153 info.status_mask = 0xffffull<<0 /* mask */;
4154 info.enable_addr = CVMX_TIM_REG_INT_MASK;
4155 info.enable_mask = 0xffffull<<0 /* mask */;
4157 info.group = CVMX_ERROR_GROUP_INTERNAL;
4158 info.group_index = 0;
4159 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4160 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4161 info.parent.status_mask = 1ull<<11 /* tim */;
4162 info.func = __cvmx_error_display;
4163 info.user_info = (long)
4164 "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n";
4165 fail |= cvmx_error_add(&info);
4167 /* CVMX_LMCX_INT(0) */
4168 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4169 info.status_addr = CVMX_LMCX_INT(0);
4170 info.status_mask = 0xfull<<1 /* sec_err */;
4171 info.enable_addr = CVMX_LMCX_INT_EN(0);
4172 info.enable_mask = 1ull<<1 /* intr_sec_ena */;
4173 info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT;
4174 info.group = CVMX_ERROR_GROUP_LMC;
4175 info.group_index = 0;
4176 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4177 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4178 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4179 info.func = __cvmx_error_display;
4180 info.user_info = (long)
4181 "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n"
4182 " [0] corresponds to DQ[63:0]_c0_p0\n"
4183 " [1] corresponds to DQ[63:0]_c0_p1\n"
4184 " [2] corresponds to DQ[63:0]_c1_p0\n"
4185 " [3] corresponds to DQ[63:0]_c1_p1\n"
4186 " where _cC_pP denotes cycle C and phase P\n"
4187 " Write of 1 will clear the corresponding error bit\n";
4188 fail |= cvmx_error_add(&info);
4190 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4191 info.status_addr = CVMX_LMCX_INT(0);
4192 info.status_mask = 1ull<<0 /* nxm_wr_err */;
4193 info.enable_addr = CVMX_LMCX_INT_EN(0);
4194 info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */;
4196 info.group = CVMX_ERROR_GROUP_LMC;
4197 info.group_index = 0;
4198 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4199 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4200 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4201 info.func = __cvmx_error_display;
4202 info.user_info = (long)
4203 "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n"
4204 " Write of 1 will clear the corresponding error bit\n";
4205 fail |= cvmx_error_add(&info);
4207 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4208 info.status_addr = CVMX_LMCX_INT(0);
4209 info.status_mask = 0xfull<<5 /* ded_err */;
4210 info.enable_addr = CVMX_LMCX_INT_EN(0);
4211 info.enable_mask = 1ull<<2 /* intr_ded_ena */;
4213 info.group = CVMX_ERROR_GROUP_LMC;
4214 info.group_index = 0;
4215 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4216 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4217 info.parent.status_mask = 1ull<<17 /* lmc0 */;
4218 info.func = __cvmx_error_display;
4219 info.user_info = (long)
4220 "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n"
4221 " [0] corresponds to DQ[63:0]_c0_p0\n"
4222 " [1] corresponds to DQ[63:0]_c0_p1\n"
4223 " [2] corresponds to DQ[63:0]_c1_p0\n"
4224 " [3] corresponds to DQ[63:0]_c1_p1\n"
4225 " where _cC_pP denotes cycle C and phase P\n"
4226 " Write of 1 will clear the corresponding error bit\n";
4227 fail |= cvmx_error_add(&info);
4229 /* CVMX_KEY_INT_SUM */
4230 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4231 info.status_addr = CVMX_KEY_INT_SUM;
4232 info.status_mask = 1ull<<0 /* ked0_sbe */;
4233 info.enable_addr = CVMX_KEY_INT_ENB;
4234 info.enable_mask = 1ull<<0 /* ked0_sbe */;
4236 info.group = CVMX_ERROR_GROUP_INTERNAL;
4237 info.group_index = 0;
4238 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4239 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4240 info.parent.status_mask = 1ull<<4 /* key */;
4241 info.func = __cvmx_error_display;
4242 info.user_info = (long)
4243 "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n"
4245 fail |= cvmx_error_add(&info);
4247 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4248 info.status_addr = CVMX_KEY_INT_SUM;
4249 info.status_mask = 1ull<<1 /* ked0_dbe */;
4250 info.enable_addr = CVMX_KEY_INT_ENB;
4251 info.enable_mask = 1ull<<1 /* ked0_dbe */;
4253 info.group = CVMX_ERROR_GROUP_INTERNAL;
4254 info.group_index = 0;
4255 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4256 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4257 info.parent.status_mask = 1ull<<4 /* key */;
4258 info.func = __cvmx_error_display;
4259 info.user_info = (long)
4260 "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n"
4262 fail |= cvmx_error_add(&info);
4264 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4265 info.status_addr = CVMX_KEY_INT_SUM;
4266 info.status_mask = 1ull<<2 /* ked1_sbe */;
4267 info.enable_addr = CVMX_KEY_INT_ENB;
4268 info.enable_mask = 1ull<<2 /* ked1_sbe */;
4270 info.group = CVMX_ERROR_GROUP_INTERNAL;
4271 info.group_index = 0;
4272 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4273 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4274 info.parent.status_mask = 1ull<<4 /* key */;
4275 info.func = __cvmx_error_display;
4276 info.user_info = (long)
4277 "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n"
4279 fail |= cvmx_error_add(&info);
4281 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4282 info.status_addr = CVMX_KEY_INT_SUM;
4283 info.status_mask = 1ull<<3 /* ked1_dbe */;
4284 info.enable_addr = CVMX_KEY_INT_ENB;
4285 info.enable_mask = 1ull<<3 /* ked1_dbe */;
4287 info.group = CVMX_ERROR_GROUP_INTERNAL;
4288 info.group_index = 0;
4289 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4290 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4291 info.parent.status_mask = 1ull<<4 /* key */;
4292 info.func = __cvmx_error_display;
4293 info.user_info = (long)
4294 "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n"
4296 fail |= cvmx_error_add(&info);
4298 /* CVMX_GMXX_BAD_REG(0) */
4299 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4300 info.status_addr = CVMX_GMXX_BAD_REG(0);
4301 info.status_mask = 0xfull<<2 /* out_ovr */;
4302 info.enable_addr = 0;
4303 info.enable_mask = 0;
4305 info.group = CVMX_ERROR_GROUP_ETHERNET;
4306 info.group_index = 0;
4307 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4308 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4309 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4310 info.func = __cvmx_error_display;
4311 info.user_info = (long)
4312 "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n";
4313 fail |= cvmx_error_add(&info);
4315 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4316 info.status_addr = CVMX_GMXX_BAD_REG(0);
4317 info.status_mask = 0xfull<<22 /* loststat */;
4318 info.enable_addr = 0;
4319 info.enable_mask = 0;
4321 info.group = CVMX_ERROR_GROUP_ETHERNET;
4322 info.group_index = 0;
4323 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4324 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4325 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4326 info.func = __cvmx_error_display;
4327 info.user_info = (long)
4328 "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n"
4329 " In SGMII, one bit per port\n"
4330 " In XAUI, only port0 is used\n"
4331 " TX Stats are corrupted\n";
4332 fail |= cvmx_error_add(&info);
4334 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4335 info.status_addr = CVMX_GMXX_BAD_REG(0);
4336 info.status_mask = 1ull<<26 /* statovr */;
4337 info.enable_addr = 0;
4338 info.enable_mask = 0;
4340 info.group = CVMX_ERROR_GROUP_ETHERNET;
4341 info.group_index = 0;
4342 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4343 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4344 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4345 info.func = __cvmx_error_display;
4346 info.user_info = (long)
4347 "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n"
4348 " The common FIFO to SGMII and XAUI had an overflow\n"
4349 " TX Stats are corrupted\n";
4350 fail |= cvmx_error_add(&info);
4352 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4353 info.status_addr = CVMX_GMXX_BAD_REG(0);
4354 info.status_mask = 0xfull<<27 /* inb_nxa */;
4355 info.enable_addr = 0;
4356 info.enable_mask = 0;
4358 info.group = CVMX_ERROR_GROUP_ETHERNET;
4359 info.group_index = 0;
4360 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4361 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4362 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4363 info.func = __cvmx_error_display;
4364 info.user_info = (long)
4365 "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n";
4366 fail |= cvmx_error_add(&info);
4368 /* CVMX_GMXX_RXX_INT_REG(0,0) */
4369 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4370 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4371 info.status_mask = 1ull<<1 /* carext */;
4372 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4373 info.enable_mask = 1ull<<1 /* carext */;
4375 info.group = CVMX_ERROR_GROUP_ETHERNET;
4376 info.group_index = 0;
4377 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4378 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4379 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4380 info.func = __cvmx_error_display;
4381 info.user_info = (long)
4382 "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n"
4383 " (SGMII/1000Base-X only)\n";
4384 fail |= cvmx_error_add(&info);
4386 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4387 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4388 info.status_mask = 1ull<<8 /* skperr */;
4389 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4390 info.enable_mask = 1ull<<8 /* skperr */;
4392 info.group = CVMX_ERROR_GROUP_ETHERNET;
4393 info.group_index = 0;
4394 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4395 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4396 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4397 info.func = __cvmx_error_display;
4398 info.user_info = (long)
4399 "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n";
4400 fail |= cvmx_error_add(&info);
4402 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4403 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4404 info.status_mask = 1ull<<10 /* ovrerr */;
4405 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4406 info.enable_mask = 1ull<<10 /* ovrerr */;
4408 info.group = CVMX_ERROR_GROUP_ETHERNET;
4409 info.group_index = 0;
4410 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4411 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4412 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4413 info.func = __cvmx_error_display;
4414 info.user_info = (long)
4415 "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4416 " This interrupt should never assert\n"
4417 " (SGMII/1000Base-X only)\n";
4418 fail |= cvmx_error_add(&info);
4420 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4421 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4422 info.status_mask = 1ull<<20 /* loc_fault */;
4423 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4424 info.enable_mask = 1ull<<20 /* loc_fault */;
4426 info.group = CVMX_ERROR_GROUP_ETHERNET;
4427 info.group_index = 0;
4428 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4429 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4430 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4431 info.func = __cvmx_error_display;
4432 info.user_info = (long)
4433 "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4434 " (XAUI Mode only)\n";
4435 fail |= cvmx_error_add(&info);
4437 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4438 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4439 info.status_mask = 1ull<<21 /* rem_fault */;
4440 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4441 info.enable_mask = 1ull<<21 /* rem_fault */;
4443 info.group = CVMX_ERROR_GROUP_ETHERNET;
4444 info.group_index = 0;
4445 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4446 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4447 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4448 info.func = __cvmx_error_display;
4449 info.user_info = (long)
4450 "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4451 " (XAUI Mode only)\n";
4452 fail |= cvmx_error_add(&info);
4454 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4455 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4456 info.status_mask = 1ull<<22 /* bad_seq */;
4457 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4458 info.enable_mask = 1ull<<22 /* bad_seq */;
4460 info.group = CVMX_ERROR_GROUP_ETHERNET;
4461 info.group_index = 0;
4462 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4463 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4464 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4465 info.func = __cvmx_error_display;
4466 info.user_info = (long)
4467 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4468 " (XAUI Mode only)\n";
4469 fail |= cvmx_error_add(&info);
4471 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4472 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4473 info.status_mask = 1ull<<23 /* bad_term */;
4474 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4475 info.enable_mask = 1ull<<23 /* bad_term */;
4477 info.group = CVMX_ERROR_GROUP_ETHERNET;
4478 info.group_index = 0;
4479 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4480 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4481 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4482 info.func = __cvmx_error_display;
4483 info.user_info = (long)
4484 "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n"
4485 " than /T/. The error propagation control\n"
4486 " character /E/ will be included as part of the\n"
4487 " frame and does not cause a frame termination.\n"
4488 " (XAUI Mode only)\n";
4489 fail |= cvmx_error_add(&info);
4491 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4492 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4493 info.status_mask = 1ull<<24 /* unsop */;
4494 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4495 info.enable_mask = 1ull<<24 /* unsop */;
4497 info.group = CVMX_ERROR_GROUP_ETHERNET;
4498 info.group_index = 0;
4499 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4500 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4501 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4502 info.func = __cvmx_error_display;
4503 info.user_info = (long)
4504 "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n"
4505 " (XAUI Mode only)\n";
4506 fail |= cvmx_error_add(&info);
4508 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4509 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4510 info.status_mask = 1ull<<25 /* uneop */;
4511 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4512 info.enable_mask = 1ull<<25 /* uneop */;
4514 info.group = CVMX_ERROR_GROUP_ETHERNET;
4515 info.group_index = 0;
4516 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4517 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4518 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4519 info.func = __cvmx_error_display;
4520 info.user_info = (long)
4521 "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n"
4522 " (XAUI Mode only)\n";
4523 fail |= cvmx_error_add(&info);
4525 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4526 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4527 info.status_mask = 1ull<<26 /* undat */;
4528 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4529 info.enable_mask = 1ull<<26 /* undat */;
4531 info.group = CVMX_ERROR_GROUP_ETHERNET;
4532 info.group_index = 0;
4533 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4534 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4535 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4536 info.func = __cvmx_error_display;
4537 info.user_info = (long)
4538 "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n"
4539 " (XAUI Mode only)\n";
4540 fail |= cvmx_error_add(&info);
4542 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4543 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4544 info.status_mask = 1ull<<27 /* hg2fld */;
4545 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4546 info.enable_mask = 1ull<<27 /* hg2fld */;
4548 info.group = CVMX_ERROR_GROUP_ETHERNET;
4549 info.group_index = 0;
4550 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4551 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4552 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4553 info.func = __cvmx_error_display;
4554 info.user_info = (long)
4555 "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n"
4556 " 1) MSG_TYPE field not 6'b00_0000\n"
4557 " i.e. it is not a FLOW CONTROL message, which\n"
4558 " is the only defined type for HiGig2\n"
4559 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
4560 " which is the only defined type for HiGig2\n"
4561 " 3) FC_OBJECT field is neither 4'b0000 for\n"
4562 " Physical Link nor 4'b0010 for Logical Link.\n"
4563 " Those are the only two defined types in HiGig2\n";
4564 fail |= cvmx_error_add(&info);
4566 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4567 info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0);
4568 info.status_mask = 1ull<<28 /* hg2cc */;
4569 info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0);
4570 info.enable_mask = 1ull<<28 /* hg2cc */;
4572 info.group = CVMX_ERROR_GROUP_ETHERNET;
4573 info.group_index = 0;
4574 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4575 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4576 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4577 info.func = __cvmx_error_display;
4578 info.user_info = (long)
4579 "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
4580 " Set when either CRC8 error detected or when\n"
4581 " a Control Character is found in the message\n"
4582 " bytes after the K.SOM\n"
4583 " NOTE: HG2CC has higher priority than HG2FLD\n"
4584 " i.e. a HiGig2 message that results in HG2CC\n"
4585 " getting set, will never set HG2FLD.\n";
4586 fail |= cvmx_error_add(&info);
4588 /* CVMX_GMXX_RXX_INT_REG(1,0) */
4589 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4590 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4591 info.status_mask = 1ull<<1 /* carext */;
4592 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4593 info.enable_mask = 1ull<<1 /* carext */;
4595 info.group = CVMX_ERROR_GROUP_ETHERNET;
4596 info.group_index = 1;
4597 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4598 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4599 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4600 info.func = __cvmx_error_display;
4601 info.user_info = (long)
4602 "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n"
4603 " (SGMII/1000Base-X only)\n";
4604 fail |= cvmx_error_add(&info);
4606 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4607 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4608 info.status_mask = 1ull<<8 /* skperr */;
4609 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4610 info.enable_mask = 1ull<<8 /* skperr */;
4612 info.group = CVMX_ERROR_GROUP_ETHERNET;
4613 info.group_index = 1;
4614 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4615 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4616 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4617 info.func = __cvmx_error_display;
4618 info.user_info = (long)
4619 "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n";
4620 fail |= cvmx_error_add(&info);
4622 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4623 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4624 info.status_mask = 1ull<<10 /* ovrerr */;
4625 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4626 info.enable_mask = 1ull<<10 /* ovrerr */;
4628 info.group = CVMX_ERROR_GROUP_ETHERNET;
4629 info.group_index = 1;
4630 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4631 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4632 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4633 info.func = __cvmx_error_display;
4634 info.user_info = (long)
4635 "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4636 " This interrupt should never assert\n"
4637 " (SGMII/1000Base-X only)\n";
4638 fail |= cvmx_error_add(&info);
4640 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4641 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4642 info.status_mask = 1ull<<20 /* loc_fault */;
4643 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4644 info.enable_mask = 1ull<<20 /* loc_fault */;
4646 info.group = CVMX_ERROR_GROUP_ETHERNET;
4647 info.group_index = 1;
4648 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4649 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4650 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4651 info.func = __cvmx_error_display;
4652 info.user_info = (long)
4653 "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4654 " (XAUI Mode only)\n";
4655 fail |= cvmx_error_add(&info);
4657 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4658 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4659 info.status_mask = 1ull<<21 /* rem_fault */;
4660 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4661 info.enable_mask = 1ull<<21 /* rem_fault */;
4663 info.group = CVMX_ERROR_GROUP_ETHERNET;
4664 info.group_index = 1;
4665 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4666 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4667 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4668 info.func = __cvmx_error_display;
4669 info.user_info = (long)
4670 "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4671 " (XAUI Mode only)\n";
4672 fail |= cvmx_error_add(&info);
4674 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4675 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4676 info.status_mask = 1ull<<22 /* bad_seq */;
4677 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4678 info.enable_mask = 1ull<<22 /* bad_seq */;
4680 info.group = CVMX_ERROR_GROUP_ETHERNET;
4681 info.group_index = 1;
4682 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4683 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4684 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4685 info.func = __cvmx_error_display;
4686 info.user_info = (long)
4687 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4688 " (XAUI Mode only)\n";
4689 fail |= cvmx_error_add(&info);
4691 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4692 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4693 info.status_mask = 1ull<<23 /* bad_term */;
4694 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4695 info.enable_mask = 1ull<<23 /* bad_term */;
4697 info.group = CVMX_ERROR_GROUP_ETHERNET;
4698 info.group_index = 1;
4699 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4700 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4701 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4702 info.func = __cvmx_error_display;
4703 info.user_info = (long)
4704 "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n"
4705 " than /T/. The error propagation control\n"
4706 " character /E/ will be included as part of the\n"
4707 " frame and does not cause a frame termination.\n"
4708 " (XAUI Mode only)\n";
4709 fail |= cvmx_error_add(&info);
4711 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4712 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4713 info.status_mask = 1ull<<24 /* unsop */;
4714 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4715 info.enable_mask = 1ull<<24 /* unsop */;
4717 info.group = CVMX_ERROR_GROUP_ETHERNET;
4718 info.group_index = 1;
4719 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4720 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4721 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4722 info.func = __cvmx_error_display;
4723 info.user_info = (long)
4724 "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n"
4725 " (XAUI Mode only)\n";
4726 fail |= cvmx_error_add(&info);
4728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4729 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4730 info.status_mask = 1ull<<25 /* uneop */;
4731 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4732 info.enable_mask = 1ull<<25 /* uneop */;
4734 info.group = CVMX_ERROR_GROUP_ETHERNET;
4735 info.group_index = 1;
4736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4737 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4738 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4739 info.func = __cvmx_error_display;
4740 info.user_info = (long)
4741 "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n"
4742 " (XAUI Mode only)\n";
4743 fail |= cvmx_error_add(&info);
4745 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4746 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4747 info.status_mask = 1ull<<26 /* undat */;
4748 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4749 info.enable_mask = 1ull<<26 /* undat */;
4751 info.group = CVMX_ERROR_GROUP_ETHERNET;
4752 info.group_index = 1;
4753 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4754 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4755 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4756 info.func = __cvmx_error_display;
4757 info.user_info = (long)
4758 "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n"
4759 " (XAUI Mode only)\n";
4760 fail |= cvmx_error_add(&info);
4762 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4763 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4764 info.status_mask = 1ull<<27 /* hg2fld */;
4765 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4766 info.enable_mask = 1ull<<27 /* hg2fld */;
4768 info.group = CVMX_ERROR_GROUP_ETHERNET;
4769 info.group_index = 1;
4770 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4771 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4772 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4773 info.func = __cvmx_error_display;
4774 info.user_info = (long)
4775 "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n"
4776 " 1) MSG_TYPE field not 6'b00_0000\n"
4777 " i.e. it is not a FLOW CONTROL message, which\n"
4778 " is the only defined type for HiGig2\n"
4779 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
4780 " which is the only defined type for HiGig2\n"
4781 " 3) FC_OBJECT field is neither 4'b0000 for\n"
4782 " Physical Link nor 4'b0010 for Logical Link.\n"
4783 " Those are the only two defined types in HiGig2\n";
4784 fail |= cvmx_error_add(&info);
4786 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4787 info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0);
4788 info.status_mask = 1ull<<28 /* hg2cc */;
4789 info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0);
4790 info.enable_mask = 1ull<<28 /* hg2cc */;
4792 info.group = CVMX_ERROR_GROUP_ETHERNET;
4793 info.group_index = 1;
4794 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4795 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4796 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4797 info.func = __cvmx_error_display;
4798 info.user_info = (long)
4799 "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
4800 " Set when either CRC8 error detected or when\n"
4801 " a Control Character is found in the message\n"
4802 " bytes after the K.SOM\n"
4803 " NOTE: HG2CC has higher priority than HG2FLD\n"
4804 " i.e. a HiGig2 message that results in HG2CC\n"
4805 " getting set, will never set HG2FLD.\n";
4806 fail |= cvmx_error_add(&info);
4808 /* CVMX_GMXX_RXX_INT_REG(2,0) */
4809 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4810 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4811 info.status_mask = 1ull<<1 /* carext */;
4812 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4813 info.enable_mask = 1ull<<1 /* carext */;
4815 info.group = CVMX_ERROR_GROUP_ETHERNET;
4816 info.group_index = 2;
4817 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4818 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4819 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4820 info.func = __cvmx_error_display;
4821 info.user_info = (long)
4822 "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n"
4823 " (SGMII/1000Base-X only)\n";
4824 fail |= cvmx_error_add(&info);
4826 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4827 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4828 info.status_mask = 1ull<<8 /* skperr */;
4829 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4830 info.enable_mask = 1ull<<8 /* skperr */;
4832 info.group = CVMX_ERROR_GROUP_ETHERNET;
4833 info.group_index = 2;
4834 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4835 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4836 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4837 info.func = __cvmx_error_display;
4838 info.user_info = (long)
4839 "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n";
4840 fail |= cvmx_error_add(&info);
4842 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4843 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4844 info.status_mask = 1ull<<10 /* ovrerr */;
4845 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4846 info.enable_mask = 1ull<<10 /* ovrerr */;
4848 info.group = CVMX_ERROR_GROUP_ETHERNET;
4849 info.group_index = 2;
4850 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4851 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4852 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4853 info.func = __cvmx_error_display;
4854 info.user_info = (long)
4855 "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n"
4856 " This interrupt should never assert\n"
4857 " (SGMII/1000Base-X only)\n";
4858 fail |= cvmx_error_add(&info);
4860 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4861 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4862 info.status_mask = 1ull<<20 /* loc_fault */;
4863 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4864 info.enable_mask = 1ull<<20 /* loc_fault */;
4866 info.group = CVMX_ERROR_GROUP_ETHERNET;
4867 info.group_index = 2;
4868 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4869 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4870 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4871 info.func = __cvmx_error_display;
4872 info.user_info = (long)
4873 "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
4874 " (XAUI Mode only)\n";
4875 fail |= cvmx_error_add(&info);
4877 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4878 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4879 info.status_mask = 1ull<<21 /* rem_fault */;
4880 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4881 info.enable_mask = 1ull<<21 /* rem_fault */;
4883 info.group = CVMX_ERROR_GROUP_ETHERNET;
4884 info.group_index = 2;
4885 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4886 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4887 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4888 info.func = __cvmx_error_display;
4889 info.user_info = (long)
4890 "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
4891 " (XAUI Mode only)\n";
4892 fail |= cvmx_error_add(&info);
4894 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4895 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4896 info.status_mask = 1ull<<22 /* bad_seq */;
4897 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4898 info.enable_mask = 1ull<<22 /* bad_seq */;
4900 info.group = CVMX_ERROR_GROUP_ETHERNET;
4901 info.group_index = 2;
4902 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4903 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4904 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4905 info.func = __cvmx_error_display;
4906 info.user_info = (long)
4907 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
4908 " (XAUI Mode only)\n";
4909 fail |= cvmx_error_add(&info);
4911 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4912 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4913 info.status_mask = 1ull<<23 /* bad_term */;
4914 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4915 info.enable_mask = 1ull<<23 /* bad_term */;
4917 info.group = CVMX_ERROR_GROUP_ETHERNET;
4918 info.group_index = 2;
4919 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4920 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4921 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4922 info.func = __cvmx_error_display;
4923 info.user_info = (long)
4924 "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n"
4925 " than /T/. The error propagation control\n"
4926 " character /E/ will be included as part of the\n"
4927 " frame and does not cause a frame termination.\n"
4928 " (XAUI Mode only)\n";
4929 fail |= cvmx_error_add(&info);
4931 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4932 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4933 info.status_mask = 1ull<<24 /* unsop */;
4934 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4935 info.enable_mask = 1ull<<24 /* unsop */;
4937 info.group = CVMX_ERROR_GROUP_ETHERNET;
4938 info.group_index = 2;
4939 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4940 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4941 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4942 info.func = __cvmx_error_display;
4943 info.user_info = (long)
4944 "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n"
4945 " (XAUI Mode only)\n";
4946 fail |= cvmx_error_add(&info);
4948 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4949 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4950 info.status_mask = 1ull<<25 /* uneop */;
4951 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4952 info.enable_mask = 1ull<<25 /* uneop */;
4954 info.group = CVMX_ERROR_GROUP_ETHERNET;
4955 info.group_index = 2;
4956 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4957 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4958 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4959 info.func = __cvmx_error_display;
4960 info.user_info = (long)
4961 "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n"
4962 " (XAUI Mode only)\n";
4963 fail |= cvmx_error_add(&info);
4965 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4966 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4967 info.status_mask = 1ull<<26 /* undat */;
4968 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4969 info.enable_mask = 1ull<<26 /* undat */;
4971 info.group = CVMX_ERROR_GROUP_ETHERNET;
4972 info.group_index = 2;
4973 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4974 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4975 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4976 info.func = __cvmx_error_display;
4977 info.user_info = (long)
4978 "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n"
4979 " (XAUI Mode only)\n";
4980 fail |= cvmx_error_add(&info);
4982 info.reg_type = CVMX_ERROR_REGISTER_IO64;
4983 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
4984 info.status_mask = 1ull<<27 /* hg2fld */;
4985 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
4986 info.enable_mask = 1ull<<27 /* hg2fld */;
4988 info.group = CVMX_ERROR_GROUP_ETHERNET;
4989 info.group_index = 2;
4990 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
4991 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
4992 info.parent.status_mask = 1ull<<1 /* gmx0 */;
4993 info.func = __cvmx_error_display;
4994 info.user_info = (long)
4995 "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n"
4996 " 1) MSG_TYPE field not 6'b00_0000\n"
4997 " i.e. it is not a FLOW CONTROL message, which\n"
4998 " is the only defined type for HiGig2\n"
4999 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5000 " which is the only defined type for HiGig2\n"
5001 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5002 " Physical Link nor 4'b0010 for Logical Link.\n"
5003 " Those are the only two defined types in HiGig2\n";
5004 fail |= cvmx_error_add(&info);
5006 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5007 info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0);
5008 info.status_mask = 1ull<<28 /* hg2cc */;
5009 info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0);
5010 info.enable_mask = 1ull<<28 /* hg2cc */;
5012 info.group = CVMX_ERROR_GROUP_ETHERNET;
5013 info.group_index = 2;
5014 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5015 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5016 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5017 info.func = __cvmx_error_display;
5018 info.user_info = (long)
5019 "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5020 " Set when either CRC8 error detected or when\n"
5021 " a Control Character is found in the message\n"
5022 " bytes after the K.SOM\n"
5023 " NOTE: HG2CC has higher priority than HG2FLD\n"
5024 " i.e. a HiGig2 message that results in HG2CC\n"
5025 " getting set, will never set HG2FLD.\n";
5026 fail |= cvmx_error_add(&info);
5028 /* CVMX_GMXX_RXX_INT_REG(3,0) */
5029 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5030 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5031 info.status_mask = 1ull<<1 /* carext */;
5032 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5033 info.enable_mask = 1ull<<1 /* carext */;
5035 info.group = CVMX_ERROR_GROUP_ETHERNET;
5036 info.group_index = 3;
5037 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5038 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5039 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5040 info.func = __cvmx_error_display;
5041 info.user_info = (long)
5042 "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n"
5043 " (SGMII/1000Base-X only)\n";
5044 fail |= cvmx_error_add(&info);
5046 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5047 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5048 info.status_mask = 1ull<<8 /* skperr */;
5049 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5050 info.enable_mask = 1ull<<8 /* skperr */;
5052 info.group = CVMX_ERROR_GROUP_ETHERNET;
5053 info.group_index = 3;
5054 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5055 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5056 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5057 info.func = __cvmx_error_display;
5058 info.user_info = (long)
5059 "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n";
5060 fail |= cvmx_error_add(&info);
5062 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5063 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5064 info.status_mask = 1ull<<10 /* ovrerr */;
5065 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5066 info.enable_mask = 1ull<<10 /* ovrerr */;
5068 info.group = CVMX_ERROR_GROUP_ETHERNET;
5069 info.group_index = 3;
5070 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5071 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5072 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5073 info.func = __cvmx_error_display;
5074 info.user_info = (long)
5075 "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n"
5076 " This interrupt should never assert\n"
5077 " (SGMII/1000Base-X only)\n";
5078 fail |= cvmx_error_add(&info);
5080 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5081 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5082 info.status_mask = 1ull<<20 /* loc_fault */;
5083 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5084 info.enable_mask = 1ull<<20 /* loc_fault */;
5086 info.group = CVMX_ERROR_GROUP_ETHERNET;
5087 info.group_index = 3;
5088 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5089 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5090 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5091 info.func = __cvmx_error_display;
5092 info.user_info = (long)
5093 "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n"
5094 " (XAUI Mode only)\n";
5095 fail |= cvmx_error_add(&info);
5097 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5098 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5099 info.status_mask = 1ull<<21 /* rem_fault */;
5100 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5101 info.enable_mask = 1ull<<21 /* rem_fault */;
5103 info.group = CVMX_ERROR_GROUP_ETHERNET;
5104 info.group_index = 3;
5105 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5106 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5107 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5108 info.func = __cvmx_error_display;
5109 info.user_info = (long)
5110 "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n"
5111 " (XAUI Mode only)\n";
5112 fail |= cvmx_error_add(&info);
5114 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5115 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5116 info.status_mask = 1ull<<22 /* bad_seq */;
5117 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5118 info.enable_mask = 1ull<<22 /* bad_seq */;
5120 info.group = CVMX_ERROR_GROUP_ETHERNET;
5121 info.group_index = 3;
5122 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5123 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5124 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5125 info.func = __cvmx_error_display;
5126 info.user_info = (long)
5127 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n"
5128 " (XAUI Mode only)\n";
5129 fail |= cvmx_error_add(&info);
5131 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5132 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5133 info.status_mask = 1ull<<23 /* bad_term */;
5134 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5135 info.enable_mask = 1ull<<23 /* bad_term */;
5137 info.group = CVMX_ERROR_GROUP_ETHERNET;
5138 info.group_index = 3;
5139 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5140 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5141 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5142 info.func = __cvmx_error_display;
5143 info.user_info = (long)
5144 "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n"
5145 " than /T/. The error propagation control\n"
5146 " character /E/ will be included as part of the\n"
5147 " frame and does not cause a frame termination.\n"
5148 " (XAUI Mode only)\n";
5149 fail |= cvmx_error_add(&info);
5151 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5152 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5153 info.status_mask = 1ull<<24 /* unsop */;
5154 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5155 info.enable_mask = 1ull<<24 /* unsop */;
5157 info.group = CVMX_ERROR_GROUP_ETHERNET;
5158 info.group_index = 3;
5159 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5160 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5161 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5162 info.func = __cvmx_error_display;
5163 info.user_info = (long)
5164 "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n"
5165 " (XAUI Mode only)\n";
5166 fail |= cvmx_error_add(&info);
5168 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5169 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5170 info.status_mask = 1ull<<25 /* uneop */;
5171 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5172 info.enable_mask = 1ull<<25 /* uneop */;
5174 info.group = CVMX_ERROR_GROUP_ETHERNET;
5175 info.group_index = 3;
5176 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5177 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5178 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5179 info.func = __cvmx_error_display;
5180 info.user_info = (long)
5181 "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n"
5182 " (XAUI Mode only)\n";
5183 fail |= cvmx_error_add(&info);
5185 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5186 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5187 info.status_mask = 1ull<<26 /* undat */;
5188 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5189 info.enable_mask = 1ull<<26 /* undat */;
5191 info.group = CVMX_ERROR_GROUP_ETHERNET;
5192 info.group_index = 3;
5193 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5194 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5195 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5196 info.func = __cvmx_error_display;
5197 info.user_info = (long)
5198 "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n"
5199 " (XAUI Mode only)\n";
5200 fail |= cvmx_error_add(&info);
5202 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5203 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5204 info.status_mask = 1ull<<27 /* hg2fld */;
5205 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5206 info.enable_mask = 1ull<<27 /* hg2fld */;
5208 info.group = CVMX_ERROR_GROUP_ETHERNET;
5209 info.group_index = 3;
5210 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5211 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5212 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5213 info.func = __cvmx_error_display;
5214 info.user_info = (long)
5215 "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n"
5216 " 1) MSG_TYPE field not 6'b00_0000\n"
5217 " i.e. it is not a FLOW CONTROL message, which\n"
5218 " is the only defined type for HiGig2\n"
5219 " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n"
5220 " which is the only defined type for HiGig2\n"
5221 " 3) FC_OBJECT field is neither 4'b0000 for\n"
5222 " Physical Link nor 4'b0010 for Logical Link.\n"
5223 " Those are the only two defined types in HiGig2\n";
5224 fail |= cvmx_error_add(&info);
5226 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5227 info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0);
5228 info.status_mask = 1ull<<28 /* hg2cc */;
5229 info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0);
5230 info.enable_mask = 1ull<<28 /* hg2cc */;
5232 info.group = CVMX_ERROR_GROUP_ETHERNET;
5233 info.group_index = 3;
5234 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5235 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5236 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5237 info.func = __cvmx_error_display;
5238 info.user_info = (long)
5239 "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n"
5240 " Set when either CRC8 error detected or when\n"
5241 " a Control Character is found in the message\n"
5242 " bytes after the K.SOM\n"
5243 " NOTE: HG2CC has higher priority than HG2FLD\n"
5244 " i.e. a HiGig2 message that results in HG2CC\n"
5245 " getting set, will never set HG2FLD.\n";
5246 fail |= cvmx_error_add(&info);
5248 /* CVMX_GMXX_TX_INT_REG(0) */
5249 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5250 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5251 info.status_mask = 1ull<<0 /* pko_nxa */;
5252 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5253 info.enable_mask = 1ull<<0 /* pko_nxa */;
5255 info.group = CVMX_ERROR_GROUP_ETHERNET;
5256 info.group_index = 0;
5257 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5258 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5259 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5260 info.func = __cvmx_error_display;
5261 info.user_info = (long)
5262 "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5263 fail |= cvmx_error_add(&info);
5265 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5266 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5267 info.status_mask = 0xfull<<2 /* undflw */;
5268 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5269 info.enable_mask = 0xfull<<2 /* undflw */;
5271 info.group = CVMX_ERROR_GROUP_ETHERNET;
5272 info.group_index = 0;
5273 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5274 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5275 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5276 info.func = __cvmx_error_display;
5277 info.user_info = (long)
5278 "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n";
5279 fail |= cvmx_error_add(&info);
5281 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5282 info.status_addr = CVMX_GMXX_TX_INT_REG(0);
5283 info.status_mask = 0xfull<<20 /* ptp_lost */;
5284 info.enable_addr = CVMX_GMXX_TX_INT_EN(0);
5285 info.enable_mask = 0xfull<<20 /* ptp_lost */;
5287 info.group = CVMX_ERROR_GROUP_ETHERNET;
5288 info.group_index = 0;
5289 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5290 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5291 info.parent.status_mask = 1ull<<1 /* gmx0 */;
5292 info.func = __cvmx_error_display;
5293 info.user_info = (long)
5294 "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n"
5295 " sent due to XSCOL\n";
5296 fail |= cvmx_error_add(&info);
5298 /* CVMX_IOB_INT_SUM */
5299 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5300 info.status_addr = CVMX_IOB_INT_SUM;
5301 info.status_mask = 1ull<<0 /* np_sop */;
5302 info.enable_addr = CVMX_IOB_INT_ENB;
5303 info.enable_mask = 1ull<<0 /* np_sop */;
5305 info.group = CVMX_ERROR_GROUP_INTERNAL;
5306 info.group_index = 0;
5307 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5308 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5309 info.parent.status_mask = 1ull<<30 /* iob */;
5310 info.func = __cvmx_error_display;
5311 info.user_info = (long)
5312 "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n"
5313 " port for a non-passthrough packet.\n"
5314 " The first detected error associated with bits [5:0]\n"
5315 " of this register will only be set here. A new bit\n"
5316 " can be set when the previous reported bit is cleared.\n";
5317 fail |= cvmx_error_add(&info);
5319 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5320 info.status_addr = CVMX_IOB_INT_SUM;
5321 info.status_mask = 1ull<<1 /* np_eop */;
5322 info.enable_addr = CVMX_IOB_INT_ENB;
5323 info.enable_mask = 1ull<<1 /* np_eop */;
5325 info.group = CVMX_ERROR_GROUP_INTERNAL;
5326 info.group_index = 0;
5327 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5328 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5329 info.parent.status_mask = 1ull<<30 /* iob */;
5330 info.func = __cvmx_error_display;
5331 info.user_info = (long)
5332 "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n"
5333 " port for a non-passthrough packet.\n"
5334 " The first detected error associated with bits [5:0]\n"
5335 " of this register will only be set here. A new bit\n"
5336 " can be set when the previous reported bit is cleared.\n";
5337 fail |= cvmx_error_add(&info);
5339 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5340 info.status_addr = CVMX_IOB_INT_SUM;
5341 info.status_mask = 1ull<<2 /* p_sop */;
5342 info.enable_addr = CVMX_IOB_INT_ENB;
5343 info.enable_mask = 1ull<<2 /* p_sop */;
5345 info.group = CVMX_ERROR_GROUP_INTERNAL;
5346 info.group_index = 0;
5347 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5348 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5349 info.parent.status_mask = 1ull<<30 /* iob */;
5350 info.func = __cvmx_error_display;
5351 info.user_info = (long)
5352 "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n"
5353 " port for a passthrough packet.\n"
5354 " The first detected error associated with bits [5:0]\n"
5355 " of this register will only be set here. A new bit\n"
5356 " can be set when the previous reported bit is cleared.\n";
5357 fail |= cvmx_error_add(&info);
5359 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5360 info.status_addr = CVMX_IOB_INT_SUM;
5361 info.status_mask = 1ull<<3 /* p_eop */;
5362 info.enable_addr = CVMX_IOB_INT_ENB;
5363 info.enable_mask = 1ull<<3 /* p_eop */;
5365 info.group = CVMX_ERROR_GROUP_INTERNAL;
5366 info.group_index = 0;
5367 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5368 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5369 info.parent.status_mask = 1ull<<30 /* iob */;
5370 info.func = __cvmx_error_display;
5371 info.user_info = (long)
5372 "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n"
5373 " port for a passthrough packet.\n"
5374 " The first detected error associated with bits [5:0]\n"
5375 " of this register will only be set here. A new bit\n"
5376 " can be set when the previous reported bit is cleared.\n";
5377 fail |= cvmx_error_add(&info);
5379 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5380 info.status_addr = CVMX_IOB_INT_SUM;
5381 info.status_mask = 1ull<<4 /* np_dat */;
5382 info.enable_addr = CVMX_IOB_INT_ENB;
5383 info.enable_mask = 1ull<<4 /* np_dat */;
5385 info.group = CVMX_ERROR_GROUP_INTERNAL;
5386 info.group_index = 0;
5387 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5388 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5389 info.parent.status_mask = 1ull<<30 /* iob */;
5390 info.func = __cvmx_error_display;
5391 info.user_info = (long)
5392 "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n"
5393 " port for a non-passthrough packet.\n"
5394 " The first detected error associated with bits [5:0]\n"
5395 " of this register will only be set here. A new bit\n"
5396 " can be set when the previous reported bit is cleared.\n";
5397 fail |= cvmx_error_add(&info);
5399 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5400 info.status_addr = CVMX_IOB_INT_SUM;
5401 info.status_mask = 1ull<<5 /* p_dat */;
5402 info.enable_addr = CVMX_IOB_INT_ENB;
5403 info.enable_mask = 1ull<<5 /* p_dat */;
5405 info.group = CVMX_ERROR_GROUP_INTERNAL;
5406 info.group_index = 0;
5407 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5408 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5409 info.parent.status_mask = 1ull<<30 /* iob */;
5410 info.func = __cvmx_error_display;
5411 info.user_info = (long)
5412 "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n"
5413 " port for a passthrough packet.\n"
5414 " The first detected error associated with bits [5:0]\n"
5415 " of this register will only be set here. A new bit\n"
5416 " can be set when the previous reported bit is cleared.\n";
5417 fail |= cvmx_error_add(&info);
5419 /* CVMX_AGL_GMX_BAD_REG */
5420 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5421 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5422 info.status_mask = 1ull<<32 /* ovrflw */;
5423 info.enable_addr = 0;
5424 info.enable_mask = 0;
5426 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5427 info.group_index = 0;
5428 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5429 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5430 info.parent.status_mask = 1ull<<28 /* agl */;
5431 info.func = __cvmx_error_display;
5432 info.user_info = (long)
5433 "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n";
5434 fail |= cvmx_error_add(&info);
5436 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5437 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5438 info.status_mask = 1ull<<33 /* txpop */;
5439 info.enable_addr = 0;
5440 info.enable_mask = 0;
5442 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5443 info.group_index = 0;
5444 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5445 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5446 info.parent.status_mask = 1ull<<28 /* agl */;
5447 info.func = __cvmx_error_display;
5448 info.user_info = (long)
5449 "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n";
5450 fail |= cvmx_error_add(&info);
5452 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5453 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5454 info.status_mask = 1ull<<34 /* txpsh */;
5455 info.enable_addr = 0;
5456 info.enable_mask = 0;
5458 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5459 info.group_index = 0;
5460 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5461 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5462 info.parent.status_mask = 1ull<<28 /* agl */;
5463 info.func = __cvmx_error_display;
5464 info.user_info = (long)
5465 "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n";
5466 fail |= cvmx_error_add(&info);
5468 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5469 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5470 info.status_mask = 1ull<<35 /* ovrflw1 */;
5471 info.enable_addr = 0;
5472 info.enable_mask = 0;
5474 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5475 info.group_index = 0;
5476 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5477 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5478 info.parent.status_mask = 1ull<<28 /* agl */;
5479 info.func = __cvmx_error_display;
5480 info.user_info = (long)
5481 "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n";
5482 fail |= cvmx_error_add(&info);
5484 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5485 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5486 info.status_mask = 1ull<<36 /* txpop1 */;
5487 info.enable_addr = 0;
5488 info.enable_mask = 0;
5490 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5491 info.group_index = 0;
5492 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5493 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5494 info.parent.status_mask = 1ull<<28 /* agl */;
5495 info.func = __cvmx_error_display;
5496 info.user_info = (long)
5497 "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n";
5498 fail |= cvmx_error_add(&info);
5500 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5501 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5502 info.status_mask = 1ull<<37 /* txpsh1 */;
5503 info.enable_addr = 0;
5504 info.enable_mask = 0;
5506 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5507 info.group_index = 0;
5508 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5509 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5510 info.parent.status_mask = 1ull<<28 /* agl */;
5511 info.func = __cvmx_error_display;
5512 info.user_info = (long)
5513 "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n";
5514 fail |= cvmx_error_add(&info);
5516 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5517 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5518 info.status_mask = 0x3ull<<2 /* out_ovr */;
5519 info.enable_addr = 0;
5520 info.enable_mask = 0;
5522 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5523 info.group_index = 0;
5524 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5525 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5526 info.parent.status_mask = 1ull<<28 /* agl */;
5527 info.func = __cvmx_error_display;
5528 info.user_info = (long)
5529 "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n";
5530 fail |= cvmx_error_add(&info);
5532 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5533 info.status_addr = CVMX_AGL_GMX_BAD_REG;
5534 info.status_mask = 0x3ull<<22 /* loststat */;
5535 info.enable_addr = 0;
5536 info.enable_mask = 0;
5538 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5539 info.group_index = 0;
5540 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5541 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5542 info.parent.status_mask = 1ull<<28 /* agl */;
5543 info.func = __cvmx_error_display;
5544 info.user_info = (long)
5545 "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n"
5546 " In MII/RGMII, one bit per port\n"
5547 " TX Stats are corrupted\n";
5548 fail |= cvmx_error_add(&info);
5550 /* CVMX_AGL_GMX_RXX_INT_REG(0) */
5551 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5552 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5553 info.status_mask = 1ull<<8 /* skperr */;
5554 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5555 info.enable_mask = 1ull<<8 /* skperr */;
5557 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5558 info.group_index = 0;
5559 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5560 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5561 info.parent.status_mask = 1ull<<28 /* agl */;
5562 info.func = __cvmx_error_display;
5563 info.user_info = (long)
5564 "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n";
5565 fail |= cvmx_error_add(&info);
5567 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5568 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0);
5569 info.status_mask = 1ull<<10 /* ovrerr */;
5570 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0);
5571 info.enable_mask = 1ull<<10 /* ovrerr */;
5573 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5574 info.group_index = 0;
5575 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5576 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5577 info.parent.status_mask = 1ull<<28 /* agl */;
5578 info.func = __cvmx_error_display;
5579 info.user_info = (long)
5580 "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n"
5581 " This interrupt should never assert\n";
5582 fail |= cvmx_error_add(&info);
5584 /* CVMX_AGL_GMX_RXX_INT_REG(1) */
5585 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5586 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5587 info.status_mask = 1ull<<8 /* skperr */;
5588 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5589 info.enable_mask = 1ull<<8 /* skperr */;
5591 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5592 info.group_index = 1;
5593 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5594 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5595 info.parent.status_mask = 1ull<<28 /* agl */;
5596 info.func = __cvmx_error_display;
5597 info.user_info = (long)
5598 "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n";
5599 fail |= cvmx_error_add(&info);
5601 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5602 info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1);
5603 info.status_mask = 1ull<<10 /* ovrerr */;
5604 info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1);
5605 info.enable_mask = 1ull<<10 /* ovrerr */;
5607 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5608 info.group_index = 1;
5609 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5610 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5611 info.parent.status_mask = 1ull<<28 /* agl */;
5612 info.func = __cvmx_error_display;
5613 info.user_info = (long)
5614 "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n"
5615 " This interrupt should never assert\n";
5616 fail |= cvmx_error_add(&info);
5618 /* CVMX_AGL_GMX_TX_INT_REG */
5619 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5620 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5621 info.status_mask = 1ull<<0 /* pko_nxa */;
5622 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5623 info.enable_mask = 1ull<<0 /* pko_nxa */;
5625 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5626 info.group_index = 0;
5627 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5628 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5629 info.parent.status_mask = 1ull<<28 /* agl */;
5630 info.func = __cvmx_error_display;
5631 info.user_info = (long)
5632 "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n";
5633 fail |= cvmx_error_add(&info);
5635 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5636 info.status_addr = CVMX_AGL_GMX_TX_INT_REG;
5637 info.status_mask = 0x3ull<<2 /* undflw */;
5638 info.enable_addr = CVMX_AGL_GMX_TX_INT_EN;
5639 info.enable_mask = 0x3ull<<2 /* undflw */;
5641 info.group = CVMX_ERROR_GROUP_MGMT_PORT;
5642 info.group_index = 0;
5643 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5644 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5645 info.parent.status_mask = 1ull<<28 /* agl */;
5646 info.func = __cvmx_error_display;
5647 info.user_info = (long)
5648 "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n";
5649 fail |= cvmx_error_add(&info);
5651 /* CVMX_ZIP_ERROR */
5652 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5653 info.status_addr = CVMX_ZIP_ERROR;
5654 info.status_mask = 1ull<<0 /* doorbell */;
5655 info.enable_addr = CVMX_ZIP_INT_MASK;
5656 info.enable_mask = 1ull<<0 /* doorbell */;
5658 info.group = CVMX_ERROR_GROUP_INTERNAL;
5659 info.group_index = 0;
5660 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5661 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5662 info.parent.status_mask = 1ull<<7 /* zip */;
5663 info.func = __cvmx_error_display;
5664 info.user_info = (long)
5665 "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n";
5666 fail |= cvmx_error_add(&info);
5668 /* CVMX_DFA_ERROR */
5669 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5670 info.status_addr = CVMX_DFA_ERROR;
5671 info.status_mask = 1ull<<0 /* dblovf */;
5672 info.enable_addr = CVMX_DFA_INTMSK;
5673 info.enable_mask = 1ull<<0 /* dblina */;
5675 info.group = CVMX_ERROR_GROUP_INTERNAL;
5676 info.group_index = 0;
5677 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5678 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5679 info.parent.status_mask = 1ull<<6 /* dfa */;
5680 info.func = __cvmx_error_display;
5681 info.user_info = (long)
5682 "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n"
5683 " When set, the 20b accumulated doorbell register\n"
5684 " had overflowed (SW wrote too many doorbell requests).\n"
5685 " If the DBLINA had previously been enabled(set),\n"
5686 " an interrupt will be posted. Software can clear\n"
5687 " the interrupt by writing a 1 to this register bit.\n"
5688 " NOTE: Detection of a Doorbell Register overflow\n"
5689 " is a catastrophic error which may leave the DFA\n"
5690 " HW in an unrecoverable state.\n";
5691 fail |= cvmx_error_add(&info);
5693 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5694 info.status_addr = CVMX_DFA_ERROR;
5695 info.status_mask = 0x7ull<<1 /* dc0perr */;
5696 info.enable_addr = CVMX_DFA_INTMSK;
5697 info.enable_mask = 0x7ull<<1 /* dc0pena */;
5699 info.group = CVMX_ERROR_GROUP_INTERNAL;
5700 info.group_index = 0;
5701 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5702 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5703 info.parent.status_mask = 1ull<<6 /* dfa */;
5704 info.func = __cvmx_error_display;
5705 info.user_info = (long)
5706 "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n"
5707 " See also DFA_DTCFADR register which contains the\n"
5708 " failing addresses for the internal node cache RAMs.\n";
5709 fail |= cvmx_error_add(&info);
5711 /* CVMX_SRIOX_INT_REG(0) */
5712 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5713 info.status_addr = CVMX_SRIOX_INT_REG(0);
5714 info.status_mask = 1ull<<4 /* bar_err */;
5715 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5716 info.enable_mask = 1ull<<4 /* bar_err */;
5718 info.group = CVMX_ERROR_GROUP_SRIO;
5719 info.group_index = 0;
5720 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5721 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5722 info.parent.status_mask = 1ull<<32 /* srio0 */;
5723 info.func = __cvmx_error_display;
5724 info.user_info = (long)
5725 "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
5726 fail |= cvmx_error_add(&info);
5728 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5729 info.status_addr = CVMX_SRIOX_INT_REG(0);
5730 info.status_mask = 1ull<<5 /* deny_wr */;
5731 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5732 info.enable_mask = 1ull<<5 /* deny_wr */;
5734 info.group = CVMX_ERROR_GROUP_SRIO;
5735 info.group_index = 0;
5736 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5737 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5738 info.parent.status_mask = 1ull<<32 /* srio0 */;
5739 info.func = __cvmx_error_display;
5740 info.user_info = (long)
5741 "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
5742 fail |= cvmx_error_add(&info);
5744 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5745 info.status_addr = CVMX_SRIOX_INT_REG(0);
5746 info.status_mask = 1ull<<6 /* sli_err */;
5747 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5748 info.enable_mask = 1ull<<6 /* sli_err */;
5750 info.group = CVMX_ERROR_GROUP_SRIO;
5751 info.group_index = 0;
5752 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5753 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5754 info.parent.status_mask = 1ull<<32 /* srio0 */;
5755 info.func = __cvmx_error_display;
5756 info.user_info = (long)
5757 "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
5758 " See SRIO(0..1)_INT_INFO[1:0]\n";
5759 fail |= cvmx_error_add(&info);
5761 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5762 info.status_addr = CVMX_SRIOX_INT_REG(0);
5763 info.status_mask = 1ull<<9 /* mce_rx */;
5764 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5765 info.enable_mask = 1ull<<9 /* mce_rx */;
5767 info.group = CVMX_ERROR_GROUP_SRIO;
5768 info.group_index = 0;
5769 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5770 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5771 info.parent.status_mask = 1ull<<32 /* srio0 */;
5772 info.func = __cvmx_error_display;
5773 info.user_info = (long)
5774 "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n";
5775 fail |= cvmx_error_add(&info);
5777 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5778 info.status_addr = CVMX_SRIOX_INT_REG(0);
5779 info.status_mask = 1ull<<12 /* log_erb */;
5780 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5781 info.enable_mask = 1ull<<12 /* log_erb */;
5783 info.group = CVMX_ERROR_GROUP_SRIO;
5784 info.group_index = 0;
5785 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5786 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5787 info.parent.status_mask = 1ull<<32 /* srio0 */;
5788 info.func = __cvmx_error_display;
5789 info.user_info = (long)
5790 "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
5791 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
5792 fail |= cvmx_error_add(&info);
5794 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5795 info.status_addr = CVMX_SRIOX_INT_REG(0);
5796 info.status_mask = 1ull<<13 /* phy_erb */;
5797 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5798 info.enable_mask = 1ull<<13 /* phy_erb */;
5800 info.group = CVMX_ERROR_GROUP_SRIO;
5801 info.group_index = 0;
5802 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5803 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5804 info.parent.status_mask = 1ull<<32 /* srio0 */;
5805 info.func = __cvmx_error_display;
5806 info.user_info = (long)
5807 "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n"
5808 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
5809 fail |= cvmx_error_add(&info);
5811 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5812 info.status_addr = CVMX_SRIOX_INT_REG(0);
5813 info.status_mask = 1ull<<18 /* omsg_err */;
5814 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5815 info.enable_mask = 1ull<<18 /* omsg_err */;
5817 info.group = CVMX_ERROR_GROUP_SRIO;
5818 info.group_index = 0;
5819 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5820 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5821 info.parent.status_mask = 1ull<<32 /* srio0 */;
5822 info.func = __cvmx_error_display;
5823 info.user_info = (long)
5824 "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
5825 " See SRIO(0..1)_INT_INFO2\n";
5826 fail |= cvmx_error_add(&info);
5828 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5829 info.status_addr = CVMX_SRIOX_INT_REG(0);
5830 info.status_mask = 1ull<<19 /* pko_err */;
5831 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5832 info.enable_mask = 1ull<<19 /* pko_err */;
5834 info.group = CVMX_ERROR_GROUP_SRIO;
5835 info.group_index = 0;
5836 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5837 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5838 info.parent.status_mask = 1ull<<32 /* srio0 */;
5839 info.func = __cvmx_error_display;
5840 info.user_info = (long)
5841 "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n";
5842 fail |= cvmx_error_add(&info);
5844 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5845 info.status_addr = CVMX_SRIOX_INT_REG(0);
5846 info.status_mask = 1ull<<20 /* rtry_err */;
5847 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5848 info.enable_mask = 1ull<<20 /* rtry_err */;
5850 info.group = CVMX_ERROR_GROUP_SRIO;
5851 info.group_index = 0;
5852 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5853 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5854 info.parent.status_mask = 1ull<<32 /* srio0 */;
5855 info.func = __cvmx_error_display;
5856 info.user_info = (long)
5857 "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
5858 " See SRIO(0..1)_INT_INFO3\n"
5859 " When one or more of the segments in an outgoing\n"
5860 " message have a RTRY_ERR, SRIO will not set\n"
5861 " OMSG* after the message \"transfer\".\n";
5862 fail |= cvmx_error_add(&info);
5864 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5865 info.status_addr = CVMX_SRIOX_INT_REG(0);
5866 info.status_mask = 1ull<<21 /* f_error */;
5867 info.enable_addr = CVMX_SRIOX_INT_ENABLE(0);
5868 info.enable_mask = 1ull<<21 /* f_error */;
5870 info.group = CVMX_ERROR_GROUP_SRIO;
5871 info.group_index = 0;
5872 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5873 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5874 info.parent.status_mask = 1ull<<32 /* srio0 */;
5875 info.func = __cvmx_error_display;
5876 info.user_info = (long)
5877 "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
5878 fail |= cvmx_error_add(&info);
5880 /* CVMX_SRIOX_INT_REG(1) */
5881 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5882 info.status_addr = CVMX_SRIOX_INT_REG(1);
5883 info.status_mask = 1ull<<4 /* bar_err */;
5884 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5885 info.enable_mask = 1ull<<4 /* bar_err */;
5887 info.group = CVMX_ERROR_GROUP_SRIO;
5888 info.group_index = 1;
5889 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5890 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5891 info.parent.status_mask = 1ull<<33 /* srio1 */;
5892 info.func = __cvmx_error_display;
5893 info.user_info = (long)
5894 "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n";
5895 fail |= cvmx_error_add(&info);
5897 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5898 info.status_addr = CVMX_SRIOX_INT_REG(1);
5899 info.status_mask = 1ull<<5 /* deny_wr */;
5900 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5901 info.enable_mask = 1ull<<5 /* deny_wr */;
5903 info.group = CVMX_ERROR_GROUP_SRIO;
5904 info.group_index = 1;
5905 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5906 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5907 info.parent.status_mask = 1ull<<33 /* srio1 */;
5908 info.func = __cvmx_error_display;
5909 info.user_info = (long)
5910 "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n";
5911 fail |= cvmx_error_add(&info);
5913 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5914 info.status_addr = CVMX_SRIOX_INT_REG(1);
5915 info.status_mask = 1ull<<6 /* sli_err */;
5916 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5917 info.enable_mask = 1ull<<6 /* sli_err */;
5919 info.group = CVMX_ERROR_GROUP_SRIO;
5920 info.group_index = 1;
5921 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5922 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5923 info.parent.status_mask = 1ull<<33 /* srio1 */;
5924 info.func = __cvmx_error_display;
5925 info.user_info = (long)
5926 "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n"
5927 " See SRIO(0..1)_INT_INFO[1:0]\n";
5928 fail |= cvmx_error_add(&info);
5930 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5931 info.status_addr = CVMX_SRIOX_INT_REG(1);
5932 info.status_mask = 1ull<<9 /* mce_rx */;
5933 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5934 info.enable_mask = 1ull<<9 /* mce_rx */;
5936 info.group = CVMX_ERROR_GROUP_SRIO;
5937 info.group_index = 1;
5938 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5939 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5940 info.parent.status_mask = 1ull<<33 /* srio1 */;
5941 info.func = __cvmx_error_display;
5942 info.user_info = (long)
5943 "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n";
5944 fail |= cvmx_error_add(&info);
5946 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5947 info.status_addr = CVMX_SRIOX_INT_REG(1);
5948 info.status_mask = 1ull<<12 /* log_erb */;
5949 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5950 info.enable_mask = 1ull<<12 /* log_erb */;
5952 info.group = CVMX_ERROR_GROUP_SRIO;
5953 info.group_index = 1;
5954 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5955 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5956 info.parent.status_mask = 1ull<<33 /* srio1 */;
5957 info.func = __cvmx_error_display;
5958 info.user_info = (long)
5959 "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n"
5960 " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n";
5961 fail |= cvmx_error_add(&info);
5963 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5964 info.status_addr = CVMX_SRIOX_INT_REG(1);
5965 info.status_mask = 1ull<<13 /* phy_erb */;
5966 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5967 info.enable_mask = 1ull<<13 /* phy_erb */;
5969 info.group = CVMX_ERROR_GROUP_SRIO;
5970 info.group_index = 1;
5971 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5972 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5973 info.parent.status_mask = 1ull<<33 /* srio1 */;
5974 info.func = __cvmx_error_display;
5975 info.user_info = (long)
5976 "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n"
5977 " See SRIOMAINT*_ERB_ATTR_CAPT\n";
5978 fail |= cvmx_error_add(&info);
5980 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5981 info.status_addr = CVMX_SRIOX_INT_REG(1);
5982 info.status_mask = 1ull<<18 /* omsg_err */;
5983 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
5984 info.enable_mask = 1ull<<18 /* omsg_err */;
5986 info.group = CVMX_ERROR_GROUP_SRIO;
5987 info.group_index = 1;
5988 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
5989 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
5990 info.parent.status_mask = 1ull<<33 /* srio1 */;
5991 info.func = __cvmx_error_display;
5992 info.user_info = (long)
5993 "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n"
5994 " See SRIO(0..1)_INT_INFO2\n";
5995 fail |= cvmx_error_add(&info);
5997 info.reg_type = CVMX_ERROR_REGISTER_IO64;
5998 info.status_addr = CVMX_SRIOX_INT_REG(1);
5999 info.status_mask = 1ull<<19 /* pko_err */;
6000 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6001 info.enable_mask = 1ull<<19 /* pko_err */;
6003 info.group = CVMX_ERROR_GROUP_SRIO;
6004 info.group_index = 1;
6005 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6006 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6007 info.parent.status_mask = 1ull<<33 /* srio1 */;
6008 info.func = __cvmx_error_display;
6009 info.user_info = (long)
6010 "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n";
6011 fail |= cvmx_error_add(&info);
6013 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6014 info.status_addr = CVMX_SRIOX_INT_REG(1);
6015 info.status_mask = 1ull<<20 /* rtry_err */;
6016 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6017 info.enable_mask = 1ull<<20 /* rtry_err */;
6019 info.group = CVMX_ERROR_GROUP_SRIO;
6020 info.group_index = 1;
6021 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6022 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6023 info.parent.status_mask = 1ull<<33 /* srio1 */;
6024 info.func = __cvmx_error_display;
6025 info.user_info = (long)
6026 "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n"
6027 " See SRIO(0..1)_INT_INFO3\n"
6028 " When one or more of the segments in an outgoing\n"
6029 " message have a RTRY_ERR, SRIO will not set\n"
6030 " OMSG* after the message \"transfer\".\n";
6031 fail |= cvmx_error_add(&info);
6033 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6034 info.status_addr = CVMX_SRIOX_INT_REG(1);
6035 info.status_mask = 1ull<<21 /* f_error */;
6036 info.enable_addr = CVMX_SRIOX_INT_ENABLE(1);
6037 info.enable_mask = 1ull<<21 /* f_error */;
6039 info.group = CVMX_ERROR_GROUP_SRIO;
6040 info.group_index = 1;
6041 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6042 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6043 info.parent.status_mask = 1ull<<33 /* srio1 */;
6044 info.func = __cvmx_error_display;
6045 info.user_info = (long)
6046 "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n";
6047 fail |= cvmx_error_add(&info);
6049 /* CVMX_PEXP_SLI_INT_SUM */
6050 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6051 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6052 info.status_mask = 1ull<<0 /* rml_to */;
6053 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6054 info.enable_mask = 1ull<<0 /* rml_to */;
6056 info.group = CVMX_ERROR_GROUP_INTERNAL;
6057 info.group_index = 0;
6058 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6059 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6060 info.parent.status_mask = 1ull<<3 /* sli */;
6061 info.func = __cvmx_error_display;
6062 info.user_info = (long)
6063 "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n"
6064 " within 0xffff core clocks.\n";
6065 fail |= cvmx_error_add(&info);
6067 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6068 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6069 info.status_mask = 1ull<<1 /* reserved_1_1 */;
6070 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6071 info.enable_mask = 1ull<<1 /* reserved_1_1 */;
6073 info.group = CVMX_ERROR_GROUP_INTERNAL;
6074 info.group_index = 0;
6075 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6076 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6077 info.parent.status_mask = 1ull<<3 /* sli */;
6078 info.func = __cvmx_error_display;
6079 info.user_info = (long)
6080 "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n"
6082 fail |= cvmx_error_add(&info);
6084 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6085 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6086 info.status_mask = 1ull<<2 /* bar0_to */;
6087 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6088 info.enable_mask = 1ull<<2 /* bar0_to */;
6090 info.group = CVMX_ERROR_GROUP_INTERNAL;
6091 info.group_index = 0;
6092 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6093 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6094 info.parent.status_mask = 1ull<<3 /* sli */;
6095 info.func = __cvmx_error_display;
6096 info.user_info = (long)
6097 "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n"
6098 " read-data/commit in 0xffff core clocks.\n";
6099 fail |= cvmx_error_add(&info);
6101 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6102 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6103 info.status_mask = 1ull<<3 /* iob2big */;
6104 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6105 info.enable_mask = 1ull<<3 /* iob2big */;
6107 info.group = CVMX_ERROR_GROUP_INTERNAL;
6108 info.group_index = 0;
6109 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6110 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6111 info.parent.status_mask = 1ull<<3 /* sli */;
6112 info.func = __cvmx_error_display;
6113 info.user_info = (long)
6114 "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n";
6115 fail |= cvmx_error_add(&info);
6117 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6118 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6119 info.status_mask = 0x3ull<<6 /* reserved_6_7 */;
6120 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6121 info.enable_mask = 0x3ull<<6 /* reserved_6_7 */;
6123 info.group = CVMX_ERROR_GROUP_INTERNAL;
6124 info.group_index = 0;
6125 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6126 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6127 info.parent.status_mask = 1ull<<3 /* sli */;
6128 info.func = __cvmx_error_display;
6129 info.user_info = (long)
6130 "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n"
6132 fail |= cvmx_error_add(&info);
6134 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6135 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6136 info.status_mask = 1ull<<8 /* m0_up_b0 */;
6137 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6138 info.enable_mask = 1ull<<8 /* m0_up_b0 */;
6140 info.group = CVMX_ERROR_GROUP_INTERNAL;
6141 info.group_index = 0;
6142 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6143 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6144 info.parent.status_mask = 1ull<<3 /* sli */;
6145 info.func = __cvmx_error_display;
6146 info.user_info = (long)
6147 "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n"
6148 " This occurs when the BAR 0 address space is\n"
6150 fail |= cvmx_error_add(&info);
6152 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6153 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6154 info.status_mask = 1ull<<9 /* m0_up_wi */;
6155 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6156 info.enable_mask = 1ull<<9 /* m0_up_wi */;
6158 info.group = CVMX_ERROR_GROUP_INTERNAL;
6159 info.group_index = 0;
6160 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6161 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6162 info.parent.status_mask = 1ull<<3 /* sli */;
6163 info.func = __cvmx_error_display;
6164 info.user_info = (long)
6165 "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6166 " from MAC 0. This occurs when the window registers\n"
6167 " are disabeld and a window register access occurs.\n";
6168 fail |= cvmx_error_add(&info);
6170 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6171 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6172 info.status_mask = 1ull<<10 /* m0_un_b0 */;
6173 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6174 info.enable_mask = 1ull<<10 /* m0_un_b0 */;
6176 info.group = CVMX_ERROR_GROUP_INTERNAL;
6177 info.group_index = 0;
6178 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6179 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6180 info.parent.status_mask = 1ull<<3 /* sli */;
6181 info.func = __cvmx_error_display;
6182 info.user_info = (long)
6183 "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n"
6184 " This occurs when the BAR 0 address space is\n"
6186 fail |= cvmx_error_add(&info);
6188 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6189 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6190 info.status_mask = 1ull<<11 /* m0_un_wi */;
6191 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6192 info.enable_mask = 1ull<<11 /* m0_un_wi */;
6194 info.group = CVMX_ERROR_GROUP_INTERNAL;
6195 info.group_index = 0;
6196 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6197 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6198 info.parent.status_mask = 1ull<<3 /* sli */;
6199 info.func = __cvmx_error_display;
6200 info.user_info = (long)
6201 "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6202 " from MAC 0. This occurs when the window registers\n"
6203 " are disabeld and a window register access occurs.\n";
6204 fail |= cvmx_error_add(&info);
6206 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6207 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6208 info.status_mask = 1ull<<12 /* m1_up_b0 */;
6209 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6210 info.enable_mask = 1ull<<12 /* m1_up_b0 */;
6212 info.group = CVMX_ERROR_GROUP_INTERNAL;
6213 info.group_index = 0;
6214 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6215 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6216 info.parent.status_mask = 1ull<<3 /* sli */;
6217 info.func = __cvmx_error_display;
6218 info.user_info = (long)
6219 "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n"
6220 " This occurs when the BAR 0 address space is\n"
6222 fail |= cvmx_error_add(&info);
6224 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6225 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6226 info.status_mask = 1ull<<13 /* m1_up_wi */;
6227 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6228 info.enable_mask = 1ull<<13 /* m1_up_wi */;
6230 info.group = CVMX_ERROR_GROUP_INTERNAL;
6231 info.group_index = 0;
6232 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6233 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6234 info.parent.status_mask = 1ull<<3 /* sli */;
6235 info.func = __cvmx_error_display;
6236 info.user_info = (long)
6237 "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n"
6238 " from MAC 1. This occurs when the window registers\n"
6239 " are disabeld and a window register access occurs.\n";
6240 fail |= cvmx_error_add(&info);
6242 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6243 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6244 info.status_mask = 1ull<<14 /* m1_un_b0 */;
6245 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6246 info.enable_mask = 1ull<<14 /* m1_un_b0 */;
6248 info.group = CVMX_ERROR_GROUP_INTERNAL;
6249 info.group_index = 0;
6250 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6251 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6252 info.parent.status_mask = 1ull<<3 /* sli */;
6253 info.func = __cvmx_error_display;
6254 info.user_info = (long)
6255 "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n"
6256 " This occurs when the BAR 0 address space is\n"
6258 fail |= cvmx_error_add(&info);
6260 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6261 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6262 info.status_mask = 1ull<<15 /* m1_un_wi */;
6263 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6264 info.enable_mask = 1ull<<15 /* m1_un_wi */;
6266 info.group = CVMX_ERROR_GROUP_INTERNAL;
6267 info.group_index = 0;
6268 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6269 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6270 info.parent.status_mask = 1ull<<3 /* sli */;
6271 info.func = __cvmx_error_display;
6272 info.user_info = (long)
6273 "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n"
6274 " from MAC 1. This occurs when the window registers\n"
6275 " are disabeld and a window register access occurs.\n";
6276 fail |= cvmx_error_add(&info);
6278 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6279 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6280 info.status_mask = 1ull<<48 /* pidbof */;
6281 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6282 info.enable_mask = 1ull<<48 /* pidbof */;
6284 info.group = CVMX_ERROR_GROUP_INTERNAL;
6285 info.group_index = 0;
6286 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6287 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6288 info.parent.status_mask = 1ull<<3 /* sli */;
6289 info.func = __cvmx_error_display;
6290 info.user_info = (long)
6291 "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n"
6292 " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n";
6293 fail |= cvmx_error_add(&info);
6295 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6296 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6297 info.status_mask = 1ull<<49 /* psldbof */;
6298 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6299 info.enable_mask = 1ull<<49 /* psldbof */;
6301 info.group = CVMX_ERROR_GROUP_INTERNAL;
6302 info.group_index = 0;
6303 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6304 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6305 info.parent.status_mask = 1ull<<3 /* sli */;
6306 info.func = __cvmx_error_display;
6307 info.user_info = (long)
6308 "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n"
6309 " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n";
6310 fail |= cvmx_error_add(&info);
6312 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6313 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6314 info.status_mask = 1ull<<50 /* pout_err */;
6315 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6316 info.enable_mask = 1ull<<50 /* pout_err */;
6318 info.group = CVMX_ERROR_GROUP_INTERNAL;
6319 info.group_index = 0;
6320 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6321 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6322 info.parent.status_mask = 1ull<<3 /* sli */;
6323 info.func = __cvmx_error_display;
6324 info.user_info = (long)
6325 "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n"
6327 fail |= cvmx_error_add(&info);
6329 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6330 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6331 info.status_mask = 1ull<<51 /* pin_bp */;
6332 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6333 info.enable_mask = 1ull<<51 /* pin_bp */;
6335 info.group = CVMX_ERROR_GROUP_INTERNAL;
6336 info.group_index = 0;
6337 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6338 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6339 info.parent.status_mask = 1ull<<3 /* sli */;
6340 info.func = __cvmx_error_display;
6341 info.user_info = (long)
6342 "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n"
6343 " See SLI_PKT_IN_BP\n";
6344 fail |= cvmx_error_add(&info);
6346 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6347 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6348 info.status_mask = 1ull<<52 /* pgl_err */;
6349 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6350 info.enable_mask = 1ull<<52 /* pgl_err */;
6352 info.group = CVMX_ERROR_GROUP_INTERNAL;
6353 info.group_index = 0;
6354 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6355 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6356 info.parent.status_mask = 1ull<<3 /* sli */;
6357 info.func = __cvmx_error_display;
6358 info.user_info = (long)
6359 "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n"
6360 " read this bit is set.\n";
6361 fail |= cvmx_error_add(&info);
6363 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6364 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6365 info.status_mask = 1ull<<53 /* pdi_err */;
6366 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6367 info.enable_mask = 1ull<<53 /* pdi_err */;
6369 info.group = CVMX_ERROR_GROUP_INTERNAL;
6370 info.group_index = 0;
6371 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6372 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6373 info.parent.status_mask = 1ull<<3 /* sli */;
6374 info.func = __cvmx_error_display;
6375 info.user_info = (long)
6376 "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n"
6377 " this bit is set.\n";
6378 fail |= cvmx_error_add(&info);
6380 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6381 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6382 info.status_mask = 1ull<<54 /* pop_err */;
6383 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6384 info.enable_mask = 1ull<<54 /* pop_err */;
6386 info.group = CVMX_ERROR_GROUP_INTERNAL;
6387 info.group_index = 0;
6388 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6389 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6390 info.parent.status_mask = 1ull<<3 /* sli */;
6391 info.func = __cvmx_error_display;
6392 info.user_info = (long)
6393 "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n"
6394 " pointer pair this bit is set.\n";
6395 fail |= cvmx_error_add(&info);
6397 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6398 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6399 info.status_mask = 1ull<<55 /* pins_err */;
6400 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6401 info.enable_mask = 1ull<<55 /* pins_err */;
6403 info.group = CVMX_ERROR_GROUP_INTERNAL;
6404 info.group_index = 0;
6405 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6406 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6407 info.parent.status_mask = 1ull<<3 /* sli */;
6408 info.func = __cvmx_error_display;
6409 info.user_info = (long)
6410 "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n"
6411 " this bit is set.\n";
6412 fail |= cvmx_error_add(&info);
6414 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6415 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6416 info.status_mask = 1ull<<56 /* sprt0_err */;
6417 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6418 info.enable_mask = 1ull<<56 /* sprt0_err */;
6420 info.group = CVMX_ERROR_GROUP_INTERNAL;
6421 info.group_index = 0;
6422 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6423 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6424 info.parent.status_mask = 1ull<<3 /* sli */;
6425 info.func = __cvmx_error_display;
6426 info.user_info = (long)
6427 "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n"
6428 " this bit is set.\n";
6429 fail |= cvmx_error_add(&info);
6431 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6432 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6433 info.status_mask = 1ull<<57 /* sprt1_err */;
6434 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6435 info.enable_mask = 1ull<<57 /* sprt1_err */;
6437 info.group = CVMX_ERROR_GROUP_INTERNAL;
6438 info.group_index = 0;
6439 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6440 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6441 info.parent.status_mask = 1ull<<3 /* sli */;
6442 info.func = __cvmx_error_display;
6443 info.user_info = (long)
6444 "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n"
6445 " this bit is set.\n";
6446 fail |= cvmx_error_add(&info);
6448 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6449 info.status_addr = CVMX_PEXP_SLI_INT_SUM;
6450 info.status_mask = 1ull<<60 /* ill_pad */;
6451 info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU;
6452 info.enable_mask = 1ull<<60 /* ill_pad */;
6454 info.group = CVMX_ERROR_GROUP_INTERNAL;
6455 info.group_index = 0;
6456 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6457 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6458 info.parent.status_mask = 1ull<<3 /* sli */;
6459 info.func = __cvmx_error_display;
6460 info.user_info = (long)
6461 "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n"
6462 " range of the Packet-CSR, but for an unused\n"
6464 fail |= cvmx_error_add(&info);
6466 /* CVMX_DPI_INT_REG */
6467 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6468 info.status_addr = CVMX_DPI_INT_REG;
6469 info.status_mask = 1ull<<0 /* nderr */;
6470 info.enable_addr = CVMX_DPI_INT_EN;
6471 info.enable_mask = 1ull<<0 /* nderr */;
6473 info.group = CVMX_ERROR_GROUP_INTERNAL;
6474 info.group_index = 0;
6475 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6476 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6477 info.parent.status_mask = 1ull<<41 /* dpi */;
6478 info.func = __cvmx_error_display;
6479 info.user_info = (long)
6480 "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n"
6481 " DPI received a NCB transaction on the outbound\n"
6482 " bus to the DPI deviceID, but the command was not\n"
6484 fail |= cvmx_error_add(&info);
6486 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6487 info.status_addr = CVMX_DPI_INT_REG;
6488 info.status_mask = 1ull<<1 /* nfovr */;
6489 info.enable_addr = CVMX_DPI_INT_EN;
6490 info.enable_mask = 1ull<<1 /* nfovr */;
6492 info.group = CVMX_ERROR_GROUP_INTERNAL;
6493 info.group_index = 0;
6494 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6495 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6496 info.parent.status_mask = 1ull<<41 /* dpi */;
6497 info.func = __cvmx_error_display;
6498 info.user_info = (long)
6499 "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n"
6500 " DPI can store upto 16 CSR request. The FIFO will\n"
6501 " overflow if that number is exceeded.\n";
6502 fail |= cvmx_error_add(&info);
6504 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6505 info.status_addr = CVMX_DPI_INT_REG;
6506 info.status_mask = 0xffull<<8 /* dmadbo */;
6507 info.enable_addr = CVMX_DPI_INT_EN;
6508 info.enable_mask = 0xffull<<8 /* dmadbo */;
6510 info.group = CVMX_ERROR_GROUP_INTERNAL;
6511 info.group_index = 0;
6512 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6513 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6514 info.parent.status_mask = 1ull<<41 /* dpi */;
6515 info.func = __cvmx_error_display;
6516 info.user_info = (long)
6517 "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n"
6518 " DPI has a 32-bit counter for each request's queue\n"
6519 " outstanding doorbell counts. Interrupt will fire\n"
6520 " if the count overflows.\n";
6521 fail |= cvmx_error_add(&info);
6523 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6524 info.status_addr = CVMX_DPI_INT_REG;
6525 info.status_mask = 1ull<<16 /* req_badadr */;
6526 info.enable_addr = CVMX_DPI_INT_EN;
6527 info.enable_mask = 1ull<<16 /* req_badadr */;
6529 info.group = CVMX_ERROR_GROUP_INTERNAL;
6530 info.group_index = 0;
6531 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6532 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6533 info.parent.status_mask = 1ull<<41 /* dpi */;
6534 info.func = __cvmx_error_display;
6535 info.user_info = (long)
6536 "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n"
6537 " Interrupt will fire if DPI forms an instruction\n"
6538 " fetch to the NULL pointer.\n";
6539 fail |= cvmx_error_add(&info);
6541 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6542 info.status_addr = CVMX_DPI_INT_REG;
6543 info.status_mask = 1ull<<17 /* req_badlen */;
6544 info.enable_addr = CVMX_DPI_INT_EN;
6545 info.enable_mask = 1ull<<17 /* req_badlen */;
6547 info.group = CVMX_ERROR_GROUP_INTERNAL;
6548 info.group_index = 0;
6549 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6550 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6551 info.parent.status_mask = 1ull<<41 /* dpi */;
6552 info.func = __cvmx_error_display;
6553 info.user_info = (long)
6554 "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n"
6555 " Interrupt will fire if DPI forms an instruction\n"
6556 " fetch with length of zero.\n";
6557 fail |= cvmx_error_add(&info);
6559 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6560 info.status_addr = CVMX_DPI_INT_REG;
6561 info.status_mask = 1ull<<18 /* req_ovrflw */;
6562 info.enable_addr = CVMX_DPI_INT_EN;
6563 info.enable_mask = 1ull<<18 /* req_ovrflw */;
6565 info.group = CVMX_ERROR_GROUP_INTERNAL;
6566 info.group_index = 0;
6567 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6568 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6569 info.parent.status_mask = 1ull<<41 /* dpi */;
6570 info.func = __cvmx_error_display;
6571 info.user_info = (long)
6572 "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n"
6573 " DPI tracks outstanding instructions fetches.\n"
6574 " Interrupt will fire when FIFO overflows.\n";
6575 fail |= cvmx_error_add(&info);
6577 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6578 info.status_addr = CVMX_DPI_INT_REG;
6579 info.status_mask = 1ull<<19 /* req_undflw */;
6580 info.enable_addr = CVMX_DPI_INT_EN;
6581 info.enable_mask = 1ull<<19 /* req_undflw */;
6583 info.group = CVMX_ERROR_GROUP_INTERNAL;
6584 info.group_index = 0;
6585 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6586 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6587 info.parent.status_mask = 1ull<<41 /* dpi */;
6588 info.func = __cvmx_error_display;
6589 info.user_info = (long)
6590 "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n"
6591 " DPI tracks outstanding instructions fetches.\n"
6592 " Interrupt will fire when FIFO underflows.\n";
6593 fail |= cvmx_error_add(&info);
6595 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6596 info.status_addr = CVMX_DPI_INT_REG;
6597 info.status_mask = 1ull<<20 /* req_anull */;
6598 info.enable_addr = CVMX_DPI_INT_EN;
6599 info.enable_mask = 1ull<<20 /* req_anull */;
6601 info.group = CVMX_ERROR_GROUP_INTERNAL;
6602 info.group_index = 0;
6603 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6604 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6605 info.parent.status_mask = 1ull<<41 /* dpi */;
6606 info.func = __cvmx_error_display;
6607 info.user_info = (long)
6608 "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n"
6609 " Fetched instruction word was 0.\n";
6610 fail |= cvmx_error_add(&info);
6612 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6613 info.status_addr = CVMX_DPI_INT_REG;
6614 info.status_mask = 1ull<<21 /* req_inull */;
6615 info.enable_addr = CVMX_DPI_INT_EN;
6616 info.enable_mask = 1ull<<21 /* req_inull */;
6618 info.group = CVMX_ERROR_GROUP_INTERNAL;
6619 info.group_index = 0;
6620 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6621 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6622 info.parent.status_mask = 1ull<<41 /* dpi */;
6623 info.func = __cvmx_error_display;
6624 info.user_info = (long)
6625 "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n"
6626 " Next pointer was NULL.\n";
6627 fail |= cvmx_error_add(&info);
6629 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6630 info.status_addr = CVMX_DPI_INT_REG;
6631 info.status_mask = 1ull<<22 /* req_badfil */;
6632 info.enable_addr = CVMX_DPI_INT_EN;
6633 info.enable_mask = 1ull<<22 /* req_badfil */;
6635 info.group = CVMX_ERROR_GROUP_INTERNAL;
6636 info.group_index = 0;
6637 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6638 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6639 info.parent.status_mask = 1ull<<41 /* dpi */;
6640 info.func = __cvmx_error_display;
6641 info.user_info = (long)
6642 "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n"
6643 " Instruction fill when none outstanding.\n";
6644 fail |= cvmx_error_add(&info);
6646 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6647 info.status_addr = CVMX_DPI_INT_REG;
6648 info.status_mask = 1ull<<24 /* sprt0_rst */;
6649 info.enable_addr = CVMX_DPI_INT_EN;
6650 info.enable_mask = 1ull<<24 /* sprt0_rst */;
6652 info.group = CVMX_ERROR_GROUP_INTERNAL;
6653 info.group_index = 0;
6654 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6655 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6656 info.parent.status_mask = 1ull<<41 /* dpi */;
6657 info.func = __cvmx_error_display;
6658 info.user_info = (long)
6659 "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n"
6660 " destination port was in reset.\n"
6661 " this bit is set.\n";
6662 fail |= cvmx_error_add(&info);
6664 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6665 info.status_addr = CVMX_DPI_INT_REG;
6666 info.status_mask = 1ull<<25 /* sprt1_rst */;
6667 info.enable_addr = CVMX_DPI_INT_EN;
6668 info.enable_mask = 1ull<<25 /* sprt1_rst */;
6670 info.group = CVMX_ERROR_GROUP_INTERNAL;
6671 info.group_index = 0;
6672 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6673 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6674 info.parent.status_mask = 1ull<<41 /* dpi */;
6675 info.func = __cvmx_error_display;
6676 info.user_info = (long)
6677 "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n"
6678 " destination port was in reset.\n"
6679 " this bit is set.\n";
6680 fail |= cvmx_error_add(&info);
6682 /* CVMX_DPI_PKT_ERR_RSP */
6683 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6684 info.status_addr = CVMX_DPI_PKT_ERR_RSP;
6685 info.status_mask = 1ull<<0 /* pkterr */;
6686 info.enable_addr = 0;
6687 info.enable_mask = 0;
6689 info.group = CVMX_ERROR_GROUP_INTERNAL;
6690 info.group_index = 0;
6691 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6692 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6693 info.parent.status_mask = 1ull<<41 /* dpi */;
6694 info.func = __cvmx_error_display;
6695 info.user_info = (long)
6696 "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n"
6697 " the I/O subsystem.\n";
6698 fail |= cvmx_error_add(&info);
6700 /* CVMX_DPI_REQ_ERR_RSP */
6701 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6702 info.status_addr = CVMX_DPI_REQ_ERR_RSP;
6703 info.status_mask = 0xffull<<0 /* qerr */;
6704 info.enable_addr = 0;
6705 info.enable_mask = 0;
6707 info.group = CVMX_ERROR_GROUP_INTERNAL;
6708 info.group_index = 0;
6709 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6710 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6711 info.parent.status_mask = 1ull<<41 /* dpi */;
6712 info.func = __cvmx_error_display;
6713 info.user_info = (long)
6714 "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n"
6715 " ErrorResponse from the I/O subsystem.\n"
6716 " SW must clear the bit before the the cooresponding\n"
6717 " instruction queue will continue processing\n"
6718 " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n";
6719 fail |= cvmx_error_add(&info);
6721 /* CVMX_DPI_REQ_ERR_RST */
6722 info.reg_type = CVMX_ERROR_REGISTER_IO64;
6723 info.status_addr = CVMX_DPI_REQ_ERR_RST;
6724 info.status_mask = 0xffull<<0 /* qerr */;
6725 info.enable_addr = 0;
6726 info.enable_mask = 0;
6728 info.group = CVMX_ERROR_GROUP_INTERNAL;
6729 info.group_index = 0;
6730 info.parent.reg_type = CVMX_ERROR_REGISTER_IO64;
6731 info.parent.status_addr = CVMX_CIU_BLOCK_INT;
6732 info.parent.status_mask = 1ull<<41 /* dpi */;
6733 info.func = __cvmx_error_display;
6734 info.user_info = (long)
6735 "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n"
6736 " instruction because the source or destination\n"
6738 " SW must clear the bit before the the cooresponding\n"
6739 " instruction queue will continue processing\n"
6740 " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n";
6741 fail |= cvmx_error_add(&info);