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45 * Helper utilities for qlm_jtag.
47 * <hr>$Revision: 42480 $<hr>
49 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
50 #include <asm/octeon/cvmx.h>
51 #include <asm/octeon/cvmx-clock.h>
52 #include <asm/octeon/cvmx-helper-jtag.h>
54 #if !defined(__FreeBSD__) || !defined(_KERNEL)
55 #include "executive-config.h"
56 #include "cvmx-config.h"
59 #if defined(__FreeBSD__) && defined(_KERNEL)
60 #include "cvmx-helper-jtag.h"
65 * Initialize the internal QLM JTAG logic to allow programming
66 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
67 * These functions should only be used at the direction of Cavium
68 * Networks. Programming incorrect values into the JTAG chain
69 * can cause chip damage.
71 void cvmx_helper_qlm_jtag_init(void)
73 cvmx_ciu_qlm_jtgc_t jtgc;
75 int divisor = cvmx_clock_get_rate(CVMX_CLOCK_SCLK) / (25 * 1000000);
76 divisor = (divisor-1)>>2;
77 /* Convert the divisor into a power of 2 shift */
84 /* Clock divider for QLM JTAG operations. sclk is divided by 2^(CLK_DIV + 2) */
86 jtgc.s.clk_div = clock_div;
88 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
90 else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
94 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
95 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
100 * Write up to 32bits into the QLM jtag chain. Bits are shifted
101 * into the MSB and out the LSB, so you should shift in the low
102 * order bits followed by the high order bits. The JTAG chain for
103 * CN52XX and CN56XX is 4 * 268 bits long, or 1072. The JTAG chain
104 * for CN63XX is 4 * 300 bits long, or 1200.
106 * @param qlm QLM to shift value into
107 * @param bits Number of bits to shift in (1-32).
108 * @param data Data to shift in. Bit 0 enters the chain first, followed by
111 * @return The low order bits of the JTAG chain that shifted out of the
114 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
116 cvmx_ciu_qlm_jtgc_t jtgc;
117 cvmx_ciu_qlm_jtgd_t jtgd;
119 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
120 jtgc.s.mux_sel = qlm;
121 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
122 jtgc.s.bypass = 1<<qlm;
123 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
124 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
128 jtgd.s.shft_cnt = bits-1;
129 jtgd.s.shft_reg = data;
130 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
131 jtgd.s.select = 1 << qlm;
132 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
135 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
136 } while (jtgd.s.shift);
137 return jtgd.s.shft_reg >> (32-bits);
142 * Shift long sequences of zeros into the QLM JTAG chain. It is
143 * common to need to shift more than 32 bits of zeros into the
144 * chain. This function is a convience wrapper around
145 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
148 * @param qlm QLM to shift zeros into
151 void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
158 cvmx_helper_qlm_jtag_shift(qlm, n, 0);
165 * Program the QLM JTAG chain into all lanes of the QLM. You must
166 * have already shifted in the proper number of bits into the
167 * JTAG chain. Updating invalid values can possibly cause chip damage.
169 * @param qlm QLM to program
171 void cvmx_helper_qlm_jtag_update(int qlm)
173 cvmx_ciu_qlm_jtgc_t jtgc;
174 cvmx_ciu_qlm_jtgd_t jtgd;
176 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
177 jtgc.s.mux_sel = qlm;
178 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
179 jtgc.s.bypass = 1<<qlm;
181 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
182 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
184 /* Update the new data */
187 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
188 jtgd.s.select = 1 << qlm;
189 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
192 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
193 } while (jtgd.s.update);
198 * Load the QLM JTAG chain with data from all lanes of the QLM.
200 * @param qlm QLM to program
202 void cvmx_helper_qlm_jtag_capture(int qlm)
204 cvmx_ciu_qlm_jtgc_t jtgc;
205 cvmx_ciu_qlm_jtgd_t jtgd;
207 jtgc.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGC);
208 jtgc.s.mux_sel = qlm;
209 if (!OCTEON_IS_MODEL(OCTEON_CN63XX))
210 jtgc.s.bypass = 1<<qlm;
212 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
213 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
217 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
218 jtgd.s.select = 1 << qlm;
219 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
222 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
223 } while (jtgd.s.capture);