2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
40 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
72 #include <dev/ale/if_alereg.h>
73 #include <dev/ale/if_alevar.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 /* For more information about Tx checksum offload issues see ale_encap(). */
79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
81 MODULE_DEPEND(ale, pci, 1, 1, 1);
82 MODULE_DEPEND(ale, ether, 1, 1, 1);
83 MODULE_DEPEND(ale, miibus, 1, 1, 1);
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
92 * Devices supported by this driver.
94 static struct ale_dev {
95 uint16_t ale_vendorid;
96 uint16_t ale_deviceid;
99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
103 static int ale_attach(device_t);
104 static int ale_check_boundary(struct ale_softc *);
105 static int ale_detach(device_t);
106 static int ale_dma_alloc(struct ale_softc *);
107 static void ale_dma_free(struct ale_softc *);
108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
109 static int ale_encap(struct ale_softc *, struct mbuf **);
110 static void ale_get_macaddr(struct ale_softc *);
111 static void ale_init(void *);
112 static void ale_init_locked(struct ale_softc *);
113 static void ale_init_rx_pages(struct ale_softc *);
114 static void ale_init_tx_ring(struct ale_softc *);
115 static void ale_int_task(void *, int);
116 static int ale_intr(void *);
117 static int ale_ioctl(struct ifnet *, u_long, caddr_t);
118 static void ale_link_task(void *, int);
119 static void ale_mac_config(struct ale_softc *);
120 static int ale_miibus_readreg(device_t, int, int);
121 static void ale_miibus_statchg(device_t);
122 static int ale_miibus_writereg(device_t, int, int, int);
123 static int ale_mediachange(struct ifnet *);
124 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
125 static void ale_phy_reset(struct ale_softc *);
126 static int ale_probe(device_t);
127 static void ale_reset(struct ale_softc *);
128 static int ale_resume(device_t);
129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
130 uint32_t, uint32_t *);
131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
132 static int ale_rxeof(struct ale_softc *sc, int);
133 static void ale_rxfilter(struct ale_softc *);
134 static void ale_rxvlan(struct ale_softc *);
135 static void ale_setlinkspeed(struct ale_softc *);
136 static void ale_setwol(struct ale_softc *);
137 static int ale_shutdown(device_t);
138 static void ale_start(struct ifnet *);
139 static void ale_start_locked(struct ifnet *);
140 static void ale_stats_clear(struct ale_softc *);
141 static void ale_stats_update(struct ale_softc *);
142 static void ale_stop(struct ale_softc *);
143 static void ale_stop_mac(struct ale_softc *);
144 static int ale_suspend(device_t);
145 static void ale_sysctl_node(struct ale_softc *);
146 static void ale_tick(void *);
147 static void ale_txeof(struct ale_softc *);
148 static void ale_watchdog(struct ale_softc *);
149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
153 static device_method_t ale_methods[] = {
154 /* Device interface. */
155 DEVMETHOD(device_probe, ale_probe),
156 DEVMETHOD(device_attach, ale_attach),
157 DEVMETHOD(device_detach, ale_detach),
158 DEVMETHOD(device_shutdown, ale_shutdown),
159 DEVMETHOD(device_suspend, ale_suspend),
160 DEVMETHOD(device_resume, ale_resume),
163 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
164 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
165 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
170 static driver_t ale_driver = {
173 sizeof(struct ale_softc)
176 static devclass_t ale_devclass;
178 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0);
179 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
181 static struct resource_spec ale_res_spec_mem[] = {
182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
186 static struct resource_spec ale_irq_spec_legacy[] = {
187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
191 static struct resource_spec ale_irq_spec_msi[] = {
192 { SYS_RES_IRQ, 1, RF_ACTIVE },
196 static struct resource_spec ale_irq_spec_msix[] = {
197 { SYS_RES_IRQ, 1, RF_ACTIVE },
202 ale_miibus_readreg(device_t dev, int phy, int reg)
204 struct ale_softc *sc;
208 sc = device_get_softc(dev);
210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
214 v = CSR_READ_4(sc, ALE_MDIO);
215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
228 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
230 struct ale_softc *sc;
234 sc = device_get_softc(dev);
236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
241 v = CSR_READ_4(sc, ALE_MDIO);
242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
253 ale_miibus_statchg(device_t dev)
255 struct ale_softc *sc;
257 sc = device_get_softc(dev);
259 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task);
263 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
265 struct ale_softc *sc;
266 struct mii_data *mii;
270 mii = device_get_softc(sc->ale_miibus);
274 ifmr->ifm_status = mii->mii_media_status;
275 ifmr->ifm_active = mii->mii_media_active;
279 ale_mediachange(struct ifnet *ifp)
281 struct ale_softc *sc;
282 struct mii_data *mii;
283 struct mii_softc *miisc;
288 mii = device_get_softc(sc->ale_miibus);
289 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
291 error = mii_mediachg(mii);
298 ale_probe(device_t dev)
302 uint16_t vendor, devid;
304 vendor = pci_get_vendor(dev);
305 devid = pci_get_device(dev);
307 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
308 if (vendor == sp->ale_vendorid &&
309 devid == sp->ale_deviceid) {
310 device_set_desc(dev, sp->ale_name);
311 return (BUS_PROBE_DEFAULT);
320 ale_get_macaddr(struct ale_softc *sc)
325 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
326 if ((reg & SPI_VPD_ENB) != 0) {
328 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
331 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
333 * PCI VPD capability found, let TWSI reload EEPROM.
334 * This will set ethernet address of controller.
336 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
337 TWSI_CTRL_SW_LD_START);
338 for (i = 100; i > 0; i--) {
340 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
341 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
345 device_printf(sc->ale_dev,
346 "reloading EEPROM timeout!\n");
349 device_printf(sc->ale_dev,
350 "PCI VPD capability not found!\n");
353 ea[0] = CSR_READ_4(sc, ALE_PAR0);
354 ea[1] = CSR_READ_4(sc, ALE_PAR1);
355 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
356 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
357 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
358 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
359 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
360 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
364 ale_phy_reset(struct ale_softc *sc)
367 /* Reset magic from Linux. */
368 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
369 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
370 GPHY_CTRL_PHY_PLL_ON);
372 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
373 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
374 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
377 #define ATPHY_DBG_ADDR 0x1D
378 #define ATPHY_DBG_DATA 0x1E
380 /* Enable hibernation mode. */
381 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
382 ATPHY_DBG_ADDR, 0x0B);
383 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
384 ATPHY_DBG_DATA, 0xBC00);
385 /* Set Class A/B for all modes. */
386 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
387 ATPHY_DBG_ADDR, 0x00);
388 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
389 ATPHY_DBG_DATA, 0x02EF);
390 /* Enable 10BT power saving. */
391 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
392 ATPHY_DBG_ADDR, 0x12);
393 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
394 ATPHY_DBG_DATA, 0x4C04);
395 /* Adjust 1000T power. */
396 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
397 ATPHY_DBG_ADDR, 0x04);
398 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
399 ATPHY_DBG_ADDR, 0x8BBB);
400 /* 10BT center tap voltage. */
401 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
402 ATPHY_DBG_ADDR, 0x05);
403 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
404 ATPHY_DBG_ADDR, 0x2C46);
406 #undef ATPHY_DBG_ADDR
407 #undef ATPHY_DBG_DATA
412 ale_attach(device_t dev)
414 struct ale_softc *sc;
417 int error, i, msic, msixc, pmc;
418 uint32_t rxf_len, txf_len;
421 sc = device_get_softc(dev);
424 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
426 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
427 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
428 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc);
430 /* Map the device. */
431 pci_enable_busmaster(dev);
432 sc->ale_res_spec = ale_res_spec_mem;
433 sc->ale_irq_spec = ale_irq_spec_legacy;
434 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
436 device_printf(dev, "cannot allocate memory resources.\n");
440 /* Set PHY address. */
441 sc->ale_phyaddr = ALE_PHY_ADDR;
446 /* Reset the ethernet controller. */
449 /* Get PCI and chip id/revision. */
450 sc->ale_rev = pci_get_revid(dev);
451 if (sc->ale_rev >= 0xF0) {
452 /* L2E Rev. B. AR8114 */
453 sc->ale_flags |= ALE_FLAG_FASTETHER;
455 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
457 sc->ale_flags |= ALE_FLAG_JUMBO;
459 /* L2E Rev. A. AR8113 */
460 sc->ale_flags |= ALE_FLAG_FASTETHER;
464 * All known controllers seems to require 4 bytes alignment
465 * of Tx buffers to make Tx checksum offload with custom
466 * checksum generation method work.
468 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
470 * All known controllers seems to have issues on Rx checksum
471 * offload for fragmented IP datagrams.
473 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
475 * Don't use Tx CMB. It is known to cause RRS update failure
476 * under certain circumstances. Typical phenomenon of the
477 * issue would be unexpected sequence number encountered in
480 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
481 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
482 MASTER_CHIP_REV_SHIFT;
484 device_printf(dev, "PCI device revision : 0x%04x\n",
486 device_printf(dev, "Chip id/revision : 0x%04x\n",
489 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
490 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
492 * Uninitialized hardware returns an invalid chip id/revision
493 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
495 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
496 rxf_len == 0xFFFFFFF) {
497 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
498 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
503 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
505 /* Allocate IRQ resources. */
506 msixc = pci_msix_count(dev);
507 msic = pci_msi_count(dev);
509 device_printf(dev, "MSIX count : %d\n", msixc);
510 device_printf(dev, "MSI count : %d\n", msic);
513 /* Prefer MSIX over MSI. */
514 if (msix_disable == 0 || msi_disable == 0) {
515 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
516 pci_alloc_msix(dev, &msixc) == 0) {
517 if (msic == ALE_MSIX_MESSAGES) {
518 device_printf(dev, "Using %d MSIX messages.\n",
520 sc->ale_flags |= ALE_FLAG_MSIX;
521 sc->ale_irq_spec = ale_irq_spec_msix;
523 pci_release_msi(dev);
525 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
526 msic == ALE_MSI_MESSAGES &&
527 pci_alloc_msi(dev, &msic) == 0) {
528 if (msic == ALE_MSI_MESSAGES) {
529 device_printf(dev, "Using %d MSI messages.\n",
531 sc->ale_flags |= ALE_FLAG_MSI;
532 sc->ale_irq_spec = ale_irq_spec_msi;
534 pci_release_msi(dev);
538 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
540 device_printf(dev, "cannot allocate IRQ resources.\n");
544 /* Get DMA parameters from PCIe device control register. */
545 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
546 sc->ale_flags |= ALE_FLAG_PCIE;
547 burst = pci_read_config(dev, i + 0x08, 2);
548 /* Max read request size. */
549 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
550 DMA_CFG_RD_BURST_SHIFT;
551 /* Max payload size. */
552 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
553 DMA_CFG_WR_BURST_SHIFT;
555 device_printf(dev, "Read request size : %d bytes.\n",
556 128 << ((burst >> 12) & 0x07));
557 device_printf(dev, "TLP payload size : %d bytes.\n",
558 128 << ((burst >> 5) & 0x07));
561 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
562 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
565 /* Create device sysctl node. */
568 if ((error = ale_dma_alloc(sc) != 0))
571 /* Load station address. */
574 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
576 device_printf(dev, "cannot allocate ifnet structure.\n");
582 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
583 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
584 ifp->if_ioctl = ale_ioctl;
585 ifp->if_start = ale_start;
586 ifp->if_init = ale_init;
587 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
588 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
589 IFQ_SET_READY(&ifp->if_snd);
590 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
591 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
592 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
593 sc->ale_flags |= ALE_FLAG_PMCAP;
594 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
596 ifp->if_capenable = ifp->if_capabilities;
598 /* Set up MII bus. */
599 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
600 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
603 device_printf(dev, "attaching PHYs failed\n");
607 ether_ifattach(ifp, sc->ale_eaddr);
609 /* VLAN capability setup. */
610 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
611 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
612 ifp->if_capenable = ifp->if_capabilities;
614 * Even though controllers supported by ale(3) have Rx checksum
615 * offload bug the workaround for fragmented frames seemed to
616 * work so far. However it seems Rx checksum offload does not
617 * work under certain conditions. So disable Rx checksum offload
618 * until I find more clue about it but allow users to override it.
620 ifp->if_capenable &= ~IFCAP_RXCSUM;
622 /* Tell the upper layer(s) we support long frames. */
623 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
625 /* Create local taskq. */
626 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
627 taskqueue_thread_enqueue, &sc->ale_tq);
628 if (sc->ale_tq == NULL) {
629 device_printf(dev, "could not create taskqueue.\n");
634 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
635 device_get_nameunit(sc->ale_dev));
637 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
638 msic = ALE_MSIX_MESSAGES;
639 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
640 msic = ALE_MSI_MESSAGES;
643 for (i = 0; i < msic; i++) {
644 error = bus_setup_intr(dev, sc->ale_irq[i],
645 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
646 &sc->ale_intrhand[i]);
651 device_printf(dev, "could not set up interrupt handler.\n");
652 taskqueue_free(sc->ale_tq);
666 ale_detach(device_t dev)
668 struct ale_softc *sc;
672 sc = device_get_softc(dev);
675 if (device_is_attached(dev)) {
680 callout_drain(&sc->ale_tick_ch);
681 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
682 taskqueue_drain(taskqueue_swi, &sc->ale_link_task);
685 if (sc->ale_tq != NULL) {
686 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
687 taskqueue_free(sc->ale_tq);
691 if (sc->ale_miibus != NULL) {
692 device_delete_child(dev, sc->ale_miibus);
693 sc->ale_miibus = NULL;
695 bus_generic_detach(dev);
703 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
704 msic = ALE_MSIX_MESSAGES;
705 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
706 msic = ALE_MSI_MESSAGES;
709 for (i = 0; i < msic; i++) {
710 if (sc->ale_intrhand[i] != NULL) {
711 bus_teardown_intr(dev, sc->ale_irq[i],
712 sc->ale_intrhand[i]);
713 sc->ale_intrhand[i] = NULL;
717 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
718 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
719 pci_release_msi(dev);
720 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
721 mtx_destroy(&sc->ale_mtx);
726 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
727 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
729 #if __FreeBSD_version >= 900030
730 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
731 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
732 #elif __FreeBSD_version > 800000
733 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
734 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
736 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
737 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
741 ale_sysctl_node(struct ale_softc *sc)
743 struct sysctl_ctx_list *ctx;
744 struct sysctl_oid_list *child, *parent;
745 struct sysctl_oid *tree;
746 struct ale_hw_stats *stats;
749 stats = &sc->ale_stats;
750 ctx = device_get_sysctl_ctx(sc->ale_dev);
751 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
753 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
754 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
755 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
756 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
757 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
758 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
759 /* Pull in device tunables. */
760 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
761 error = resource_int_value(device_get_name(sc->ale_dev),
762 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
764 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
765 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
766 device_printf(sc->ale_dev, "int_rx_mod value out of "
767 "range; using default: %d\n",
768 ALE_IM_RX_TIMER_DEFAULT);
769 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
772 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
773 error = resource_int_value(device_get_name(sc->ale_dev),
774 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
776 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
777 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
778 device_printf(sc->ale_dev, "int_tx_mod value out of "
779 "range; using default: %d\n",
780 ALE_IM_TX_TIMER_DEFAULT);
781 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
784 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
785 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0,
786 sysctl_hw_ale_proc_limit, "I",
787 "max number of Rx events to process");
788 /* Pull in device tunables. */
789 sc->ale_process_limit = ALE_PROC_DEFAULT;
790 error = resource_int_value(device_get_name(sc->ale_dev),
791 device_get_unit(sc->ale_dev), "process_limit",
792 &sc->ale_process_limit);
794 if (sc->ale_process_limit < ALE_PROC_MIN ||
795 sc->ale_process_limit > ALE_PROC_MAX) {
796 device_printf(sc->ale_dev,
797 "process_limit value out of range; "
798 "using default: %d\n", ALE_PROC_DEFAULT);
799 sc->ale_process_limit = ALE_PROC_DEFAULT;
803 /* Misc statistics. */
804 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
805 &stats->reset_brk_seq,
806 "Controller resets due to broken Rx sequnce number");
808 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
809 NULL, "ATE statistics");
810 parent = SYSCTL_CHILDREN(tree);
813 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
814 NULL, "Rx MAC statistics");
815 child = SYSCTL_CHILDREN(tree);
816 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
817 &stats->rx_frames, "Good frames");
818 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
819 &stats->rx_bcast_frames, "Good broadcast frames");
820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
821 &stats->rx_mcast_frames, "Good multicast frames");
822 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
823 &stats->rx_pause_frames, "Pause control frames");
824 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
825 &stats->rx_control_frames, "Control frames");
826 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
827 &stats->rx_crcerrs, "CRC errors");
828 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
829 &stats->rx_lenerrs, "Frames with length mismatched");
830 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
831 &stats->rx_bytes, "Good octets");
832 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
833 &stats->rx_bcast_bytes, "Good broadcast octets");
834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
835 &stats->rx_mcast_bytes, "Good multicast octets");
836 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
837 &stats->rx_runts, "Too short frames");
838 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
839 &stats->rx_fragments, "Fragmented frames");
840 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
841 &stats->rx_pkts_64, "64 bytes frames");
842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
843 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
845 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
847 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
849 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
851 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
853 &stats->rx_pkts_1519_max, "1519 to max frames");
854 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
855 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
856 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
857 &stats->rx_fifo_oflows, "FIFO overflows");
858 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
859 &stats->rx_rrs_errs, "Return status write-back errors");
860 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
861 &stats->rx_alignerrs, "Alignment errors");
862 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
863 &stats->rx_pkts_filtered,
864 "Frames dropped due to address filtering");
867 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
868 NULL, "Tx MAC statistics");
869 child = SYSCTL_CHILDREN(tree);
870 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
871 &stats->tx_frames, "Good frames");
872 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
873 &stats->tx_bcast_frames, "Good broadcast frames");
874 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
875 &stats->tx_mcast_frames, "Good multicast frames");
876 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
877 &stats->tx_pause_frames, "Pause control frames");
878 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
879 &stats->tx_control_frames, "Control frames");
880 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
881 &stats->tx_excess_defer, "Frames with excessive derferrals");
882 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
883 &stats->tx_excess_defer, "Frames with derferrals");
884 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
885 &stats->tx_bytes, "Good octets");
886 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
887 &stats->tx_bcast_bytes, "Good broadcast octets");
888 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
889 &stats->tx_mcast_bytes, "Good multicast octets");
890 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
891 &stats->tx_pkts_64, "64 bytes frames");
892 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
893 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
894 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
895 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
896 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
897 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
898 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
899 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
901 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
903 &stats->tx_pkts_1519_max, "1519 to max frames");
904 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
905 &stats->tx_single_colls, "Single collisions");
906 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
907 &stats->tx_multi_colls, "Multiple collisions");
908 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
909 &stats->tx_late_colls, "Late collisions");
910 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
911 &stats->tx_excess_colls, "Excessive collisions");
912 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
913 &stats->tx_abort, "Aborted frames due to Excessive collisions");
914 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
915 &stats->tx_underrun, "FIFO underruns");
916 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
917 &stats->tx_desc_underrun, "Descriptor write-back errors");
918 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
919 &stats->tx_lenerrs, "Frames with length mismatched");
920 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
921 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
924 #undef ALE_SYSCTL_STAT_ADD32
925 #undef ALE_SYSCTL_STAT_ADD64
927 struct ale_dmamap_arg {
928 bus_addr_t ale_busaddr;
932 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
934 struct ale_dmamap_arg *ctx;
939 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
941 ctx = (struct ale_dmamap_arg *)arg;
942 ctx->ale_busaddr = segs[0].ds_addr;
946 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
947 * which specifies high address region of DMA blocks. Therefore these
948 * blocks should have the same high address of given 4GB address
949 * space(i.e. crossing 4GB boundary is not allowed).
952 ale_check_boundary(struct ale_softc *sc)
954 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
955 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
957 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
959 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
961 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
962 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
963 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
964 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
966 if ((ALE_ADDR_HI(tx_ring_end) !=
967 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
968 (ALE_ADDR_HI(rx_page_end[0]) !=
969 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
970 (ALE_ADDR_HI(rx_page_end[1]) !=
971 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
972 (ALE_ADDR_HI(tx_cmb_end) !=
973 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
974 (ALE_ADDR_HI(rx_cmb_end[0]) !=
975 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
976 (ALE_ADDR_HI(rx_cmb_end[1]) !=
977 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
980 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
981 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
982 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
983 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
984 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
991 ale_dma_alloc(struct ale_softc *sc)
993 struct ale_txdesc *txd;
995 struct ale_dmamap_arg ctx;
996 int error, guard_size, i;
998 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
999 guard_size = ALE_JUMBO_FRAMELEN;
1001 guard_size = ALE_MAX_FRAMELEN;
1002 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1004 lowaddr = BUS_SPACE_MAXADDR;
1006 /* Create parent DMA tag. */
1007 error = bus_dma_tag_create(
1008 bus_get_dma_tag(sc->ale_dev), /* parent */
1009 1, 0, /* alignment, boundary */
1010 lowaddr, /* lowaddr */
1011 BUS_SPACE_MAXADDR, /* highaddr */
1012 NULL, NULL, /* filter, filterarg */
1013 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1015 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1017 NULL, NULL, /* lockfunc, lockarg */
1018 &sc->ale_cdata.ale_parent_tag);
1020 device_printf(sc->ale_dev,
1021 "could not create parent DMA tag.\n");
1025 /* Create DMA tag for Tx descriptor ring. */
1026 error = bus_dma_tag_create(
1027 sc->ale_cdata.ale_parent_tag, /* parent */
1028 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1029 BUS_SPACE_MAXADDR, /* lowaddr */
1030 BUS_SPACE_MAXADDR, /* highaddr */
1031 NULL, NULL, /* filter, filterarg */
1032 ALE_TX_RING_SZ, /* maxsize */
1034 ALE_TX_RING_SZ, /* maxsegsize */
1036 NULL, NULL, /* lockfunc, lockarg */
1037 &sc->ale_cdata.ale_tx_ring_tag);
1039 device_printf(sc->ale_dev,
1040 "could not create Tx ring DMA tag.\n");
1044 /* Create DMA tag for Rx pages. */
1045 for (i = 0; i < ALE_RX_PAGES; i++) {
1046 error = bus_dma_tag_create(
1047 sc->ale_cdata.ale_parent_tag, /* parent */
1048 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1049 BUS_SPACE_MAXADDR, /* lowaddr */
1050 BUS_SPACE_MAXADDR, /* highaddr */
1051 NULL, NULL, /* filter, filterarg */
1052 sc->ale_pagesize, /* maxsize */
1054 sc->ale_pagesize, /* maxsegsize */
1056 NULL, NULL, /* lockfunc, lockarg */
1057 &sc->ale_cdata.ale_rx_page[i].page_tag);
1059 device_printf(sc->ale_dev,
1060 "could not create Rx page %d DMA tag.\n", i);
1065 /* Create DMA tag for Tx coalescing message block. */
1066 error = bus_dma_tag_create(
1067 sc->ale_cdata.ale_parent_tag, /* parent */
1068 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1069 BUS_SPACE_MAXADDR, /* lowaddr */
1070 BUS_SPACE_MAXADDR, /* highaddr */
1071 NULL, NULL, /* filter, filterarg */
1072 ALE_TX_CMB_SZ, /* maxsize */
1074 ALE_TX_CMB_SZ, /* maxsegsize */
1076 NULL, NULL, /* lockfunc, lockarg */
1077 &sc->ale_cdata.ale_tx_cmb_tag);
1079 device_printf(sc->ale_dev,
1080 "could not create Tx CMB DMA tag.\n");
1084 /* Create DMA tag for Rx coalescing message block. */
1085 for (i = 0; i < ALE_RX_PAGES; i++) {
1086 error = bus_dma_tag_create(
1087 sc->ale_cdata.ale_parent_tag, /* parent */
1088 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1089 BUS_SPACE_MAXADDR, /* lowaddr */
1090 BUS_SPACE_MAXADDR, /* highaddr */
1091 NULL, NULL, /* filter, filterarg */
1092 ALE_RX_CMB_SZ, /* maxsize */
1094 ALE_RX_CMB_SZ, /* maxsegsize */
1096 NULL, NULL, /* lockfunc, lockarg */
1097 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1099 device_printf(sc->ale_dev,
1100 "could not create Rx page %d CMB DMA tag.\n", i);
1105 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1106 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1107 (void **)&sc->ale_cdata.ale_tx_ring,
1108 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1109 &sc->ale_cdata.ale_tx_ring_map);
1111 device_printf(sc->ale_dev,
1112 "could not allocate DMA'able memory for Tx ring.\n");
1115 ctx.ale_busaddr = 0;
1116 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1117 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1118 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1119 if (error != 0 || ctx.ale_busaddr == 0) {
1120 device_printf(sc->ale_dev,
1121 "could not load DMA'able memory for Tx ring.\n");
1124 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1127 for (i = 0; i < ALE_RX_PAGES; i++) {
1128 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1129 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1130 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1131 &sc->ale_cdata.ale_rx_page[i].page_map);
1133 device_printf(sc->ale_dev,
1134 "could not allocate DMA'able memory for "
1135 "Rx page %d.\n", i);
1138 ctx.ale_busaddr = 0;
1139 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1140 sc->ale_cdata.ale_rx_page[i].page_map,
1141 sc->ale_cdata.ale_rx_page[i].page_addr,
1142 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1143 if (error != 0 || ctx.ale_busaddr == 0) {
1144 device_printf(sc->ale_dev,
1145 "could not load DMA'able memory for "
1146 "Rx page %d.\n", i);
1149 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1153 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1154 (void **)&sc->ale_cdata.ale_tx_cmb,
1155 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1156 &sc->ale_cdata.ale_tx_cmb_map);
1158 device_printf(sc->ale_dev,
1159 "could not allocate DMA'able memory for Tx CMB.\n");
1162 ctx.ale_busaddr = 0;
1163 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1164 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1165 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1166 if (error != 0 || ctx.ale_busaddr == 0) {
1167 device_printf(sc->ale_dev,
1168 "could not load DMA'able memory for Tx CMB.\n");
1171 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1174 for (i = 0; i < ALE_RX_PAGES; i++) {
1175 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1176 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1177 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1178 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1180 device_printf(sc->ale_dev, "could not allocate "
1181 "DMA'able memory for Rx page %d CMB.\n", i);
1184 ctx.ale_busaddr = 0;
1185 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1186 sc->ale_cdata.ale_rx_page[i].cmb_map,
1187 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1188 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1189 if (error != 0 || ctx.ale_busaddr == 0) {
1190 device_printf(sc->ale_dev, "could not load DMA'able "
1191 "memory for Rx page %d CMB.\n", i);
1194 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1198 * Tx descriptors/RXF0/CMB DMA blocks share the same
1199 * high address region of 64bit DMA address space.
1201 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1202 (error = ale_check_boundary(sc)) != 0) {
1203 device_printf(sc->ale_dev, "4GB boundary crossed, "
1204 "switching to 32bit DMA addressing mode.\n");
1207 * Limit max allowable DMA address space to 32bit
1210 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1215 * Create Tx buffer parent tag.
1216 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1217 * needs separate parent DMA tag as parent DMA address space
1218 * could be restricted to be within 32bit address space by
1219 * 4GB boundary crossing.
1221 error = bus_dma_tag_create(
1222 bus_get_dma_tag(sc->ale_dev), /* parent */
1223 1, 0, /* alignment, boundary */
1224 BUS_SPACE_MAXADDR, /* lowaddr */
1225 BUS_SPACE_MAXADDR, /* highaddr */
1226 NULL, NULL, /* filter, filterarg */
1227 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1229 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1231 NULL, NULL, /* lockfunc, lockarg */
1232 &sc->ale_cdata.ale_buffer_tag);
1234 device_printf(sc->ale_dev,
1235 "could not create parent buffer DMA tag.\n");
1239 /* Create DMA tag for Tx buffers. */
1240 error = bus_dma_tag_create(
1241 sc->ale_cdata.ale_buffer_tag, /* parent */
1242 1, 0, /* alignment, boundary */
1243 BUS_SPACE_MAXADDR, /* lowaddr */
1244 BUS_SPACE_MAXADDR, /* highaddr */
1245 NULL, NULL, /* filter, filterarg */
1246 ALE_TSO_MAXSIZE, /* maxsize */
1247 ALE_MAXTXSEGS, /* nsegments */
1248 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1250 NULL, NULL, /* lockfunc, lockarg */
1251 &sc->ale_cdata.ale_tx_tag);
1253 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1257 /* Create DMA maps for Tx buffers. */
1258 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1259 txd = &sc->ale_cdata.ale_txdesc[i];
1261 txd->tx_dmamap = NULL;
1262 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1265 device_printf(sc->ale_dev,
1266 "could not create Tx dmamap.\n");
1276 ale_dma_free(struct ale_softc *sc)
1278 struct ale_txdesc *txd;
1282 if (sc->ale_cdata.ale_tx_tag != NULL) {
1283 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1284 txd = &sc->ale_cdata.ale_txdesc[i];
1285 if (txd->tx_dmamap != NULL) {
1286 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1288 txd->tx_dmamap = NULL;
1291 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1292 sc->ale_cdata.ale_tx_tag = NULL;
1294 /* Tx descriptor ring. */
1295 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1296 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1297 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1298 sc->ale_cdata.ale_tx_ring_map);
1299 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1300 sc->ale_cdata.ale_tx_ring != NULL)
1301 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1302 sc->ale_cdata.ale_tx_ring,
1303 sc->ale_cdata.ale_tx_ring_map);
1304 sc->ale_cdata.ale_tx_ring = NULL;
1305 sc->ale_cdata.ale_tx_ring_map = NULL;
1306 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1307 sc->ale_cdata.ale_tx_ring_tag = NULL;
1309 /* Rx page block. */
1310 for (i = 0; i < ALE_RX_PAGES; i++) {
1311 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1312 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1314 sc->ale_cdata.ale_rx_page[i].page_tag,
1315 sc->ale_cdata.ale_rx_page[i].page_map);
1316 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1317 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1319 sc->ale_cdata.ale_rx_page[i].page_tag,
1320 sc->ale_cdata.ale_rx_page[i].page_addr,
1321 sc->ale_cdata.ale_rx_page[i].page_map);
1322 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1323 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1324 bus_dma_tag_destroy(
1325 sc->ale_cdata.ale_rx_page[i].page_tag);
1326 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1330 for (i = 0; i < ALE_RX_PAGES; i++) {
1331 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1332 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1334 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1335 sc->ale_cdata.ale_rx_page[i].cmb_map);
1336 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1337 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1339 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1340 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1341 sc->ale_cdata.ale_rx_page[i].cmb_map);
1342 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1343 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1344 bus_dma_tag_destroy(
1345 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1346 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1350 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1351 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1352 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1353 sc->ale_cdata.ale_tx_cmb_map);
1354 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1355 sc->ale_cdata.ale_tx_cmb != NULL)
1356 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1357 sc->ale_cdata.ale_tx_cmb,
1358 sc->ale_cdata.ale_tx_cmb_map);
1359 sc->ale_cdata.ale_tx_cmb = NULL;
1360 sc->ale_cdata.ale_tx_cmb_map = NULL;
1361 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1362 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1364 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1365 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1366 sc->ale_cdata.ale_buffer_tag = NULL;
1368 if (sc->ale_cdata.ale_parent_tag != NULL) {
1369 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1370 sc->ale_cdata.ale_parent_tag = NULL;
1375 ale_shutdown(device_t dev)
1378 return (ale_suspend(dev));
1382 * Note, this driver resets the link speed to 10/100Mbps by
1383 * restarting auto-negotiation in suspend/shutdown phase but we
1384 * don't know whether that auto-negotiation would succeed or not
1385 * as driver has no control after powering off/suspend operation.
1386 * If the renegotiation fail WOL may not work. Running at 1Gbps
1387 * will draw more power than 375mA at 3.3V which is specified in
1388 * PCI specification and that would result in complete
1389 * shutdowning power to ethernet controller.
1392 * Save current negotiated media speed/duplex/flow-control to
1393 * softc and restore the same link again after resuming. PHY
1394 * handling such as power down/resetting to 100Mbps may be better
1395 * handled in suspend method in phy driver.
1398 ale_setlinkspeed(struct ale_softc *sc)
1400 struct mii_data *mii;
1403 mii = device_get_softc(sc->ale_miibus);
1406 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1407 (IFM_ACTIVE | IFM_AVALID)) {
1408 switch IFM_SUBTYPE(mii->mii_media_active) {
1419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1421 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1423 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1427 * Poll link state until ale(4) get a 10/100Mbps link.
1429 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1431 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1432 == (IFM_ACTIVE | IFM_AVALID)) {
1433 switch (IFM_SUBTYPE(
1434 mii->mii_media_active)) {
1444 pause("alelnk", hz);
1447 if (i == MII_ANEGTICKS_GIGE)
1448 device_printf(sc->ale_dev,
1449 "establishing a link failed, WOL may not work!");
1452 * No link, force MAC to have 100Mbps, full-duplex link.
1453 * This is the last resort and may/may not work.
1455 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1456 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1461 ale_setwol(struct ale_softc *sc)
1468 ALE_LOCK_ASSERT(sc);
1470 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1472 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1473 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1474 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1475 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1476 /* Force PHY power down. */
1477 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1478 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1479 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1480 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1481 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1486 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1487 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1488 ale_setlinkspeed(sc);
1492 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1493 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1494 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1495 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1496 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1498 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1499 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1500 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1501 reg |= MAC_CFG_RX_ENB;
1502 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1504 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1505 /* WOL disabled, PHY power down. */
1506 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1507 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1508 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1509 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1510 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1511 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1512 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1513 GPHY_CTRL_PWDOWN_HW);
1516 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1517 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1518 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1519 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1520 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1524 ale_suspend(device_t dev)
1526 struct ale_softc *sc;
1528 sc = device_get_softc(dev);
1539 ale_resume(device_t dev)
1541 struct ale_softc *sc;
1546 sc = device_get_softc(dev);
1549 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1550 /* Disable PME and clear PME status. */
1551 pmstat = pci_read_config(sc->ale_dev,
1552 pmc + PCIR_POWER_STATUS, 2);
1553 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1554 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1555 pci_write_config(sc->ale_dev,
1556 pmc + PCIR_POWER_STATUS, pmstat, 2);
1562 if ((ifp->if_flags & IFF_UP) != 0) {
1563 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1564 ale_init_locked(sc);
1572 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1574 struct ale_txdesc *txd, *txd_last;
1575 struct tx_desc *desc;
1579 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1581 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1582 int error, i, nsegs, prod, si;
1584 ALE_LOCK_ASSERT(sc);
1586 M_ASSERTPKTHDR((*m_head));
1593 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1595 * AR81xx requires offset of TCP/UDP payload in its Tx
1596 * descriptor to perform hardware Tx checksum offload.
1597 * Additionally, TSO requires IP/TCP header size and
1598 * modification of IP/TCP header in order to make TSO
1599 * engine work. This kind of operation takes many CPU
1600 * cycles on FreeBSD so fast host CPU is required to
1601 * get smooth TSO performance.
1603 struct ether_header *eh;
1605 if (M_WRITABLE(m) == 0) {
1606 /* Get a writable copy. */
1607 m = m_dup(*m_head, M_DONTWAIT);
1608 /* Release original mbufs. */
1618 * Buggy-controller requires 4 byte aligned Tx buffer
1619 * to make custom checksum offload work.
1621 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1622 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1623 (mtod(m, intptr_t) & 3) != 0) {
1624 m = m_defrag(*m_head, M_DONTWAIT);
1632 ip_off = sizeof(struct ether_header);
1633 m = m_pullup(m, ip_off);
1638 eh = mtod(m, struct ether_header *);
1640 * Check if hardware VLAN insertion is off.
1641 * Additional check for LLC/SNAP frame?
1643 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1644 ip_off = sizeof(struct ether_vlan_header);
1645 m = m_pullup(m, ip_off);
1651 m = m_pullup(m, ip_off + sizeof(struct ip));
1656 ip = (struct ip *)(mtod(m, char *) + ip_off);
1657 poff = ip_off + (ip->ip_hl << 2);
1658 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1661 * AR81xx requires the first descriptor should
1662 * not include any TCP playload for TSO case.
1663 * (i.e. ethernet header + IP + TCP header only)
1664 * m_pullup(9) above will ensure this too.
1665 * However it's not correct if the first mbuf
1666 * of the chain does not use cluster.
1668 m = m_pullup(m, poff + sizeof(struct tcphdr));
1673 ip = (struct ip *)(mtod(m, char *) + ip_off);
1674 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1675 m = m_pullup(m, poff + (tcp->th_off << 2));
1681 * AR81xx requires IP/TCP header size and offset as
1682 * well as TCP pseudo checksum which complicates
1683 * TSO configuration. I guess this comes from the
1684 * adherence to Microsoft NDIS Large Send
1685 * specification which requires insertion of
1686 * pseudo checksum by upper stack. The pseudo
1687 * checksum that NDIS refers to doesn't include
1688 * TCP payload length so ale(4) should recompute
1689 * the pseudo checksum here. Hopefully this wouldn't
1690 * be much burden on modern CPUs.
1691 * Reset IP checksum and recompute TCP pseudo
1692 * checksum as NDIS specification said.
1695 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1696 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1701 si = prod = sc->ale_cdata.ale_tx_prod;
1702 txd = &sc->ale_cdata.ale_txdesc[prod];
1704 map = txd->tx_dmamap;
1706 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1707 *m_head, txsegs, &nsegs, 0);
1708 if (error == EFBIG) {
1709 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS);
1716 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1717 *m_head, txsegs, &nsegs, 0);
1723 } else if (error != 0)
1731 /* Check descriptor overrun. */
1732 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1733 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1736 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1739 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1740 /* Request TSO and set MSS. */
1741 cflags |= ALE_TD_TSO;
1742 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1743 /* Set IP/TCP header size. */
1744 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1745 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1746 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1748 * AR81xx supports Tx custom checksum offload feature
1749 * that offloads single 16bit checksum computation.
1750 * So you can choose one among IP, TCP and UDP.
1751 * Normally driver sets checksum start/insertion
1752 * position from the information of TCP/UDP frame as
1753 * TCP/UDP checksum takes more time than that of IP.
1754 * However it seems that custom checksum offload
1755 * requires 4 bytes aligned Tx buffers due to hardware
1757 * AR81xx also supports explicit Tx checksum computation
1758 * if it is told that the size of IP header and TCP
1759 * header(for UDP, the header size does not matter
1760 * because it's fixed length). However with this scheme
1761 * TSO does not work so you have to choose one either
1762 * TSO or explicit Tx checksum offload. I chosen TSO
1763 * plus custom checksum offload with work-around which
1764 * will cover most common usage for this consumer
1765 * ethernet controller. The work-around takes a lot of
1766 * CPU cycles if Tx buffer is not aligned on 4 bytes
1769 cflags |= ALE_TD_CXSUM;
1770 /* Set checksum start offset. */
1771 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1772 /* Set checksum insertion position of TCP/UDP. */
1773 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1774 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1777 /* Configure VLAN hardware tag insertion. */
1778 if ((m->m_flags & M_VLANTAG) != 0) {
1779 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1780 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1781 cflags |= ALE_TD_INSERT_VLAN_TAG;
1785 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1787 * Make sure the first fragment contains
1788 * only ethernet and IP/TCP header with options.
1790 hdrlen = poff + (tcp->th_off << 2);
1791 desc = &sc->ale_cdata.ale_tx_ring[prod];
1792 desc->addr = htole64(txsegs[i].ds_addr);
1793 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1794 desc->flags = htole32(cflags);
1795 sc->ale_cdata.ale_tx_cnt++;
1796 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1797 if (m->m_len - hdrlen > 0) {
1798 /* Handle remaining payload of the first fragment. */
1799 desc = &sc->ale_cdata.ale_tx_ring[prod];
1800 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1801 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1803 desc->flags = htole32(cflags);
1804 sc->ale_cdata.ale_tx_cnt++;
1805 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1809 for (; i < nsegs; i++) {
1810 desc = &sc->ale_cdata.ale_tx_ring[prod];
1811 desc->addr = htole64(txsegs[i].ds_addr);
1812 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1813 desc->flags = htole32(cflags);
1814 sc->ale_cdata.ale_tx_cnt++;
1815 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1817 /* Update producer index. */
1818 sc->ale_cdata.ale_tx_prod = prod;
1819 /* Set TSO header on the first descriptor. */
1820 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1821 desc = &sc->ale_cdata.ale_tx_ring[si];
1822 desc->flags |= htole32(ALE_TD_TSO_HDR);
1825 /* Finally set EOP on the last descriptor. */
1826 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1827 desc = &sc->ale_cdata.ale_tx_ring[prod];
1828 desc->flags |= htole32(ALE_TD_EOP);
1830 /* Swap dmamap of the first and the last. */
1831 txd = &sc->ale_cdata.ale_txdesc[prod];
1832 map = txd_last->tx_dmamap;
1833 txd_last->tx_dmamap = txd->tx_dmamap;
1834 txd->tx_dmamap = map;
1837 /* Sync descriptors. */
1838 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1839 sc->ale_cdata.ale_tx_ring_map,
1840 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1846 ale_start(struct ifnet *ifp)
1848 struct ale_softc *sc;
1852 ale_start_locked(ifp);
1857 ale_start_locked(struct ifnet *ifp)
1859 struct ale_softc *sc;
1860 struct mbuf *m_head;
1865 ALE_LOCK_ASSERT(sc);
1867 /* Reclaim transmitted frames. */
1868 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1871 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1872 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1875 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1876 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1880 * Pack the data into the transmit ring. If we
1881 * don't have room, set the OACTIVE flag and wait
1882 * for the NIC to drain the ring.
1884 if (ale_encap(sc, &m_head)) {
1887 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1888 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1894 * If there's a BPF listener, bounce a copy of this frame
1897 ETHER_BPF_MTAP(ifp, m_head);
1902 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1903 sc->ale_cdata.ale_tx_prod);
1904 /* Set a timeout in case the chip goes out to lunch. */
1905 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1910 ale_watchdog(struct ale_softc *sc)
1914 ALE_LOCK_ASSERT(sc);
1916 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1920 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1921 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1923 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1924 ale_init_locked(sc);
1927 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1929 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1930 ale_init_locked(sc);
1931 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1932 ale_start_locked(ifp);
1936 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1938 struct ale_softc *sc;
1940 struct mii_data *mii;
1944 ifr = (struct ifreq *)data;
1948 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1949 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1950 ifr->ifr_mtu > ETHERMTU))
1952 else if (ifp->if_mtu != ifr->ifr_mtu) {
1954 ifp->if_mtu = ifr->ifr_mtu;
1955 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1956 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1957 ale_init_locked(sc);
1964 if ((ifp->if_flags & IFF_UP) != 0) {
1965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1966 if (((ifp->if_flags ^ sc->ale_if_flags)
1967 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1970 ale_init_locked(sc);
1973 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1976 sc->ale_if_flags = ifp->if_flags;
1982 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1988 mii = device_get_softc(sc->ale_miibus);
1989 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1993 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1994 if ((mask & IFCAP_TXCSUM) != 0 &&
1995 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1996 ifp->if_capenable ^= IFCAP_TXCSUM;
1997 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1998 ifp->if_hwassist |= ALE_CSUM_FEATURES;
2000 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2002 if ((mask & IFCAP_RXCSUM) != 0 &&
2003 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2004 ifp->if_capenable ^= IFCAP_RXCSUM;
2005 if ((mask & IFCAP_TSO4) != 0 &&
2006 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2007 ifp->if_capenable ^= IFCAP_TSO4;
2008 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2009 ifp->if_hwassist |= CSUM_TSO;
2011 ifp->if_hwassist &= ~CSUM_TSO;
2014 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2015 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2016 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2017 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2018 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2019 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2020 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2021 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2022 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2023 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2024 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2025 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2026 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2027 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2028 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2029 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2030 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2034 VLAN_CAPABILITIES(ifp);
2037 error = ether_ioctl(ifp, cmd, data);
2045 ale_mac_config(struct ale_softc *sc)
2047 struct mii_data *mii;
2050 ALE_LOCK_ASSERT(sc);
2052 mii = device_get_softc(sc->ale_miibus);
2053 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2054 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2055 MAC_CFG_SPEED_MASK);
2056 /* Reprogram MAC with resolved speed/duplex. */
2057 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2060 reg |= MAC_CFG_SPEED_10_100;
2063 reg |= MAC_CFG_SPEED_1000;
2066 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2067 reg |= MAC_CFG_FULL_DUPLEX;
2069 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2070 reg |= MAC_CFG_TX_FC;
2071 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2072 reg |= MAC_CFG_RX_FC;
2075 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2079 ale_link_task(void *arg, int pending)
2081 struct ale_softc *sc;
2082 struct mii_data *mii;
2086 sc = (struct ale_softc *)arg;
2089 mii = device_get_softc(sc->ale_miibus);
2091 if (mii == NULL || ifp == NULL ||
2092 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2097 sc->ale_flags &= ~ALE_FLAG_LINK;
2098 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
2099 (IFM_ACTIVE | IFM_AVALID)) {
2100 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2103 sc->ale_flags |= ALE_FLAG_LINK;
2106 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
2107 sc->ale_flags |= ALE_FLAG_LINK;
2114 /* Stop Rx/Tx MACs. */
2117 /* Program MACs with resolved speed/duplex/flow-control. */
2118 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
2120 /* Reenable Tx/Rx MACs. */
2121 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2122 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2123 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2130 ale_stats_clear(struct ale_softc *sc)
2136 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2137 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2138 i += sizeof(uint32_t);
2140 /* Read Tx statistics. */
2141 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2142 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2143 i += sizeof(uint32_t);
2148 ale_stats_update(struct ale_softc *sc)
2150 struct ale_hw_stats *stat;
2151 struct smb sb, *smb;
2156 ALE_LOCK_ASSERT(sc);
2159 stat = &sc->ale_stats;
2162 /* Read Rx statistics. */
2163 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2164 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2165 i += sizeof(uint32_t);
2167 /* Read Tx statistics. */
2168 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2169 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2170 i += sizeof(uint32_t);
2174 stat->rx_frames += smb->rx_frames;
2175 stat->rx_bcast_frames += smb->rx_bcast_frames;
2176 stat->rx_mcast_frames += smb->rx_mcast_frames;
2177 stat->rx_pause_frames += smb->rx_pause_frames;
2178 stat->rx_control_frames += smb->rx_control_frames;
2179 stat->rx_crcerrs += smb->rx_crcerrs;
2180 stat->rx_lenerrs += smb->rx_lenerrs;
2181 stat->rx_bytes += smb->rx_bytes;
2182 stat->rx_runts += smb->rx_runts;
2183 stat->rx_fragments += smb->rx_fragments;
2184 stat->rx_pkts_64 += smb->rx_pkts_64;
2185 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2186 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2187 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2188 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2189 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2190 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2191 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2192 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2193 stat->rx_rrs_errs += smb->rx_rrs_errs;
2194 stat->rx_alignerrs += smb->rx_alignerrs;
2195 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2196 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2197 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2200 stat->tx_frames += smb->tx_frames;
2201 stat->tx_bcast_frames += smb->tx_bcast_frames;
2202 stat->tx_mcast_frames += smb->tx_mcast_frames;
2203 stat->tx_pause_frames += smb->tx_pause_frames;
2204 stat->tx_excess_defer += smb->tx_excess_defer;
2205 stat->tx_control_frames += smb->tx_control_frames;
2206 stat->tx_deferred += smb->tx_deferred;
2207 stat->tx_bytes += smb->tx_bytes;
2208 stat->tx_pkts_64 += smb->tx_pkts_64;
2209 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2210 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2211 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2212 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2213 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2214 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2215 stat->tx_single_colls += smb->tx_single_colls;
2216 stat->tx_multi_colls += smb->tx_multi_colls;
2217 stat->tx_late_colls += smb->tx_late_colls;
2218 stat->tx_excess_colls += smb->tx_excess_colls;
2219 stat->tx_abort += smb->tx_abort;
2220 stat->tx_underrun += smb->tx_underrun;
2221 stat->tx_desc_underrun += smb->tx_desc_underrun;
2222 stat->tx_lenerrs += smb->tx_lenerrs;
2223 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2224 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2225 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2227 /* Update counters in ifnet. */
2228 ifp->if_opackets += smb->tx_frames;
2230 ifp->if_collisions += smb->tx_single_colls +
2231 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2232 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
2236 * tx_pkts_truncated counter looks suspicious. It constantly
2237 * increments with no sign of Tx errors. This may indicate
2238 * the counter name is not correct one so I've removed the
2239 * counter in output errors.
2241 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
2244 ifp->if_ipackets += smb->rx_frames;
2246 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
2247 smb->rx_runts + smb->rx_pkts_truncated +
2248 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2255 struct ale_softc *sc;
2258 sc = (struct ale_softc *)arg;
2260 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2261 if ((status & ALE_INTRS) == 0)
2262 return (FILTER_STRAY);
2263 /* Disable interrupts. */
2264 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2265 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2267 return (FILTER_HANDLED);
2271 ale_int_task(void *arg, int pending)
2273 struct ale_softc *sc;
2278 sc = (struct ale_softc *)arg;
2280 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2282 if (sc->ale_morework != 0)
2283 status |= INTR_RX_PKT;
2284 if ((status & ALE_INTRS) == 0)
2287 /* Acknowledge interrupts but still disable interrupts. */
2288 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2292 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2293 more = ale_rxeof(sc, sc->ale_process_limit);
2295 sc->ale_morework = 1;
2296 else if (more == EIO) {
2297 sc->ale_stats.reset_brk_seq++;
2298 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2299 ale_init_locked(sc);
2304 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2305 if ((status & INTR_DMA_RD_TO_RST) != 0)
2306 device_printf(sc->ale_dev,
2307 "DMA read error! -- resetting\n");
2308 if ((status & INTR_DMA_WR_TO_RST) != 0)
2309 device_printf(sc->ale_dev,
2310 "DMA write error! -- resetting\n");
2311 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2312 ale_init_locked(sc);
2316 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2317 ale_start_locked(ifp);
2320 if (more == EAGAIN ||
2321 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2323 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2330 /* Re-enable interrupts. */
2331 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2335 ale_txeof(struct ale_softc *sc)
2338 struct ale_txdesc *txd;
2339 uint32_t cons, prod;
2342 ALE_LOCK_ASSERT(sc);
2346 if (sc->ale_cdata.ale_tx_cnt == 0)
2349 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2350 sc->ale_cdata.ale_tx_ring_map,
2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2352 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2353 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2354 sc->ale_cdata.ale_tx_cmb_map,
2355 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2356 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2358 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2359 cons = sc->ale_cdata.ale_tx_cons;
2361 * Go through our Tx list and free mbufs for those
2362 * frames which have been transmitted.
2364 for (prog = 0; cons != prod; prog++,
2365 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2366 if (sc->ale_cdata.ale_tx_cnt <= 0)
2369 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2370 sc->ale_cdata.ale_tx_cnt--;
2371 txd = &sc->ale_cdata.ale_txdesc[cons];
2372 if (txd->tx_m != NULL) {
2373 /* Reclaim transmitted mbufs. */
2374 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2375 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2376 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2384 sc->ale_cdata.ale_tx_cons = cons;
2386 * Unarm watchdog timer only when there is no pending
2387 * Tx descriptors in queue.
2389 if (sc->ale_cdata.ale_tx_cnt == 0)
2390 sc->ale_watchdog_timer = 0;
2395 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2396 uint32_t length, uint32_t *prod)
2398 struct ale_rx_page *rx_page;
2401 /* Update consumer position. */
2402 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2404 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2406 * End of Rx page reached, let hardware reuse
2410 *rx_page->cmb_addr = 0;
2411 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2412 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2413 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2415 /* Switch to alternate Rx page. */
2416 sc->ale_cdata.ale_rx_curp ^= 1;
2418 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2419 /* Page flipped, sync CMB and Rx page. */
2420 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2421 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2422 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2423 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2424 /* Sync completed, cache updated producer index. */
2425 *prod = *rx_page->cmb_addr;
2431 * It seems that AR81xx controller can compute partial checksum.
2432 * The partial checksum value can be used to accelerate checksum
2433 * computation for fragmented TCP/UDP packets. Upper network stack
2434 * already takes advantage of the partial checksum value in IP
2435 * reassembly stage. But I'm not sure the correctness of the
2436 * partial hardware checksum assistance due to lack of data sheet.
2437 * In addition, the Rx feature of controller that requires copying
2438 * for every frames effectively nullifies one of most nice offload
2439 * capability of controller.
2442 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2449 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2450 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2451 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2453 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2454 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2455 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2456 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2457 m->m_pkthdr.csum_flags |=
2458 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2459 m->m_pkthdr.csum_data = 0xffff;
2462 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2463 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2464 p = mtod(m, char *);
2466 if ((status & ALE_RD_802_3) != 0)
2467 p += LLC_SNAPFRAMELEN;
2468 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2469 (status & ALE_RD_VLAN) != 0)
2470 p += ETHER_VLAN_ENCAP_LEN;
2471 ip = (struct ip *)p;
2472 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2474 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2476 m->m_pkthdr.csum_data = 0xffff;
2480 * Don't mark bad checksum for TCP/UDP frames
2481 * as fragmented frames may always have set
2482 * bad checksummed bit of frame status.
2486 /* Process received frames. */
2488 ale_rxeof(struct ale_softc *sc, int count)
2490 struct ale_rx_page *rx_page;
2494 uint32_t length, prod, seqno, status, vtags;
2498 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2499 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2500 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2501 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2504 * Don't directly access producer index as hardware may
2505 * update it while Rx handler is in progress. It would
2506 * be even better if there is a way to let hardware
2507 * know how far driver processed its received frames.
2508 * Alternatively, hardware could provide a way to disable
2509 * CMB updates until driver acknowledges the end of CMB
2512 prod = *rx_page->cmb_addr;
2513 for (prog = 0; prog < count; prog++) {
2514 if (rx_page->cons >= prod)
2516 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2517 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2518 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2520 * Normally I believe this should not happen unless
2521 * severe driver bug or corrupted memory. However
2522 * it seems to happen under certain conditions which
2523 * is triggered by abrupt Rx events such as initiation
2524 * of bulk transfer of remote host. It's not easy to
2525 * reproduce this and I doubt it could be related
2526 * with FIFO overflow of hardware or activity of Tx
2527 * CMB updates. I also remember similar behaviour
2528 * seen on RealTek 8139 which uses resembling Rx
2532 device_printf(sc->ale_dev,
2533 "garbled seq: %u, expected: %u -- "
2534 "resetting!\n", seqno,
2535 sc->ale_cdata.ale_rx_seqno);
2538 /* Frame received. */
2539 sc->ale_cdata.ale_rx_seqno++;
2540 length = ALE_RX_BYTES(le32toh(rs->length));
2541 status = le32toh(rs->flags);
2542 if ((status & ALE_RD_ERROR) != 0) {
2544 * We want to pass the following frames to upper
2545 * layer regardless of error status of Rx return
2548 * o IP/TCP/UDP checksum is bad.
2549 * o frame length and protocol specific length
2552 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2553 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2554 ALE_RD_TRUNC)) != 0) {
2555 ale_rx_update_page(sc, &rx_page, length, &prod);
2560 * m_devget(9) is major bottle-neck of ale(4)(It comes
2561 * from hardware limitation). For jumbo frames we could
2562 * get a slightly better performance if driver use
2563 * m_getjcl(9) with proper buffer size argument. However
2564 * that would make code more complicated and I don't
2565 * think users would expect good Rx performance numbers
2566 * on these low-end consumer ethernet controller.
2568 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2569 ETHER_ALIGN, ifp, NULL);
2572 ale_rx_update_page(sc, &rx_page, length, &prod);
2575 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2576 (status & ALE_RD_IPV4) != 0)
2577 ale_rxcsum(sc, m, status);
2578 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2579 (status & ALE_RD_VLAN) != 0) {
2580 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2581 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2582 m->m_flags |= M_VLANTAG;
2585 /* Pass it to upper layer. */
2587 (*ifp->if_input)(ifp, m);
2590 ale_rx_update_page(sc, &rx_page, length, &prod);
2593 return (count > 0 ? 0 : EAGAIN);
2599 struct ale_softc *sc;
2600 struct mii_data *mii;
2602 sc = (struct ale_softc *)arg;
2604 ALE_LOCK_ASSERT(sc);
2606 mii = device_get_softc(sc->ale_miibus);
2608 ale_stats_update(sc);
2610 * Reclaim Tx buffers that have been transferred. It's not
2611 * needed here but it would release allocated mbuf chains
2612 * faster and limit the maximum delay to a hz.
2616 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2620 ale_reset(struct ale_softc *sc)
2625 /* Initialize PCIe module. From Linux. */
2626 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2628 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2629 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2631 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2635 device_printf(sc->ale_dev, "master reset timeout!\n");
2637 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2638 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2644 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2650 struct ale_softc *sc;
2652 sc = (struct ale_softc *)xsc;
2654 ale_init_locked(sc);
2659 ale_init_locked(struct ale_softc *sc)
2662 struct mii_data *mii;
2663 uint8_t eaddr[ETHER_ADDR_LEN];
2665 uint32_t reg, rxf_hi, rxf_lo;
2667 ALE_LOCK_ASSERT(sc);
2670 mii = device_get_softc(sc->ale_miibus);
2672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2675 * Cancel any pending I/O.
2679 * Reset the chip to a known state.
2682 /* Initialize Tx descriptors, DMA memory blocks. */
2683 ale_init_rx_pages(sc);
2684 ale_init_tx_ring(sc);
2686 /* Reprogram the station address. */
2687 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2688 CSR_WRITE_4(sc, ALE_PAR0,
2689 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2690 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2692 * Clear WOL status and disable all WOL feature as WOL
2693 * would interfere Rx operation under normal environments.
2695 CSR_READ_4(sc, ALE_WOL_CFG);
2696 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2698 * Set Tx descriptor/RXF0/CMB base addresses. They share
2699 * the same high address part of DMAable region.
2701 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2702 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2703 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2704 CSR_WRITE_4(sc, ALE_TPD_CNT,
2705 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2706 /* Set Rx page base address, note we use single queue. */
2707 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2708 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2709 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2710 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2711 /* Set Tx/Rx CMB addresses. */
2712 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2713 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2714 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2715 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2716 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2717 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2718 /* Mark RXF0 is valid. */
2719 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2720 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2722 * No need to initialize RFX1/RXF2/RXF3. We don't use
2726 /* Set Rx page size, excluding guard frame size. */
2727 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2728 /* Tell hardware that we're ready to load DMA blocks. */
2729 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2731 /* Set Rx/Tx interrupt trigger threshold. */
2732 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2733 (4 << INT_TRIG_TX_THRESH_SHIFT));
2736 * Set interrupt trigger timer, its purpose and relation
2737 * with interrupt moderation mechanism is not clear yet.
2739 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2740 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2741 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2743 /* Configure interrupt moderation timer. */
2744 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2745 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2746 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2747 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2748 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2749 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2750 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2751 reg |= MASTER_IM_RX_TIMER_ENB;
2752 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2753 reg |= MASTER_IM_TX_TIMER_ENB;
2754 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2755 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2757 /* Set Maximum frame size of controller. */
2758 if (ifp->if_mtu < ETHERMTU)
2759 sc->ale_max_frame_size = ETHERMTU;
2761 sc->ale_max_frame_size = ifp->if_mtu;
2762 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2764 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2765 /* Configure IPG/IFG parameters. */
2766 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2767 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2768 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2769 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2770 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2771 /* Set parameters for half-duplex media. */
2772 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2773 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2774 HDPX_CFG_LCOL_MASK) |
2775 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2776 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2777 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2778 HDPX_CFG_ABEBT_MASK) |
2779 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2780 HDPX_CFG_JAMIPG_MASK));
2782 /* Configure Tx jumbo frame parameters. */
2783 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2784 if (ifp->if_mtu < ETHERMTU)
2785 reg = sc->ale_max_frame_size;
2786 else if (ifp->if_mtu < 6 * 1024)
2787 reg = (sc->ale_max_frame_size * 2) / 3;
2789 reg = sc->ale_max_frame_size / 2;
2790 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2791 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2792 TX_JUMBO_THRESH_UNIT_SHIFT);
2794 /* Configure TxQ. */
2795 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2796 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2797 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2798 TXQ_CFG_TPD_BURST_MASK;
2799 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2801 /* Configure Rx jumbo frame & flow control parameters. */
2802 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2803 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2804 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2805 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2806 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2807 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2808 RX_JUMBO_LKAH_MASK));
2809 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2810 rxf_hi = (reg * 7) / 10;
2811 rxf_lo = (reg * 3)/ 10;
2812 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2813 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2814 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2815 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2816 RX_FIFO_PAUSE_THRESH_HI_MASK));
2820 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2821 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2823 /* Configure RxQ. */
2824 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2825 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2827 /* Configure DMA parameters. */
2829 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2830 reg |= DMA_CFG_TXCMB_ENB;
2831 CSR_WRITE_4(sc, ALE_DMA_CFG,
2832 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2833 sc->ale_dma_rd_burst | reg |
2834 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2835 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2836 DMA_CFG_RD_DELAY_CNT_MASK) |
2837 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2838 DMA_CFG_WR_DELAY_CNT_MASK));
2841 * Hardware can be configured to issue SMB interrupt based
2842 * on programmed interval. Since there is a callout that is
2843 * invoked for every hz in driver we use that instead of
2844 * relying on periodic SMB interrupt.
2846 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2847 /* Clear MAC statistics. */
2848 ale_stats_clear(sc);
2851 * Configure Tx/Rx MACs.
2852 * - Auto-padding for short frames.
2853 * - Enable CRC generation.
2854 * Actual reconfiguration of MAC for resolved speed/duplex
2855 * is followed after detection of link establishment.
2856 * AR81xx always does checksum computation regardless of
2857 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2858 * cause Rx handling issue for fragmented IP datagrams due
2861 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2862 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2863 MAC_CFG_PREAMBLE_MASK);
2864 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2865 reg |= MAC_CFG_SPEED_10_100;
2867 reg |= MAC_CFG_SPEED_1000;
2868 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2870 /* Set up the receive filter. */
2874 /* Acknowledge all pending interrupts and clear it. */
2875 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2876 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2877 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2879 sc->ale_flags &= ~ALE_FLAG_LINK;
2880 /* Switch to the current media. */
2883 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2885 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2886 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2890 ale_stop(struct ale_softc *sc)
2893 struct ale_txdesc *txd;
2897 ALE_LOCK_ASSERT(sc);
2899 * Mark the interface down and cancel the watchdog timer.
2902 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2903 sc->ale_flags &= ~ALE_FLAG_LINK;
2904 callout_stop(&sc->ale_tick_ch);
2905 sc->ale_watchdog_timer = 0;
2906 ale_stats_update(sc);
2907 /* Disable interrupts. */
2908 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2909 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2910 /* Disable queue processing and DMA. */
2911 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2912 reg &= ~TXQ_CFG_ENB;
2913 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2914 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2915 reg &= ~RXQ_CFG_ENB;
2916 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2917 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2918 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2919 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2921 /* Stop Rx/Tx MACs. */
2923 /* Disable interrupts which might be touched in taskq handler. */
2924 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2927 * Free TX mbufs still in the queues.
2929 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2930 txd = &sc->ale_cdata.ale_txdesc[i];
2931 if (txd->tx_m != NULL) {
2932 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2933 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2934 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2943 ale_stop_mac(struct ale_softc *sc)
2948 ALE_LOCK_ASSERT(sc);
2950 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2951 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2952 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2953 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2956 for (i = ALE_TIMEOUT; i > 0; i--) {
2957 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2963 device_printf(sc->ale_dev,
2964 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2968 ale_init_tx_ring(struct ale_softc *sc)
2970 struct ale_txdesc *txd;
2973 ALE_LOCK_ASSERT(sc);
2975 sc->ale_cdata.ale_tx_prod = 0;
2976 sc->ale_cdata.ale_tx_cons = 0;
2977 sc->ale_cdata.ale_tx_cnt = 0;
2979 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2980 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2981 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2982 txd = &sc->ale_cdata.ale_txdesc[i];
2985 *sc->ale_cdata.ale_tx_cmb = 0;
2986 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2987 sc->ale_cdata.ale_tx_cmb_map,
2988 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2989 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2990 sc->ale_cdata.ale_tx_ring_map,
2991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2995 ale_init_rx_pages(struct ale_softc *sc)
2997 struct ale_rx_page *rx_page;
3000 ALE_LOCK_ASSERT(sc);
3002 sc->ale_morework = 0;
3003 sc->ale_cdata.ale_rx_seqno = 0;
3004 sc->ale_cdata.ale_rx_curp = 0;
3006 for (i = 0; i < ALE_RX_PAGES; i++) {
3007 rx_page = &sc->ale_cdata.ale_rx_page[i];
3008 bzero(rx_page->page_addr, sc->ale_pagesize);
3009 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
3011 *rx_page->cmb_addr = 0;
3012 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
3013 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3014 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
3015 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3020 ale_rxvlan(struct ale_softc *sc)
3025 ALE_LOCK_ASSERT(sc);
3028 reg = CSR_READ_4(sc, ALE_MAC_CFG);
3029 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3030 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3031 reg |= MAC_CFG_VLAN_TAG_STRIP;
3032 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
3036 ale_rxfilter(struct ale_softc *sc)
3039 struct ifmultiaddr *ifma;
3044 ALE_LOCK_ASSERT(sc);
3048 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3049 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3050 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3051 rxcfg |= MAC_CFG_BCAST;
3052 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3053 if ((ifp->if_flags & IFF_PROMISC) != 0)
3054 rxcfg |= MAC_CFG_PROMISC;
3055 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3056 rxcfg |= MAC_CFG_ALLMULTI;
3057 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3058 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3059 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3063 /* Program new filter. */
3064 bzero(mchash, sizeof(mchash));
3066 if_maddr_rlock(ifp);
3067 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) {
3068 if (ifma->ifma_addr->sa_family != AF_LINK)
3070 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3071 ifma->ifma_addr), ETHER_ADDR_LEN);
3072 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3074 if_maddr_runlock(ifp);
3076 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3077 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3078 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3082 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3088 value = *(int *)arg1;
3089 error = sysctl_handle_int(oidp, &value, 0, req);
3090 if (error || req->newptr == NULL)
3092 if (value < low || value > high)
3094 *(int *)arg1 = value;
3100 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3102 return (sysctl_int_range(oidp, arg1, arg2, req,
3103 ALE_PROC_MIN, ALE_PROC_MAX));
3107 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3110 return (sysctl_int_range(oidp, arg1, arg2, req,
3111 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));