2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
27 #include "ar5212/ar5212phy.h"
28 #ifdef AH_SUPPORT_5311
29 #include "ar5212/ar5311reg.h"
32 #ifdef AH_NEED_DESC_SWAP
33 static void ar5212SwapTxDesc(struct ath_desc *ds);
37 * Update Tx FIFO trigger level.
39 * Set bIncTrigLevel to TRUE to increase the trigger level.
40 * Set bIncTrigLevel to FALSE to decrease the trigger level.
42 * Returns TRUE if the trigger level was updated
45 ar5212UpdateTxTrigLevel(struct ath_hal *ah, HAL_BOOL bIncTrigLevel)
47 struct ath_hal_5212 *ahp = AH5212(ah);
48 uint32_t txcfg, curLevel, newLevel;
51 if (ahp->ah_txTrigLev >= ahp->ah_maxTxTrigLev)
55 * Disable interrupts while futzing with the fifo level.
57 omask = ath_hal_setInterrupts(ah, ahp->ah_maskReg &~ HAL_INT_GLOBAL);
59 txcfg = OS_REG_READ(ah, AR_TXCFG);
60 curLevel = MS(txcfg, AR_FTRIG);
62 if (bIncTrigLevel) { /* increase the trigger level */
63 if (curLevel < ahp->ah_maxTxTrigLev)
65 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
67 if (newLevel != curLevel)
68 /* Update the trigger level */
69 OS_REG_WRITE(ah, AR_TXCFG,
70 (txcfg &~ AR_FTRIG) | SM(newLevel, AR_FTRIG));
72 ahp->ah_txTrigLev = newLevel;
74 /* re-enable chip interrupts */
75 ath_hal_setInterrupts(ah, omask);
77 return (newLevel != curLevel);
81 * Set the properties of the tx queue with the parameters
85 ar5212SetTxQueueProps(struct ath_hal *ah, int q, const HAL_TXQ_INFO *qInfo)
87 struct ath_hal_5212 *ahp = AH5212(ah);
88 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
90 if (q >= pCap->halTotalQueues) {
91 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
95 return ath_hal_setTxQProps(ah, &ahp->ah_txq[q], qInfo);
99 * Return the properties for the specified tx queue.
102 ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_TXQ_INFO *qInfo)
104 struct ath_hal_5212 *ahp = AH5212(ah);
105 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
108 if (q >= pCap->halTotalQueues) {
109 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
113 return ath_hal_getTxQProps(ah, qInfo, &ahp->ah_txq[q]);
117 * Allocate and initialize a tx DCU/QCU combination.
120 ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
121 const HAL_TXQ_INFO *qInfo)
123 struct ath_hal_5212 *ahp = AH5212(ah);
124 HAL_TX_QUEUE_INFO *qi;
125 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
128 /* by default enable OK+ERR+DESC+URN interrupts */
129 defqflags = HAL_TXQ_TXOKINT_ENABLE
130 | HAL_TXQ_TXERRINT_ENABLE
131 | HAL_TXQ_TXDESCINT_ENABLE
132 | HAL_TXQ_TXURNINT_ENABLE;
133 /* XXX move queue assignment to driver */
135 case HAL_TX_QUEUE_BEACON:
136 q = pCap->halTotalQueues-1; /* highest priority */
137 defqflags |= HAL_TXQ_DBA_GATED
138 | HAL_TXQ_CBR_DIS_QEMPTY
139 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
140 | HAL_TXQ_BACKOFF_DISABLE;
142 case HAL_TX_QUEUE_CAB:
143 q = pCap->halTotalQueues-2; /* next highest priority */
144 defqflags |= HAL_TXQ_DBA_GATED
145 | HAL_TXQ_CBR_DIS_QEMPTY
146 | HAL_TXQ_CBR_DIS_BEMPTY
147 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
148 | HAL_TXQ_BACKOFF_DISABLE;
150 case HAL_TX_QUEUE_UAPSD:
151 q = pCap->halTotalQueues-3; /* nextest highest priority */
152 if (ahp->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE) {
153 HALDEBUG(ah, HAL_DEBUG_ANY,
154 "%s: no available UAPSD tx queue\n", __func__);
158 case HAL_TX_QUEUE_DATA:
159 for (q = 0; q < pCap->halTotalQueues; q++)
160 if (ahp->ah_txq[q].tqi_type == HAL_TX_QUEUE_INACTIVE)
162 if (q == pCap->halTotalQueues) {
163 HALDEBUG(ah, HAL_DEBUG_ANY,
164 "%s: no available tx queue\n", __func__);
169 HALDEBUG(ah, HAL_DEBUG_ANY,
170 "%s: bad tx queue type %u\n", __func__, type);
174 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
176 qi = &ahp->ah_txq[q];
177 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
178 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: tx queue %u already active\n",
182 OS_MEMZERO(qi, sizeof(HAL_TX_QUEUE_INFO));
184 if (qInfo == AH_NULL) {
185 qi->tqi_qflags = defqflags;
186 qi->tqi_aifs = INIT_AIFS;
187 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT; /* NB: do at reset */
188 qi->tqi_cwmax = INIT_CWMAX;
189 qi->tqi_shretry = INIT_SH_RETRY;
190 qi->tqi_lgretry = INIT_LG_RETRY;
191 qi->tqi_physCompBuf = 0;
193 qi->tqi_physCompBuf = qInfo->tqi_compBuf;
194 (void) ar5212SetTxQueueProps(ah, q, qInfo);
196 /* NB: must be followed by ar5212ResetTxQueue */
201 * Update the h/w interrupt registers to reflect a tx q's configuration.
204 setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO *qi)
206 struct ath_hal_5212 *ahp = AH5212(ah);
208 HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
209 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", __func__,
210 ahp->ah_txOkInterruptMask, ahp->ah_txErrInterruptMask,
211 ahp->ah_txDescInterruptMask, ahp->ah_txEolInterruptMask,
212 ahp->ah_txUrnInterruptMask);
214 OS_REG_WRITE(ah, AR_IMR_S0,
215 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
216 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
218 OS_REG_WRITE(ah, AR_IMR_S1,
219 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
220 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
222 OS_REG_RMW_FIELD(ah, AR_IMR_S2,
223 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
227 * Free a tx DCU/QCU combination.
230 ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q)
232 struct ath_hal_5212 *ahp = AH5212(ah);
233 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
234 HAL_TX_QUEUE_INFO *qi;
236 if (q >= pCap->halTotalQueues) {
237 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
241 qi = &ahp->ah_txq[q];
242 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
243 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
248 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: release queue %u\n", __func__, q);
250 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
251 ahp->ah_txOkInterruptMask &= ~(1 << q);
252 ahp->ah_txErrInterruptMask &= ~(1 << q);
253 ahp->ah_txDescInterruptMask &= ~(1 << q);
254 ahp->ah_txEolInterruptMask &= ~(1 << q);
255 ahp->ah_txUrnInterruptMask &= ~(1 << q);
256 setTxQInterrupts(ah, qi);
262 * Set the retry, aifs, cwmin/max, readyTime regs for specified queue
264 * phwChannel has been set to point to the current channel
267 ar5212ResetTxQueue(struct ath_hal *ah, u_int q)
269 struct ath_hal_5212 *ahp = AH5212(ah);
270 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
271 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
272 HAL_TX_QUEUE_INFO *qi;
273 uint32_t cwMin, chanCwMin, value, qmisc, dmisc;
275 if (q >= pCap->halTotalQueues) {
276 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n",
280 qi = &ahp->ah_txq[q];
281 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
282 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: inactive queue %u\n",
284 return AH_TRUE; /* XXX??? */
287 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: reset queue %u\n", __func__, q);
289 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
291 * Select cwmin according to channel type.
292 * NB: chan can be NULL during attach
294 if (chan && IEEE80211_IS_CHAN_B(chan))
295 chanCwMin = INIT_CWMIN_11B;
297 chanCwMin = INIT_CWMIN;
298 /* make sure that the CWmin is of the form (2^n - 1) */
299 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1)
302 cwMin = qi->tqi_cwmin;
304 /* set cwMin/Max and AIFS values */
305 OS_REG_WRITE(ah, AR_DLCL_IFS(q),
306 SM(cwMin, AR_D_LCL_IFS_CWMIN)
307 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
308 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
310 /* Set retry limit values */
311 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(q),
312 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
313 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
314 | SM(qi->tqi_lgretry, AR_D_RETRY_LIMIT_FR_LG)
315 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
318 /* NB: always enable early termination on the QCU */
319 qmisc = AR_Q_MISC_DCU_EARLY_TERM_REQ
320 | SM(AR_Q_MISC_FSP_ASAP, AR_Q_MISC_FSP);
322 /* NB: always enable DCU to wait for next fragment from QCU */
323 dmisc = AR_D_MISC_FRAG_WAIT_EN;
325 #ifdef AH_SUPPORT_5311
326 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_OAHU) {
327 /* Configure DCU to use the global sequence count */
328 dmisc |= AR5311_D_MISC_SEQ_NUM_CONTROL;
331 /* multiqueue support */
332 if (qi->tqi_cbrPeriod) {
333 OS_REG_WRITE(ah, AR_QCBRCFG(q),
334 SM(qi->tqi_cbrPeriod,AR_Q_CBRCFG_CBR_INTERVAL)
335 | SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_CBR_OVF_THRESH));
336 qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_CBR;
337 if (qi->tqi_cbrOverflowLimit)
338 qmisc |= AR_Q_MISC_CBR_EXP_CNTR_LIMIT;
340 if (qi->tqi_readyTime) {
341 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q),
342 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT)
343 | AR_Q_RDYTIMECFG_ENA);
346 OS_REG_WRITE(ah, AR_DCHNTIME(q),
347 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR)
348 | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
350 if (qi->tqi_readyTime &&
351 (qi->tqi_qflags & HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE))
352 qmisc |= AR_Q_MISC_RDYTIME_EXP_POLICY;
353 if (qi->tqi_qflags & HAL_TXQ_DBA_GATED)
354 qmisc = (qmisc &~ AR_Q_MISC_FSP) | AR_Q_MISC_FSP_DBA_GATED;
355 if (MS(qmisc, AR_Q_MISC_FSP) != AR_Q_MISC_FSP_ASAP) {
357 * These are meangingful only when not scheduled asap.
359 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_BEMPTY)
360 qmisc |= AR_Q_MISC_CBR_INCR_DIS0;
362 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS0;
363 if (qi->tqi_qflags & HAL_TXQ_CBR_DIS_QEMPTY)
364 qmisc |= AR_Q_MISC_CBR_INCR_DIS1;
366 qmisc &= ~AR_Q_MISC_CBR_INCR_DIS1;
369 if (qi->tqi_qflags & HAL_TXQ_BACKOFF_DISABLE)
370 dmisc |= AR_D_MISC_POST_FR_BKOFF_DIS;
371 if (qi->tqi_qflags & HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE)
372 dmisc |= AR_D_MISC_FRAG_BKOFF_EN;
373 if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_GLOBAL)
374 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
375 AR_D_MISC_ARB_LOCKOUT_CNTRL);
376 else if (qi->tqi_qflags & HAL_TXQ_ARB_LOCKOUT_INTRA)
377 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR,
378 AR_D_MISC_ARB_LOCKOUT_CNTRL);
379 if (qi->tqi_qflags & HAL_TXQ_IGNORE_VIRTCOL)
380 dmisc |= SM(AR_D_MISC_VIR_COL_HANDLING_IGNORE,
381 AR_D_MISC_VIR_COL_HANDLING);
382 if (qi->tqi_qflags & HAL_TXQ_SEQNUM_INC_DIS)
383 dmisc |= AR_D_MISC_SEQ_NUM_INCR_DIS;
386 * Fillin type-dependent bits. Most of this can be
387 * removed by specifying the queue parameters in the
388 * driver; it's here for backwards compatibility.
390 switch (qi->tqi_type) {
391 case HAL_TX_QUEUE_BEACON: /* beacon frames */
392 qmisc |= AR_Q_MISC_FSP_DBA_GATED
393 | AR_Q_MISC_BEACON_USE
394 | AR_Q_MISC_CBR_INCR_DIS1;
396 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
397 AR_D_MISC_ARB_LOCKOUT_CNTRL)
398 | AR_D_MISC_BEACON_USE
399 | AR_D_MISC_POST_FR_BKOFF_DIS;
401 case HAL_TX_QUEUE_CAB: /* CAB frames */
403 * No longer Enable AR_Q_MISC_RDYTIME_EXP_POLICY,
404 * There is an issue with the CAB Queue
405 * not properly refreshing the Tx descriptor if
406 * the TXE clear setting is used.
408 qmisc |= AR_Q_MISC_FSP_DBA_GATED
409 | AR_Q_MISC_CBR_INCR_DIS1
410 | AR_Q_MISC_CBR_INCR_DIS0;
412 if (!qi->tqi_readyTime) {
414 * NB: don't set default ready time if driver
415 * has explicitly specified something. This is
416 * here solely for backwards compatibility.
418 value = (ahp->ah_beaconInterval
419 - (ah->ah_config.ah_sw_beacon_response_time -
420 ah->ah_config.ah_dma_beacon_response_time)
421 - ah->ah_config.ah_additional_swba_backoff) * 1024;
422 OS_REG_WRITE(ah, AR_QRDYTIMECFG(q), value | AR_Q_RDYTIMECFG_ENA);
424 dmisc |= SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
425 AR_D_MISC_ARB_LOCKOUT_CNTRL);
427 default: /* NB: silence compiler */
431 OS_REG_WRITE(ah, AR_QMISC(q), qmisc);
432 OS_REG_WRITE(ah, AR_DMISC(q), dmisc);
434 /* Setup compression scratchpad buffer */
436 * XXX: calling this asynchronously to queue operation can
437 * cause unexpected behavior!!!
439 if (qi->tqi_physCompBuf) {
440 HALASSERT(qi->tqi_type == HAL_TX_QUEUE_DATA ||
441 qi->tqi_type == HAL_TX_QUEUE_UAPSD);
442 OS_REG_WRITE(ah, AR_Q_CBBS, (80 + 2*q));
443 OS_REG_WRITE(ah, AR_Q_CBBA, qi->tqi_physCompBuf);
444 OS_REG_WRITE(ah, AR_Q_CBC, HAL_COMP_BUF_MAX_SIZE/1024);
445 OS_REG_WRITE(ah, AR_Q0_MISC + 4*q,
446 OS_REG_READ(ah, AR_Q0_MISC + 4*q)
447 | AR_Q_MISC_QCU_COMP_EN);
451 * Always update the secondary interrupt mask registers - this
452 * could be a new queue getting enabled in a running system or
453 * hw getting re-initialized during a reset!
455 * Since we don't differentiate between tx interrupts corresponding
456 * to individual queues - secondary tx mask regs are always unmasked;
457 * tx interrupts are enabled/disabled for all queues collectively
458 * using the primary mask reg
460 if (qi->tqi_qflags & HAL_TXQ_TXOKINT_ENABLE)
461 ahp->ah_txOkInterruptMask |= 1 << q;
463 ahp->ah_txOkInterruptMask &= ~(1 << q);
464 if (qi->tqi_qflags & HAL_TXQ_TXERRINT_ENABLE)
465 ahp->ah_txErrInterruptMask |= 1 << q;
467 ahp->ah_txErrInterruptMask &= ~(1 << q);
468 if (qi->tqi_qflags & HAL_TXQ_TXDESCINT_ENABLE)
469 ahp->ah_txDescInterruptMask |= 1 << q;
471 ahp->ah_txDescInterruptMask &= ~(1 << q);
472 if (qi->tqi_qflags & HAL_TXQ_TXEOLINT_ENABLE)
473 ahp->ah_txEolInterruptMask |= 1 << q;
475 ahp->ah_txEolInterruptMask &= ~(1 << q);
476 if (qi->tqi_qflags & HAL_TXQ_TXURNINT_ENABLE)
477 ahp->ah_txUrnInterruptMask |= 1 << q;
479 ahp->ah_txUrnInterruptMask &= ~(1 << q);
480 setTxQInterrupts(ah, qi);
486 * Get the TXDP for the specified queue
489 ar5212GetTxDP(struct ath_hal *ah, u_int q)
491 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
492 return OS_REG_READ(ah, AR_QTXDP(q));
496 * Set the TxDP for the specified queue
499 ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp)
501 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
502 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
505 * Make sure that TXE is deasserted before setting the TXDP. If TXE
506 * is still asserted, setting TXDP will have no effect.
508 HALASSERT((OS_REG_READ(ah, AR_Q_TXE) & (1 << q)) == 0);
510 OS_REG_WRITE(ah, AR_QTXDP(q), txdp);
516 * Set Transmit Enable bits for the specified queue
519 ar5212StartTxDma(struct ath_hal *ah, u_int q)
521 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
523 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
525 HALDEBUG(ah, HAL_DEBUG_TXQUEUE, "%s: queue %u\n", __func__, q);
527 /* Check to be sure we're not enabling a q that has its TXD bit set. */
528 HALASSERT((OS_REG_READ(ah, AR_Q_TXD) & (1 << q)) == 0);
530 OS_REG_WRITE(ah, AR_Q_TXE, 1 << q);
535 * Return the number of pending frames or 0 if the specified
539 ar5212NumTxPending(struct ath_hal *ah, u_int q)
543 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
544 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
546 npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
549 * Pending frame count (PFC) can momentarily go to zero
550 * while TXE remains asserted. In other words a PFC of
551 * zero is not sufficient to say that the queue has stopped.
553 if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
554 npend = 1; /* arbitrarily return 1 */
560 * Stop transmit on the specified queue
563 ar5212StopTxDma(struct ath_hal *ah, u_int q)
568 HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
570 HALASSERT(AH5212(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
572 OS_REG_WRITE(ah, AR_Q_TXD, 1 << q);
573 for (i = 1000; i != 0; i--) {
574 if (ar5212NumTxPending(ah, q) == 0)
576 OS_DELAY(100); /* XXX get actual value */
580 HALDEBUG(ah, HAL_DEBUG_ANY,
581 "%s: queue %u DMA did not stop in 100 msec\n", __func__, q);
582 HALDEBUG(ah, HAL_DEBUG_ANY,
583 "%s: QSTS 0x%x Q_TXE 0x%x Q_TXD 0x%x Q_CBR 0x%x\n", __func__,
584 OS_REG_READ(ah, AR_QSTS(q)), OS_REG_READ(ah, AR_Q_TXE),
585 OS_REG_READ(ah, AR_Q_TXD), OS_REG_READ(ah, AR_QCBRCFG(q)));
586 HALDEBUG(ah, HAL_DEBUG_ANY,
587 "%s: Q_MISC 0x%x Q_RDYTIMECFG 0x%x Q_RDYTIMESHDN 0x%x\n",
588 __func__, OS_REG_READ(ah, AR_QMISC(q)),
589 OS_REG_READ(ah, AR_QRDYTIMECFG(q)),
590 OS_REG_READ(ah, AR_Q_RDYTIMESHDN));
592 #endif /* AH_DEBUG */
594 /* 2413+ and up can kill packets at the PCU level */
595 if (ar5212NumTxPending(ah, q) &&
596 (IS_2413(ah) || IS_5413(ah) || IS_2425(ah) || IS_2417(ah))) {
599 HALDEBUG(ah, HAL_DEBUG_TXQUEUE,
600 "%s: Num of pending TX Frames %d on Q %d\n",
601 __func__, ar5212NumTxPending(ah, q), q);
603 /* Kill last PCU Tx Frame */
604 /* TODO - save off and restore current values of Q1/Q2? */
605 for (j = 0; j < 2; j++) {
606 tsfLow = OS_REG_READ(ah, AR_TSF_L32);
607 OS_REG_WRITE(ah, AR_QUIET2, SM(100, AR_QUIET2_QUIET_PER) |
608 SM(10, AR_QUIET2_QUIET_DUR));
609 OS_REG_WRITE(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE |
610 SM(tsfLow >> 10, AR_QUIET1_NEXT_QUIET));
611 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) {
614 HALDEBUG(ah, HAL_DEBUG_ANY,
615 "%s: TSF moved while trying to set quiet time "
616 "TSF: 0x%08x\n", __func__, tsfLow);
617 HALASSERT(j < 1); /* TSF shouldn't count twice or reg access is taking forever */
620 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
622 /* Allow the quiet mechanism to do its work */
624 OS_REG_CLR_BIT(ah, AR_QUIET1, AR_QUIET1_QUIET_ENABLE);
626 /* Give at least 1 millisec more to wait */
629 /* Verify all transmit is dead */
630 while (ar5212NumTxPending(ah, q)) {
632 HALDEBUG(ah, HAL_DEBUG_ANY,
633 "%s: Failed to stop Tx DMA in %d msec after killing last frame\n",
640 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_CHAN_IDLE);
643 OS_REG_WRITE(ah, AR_Q_TXD, 0);
648 * Descriptor Access Functions
651 #define VALID_PKT_TYPES \
652 ((1<<HAL_PKT_TYPE_NORMAL)|(1<<HAL_PKT_TYPE_ATIM)|\
653 (1<<HAL_PKT_TYPE_PSPOLL)|(1<<HAL_PKT_TYPE_PROBE_RESP)|\
654 (1<<HAL_PKT_TYPE_BEACON))
655 #define isValidPktType(_t) ((1<<(_t)) & VALID_PKT_TYPES)
656 #define VALID_TX_RATES \
657 ((1<<0x0b)|(1<<0x0f)|(1<<0x0a)|(1<<0x0e)|(1<<0x09)|(1<<0x0d)|\
658 (1<<0x08)|(1<<0x0c)|(1<<0x1b)|(1<<0x1a)|(1<<0x1e)|(1<<0x19)|\
659 (1<<0x1d)|(1<<0x18)|(1<<0x1c))
660 #define isValidTxRate(_r) ((1<<(_r)) & VALID_TX_RATES)
663 ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
668 u_int txRate0, u_int txTries0,
673 u_int rtsctsDuration,
678 #define RTSCTS (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)
679 struct ar5212_desc *ads = AR5212DESC(ds);
680 struct ath_hal_5212 *ahp = AH5212(ah);
684 HALASSERT(txTries0 != 0);
685 HALASSERT(isValidPktType(type));
686 HALASSERT(isValidTxRate(txRate0));
687 HALASSERT((flags & RTSCTS) != RTSCTS);
688 /* XXX validate antMode */
690 txPower = (txPower + ahp->ah_txPowerIndexOffset );
691 if(txPower > 63) txPower=63;
693 ads->ds_ctl0 = (pktLen & AR_FrameLen)
694 | (txPower << AR_XmitPower_S)
695 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
696 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
697 | SM(antMode, AR_AntModeXmit)
698 | (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
700 ads->ds_ctl1 = (type << AR_FrmType_S)
701 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
702 | (comp << AR_CompProc_S)
703 | (compicvLen << AR_CompICVLen_S)
704 | (compivLen << AR_CompIVLen_S)
706 ads->ds_ctl2 = SM(txTries0, AR_XmitDataTries0)
707 | (flags & HAL_TXDESC_DURENA ? AR_DurUpdateEna : 0)
709 ads->ds_ctl3 = (txRate0 << AR_XmitRate0_S)
711 if (keyIx != HAL_TXKEYIX_INVALID) {
712 /* XXX validate key index */
713 ads->ds_ctl1 |= SM(keyIx, AR_DestIdx);
714 ads->ds_ctl0 |= AR_DestIdxValid;
716 if (flags & RTSCTS) {
717 if (!isValidTxRate(rtsctsRate)) {
718 HALDEBUG(ah, HAL_DEBUG_ANY,
719 "%s: invalid rts/cts rate 0x%x\n",
720 __func__, rtsctsRate);
723 /* XXX validate rtsctsDuration */
724 ads->ds_ctl0 |= (flags & HAL_TXDESC_CTSENA ? AR_CTSEnable : 0)
725 | (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
727 ads->ds_ctl2 |= SM(rtsctsDuration, AR_RTSCTSDuration);
728 ads->ds_ctl3 |= (rtsctsRate << AR_RTSCTSRate_S);
735 ar5212SetupXTxDesc(struct ath_hal *ah, struct ath_desc *ds,
736 u_int txRate1, u_int txTries1,
737 u_int txRate2, u_int txTries2,
738 u_int txRate3, u_int txTries3)
740 struct ar5212_desc *ads = AR5212DESC(ds);
743 HALASSERT(isValidTxRate(txRate1));
744 ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1)
747 ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
750 HALASSERT(isValidTxRate(txRate2));
751 ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2)
754 ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
757 HALASSERT(isValidTxRate(txRate3));
758 ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3)
761 ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
767 ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
769 struct ar5212_desc *ads = AR5212DESC(ds);
771 #ifdef AH_NEED_DESC_SWAP
772 ads->ds_ctl0 |= __bswap32(AR_TxInterReq);
774 ads->ds_ctl0 |= AR_TxInterReq;
779 ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
780 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
781 const struct ath_desc *ds0)
783 struct ar5212_desc *ads = AR5212DESC(ds);
785 HALASSERT((segLen &~ AR_BufLen) == 0);
789 * First descriptor, don't clobber xmit control data
790 * setup by ar5212SetupTxDesc.
792 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
793 } else if (lastSeg) { /* !firstSeg && lastSeg */
795 * Last descriptor in a multi-descriptor frame,
796 * copy the multi-rate transmit parameters from
797 * the first frame for processing on completion.
800 ads->ds_ctl1 = segLen;
801 #ifdef AH_NEED_DESC_SWAP
802 ads->ds_ctl2 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl2);
803 ads->ds_ctl3 = __bswap32(AR5212DESC_CONST(ds0)->ds_ctl3);
805 ads->ds_ctl2 = AR5212DESC_CONST(ds0)->ds_ctl2;
806 ads->ds_ctl3 = AR5212DESC_CONST(ds0)->ds_ctl3;
808 } else { /* !firstSeg && !lastSeg */
810 * Intermediate descriptor in a multi-descriptor frame.
813 ads->ds_ctl1 = segLen | AR_More;
817 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
821 #ifdef AH_NEED_DESC_SWAP
822 /* Swap transmit descriptor */
824 ar5212SwapTxDesc(struct ath_desc *ds)
826 ds->ds_data = __bswap32(ds->ds_data);
827 ds->ds_ctl0 = __bswap32(ds->ds_ctl0);
828 ds->ds_ctl1 = __bswap32(ds->ds_ctl1);
829 ds->ds_hw[0] = __bswap32(ds->ds_hw[0]);
830 ds->ds_hw[1] = __bswap32(ds->ds_hw[1]);
831 ds->ds_hw[2] = __bswap32(ds->ds_hw[2]);
832 ds->ds_hw[3] = __bswap32(ds->ds_hw[3]);
837 * Processing of HW TX descriptor.
840 ar5212ProcTxDesc(struct ath_hal *ah,
841 struct ath_desc *ds, struct ath_tx_status *ts)
843 struct ar5212_desc *ads = AR5212DESC(ds);
845 #ifdef AH_NEED_DESC_SWAP
846 if ((ads->ds_txstatus1 & __bswap32(AR_Done)) == 0)
847 return HAL_EINPROGRESS;
849 ar5212SwapTxDesc(ds);
851 if ((ads->ds_txstatus1 & AR_Done) == 0)
852 return HAL_EINPROGRESS;
855 /* Update software copies of the HW status */
856 ts->ts_seqnum = MS(ads->ds_txstatus1, AR_SeqNum);
857 ts->ts_tstamp = MS(ads->ds_txstatus0, AR_SendTimestamp);
859 if ((ads->ds_txstatus0 & AR_FrmXmitOK) == 0) {
860 if (ads->ds_txstatus0 & AR_ExcessiveRetries)
861 ts->ts_status |= HAL_TXERR_XRETRY;
862 if (ads->ds_txstatus0 & AR_Filtered)
863 ts->ts_status |= HAL_TXERR_FILT;
864 if (ads->ds_txstatus0 & AR_FIFOUnderrun)
865 ts->ts_status |= HAL_TXERR_FIFO;
868 * Extract the transmit rate used and mark the rate as
869 * ``alternate'' if it wasn't the series 0 rate.
871 ts->ts_finaltsi = MS(ads->ds_txstatus1, AR_FinalTSIndex);
872 switch (ts->ts_finaltsi) {
874 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate0);
877 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate1);
880 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate2);
883 ts->ts_rate = MS(ads->ds_ctl3, AR_XmitRate3);
886 ts->ts_rssi = MS(ads->ds_txstatus1, AR_AckSigStrength);
887 ts->ts_shortretry = MS(ads->ds_txstatus0, AR_RTSFailCnt);
888 ts->ts_longretry = MS(ads->ds_txstatus0, AR_DataFailCnt);
890 * The retry count has the number of un-acked tries for the
891 * final series used. When doing multi-rate retry we must
892 * fixup the retry count by adding in the try counts for
893 * each series that was fully-processed. Beware that this
894 * takes values from the try counts in the final descriptor.
895 * These are not required by the hardware. We assume they
896 * are placed there by the driver as otherwise we have no
897 * access and the driver can't do the calculation because it
898 * doesn't know the descriptor format.
900 switch (ts->ts_finaltsi) {
901 case 3: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries2);
902 case 2: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries1);
903 case 1: ts->ts_longretry += MS(ads->ds_ctl2, AR_XmitDataTries0);
905 ts->ts_virtcol = MS(ads->ds_txstatus0, AR_VirtCollCnt);
906 ts->ts_antenna = (ads->ds_txstatus1 & AR_XmitAtenna ? 2 : 1);
912 * Determine which tx queues need interrupt servicing.
915 ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *txqs)
917 struct ath_hal_5212 *ahp = AH5212(ah);
918 *txqs &= ahp->ah_intrTxqs;
919 ahp->ah_intrTxqs &= ~(*txqs);
923 * Retrieve the rate table from the given TX completion descriptor
926 ar5212GetTxCompletionRates(struct ath_hal *ah, const struct ath_desc *ds0, int *rates, int *tries)
928 const struct ar5212_desc *ads = AR5212DESC_CONST(ds0);
930 rates[0] = MS(ads->ds_ctl3, AR_XmitRate0);
931 rates[1] = MS(ads->ds_ctl3, AR_XmitRate1);
932 rates[2] = MS(ads->ds_ctl3, AR_XmitRate2);
933 rates[3] = MS(ads->ds_ctl3, AR_XmitRate3);
935 tries[0] = MS(ads->ds_ctl2, AR_XmitDataTries0);
936 tries[1] = MS(ads->ds_ctl2, AR_XmitDataTries1);
937 tries[2] = MS(ads->ds_ctl2, AR_XmitDataTries2);
938 tries[3] = MS(ads->ds_ctl2, AR_XmitDataTries3);