2 * Copyright 2008 Nathan Whitehorn. All rights reserved.
3 * Copyright 2003 by Peter Grehan. All rights reserved.
4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * NetBSD: if_bm.c,v 1.9.2.1 2000/11/01 15:02:49 tv Exp
34 * BMAC/BMAC+ Macio cell 10/100 ethernet driver
35 * The low-cost, low-feature Apple variant of the Sun HME
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
44 #include <sys/endian.h>
46 #include <sys/module.h>
47 #include <sys/malloc.h>
48 #include <sys/kernel.h>
49 #include <sys/socket.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
59 #include <machine/pio.h>
60 #include <machine/bus.h>
61 #include <machine/resource.h>
65 #include <dev/mii/mii.h>
66 #include <dev/mii/miivar.h>
68 #include <dev/ofw/ofw_bus.h>
69 #include <dev/ofw/openfirm.h>
70 #include <machine/dbdma.h>
72 MODULE_DEPEND(bm, ether, 1, 1, 1);
73 MODULE_DEPEND(bm, miibus, 1, 1, 1);
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
81 static int bm_probe (device_t);
82 static int bm_attach (device_t);
83 static int bm_detach (device_t);
84 static int bm_shutdown (device_t);
86 static void bm_start (struct ifnet *);
87 static void bm_start_locked (struct ifnet *);
88 static int bm_encap (struct bm_softc *sc, struct mbuf **m_head);
89 static int bm_ioctl (struct ifnet *, u_long, caddr_t);
90 static void bm_init (void *);
91 static void bm_init_locked (struct bm_softc *sc);
92 static void bm_chip_setup (struct bm_softc *sc);
93 static void bm_stop (struct bm_softc *sc);
94 static void bm_setladrf (struct bm_softc *sc);
95 static void bm_dummypacket (struct bm_softc *sc);
96 static void bm_txintr (void *xsc);
97 static void bm_rxintr (void *xsc);
99 static int bm_add_rxbuf (struct bm_softc *sc, int i);
100 static int bm_add_rxbuf_dma (struct bm_softc *sc, int i);
101 static void bm_enable_interrupts (struct bm_softc *sc);
102 static void bm_disable_interrupts (struct bm_softc *sc);
103 static void bm_tick (void *xsc);
105 static int bm_ifmedia_upd (struct ifnet *);
106 static void bm_ifmedia_sts (struct ifnet *, struct ifmediareq *);
108 static void bm_miicsr_dwrite (struct bm_softc *, u_int16_t);
109 static void bm_mii_writebit (struct bm_softc *, int);
110 static int bm_mii_readbit (struct bm_softc *);
111 static void bm_mii_sync (struct bm_softc *);
112 static void bm_mii_send (struct bm_softc *, u_int32_t, int);
113 static int bm_mii_readreg (struct bm_softc *, struct bm_mii_frame *);
114 static int bm_mii_writereg (struct bm_softc *, struct bm_mii_frame *);
115 static int bm_miibus_readreg (device_t, int, int);
116 static int bm_miibus_writereg (device_t, int, int, int);
117 static void bm_miibus_statchg (device_t);
119 static device_method_t bm_methods[] = {
120 /* Device interface */
121 DEVMETHOD(device_probe, bm_probe),
122 DEVMETHOD(device_attach, bm_attach),
123 DEVMETHOD(device_detach, bm_detach),
124 DEVMETHOD(device_shutdown, bm_shutdown),
126 /* bus interface, for miibus */
127 DEVMETHOD(bus_print_child, bus_generic_print_child),
128 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
131 DEVMETHOD(miibus_readreg, bm_miibus_readreg),
132 DEVMETHOD(miibus_writereg, bm_miibus_writereg),
133 DEVMETHOD(miibus_statchg, bm_miibus_statchg),
137 static driver_t bm_macio_driver = {
140 sizeof(struct bm_softc)
143 static devclass_t bm_devclass;
145 DRIVER_MODULE(bm, macio, bm_macio_driver, bm_devclass, 0, 0);
146 DRIVER_MODULE(miibus, bm, miibus_driver, miibus_devclass, 0, 0);
149 * MII internal routines
153 * Write to the MII csr, introducing a delay to allow valid
154 * MII clock pulses to be formed
157 bm_miicsr_dwrite(struct bm_softc *sc, u_int16_t val)
159 CSR_WRITE_2(sc, BM_MII_CSR, val);
161 * Assume this is a clock toggle and generate a 1us delay
162 * to cover both MII's 160ns high/low minimum and 400ns
169 * Write a bit to the MII bus.
172 bm_mii_writebit(struct bm_softc *sc, int bit)
176 regval = BM_MII_OENABLE;
178 regval |= BM_MII_DATAOUT;
180 bm_miicsr_dwrite(sc, regval);
181 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
182 bm_miicsr_dwrite(sc, regval);
186 * Read a bit from the MII bus.
189 bm_mii_readbit(struct bm_softc *sc)
191 u_int16_t regval, bitin;
193 /* ~BM_MII_OENABLE */
196 bm_miicsr_dwrite(sc, regval);
197 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
198 bm_miicsr_dwrite(sc, regval);
199 bitin = CSR_READ_2(sc, BM_MII_CSR) & BM_MII_DATAIN;
201 return (bitin == BM_MII_DATAIN);
205 * Sync the PHYs by setting data bit and strobing the clock 32 times.
208 bm_mii_sync(struct bm_softc *sc)
213 regval = BM_MII_OENABLE | BM_MII_DATAOUT;
215 bm_miicsr_dwrite(sc, regval);
216 for (i = 0; i < 32; i++) {
217 bm_miicsr_dwrite(sc, regval | BM_MII_CLK);
218 bm_miicsr_dwrite(sc, regval);
223 * Clock a series of bits through the MII.
226 bm_mii_send(struct bm_softc *sc, u_int32_t bits, int cnt)
230 for (i = (0x1 << (cnt - 1)); i; i >>= 1)
231 bm_mii_writebit(sc, bits & i);
235 * Read a PHY register through the MII.
238 bm_mii_readreg(struct bm_softc *sc, struct bm_mii_frame *frame)
243 * Set up frame for RX.
245 frame->mii_stdelim = BM_MII_STARTDELIM;
246 frame->mii_opcode = BM_MII_READOP;
247 frame->mii_turnaround = 0;
256 * Send command/address info
258 bm_mii_send(sc, frame->mii_stdelim, 2);
259 bm_mii_send(sc, frame->mii_opcode, 2);
260 bm_mii_send(sc, frame->mii_phyaddr, 5);
261 bm_mii_send(sc, frame->mii_regaddr, 5);
266 ack = bm_mii_readbit(sc);
269 * Now try reading data bits. If the ack failed, we still
270 * need to clock through 16 cycles to keep the PHY(s) in sync.
272 for (i = 0x8000; i; i >>= 1) {
273 bit = bm_mii_readbit(sc);
275 frame->mii_data |= i;
279 * Skip through idle bit-times
281 bm_mii_writebit(sc, 0);
282 bm_mii_writebit(sc, 0);
284 return ((ack) ? 1 : 0);
288 * Write to a PHY register through the MII.
291 bm_mii_writereg(struct bm_softc *sc, struct bm_mii_frame *frame)
294 * Set up frame for tx
296 frame->mii_stdelim = BM_MII_STARTDELIM;
297 frame->mii_opcode = BM_MII_WRITEOP;
298 frame->mii_turnaround = BM_MII_TURNAROUND;
301 * Sync the phy and start the bitbang write sequence
305 bm_mii_send(sc, frame->mii_stdelim, 2);
306 bm_mii_send(sc, frame->mii_opcode, 2);
307 bm_mii_send(sc, frame->mii_phyaddr, 5);
308 bm_mii_send(sc, frame->mii_regaddr, 5);
309 bm_mii_send(sc, frame->mii_turnaround, 2);
310 bm_mii_send(sc, frame->mii_data, 16);
315 bm_mii_writebit(sc, 0);
324 bm_miibus_readreg(device_t dev, int phy, int reg)
327 struct bm_mii_frame frame;
329 sc = device_get_softc(dev);
330 bzero(&frame, sizeof(frame));
332 frame.mii_phyaddr = phy;
333 frame.mii_regaddr = reg;
335 bm_mii_readreg(sc, &frame);
337 return (frame.mii_data);
341 bm_miibus_writereg(device_t dev, int phy, int reg, int data)
344 struct bm_mii_frame frame;
346 sc = device_get_softc(dev);
347 bzero(&frame, sizeof(frame));
349 frame.mii_phyaddr = phy;
350 frame.mii_regaddr = reg;
351 frame.mii_data = data;
353 bm_mii_writereg(sc, &frame);
359 bm_miibus_statchg(device_t dev)
361 struct bm_softc *sc = device_get_softc(dev);
365 reg = CSR_READ_2(sc, BM_TX_CONFIG);
366 new_duplex = IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX;
368 if (new_duplex != sc->sc_duplex) {
369 /* Turn off TX MAC while we fiddle its settings */
372 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
373 while (CSR_READ_2(sc, BM_TX_CONFIG) & BM_ENABLE)
377 if (new_duplex && !sc->sc_duplex)
378 reg |= BM_TX_IGNORECOLL | BM_TX_FULLDPX;
379 else if (!new_duplex && sc->sc_duplex)
380 reg &= ~(BM_TX_IGNORECOLL | BM_TX_FULLDPX);
382 if (new_duplex != sc->sc_duplex) {
383 /* Turn TX MAC back on */
386 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
387 sc->sc_duplex = new_duplex;
392 * ifmedia/mii callbacks
395 bm_ifmedia_upd(struct ifnet *ifp)
397 struct bm_softc *sc = ifp->if_softc;
401 error = mii_mediachg(sc->sc_mii);
407 bm_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifm)
409 struct bm_softc *sc = ifp->if_softc;
412 mii_pollstat(sc->sc_mii);
413 ifm->ifm_active = sc->sc_mii->mii_media_active;
414 ifm->ifm_status = sc->sc_mii->mii_media_status;
422 bm_probe(device_t dev)
424 const char *dname = ofw_bus_get_name(dev);
425 const char *dcompat = ofw_bus_get_compat(dev);
428 * BMAC+ cells have a name of "ethernet" and
429 * a compatible property of "bmac+"
431 if (strcmp(dname, "bmac") == 0) {
432 device_set_desc(dev, "Apple BMAC Ethernet Adaptor");
433 } else if (strcmp(dcompat, "bmac+") == 0) {
434 device_set_desc(dev, "Apple BMAC+ Ethernet Adaptor");
442 bm_attach(device_t dev)
447 int error, cellid, i;
448 struct bm_txsoft *txs;
449 struct bm_softc *sc = device_get_softc(dev);
451 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
454 sc->sc_duplex = ~IFM_FDX;
457 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
459 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
461 /* Check for an improved version of Paddington */
462 sc->sc_streaming = 0;
464 node = ofw_bus_get_node(dev);
466 OF_getprop(node, "cell-id", &cellid, sizeof(cellid));
468 sc->sc_streaming = 1;
471 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
472 &sc->sc_memrid, RF_ACTIVE);
473 if (sc->sc_memr == NULL) {
474 device_printf(dev, "Could not alloc chip registers!\n");
478 sc->sc_txdmarid = BM_TXDMA_REGISTERS;
479 sc->sc_rxdmarid = BM_RXDMA_REGISTERS;
481 sc->sc_txdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
482 &sc->sc_txdmarid, RF_ACTIVE);
483 sc->sc_rxdmar = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
484 &sc->sc_rxdmarid, RF_ACTIVE);
486 if (sc->sc_txdmar == NULL || sc->sc_rxdmar == NULL) {
487 device_printf(dev, "Could not map DBDMA registers!\n");
491 error = dbdma_allocate_channel(sc->sc_txdmar, 0, bus_get_dma_tag(dev),
492 BM_MAX_DMA_COMMANDS, &sc->sc_txdma);
493 error += dbdma_allocate_channel(sc->sc_rxdmar, 0, bus_get_dma_tag(dev),
494 BM_MAX_DMA_COMMANDS, &sc->sc_rxdma);
497 device_printf(dev,"Could not allocate DBDMA channel!\n");
501 /* alloc DMA tags and buffers */
502 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
503 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
504 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,
505 NULL, &sc->sc_pdma_tag);
508 device_printf(dev,"Could not allocate DMA tag!\n");
512 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
513 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES,
514 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_rdma_tag);
517 device_printf(dev,"Could not allocate RX DMA channel!\n");
521 error = bus_dma_tag_create(sc->sc_pdma_tag, 1, 0, BUS_SPACE_MAXADDR,
522 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * BM_NTXSEGS, BM_NTXSEGS,
523 MCLBYTES, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdma_tag);
526 device_printf(dev,"Could not allocate TX DMA tag!\n");
530 /* init transmit descriptors */
531 STAILQ_INIT(&sc->sc_txfreeq);
532 STAILQ_INIT(&sc->sc_txdirtyq);
534 /* create TX DMA maps */
536 for (i = 0; i < BM_MAX_TX_PACKETS; i++) {
537 txs = &sc->sc_txsoft[i];
538 txs->txs_mbuf = NULL;
539 error = bus_dmamap_create(sc->sc_tdma_tag, 0, &txs->txs_dmamap);
541 device_printf(sc->sc_dev,
542 "unable to create TX DMA map %d, error = %d\n",
545 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
548 /* Create the receive buffer DMA maps. */
549 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
550 error = bus_dmamap_create(sc->sc_rdma_tag, 0,
551 &sc->sc_rxsoft[i].rxs_dmamap);
553 device_printf(sc->sc_dev,
554 "unable to create RX DMA map %d, error = %d\n",
557 sc->sc_rxsoft[i].rxs_mbuf = NULL;
560 /* alloc interrupt */
561 bm_disable_interrupts(sc);
563 sc->sc_txdmairqid = BM_TXDMA_INTERRUPT;
564 sc->sc_txdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
565 &sc->sc_txdmairqid, RF_ACTIVE);
568 device_printf(dev,"Could not allocate TX interrupt!\n");
572 bus_setup_intr(dev,sc->sc_txdmairq,
573 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_txintr, sc,
576 sc->sc_rxdmairqid = BM_RXDMA_INTERRUPT;
577 sc->sc_rxdmairq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
578 &sc->sc_rxdmairqid, RF_ACTIVE);
581 device_printf(dev,"Could not allocate RX interrupt!\n");
585 bus_setup_intr(dev,sc->sc_rxdmairq,
586 INTR_TYPE_MISC | INTR_MPSAFE | INTR_ENTROPY, NULL, bm_rxintr, sc,
590 * Get the ethernet address from OpenFirmware
592 eaddr = sc->sc_enaddr;
593 OF_getprop(node, "local-mac-address", eaddr, ETHER_ADDR_LEN);
597 * On Apple BMAC controllers, we end up in a weird state of
598 * partially-completed autonegotiation on boot. So we force
599 * autonegotation to try again.
601 error = mii_attach(dev, &sc->sc_miibus, ifp, bm_ifmedia_upd,
602 bm_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
605 device_printf(dev, "attaching PHYs failed\n");
609 /* reset the adapter */
612 sc->sc_mii = device_get_softc(sc->sc_miibus);
614 if_initname(ifp, device_get_name(sc->sc_dev),
615 device_get_unit(sc->sc_dev));
616 ifp->if_mtu = ETHERMTU;
617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
618 ifp->if_start = bm_start;
619 ifp->if_ioctl = bm_ioctl;
620 ifp->if_init = bm_init;
621 IFQ_SET_MAXLEN(&ifp->if_snd, BM_MAX_TX_PACKETS);
622 ifp->if_snd.ifq_drv_maxlen = BM_MAX_TX_PACKETS;
623 IFQ_SET_READY(&ifp->if_snd);
625 /* Attach the interface. */
626 ether_ifattach(ifp, sc->sc_enaddr);
627 ifp->if_hwassist = 0;
633 bm_detach(device_t dev)
635 struct bm_softc *sc = device_get_softc(dev);
641 callout_drain(&sc->sc_tick_ch);
642 ether_ifdetach(sc->sc_ifp);
643 bus_teardown_intr(dev, sc->sc_txdmairq, sc->sc_txihtx);
644 bus_teardown_intr(dev, sc->sc_rxdmairq, sc->sc_rxih);
646 dbdma_free_channel(sc->sc_txdma);
647 dbdma_free_channel(sc->sc_rxdma);
649 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_memrid, sc->sc_memr);
650 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_txdmarid,
652 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rxdmarid,
655 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_txdmairqid,
657 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rxdmairqid,
660 mtx_destroy(&sc->sc_mtx);
667 bm_shutdown(device_t dev)
671 sc = device_get_softc(dev);
681 bm_dummypacket(struct bm_softc *sc)
688 MGETHDR(m, M_DONTWAIT, MT_DATA);
694 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
696 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
697 mtod(m, struct ether_header *)->ether_type = htons(3);
698 mtod(m, unsigned char *)[14] = 0;
699 mtod(m, unsigned char *)[15] = 0;
700 mtod(m, unsigned char *)[16] = 0xE3;
701 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
702 IF_ENQUEUE(&ifp->if_snd, m);
703 bm_start_locked(ifp);
709 struct bm_softc *sc = xsc;
710 struct ifnet *ifp = sc->sc_ifp;
712 int i, prev_stop, new_stop;
717 status = dbdma_get_chan_status(sc->sc_rxdma);
718 if (status & DBDMA_STATUS_DEAD) {
719 dbdma_reset(sc->sc_rxdma);
723 if (!(status & DBDMA_STATUS_RUN)) {
724 device_printf(sc->sc_dev,"Bad RX Interrupt!\n");
729 prev_stop = sc->next_rxdma_slot - 1;
731 prev_stop = sc->rxdma_loop_slot - 1;
739 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_POSTREAD);
741 for (i = sc->next_rxdma_slot; i < BM_MAX_RX_PACKETS; i++) {
742 if (i == sc->rxdma_loop_slot)
748 status = dbdma_get_cmd_status(sc->sc_rxdma, i);
753 m = sc->sc_rxsoft[i].rxs_mbuf;
755 if (bm_add_rxbuf(sc, i)) {
765 m->m_pkthdr.rcvif = ifp;
766 m->m_len -= (dbdma_get_residuals(sc->sc_rxdma, i) + 2);
767 m->m_pkthdr.len = m->m_len;
769 /* Send up the stack */
771 (*ifp->if_input)(ifp, m);
774 /* Clear all fields on this command */
775 bm_add_rxbuf_dma(sc, i);
780 /* Change the last packet we processed to the ring buffer terminator,
781 * and restore a receive buffer to the old terminator */
783 dbdma_insert_stop(sc->sc_rxdma, new_stop);
784 bm_add_rxbuf_dma(sc, prev_stop);
785 if (i < sc->rxdma_loop_slot)
786 sc->next_rxdma_slot = i;
788 sc->next_rxdma_slot = 0;
790 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
792 dbdma_wake(sc->sc_rxdma);
800 struct bm_softc *sc = xsc;
801 struct ifnet *ifp = sc->sc_ifp;
802 struct bm_txsoft *txs;
807 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
808 if (!dbdma_get_cmd_status(sc->sc_txdma, txs->txs_lastdesc))
811 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
812 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
814 if (txs->txs_mbuf != NULL) {
815 m_freem(txs->txs_mbuf);
816 txs->txs_mbuf = NULL;
819 /* Set the first used TXDMA slot to the location of the
820 * STOP/NOP command associated with this packet. */
822 sc->first_used_txdma_slot = txs->txs_stopdesc;
824 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
832 * We freed some descriptors, so reset IFF_DRV_OACTIVE
835 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
836 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
838 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
839 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
840 bm_start_locked(ifp);
847 bm_start(struct ifnet *ifp)
849 struct bm_softc *sc = ifp->if_softc;
852 bm_start_locked(ifp);
857 bm_start_locked(struct ifnet *ifp)
859 struct bm_softc *sc = ifp->if_softc;
860 struct mbuf *mb_head;
865 * We lay out our DBDMA program in the following manner:
868 * OUTPUT_LAST (+ Interrupt)
871 * To extend the channel, we append a new program,
872 * then replace STOP with NOP and wake the channel.
873 * If we stalled on the STOP already, the program proceeds,
874 * if not it will sail through the NOP.
877 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
878 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
883 prev_stop = sc->next_txdma_slot - 1;
885 if (bm_encap(sc, &mb_head)) {
886 /* Put the packet back and stop */
887 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
888 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
892 dbdma_insert_nop(sc->sc_txdma, prev_stop);
896 BPF_MTAP(ifp, mb_head);
899 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
902 dbdma_wake(sc->sc_txdma);
903 sc->sc_wdog_timer = 5;
908 bm_encap(struct bm_softc *sc, struct mbuf **m_head)
910 bus_dma_segment_t segs[BM_NTXSEGS];
911 struct bm_txsoft *txs;
913 int nsegs = BM_NTXSEGS;
918 /* Limit the command size to the number of free DBDMA slots */
920 if (sc->next_txdma_slot >= sc->first_used_txdma_slot)
921 nsegs = BM_MAX_DMA_COMMANDS - 2 - sc->next_txdma_slot +
922 sc->first_used_txdma_slot; /* -2 for branch and indexing */
924 nsegs = sc->first_used_txdma_slot - sc->next_txdma_slot;
926 /* Remove one slot for the STOP/NOP terminator */
929 if (nsegs > BM_NTXSEGS)
932 /* Get a work queue entry. */
933 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
934 /* Ran out of descriptors. */
938 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag, txs->txs_dmamap,
939 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
941 if (error == EFBIG) {
942 m = m_collapse(*m_head, M_DONTWAIT, nsegs);
950 error = bus_dmamap_load_mbuf_sg(sc->sc_tdma_tag,
951 txs->txs_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
957 } else if (error != 0)
966 txs->txs_ndescs = nsegs;
967 txs->txs_firstdesc = sc->next_txdma_slot;
969 for (i = 0; i < nsegs; i++) {
970 /* Loop back to the beginning if this is our last slot */
971 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1))
972 branch_type = DBDMA_ALWAYS;
974 branch_type = DBDMA_NEVER;
977 txs->txs_lastdesc = sc->next_txdma_slot;
979 dbdma_insert_command(sc->sc_txdma, sc->next_txdma_slot++,
980 (i + 1 < nsegs) ? DBDMA_OUTPUT_MORE : DBDMA_OUTPUT_LAST,
981 0, segs[i].ds_addr, segs[i].ds_len,
982 (i + 1 < nsegs) ? DBDMA_NEVER : DBDMA_ALWAYS,
983 branch_type, DBDMA_NEVER, 0);
985 if (branch_type == DBDMA_ALWAYS)
986 sc->next_txdma_slot = 0;
989 /* We have a corner case where the STOP command is the last slot,
990 * but you can't branch in STOP commands. So add a NOP branch here
991 * and the STOP in slot 0. */
993 if (sc->next_txdma_slot == (BM_MAX_DMA_COMMANDS - 1)) {
994 dbdma_insert_branch(sc->sc_txdma, sc->next_txdma_slot, 0);
995 sc->next_txdma_slot = 0;
998 txs->txs_stopdesc = sc->next_txdma_slot;
999 dbdma_insert_stop(sc->sc_txdma, sc->next_txdma_slot++);
1001 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1002 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1003 txs->txs_mbuf = *m_head;
1009 bm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1011 struct bm_softc *sc = ifp->if_softc;
1012 struct ifreq *ifr = (struct ifreq *)data;
1020 if ((ifp->if_flags & IFF_UP) != 0) {
1021 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1022 ((ifp->if_flags ^ sc->sc_ifpflags) &
1023 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
1027 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1029 sc->sc_ifpflags = ifp->if_flags;
1039 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
1042 error = ether_ioctl(ifp, cmd, data);
1050 bm_setladrf(struct bm_softc *sc)
1052 struct ifnet *ifp = sc->sc_ifp;
1053 struct ifmultiaddr *inm;
1058 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS;
1060 /* Turn off RX MAC while we fiddle its settings */
1061 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1062 while (CSR_READ_2(sc, BM_RX_CONFIG) & BM_ENABLE)
1065 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1068 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1072 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1074 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1078 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
1079 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1081 /* Clear the hash table. */
1082 memset(hash, 0, sizeof(hash));
1084 if_maddr_rlock(ifp);
1085 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
1086 if (inm->ifma_addr->sa_family != AF_LINK)
1088 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
1089 inm->ifma_addr), ETHER_ADDR_LEN);
1091 /* We just want the 6 most significant bits */
1094 /* Set the corresponding bit in the filter. */
1095 hash[crc >> 4] |= 1 << (crc & 0xf);
1097 if_maddr_runlock(ifp);
1100 /* Write out new hash table */
1101 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
1102 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
1103 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
1104 CSR_WRITE_2(sc, BM_HASHTAB3, hash[3]);
1106 /* And turn the RX MAC back on, this time with the hash bit set */
1107 reg |= BM_HASH_FILTER_ENABLE;
1108 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1110 while (!(CSR_READ_2(sc, BM_RX_CONFIG) & BM_HASH_FILTER_ENABLE))
1113 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1115 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1121 struct bm_softc *sc = xsc;
1129 bm_chip_setup(struct bm_softc *sc)
1132 uint16_t *eaddr_sect;
1134 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1135 dbdma_stop(sc->sc_txdma);
1136 dbdma_stop(sc->sc_rxdma);
1139 CSR_WRITE_2(sc, BM_RX_RESET, 0x0000);
1140 CSR_WRITE_2(sc, BM_TX_RESET, 0x0001);
1143 reg = CSR_READ_2(sc, BM_TX_RESET);
1144 } while (reg & 0x0001);
1146 /* Some random junk. OS X uses the system time. We use
1147 * the low 16 bits of the MAC address. */
1148 CSR_WRITE_2(sc, BM_TX_RANDSEED, eaddr_sect[2]);
1150 /* Enable transmit */
1151 reg = CSR_READ_2(sc, BM_TX_IFC);
1153 CSR_WRITE_2(sc, BM_TX_IFC, reg);
1155 CSR_READ_2(sc, BM_TX_PEAKCNT);
1159 bm_stop(struct bm_softc *sc)
1161 struct bm_txsoft *txs;
1164 /* Disable TX and RX MACs */
1165 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1167 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1169 reg = CSR_READ_2(sc, BM_RX_CONFIG);
1171 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1175 /* Stop DMA engine */
1176 dbdma_stop(sc->sc_rxdma);
1177 dbdma_stop(sc->sc_txdma);
1178 sc->next_rxdma_slot = 0;
1179 sc->rxdma_loop_slot = 0;
1181 /* Disable interrupts */
1182 bm_disable_interrupts(sc);
1184 /* Don't worry about pending transmits anymore */
1185 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1186 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1187 if (txs->txs_ndescs != 0) {
1188 bus_dmamap_sync(sc->sc_tdma_tag, txs->txs_dmamap,
1189 BUS_DMASYNC_POSTWRITE);
1190 bus_dmamap_unload(sc->sc_tdma_tag, txs->txs_dmamap);
1191 if (txs->txs_mbuf != NULL) {
1192 m_freem(txs->txs_mbuf);
1193 txs->txs_mbuf = NULL;
1196 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1199 /* And we're down */
1200 sc->sc_ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1201 sc->sc_wdog_timer = 0;
1202 callout_stop(&sc->sc_tick_ch);
1206 bm_init_locked(struct bm_softc *sc)
1209 uint16_t *eaddr_sect;
1210 struct bm_rxsoft *rxs;
1213 eaddr_sect = (uint16_t *)(sc->sc_enaddr);
1215 /* Zero RX slot info and stop DMA */
1216 dbdma_stop(sc->sc_rxdma);
1217 dbdma_stop(sc->sc_txdma);
1218 sc->next_rxdma_slot = 0;
1219 sc->rxdma_loop_slot = 0;
1221 /* Initialize TX/RX DBDMA programs */
1222 dbdma_insert_stop(sc->sc_rxdma, 0);
1223 dbdma_insert_stop(sc->sc_txdma, 0);
1224 dbdma_set_current_cmd(sc->sc_rxdma, 0);
1225 dbdma_set_current_cmd(sc->sc_txdma, 0);
1227 sc->next_rxdma_slot = 0;
1228 sc->next_txdma_slot = 1;
1229 sc->first_used_txdma_slot = 0;
1231 for (i = 0; i < BM_MAX_RX_PACKETS; i++) {
1232 rxs = &sc->sc_rxsoft[i];
1233 rxs->dbdma_slot = i;
1235 if (rxs->rxs_mbuf == NULL) {
1236 bm_add_rxbuf(sc, i);
1238 if (rxs->rxs_mbuf == NULL) {
1239 /* If we can't add anymore, mark the problem */
1240 rxs->dbdma_slot = -1;
1246 bm_add_rxbuf_dma(sc, i);
1250 * Now terminate the RX ring buffer, and follow with the loop to
1253 dbdma_insert_stop(sc->sc_rxdma, i - 1);
1254 dbdma_insert_branch(sc->sc_rxdma, i, 0);
1255 sc->rxdma_loop_slot = i;
1257 /* Now add in the first element of the RX DMA chain */
1258 bm_add_rxbuf_dma(sc, 0);
1260 dbdma_sync_commands(sc->sc_rxdma, BUS_DMASYNC_PREWRITE);
1261 dbdma_sync_commands(sc->sc_txdma, BUS_DMASYNC_PREWRITE);
1263 /* Zero collision counters */
1264 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1265 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1266 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1267 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1269 /* Zero receive counters */
1270 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1271 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1272 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1273 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1274 CSR_WRITE_2(sc, BM_RXCV, 0);
1276 /* Prime transmit */
1277 CSR_WRITE_2(sc, BM_TX_THRESH, 0xff);
1279 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0);
1280 CSR_WRITE_2(sc, BM_TXFIFO_CSR, 0x0001);
1283 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0);
1284 CSR_WRITE_2(sc, BM_RXFIFO_CSR, 0x0001);
1286 /* Clear status reg */
1287 CSR_READ_2(sc, BM_STATUS);
1289 /* Zero hash filters */
1290 CSR_WRITE_2(sc, BM_HASHTAB0, 0);
1291 CSR_WRITE_2(sc, BM_HASHTAB1, 0);
1292 CSR_WRITE_2(sc, BM_HASHTAB2, 0);
1293 CSR_WRITE_2(sc, BM_HASHTAB3, 0);
1295 /* Write MAC address to chip */
1296 CSR_WRITE_2(sc, BM_MACADDR0, eaddr_sect[0]);
1297 CSR_WRITE_2(sc, BM_MACADDR1, eaddr_sect[1]);
1298 CSR_WRITE_2(sc, BM_MACADDR2, eaddr_sect[2]);
1300 /* Final receive engine setup */
1301 reg = BM_CRC_ENABLE | BM_REJECT_OWN_PKTS | BM_HASH_FILTER_ENABLE;
1302 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
1304 /* Now turn it all on! */
1305 dbdma_reset(sc->sc_rxdma);
1306 dbdma_reset(sc->sc_txdma);
1308 /* Enable RX and TX MACs. Setting the address filter has
1309 * the side effect of enabling the RX MAC. */
1312 reg = CSR_READ_2(sc, BM_TX_CONFIG);
1314 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
1317 * Enable interrupts, unwedge the controller with a dummy packet,
1318 * and nudge the DMA queue.
1320 bm_enable_interrupts(sc);
1322 dbdma_wake(sc->sc_rxdma); /* Nudge RXDMA */
1324 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
1325 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1326 sc->sc_ifpflags = sc->sc_ifp->if_flags;
1328 /* Resync PHY and MAC states */
1329 sc->sc_mii = device_get_softc(sc->sc_miibus);
1330 sc->sc_duplex = ~IFM_FDX;
1331 mii_mediachg(sc->sc_mii);
1333 /* Start the one second timer. */
1334 sc->sc_wdog_timer = 0;
1335 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1341 struct bm_softc *sc = arg;
1343 /* Read error counters */
1344 sc->sc_ifp->if_collisions += CSR_READ_2(sc, BM_TX_NCCNT) +
1345 CSR_READ_2(sc, BM_TX_FCCNT) + CSR_READ_2(sc, BM_TX_EXCNT) +
1346 CSR_READ_2(sc, BM_TX_LTCNT);
1348 sc->sc_ifp->if_ierrors += CSR_READ_2(sc, BM_RX_LECNT) +
1349 CSR_READ_2(sc, BM_RX_AECNT) + CSR_READ_2(sc, BM_RX_FECNT);
1351 /* Zero collision counters */
1352 CSR_WRITE_2(sc, BM_TX_NCCNT, 0);
1353 CSR_WRITE_2(sc, BM_TX_FCCNT, 0);
1354 CSR_WRITE_2(sc, BM_TX_EXCNT, 0);
1355 CSR_WRITE_2(sc, BM_TX_LTCNT, 0);
1357 /* Zero receive counters */
1358 CSR_WRITE_2(sc, BM_RX_FRCNT, 0);
1359 CSR_WRITE_2(sc, BM_RX_LECNT, 0);
1360 CSR_WRITE_2(sc, BM_RX_AECNT, 0);
1361 CSR_WRITE_2(sc, BM_RX_FECNT, 0);
1362 CSR_WRITE_2(sc, BM_RXCV, 0);
1364 /* Check for link changes and run watchdog */
1365 mii_tick(sc->sc_mii);
1366 bm_miibus_statchg(sc->sc_dev);
1368 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
1369 callout_reset(&sc->sc_tick_ch, hz, bm_tick, sc);
1374 device_printf(sc->sc_dev, "device timeout\n");
1380 bm_add_rxbuf(struct bm_softc *sc, int idx)
1382 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1384 bus_dma_segment_t segs[1];
1387 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1390 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1392 if (rxs->rxs_mbuf != NULL) {
1393 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap,
1394 BUS_DMASYNC_POSTREAD);
1395 bus_dmamap_unload(sc->sc_rdma_tag, rxs->rxs_dmamap);
1398 error = bus_dmamap_load_mbuf_sg(sc->sc_rdma_tag, rxs->rxs_dmamap, m,
1399 segs, &nsegs, BUS_DMA_NOWAIT);
1401 device_printf(sc->sc_dev,
1402 "cannot load RS DMA map %d, error = %d\n", idx, error);
1406 /* If nsegs is wrong then the stack is corrupt. */
1408 ("%s: too many DMA segments (%d)", __func__, nsegs));
1410 rxs->segment = segs[0];
1412 bus_dmamap_sync(sc->sc_rdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1418 bm_add_rxbuf_dma(struct bm_softc *sc, int idx)
1420 struct bm_rxsoft *rxs = &sc->sc_rxsoft[idx];
1422 dbdma_insert_command(sc->sc_rxdma, idx, DBDMA_INPUT_LAST, 0,
1423 rxs->segment.ds_addr, rxs->segment.ds_len, DBDMA_ALWAYS,
1424 DBDMA_NEVER, DBDMA_NEVER, 0);
1430 bm_enable_interrupts(struct bm_softc *sc)
1432 CSR_WRITE_2(sc, BM_INTR_DISABLE,
1433 (sc->sc_streaming) ? BM_INTR_NONE : BM_INTR_NORMAL);
1437 bm_disable_interrupts(struct bm_softc *sc)
1439 CSR_WRITE_2(sc, BM_INTR_DISABLE, BM_INTR_NONE);