2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #define BXE_DRIVER_VERSION "1.78.91"
34 #include "ecore_init.h"
35 #include "ecore_init_ops.h"
37 #include "57710_int_offsets.h"
38 #include "57711_int_offsets.h"
39 #include "57712_int_offsets.h"
42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
43 * explicitly here for older kernels that don't include this changeset.
46 #define CTLTYPE_U64 CTLTYPE_QUAD
47 #define sysctl_handle_64 sysctl_handle_quad
51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
52 * here as zero(0) for older kernels that don't include this changeset
53 * thereby masking the functionality.
56 #define CSUM_TCP_IPV6 0
57 #define CSUM_UDP_IPV6 0
61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap
62 * for older kernels that don't include this changeset.
64 #if __FreeBSD_version < 900035
65 #define pci_find_cap pci_find_extcap
68 #define BXE_DEF_SB_ATT_IDX 0x0001
69 #define BXE_DEF_SB_IDX 0x0002
72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
73 * function HW initialization.
75 #define FLR_WAIT_USEC 10000 /* 10 msecs */
76 #define FLR_WAIT_INTERVAL 50 /* usecs */
77 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
79 struct pbf_pN_buf_regs {
86 struct pbf_pN_cmd_regs {
93 * PCI Device ID Table used by bxe_probe().
95 #define BXE_DEVDESC_MAX 64
96 static struct bxe_device_type bxe_devs[] = {
100 PCI_ANY_ID, PCI_ANY_ID,
101 "QLogic NetXtreme II BCM57710 10GbE"
106 PCI_ANY_ID, PCI_ANY_ID,
107 "QLogic NetXtreme II BCM57711 10GbE"
112 PCI_ANY_ID, PCI_ANY_ID,
113 "QLogic NetXtreme II BCM57711E 10GbE"
118 PCI_ANY_ID, PCI_ANY_ID,
119 "QLogic NetXtreme II BCM57712 10GbE"
124 PCI_ANY_ID, PCI_ANY_ID,
125 "QLogic NetXtreme II BCM57712 MF 10GbE"
130 PCI_ANY_ID, PCI_ANY_ID,
131 "QLogic NetXtreme II BCM57800 10GbE"
136 PCI_ANY_ID, PCI_ANY_ID,
137 "QLogic NetXtreme II BCM57800 MF 10GbE"
142 PCI_ANY_ID, PCI_ANY_ID,
143 "QLogic NetXtreme II BCM57810 10GbE"
148 PCI_ANY_ID, PCI_ANY_ID,
149 "QLogic NetXtreme II BCM57810 MF 10GbE"
154 PCI_ANY_ID, PCI_ANY_ID,
155 "QLogic NetXtreme II BCM57811 10GbE"
160 PCI_ANY_ID, PCI_ANY_ID,
161 "QLogic NetXtreme II BCM57811 MF 10GbE"
166 PCI_ANY_ID, PCI_ANY_ID,
167 "QLogic NetXtreme II BCM57840 4x10GbE"
172 PCI_ANY_ID, PCI_ANY_ID,
173 "QLogic NetXtreme II BCM57840 MF 10GbE"
180 MALLOC_DECLARE(M_BXE_ILT);
181 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
184 * FreeBSD device entry points.
186 static int bxe_probe(device_t);
187 static int bxe_attach(device_t);
188 static int bxe_detach(device_t);
189 static int bxe_shutdown(device_t);
192 * FreeBSD KLD module/device interface event handler method.
194 static device_method_t bxe_methods[] = {
195 /* Device interface (device_if.h) */
196 DEVMETHOD(device_probe, bxe_probe),
197 DEVMETHOD(device_attach, bxe_attach),
198 DEVMETHOD(device_detach, bxe_detach),
199 DEVMETHOD(device_shutdown, bxe_shutdown),
200 /* Bus interface (bus_if.h) */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
207 * FreeBSD KLD Module data declaration
209 static driver_t bxe_driver = {
210 "bxe", /* module name */
211 bxe_methods, /* event handler */
212 sizeof(struct bxe_softc) /* extra data */
216 * FreeBSD dev class is needed to manage dev instances and
217 * to associate with a bus type
219 static devclass_t bxe_devclass;
221 MODULE_DEPEND(bxe, pci, 1, 1, 1);
222 MODULE_DEPEND(bxe, ether, 1, 1, 1);
223 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
225 /* resources needed for unloading a previously loaded device */
227 #define BXE_PREV_WAIT_NEEDED 1
228 struct mtx bxe_prev_mtx;
229 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
230 struct bxe_prev_list_node {
231 LIST_ENTRY(bxe_prev_list_node) node;
235 uint8_t aer; /* XXX automatic error recovery */
238 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
240 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
242 /* Tunable device values... */
244 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
247 unsigned long bxe_debug = 0;
248 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug);
249 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN),
250 &bxe_debug, 0, "Debug logging mode");
252 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
253 static int bxe_interrupt_mode = INTR_MODE_MSIX;
254 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode);
255 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
258 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
259 static int bxe_queue_count = 4;
260 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
261 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
262 &bxe_queue_count, 0, "Multi-Queue queue count");
264 /* max number of buffers per queue (default RX_BD_USABLE) */
265 static int bxe_max_rx_bufs = 0;
266 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs);
267 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
268 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
270 /* Host interrupt coalescing RX tick timer (usecs) */
271 static int bxe_hc_rx_ticks = 25;
272 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks);
273 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
274 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
276 /* Host interrupt coalescing TX tick timer (usecs) */
277 static int bxe_hc_tx_ticks = 50;
278 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks);
279 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
280 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
282 /* Maximum number of Rx packets to process at a time */
283 static int bxe_rx_budget = 0xffffffff;
284 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget);
285 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN,
286 &bxe_rx_budget, 0, "Rx processing budget");
288 /* Maximum LRO aggregation size */
289 static int bxe_max_aggregation_size = 0;
290 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size);
291 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
292 &bxe_max_aggregation_size, 0, "max aggregation size");
294 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
295 static int bxe_mrrs = -1;
296 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
297 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
298 &bxe_mrrs, 0, "PCIe maximum read request size");
300 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
301 static int bxe_autogreeen = 0;
302 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen);
303 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
304 &bxe_autogreeen, 0, "AutoGrEEEn support");
306 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
307 static int bxe_udp_rss = 0;
308 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss);
309 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
310 &bxe_udp_rss, 0, "UDP RSS support");
313 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
315 #define STATS_OFFSET32(stat_name) \
316 (offsetof(struct bxe_eth_stats, stat_name) / 4)
318 #define Q_STATS_OFFSET32(stat_name) \
319 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
321 static const struct {
325 #define STATS_FLAGS_PORT 1
326 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */
327 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
328 char string[STAT_NAME_LEN];
329 } bxe_eth_stats_arr[] = {
330 { STATS_OFFSET32(total_bytes_received_hi),
331 8, STATS_FLAGS_BOTH, "rx_bytes" },
332 { STATS_OFFSET32(error_bytes_received_hi),
333 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
334 { STATS_OFFSET32(total_unicast_packets_received_hi),
335 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
336 { STATS_OFFSET32(total_multicast_packets_received_hi),
337 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
338 { STATS_OFFSET32(total_broadcast_packets_received_hi),
339 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
340 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
341 8, STATS_FLAGS_PORT, "rx_crc_errors" },
342 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
343 8, STATS_FLAGS_PORT, "rx_align_errors" },
344 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
345 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
346 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
347 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
348 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
349 8, STATS_FLAGS_PORT, "rx_fragments" },
350 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
351 8, STATS_FLAGS_PORT, "rx_jabbers" },
352 { STATS_OFFSET32(no_buff_discard_hi),
353 8, STATS_FLAGS_BOTH, "rx_discards" },
354 { STATS_OFFSET32(mac_filter_discard),
355 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
356 { STATS_OFFSET32(mf_tag_discard),
357 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
358 { STATS_OFFSET32(pfc_frames_received_hi),
359 8, STATS_FLAGS_PORT, "pfc_frames_received" },
360 { STATS_OFFSET32(pfc_frames_sent_hi),
361 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
362 { STATS_OFFSET32(brb_drop_hi),
363 8, STATS_FLAGS_PORT, "rx_brb_discard" },
364 { STATS_OFFSET32(brb_truncate_hi),
365 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
366 { STATS_OFFSET32(pause_frames_received_hi),
367 8, STATS_FLAGS_PORT, "rx_pause_frames" },
368 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
369 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
370 { STATS_OFFSET32(nig_timer_max),
371 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
372 { STATS_OFFSET32(total_bytes_transmitted_hi),
373 8, STATS_FLAGS_BOTH, "tx_bytes" },
374 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
375 8, STATS_FLAGS_PORT, "tx_error_bytes" },
376 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
377 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
378 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
379 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
380 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
381 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
382 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
383 8, STATS_FLAGS_PORT, "tx_mac_errors" },
384 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
385 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
386 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
387 8, STATS_FLAGS_PORT, "tx_single_collisions" },
388 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
389 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
390 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
391 8, STATS_FLAGS_PORT, "tx_deferred" },
392 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
393 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
394 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
395 8, STATS_FLAGS_PORT, "tx_late_collisions" },
396 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
397 8, STATS_FLAGS_PORT, "tx_total_collisions" },
398 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
399 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
400 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
401 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
402 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
403 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
404 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
405 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
406 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
407 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
408 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
409 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
410 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
411 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
412 { STATS_OFFSET32(pause_frames_sent_hi),
413 8, STATS_FLAGS_PORT, "tx_pause_frames" },
414 { STATS_OFFSET32(total_tpa_aggregations_hi),
415 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
416 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
417 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
418 { STATS_OFFSET32(total_tpa_bytes_hi),
419 8, STATS_FLAGS_FUNC, "tpa_bytes"},
420 { STATS_OFFSET32(eee_tx_lpi),
421 4, STATS_FLAGS_PORT, "eee_tx_lpi"},
422 { STATS_OFFSET32(rx_calls),
423 4, STATS_FLAGS_FUNC, "rx_calls"},
424 { STATS_OFFSET32(rx_pkts),
425 4, STATS_FLAGS_FUNC, "rx_pkts"},
426 { STATS_OFFSET32(rx_tpa_pkts),
427 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
428 { STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
429 4, STATS_FLAGS_FUNC, "rx_erroneous_jumbo_sge_pkts"},
430 { STATS_OFFSET32(rx_bxe_service_rxsgl),
431 4, STATS_FLAGS_FUNC, "rx_bxe_service_rxsgl"},
432 { STATS_OFFSET32(rx_jumbo_sge_pkts),
433 4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"},
434 { STATS_OFFSET32(rx_soft_errors),
435 4, STATS_FLAGS_FUNC, "rx_soft_errors"},
436 { STATS_OFFSET32(rx_hw_csum_errors),
437 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
438 { STATS_OFFSET32(rx_ofld_frames_csum_ip),
439 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
440 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
441 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
442 { STATS_OFFSET32(rx_budget_reached),
443 4, STATS_FLAGS_FUNC, "rx_budget_reached"},
444 { STATS_OFFSET32(tx_pkts),
445 4, STATS_FLAGS_FUNC, "tx_pkts"},
446 { STATS_OFFSET32(tx_soft_errors),
447 4, STATS_FLAGS_FUNC, "tx_soft_errors"},
448 { STATS_OFFSET32(tx_ofld_frames_csum_ip),
449 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
450 { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
451 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
452 { STATS_OFFSET32(tx_ofld_frames_csum_udp),
453 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
454 { STATS_OFFSET32(tx_ofld_frames_lso),
455 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
456 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
457 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
458 { STATS_OFFSET32(tx_encap_failures),
459 4, STATS_FLAGS_FUNC, "tx_encap_failures"},
460 { STATS_OFFSET32(tx_hw_queue_full),
461 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
462 { STATS_OFFSET32(tx_hw_max_queue_depth),
463 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
464 { STATS_OFFSET32(tx_dma_mapping_failure),
465 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
466 { STATS_OFFSET32(tx_max_drbr_queue_depth),
467 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
468 { STATS_OFFSET32(tx_window_violation_std),
469 4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
470 { STATS_OFFSET32(tx_window_violation_tso),
471 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
472 { STATS_OFFSET32(tx_chain_lost_mbuf),
473 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
474 { STATS_OFFSET32(tx_frames_deferred),
475 4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
476 { STATS_OFFSET32(tx_queue_xoff),
477 4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
478 { STATS_OFFSET32(mbuf_defrag_attempts),
479 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
480 { STATS_OFFSET32(mbuf_defrag_failures),
481 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
482 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
483 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
484 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
485 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
486 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
487 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
488 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
489 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
490 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
491 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
492 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
493 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
494 { STATS_OFFSET32(mbuf_alloc_tx),
495 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
496 { STATS_OFFSET32(mbuf_alloc_rx),
497 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
498 { STATS_OFFSET32(mbuf_alloc_sge),
499 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
500 { STATS_OFFSET32(mbuf_alloc_tpa),
501 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"},
502 { STATS_OFFSET32(tx_queue_full_return),
503 4, STATS_FLAGS_FUNC, "tx_queue_full_return"},
504 { STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
505 4, STATS_FLAGS_FUNC, "bxe_tx_mq_sc_state_failures"},
506 { STATS_OFFSET32(tx_request_link_down_failures),
507 4, STATS_FLAGS_FUNC, "tx_request_link_down_failures"},
508 { STATS_OFFSET32(bd_avail_too_less_failures),
509 4, STATS_FLAGS_FUNC, "bd_avail_too_less_failures"},
510 { STATS_OFFSET32(tx_mq_not_empty),
511 4, STATS_FLAGS_FUNC, "tx_mq_not_empty"},
512 { STATS_OFFSET32(nsegs_path1_errors),
513 4, STATS_FLAGS_FUNC, "nsegs_path1_errors"},
514 { STATS_OFFSET32(nsegs_path2_errors),
515 4, STATS_FLAGS_FUNC, "nsegs_path2_errors"}
520 static const struct {
523 char string[STAT_NAME_LEN];
524 } bxe_eth_q_stats_arr[] = {
525 { Q_STATS_OFFSET32(total_bytes_received_hi),
527 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
528 8, "rx_ucast_packets" },
529 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
530 8, "rx_mcast_packets" },
531 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
532 8, "rx_bcast_packets" },
533 { Q_STATS_OFFSET32(no_buff_discard_hi),
535 { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
537 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
538 8, "tx_ucast_packets" },
539 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
540 8, "tx_mcast_packets" },
541 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
542 8, "tx_bcast_packets" },
543 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
544 8, "tpa_aggregations" },
545 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
546 8, "tpa_aggregated_frames"},
547 { Q_STATS_OFFSET32(total_tpa_bytes_hi),
549 { Q_STATS_OFFSET32(rx_calls),
551 { Q_STATS_OFFSET32(rx_pkts),
553 { Q_STATS_OFFSET32(rx_tpa_pkts),
555 { Q_STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts),
556 4, "rx_erroneous_jumbo_sge_pkts"},
557 { Q_STATS_OFFSET32(rx_bxe_service_rxsgl),
558 4, "rx_bxe_service_rxsgl"},
559 { Q_STATS_OFFSET32(rx_jumbo_sge_pkts),
560 4, "rx_jumbo_sge_pkts"},
561 { Q_STATS_OFFSET32(rx_soft_errors),
562 4, "rx_soft_errors"},
563 { Q_STATS_OFFSET32(rx_hw_csum_errors),
564 4, "rx_hw_csum_errors"},
565 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
566 4, "rx_ofld_frames_csum_ip"},
567 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
568 4, "rx_ofld_frames_csum_tcp_udp"},
569 { Q_STATS_OFFSET32(rx_budget_reached),
570 4, "rx_budget_reached"},
571 { Q_STATS_OFFSET32(tx_pkts),
573 { Q_STATS_OFFSET32(tx_soft_errors),
574 4, "tx_soft_errors"},
575 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
576 4, "tx_ofld_frames_csum_ip"},
577 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
578 4, "tx_ofld_frames_csum_tcp"},
579 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
580 4, "tx_ofld_frames_csum_udp"},
581 { Q_STATS_OFFSET32(tx_ofld_frames_lso),
582 4, "tx_ofld_frames_lso"},
583 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
584 4, "tx_ofld_frames_lso_hdr_splits"},
585 { Q_STATS_OFFSET32(tx_encap_failures),
586 4, "tx_encap_failures"},
587 { Q_STATS_OFFSET32(tx_hw_queue_full),
588 4, "tx_hw_queue_full"},
589 { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
590 4, "tx_hw_max_queue_depth"},
591 { Q_STATS_OFFSET32(tx_dma_mapping_failure),
592 4, "tx_dma_mapping_failure"},
593 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
594 4, "tx_max_drbr_queue_depth"},
595 { Q_STATS_OFFSET32(tx_window_violation_std),
596 4, "tx_window_violation_std"},
597 { Q_STATS_OFFSET32(tx_window_violation_tso),
598 4, "tx_window_violation_tso"},
599 { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
600 4, "tx_chain_lost_mbuf"},
601 { Q_STATS_OFFSET32(tx_frames_deferred),
602 4, "tx_frames_deferred"},
603 { Q_STATS_OFFSET32(tx_queue_xoff),
605 { Q_STATS_OFFSET32(mbuf_defrag_attempts),
606 4, "mbuf_defrag_attempts"},
607 { Q_STATS_OFFSET32(mbuf_defrag_failures),
608 4, "mbuf_defrag_failures"},
609 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
610 4, "mbuf_rx_bd_alloc_failed"},
611 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
612 4, "mbuf_rx_bd_mapping_failed"},
613 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
614 4, "mbuf_rx_tpa_alloc_failed"},
615 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
616 4, "mbuf_rx_tpa_mapping_failed"},
617 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
618 4, "mbuf_rx_sge_alloc_failed"},
619 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
620 4, "mbuf_rx_sge_mapping_failed"},
621 { Q_STATS_OFFSET32(mbuf_alloc_tx),
623 { Q_STATS_OFFSET32(mbuf_alloc_rx),
625 { Q_STATS_OFFSET32(mbuf_alloc_sge),
626 4, "mbuf_alloc_sge"},
627 { Q_STATS_OFFSET32(mbuf_alloc_tpa),
628 4, "mbuf_alloc_tpa"},
629 { Q_STATS_OFFSET32(tx_queue_full_return),
630 4, "tx_queue_full_return"},
631 { Q_STATS_OFFSET32(bxe_tx_mq_sc_state_failures),
632 4, "bxe_tx_mq_sc_state_failures"},
633 { Q_STATS_OFFSET32(tx_request_link_down_failures),
634 4, "tx_request_link_down_failures"},
635 { Q_STATS_OFFSET32(bd_avail_too_less_failures),
636 4, "bd_avail_too_less_failures"},
637 { Q_STATS_OFFSET32(tx_mq_not_empty),
638 4, "tx_mq_not_empty"},
639 { Q_STATS_OFFSET32(nsegs_path1_errors),
640 4, "nsegs_path1_errors"},
641 { Q_STATS_OFFSET32(nsegs_path2_errors),
642 4, "nsegs_path2_errors"}
647 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
648 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
651 static void bxe_cmng_fns_init(struct bxe_softc *sc,
654 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
655 static void storm_memset_cmng(struct bxe_softc *sc,
656 struct cmng_init *cmng,
658 static void bxe_set_reset_global(struct bxe_softc *sc);
659 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
660 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
662 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
663 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
666 static void bxe_int_disable(struct bxe_softc *sc);
667 static int bxe_release_leader_lock(struct bxe_softc *sc);
668 static void bxe_pf_disable(struct bxe_softc *sc);
669 static void bxe_free_fp_buffers(struct bxe_softc *sc);
670 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
671 struct bxe_fastpath *fp,
674 uint16_t rx_sge_prod);
675 static void bxe_link_report_locked(struct bxe_softc *sc);
676 static void bxe_link_report(struct bxe_softc *sc);
677 static void bxe_link_status_update(struct bxe_softc *sc);
678 static void bxe_periodic_callout_func(void *xsc);
679 static void bxe_periodic_start(struct bxe_softc *sc);
680 static void bxe_periodic_stop(struct bxe_softc *sc);
681 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
684 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
686 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
688 static uint8_t bxe_txeof(struct bxe_softc *sc,
689 struct bxe_fastpath *fp);
690 static void bxe_task_fp(struct bxe_fastpath *fp);
691 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
694 static int bxe_alloc_mem(struct bxe_softc *sc);
695 static void bxe_free_mem(struct bxe_softc *sc);
696 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
697 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
698 static int bxe_interrupt_attach(struct bxe_softc *sc);
699 static void bxe_interrupt_detach(struct bxe_softc *sc);
700 static void bxe_set_rx_mode(struct bxe_softc *sc);
701 static int bxe_init_locked(struct bxe_softc *sc);
702 static int bxe_stop_locked(struct bxe_softc *sc);
703 static __noinline int bxe_nic_load(struct bxe_softc *sc,
705 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
706 uint32_t unload_mode,
709 static void bxe_handle_sp_tq(void *context, int pending);
710 static void bxe_handle_fp_tq(void *context, int pending);
712 static int bxe_add_cdev(struct bxe_softc *sc);
713 static void bxe_del_cdev(struct bxe_softc *sc);
714 int bxe_grc_dump(struct bxe_softc *sc);
715 static int bxe_alloc_buf_rings(struct bxe_softc *sc);
716 static void bxe_free_buf_rings(struct bxe_softc *sc);
718 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
720 calc_crc32(uint8_t *crc32_packet,
721 uint32_t crc32_length,
730 uint8_t current_byte = 0;
731 uint32_t crc32_result = crc32_seed;
732 const uint32_t CRC32_POLY = 0x1edc6f41;
734 if ((crc32_packet == NULL) ||
735 (crc32_length == 0) ||
736 ((crc32_length % 8) != 0))
738 return (crc32_result);
741 for (byte = 0; byte < crc32_length; byte = byte + 1)
743 current_byte = crc32_packet[byte];
744 for (bit = 0; bit < 8; bit = bit + 1)
746 /* msb = crc32_result[31]; */
747 msb = (uint8_t)(crc32_result >> 31);
749 crc32_result = crc32_result << 1;
751 /* it (msb != current_byte[bit]) */
752 if (msb != (0x1 & (current_byte >> bit)))
754 crc32_result = crc32_result ^ CRC32_POLY;
755 /* crc32_result[0] = 1 */
762 * 1. "mirror" every bit
763 * 2. swap the 4 bytes
764 * 3. complement each bit
769 shft = sizeof(crc32_result) * 8 - 1;
771 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
774 temp |= crc32_result & 1;
778 /* temp[31-bit] = crc32_result[bit] */
782 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
784 uint32_t t0, t1, t2, t3;
785 t0 = (0x000000ff & (temp >> 24));
786 t1 = (0x0000ff00 & (temp >> 8));
787 t2 = (0x00ff0000 & (temp << 8));
788 t3 = (0xff000000 & (temp << 24));
789 crc32_result = t0 | t1 | t2 | t3;
795 crc32_result = ~crc32_result;
798 return (crc32_result);
803 volatile unsigned long *addr)
805 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
809 bxe_set_bit(unsigned int nr,
810 volatile unsigned long *addr)
812 atomic_set_acq_long(addr, (1 << nr));
816 bxe_clear_bit(int nr,
817 volatile unsigned long *addr)
819 atomic_clear_acq_long(addr, (1 << nr));
823 bxe_test_and_set_bit(int nr,
824 volatile unsigned long *addr)
830 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
831 // if (x & nr) bit_was_set; else bit_was_not_set;
836 bxe_test_and_clear_bit(int nr,
837 volatile unsigned long *addr)
843 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
844 // if (x & nr) bit_was_set; else bit_was_not_set;
849 bxe_cmpxchg(volatile int *addr,
856 } while (atomic_cmpset_acq_int(addr, old, new) == 0);
861 * Get DMA memory from the OS.
863 * Validates that the OS has provided DMA buffers in response to a
864 * bus_dmamap_load call and saves the physical address of those buffers.
865 * When the callback is used the OS will return 0 for the mapping function
866 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
867 * failures back to the caller.
873 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
875 struct bxe_dma *dma = arg;
880 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
882 dma->paddr = segs->ds_addr;
888 * Allocate a block of memory and map it for DMA. No partial completions
889 * allowed and release any resources acquired if we can't acquire all
893 * 0 = Success, !0 = Failure
896 bxe_dma_alloc(struct bxe_softc *sc,
904 BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
905 (unsigned long)dma->size);
909 memset(dma, 0, sizeof(*dma)); /* sanity */
912 snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
914 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
915 BCM_PAGE_SIZE, /* alignment */
916 0, /* boundary limit */
917 BUS_SPACE_MAXADDR, /* restricted low */
918 BUS_SPACE_MAXADDR, /* restricted hi */
919 NULL, /* addr filter() */
920 NULL, /* addr filter() arg */
921 size, /* max map size */
922 1, /* num discontinuous */
923 size, /* max seg size */
924 BUS_DMA_ALLOCNOW, /* flags */
926 NULL, /* lock() arg */
927 &dma->tag); /* returned dma tag */
929 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
930 memset(dma, 0, sizeof(*dma));
934 rc = bus_dmamem_alloc(dma->tag,
935 (void **)&dma->vaddr,
936 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
939 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
940 bus_dma_tag_destroy(dma->tag);
941 memset(dma, 0, sizeof(*dma));
945 rc = bus_dmamap_load(dma->tag,
949 bxe_dma_map_addr, /* BLOGD in here */
953 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
954 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
955 bus_dma_tag_destroy(dma->tag);
956 memset(dma, 0, sizeof(*dma));
964 bxe_dma_free(struct bxe_softc *sc,
968 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
970 bus_dmamap_sync(dma->tag, dma->map,
971 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
972 bus_dmamap_unload(dma->tag, dma->map);
973 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
974 bus_dma_tag_destroy(dma->tag);
977 memset(dma, 0, sizeof(*dma));
981 * These indirect read and write routines are only during init.
982 * The locking is handled by the MCP.
986 bxe_reg_wr_ind(struct bxe_softc *sc,
990 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
991 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
992 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
996 bxe_reg_rd_ind(struct bxe_softc *sc,
1001 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1002 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
1003 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1009 bxe_acquire_hw_lock(struct bxe_softc *sc,
1012 uint32_t lock_status;
1013 uint32_t resource_bit = (1 << resource);
1014 int func = SC_FUNC(sc);
1015 uint32_t hw_lock_control_reg;
1018 /* validate the resource is within range */
1019 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1020 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1021 " resource_bit 0x%x\n", resource, resource_bit);
1026 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1028 hw_lock_control_reg =
1029 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1032 /* validate the resource is not already taken */
1033 lock_status = REG_RD(sc, hw_lock_control_reg);
1034 if (lock_status & resource_bit) {
1035 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n",
1036 resource, lock_status, resource_bit);
1040 /* try every 5ms for 5 seconds */
1041 for (cnt = 0; cnt < 1000; cnt++) {
1042 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1043 lock_status = REG_RD(sc, hw_lock_control_reg);
1044 if (lock_status & resource_bit) {
1050 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n",
1051 resource, resource_bit);
1056 bxe_release_hw_lock(struct bxe_softc *sc,
1059 uint32_t lock_status;
1060 uint32_t resource_bit = (1 << resource);
1061 int func = SC_FUNC(sc);
1062 uint32_t hw_lock_control_reg;
1064 /* validate the resource is within range */
1065 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1066 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)"
1067 " resource_bit 0x%x\n", resource, resource_bit);
1072 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1074 hw_lock_control_reg =
1075 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1078 /* validate the resource is currently taken */
1079 lock_status = REG_RD(sc, hw_lock_control_reg);
1080 if (!(lock_status & resource_bit)) {
1081 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n",
1082 resource, lock_status, resource_bit);
1086 REG_WR(sc, hw_lock_control_reg, resource_bit);
1089 static void bxe_acquire_phy_lock(struct bxe_softc *sc)
1092 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1095 static void bxe_release_phy_lock(struct bxe_softc *sc)
1097 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO);
1101 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1102 * had we done things the other way around, if two pfs from the same port
1103 * would attempt to access nvram at the same time, we could run into a
1105 * pf A takes the port lock.
1106 * pf B succeeds in taking the same lock since they are from the same port.
1107 * pf A takes the per pf misc lock. Performs eeprom access.
1108 * pf A finishes. Unlocks the per pf misc lock.
1109 * Pf B takes the lock and proceeds to perform it's own access.
1110 * pf A unlocks the per port lock, while pf B is still working (!).
1111 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1112 * access corrupted by pf B).*
1115 bxe_acquire_nvram_lock(struct bxe_softc *sc)
1117 int port = SC_PORT(sc);
1121 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1122 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1124 /* adjust timeout for emulation/FPGA */
1125 count = NVRAM_TIMEOUT_COUNT;
1126 if (CHIP_REV_IS_SLOW(sc)) {
1130 /* request access to nvram interface */
1131 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1132 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1134 for (i = 0; i < count*10; i++) {
1135 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1136 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1143 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1144 BLOGE(sc, "Cannot get access to nvram interface "
1145 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1154 bxe_release_nvram_lock(struct bxe_softc *sc)
1156 int port = SC_PORT(sc);
1160 /* adjust timeout for emulation/FPGA */
1161 count = NVRAM_TIMEOUT_COUNT;
1162 if (CHIP_REV_IS_SLOW(sc)) {
1166 /* relinquish nvram interface */
1167 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1168 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1170 for (i = 0; i < count*10; i++) {
1171 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1172 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1179 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1180 BLOGE(sc, "Cannot free access to nvram interface "
1181 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n",
1186 /* release HW lock: protect against other PFs in PF Direct Assignment */
1187 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1193 bxe_enable_nvram_access(struct bxe_softc *sc)
1197 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1199 /* enable both bits, even on read */
1200 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1201 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1205 bxe_disable_nvram_access(struct bxe_softc *sc)
1209 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1211 /* disable both bits, even after read */
1212 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1213 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1214 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1218 bxe_nvram_read_dword(struct bxe_softc *sc,
1226 /* build the command word */
1227 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1229 /* need to clear DONE bit separately */
1230 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1232 /* address of the NVRAM to read from */
1233 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1234 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1236 /* issue a read command */
1237 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1239 /* adjust timeout for emulation/FPGA */
1240 count = NVRAM_TIMEOUT_COUNT;
1241 if (CHIP_REV_IS_SLOW(sc)) {
1245 /* wait for completion */
1248 for (i = 0; i < count; i++) {
1250 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1252 if (val & MCPR_NVM_COMMAND_DONE) {
1253 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1254 /* we read nvram data in cpu order
1255 * but ethtool sees it as an array of bytes
1256 * converting to big-endian will do the work
1258 *ret_val = htobe32(val);
1265 BLOGE(sc, "nvram read timeout expired "
1266 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1267 offset, cmd_flags, val);
1274 bxe_nvram_read(struct bxe_softc *sc,
1283 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1284 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1289 if ((offset + buf_size) > sc->devinfo.flash_size) {
1290 BLOGE(sc, "Invalid parameter, "
1291 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1292 offset, buf_size, sc->devinfo.flash_size);
1296 /* request access to nvram interface */
1297 rc = bxe_acquire_nvram_lock(sc);
1302 /* enable access to nvram interface */
1303 bxe_enable_nvram_access(sc);
1305 /* read the first word(s) */
1306 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1307 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1308 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1309 memcpy(ret_buf, &val, 4);
1311 /* advance to the next dword */
1312 offset += sizeof(uint32_t);
1313 ret_buf += sizeof(uint32_t);
1314 buf_size -= sizeof(uint32_t);
1319 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1320 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1321 memcpy(ret_buf, &val, 4);
1324 /* disable access to nvram interface */
1325 bxe_disable_nvram_access(sc);
1326 bxe_release_nvram_lock(sc);
1332 bxe_nvram_write_dword(struct bxe_softc *sc,
1339 /* build the command word */
1340 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1342 /* need to clear DONE bit separately */
1343 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1345 /* write the data */
1346 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1348 /* address of the NVRAM to write to */
1349 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1350 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1352 /* issue the write command */
1353 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1355 /* adjust timeout for emulation/FPGA */
1356 count = NVRAM_TIMEOUT_COUNT;
1357 if (CHIP_REV_IS_SLOW(sc)) {
1361 /* wait for completion */
1363 for (i = 0; i < count; i++) {
1365 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1366 if (val & MCPR_NVM_COMMAND_DONE) {
1373 BLOGE(sc, "nvram write timeout expired "
1374 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n",
1375 offset, cmd_flags, val);
1381 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1384 bxe_nvram_write1(struct bxe_softc *sc,
1390 uint32_t align_offset;
1394 if ((offset + buf_size) > sc->devinfo.flash_size) {
1395 BLOGE(sc, "Invalid parameter, "
1396 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1397 offset, buf_size, sc->devinfo.flash_size);
1401 /* request access to nvram interface */
1402 rc = bxe_acquire_nvram_lock(sc);
1407 /* enable access to nvram interface */
1408 bxe_enable_nvram_access(sc);
1410 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1411 align_offset = (offset & ~0x03);
1412 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1415 val &= ~(0xff << BYTE_OFFSET(offset));
1416 val |= (*data_buf << BYTE_OFFSET(offset));
1418 /* nvram data is returned as an array of bytes
1419 * convert it back to cpu order
1423 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1426 /* disable access to nvram interface */
1427 bxe_disable_nvram_access(sc);
1428 bxe_release_nvram_lock(sc);
1434 bxe_nvram_write(struct bxe_softc *sc,
1441 uint32_t written_so_far;
1444 if (buf_size == 1) {
1445 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1448 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1449 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1454 if (buf_size == 0) {
1455 return (0); /* nothing to do */
1458 if ((offset + buf_size) > sc->devinfo.flash_size) {
1459 BLOGE(sc, "Invalid parameter, "
1460 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1461 offset, buf_size, sc->devinfo.flash_size);
1465 /* request access to nvram interface */
1466 rc = bxe_acquire_nvram_lock(sc);
1471 /* enable access to nvram interface */
1472 bxe_enable_nvram_access(sc);
1475 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1476 while ((written_so_far < buf_size) && (rc == 0)) {
1477 if (written_so_far == (buf_size - sizeof(uint32_t))) {
1478 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1479 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1480 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1481 } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1482 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1485 memcpy(&val, data_buf, 4);
1487 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1489 /* advance to the next dword */
1490 offset += sizeof(uint32_t);
1491 data_buf += sizeof(uint32_t);
1492 written_so_far += sizeof(uint32_t);
1496 /* disable access to nvram interface */
1497 bxe_disable_nvram_access(sc);
1498 bxe_release_nvram_lock(sc);
1503 /* copy command into DMAE command memory and set DMAE command Go */
1505 bxe_post_dmae(struct bxe_softc *sc,
1506 struct dmae_cmd *dmae,
1509 uint32_t cmd_offset;
1512 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_cmd) * idx));
1513 for (i = 0; i < ((sizeof(struct dmae_cmd) / 4)); i++) {
1514 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1517 REG_WR(sc, dmae_reg_go_c[idx], 1);
1521 bxe_dmae_opcode_add_comp(uint32_t opcode,
1524 return (opcode | ((comp_type << DMAE_CMD_C_DST_SHIFT) |
1525 DMAE_CMD_C_TYPE_ENABLE));
1529 bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1531 return (opcode & ~DMAE_CMD_SRC_RESET);
1535 bxe_dmae_opcode(struct bxe_softc *sc,
1541 uint32_t opcode = 0;
1543 opcode |= ((src_type << DMAE_CMD_SRC_SHIFT) |
1544 (dst_type << DMAE_CMD_DST_SHIFT));
1546 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
1548 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1550 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) |
1551 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT));
1553 opcode |= (DMAE_COM_SET_ERR << DMAE_CMD_ERR_POLICY_SHIFT);
1556 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1558 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1562 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1569 bxe_prep_dmae_with_comp(struct bxe_softc *sc,
1570 struct dmae_cmd *dmae,
1574 memset(dmae, 0, sizeof(struct dmae_cmd));
1576 /* set the opcode */
1577 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1578 TRUE, DMAE_COMP_PCI);
1580 /* fill in the completion parameters */
1581 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1582 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1583 dmae->comp_val = DMAE_COMP_VAL;
1586 /* issue a DMAE command over the init channel and wait for completion */
1588 bxe_issue_dmae_with_comp(struct bxe_softc *sc,
1589 struct dmae_cmd *dmae)
1591 uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1592 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1596 /* reset completion */
1599 /* post the command on the channel used for initializations */
1600 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1602 /* wait for completion */
1605 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1607 (sc->recovery_state != BXE_RECOVERY_DONE &&
1608 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1609 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n",
1610 *wb_comp, sc->recovery_state);
1611 BXE_DMAE_UNLOCK(sc);
1612 return (DMAE_TIMEOUT);
1619 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1620 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n",
1621 *wb_comp, sc->recovery_state);
1622 BXE_DMAE_UNLOCK(sc);
1623 return (DMAE_PCI_ERROR);
1626 BXE_DMAE_UNLOCK(sc);
1631 bxe_read_dmae(struct bxe_softc *sc,
1635 struct dmae_cmd dmae;
1639 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1641 if (!sc->dmae_ready) {
1642 data = BXE_SP(sc, wb_data[0]);
1644 for (i = 0; i < len32; i++) {
1645 data[i] = (CHIP_IS_E1(sc)) ?
1646 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1647 REG_RD(sc, (src_addr + (i * 4)));
1653 /* set opcode and fixed command fields */
1654 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1656 /* fill in addresses and len */
1657 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1658 dmae.src_addr_hi = 0;
1659 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1660 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1663 /* issue the command and wait for completion */
1664 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1665 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1670 bxe_write_dmae(struct bxe_softc *sc,
1671 bus_addr_t dma_addr,
1675 struct dmae_cmd dmae;
1678 if (!sc->dmae_ready) {
1679 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1681 if (CHIP_IS_E1(sc)) {
1682 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1684 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1690 /* set opcode and fixed command fields */
1691 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1693 /* fill in addresses and len */
1694 dmae.src_addr_lo = U64_LO(dma_addr);
1695 dmae.src_addr_hi = U64_HI(dma_addr);
1696 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1697 dmae.dst_addr_hi = 0;
1700 /* issue the command and wait for completion */
1701 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1702 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1707 bxe_write_dmae_phys_len(struct bxe_softc *sc,
1708 bus_addr_t phys_addr,
1712 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1715 while (len > dmae_wr_max) {
1717 (phys_addr + offset), /* src DMA address */
1718 (addr + offset), /* dst GRC address */
1720 offset += (dmae_wr_max * 4);
1725 (phys_addr + offset), /* src DMA address */
1726 (addr + offset), /* dst GRC address */
1731 bxe_set_ctx_validation(struct bxe_softc *sc,
1732 struct eth_context *cxt,
1735 /* ustorm cxt validation */
1736 cxt->ustorm_ag_context.cdu_usage =
1737 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1738 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1739 /* xcontext validation */
1740 cxt->xstorm_ag_context.cdu_reserved =
1741 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1742 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1746 bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1753 (BAR_CSTRORM_INTMEM +
1754 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1756 REG_WR8(sc, addr, ticks);
1759 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1760 port, fw_sb_id, sb_index, ticks);
1764 bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1770 uint32_t enable_flag =
1771 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1773 (BAR_CSTRORM_INTMEM +
1774 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1778 flags = REG_RD8(sc, addr);
1779 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1780 flags |= enable_flag;
1781 REG_WR8(sc, addr, flags);
1784 "port %d fw_sb_id %d sb_index %d disable %d\n",
1785 port, fw_sb_id, sb_index, disable);
1789 bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1795 int port = SC_PORT(sc);
1796 uint8_t ticks = (usec / 4); /* XXX ??? */
1798 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1800 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1801 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1805 elink_cb_udelay(struct bxe_softc *sc,
1812 elink_cb_reg_read(struct bxe_softc *sc,
1815 return (REG_RD(sc, reg_addr));
1819 elink_cb_reg_write(struct bxe_softc *sc,
1823 REG_WR(sc, reg_addr, val);
1827 elink_cb_reg_wb_write(struct bxe_softc *sc,
1832 REG_WR_DMAE(sc, offset, wb_write, len);
1836 elink_cb_reg_wb_read(struct bxe_softc *sc,
1841 REG_RD_DMAE(sc, offset, wb_write, len);
1845 elink_cb_path_id(struct bxe_softc *sc)
1847 return (SC_PATH(sc));
1851 elink_cb_event_log(struct bxe_softc *sc,
1852 const elink_log_id_t elink_log_id,
1856 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1860 bxe_set_spio(struct bxe_softc *sc,
1866 /* Only 2 SPIOs are configurable */
1867 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1868 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode);
1872 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1874 /* read SPIO and mask except the float bits */
1875 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1878 case MISC_SPIO_OUTPUT_LOW:
1879 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1880 /* clear FLOAT and set CLR */
1881 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1882 spio_reg |= (spio << MISC_SPIO_CLR_POS);
1885 case MISC_SPIO_OUTPUT_HIGH:
1886 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1887 /* clear FLOAT and set SET */
1888 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1889 spio_reg |= (spio << MISC_SPIO_SET_POS);
1892 case MISC_SPIO_INPUT_HI_Z:
1893 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1895 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1902 REG_WR(sc, MISC_REG_SPIO, spio_reg);
1903 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1909 bxe_gpio_read(struct bxe_softc *sc,
1913 /* The GPIO should be swapped if swap register is set and active */
1914 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1915 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1916 int gpio_shift = (gpio_num +
1917 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1918 uint32_t gpio_mask = (1 << gpio_shift);
1921 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1922 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d"
1923 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift,
1928 /* read GPIO value */
1929 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
1931 /* get the requested pin value */
1932 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
1936 bxe_gpio_write(struct bxe_softc *sc,
1941 /* The GPIO should be swapped if swap register is set and active */
1942 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1943 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1944 int gpio_shift = (gpio_num +
1945 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1946 uint32_t gpio_mask = (1 << gpio_shift);
1949 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1950 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
1951 " gpio_shift %d gpio_mask 0x%x\n",
1952 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
1956 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1958 /* read GPIO and mask except the float bits */
1959 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1964 "Set GPIO %d (shift %d) -> output low\n",
1965 gpio_num, gpio_shift);
1966 /* clear FLOAT and set CLR */
1967 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1968 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1971 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1973 "Set GPIO %d (shift %d) -> output high\n",
1974 gpio_num, gpio_shift);
1975 /* clear FLOAT and set SET */
1976 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1977 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1980 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1982 "Set GPIO %d (shift %d) -> input\n",
1983 gpio_num, gpio_shift);
1985 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1992 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
1993 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
1999 bxe_gpio_mult_write(struct bxe_softc *sc,
2005 /* any port swapping should be handled by caller */
2007 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2009 /* read GPIO and mask except the float bits */
2010 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2011 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2012 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2013 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2016 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2017 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
2019 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2022 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2023 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
2025 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2028 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2029 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2031 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2035 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x"
2036 " gpio_reg 0x%x\n", pins, mode, gpio_reg);
2037 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2041 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2042 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2048 bxe_gpio_int_write(struct bxe_softc *sc,
2053 /* The GPIO should be swapped if swap register is set and active */
2054 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2055 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2056 int gpio_shift = (gpio_num +
2057 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2058 uint32_t gpio_mask = (1 << gpio_shift);
2061 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2062 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d"
2063 " gpio_shift %d gpio_mask 0x%x\n",
2064 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask);
2068 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2071 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2074 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2076 "Clear GPIO INT %d (shift %d) -> output low\n",
2077 gpio_num, gpio_shift);
2078 /* clear SET and set CLR */
2079 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2080 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2083 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2085 "Set GPIO INT %d (shift %d) -> output high\n",
2086 gpio_num, gpio_shift);
2087 /* clear CLR and set SET */
2088 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2089 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2096 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2097 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2103 elink_cb_gpio_read(struct bxe_softc *sc,
2107 return (bxe_gpio_read(sc, gpio_num, port));
2111 elink_cb_gpio_write(struct bxe_softc *sc,
2113 uint8_t mode, /* 0=low 1=high */
2116 return (bxe_gpio_write(sc, gpio_num, mode, port));
2120 elink_cb_gpio_mult_write(struct bxe_softc *sc,
2122 uint8_t mode) /* 0=low 1=high */
2124 return (bxe_gpio_mult_write(sc, pins, mode));
2128 elink_cb_gpio_int_write(struct bxe_softc *sc,
2130 uint8_t mode, /* 0=low 1=high */
2133 return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2137 elink_cb_notify_link_changed(struct bxe_softc *sc)
2139 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2140 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2143 /* send the MCP a request, block until there is a reply */
2145 elink_cb_fw_command(struct bxe_softc *sc,
2149 int mb_idx = SC_FW_MB_IDX(sc);
2153 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2158 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2159 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2162 "wrote command 0x%08x to FW MB param 0x%08x\n",
2163 (command | seq), param);
2165 /* Let the FW do it's magic. GIve it up to 5 seconds... */
2167 DELAY(delay * 1000);
2168 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2169 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2172 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2173 cnt*delay, rc, seq);
2175 /* is this a reply to our command? */
2176 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2177 rc &= FW_MSG_CODE_MASK;
2180 BLOGE(sc, "FW failed to respond!\n");
2181 // XXX bxe_fw_dump(sc);
2185 BXE_FWMB_UNLOCK(sc);
2190 bxe_fw_command(struct bxe_softc *sc,
2194 return (elink_cb_fw_command(sc, command, param));
2198 __storm_memset_dma_mapping(struct bxe_softc *sc,
2202 REG_WR(sc, addr, U64_LO(mapping));
2203 REG_WR(sc, (addr + 4), U64_HI(mapping));
2207 storm_memset_spq_addr(struct bxe_softc *sc,
2211 uint32_t addr = (XSEM_REG_FAST_MEMORY +
2212 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2213 __storm_memset_dma_mapping(sc, addr, mapping);
2217 storm_memset_vf_to_pf(struct bxe_softc *sc,
2221 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2222 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2223 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2224 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2228 storm_memset_func_en(struct bxe_softc *sc,
2232 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2233 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2234 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2235 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2239 storm_memset_eq_data(struct bxe_softc *sc,
2240 struct event_ring_data *eq_data,
2246 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2247 size = sizeof(struct event_ring_data);
2248 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2252 storm_memset_eq_prod(struct bxe_softc *sc,
2256 uint32_t addr = (BAR_CSTRORM_INTMEM +
2257 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2258 REG_WR16(sc, addr, eq_prod);
2262 * Post a slowpath command.
2264 * A slowpath command is used to propogate a configuration change through
2265 * the controller in a controlled manner, allowing each STORM processor and
2266 * other H/W blocks to phase in the change. The commands sent on the
2267 * slowpath are referred to as ramrods. Depending on the ramrod used the
2268 * completion of the ramrod will occur in different ways. Here's a
2269 * breakdown of ramrods and how they complete:
2271 * RAMROD_CMD_ID_ETH_PORT_SETUP
2272 * Used to setup the leading connection on a port. Completes on the
2273 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
2275 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2276 * Used to setup an additional connection on a port. Completes on the
2277 * RCQ of the multi-queue/RSS connection being initialized.
2279 * RAMROD_CMD_ID_ETH_STAT_QUERY
2280 * Used to force the storm processors to update the statistics database
2281 * in host memory. This ramrod is send on the leading connection CID and
2282 * completes as an index increment of the CSTORM on the default status
2285 * RAMROD_CMD_ID_ETH_UPDATE
2286 * Used to update the state of the leading connection, usually to udpate
2287 * the RSS indirection table. Completes on the RCQ of the leading
2288 * connection. (Not currently used under FreeBSD until OS support becomes
2291 * RAMROD_CMD_ID_ETH_HALT
2292 * Used when tearing down a connection prior to driver unload. Completes
2293 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
2294 * use this on the leading connection.
2296 * RAMROD_CMD_ID_ETH_SET_MAC
2297 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
2298 * the RCQ of the leading connection.
2300 * RAMROD_CMD_ID_ETH_CFC_DEL
2301 * Used when tearing down a conneciton prior to driver unload. Completes
2302 * on the RCQ of the leading connection (since the current connection
2303 * has been completely removed from controller memory).
2305 * RAMROD_CMD_ID_ETH_PORT_DEL
2306 * Used to tear down the leading connection prior to driver unload,
2307 * typically fp[0]. Completes as an index increment of the CSTORM on the
2308 * default status block.
2310 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2311 * Used for connection offload. Completes on the RCQ of the multi-queue
2312 * RSS connection that is being offloaded. (Not currently used under
2315 * There can only be one command pending per function.
2318 * 0 = Success, !0 = Failure.
2321 /* must be called under the spq lock */
2323 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2325 struct eth_spe *next_spe = sc->spq_prod_bd;
2327 if (sc->spq_prod_bd == sc->spq_last_bd) {
2328 /* wrap back to the first eth_spq */
2329 sc->spq_prod_bd = sc->spq;
2330 sc->spq_prod_idx = 0;
2339 /* must be called under the spq lock */
2341 void bxe_sp_prod_update(struct bxe_softc *sc)
2343 int func = SC_FUNC(sc);
2346 * Make sure that BD data is updated before writing the producer.
2347 * BD data is written to the memory, the producer is read from the
2348 * memory, thus we need a full memory barrier to ensure the ordering.
2352 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2355 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2356 BUS_SPACE_BARRIER_WRITE);
2360 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2362 * @cmd: command to check
2363 * @cmd_type: command type
2366 int bxe_is_contextless_ramrod(int cmd,
2369 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2370 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2371 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2372 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2373 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2374 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2375 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2383 * bxe_sp_post - place a single command on an SP ring
2385 * @sc: driver handle
2386 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2387 * @cid: SW CID the command is related to
2388 * @data_hi: command private data address (high 32 bits)
2389 * @data_lo: command private data address (low 32 bits)
2390 * @cmd_type: command type (e.g. NONE, ETH)
2392 * SP data is handled as if it's always an address pair, thus data fields are
2393 * not swapped to little endian in upper functions. Instead this function swaps
2394 * data as if it's two uint32 fields.
2397 bxe_sp_post(struct bxe_softc *sc,
2404 struct eth_spe *spe;
2408 common = bxe_is_contextless_ramrod(command, cmd_type);
2413 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2414 BLOGE(sc, "EQ ring is full!\n");
2419 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2420 BLOGE(sc, "SPQ ring is full!\n");
2426 spe = bxe_sp_get_next(sc);
2428 /* CID needs port number to be encoded int it */
2429 spe->hdr.conn_and_cmd_data =
2430 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid));
2432 type = (cmd_type << SPE_HDR_T_CONN_TYPE_SHIFT) & SPE_HDR_T_CONN_TYPE;
2434 /* TBD: Check if it works for VFs */
2435 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) &
2436 SPE_HDR_T_FUNCTION_ID);
2438 spe->hdr.type = htole16(type);
2440 spe->data.update_data_addr.hi = htole32(data_hi);
2441 spe->data.update_data_addr.lo = htole32(data_lo);
2444 * It's ok if the actual decrement is issued towards the memory
2445 * somewhere between the lock and unlock. Thus no more explict
2446 * memory barrier is needed.
2449 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2451 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2454 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2455 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2456 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2458 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2460 (uint32_t)U64_HI(sc->spq_dma.paddr),
2461 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2468 atomic_load_acq_long(&sc->cq_spq_left),
2469 atomic_load_acq_long(&sc->eq_spq_left));
2471 bxe_sp_prod_update(sc);
2478 * bxe_debug_print_ind_table - prints the indirection table configuration.
2480 * @sc: driver hanlde
2481 * @p: pointer to rss configuration
2485 * FreeBSD Device probe function.
2487 * Compares the device found to the driver's list of supported devices and
2488 * reports back to the bsd loader whether this is the right driver for the device.
2489 * This is the driver entry function called from the "kldload" command.
2492 * BUS_PROBE_DEFAULT on success, positive value on failure.
2495 bxe_probe(device_t dev)
2497 struct bxe_softc *sc;
2498 struct bxe_device_type *t;
2500 uint16_t did, sdid, svid, vid;
2502 /* Find our device structure */
2503 sc = device_get_softc(dev);
2507 /* Get the data for the device to be probed. */
2508 vid = pci_get_vendor(dev);
2509 did = pci_get_device(dev);
2510 svid = pci_get_subvendor(dev);
2511 sdid = pci_get_subdevice(dev);
2514 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
2515 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
2517 /* Look through the list of known devices for a match. */
2518 while (t->bxe_name != NULL) {
2519 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2520 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2521 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2522 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
2523 if (descbuf == NULL)
2526 /* Print out the device identity. */
2527 snprintf(descbuf, BXE_DEVDESC_MAX,
2528 "%s (%c%d) BXE v:%s\n", t->bxe_name,
2529 (((pci_read_config(dev, PCIR_REVID, 4) &
2531 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2532 BXE_DRIVER_VERSION);
2534 device_set_desc_copy(dev, descbuf);
2535 free(descbuf, M_TEMP);
2536 return (BUS_PROBE_DEFAULT);
2545 bxe_init_mutexes(struct bxe_softc *sc)
2547 #ifdef BXE_CORE_LOCK_SX
2548 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2549 "bxe%d_core_lock", sc->unit);
2550 sx_init(&sc->core_sx, sc->core_sx_name);
2552 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2553 "bxe%d_core_lock", sc->unit);
2554 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2557 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2558 "bxe%d_sp_lock", sc->unit);
2559 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2561 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2562 "bxe%d_dmae_lock", sc->unit);
2563 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2565 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2566 "bxe%d_phy_lock", sc->unit);
2567 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2569 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2570 "bxe%d_fwmb_lock", sc->unit);
2571 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2573 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2574 "bxe%d_print_lock", sc->unit);
2575 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2577 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2578 "bxe%d_stats_lock", sc->unit);
2579 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2581 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2582 "bxe%d_mcast_lock", sc->unit);
2583 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2587 bxe_release_mutexes(struct bxe_softc *sc)
2589 #ifdef BXE_CORE_LOCK_SX
2590 sx_destroy(&sc->core_sx);
2592 if (mtx_initialized(&sc->core_mtx)) {
2593 mtx_destroy(&sc->core_mtx);
2597 if (mtx_initialized(&sc->sp_mtx)) {
2598 mtx_destroy(&sc->sp_mtx);
2601 if (mtx_initialized(&sc->dmae_mtx)) {
2602 mtx_destroy(&sc->dmae_mtx);
2605 if (mtx_initialized(&sc->port.phy_mtx)) {
2606 mtx_destroy(&sc->port.phy_mtx);
2609 if (mtx_initialized(&sc->fwmb_mtx)) {
2610 mtx_destroy(&sc->fwmb_mtx);
2613 if (mtx_initialized(&sc->print_mtx)) {
2614 mtx_destroy(&sc->print_mtx);
2617 if (mtx_initialized(&sc->stats_mtx)) {
2618 mtx_destroy(&sc->stats_mtx);
2621 if (mtx_initialized(&sc->mcast_mtx)) {
2622 mtx_destroy(&sc->mcast_mtx);
2627 bxe_tx_disable(struct bxe_softc* sc)
2629 struct ifnet *ifp = sc->ifnet;
2631 /* tell the stack the driver is stopped and TX queue is full */
2633 ifp->if_drv_flags = 0;
2638 bxe_drv_pulse(struct bxe_softc *sc)
2640 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2641 sc->fw_drv_pulse_wr_seq);
2644 static inline uint16_t
2645 bxe_tx_avail(struct bxe_softc *sc,
2646 struct bxe_fastpath *fp)
2652 prod = fp->tx_bd_prod;
2653 cons = fp->tx_bd_cons;
2655 used = SUB_S16(prod, cons);
2657 return (int16_t)(sc->tx_ring_size) - used;
2661 bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2665 mb(); /* status block fields can change */
2666 hw_cons = le16toh(*fp->tx_cons_sb);
2667 return (hw_cons != fp->tx_pkt_cons);
2670 static inline uint8_t
2671 bxe_has_tx_work(struct bxe_fastpath *fp)
2673 /* expand this for multi-cos if ever supported */
2674 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2678 bxe_has_rx_work(struct bxe_fastpath *fp)
2680 uint16_t rx_cq_cons_sb;
2682 mb(); /* status block fields can change */
2683 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2684 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2686 return (fp->rx_cq_cons != rx_cq_cons_sb);
2690 bxe_sp_event(struct bxe_softc *sc,
2691 struct bxe_fastpath *fp,
2692 union eth_rx_cqe *rr_cqe)
2694 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2695 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2696 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2697 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2699 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2700 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2703 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2704 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2705 drv_cmd = ECORE_Q_CMD_UPDATE;
2708 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2709 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2710 drv_cmd = ECORE_Q_CMD_SETUP;
2713 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2714 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2715 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2718 case (RAMROD_CMD_ID_ETH_HALT):
2719 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2720 drv_cmd = ECORE_Q_CMD_HALT;
2723 case (RAMROD_CMD_ID_ETH_TERMINATE):
2724 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2725 drv_cmd = ECORE_Q_CMD_TERMINATE;
2728 case (RAMROD_CMD_ID_ETH_EMPTY):
2729 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2730 drv_cmd = ECORE_Q_CMD_EMPTY;
2734 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2735 command, fp->index);
2739 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2740 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2742 * q_obj->complete_cmd() failure means that this was
2743 * an unexpected completion.
2745 * In this case we don't want to increase the sc->spq_left
2746 * because apparently we haven't sent this command the first
2749 // bxe_panic(sc, ("Unexpected SP completion\n"));
2753 atomic_add_acq_long(&sc->cq_spq_left, 1);
2755 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2756 atomic_load_acq_long(&sc->cq_spq_left));
2760 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2761 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2762 * the current aggregation queue as in-progress.
2765 bxe_tpa_start(struct bxe_softc *sc,
2766 struct bxe_fastpath *fp,
2770 struct eth_fast_path_rx_cqe *cqe)
2772 struct bxe_sw_rx_bd tmp_bd;
2773 struct bxe_sw_rx_bd *rx_buf;
2774 struct eth_rx_bd *rx_bd;
2776 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2779 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2780 "cons=%d prod=%d\n",
2781 fp->index, queue, cons, prod);
2783 max_agg_queues = MAX_AGG_QS(sc);
2785 KASSERT((queue < max_agg_queues),
2786 ("fp[%02d] invalid aggr queue (%d >= %d)!",
2787 fp->index, queue, max_agg_queues));
2789 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2790 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2793 /* copy the existing mbuf and mapping from the TPA pool */
2794 tmp_bd = tpa_info->bd;
2796 if (tmp_bd.m == NULL) {
2799 tmp = (uint32_t *)cqe;
2801 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n",
2802 fp->index, queue, cons, prod);
2803 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2804 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2806 /* XXX Error handling? */
2810 /* change the TPA queue to the start state */
2811 tpa_info->state = BXE_TPA_STATE_START;
2812 tpa_info->placement_offset = cqe->placement_offset;
2813 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags);
2814 tpa_info->vlan_tag = le16toh(cqe->vlan_tag);
2815 tpa_info->len_on_bd = le16toh(cqe->len_on_bd);
2817 fp->rx_tpa_queue_used |= (1 << queue);
2820 * If all the buffer descriptors are filled with mbufs then fill in
2821 * the current consumer index with a new BD. Else if a maximum Rx
2822 * buffer limit is imposed then fill in the next producer index.
2824 index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2827 /* move the received mbuf and mapping to TPA pool */
2828 tpa_info->bd = fp->rx_mbuf_chain[cons];
2830 /* release any existing RX BD mbuf mappings */
2831 if (cons != index) {
2832 rx_buf = &fp->rx_mbuf_chain[cons];
2834 if (rx_buf->m_map != NULL) {
2835 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2836 BUS_DMASYNC_POSTREAD);
2837 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2841 * We get here when the maximum number of rx buffers is less than
2842 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2843 * it out here without concern of a memory leak.
2845 fp->rx_mbuf_chain[cons].m = NULL;
2848 /* update the Rx SW BD with the mbuf info from the TPA pool */
2849 fp->rx_mbuf_chain[index] = tmp_bd;
2851 /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2852 rx_bd = &fp->rx_chain[index];
2853 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2854 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2858 * When a TPA aggregation is completed, loop through the individual mbufs
2859 * of the aggregation, combining them into a single mbuf which will be sent
2860 * up the stack. Refill all freed SGEs with mbufs as we go along.
2863 bxe_fill_frag_mbuf(struct bxe_softc *sc,
2864 struct bxe_fastpath *fp,
2865 struct bxe_sw_tpa_info *tpa_info,
2869 struct eth_end_agg_rx_cqe *cqe,
2872 struct mbuf *m_frag;
2873 uint32_t frag_len, frag_size, i;
2878 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
2881 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
2882 fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
2884 /* make sure the aggregated frame is not too big to handle */
2885 if (pages > 8 * PAGES_PER_SGE) {
2887 uint32_t *tmp = (uint32_t *)cqe;
2889 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
2890 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
2891 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
2892 tpa_info->len_on_bd, frag_size);
2894 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n",
2895 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7));
2897 bxe_panic(sc, ("sge page count error\n"));
2902 * Scan through the scatter gather list pulling individual mbufs into a
2903 * single mbuf for the host stack.
2905 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
2906 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
2909 * Firmware gives the indices of the SGE as if the ring is an array
2910 * (meaning that the "next" element will consume 2 indices).
2912 frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
2914 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
2915 "sge_idx=%d frag_size=%d frag_len=%d\n",
2916 fp->index, queue, i, j, sge_idx, frag_size, frag_len);
2918 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
2920 /* allocate a new mbuf for the SGE */
2921 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
2923 /* Leave all remaining SGEs in the ring! */
2927 /* update the fragment length */
2928 m_frag->m_len = frag_len;
2930 /* concatenate the fragment to the head mbuf */
2932 fp->eth_q_stats.mbuf_alloc_sge--;
2934 /* update the TPA mbuf size and remaining fragment size */
2935 m->m_pkthdr.len += frag_len;
2936 frag_size -= frag_len;
2940 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
2941 fp->index, queue, frag_size);
2947 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
2951 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
2952 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
2954 for (j = 0; j < 2; j++) {
2955 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
2962 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
2964 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
2965 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
2968 * Clear the two last indices in the page to 1. These are the indices that
2969 * correspond to the "next" element, hence will never be indicated and
2970 * should be removed from the calculations.
2972 bxe_clear_sge_mask_next_elems(fp);
2976 bxe_update_last_max_sge(struct bxe_fastpath *fp,
2979 uint16_t last_max = fp->last_max_sge;
2981 if (SUB_S16(idx, last_max) > 0) {
2982 fp->last_max_sge = idx;
2987 bxe_update_sge_prod(struct bxe_softc *sc,
2988 struct bxe_fastpath *fp,
2990 union eth_sgl_or_raw_data *cqe)
2992 uint16_t last_max, last_elem, first_elem;
3000 /* first mark all used pages */
3001 for (i = 0; i < sge_len; i++) {
3002 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
3003 RX_SGE(le16toh(cqe->sgl[i])));
3007 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
3008 fp->index, sge_len - 1,
3009 le16toh(cqe->sgl[sge_len - 1]));
3011 /* assume that the last SGE index is the biggest */
3012 bxe_update_last_max_sge(fp,
3013 le16toh(cqe->sgl[sge_len - 1]));
3015 last_max = RX_SGE(fp->last_max_sge);
3016 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
3017 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
3019 /* if ring is not full */
3020 if (last_elem + 1 != first_elem) {
3024 /* now update the prod */
3025 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
3026 if (__predict_true(fp->sge_mask[i])) {
3030 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3031 delta += BIT_VEC64_ELEM_SZ;
3035 fp->rx_sge_prod += delta;
3036 /* clear page-end entries */
3037 bxe_clear_sge_mask_next_elems(fp);
3041 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3042 fp->index, fp->last_max_sge, fp->rx_sge_prod);
3046 * The aggregation on the current TPA queue has completed. Pull the individual
3047 * mbuf fragments together into a single mbuf, perform all necessary checksum
3048 * calculations, and send the resuting mbuf to the stack.
3051 bxe_tpa_stop(struct bxe_softc *sc,
3052 struct bxe_fastpath *fp,
3053 struct bxe_sw_tpa_info *tpa_info,
3056 struct eth_end_agg_rx_cqe *cqe,
3059 struct ifnet *ifp = sc->ifnet;
3064 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3065 fp->index, queue, tpa_info->placement_offset,
3066 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3070 /* allocate a replacement before modifying existing mbuf */
3071 rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3073 /* drop the frame and log an error */
3074 fp->eth_q_stats.rx_soft_errors++;
3075 goto bxe_tpa_stop_exit;
3078 /* we have a replacement, fixup the current mbuf */
3079 m_adj(m, tpa_info->placement_offset);
3080 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3082 /* mark the checksums valid (taken care of by the firmware) */
3083 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3084 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3085 m->m_pkthdr.csum_data = 0xffff;
3086 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3091 /* aggregate all of the SGEs into a single mbuf */
3092 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3094 /* drop the packet and log an error */
3095 fp->eth_q_stats.rx_soft_errors++;
3098 if (tpa_info->parsing_flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3099 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3100 m->m_flags |= M_VLANTAG;
3103 /* assign packet to this interface interface */
3104 m->m_pkthdr.rcvif = ifp;
3106 #if __FreeBSD_version >= 800000
3107 /* specify what RSS queue was used for this flow */
3108 m->m_pkthdr.flowid = fp->index;
3113 fp->eth_q_stats.rx_tpa_pkts++;
3115 /* pass the frame to the stack */
3116 (*ifp->if_input)(ifp, m);
3119 /* we passed an mbuf up the stack or dropped the frame */
3120 fp->eth_q_stats.mbuf_alloc_tpa--;
3124 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3125 fp->rx_tpa_queue_used &= ~(1 << queue);
3130 struct bxe_fastpath *fp,
3134 struct eth_fast_path_rx_cqe *cqe_fp)
3136 struct mbuf *m_frag;
3137 uint16_t frags, frag_len;
3138 uint16_t sge_idx = 0;
3143 /* adjust the mbuf */
3146 frag_size = len - lenonbd;
3147 frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3149 for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) {
3150 sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j]));
3152 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3153 frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE));
3154 m_frag->m_len = frag_len;
3156 /* allocate a new mbuf for the SGE */
3157 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3159 /* Leave all remaining SGEs in the ring! */
3162 fp->eth_q_stats.mbuf_alloc_sge--;
3164 /* concatenate the fragment to the head mbuf */
3167 frag_size -= frag_len;
3170 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data);
3176 bxe_rxeof(struct bxe_softc *sc,
3177 struct bxe_fastpath *fp)
3179 struct ifnet *ifp = sc->ifnet;
3180 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3181 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3187 /* CQ "next element" is of the size of the regular element */
3188 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3189 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3193 bd_cons = fp->rx_bd_cons;
3194 bd_prod = fp->rx_bd_prod;
3195 bd_prod_fw = bd_prod;
3196 sw_cq_cons = fp->rx_cq_cons;
3197 sw_cq_prod = fp->rx_cq_prod;
3200 * Memory barrier necessary as speculative reads of the rx
3201 * buffer can be ahead of the index in the status block
3206 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3207 fp->index, hw_cq_cons, sw_cq_cons);
3209 while (sw_cq_cons != hw_cq_cons) {
3210 struct bxe_sw_rx_bd *rx_buf = NULL;
3211 union eth_rx_cqe *cqe;
3212 struct eth_fast_path_rx_cqe *cqe_fp;
3213 uint8_t cqe_fp_flags;
3214 enum eth_rx_cqe_type cqe_fp_type;
3215 uint16_t len, lenonbd, pad;
3216 struct mbuf *m = NULL;
3218 comp_ring_cons = RCQ(sw_cq_cons);
3219 bd_prod = RX_BD(bd_prod);
3220 bd_cons = RX_BD(bd_cons);
3222 cqe = &fp->rcq_chain[comp_ring_cons];
3223 cqe_fp = &cqe->fast_path_cqe;
3224 cqe_fp_flags = cqe_fp->type_error_flags;
3225 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3228 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3229 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3230 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n",
3236 CQE_TYPE(cqe_fp_flags),
3238 cqe_fp->status_flags,
3239 le32toh(cqe_fp->rss_hash_result),
3240 le16toh(cqe_fp->vlan_tag),
3241 le16toh(cqe_fp->pkt_len_or_gro_seg_len),
3242 le16toh(cqe_fp->len_on_bd));
3244 /* is this a slowpath msg? */
3245 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3246 bxe_sp_event(sc, fp, cqe);
3250 rx_buf = &fp->rx_mbuf_chain[bd_cons];
3252 if (!CQE_TYPE_FAST(cqe_fp_type)) {
3253 struct bxe_sw_tpa_info *tpa_info;
3254 uint16_t frag_size, pages;
3257 if (CQE_TYPE_START(cqe_fp_type)) {
3258 bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3259 bd_cons, bd_prod, cqe_fp);
3260 m = NULL; /* packet not ready yet */
3264 KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3265 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3267 queue = cqe->end_agg_cqe.queue_index;
3268 tpa_info = &fp->rx_tpa_info[queue];
3270 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3273 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3274 tpa_info->len_on_bd);
3275 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3277 bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3278 &cqe->end_agg_cqe, comp_ring_cons);
3280 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data);
3287 /* is this an error packet? */
3288 if (__predict_false(cqe_fp_flags &
3289 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3290 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3291 fp->eth_q_stats.rx_soft_errors++;
3295 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3296 lenonbd = le16toh(cqe_fp->len_on_bd);
3297 pad = cqe_fp->placement_offset;
3301 if (__predict_false(m == NULL)) {
3302 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3303 bd_cons, fp->index);
3307 /* XXX double copy if packet length under a threshold */
3310 * If all the buffer descriptors are filled with mbufs then fill in
3311 * the current consumer index with a new BD. Else if a maximum Rx
3312 * buffer limit is imposed then fill in the next producer index.
3314 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3315 (sc->max_rx_bufs != RX_BD_USABLE) ?
3319 /* we simply reuse the received mbuf and don't post it to the stack */
3322 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3324 fp->eth_q_stats.rx_soft_errors++;
3326 if (sc->max_rx_bufs != RX_BD_USABLE) {
3327 /* copy this consumer index to the producer index */
3328 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3329 sizeof(struct bxe_sw_rx_bd));
3330 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3336 /* current mbuf was detached from the bd */
3337 fp->eth_q_stats.mbuf_alloc_rx--;
3339 /* we allocated a replacement mbuf, fixup the current one */
3341 m->m_pkthdr.len = m->m_len = len;
3343 if ((len > 60) && (len > lenonbd)) {
3344 fp->eth_q_stats.rx_bxe_service_rxsgl++;
3345 rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp);
3348 fp->eth_q_stats.rx_jumbo_sge_pkts++;
3349 } else if (lenonbd < len) {
3350 fp->eth_q_stats.rx_erroneous_jumbo_sge_pkts++;
3353 /* assign packet to this interface interface */
3354 m->m_pkthdr.rcvif = ifp;
3356 /* assume no hardware checksum has complated */
3357 m->m_pkthdr.csum_flags = 0;
3359 /* validate checksum if offload enabled */
3360 if (ifp->if_capenable & IFCAP_RXCSUM) {
3361 /* check for a valid IP frame */
3362 if (!(cqe->fast_path_cqe.status_flags &
3363 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3364 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3365 if (__predict_false(cqe_fp_flags &
3366 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3367 fp->eth_q_stats.rx_hw_csum_errors++;
3369 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3370 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3374 /* check for a valid TCP/UDP frame */
3375 if (!(cqe->fast_path_cqe.status_flags &
3376 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3377 if (__predict_false(cqe_fp_flags &
3378 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3379 fp->eth_q_stats.rx_hw_csum_errors++;
3381 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3382 m->m_pkthdr.csum_data = 0xFFFF;
3383 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3389 /* if there is a VLAN tag then flag that info */
3390 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_INNER_VLAN_EXIST) {
3391 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3392 m->m_flags |= M_VLANTAG;
3395 #if __FreeBSD_version >= 800000
3396 /* specify what RSS queue was used for this flow */
3397 m->m_pkthdr.flowid = fp->index;
3403 bd_cons = RX_BD_NEXT(bd_cons);
3404 bd_prod = RX_BD_NEXT(bd_prod);
3405 bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3407 /* pass the frame to the stack */
3408 if (__predict_true(m != NULL)) {
3411 (*ifp->if_input)(ifp, m);
3416 sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3417 sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3419 /* limit spinning on the queue */
3423 if (rx_pkts == sc->rx_budget) {
3424 fp->eth_q_stats.rx_budget_reached++;
3427 } /* while work to do */
3429 fp->rx_bd_cons = bd_cons;
3430 fp->rx_bd_prod = bd_prod_fw;
3431 fp->rx_cq_cons = sw_cq_cons;
3432 fp->rx_cq_prod = sw_cq_prod;
3434 /* Update producers */
3435 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3437 fp->eth_q_stats.rx_pkts += rx_pkts;
3438 fp->eth_q_stats.rx_calls++;
3440 BXE_FP_RX_UNLOCK(fp);
3442 return (sw_cq_cons != hw_cq_cons);
3446 bxe_free_tx_pkt(struct bxe_softc *sc,
3447 struct bxe_fastpath *fp,
3450 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3451 struct eth_tx_start_bd *tx_start_bd;
3452 uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3456 /* unmap the mbuf from non-paged memory */
3457 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3459 tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3460 nbd = le16toh(tx_start_bd->nbd) - 1;
3462 new_cons = (tx_buf->first_bd + nbd);
3465 if (__predict_true(tx_buf->m != NULL)) {
3467 fp->eth_q_stats.mbuf_alloc_tx--;
3469 fp->eth_q_stats.tx_chain_lost_mbuf++;
3473 tx_buf->first_bd = 0;
3478 /* transmit timeout watchdog */
3480 bxe_watchdog(struct bxe_softc *sc,
3481 struct bxe_fastpath *fp)
3485 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3486 BXE_FP_TX_UNLOCK(fp);
3490 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3491 if(sc->trigger_grcdump) {
3492 /* taking grcdump */
3496 BXE_FP_TX_UNLOCK(fp);
3498 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
3499 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
3504 /* processes transmit completions */
3506 bxe_txeof(struct bxe_softc *sc,
3507 struct bxe_fastpath *fp)
3509 struct ifnet *ifp = sc->ifnet;
3510 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3511 uint16_t tx_bd_avail;
3513 BXE_FP_TX_LOCK_ASSERT(fp);
3515 bd_cons = fp->tx_bd_cons;
3516 hw_cons = le16toh(*fp->tx_cons_sb);
3517 sw_cons = fp->tx_pkt_cons;
3519 while (sw_cons != hw_cons) {
3520 pkt_cons = TX_BD(sw_cons);
3523 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3524 fp->index, hw_cons, sw_cons, pkt_cons);
3526 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3531 fp->tx_pkt_cons = sw_cons;
3532 fp->tx_bd_cons = bd_cons;
3535 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3536 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3540 tx_bd_avail = bxe_tx_avail(sc, fp);
3542 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3543 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3545 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3548 if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3549 /* reset the watchdog timer if there are pending transmits */
3550 fp->watchdog_timer = BXE_TX_TIMEOUT;
3553 /* clear watchdog when there are no pending transmits */
3554 fp->watchdog_timer = 0;
3560 bxe_drain_tx_queues(struct bxe_softc *sc)
3562 struct bxe_fastpath *fp;
3565 /* wait until all TX fastpath tasks have completed */
3566 for (i = 0; i < sc->num_queues; i++) {
3571 while (bxe_has_tx_work(fp)) {
3575 BXE_FP_TX_UNLOCK(fp);
3578 BLOGE(sc, "Timeout waiting for fp[%d] "
3579 "transmits to complete!\n", i);
3580 bxe_panic(sc, ("tx drain failure\n"));
3594 bxe_del_all_macs(struct bxe_softc *sc,
3595 struct ecore_vlan_mac_obj *mac_obj,
3597 uint8_t wait_for_comp)
3599 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3602 /* wait for completion of requested */
3603 if (wait_for_comp) {
3604 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3607 /* Set the mac type of addresses we want to clear */
3608 bxe_set_bit(mac_type, &vlan_mac_flags);
3610 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3612 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n",
3613 rc, mac_type, wait_for_comp);
3620 bxe_fill_accept_flags(struct bxe_softc *sc,
3622 unsigned long *rx_accept_flags,
3623 unsigned long *tx_accept_flags)
3625 /* Clear the flags first */
3626 *rx_accept_flags = 0;
3627 *tx_accept_flags = 0;
3630 case BXE_RX_MODE_NONE:
3632 * 'drop all' supersedes any accept flags that may have been
3633 * passed to the function.
3637 case BXE_RX_MODE_NORMAL:
3638 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3639 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3640 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3642 /* internal switching mode */
3643 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3644 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3645 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3649 case BXE_RX_MODE_ALLMULTI:
3650 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3651 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3652 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3654 /* internal switching mode */
3655 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3656 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3657 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3661 case BXE_RX_MODE_PROMISC:
3663 * According to deffinition of SI mode, iface in promisc mode
3664 * should receive matched and unmatched (in resolution of port)
3667 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3668 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3669 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3670 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3672 /* internal switching mode */
3673 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3674 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3677 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3679 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3685 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode);
3689 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3690 if (rx_mode != BXE_RX_MODE_NONE) {
3691 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3692 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3699 bxe_set_q_rx_mode(struct bxe_softc *sc,
3701 unsigned long rx_mode_flags,
3702 unsigned long rx_accept_flags,
3703 unsigned long tx_accept_flags,
3704 unsigned long ramrod_flags)
3706 struct ecore_rx_mode_ramrod_params ramrod_param;
3709 memset(&ramrod_param, 0, sizeof(ramrod_param));
3711 /* Prepare ramrod parameters */
3712 ramrod_param.cid = 0;
3713 ramrod_param.cl_id = cl_id;
3714 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3715 ramrod_param.func_id = SC_FUNC(sc);
3717 ramrod_param.pstate = &sc->sp_state;
3718 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3720 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3721 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3723 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3725 ramrod_param.ramrod_flags = ramrod_flags;
3726 ramrod_param.rx_mode_flags = rx_mode_flags;
3728 ramrod_param.rx_accept_flags = rx_accept_flags;
3729 ramrod_param.tx_accept_flags = tx_accept_flags;
3731 rc = ecore_config_rx_mode(sc, &ramrod_param);
3733 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x "
3734 "rx_accept_flags 0x%x tx_accept_flags 0x%x "
3735 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id,
3736 (uint32_t)rx_mode_flags, (uint32_t)rx_accept_flags,
3737 (uint32_t)tx_accept_flags, (uint32_t)ramrod_flags, rc);
3745 bxe_set_storm_rx_mode(struct bxe_softc *sc)
3747 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3748 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3751 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3757 bxe_set_bit(RAMROD_RX, &ramrod_flags);
3758 bxe_set_bit(RAMROD_TX, &ramrod_flags);
3760 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3761 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3762 rx_accept_flags, tx_accept_flags,
3766 /* returns the "mcp load_code" according to global load_count array */
3768 bxe_nic_load_no_mcp(struct bxe_softc *sc)
3770 int path = SC_PATH(sc);
3771 int port = SC_PORT(sc);
3773 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3774 path, load_count[path][0], load_count[path][1],
3775 load_count[path][2]);
3776 load_count[path][0]++;
3777 load_count[path][1 + port]++;
3778 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3779 path, load_count[path][0], load_count[path][1],
3780 load_count[path][2]);
3781 if (load_count[path][0] == 1) {
3782 return (FW_MSG_CODE_DRV_LOAD_COMMON);
3783 } else if (load_count[path][1 + port] == 1) {
3784 return (FW_MSG_CODE_DRV_LOAD_PORT);
3786 return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3790 /* returns the "mcp load_code" according to global load_count array */
3792 bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3794 int port = SC_PORT(sc);
3795 int path = SC_PATH(sc);
3797 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3798 path, load_count[path][0], load_count[path][1],
3799 load_count[path][2]);
3800 load_count[path][0]--;
3801 load_count[path][1 + port]--;
3802 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3803 path, load_count[path][0], load_count[path][1],
3804 load_count[path][2]);
3805 if (load_count[path][0] == 0) {
3806 return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3807 } else if (load_count[path][1 + port] == 0) {
3808 return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3810 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3814 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3816 bxe_send_unload_req(struct bxe_softc *sc,
3819 uint32_t reset_code = 0;
3821 /* Select the UNLOAD request mode */
3822 if (unload_mode == UNLOAD_NORMAL) {
3823 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3825 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3828 /* Send the request to the MCP */
3829 if (!BXE_NOMCP(sc)) {
3830 reset_code = bxe_fw_command(sc, reset_code, 0);
3832 reset_code = bxe_nic_unload_no_mcp(sc);
3835 return (reset_code);
3838 /* send UNLOAD_DONE command to the MCP */
3840 bxe_send_unload_done(struct bxe_softc *sc,
3843 uint32_t reset_param =
3844 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
3846 /* Report UNLOAD_DONE to MCP */
3847 if (!BXE_NOMCP(sc)) {
3848 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
3853 bxe_func_wait_started(struct bxe_softc *sc)
3857 if (!sc->port.pmf) {
3862 * (assumption: No Attention from MCP at this stage)
3863 * PMF probably in the middle of TX disable/enable transaction
3864 * 1. Sync IRS for default SB
3865 * 2. Sync SP queue - this guarantees us that attention handling started
3866 * 3. Wait, that TX disable/enable transaction completes
3868 * 1+2 guarantee that if DCBX attention was scheduled it already changed
3869 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
3870 * received completion for the transaction the state is TX_STOPPED.
3871 * State will return to STARTED after completion of TX_STOPPED-->STARTED
3875 /* XXX make sure default SB ISR is done */
3876 /* need a way to synchronize an irq (intr_mtx?) */
3878 /* XXX flush any work queues */
3880 while (ecore_func_get_state(sc, &sc->func_obj) !=
3881 ECORE_F_STATE_STARTED && tout--) {
3885 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
3887 * Failed to complete the transaction in a "good way"
3888 * Force both transactions with CLR bit.
3890 struct ecore_func_state_params func_params = { NULL };
3892 BLOGE(sc, "Unexpected function state! "
3893 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
3895 func_params.f_obj = &sc->func_obj;
3896 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
3898 /* STARTED-->TX_STOPPED */
3899 func_params.cmd = ECORE_F_CMD_TX_STOP;
3900 ecore_func_state_change(sc, &func_params);
3902 /* TX_STOPPED-->STARTED */
3903 func_params.cmd = ECORE_F_CMD_TX_START;
3904 return (ecore_func_state_change(sc, &func_params));
3911 bxe_stop_queue(struct bxe_softc *sc,
3914 struct bxe_fastpath *fp = &sc->fp[index];
3915 struct ecore_queue_state_params q_params = { NULL };
3918 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
3920 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
3921 /* We want to wait for completion in this context */
3922 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
3924 /* Stop the primary connection: */
3926 /* ...halt the connection */
3927 q_params.cmd = ECORE_Q_CMD_HALT;
3928 rc = ecore_queue_state_change(sc, &q_params);
3933 /* ...terminate the connection */
3934 q_params.cmd = ECORE_Q_CMD_TERMINATE;
3935 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
3936 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
3937 rc = ecore_queue_state_change(sc, &q_params);
3942 /* ...delete cfc entry */
3943 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
3944 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
3945 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
3946 return (ecore_queue_state_change(sc, &q_params));
3949 /* wait for the outstanding SP commands */
3950 static inline uint8_t
3951 bxe_wait_sp_comp(struct bxe_softc *sc,
3955 int tout = 5000; /* wait for 5 secs tops */
3959 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
3968 tmp = atomic_load_acq_long(&sc->sp_state);
3970 BLOGE(sc, "Filtering completion timed out: "
3971 "sp_state 0x%lx, mask 0x%lx\n",
3980 bxe_func_stop(struct bxe_softc *sc)
3982 struct ecore_func_state_params func_params = { NULL };
3985 /* prepare parameters for function state transitions */
3986 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
3987 func_params.f_obj = &sc->func_obj;
3988 func_params.cmd = ECORE_F_CMD_STOP;
3991 * Try to stop the function the 'good way'. If it fails (in case
3992 * of a parity error during bxe_chip_cleanup()) and we are
3993 * not in a debug mode, perform a state transaction in order to
3994 * enable further HW_RESET transaction.
3996 rc = ecore_func_state_change(sc, &func_params);
3998 BLOGE(sc, "FUNC_STOP ramrod failed. "
3999 "Running a dry transaction (%d)\n", rc);
4000 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4001 return (ecore_func_state_change(sc, &func_params));
4008 bxe_reset_hw(struct bxe_softc *sc,
4011 struct ecore_func_state_params func_params = { NULL };
4013 /* Prepare parameters for function state transitions */
4014 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4016 func_params.f_obj = &sc->func_obj;
4017 func_params.cmd = ECORE_F_CMD_HW_RESET;
4019 func_params.params.hw_init.load_phase = load_code;
4021 return (ecore_func_state_change(sc, &func_params));
4025 bxe_int_disable_sync(struct bxe_softc *sc,
4029 /* prevent the HW from sending interrupts */
4030 bxe_int_disable(sc);
4033 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4034 /* make sure all ISRs are done */
4036 /* XXX make sure sp_task is not running */
4037 /* cancel and flush work queues */
4041 bxe_chip_cleanup(struct bxe_softc *sc,
4042 uint32_t unload_mode,
4045 int port = SC_PORT(sc);
4046 struct ecore_mcast_ramrod_params rparam = { NULL };
4047 uint32_t reset_code;
4050 bxe_drain_tx_queues(sc);
4052 /* give HW time to discard old tx messages */
4055 /* Clean all ETH MACs */
4056 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4058 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4061 /* Clean up UC list */
4062 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4064 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4068 if (!CHIP_IS_E1(sc)) {
4069 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4072 /* Set "drop all" to stop Rx */
4075 * We need to take the BXE_MCAST_LOCK() here in order to prevent
4076 * a race between the completion code and this code.
4080 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4081 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4083 bxe_set_storm_rx_mode(sc);
4086 /* Clean up multicast configuration */
4087 rparam.mcast_obj = &sc->mcast_obj;
4088 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4090 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4093 BXE_MCAST_UNLOCK(sc);
4095 // XXX bxe_iov_chip_cleanup(sc);
4098 * Send the UNLOAD_REQUEST to the MCP. This will return if
4099 * this function should perform FUNCTION, PORT, or COMMON HW
4102 reset_code = bxe_send_unload_req(sc, unload_mode);
4105 * (assumption: No Attention from MCP at this stage)
4106 * PMF probably in the middle of TX disable/enable transaction
4108 rc = bxe_func_wait_started(sc);
4110 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc);
4114 * Close multi and leading connections
4115 * Completions for ramrods are collected in a synchronous way
4117 for (i = 0; i < sc->num_queues; i++) {
4118 if (bxe_stop_queue(sc, i)) {
4124 * If SP settings didn't get completed so far - something
4125 * very wrong has happen.
4127 if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4128 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc);
4133 rc = bxe_func_stop(sc);
4135 BLOGE(sc, "Function stop failed!(%d)\n", rc);
4138 /* disable HW interrupts */
4139 bxe_int_disable_sync(sc, TRUE);
4141 /* detach interrupts */
4142 bxe_interrupt_detach(sc);
4144 /* Reset the chip */
4145 rc = bxe_reset_hw(sc, reset_code);
4147 BLOGE(sc, "Hardware reset failed(%d)\n", rc);
4150 /* Report UNLOAD_DONE to MCP */
4151 bxe_send_unload_done(sc, keep_link);
4155 bxe_disable_close_the_gate(struct bxe_softc *sc)
4158 int port = SC_PORT(sc);
4161 "Disabling 'close the gates'\n");
4163 if (CHIP_IS_E1(sc)) {
4164 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4165 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4166 val = REG_RD(sc, addr);
4168 REG_WR(sc, addr, val);
4170 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4171 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4172 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4173 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4178 * Cleans the object that have internal lists without sending
4179 * ramrods. Should be run when interrutps are disabled.
4182 bxe_squeeze_objects(struct bxe_softc *sc)
4184 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4185 struct ecore_mcast_ramrod_params rparam = { NULL };
4186 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4189 /* Cleanup MACs' object first... */
4191 /* Wait for completion of requested */
4192 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4193 /* Perform a dry cleanup */
4194 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4196 /* Clean ETH primary MAC */
4197 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4198 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4201 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4204 /* Cleanup UC list */
4206 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4207 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4210 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4213 /* Now clean mcast object... */
4215 rparam.mcast_obj = &sc->mcast_obj;
4216 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4218 /* Add a DEL command... */
4219 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4221 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4224 /* now wait until all pending commands are cleared */
4226 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4229 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4233 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4237 /* stop the controller */
4238 static __noinline int
4239 bxe_nic_unload(struct bxe_softc *sc,
4240 uint32_t unload_mode,
4243 uint8_t global = FALSE;
4247 BXE_CORE_LOCK_ASSERT(sc);
4249 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
4251 for (i = 0; i < sc->num_queues; i++) {
4252 struct bxe_fastpath *fp;
4256 BXE_FP_TX_UNLOCK(fp);
4259 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4261 /* mark driver as unloaded in shmem2 */
4262 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4263 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4264 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4265 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4268 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4269 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4271 * We can get here if the driver has been unloaded
4272 * during parity error recovery and is either waiting for a
4273 * leader to complete or for other functions to unload and
4274 * then ifconfig down has been issued. In this case we want to
4275 * unload and let other functions to complete a recovery
4278 sc->recovery_state = BXE_RECOVERY_DONE;
4280 bxe_release_leader_lock(sc);
4283 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4284 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x"
4285 " state = 0x%x\n", sc->recovery_state, sc->state);
4290 * Nothing to do during unload if previous bxe_nic_load()
4291 * did not completed succesfully - all resourses are released.
4293 if ((sc->state == BXE_STATE_CLOSED) ||
4294 (sc->state == BXE_STATE_ERROR)) {
4298 sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4304 sc->rx_mode = BXE_RX_MODE_NONE;
4305 /* XXX set rx mode ??? */
4307 if (IS_PF(sc) && !sc->grcdump_done) {
4308 /* set ALWAYS_ALIVE bit in shmem */
4309 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4313 bxe_stats_handle(sc, STATS_EVENT_STOP);
4314 bxe_save_statistics(sc);
4317 /* wait till consumers catch up with producers in all queues */
4318 bxe_drain_tx_queues(sc);
4320 /* if VF indicate to PF this function is going down (PF will delete sp
4321 * elements and clear initializations
4324 ; /* bxe_vfpf_close_vf(sc); */
4325 } else if (unload_mode != UNLOAD_RECOVERY) {
4326 /* if this is a normal/close unload need to clean up chip */
4327 if (!sc->grcdump_done)
4328 bxe_chip_cleanup(sc, unload_mode, keep_link);
4330 /* Send the UNLOAD_REQUEST to the MCP */
4331 bxe_send_unload_req(sc, unload_mode);
4334 * Prevent transactions to host from the functions on the
4335 * engine that doesn't reset global blocks in case of global
4336 * attention once gloabl blocks are reset and gates are opened
4337 * (the engine which leader will perform the recovery
4340 if (!CHIP_IS_E1x(sc)) {
4344 /* disable HW interrupts */
4345 bxe_int_disable_sync(sc, TRUE);
4347 /* detach interrupts */
4348 bxe_interrupt_detach(sc);
4350 /* Report UNLOAD_DONE to MCP */
4351 bxe_send_unload_done(sc, FALSE);
4355 * At this stage no more interrupts will arrive so we may safely clean
4356 * the queue'able objects here in case they failed to get cleaned so far.
4359 bxe_squeeze_objects(sc);
4362 /* There should be no more pending SP commands at this stage */
4367 bxe_free_fp_buffers(sc);
4373 bxe_free_fw_stats_mem(sc);
4375 sc->state = BXE_STATE_CLOSED;
4378 * Check if there are pending parity attentions. If there are - set
4379 * RECOVERY_IN_PROGRESS.
4381 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4382 bxe_set_reset_in_progress(sc);
4384 /* Set RESET_IS_GLOBAL if needed */
4386 bxe_set_reset_global(sc);
4391 * The last driver must disable a "close the gate" if there is no
4392 * parity attention or "process kill" pending.
4394 if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4395 bxe_reset_is_done(sc, SC_PATH(sc))) {
4396 bxe_disable_close_the_gate(sc);
4399 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4405 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4406 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4409 bxe_ifmedia_update(struct ifnet *ifp)
4411 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc;
4412 struct ifmedia *ifm;
4416 /* We only support Ethernet media type. */
4417 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4421 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4427 case IFM_10G_TWINAX:
4429 /* We don't support changing the media type. */
4430 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4431 IFM_SUBTYPE(ifm->ifm_media));
4439 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4442 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4444 struct bxe_softc *sc = ifp->if_softc;
4446 /* Report link down if the driver isn't running. */
4447 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4448 ifmr->ifm_active |= IFM_NONE;
4452 /* Setup the default interface info. */
4453 ifmr->ifm_status = IFM_AVALID;
4454 ifmr->ifm_active = IFM_ETHER;
4456 if (sc->link_vars.link_up) {
4457 ifmr->ifm_status |= IFM_ACTIVE;
4459 ifmr->ifm_active |= IFM_NONE;
4463 ifmr->ifm_active |= sc->media;
4465 if (sc->link_vars.duplex == DUPLEX_FULL) {
4466 ifmr->ifm_active |= IFM_FDX;
4468 ifmr->ifm_active |= IFM_HDX;
4473 bxe_handle_chip_tq(void *context,
4476 struct bxe_softc *sc = (struct bxe_softc *)context;
4477 long work = atomic_load_acq_long(&sc->chip_tq_flags);
4481 case CHIP_TQ_REINIT:
4482 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
4483 /* restart the interface */
4484 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4485 bxe_periodic_stop(sc);
4487 bxe_stop_locked(sc);
4488 bxe_init_locked(sc);
4489 BXE_CORE_UNLOCK(sc);
4499 * Handles any IOCTL calls from the operating system.
4502 * 0 = Success, >0 Failure
4505 bxe_ioctl(struct ifnet *ifp,
4509 struct bxe_softc *sc = ifp->if_softc;
4510 struct ifreq *ifr = (struct ifreq *)data;
4515 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4516 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4521 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4524 if (sc->mtu == ifr->ifr_mtu) {
4525 /* nothing to change */
4529 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4530 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4531 ifr->ifr_mtu, mtu_min, mtu_max);
4536 atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4537 (unsigned long)ifr->ifr_mtu);
4538 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu,
4539 (unsigned long)ifr->ifr_mtu);
4545 /* toggle the interface state up or down */
4546 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4549 /* check if the interface is up */
4550 if (ifp->if_flags & IFF_UP) {
4551 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4552 /* set the receive mode flags */
4553 bxe_set_rx_mode(sc);
4554 } else if(sc->state != BXE_STATE_DISABLED) {
4555 bxe_init_locked(sc);
4558 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4559 bxe_periodic_stop(sc);
4560 bxe_stop_locked(sc);
4563 BXE_CORE_UNLOCK(sc);
4569 /* add/delete multicast addresses */
4570 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4572 /* check if the interface is up */
4573 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4574 /* set the receive mode flags */
4576 bxe_set_rx_mode(sc);
4577 BXE_CORE_UNLOCK(sc);
4583 /* find out which capabilities have changed */
4584 mask = (ifr->ifr_reqcap ^ ifp->if_capenable);
4586 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4589 /* toggle the LRO capabilites enable flag */
4590 if (mask & IFCAP_LRO) {
4591 ifp->if_capenable ^= IFCAP_LRO;
4592 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4593 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF");
4597 /* toggle the TXCSUM checksum capabilites enable flag */
4598 if (mask & IFCAP_TXCSUM) {
4599 ifp->if_capenable ^= IFCAP_TXCSUM;
4600 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4601 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF");
4602 if (ifp->if_capenable & IFCAP_TXCSUM) {
4603 ifp->if_hwassist = (CSUM_IP |
4610 ifp->if_hwassist = 0;
4614 /* toggle the RXCSUM checksum capabilities enable flag */
4615 if (mask & IFCAP_RXCSUM) {
4616 ifp->if_capenable ^= IFCAP_RXCSUM;
4617 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4618 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF");
4619 if (ifp->if_capenable & IFCAP_RXCSUM) {
4620 ifp->if_hwassist = (CSUM_IP |
4627 ifp->if_hwassist = 0;
4631 /* toggle TSO4 capabilities enabled flag */
4632 if (mask & IFCAP_TSO4) {
4633 ifp->if_capenable ^= IFCAP_TSO4;
4634 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4635 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF");
4638 /* toggle TSO6 capabilities enabled flag */
4639 if (mask & IFCAP_TSO6) {
4640 ifp->if_capenable ^= IFCAP_TSO6;
4641 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4642 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF");
4645 /* toggle VLAN_HWTSO capabilities enabled flag */
4646 if (mask & IFCAP_VLAN_HWTSO) {
4647 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4648 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4649 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4652 /* toggle VLAN_HWCSUM capabilities enabled flag */
4653 if (mask & IFCAP_VLAN_HWCSUM) {
4654 /* XXX investigate this... */
4655 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4659 /* toggle VLAN_MTU capabilities enable flag */
4660 if (mask & IFCAP_VLAN_MTU) {
4661 /* XXX investigate this... */
4662 BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4666 /* toggle VLAN_HWTAGGING capabilities enabled flag */
4667 if (mask & IFCAP_VLAN_HWTAGGING) {
4668 /* XXX investigate this... */
4669 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4673 /* toggle VLAN_HWFILTER capabilities enabled flag */
4674 if (mask & IFCAP_VLAN_HWFILTER) {
4675 /* XXX investigate this... */
4676 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4688 /* set/get interface media */
4689 BLOGD(sc, DBG_IOCTL,
4690 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4692 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4696 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
4698 error = ether_ioctl(ifp, command, data);
4702 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4703 BLOGD(sc, DBG_LOAD | DBG_IOCTL,
4704 "Re-initializing hardware from IOCTL change\n");
4705 bxe_periodic_stop(sc);
4707 bxe_stop_locked(sc);
4708 bxe_init_locked(sc);
4709 BXE_CORE_UNLOCK(sc);
4715 static __noinline void
4716 bxe_dump_mbuf(struct bxe_softc *sc,
4723 if (!(sc->debug & DBG_MBUF)) {
4728 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
4734 #if __FreeBSD_version >= 1000000
4736 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4737 i, m, m->m_len, m->m_flags,
4738 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
4740 if (m->m_flags & M_PKTHDR) {
4742 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4743 i, m->m_pkthdr.len, m->m_flags,
4744 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
4745 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
4746 "\22M_PROMISC\23M_NOFREE",
4747 (int)m->m_pkthdr.csum_flags,
4748 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
4749 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
4750 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
4751 "\14CSUM_PSEUDO_HDR");
4755 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
4756 i, m, m->m_len, m->m_flags,
4757 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
4759 if (m->m_flags & M_PKTHDR) {
4761 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
4762 i, m->m_pkthdr.len, m->m_flags,
4763 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
4764 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
4765 "\22M_PROMISC\23M_NOFREE",
4766 (int)m->m_pkthdr.csum_flags,
4767 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
4768 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
4769 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
4770 "\14CSUM_PSEUDO_HDR");
4772 #endif /* #if __FreeBSD_version >= 1000000 */
4774 if (m->m_flags & M_EXT) {
4775 switch (m->m_ext.ext_type) {
4776 case EXT_CLUSTER: type = "EXT_CLUSTER"; break;
4777 case EXT_SFBUF: type = "EXT_SFBUF"; break;
4778 case EXT_JUMBOP: type = "EXT_JUMBOP"; break;
4779 case EXT_JUMBO9: type = "EXT_JUMBO9"; break;
4780 case EXT_JUMBO16: type = "EXT_JUMBO16"; break;
4781 case EXT_PACKET: type = "EXT_PACKET"; break;
4782 case EXT_MBUF: type = "EXT_MBUF"; break;
4783 case EXT_NET_DRV: type = "EXT_NET_DRV"; break;
4784 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break;
4785 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
4786 case EXT_EXTREF: type = "EXT_EXTREF"; break;
4787 default: type = "UNKNOWN"; break;
4791 "%02d: - m_ext: %p ext_size=%d type=%s\n",
4792 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
4796 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
4805 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
4806 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
4807 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
4808 * The headers comes in a seperate bd in FreeBSD so 13-3=10.
4809 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
4812 bxe_chktso_window(struct bxe_softc *sc,
4814 bus_dma_segment_t *segs,
4817 uint32_t num_wnds, wnd_size, wnd_sum;
4818 int32_t frag_idx, wnd_idx;
4819 unsigned short lso_mss;
4825 num_wnds = nsegs - wnd_size;
4826 lso_mss = htole16(m->m_pkthdr.tso_segsz);
4829 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
4830 * first window sum of data while skipping the first assuming it is the
4831 * header in FreeBSD.
4833 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
4834 wnd_sum += htole16(segs[frag_idx].ds_len);
4837 /* check the first 10 bd window size */
4838 if (wnd_sum < lso_mss) {
4842 /* run through the windows */
4843 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
4844 /* subtract the first mbuf->m_len of the last wndw(-header) */
4845 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
4846 /* add the next mbuf len to the len of our new window */
4847 wnd_sum += htole16(segs[frag_idx].ds_len);
4848 if (wnd_sum < lso_mss) {
4857 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
4859 uint32_t *parsing_data)
4861 struct ether_vlan_header *eh = NULL;
4862 struct ip *ip4 = NULL;
4863 struct ip6_hdr *ip6 = NULL;
4865 struct tcphdr *th = NULL;
4866 int e_hlen, ip_hlen, l4_off;
4869 if (m->m_pkthdr.csum_flags == CSUM_IP) {
4870 /* no L4 checksum offload needed */
4874 /* get the Ethernet header */
4875 eh = mtod(m, struct ether_vlan_header *);
4877 /* handle VLAN encapsulation if present */
4878 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4879 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4880 proto = ntohs(eh->evl_proto);
4882 e_hlen = ETHER_HDR_LEN;
4883 proto = ntohs(eh->evl_encap_proto);
4888 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4889 ip4 = (m->m_len < sizeof(struct ip)) ?
4890 (struct ip *)m->m_next->m_data :
4891 (struct ip *)(m->m_data + e_hlen);
4892 /* ip_hl is number of 32-bit words */
4893 ip_hlen = (ip4->ip_hl << 2);
4896 case ETHERTYPE_IPV6:
4897 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4898 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4899 (struct ip6_hdr *)m->m_next->m_data :
4900 (struct ip6_hdr *)(m->m_data + e_hlen);
4901 /* XXX cannot support offload with IPv6 extensions */
4902 ip_hlen = sizeof(struct ip6_hdr);
4906 /* We can't offload in this case... */
4907 /* XXX error stat ??? */
4911 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
4912 l4_off = (e_hlen + ip_hlen);
4915 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
4916 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
4918 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
4921 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
4922 th = (struct tcphdr *)(ip + ip_hlen);
4923 /* th_off is number of 32-bit words */
4924 *parsing_data |= ((th->th_off <<
4925 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
4926 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
4927 return (l4_off + (th->th_off << 2)); /* entire header length */
4928 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
4930 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
4931 return (l4_off + sizeof(struct udphdr)); /* entire header length */
4933 /* XXX error stat ??? */
4939 bxe_set_pbd_csum(struct bxe_fastpath *fp,
4941 struct eth_tx_parse_bd_e1x *pbd)
4943 struct ether_vlan_header *eh = NULL;
4944 struct ip *ip4 = NULL;
4945 struct ip6_hdr *ip6 = NULL;
4947 struct tcphdr *th = NULL;
4948 struct udphdr *uh = NULL;
4949 int e_hlen, ip_hlen;
4955 /* get the Ethernet header */
4956 eh = mtod(m, struct ether_vlan_header *);
4958 /* handle VLAN encapsulation if present */
4959 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
4960 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4961 proto = ntohs(eh->evl_proto);
4963 e_hlen = ETHER_HDR_LEN;
4964 proto = ntohs(eh->evl_encap_proto);
4969 /* get the IP header, if mbuf len < 20 then header in next mbuf */
4970 ip4 = (m->m_len < sizeof(struct ip)) ?
4971 (struct ip *)m->m_next->m_data :
4972 (struct ip *)(m->m_data + e_hlen);
4973 /* ip_hl is number of 32-bit words */
4974 ip_hlen = (ip4->ip_hl << 1);
4977 case ETHERTYPE_IPV6:
4978 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
4979 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
4980 (struct ip6_hdr *)m->m_next->m_data :
4981 (struct ip6_hdr *)(m->m_data + e_hlen);
4982 /* XXX cannot support offload with IPv6 extensions */
4983 ip_hlen = (sizeof(struct ip6_hdr) >> 1);
4987 /* We can't offload in this case... */
4988 /* XXX error stat ??? */
4992 hlen = (e_hlen >> 1);
4994 /* note that rest of global_data is indirectly zeroed here */
4995 if (m->m_flags & M_VLANTAG) {
4997 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
4999 pbd->global_data = htole16(hlen);
5002 pbd->ip_hlen_w = ip_hlen;
5004 hlen += pbd->ip_hlen_w;
5006 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5008 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5011 th = (struct tcphdr *)(ip + (ip_hlen << 1));
5012 /* th_off is number of 32-bit words */
5013 hlen += (uint16_t)(th->th_off << 1);
5014 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5016 uh = (struct udphdr *)(ip + (ip_hlen << 1));
5017 hlen += (sizeof(struct udphdr) / 2);
5019 /* valid case as only CSUM_IP was set */
5023 pbd->total_hlen_w = htole16(hlen);
5025 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5028 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5029 pbd->tcp_pseudo_csum = ntohs(th->th_sum);
5030 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5032 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5035 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
5036 * checksums and does not know anything about the UDP header and where
5037 * the checksum field is located. It only knows about TCP. Therefore
5038 * we "lie" to the hardware for outgoing UDP packets w/ checksum
5039 * offload. Since the checksum field offset for TCP is 16 bytes and
5040 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5041 * bytes less than the start of the UDP header. This allows the
5042 * hardware to write the checksum in the correct spot. But the
5043 * hardware will compute a checksum which includes the last 10 bytes
5044 * of the IP header. To correct this we tweak the stack computed
5045 * pseudo checksum by folding in the calculation of the inverse
5046 * checksum for those final 10 bytes of the IP header. This allows
5047 * the correct checksum to be computed by the hardware.
5050 /* set pointer 10 bytes before UDP header */
5051 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5053 /* calculate a pseudo header checksum over the first 10 bytes */
5054 tmp_csum = in_pseudo(*tmp_uh,
5056 *(uint16_t *)(tmp_uh + 2));
5058 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5061 return (hlen * 2); /* entire header length, number of bytes */
5065 bxe_set_pbd_lso_e2(struct mbuf *m,
5066 uint32_t *parsing_data)
5068 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5069 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5070 ETH_TX_PARSE_BD_E2_LSO_MSS);
5072 /* XXX test for IPv6 with extension header... */
5076 bxe_set_pbd_lso(struct mbuf *m,
5077 struct eth_tx_parse_bd_e1x *pbd)
5079 struct ether_vlan_header *eh = NULL;
5080 struct ip *ip = NULL;
5081 struct tcphdr *th = NULL;
5084 /* get the Ethernet header */
5085 eh = mtod(m, struct ether_vlan_header *);
5087 /* handle VLAN encapsulation if present */
5088 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5089 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5091 /* get the IP and TCP header, with LSO entire header in first mbuf */
5092 /* XXX assuming IPv4 */
5093 ip = (struct ip *)(m->m_data + e_hlen);
5094 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5096 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5097 pbd->tcp_send_seq = ntohl(th->th_seq);
5098 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5102 pbd->ip_id = ntohs(ip->ip_id);
5103 pbd->tcp_pseudo_csum =
5104 ntohs(in_pseudo(ip->ip_src.s_addr,
5106 htons(IPPROTO_TCP)));
5109 pbd->tcp_pseudo_csum =
5110 ntohs(in_pseudo(&ip6->ip6_src,
5112 htons(IPPROTO_TCP)));
5116 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5120 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5121 * visible to the controller.
5123 * If an mbuf is submitted to this routine and cannot be given to the
5124 * controller (e.g. it has too many fragments) then the function may free
5125 * the mbuf and return to the caller.
5128 * 0 = Success, !0 = Failure
5129 * Note the side effect that an mbuf may be freed if it causes a problem.
5132 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5134 bus_dma_segment_t segs[32];
5136 struct bxe_sw_tx_bd *tx_buf;
5137 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5138 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5139 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5140 struct eth_tx_bd *tx_data_bd;
5141 struct eth_tx_bd *tx_total_pkt_size_bd;
5142 struct eth_tx_start_bd *tx_start_bd;
5143 uint16_t bd_prod, pkt_prod, total_pkt_size;
5145 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5146 struct bxe_softc *sc;
5147 uint16_t tx_bd_avail;
5148 struct ether_vlan_header *eh;
5149 uint32_t pbd_e2_parsing_data = 0;
5156 #if __FreeBSD_version >= 800000
5157 M_ASSERTPKTHDR(*m_head);
5158 #endif /* #if __FreeBSD_version >= 800000 */
5161 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5164 tx_total_pkt_size_bd = NULL;
5166 /* get the H/W pointer for packets and BDs */
5167 pkt_prod = fp->tx_pkt_prod;
5168 bd_prod = fp->tx_bd_prod;
5170 mac_type = UNICAST_ADDRESS;
5172 /* map the mbuf into the next open DMAable memory */
5173 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5174 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5176 segs, &nsegs, BUS_DMA_NOWAIT);
5178 /* mapping errors */
5179 if(__predict_false(error != 0)) {
5180 fp->eth_q_stats.tx_dma_mapping_failure++;
5181 if (error == ENOMEM) {
5182 /* resource issue, try again later */
5184 } else if (error == EFBIG) {
5185 /* possibly recoverable with defragmentation */
5186 fp->eth_q_stats.mbuf_defrag_attempts++;
5187 m0 = m_defrag(*m_head, M_DONTWAIT);
5189 fp->eth_q_stats.mbuf_defrag_failures++;
5192 /* defrag successful, try mapping again */
5194 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5196 segs, &nsegs, BUS_DMA_NOWAIT);
5198 fp->eth_q_stats.tx_dma_mapping_failure++;
5203 /* unknown, unrecoverable mapping error */
5204 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5205 bxe_dump_mbuf(sc, m0, FALSE);
5209 goto bxe_tx_encap_continue;
5212 tx_bd_avail = bxe_tx_avail(sc, fp);
5214 /* make sure there is enough room in the send queue */
5215 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5216 /* Recoverable, try again later. */
5217 fp->eth_q_stats.tx_hw_queue_full++;
5218 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5220 goto bxe_tx_encap_continue;
5223 /* capture the current H/W TX chain high watermark */
5224 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5225 (TX_BD_USABLE - tx_bd_avail))) {
5226 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5229 /* make sure it fits in the packet window */
5230 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5232 * The mbuf may be to big for the controller to handle. If the frame
5233 * is a TSO frame we'll need to do an additional check.
5235 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5236 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5237 goto bxe_tx_encap_continue; /* OK to send */
5239 fp->eth_q_stats.tx_window_violation_tso++;
5242 fp->eth_q_stats.tx_window_violation_std++;
5245 /* lets try to defragment this mbuf and remap it */
5246 fp->eth_q_stats.mbuf_defrag_attempts++;
5247 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5249 m0 = m_defrag(*m_head, M_DONTWAIT);
5251 fp->eth_q_stats.mbuf_defrag_failures++;
5252 /* Ugh, just drop the frame... :( */
5255 /* defrag successful, try mapping again */
5257 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5259 segs, &nsegs, BUS_DMA_NOWAIT);
5261 fp->eth_q_stats.tx_dma_mapping_failure++;
5262 /* No sense in trying to defrag/copy chain, drop it. :( */
5265 /* if the chain is still too long then drop it */
5266 if(m0->m_pkthdr.csum_flags & CSUM_TSO) {
5268 * in case TSO is enabled nsegs should be checked against
5269 * BXE_TSO_MAX_SEGMENTS
5271 if (__predict_false(nsegs > BXE_TSO_MAX_SEGMENTS)) {
5272 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5273 fp->eth_q_stats.nsegs_path1_errors++;
5277 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5278 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5279 fp->eth_q_stats.nsegs_path2_errors++;
5287 bxe_tx_encap_continue:
5289 /* Check for errors */
5292 /* recoverable try again later */
5294 fp->eth_q_stats.tx_soft_errors++;
5295 fp->eth_q_stats.mbuf_alloc_tx--;
5303 /* set flag according to packet type (UNICAST_ADDRESS is default) */
5304 if (m0->m_flags & M_BCAST) {
5305 mac_type = BROADCAST_ADDRESS;
5306 } else if (m0->m_flags & M_MCAST) {
5307 mac_type = MULTICAST_ADDRESS;
5310 /* store the mbuf into the mbuf ring */
5312 tx_buf->first_bd = fp->tx_bd_prod;
5315 /* prepare the first transmit (start) BD for the mbuf */
5316 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5319 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5320 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5322 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5323 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5324 tx_start_bd->nbytes = htole16(segs[0].ds_len);
5325 total_pkt_size += tx_start_bd->nbytes;
5326 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5328 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5330 /* all frames have at least Start BD + Parsing BD */
5332 tx_start_bd->nbd = htole16(nbds);
5334 if (m0->m_flags & M_VLANTAG) {
5335 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5336 tx_start_bd->bd_flags.as_bitfield |=
5337 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5339 /* vf tx, start bd must hold the ethertype for fw to enforce it */
5341 /* map ethernet header to find type and header length */
5342 eh = mtod(m0, struct ether_vlan_header *);
5343 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5345 /* used by FW for packet accounting */
5346 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5351 * add a parsing BD from the chain. The parsing BD is always added
5352 * though it is only used for TSO and chksum
5354 bd_prod = TX_BD_NEXT(bd_prod);
5356 if (m0->m_pkthdr.csum_flags) {
5357 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5358 fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5359 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5362 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5363 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5364 ETH_TX_BD_FLAGS_L4_CSUM);
5365 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5366 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5367 ETH_TX_BD_FLAGS_IS_UDP |
5368 ETH_TX_BD_FLAGS_L4_CSUM);
5369 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5370 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5371 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5372 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5373 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5374 ETH_TX_BD_FLAGS_IS_UDP);
5378 if (!CHIP_IS_E1x(sc)) {
5379 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5380 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5382 if (m0->m_pkthdr.csum_flags) {
5383 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5386 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5389 uint16_t global_data = 0;
5391 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5392 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5394 if (m0->m_pkthdr.csum_flags) {
5395 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5398 SET_FLAG(global_data,
5399 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5400 pbd_e1x->global_data |= htole16(global_data);
5403 /* setup the parsing BD with TSO specific info */
5404 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5405 fp->eth_q_stats.tx_ofld_frames_lso++;
5406 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5408 if (__predict_false(tx_start_bd->nbytes > hlen)) {
5409 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5411 /* split the first BD into header/data making the fw job easy */
5413 tx_start_bd->nbd = htole16(nbds);
5414 tx_start_bd->nbytes = htole16(hlen);
5416 bd_prod = TX_BD_NEXT(bd_prod);
5418 /* new transmit BD after the tx_parse_bd */
5419 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5420 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5421 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5422 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen);
5423 if (tx_total_pkt_size_bd == NULL) {
5424 tx_total_pkt_size_bd = tx_data_bd;
5428 "TSO split header size is %d (%x:%x) nbds %d\n",
5429 le16toh(tx_start_bd->nbytes),
5430 le32toh(tx_start_bd->addr_hi),
5431 le32toh(tx_start_bd->addr_lo),
5435 if (!CHIP_IS_E1x(sc)) {
5436 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5438 bxe_set_pbd_lso(m0, pbd_e1x);
5442 if (pbd_e2_parsing_data) {
5443 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5446 /* prepare remaining BDs, start tx bd contains first seg/frag */
5447 for (i = 1; i < nsegs ; i++) {
5448 bd_prod = TX_BD_NEXT(bd_prod);
5449 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5450 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5451 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5452 tx_data_bd->nbytes = htole16(segs[i].ds_len);
5453 if (tx_total_pkt_size_bd == NULL) {
5454 tx_total_pkt_size_bd = tx_data_bd;
5456 total_pkt_size += tx_data_bd->nbytes;
5459 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5461 if (tx_total_pkt_size_bd != NULL) {
5462 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5465 if (__predict_false(sc->debug & DBG_TX)) {
5466 tmp_bd = tx_buf->first_bd;
5467 for (i = 0; i < nbds; i++)
5471 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5472 "bd_flags=0x%x hdr_nbds=%d\n",
5475 le16toh(tx_start_bd->nbd),
5476 le16toh(tx_start_bd->vlan_or_ethertype),
5477 tx_start_bd->bd_flags.as_bitfield,
5478 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5479 } else if (i == 1) {
5482 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5483 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5484 "tcp_seq=%u total_hlen_w=%u\n",
5487 pbd_e1x->global_data,
5492 pbd_e1x->tcp_pseudo_csum,
5493 pbd_e1x->tcp_send_seq,
5494 le16toh(pbd_e1x->total_hlen_w));
5495 } else { /* if (pbd_e2) */
5497 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5498 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5501 pbd_e2->data.mac_addr.dst_hi,
5502 pbd_e2->data.mac_addr.dst_mid,
5503 pbd_e2->data.mac_addr.dst_lo,
5504 pbd_e2->data.mac_addr.src_hi,
5505 pbd_e2->data.mac_addr.src_mid,
5506 pbd_e2->data.mac_addr.src_lo,
5507 pbd_e2->parsing_data);
5511 if (i != 1) { /* skip parse db as it doesn't hold data */
5512 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5514 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5517 le16toh(tx_data_bd->nbytes),
5518 le32toh(tx_data_bd->addr_hi),
5519 le32toh(tx_data_bd->addr_lo));
5522 tmp_bd = TX_BD_NEXT(tmp_bd);
5526 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5528 /* update TX BD producer index value for next TX */
5529 bd_prod = TX_BD_NEXT(bd_prod);
5532 * If the chain of tx_bd's describing this frame is adjacent to or spans
5533 * an eth_tx_next_bd element then we need to increment the nbds value.
5535 if (TX_BD_IDX(bd_prod) < nbds) {
5539 /* don't allow reordering of writes for nbd and packets */
5542 fp->tx_db.data.prod += nbds;
5544 /* producer points to the next free tx_bd at this point */
5546 fp->tx_bd_prod = bd_prod;
5548 DOORBELL(sc, fp->index, fp->tx_db.raw);
5550 fp->eth_q_stats.tx_pkts++;
5552 /* Prevent speculative reads from getting ahead of the status block. */
5553 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5554 0, 0, BUS_SPACE_BARRIER_READ);
5556 /* Prevent speculative reads from getting ahead of the doorbell. */
5557 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5558 0, 0, BUS_SPACE_BARRIER_READ);
5564 bxe_tx_start_locked(struct bxe_softc *sc,
5566 struct bxe_fastpath *fp)
5568 struct mbuf *m = NULL;
5570 uint16_t tx_bd_avail;
5572 BXE_FP_TX_LOCK_ASSERT(fp);
5574 /* keep adding entries while there are frames to send */
5575 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5578 * check for any frames to send
5579 * dequeue can still be NULL even if queue is not empty
5581 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
5582 if (__predict_false(m == NULL)) {
5586 /* the mbuf now belongs to us */
5587 fp->eth_q_stats.mbuf_alloc_tx++;
5590 * Put the frame into the transmit ring. If we don't have room,
5591 * place the mbuf back at the head of the TX queue, set the
5592 * OACTIVE flag, and wait for the NIC to drain the chain.
5594 if (__predict_false(bxe_tx_encap(fp, &m))) {
5595 fp->eth_q_stats.tx_encap_failures++;
5597 /* mark the TX queue as full and return the frame */
5598 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5599 IFQ_DRV_PREPEND(&ifp->if_snd, m);
5600 fp->eth_q_stats.mbuf_alloc_tx--;
5601 fp->eth_q_stats.tx_queue_xoff++;
5604 /* stop looking for more work */
5608 /* the frame was enqueued successfully */
5611 /* send a copy of the frame to any BPF listeners. */
5614 tx_bd_avail = bxe_tx_avail(sc, fp);
5616 /* handle any completions if we're running low */
5617 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5618 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5620 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5626 /* all TX packets were dequeued and/or the tx ring is full */
5628 /* reset the TX watchdog timeout timer */
5629 fp->watchdog_timer = BXE_TX_TIMEOUT;
5633 /* Legacy (non-RSS) dispatch routine */
5635 bxe_tx_start(struct ifnet *ifp)
5637 struct bxe_softc *sc;
5638 struct bxe_fastpath *fp;
5642 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5643 BLOGW(sc, "Interface not running, ignoring transmit request\n");
5647 if (!sc->link_vars.link_up) {
5648 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5654 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5655 fp->eth_q_stats.tx_queue_full_return++;
5660 bxe_tx_start_locked(sc, ifp, fp);
5661 BXE_FP_TX_UNLOCK(fp);
5664 #if __FreeBSD_version >= 901504
5667 bxe_tx_mq_start_locked(struct bxe_softc *sc,
5669 struct bxe_fastpath *fp,
5672 struct buf_ring *tx_br = fp->tx_br;
5674 int depth, rc, tx_count;
5675 uint16_t tx_bd_avail;
5679 BXE_FP_TX_LOCK_ASSERT(fp);
5681 if (sc->state != BXE_STATE_OPEN) {
5682 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5687 BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
5692 rc = drbr_enqueue(ifp, tx_br, m);
5694 fp->eth_q_stats.tx_soft_errors++;
5695 goto bxe_tx_mq_start_locked_exit;
5699 if (!sc->link_vars.link_up || !(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5700 fp->eth_q_stats.tx_request_link_down_failures++;
5701 goto bxe_tx_mq_start_locked_exit;
5704 /* fetch the depth of the driver queue */
5705 depth = drbr_inuse(ifp, tx_br);
5706 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
5707 fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
5710 /* keep adding entries while there are frames to send */
5711 while ((next = drbr_peek(ifp, tx_br)) != NULL) {
5712 /* handle any completions if we're running low */
5713 tx_bd_avail = bxe_tx_avail(sc, fp);
5714 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5715 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5717 tx_bd_avail = bxe_tx_avail(sc, fp);
5718 if (tx_bd_avail < (BXE_TSO_MAX_SEGMENTS + 1)) {
5719 fp->eth_q_stats.bd_avail_too_less_failures++;
5721 drbr_advance(ifp, tx_br);
5727 /* the mbuf now belongs to us */
5728 fp->eth_q_stats.mbuf_alloc_tx++;
5731 * Put the frame into the transmit ring. If we don't have room,
5732 * place the mbuf back at the head of the TX queue, set the
5733 * OACTIVE flag, and wait for the NIC to drain the chain.
5735 rc = bxe_tx_encap(fp, &next);
5736 if (__predict_false(rc != 0)) {
5737 fp->eth_q_stats.tx_encap_failures++;
5739 /* mark the TX queue as full and save the frame */
5740 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5741 drbr_putback(ifp, tx_br, next);
5742 fp->eth_q_stats.mbuf_alloc_tx--;
5743 fp->eth_q_stats.tx_frames_deferred++;
5745 drbr_advance(ifp, tx_br);
5747 /* stop looking for more work */
5751 /* the transmit frame was enqueued successfully */
5754 /* send a copy of the frame to any BPF listeners */
5755 BPF_MTAP(ifp, next);
5757 drbr_advance(ifp, tx_br);
5760 /* all TX packets were dequeued and/or the tx ring is full */
5762 /* reset the TX watchdog timeout timer */
5763 fp->watchdog_timer = BXE_TX_TIMEOUT;
5766 bxe_tx_mq_start_locked_exit:
5767 /* If we didn't drain the drbr, enqueue a task in the future to do it. */
5768 if (!drbr_empty(ifp, tx_br)) {
5769 fp->eth_q_stats.tx_mq_not_empty++;
5770 taskqueue_enqueue_timeout(fp->tq, &fp->tx_timeout_task, 1);
5777 bxe_tx_mq_start_deferred(void *arg,
5780 struct bxe_fastpath *fp = (struct bxe_fastpath *)arg;
5781 struct bxe_softc *sc = fp->sc;
5782 struct ifnet *ifp = sc->ifnet;
5785 bxe_tx_mq_start_locked(sc, ifp, fp, NULL);
5786 BXE_FP_TX_UNLOCK(fp);
5789 /* Multiqueue (TSS) dispatch routine. */
5791 bxe_tx_mq_start(struct ifnet *ifp,
5794 struct bxe_softc *sc = ifp->if_softc;
5795 struct bxe_fastpath *fp;
5798 fp_index = 0; /* default is the first queue */
5800 /* check if flowid is set */
5802 if (BXE_VALID_FLOWID(m))
5803 fp_index = (m->m_pkthdr.flowid % sc->num_queues);
5805 fp = &sc->fp[fp_index];
5807 if (sc->state != BXE_STATE_OPEN) {
5808 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++;
5812 if (BXE_FP_TX_TRYLOCK(fp)) {
5813 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
5814 BXE_FP_TX_UNLOCK(fp);
5816 rc = drbr_enqueue(ifp, fp->tx_br, m);
5817 taskqueue_enqueue(fp->tq, &fp->tx_task);
5824 bxe_mq_flush(struct ifnet *ifp)
5826 struct bxe_softc *sc = ifp->if_softc;
5827 struct bxe_fastpath *fp;
5831 for (i = 0; i < sc->num_queues; i++) {
5834 if (fp->state != BXE_FP_STATE_IRQ) {
5835 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
5836 fp->index, fp->state);
5840 if (fp->tx_br != NULL) {
5841 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
5843 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
5846 BXE_FP_TX_UNLOCK(fp);
5853 #endif /* FreeBSD_version >= 901504 */
5856 bxe_cid_ilt_lines(struct bxe_softc *sc)
5859 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
5861 return (L2_ILT_LINES(sc));
5865 bxe_ilt_set_info(struct bxe_softc *sc)
5867 struct ilt_client_info *ilt_client;
5868 struct ecore_ilt *ilt = sc->ilt;
5871 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
5872 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
5875 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
5876 ilt_client->client_num = ILT_CLIENT_CDU;
5877 ilt_client->page_size = CDU_ILT_PAGE_SZ;
5878 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
5879 ilt_client->start = line;
5880 line += bxe_cid_ilt_lines(sc);
5882 if (CNIC_SUPPORT(sc)) {
5883 line += CNIC_ILT_LINES;
5886 ilt_client->end = (line - 1);
5889 "ilt client[CDU]: start %d, end %d, "
5890 "psz 0x%x, flags 0x%x, hw psz %d\n",
5891 ilt_client->start, ilt_client->end,
5892 ilt_client->page_size,
5894 ilog2(ilt_client->page_size >> 12));
5897 if (QM_INIT(sc->qm_cid_count)) {
5898 ilt_client = &ilt->clients[ILT_CLIENT_QM];
5899 ilt_client->client_num = ILT_CLIENT_QM;
5900 ilt_client->page_size = QM_ILT_PAGE_SZ;
5901 ilt_client->flags = 0;
5902 ilt_client->start = line;
5904 /* 4 bytes for each cid */
5905 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
5908 ilt_client->end = (line - 1);
5911 "ilt client[QM]: start %d, end %d, "
5912 "psz 0x%x, flags 0x%x, hw psz %d\n",
5913 ilt_client->start, ilt_client->end,
5914 ilt_client->page_size, ilt_client->flags,
5915 ilog2(ilt_client->page_size >> 12));
5918 if (CNIC_SUPPORT(sc)) {
5920 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
5921 ilt_client->client_num = ILT_CLIENT_SRC;
5922 ilt_client->page_size = SRC_ILT_PAGE_SZ;
5923 ilt_client->flags = 0;
5924 ilt_client->start = line;
5925 line += SRC_ILT_LINES;
5926 ilt_client->end = (line - 1);
5929 "ilt client[SRC]: start %d, end %d, "
5930 "psz 0x%x, flags 0x%x, hw psz %d\n",
5931 ilt_client->start, ilt_client->end,
5932 ilt_client->page_size, ilt_client->flags,
5933 ilog2(ilt_client->page_size >> 12));
5936 ilt_client = &ilt->clients[ILT_CLIENT_TM];
5937 ilt_client->client_num = ILT_CLIENT_TM;
5938 ilt_client->page_size = TM_ILT_PAGE_SZ;
5939 ilt_client->flags = 0;
5940 ilt_client->start = line;
5941 line += TM_ILT_LINES;
5942 ilt_client->end = (line - 1);
5945 "ilt client[TM]: start %d, end %d, "
5946 "psz 0x%x, flags 0x%x, hw psz %d\n",
5947 ilt_client->start, ilt_client->end,
5948 ilt_client->page_size, ilt_client->flags,
5949 ilog2(ilt_client->page_size >> 12));
5952 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
5956 bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
5959 uint32_t rx_buf_size;
5961 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu);
5963 for (i = 0; i < sc->num_queues; i++) {
5964 if(rx_buf_size <= MCLBYTES){
5965 sc->fp[i].rx_buf_size = rx_buf_size;
5966 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5967 }else if (rx_buf_size <= MJUMPAGESIZE){
5968 sc->fp[i].rx_buf_size = rx_buf_size;
5969 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5970 }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){
5971 sc->fp[i].rx_buf_size = MCLBYTES;
5972 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5973 }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){
5974 sc->fp[i].rx_buf_size = MJUMPAGESIZE;
5975 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE;
5977 sc->fp[i].rx_buf_size = MCLBYTES;
5978 sc->fp[i].mbuf_alloc_size = MCLBYTES;
5984 bxe_alloc_ilt_mem(struct bxe_softc *sc)
5989 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
5991 (M_NOWAIT | M_ZERO))) == NULL) {
5999 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
6003 if ((sc->ilt->lines =
6004 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
6006 (M_NOWAIT | M_ZERO))) == NULL) {
6014 bxe_free_ilt_mem(struct bxe_softc *sc)
6016 if (sc->ilt != NULL) {
6017 free(sc->ilt, M_BXE_ILT);
6023 bxe_free_ilt_lines_mem(struct bxe_softc *sc)
6025 if (sc->ilt->lines != NULL) {
6026 free(sc->ilt->lines, M_BXE_ILT);
6027 sc->ilt->lines = NULL;
6032 bxe_free_mem(struct bxe_softc *sc)
6036 for (i = 0; i < L2_ILT_LINES(sc); i++) {
6037 bxe_dma_free(sc, &sc->context[i].vcxt_dma);
6038 sc->context[i].vcxt = NULL;
6039 sc->context[i].size = 0;
6042 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6044 bxe_free_ilt_lines_mem(sc);
6049 bxe_alloc_mem(struct bxe_softc *sc)
6057 * Allocate memory for CDU context:
6058 * This memory is allocated separately and not in the generic ILT
6059 * functions because CDU differs in few aspects:
6060 * 1. There can be multiple entities allocating memory for context -
6061 * regular L2, CNIC, and SRIOV drivers. Each separately controls
6062 * its own ILT lines.
6063 * 2. Since CDU page-size is not a single 4KB page (which is the case
6064 * for the other ILT clients), to be efficient we want to support
6065 * allocation of sub-page-size in the last entry.
6066 * 3. Context pointers are used by the driver to pass to FW / update
6067 * the context (for the other ILT clients the pointers are used just to
6068 * free the memory during unload).
6070 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6071 for (i = 0, allocated = 0; allocated < context_size; i++) {
6072 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6073 (context_size - allocated));
6075 if (bxe_dma_alloc(sc, sc->context[i].size,
6076 &sc->context[i].vcxt_dma,
6077 "cdu context") != 0) {
6082 sc->context[i].vcxt =
6083 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6085 allocated += sc->context[i].size;
6088 bxe_alloc_ilt_lines_mem(sc);
6090 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6091 sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6093 for (i = 0; i < 4; i++) {
6095 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6097 sc->ilt->clients[i].page_size,
6098 sc->ilt->clients[i].start,
6099 sc->ilt->clients[i].end,
6100 sc->ilt->clients[i].client_num,
6101 sc->ilt->clients[i].flags);
6104 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6105 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6114 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6116 struct bxe_softc *sc;
6121 if (fp->rx_mbuf_tag == NULL) {
6125 /* free all mbufs and unload all maps */
6126 for (i = 0; i < RX_BD_TOTAL; i++) {
6127 if (fp->rx_mbuf_chain[i].m_map != NULL) {
6128 bus_dmamap_sync(fp->rx_mbuf_tag,
6129 fp->rx_mbuf_chain[i].m_map,
6130 BUS_DMASYNC_POSTREAD);
6131 bus_dmamap_unload(fp->rx_mbuf_tag,
6132 fp->rx_mbuf_chain[i].m_map);
6135 if (fp->rx_mbuf_chain[i].m != NULL) {
6136 m_freem(fp->rx_mbuf_chain[i].m);
6137 fp->rx_mbuf_chain[i].m = NULL;
6138 fp->eth_q_stats.mbuf_alloc_rx--;
6144 bxe_free_tpa_pool(struct bxe_fastpath *fp)
6146 struct bxe_softc *sc;
6147 int i, max_agg_queues;
6151 if (fp->rx_mbuf_tag == NULL) {
6155 max_agg_queues = MAX_AGG_QS(sc);
6157 /* release all mbufs and unload all DMA maps in the TPA pool */
6158 for (i = 0; i < max_agg_queues; i++) {
6159 if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6160 bus_dmamap_sync(fp->rx_mbuf_tag,
6161 fp->rx_tpa_info[i].bd.m_map,
6162 BUS_DMASYNC_POSTREAD);
6163 bus_dmamap_unload(fp->rx_mbuf_tag,
6164 fp->rx_tpa_info[i].bd.m_map);
6167 if (fp->rx_tpa_info[i].bd.m != NULL) {
6168 m_freem(fp->rx_tpa_info[i].bd.m);
6169 fp->rx_tpa_info[i].bd.m = NULL;
6170 fp->eth_q_stats.mbuf_alloc_tpa--;
6176 bxe_free_sge_chain(struct bxe_fastpath *fp)
6178 struct bxe_softc *sc;
6183 if (fp->rx_sge_mbuf_tag == NULL) {
6187 /* rree all mbufs and unload all maps */
6188 for (i = 0; i < RX_SGE_TOTAL; i++) {
6189 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6190 bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6191 fp->rx_sge_mbuf_chain[i].m_map,
6192 BUS_DMASYNC_POSTREAD);
6193 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6194 fp->rx_sge_mbuf_chain[i].m_map);
6197 if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6198 m_freem(fp->rx_sge_mbuf_chain[i].m);
6199 fp->rx_sge_mbuf_chain[i].m = NULL;
6200 fp->eth_q_stats.mbuf_alloc_sge--;
6206 bxe_free_fp_buffers(struct bxe_softc *sc)
6208 struct bxe_fastpath *fp;
6211 for (i = 0; i < sc->num_queues; i++) {
6214 #if __FreeBSD_version >= 901504
6215 if (fp->tx_br != NULL) {
6216 /* just in case bxe_mq_flush() wasn't called */
6217 if (mtx_initialized(&fp->tx_mtx)) {
6221 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL)
6223 BXE_FP_TX_UNLOCK(fp);
6228 /* free all RX buffers */
6229 bxe_free_rx_bd_chain(fp);
6230 bxe_free_tpa_pool(fp);
6231 bxe_free_sge_chain(fp);
6233 if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6234 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6235 fp->eth_q_stats.mbuf_alloc_rx);
6238 if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6239 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6240 fp->eth_q_stats.mbuf_alloc_sge);
6243 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6244 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6245 fp->eth_q_stats.mbuf_alloc_tpa);
6248 if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6249 BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6250 fp->eth_q_stats.mbuf_alloc_tx);
6253 /* XXX verify all mbufs were reclaimed */
6258 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6259 uint16_t prev_index,
6262 struct bxe_sw_rx_bd *rx_buf;
6263 struct eth_rx_bd *rx_bd;
6264 bus_dma_segment_t segs[1];
6271 /* allocate the new RX BD mbuf */
6272 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6273 if (__predict_false(m == NULL)) {
6274 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6278 fp->eth_q_stats.mbuf_alloc_rx++;
6280 /* initialize the mbuf buffer length */
6281 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6283 /* map the mbuf into non-paged pool */
6284 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6285 fp->rx_mbuf_spare_map,
6286 m, segs, &nsegs, BUS_DMA_NOWAIT);
6287 if (__predict_false(rc != 0)) {
6288 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6290 fp->eth_q_stats.mbuf_alloc_rx--;
6294 /* all mbufs must map to a single segment */
6295 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6297 /* release any existing RX BD mbuf mappings */
6299 if (prev_index != index) {
6300 rx_buf = &fp->rx_mbuf_chain[prev_index];
6302 if (rx_buf->m_map != NULL) {
6303 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6304 BUS_DMASYNC_POSTREAD);
6305 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6309 * We only get here from bxe_rxeof() when the maximum number
6310 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6311 * holds the mbuf in the prev_index so it's OK to NULL it out
6312 * here without concern of a memory leak.
6314 fp->rx_mbuf_chain[prev_index].m = NULL;
6317 rx_buf = &fp->rx_mbuf_chain[index];
6319 if (rx_buf->m_map != NULL) {
6320 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6321 BUS_DMASYNC_POSTREAD);
6322 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6325 /* save the mbuf and mapping info for a future packet */
6326 map = (prev_index != index) ?
6327 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6328 rx_buf->m_map = fp->rx_mbuf_spare_map;
6329 fp->rx_mbuf_spare_map = map;
6330 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6331 BUS_DMASYNC_PREREAD);
6334 rx_bd = &fp->rx_chain[index];
6335 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6336 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6342 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6345 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6346 bus_dma_segment_t segs[1];
6352 /* allocate the new TPA mbuf */
6353 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6354 if (__predict_false(m == NULL)) {
6355 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6359 fp->eth_q_stats.mbuf_alloc_tpa++;
6361 /* initialize the mbuf buffer length */
6362 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6364 /* map the mbuf into non-paged pool */
6365 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6366 fp->rx_tpa_info_mbuf_spare_map,
6367 m, segs, &nsegs, BUS_DMA_NOWAIT);
6368 if (__predict_false(rc != 0)) {
6369 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6371 fp->eth_q_stats.mbuf_alloc_tpa--;
6375 /* all mbufs must map to a single segment */
6376 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6378 /* release any existing TPA mbuf mapping */
6379 if (tpa_info->bd.m_map != NULL) {
6380 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6381 BUS_DMASYNC_POSTREAD);
6382 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6385 /* save the mbuf and mapping info for the TPA mbuf */
6386 map = tpa_info->bd.m_map;
6387 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6388 fp->rx_tpa_info_mbuf_spare_map = map;
6389 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6390 BUS_DMASYNC_PREREAD);
6392 tpa_info->seg = segs[0];
6398 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6399 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6403 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6406 struct bxe_sw_rx_bd *sge_buf;
6407 struct eth_rx_sge *sge;
6408 bus_dma_segment_t segs[1];
6414 /* allocate a new SGE mbuf */
6415 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6416 if (__predict_false(m == NULL)) {
6417 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6421 fp->eth_q_stats.mbuf_alloc_sge++;
6423 /* initialize the mbuf buffer length */
6424 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6426 /* map the SGE mbuf into non-paged pool */
6427 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6428 fp->rx_sge_mbuf_spare_map,
6429 m, segs, &nsegs, BUS_DMA_NOWAIT);
6430 if (__predict_false(rc != 0)) {
6431 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6433 fp->eth_q_stats.mbuf_alloc_sge--;
6437 /* all mbufs must map to a single segment */
6438 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6440 sge_buf = &fp->rx_sge_mbuf_chain[index];
6442 /* release any existing SGE mbuf mapping */
6443 if (sge_buf->m_map != NULL) {
6444 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6445 BUS_DMASYNC_POSTREAD);
6446 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6449 /* save the mbuf and mapping info for a future packet */
6450 map = sge_buf->m_map;
6451 sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6452 fp->rx_sge_mbuf_spare_map = map;
6453 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6454 BUS_DMASYNC_PREREAD);
6457 sge = &fp->rx_sge_chain[index];
6458 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6459 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6464 static __noinline int
6465 bxe_alloc_fp_buffers(struct bxe_softc *sc)
6467 struct bxe_fastpath *fp;
6469 int ring_prod, cqe_ring_prod;
6472 for (i = 0; i < sc->num_queues; i++) {
6475 ring_prod = cqe_ring_prod = 0;
6479 /* allocate buffers for the RX BDs in RX BD chain */
6480 for (j = 0; j < sc->max_rx_bufs; j++) {
6481 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6483 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6485 goto bxe_alloc_fp_buffers_error;
6488 ring_prod = RX_BD_NEXT(ring_prod);
6489 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6492 fp->rx_bd_prod = ring_prod;
6493 fp->rx_cq_prod = cqe_ring_prod;
6494 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6496 max_agg_queues = MAX_AGG_QS(sc);
6498 fp->tpa_enable = TRUE;
6500 /* fill the TPA pool */
6501 for (j = 0; j < max_agg_queues; j++) {
6502 rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6504 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6506 fp->tpa_enable = FALSE;
6507 goto bxe_alloc_fp_buffers_error;
6510 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6513 if (fp->tpa_enable) {
6514 /* fill the RX SGE chain */
6516 for (j = 0; j < RX_SGE_USABLE; j++) {
6517 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6519 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6521 fp->tpa_enable = FALSE;
6523 goto bxe_alloc_fp_buffers_error;
6526 ring_prod = RX_SGE_NEXT(ring_prod);
6529 fp->rx_sge_prod = ring_prod;
6535 bxe_alloc_fp_buffers_error:
6537 /* unwind what was already allocated */
6538 bxe_free_rx_bd_chain(fp);
6539 bxe_free_tpa_pool(fp);
6540 bxe_free_sge_chain(fp);
6546 bxe_free_fw_stats_mem(struct bxe_softc *sc)
6548 bxe_dma_free(sc, &sc->fw_stats_dma);
6550 sc->fw_stats_num = 0;
6552 sc->fw_stats_req_size = 0;
6553 sc->fw_stats_req = NULL;
6554 sc->fw_stats_req_mapping = 0;
6556 sc->fw_stats_data_size = 0;
6557 sc->fw_stats_data = NULL;
6558 sc->fw_stats_data_mapping = 0;
6562 bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6564 uint8_t num_queue_stats;
6567 /* number of queues for statistics is number of eth queues */
6568 num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6571 * Total number of FW statistics requests =
6572 * 1 for port stats + 1 for PF stats + num of queues
6574 sc->fw_stats_num = (2 + num_queue_stats);
6577 * Request is built from stats_query_header and an array of
6578 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6579 * rules. The real number or requests is configured in the
6580 * stats_query_header.
6583 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6584 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6586 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6587 sc->fw_stats_num, num_groups);
6589 sc->fw_stats_req_size =
6590 (sizeof(struct stats_query_header) +
6591 (num_groups * sizeof(struct stats_query_cmd_group)));
6594 * Data for statistics requests + stats_counter.
6595 * stats_counter holds per-STORM counters that are incremented when
6596 * STORM has finished with the current request. Memory for FCoE
6597 * offloaded statistics are counted anyway, even if they will not be sent.
6598 * VF stats are not accounted for here as the data of VF stats is stored
6599 * in memory allocated by the VF, not here.
6601 sc->fw_stats_data_size =
6602 (sizeof(struct stats_counter) +
6603 sizeof(struct per_port_stats) +
6604 sizeof(struct per_pf_stats) +
6605 /* sizeof(struct fcoe_statistics_params) + */
6606 (sizeof(struct per_queue_stats) * num_queue_stats));
6608 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6609 &sc->fw_stats_dma, "fw stats") != 0) {
6610 bxe_free_fw_stats_mem(sc);
6614 /* set up the shortcuts */
6617 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6618 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6621 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6622 sc->fw_stats_req_size);
6623 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6624 sc->fw_stats_req_size);
6626 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6627 (uintmax_t)sc->fw_stats_req_mapping);
6629 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6630 (uintmax_t)sc->fw_stats_data_mapping);
6637 * 0-7 - Engine0 load counter.
6638 * 8-15 - Engine1 load counter.
6639 * 16 - Engine0 RESET_IN_PROGRESS bit.
6640 * 17 - Engine1 RESET_IN_PROGRESS bit.
6641 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
6642 * function on the engine
6643 * 19 - Engine1 ONE_IS_LOADED.
6644 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
6645 * leader to complete (check for both RESET_IN_PROGRESS bits and not
6646 * for just the one belonging to its engine).
6648 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6649 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6650 #define BXE_PATH0_LOAD_CNT_SHIFT 0
6651 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6652 #define BXE_PATH1_LOAD_CNT_SHIFT 8
6653 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6654 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6655 #define BXE_GLOBAL_RESET_BIT 0x00040000
6657 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
6659 bxe_set_reset_global(struct bxe_softc *sc)
6662 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6663 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6664 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
6665 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6668 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
6670 bxe_clear_reset_global(struct bxe_softc *sc)
6673 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6674 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6675 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
6676 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6679 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
6681 bxe_reset_is_global(struct bxe_softc *sc)
6683 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6684 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
6685 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
6688 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
6690 bxe_set_reset_done(struct bxe_softc *sc)
6693 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6694 BXE_PATH0_RST_IN_PROG_BIT;
6696 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6698 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6701 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6703 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6706 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
6708 bxe_set_reset_in_progress(struct bxe_softc *sc)
6711 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
6712 BXE_PATH0_RST_IN_PROG_BIT;
6714 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6716 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6719 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6721 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6724 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
6726 bxe_reset_is_done(struct bxe_softc *sc,
6729 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6730 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
6731 BXE_PATH0_RST_IN_PROG_BIT;
6733 /* return false if bit is set */
6734 return (val & bit) ? FALSE : TRUE;
6737 /* get the load status for an engine, should be run under rtnl lock */
6739 bxe_get_load_status(struct bxe_softc *sc,
6742 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
6743 BXE_PATH0_LOAD_CNT_MASK;
6744 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
6745 BXE_PATH0_LOAD_CNT_SHIFT;
6746 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6748 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6750 val = ((val & mask) >> shift);
6752 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
6757 /* set pf load mark */
6758 /* XXX needs to be under rtnl lock */
6760 bxe_set_pf_load(struct bxe_softc *sc)
6764 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6765 BXE_PATH0_LOAD_CNT_MASK;
6766 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6767 BXE_PATH0_LOAD_CNT_SHIFT;
6769 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6771 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6772 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
6774 /* get the current counter value */
6775 val1 = ((val & mask) >> shift);
6777 /* set bit of this PF */
6778 val1 |= (1 << SC_ABS_FUNC(sc));
6780 /* clear the old value */
6783 /* set the new one */
6784 val |= ((val1 << shift) & mask);
6786 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6788 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6791 /* clear pf load mark */
6792 /* XXX needs to be under rtnl lock */
6794 bxe_clear_pf_load(struct bxe_softc *sc)
6797 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
6798 BXE_PATH0_LOAD_CNT_MASK;
6799 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
6800 BXE_PATH0_LOAD_CNT_SHIFT;
6802 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6803 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6804 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
6806 /* get the current counter value */
6807 val1 = (val & mask) >> shift;
6809 /* clear bit of that PF */
6810 val1 &= ~(1 << SC_ABS_FUNC(sc));
6812 /* clear the old value */
6815 /* set the new one */
6816 val |= ((val1 << shift) & mask);
6818 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
6819 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6823 /* send load requrest to mcp and analyze response */
6825 bxe_nic_load_request(struct bxe_softc *sc,
6826 uint32_t *load_code)
6830 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
6831 DRV_MSG_SEQ_NUMBER_MASK);
6833 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
6835 /* get the current FW pulse sequence */
6836 sc->fw_drv_pulse_wr_seq =
6837 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
6838 DRV_PULSE_SEQ_MASK);
6840 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
6841 sc->fw_drv_pulse_wr_seq);
6844 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
6845 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
6847 /* if the MCP fails to respond we must abort */
6848 if (!(*load_code)) {
6849 BLOGE(sc, "MCP response failure!\n");
6853 /* if MCP refused then must abort */
6854 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
6855 BLOGE(sc, "MCP refused load request\n");
6863 * Check whether another PF has already loaded FW to chip. In virtualized
6864 * environments a pf from anoth VM may have already initialized the device
6865 * including loading FW.
6868 bxe_nic_load_analyze_req(struct bxe_softc *sc,
6871 uint32_t my_fw, loaded_fw;
6873 /* is another pf loaded on this engine? */
6874 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
6875 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
6876 /* build my FW version dword */
6877 my_fw = (BCM_5710_FW_MAJOR_VERSION +
6878 (BCM_5710_FW_MINOR_VERSION << 8 ) +
6879 (BCM_5710_FW_REVISION_VERSION << 16) +
6880 (BCM_5710_FW_ENGINEERING_VERSION << 24));
6882 /* read loaded FW from chip */
6883 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
6884 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
6887 /* abort nic load if version mismatch */
6888 if (my_fw != loaded_fw) {
6889 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
6898 /* mark PMF if applicable */
6900 bxe_nic_load_pmf(struct bxe_softc *sc,
6903 uint32_t ncsi_oem_data_addr;
6905 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
6906 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
6907 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
6909 * Barrier here for ordering between the writing to sc->port.pmf here
6910 * and reading it from the periodic task.
6918 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
6921 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
6922 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
6923 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
6924 if (ncsi_oem_data_addr) {
6926 (ncsi_oem_data_addr +
6927 offsetof(struct glob_ncsi_oem_data, driver_version)),
6935 bxe_read_mf_cfg(struct bxe_softc *sc)
6937 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
6941 if (BXE_NOMCP(sc)) {
6942 return; /* what should be the default bvalue in this case */
6946 * The formula for computing the absolute function number is...
6947 * For 2 port configuration (4 functions per port):
6948 * abs_func = 2 * vn + SC_PORT + SC_PATH
6949 * For 4 port configuration (2 functions per port):
6950 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
6952 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
6953 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
6954 if (abs_func >= E1H_FUNC_MAX) {
6957 sc->devinfo.mf_info.mf_config[vn] =
6958 MFCFG_RD(sc, func_mf_config[abs_func].config);
6961 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
6962 FUNC_MF_CFG_FUNC_DISABLED) {
6963 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
6964 sc->flags |= BXE_MF_FUNC_DIS;
6966 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
6967 sc->flags &= ~BXE_MF_FUNC_DIS;
6971 /* acquire split MCP access lock register */
6972 static int bxe_acquire_alr(struct bxe_softc *sc)
6976 for (j = 0; j < 1000; j++) {
6978 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
6979 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
6980 if (val & (1L << 31))
6986 if (!(val & (1L << 31))) {
6987 BLOGE(sc, "Cannot acquire MCP access lock register\n");
6994 /* release split MCP access lock register */
6995 static void bxe_release_alr(struct bxe_softc *sc)
6997 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
7001 bxe_fan_failure(struct bxe_softc *sc)
7003 int port = SC_PORT(sc);
7004 uint32_t ext_phy_config;
7006 /* mark the failure */
7008 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
7010 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
7011 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
7012 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
7015 /* log the failure */
7016 BLOGW(sc, "Fan Failure has caused the driver to shutdown "
7017 "the card to prevent permanent damage. "
7018 "Please contact OEM Support for assistance\n");
7022 bxe_panic(sc, ("Schedule task to handle fan failure\n"));
7025 * Schedule device reset (unload)
7026 * This is due to some boards consuming sufficient power when driver is
7027 * up to overheat if fan fails.
7029 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
7030 schedule_delayed_work(&sc->sp_rtnl_task, 0);
7034 /* this function is called upon a link interrupt */
7036 bxe_link_attn(struct bxe_softc *sc)
7038 uint32_t pause_enabled = 0;
7039 struct host_port_stats *pstats;
7041 struct bxe_fastpath *fp;
7044 /* Make sure that we are synced with the current statistics */
7045 bxe_stats_handle(sc, STATS_EVENT_STOP);
7046 BLOGI(sc, "link_vars phy_flags : %x\n", sc->link_vars.phy_flags);
7047 elink_link_update(&sc->link_params, &sc->link_vars);
7049 if (sc->link_vars.link_up) {
7051 /* dropless flow control */
7052 if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7055 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7060 (BAR_USTRORM_INTMEM +
7061 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7065 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7066 pstats = BXE_SP(sc, port_stats);
7067 /* reset old mac stats */
7068 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7071 if (sc->state == BXE_STATE_OPEN) {
7072 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7075 /* Restart tx when the link comes back. */
7076 FOR_EACH_ETH_QUEUE(sc, i) {
7078 taskqueue_enqueue(fp->tq, &fp->tx_task);
7082 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7083 cmng_fns = bxe_get_cmng_fns_mode(sc);
7085 if (cmng_fns != CMNG_FNS_NONE) {
7086 bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7087 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7089 /* rate shaping and fairness are disabled */
7090 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7094 bxe_link_report_locked(sc);
7097 ; // XXX bxe_link_sync_notify(sc);
7102 bxe_attn_int_asserted(struct bxe_softc *sc,
7105 int port = SC_PORT(sc);
7106 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7107 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7108 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7109 NIG_REG_MASK_INTERRUPT_PORT0;
7111 uint32_t nig_mask = 0;
7116 if (sc->attn_state & asserted) {
7117 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7120 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7122 aeu_mask = REG_RD(sc, aeu_addr);
7124 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7125 aeu_mask, asserted);
7127 aeu_mask &= ~(asserted & 0x3ff);
7129 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7131 REG_WR(sc, aeu_addr, aeu_mask);
7133 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7135 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7136 sc->attn_state |= asserted;
7137 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7139 if (asserted & ATTN_HARD_WIRED_MASK) {
7140 if (asserted & ATTN_NIG_FOR_FUNC) {
7142 bxe_acquire_phy_lock(sc);
7143 /* save nig interrupt mask */
7144 nig_mask = REG_RD(sc, nig_int_mask_addr);
7146 /* If nig_mask is not set, no need to call the update function */
7148 REG_WR(sc, nig_int_mask_addr, 0);
7153 /* handle unicore attn? */
7156 if (asserted & ATTN_SW_TIMER_4_FUNC) {
7157 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7160 if (asserted & GPIO_2_FUNC) {
7161 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7164 if (asserted & GPIO_3_FUNC) {
7165 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7168 if (asserted & GPIO_4_FUNC) {
7169 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7173 if (asserted & ATTN_GENERAL_ATTN_1) {
7174 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7175 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7177 if (asserted & ATTN_GENERAL_ATTN_2) {
7178 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7179 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7181 if (asserted & ATTN_GENERAL_ATTN_3) {
7182 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7183 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7186 if (asserted & ATTN_GENERAL_ATTN_4) {
7187 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7188 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7190 if (asserted & ATTN_GENERAL_ATTN_5) {
7191 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7192 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7194 if (asserted & ATTN_GENERAL_ATTN_6) {
7195 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7196 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7201 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7202 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7204 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7207 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7209 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7210 REG_WR(sc, reg_addr, asserted);
7212 /* now set back the mask */
7213 if (asserted & ATTN_NIG_FOR_FUNC) {
7215 * Verify that IGU ack through BAR was written before restoring
7216 * NIG mask. This loop should exit after 2-3 iterations max.
7218 if (sc->devinfo.int_block != INT_BLOCK_HC) {
7222 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7223 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7224 (++cnt < MAX_IGU_ATTN_ACK_TO));
7227 BLOGE(sc, "Failed to verify IGU ack on time\n");
7233 REG_WR(sc, nig_int_mask_addr, nig_mask);
7235 bxe_release_phy_lock(sc);
7240 bxe_print_next_block(struct bxe_softc *sc,
7244 BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7248 bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7253 uint32_t cur_bit = 0;
7256 for (i = 0; sig; i++) {
7257 cur_bit = ((uint32_t)0x1 << i);
7258 if (sig & cur_bit) {
7260 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7262 bxe_print_next_block(sc, par_num++, "BRB");
7264 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7266 bxe_print_next_block(sc, par_num++, "PARSER");
7268 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7270 bxe_print_next_block(sc, par_num++, "TSDM");
7272 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7274 bxe_print_next_block(sc, par_num++, "SEARCHER");
7276 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7278 bxe_print_next_block(sc, par_num++, "TCM");
7280 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7282 bxe_print_next_block(sc, par_num++, "TSEMI");
7284 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7286 bxe_print_next_block(sc, par_num++, "XPB");
7299 bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7306 uint32_t cur_bit = 0;
7307 for (i = 0; sig; i++) {
7308 cur_bit = ((uint32_t)0x1 << i);
7309 if (sig & cur_bit) {
7311 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7313 bxe_print_next_block(sc, par_num++, "PBF");
7315 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7317 bxe_print_next_block(sc, par_num++, "QM");
7319 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7321 bxe_print_next_block(sc, par_num++, "TM");
7323 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7325 bxe_print_next_block(sc, par_num++, "XSDM");
7327 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7329 bxe_print_next_block(sc, par_num++, "XCM");
7331 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7333 bxe_print_next_block(sc, par_num++, "XSEMI");
7335 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7337 bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7339 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7341 bxe_print_next_block(sc, par_num++, "NIG");
7343 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7345 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7348 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7350 bxe_print_next_block(sc, par_num++, "DEBUG");
7352 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7354 bxe_print_next_block(sc, par_num++, "USDM");
7356 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7358 bxe_print_next_block(sc, par_num++, "UCM");
7360 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7362 bxe_print_next_block(sc, par_num++, "USEMI");
7364 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7366 bxe_print_next_block(sc, par_num++, "UPB");
7368 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7370 bxe_print_next_block(sc, par_num++, "CSDM");
7372 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7374 bxe_print_next_block(sc, par_num++, "CCM");
7387 bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7392 uint32_t cur_bit = 0;
7395 for (i = 0; sig; i++) {
7396 cur_bit = ((uint32_t)0x1 << i);
7397 if (sig & cur_bit) {
7399 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7401 bxe_print_next_block(sc, par_num++, "CSEMI");
7403 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7405 bxe_print_next_block(sc, par_num++, "PXP");
7407 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7409 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7411 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7413 bxe_print_next_block(sc, par_num++, "CFC");
7415 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7417 bxe_print_next_block(sc, par_num++, "CDU");
7419 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7421 bxe_print_next_block(sc, par_num++, "DMAE");
7423 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7425 bxe_print_next_block(sc, par_num++, "IGU");
7427 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7429 bxe_print_next_block(sc, par_num++, "MISC");
7442 bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7448 uint32_t cur_bit = 0;
7451 for (i = 0; sig; i++) {
7452 cur_bit = ((uint32_t)0x1 << i);
7453 if (sig & cur_bit) {
7455 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7457 bxe_print_next_block(sc, par_num++, "MCP ROM");
7460 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7462 bxe_print_next_block(sc, par_num++,
7466 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7468 bxe_print_next_block(sc, par_num++,
7472 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7474 bxe_print_next_block(sc, par_num++,
7489 bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7494 uint32_t cur_bit = 0;
7497 for (i = 0; sig; i++) {
7498 cur_bit = ((uint32_t)0x1 << i);
7499 if (sig & cur_bit) {
7501 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7503 bxe_print_next_block(sc, par_num++, "PGLUE_B");
7505 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7507 bxe_print_next_block(sc, par_num++, "ATC");
7520 bxe_parity_attn(struct bxe_softc *sc,
7527 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7528 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7529 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7530 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7531 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7532 BLOGE(sc, "Parity error: HW block parity attention:\n"
7533 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7534 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7535 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7536 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7537 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7538 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7541 BLOGI(sc, "Parity errors detected in blocks: ");
7544 bxe_check_blocks_with_parity0(sc, sig[0] &
7545 HW_PRTY_ASSERT_SET_0,
7548 bxe_check_blocks_with_parity1(sc, sig[1] &
7549 HW_PRTY_ASSERT_SET_1,
7550 par_num, global, print);
7552 bxe_check_blocks_with_parity2(sc, sig[2] &
7553 HW_PRTY_ASSERT_SET_2,
7556 bxe_check_blocks_with_parity3(sc, sig[3] &
7557 HW_PRTY_ASSERT_SET_3,
7558 par_num, global, print);
7560 bxe_check_blocks_with_parity4(sc, sig[4] &
7561 HW_PRTY_ASSERT_SET_4,
7574 bxe_chk_parity_attn(struct bxe_softc *sc,
7578 struct attn_route attn = { {0} };
7579 int port = SC_PORT(sc);
7581 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7582 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7583 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7584 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7587 * Since MCP attentions can't be disabled inside the block, we need to
7588 * read AEU registers to see whether they're currently disabled
7590 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
7591 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0)) &
7592 MISC_AEU_ENABLE_MCP_PRTY_BITS) |
7593 ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
7596 if (!CHIP_IS_E1x(sc))
7597 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7599 return (bxe_parity_attn(sc, global, print, attn.sig));
7603 bxe_attn_int_deasserted4(struct bxe_softc *sc,
7608 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7609 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7610 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7611 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7612 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7613 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7614 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7615 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7616 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7617 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7618 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7619 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7620 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7621 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7622 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7623 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7624 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7625 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7626 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7627 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7628 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7631 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7632 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7633 BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7634 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7635 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7636 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7637 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7638 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7639 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7640 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7641 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7642 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7643 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7644 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7645 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7648 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7649 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7650 BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7651 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7652 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7657 bxe_e1h_disable(struct bxe_softc *sc)
7659 int port = SC_PORT(sc);
7663 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7667 bxe_e1h_enable(struct bxe_softc *sc)
7669 int port = SC_PORT(sc);
7671 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7673 // XXX bxe_tx_enable(sc);
7677 * called due to MCP event (on pmf):
7678 * reread new bandwidth configuration
7680 * notify others function about the change
7683 bxe_config_mf_bw(struct bxe_softc *sc)
7685 if (sc->link_vars.link_up) {
7686 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
7687 // XXX bxe_link_sync_notify(sc);
7690 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7694 bxe_set_mf_bw(struct bxe_softc *sc)
7696 bxe_config_mf_bw(sc);
7697 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
7701 bxe_handle_eee_event(struct bxe_softc *sc)
7703 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
7704 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
7707 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
7710 bxe_drv_info_ether_stat(struct bxe_softc *sc)
7712 struct eth_stats_info *ether_stat =
7713 &sc->sp->drv_info_to_mcp.ether_stat;
7715 strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
7716 ETH_STAT_INFO_VERSION_LEN);
7718 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
7719 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
7720 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
7721 ether_stat->mac_local + MAC_PAD,
7724 ether_stat->mtu_size = sc->mtu;
7726 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
7727 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
7728 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
7731 // XXX ether_stat->feature_flags |= ???;
7733 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
7735 ether_stat->txq_size = sc->tx_ring_size;
7736 ether_stat->rxq_size = sc->rx_ring_size;
7740 bxe_handle_drv_info_req(struct bxe_softc *sc)
7742 enum drv_info_opcode op_code;
7743 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
7745 /* if drv_info version supported by MFW doesn't match - send NACK */
7746 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
7747 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7751 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
7752 DRV_INFO_CONTROL_OP_CODE_SHIFT);
7754 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
7757 case ETH_STATS_OPCODE:
7758 bxe_drv_info_ether_stat(sc);
7760 case FCOE_STATS_OPCODE:
7761 case ISCSI_STATS_OPCODE:
7763 /* if op code isn't supported - send NACK */
7764 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
7769 * If we got drv_info attn from MFW then these fields are defined in
7772 SHMEM2_WR(sc, drv_info_host_addr_lo,
7773 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7774 SHMEM2_WR(sc, drv_info_host_addr_hi,
7775 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
7777 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
7781 bxe_dcc_event(struct bxe_softc *sc,
7784 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
7786 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
7788 * This is the only place besides the function initialization
7789 * where the sc->flags can change so it is done without any
7792 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
7793 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
7794 sc->flags |= BXE_MF_FUNC_DIS;
7795 bxe_e1h_disable(sc);
7797 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
7798 sc->flags &= ~BXE_MF_FUNC_DIS;
7801 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
7804 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
7805 bxe_config_mf_bw(sc);
7806 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
7809 /* Report results to MCP */
7811 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
7813 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
7817 bxe_pmf_update(struct bxe_softc *sc)
7819 int port = SC_PORT(sc);
7823 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
7826 * We need the mb() to ensure the ordering between the writing to
7827 * sc->port.pmf here and reading it from the bxe_periodic_task().
7831 /* queue a periodic task */
7832 // XXX schedule task...
7834 // XXX bxe_dcbx_pmf_update(sc);
7836 /* enable nig attention */
7837 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
7838 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7839 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
7840 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
7841 } else if (!CHIP_IS_E1x(sc)) {
7842 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
7843 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
7846 bxe_stats_handle(sc, STATS_EVENT_PMF);
7850 bxe_mc_assert(struct bxe_softc *sc)
7854 uint32_t row0, row1, row2, row3;
7857 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
7859 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7861 /* print the asserts */
7862 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7864 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
7865 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
7866 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
7867 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
7869 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7870 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7871 i, row3, row2, row1, row0);
7879 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
7881 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7884 /* print the asserts */
7885 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7887 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
7888 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
7889 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
7890 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
7892 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7893 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7894 i, row3, row2, row1, row0);
7902 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
7904 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7907 /* print the asserts */
7908 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7910 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
7911 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
7912 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
7913 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
7915 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7916 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7917 i, row3, row2, row1, row0);
7925 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
7927 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
7930 /* print the asserts */
7931 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
7933 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
7934 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
7935 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
7936 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
7938 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
7939 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
7940 i, row3, row2, row1, row0);
7951 bxe_attn_int_deasserted3(struct bxe_softc *sc,
7954 int func = SC_FUNC(sc);
7957 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
7959 if (attn & BXE_PMF_LINK_ASSERT(sc)) {
7961 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7962 bxe_read_mf_cfg(sc);
7963 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
7964 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
7965 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
7967 if (val & DRV_STATUS_DCC_EVENT_MASK)
7968 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
7970 if (val & DRV_STATUS_SET_MF_BW)
7973 if (val & DRV_STATUS_DRV_INFO_REQ)
7974 bxe_handle_drv_info_req(sc);
7976 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
7979 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
7980 bxe_handle_eee_event(sc);
7982 if (sc->link_vars.periodic_flags &
7983 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
7984 /* sync with link */
7985 bxe_acquire_phy_lock(sc);
7986 sc->link_vars.periodic_flags &=
7987 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
7988 bxe_release_phy_lock(sc);
7990 ; // XXX bxe_link_sync_notify(sc);
7991 bxe_link_report(sc);
7995 * Always call it here: bxe_link_report() will
7996 * prevent the link indication duplication.
7998 bxe_link_status_update(sc);
8000 } else if (attn & BXE_MC_ASSERT_BITS) {
8002 BLOGE(sc, "MC assert!\n");
8004 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
8005 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
8006 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
8007 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
8008 bxe_panic(sc, ("MC assert!\n"));
8010 } else if (attn & BXE_MCP_ASSERT) {
8012 BLOGE(sc, "MCP assert!\n");
8013 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
8014 // XXX bxe_fw_dump(sc);
8017 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
8021 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
8022 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
8023 if (attn & BXE_GRC_TIMEOUT) {
8024 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8025 BLOGE(sc, "GRC time-out 0x%08x\n", val);
8027 if (attn & BXE_GRC_RSV) {
8028 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8029 BLOGE(sc, "GRC reserved 0x%08x\n", val);
8031 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8036 bxe_attn_int_deasserted2(struct bxe_softc *sc,
8039 int port = SC_PORT(sc);
8041 uint32_t val0, mask0, val1, mask1;
8044 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8045 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8046 BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8047 /* CFC error attention */
8049 BLOGE(sc, "FATAL error from CFC\n");
8053 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8054 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8055 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8056 /* RQ_USDMDP_FIFO_OVERFLOW */
8057 if (val & 0x18000) {
8058 BLOGE(sc, "FATAL error from PXP\n");
8061 if (!CHIP_IS_E1x(sc)) {
8062 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8063 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8067 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8068 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8070 if (attn & AEU_PXP2_HW_INT_BIT) {
8071 /* CQ47854 workaround do not panic on
8072 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8074 if (!CHIP_IS_E1x(sc)) {
8075 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8076 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8077 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8078 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8080 * If the olny PXP2_EOP_ERROR_BIT is set in
8081 * STS0 and STS1 - clear it
8083 * probably we lose additional attentions between
8084 * STS0 and STS_CLR0, in this case user will not
8085 * be notified about them
8087 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8089 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8091 /* print the register, since no one can restore it */
8092 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8095 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8098 if (val0 & PXP2_EOP_ERROR_BIT) {
8099 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8102 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8103 * set then clear attention from PXP2 block without panic
8105 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8106 ((val1 & mask1) == 0))
8107 attn &= ~AEU_PXP2_HW_INT_BIT;
8112 if (attn & HW_INTERRUT_ASSERT_SET_2) {
8113 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8114 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8116 val = REG_RD(sc, reg_offset);
8117 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8118 REG_WR(sc, reg_offset, val);
8120 BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8121 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8122 bxe_panic(sc, ("HW block attention set2\n"));
8127 bxe_attn_int_deasserted1(struct bxe_softc *sc,
8130 int port = SC_PORT(sc);
8134 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8135 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8136 BLOGE(sc, "DB hw attention 0x%08x\n", val);
8137 /* DORQ discard attention */
8139 BLOGE(sc, "FATAL error from DORQ\n");
8143 if (attn & HW_INTERRUT_ASSERT_SET_1) {
8144 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8145 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8147 val = REG_RD(sc, reg_offset);
8148 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8149 REG_WR(sc, reg_offset, val);
8151 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8152 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8153 bxe_panic(sc, ("HW block attention set1\n"));
8158 bxe_attn_int_deasserted0(struct bxe_softc *sc,
8161 int port = SC_PORT(sc);
8165 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8166 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8168 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8169 val = REG_RD(sc, reg_offset);
8170 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8171 REG_WR(sc, reg_offset, val);
8173 BLOGW(sc, "SPIO5 hw attention\n");
8175 /* Fan failure attention */
8176 elink_hw_reset_phy(&sc->link_params);
8177 bxe_fan_failure(sc);
8180 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8181 bxe_acquire_phy_lock(sc);
8182 elink_handle_module_detect_int(&sc->link_params);
8183 bxe_release_phy_lock(sc);
8186 if (attn & HW_INTERRUT_ASSERT_SET_0) {
8187 val = REG_RD(sc, reg_offset);
8188 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8189 REG_WR(sc, reg_offset, val);
8191 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8192 (attn & HW_INTERRUT_ASSERT_SET_0)));
8197 bxe_attn_int_deasserted(struct bxe_softc *sc,
8198 uint32_t deasserted)
8200 struct attn_route attn;
8201 struct attn_route *group_mask;
8202 int port = SC_PORT(sc);
8207 uint8_t global = FALSE;
8210 * Need to take HW lock because MCP or other port might also
8211 * try to handle this event.
8213 bxe_acquire_alr(sc);
8215 if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8217 * In case of parity errors don't handle attentions so that
8218 * other function would "see" parity errors.
8220 sc->recovery_state = BXE_RECOVERY_INIT;
8221 // XXX schedule a recovery task...
8222 /* disable HW interrupts */
8223 bxe_int_disable(sc);
8224 bxe_release_alr(sc);
8228 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8229 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8230 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8231 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8232 if (!CHIP_IS_E1x(sc)) {
8233 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8238 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8239 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8241 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8242 if (deasserted & (1 << index)) {
8243 group_mask = &sc->attn_group[index];
8246 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8247 group_mask->sig[0], group_mask->sig[1],
8248 group_mask->sig[2], group_mask->sig[3],
8249 group_mask->sig[4]);
8251 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8252 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8253 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8254 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8255 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8259 bxe_release_alr(sc);
8261 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8262 reg_addr = (HC_REG_COMMAND_REG + port*32 +
8263 COMMAND_REG_ATTN_BITS_CLR);
8265 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8270 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8271 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8272 REG_WR(sc, reg_addr, val);
8274 if (~sc->attn_state & deasserted) {
8275 BLOGE(sc, "IGU error\n");
8278 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8279 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8281 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8283 aeu_mask = REG_RD(sc, reg_addr);
8285 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8286 aeu_mask, deasserted);
8287 aeu_mask |= (deasserted & 0x3ff);
8288 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8290 REG_WR(sc, reg_addr, aeu_mask);
8291 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8293 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8294 sc->attn_state &= ~deasserted;
8295 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8299 bxe_attn_int(struct bxe_softc *sc)
8301 /* read local copy of bits */
8302 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8303 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8304 uint32_t attn_state = sc->attn_state;
8306 /* look for changed bits */
8307 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8308 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8311 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8312 attn_bits, attn_ack, asserted, deasserted);
8314 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8315 BLOGE(sc, "BAD attention state\n");
8318 /* handle bits that were raised */
8320 bxe_attn_int_asserted(sc, asserted);
8324 bxe_attn_int_deasserted(sc, deasserted);
8329 bxe_update_dsb_idx(struct bxe_softc *sc)
8331 struct host_sp_status_block *def_sb = sc->def_sb;
8334 mb(); /* status block is written to by the chip */
8336 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8337 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8338 rc |= BXE_DEF_SB_ATT_IDX;
8341 if (sc->def_idx != def_sb->sp_sb.running_index) {
8342 sc->def_idx = def_sb->sp_sb.running_index;
8343 rc |= BXE_DEF_SB_IDX;
8351 static inline struct ecore_queue_sp_obj *
8352 bxe_cid_to_q_obj(struct bxe_softc *sc,
8355 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8356 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8360 bxe_handle_mcast_eqe(struct bxe_softc *sc)
8362 struct ecore_mcast_ramrod_params rparam;
8365 memset(&rparam, 0, sizeof(rparam));
8367 rparam.mcast_obj = &sc->mcast_obj;
8371 /* clear pending state for the last command */
8372 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8374 /* if there are pending mcast commands - send them */
8375 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8376 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8379 "ERROR: Failed to send pending mcast commands (%d)\n", rc);
8383 BXE_MCAST_UNLOCK(sc);
8387 bxe_handle_classification_eqe(struct bxe_softc *sc,
8388 union event_ring_elem *elem)
8390 unsigned long ramrod_flags = 0;
8392 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8393 struct ecore_vlan_mac_obj *vlan_mac_obj;
8395 /* always push next commands out, don't wait here */
8396 bit_set(&ramrod_flags, RAMROD_CONT);
8398 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8399 case ECORE_FILTER_MAC_PENDING:
8400 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8401 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8404 case ECORE_FILTER_MCAST_PENDING:
8405 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8407 * This is only relevant for 57710 where multicast MACs are
8408 * configured as unicast MACs using the same ramrod.
8410 bxe_handle_mcast_eqe(sc);
8414 BLOGE(sc, "Unsupported classification command: %d\n",
8415 elem->message.data.eth_event.echo);
8419 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8422 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8423 } else if (rc > 0) {
8424 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8429 bxe_handle_rx_mode_eqe(struct bxe_softc *sc,
8430 union event_ring_elem *elem)
8432 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8434 /* send rx_mode command again if was requested */
8435 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8437 bxe_set_storm_rx_mode(sc);
8442 bxe_update_eq_prod(struct bxe_softc *sc,
8445 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8446 wmb(); /* keep prod updates ordered */
8450 bxe_eq_int(struct bxe_softc *sc)
8452 uint16_t hw_cons, sw_cons, sw_prod;
8453 union event_ring_elem *elem;
8458 struct ecore_queue_sp_obj *q_obj;
8459 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8460 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8462 hw_cons = le16toh(*sc->eq_cons_sb);
8465 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8466 * when we get to the next-page we need to adjust so the loop
8467 * condition below will be met. The next element is the size of a
8468 * regular element and hence incrementing by 1
8470 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8475 * This function may never run in parallel with itself for a
8476 * specific sc and no need for a read memory barrier here.
8478 sw_cons = sc->eq_cons;
8479 sw_prod = sc->eq_prod;
8481 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8482 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8486 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8488 elem = &sc->eq[EQ_DESC(sw_cons)];
8490 /* elem CID originates from FW, actually LE */
8491 cid = SW_CID(elem->message.data.cfc_del_event.cid);
8492 opcode = elem->message.opcode;
8494 /* handle eq element */
8497 case EVENT_RING_OPCODE_STAT_QUERY:
8498 BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8500 /* nothing to do with stats comp */
8503 case EVENT_RING_OPCODE_CFC_DEL:
8504 /* handle according to cid range */
8505 /* we may want to verify here that the sc state is HALTING */
8506 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8507 q_obj = bxe_cid_to_q_obj(sc, cid);
8508 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8513 case EVENT_RING_OPCODE_STOP_TRAFFIC:
8514 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8515 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8518 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8521 case EVENT_RING_OPCODE_START_TRAFFIC:
8522 BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8523 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8526 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8529 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8530 echo = elem->message.data.function_update_event.echo;
8531 if (echo == SWITCH_UPDATE) {
8532 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8533 if (f_obj->complete_cmd(sc, f_obj,
8534 ECORE_F_CMD_SWITCH_UPDATE)) {
8540 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8544 case EVENT_RING_OPCODE_FORWARD_SETUP:
8545 q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8546 if (q_obj->complete_cmd(sc, q_obj,
8547 ECORE_Q_CMD_SETUP_TX_ONLY)) {
8552 case EVENT_RING_OPCODE_FUNCTION_START:
8553 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8554 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8559 case EVENT_RING_OPCODE_FUNCTION_STOP:
8560 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8561 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8567 switch (opcode | sc->state) {
8568 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8569 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8570 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8571 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8572 rss_raw->clear_pending(rss_raw);
8575 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8576 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8577 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8578 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8579 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8580 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8581 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8582 bxe_handle_classification_eqe(sc, elem);
8585 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8586 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8587 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8588 BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8589 bxe_handle_mcast_eqe(sc);
8592 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8593 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8594 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8595 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8596 bxe_handle_rx_mode_eqe(sc, elem);
8600 /* unknown event log error and continue */
8601 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8602 elem->message.opcode, sc->state);
8610 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8612 sc->eq_cons = sw_cons;
8613 sc->eq_prod = sw_prod;
8615 /* make sure that above mem writes were issued towards the memory */
8618 /* update producer */
8619 bxe_update_eq_prod(sc, sc->eq_prod);
8623 bxe_handle_sp_tq(void *context,
8626 struct bxe_softc *sc = (struct bxe_softc *)context;
8629 BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
8631 /* what work needs to be performed? */
8632 status = bxe_update_dsb_idx(sc);
8634 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
8637 if (status & BXE_DEF_SB_ATT_IDX) {
8638 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
8640 status &= ~BXE_DEF_SB_ATT_IDX;
8643 /* SP events: STAT_QUERY and others */
8644 if (status & BXE_DEF_SB_IDX) {
8645 /* handle EQ completions */
8646 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
8648 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
8649 le16toh(sc->def_idx), IGU_INT_NOP, 1);
8650 status &= ~BXE_DEF_SB_IDX;
8653 /* if status is non zero then something went wrong */
8654 if (__predict_false(status)) {
8655 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
8658 /* ack status block only if something was actually handled */
8659 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
8660 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
8663 * Must be called after the EQ processing (since eq leads to sriov
8664 * ramrod completion flows).
8665 * This flow may have been scheduled by the arrival of a ramrod
8666 * completion, or by the sriov code rescheduling itself.
8668 // XXX bxe_iov_sp_task(sc);
8673 bxe_handle_fp_tq(void *context,
8676 struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
8677 struct bxe_softc *sc = fp->sc;
8678 uint8_t more_tx = FALSE;
8679 uint8_t more_rx = FALSE;
8681 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
8684 * IFF_DRV_RUNNING state can't be checked here since we process
8685 * slowpath events on a client queue during setup. Instead
8686 * we need to add a "process/continue" flag here that the driver
8687 * can use to tell the task here not to do anything.
8690 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
8695 /* update the fastpath index */
8696 bxe_update_fp_sb_idx(fp);
8698 /* XXX add loop here if ever support multiple tx CoS */
8699 /* fp->txdata[cos] */
8700 if (bxe_has_tx_work(fp)) {
8702 more_tx = bxe_txeof(sc, fp);
8703 BXE_FP_TX_UNLOCK(fp);
8706 if (bxe_has_rx_work(fp)) {
8707 more_rx = bxe_rxeof(sc, fp);
8710 if (more_rx /*|| more_tx*/) {
8711 /* still more work to do */
8712 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8716 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8717 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8721 bxe_task_fp(struct bxe_fastpath *fp)
8723 struct bxe_softc *sc = fp->sc;
8724 uint8_t more_tx = FALSE;
8725 uint8_t more_rx = FALSE;
8727 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
8729 /* update the fastpath index */
8730 bxe_update_fp_sb_idx(fp);
8732 /* XXX add loop here if ever support multiple tx CoS */
8733 /* fp->txdata[cos] */
8734 if (bxe_has_tx_work(fp)) {
8736 more_tx = bxe_txeof(sc, fp);
8737 BXE_FP_TX_UNLOCK(fp);
8740 if (bxe_has_rx_work(fp)) {
8741 more_rx = bxe_rxeof(sc, fp);
8744 if (more_rx /*|| more_tx*/) {
8745 /* still more work to do, bail out if this ISR and process later */
8746 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
8751 * Here we write the fastpath index taken before doing any tx or rx work.
8752 * It is very well possible other hw events occurred up to this point and
8753 * they were actually processed accordingly above. Since we're going to
8754 * write an older fastpath index, an interrupt is coming which we might
8755 * not do any work in.
8757 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
8758 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
8762 * Legacy interrupt entry point.
8764 * Verifies that the controller generated the interrupt and
8765 * then calls a separate routine to handle the various
8766 * interrupt causes: link, RX, and TX.
8769 bxe_intr_legacy(void *xsc)
8771 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8772 struct bxe_fastpath *fp;
8773 uint16_t status, mask;
8776 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
8779 * 0 for ustorm, 1 for cstorm
8780 * the bits returned from ack_int() are 0-15
8781 * bit 0 = attention status block
8782 * bit 1 = fast path status block
8783 * a mask of 0x2 or more = tx/rx event
8784 * a mask of 1 = slow path event
8787 status = bxe_ack_int(sc);
8789 /* the interrupt is not for us */
8790 if (__predict_false(status == 0)) {
8791 BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
8795 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
8797 FOR_EACH_ETH_QUEUE(sc, i) {
8799 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
8800 if (status & mask) {
8801 /* acknowledge and disable further fastpath interrupts */
8802 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8808 if (__predict_false(status & 0x1)) {
8809 /* acknowledge and disable further slowpath interrupts */
8810 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8812 /* schedule slowpath handler */
8813 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8818 if (__predict_false(status)) {
8819 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
8823 /* slowpath interrupt entry point */
8825 bxe_intr_sp(void *xsc)
8827 struct bxe_softc *sc = (struct bxe_softc *)xsc;
8829 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
8831 /* acknowledge and disable further slowpath interrupts */
8832 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8834 /* schedule slowpath handler */
8835 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
8838 /* fastpath interrupt entry point */
8840 bxe_intr_fp(void *xfp)
8842 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
8843 struct bxe_softc *sc = fp->sc;
8845 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
8848 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
8849 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
8851 /* acknowledge and disable further fastpath interrupts */
8852 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
8857 /* Release all interrupts allocated by the driver. */
8859 bxe_interrupt_free(struct bxe_softc *sc)
8863 switch (sc->interrupt_mode) {
8864 case INTR_MODE_INTX:
8865 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
8866 if (sc->intr[0].resource != NULL) {
8867 bus_release_resource(sc->dev,
8870 sc->intr[0].resource);
8874 for (i = 0; i < sc->intr_count; i++) {
8875 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
8876 if (sc->intr[i].resource && sc->intr[i].rid) {
8877 bus_release_resource(sc->dev,
8880 sc->intr[i].resource);
8883 pci_release_msi(sc->dev);
8885 case INTR_MODE_MSIX:
8886 for (i = 0; i < sc->intr_count; i++) {
8887 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
8888 if (sc->intr[i].resource && sc->intr[i].rid) {
8889 bus_release_resource(sc->dev,
8892 sc->intr[i].resource);
8895 pci_release_msi(sc->dev);
8898 /* nothing to do as initial allocation failed */
8904 * This function determines and allocates the appropriate
8905 * interrupt based on system capabilites and user request.
8907 * The user may force a particular interrupt mode, specify
8908 * the number of receive queues, specify the method for
8909 * distribuitng received frames to receive queues, or use
8910 * the default settings which will automatically select the
8911 * best supported combination. In addition, the OS may or
8912 * may not support certain combinations of these settings.
8913 * This routine attempts to reconcile the settings requested
8914 * by the user with the capabilites available from the system
8915 * to select the optimal combination of features.
8918 * 0 = Success, !0 = Failure.
8921 bxe_interrupt_alloc(struct bxe_softc *sc)
8925 int num_requested = 0;
8926 int num_allocated = 0;
8930 /* get the number of available MSI/MSI-X interrupts from the OS */
8931 if (sc->interrupt_mode > 0) {
8932 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
8933 msix_count = pci_msix_count(sc->dev);
8936 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
8937 msi_count = pci_msi_count(sc->dev);
8940 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
8941 msi_count, msix_count);
8944 do { /* try allocating MSI-X interrupt resources (at least 2) */
8945 if (sc->interrupt_mode != INTR_MODE_MSIX) {
8949 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
8951 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8955 /* ask for the necessary number of MSI-X vectors */
8956 num_requested = min((sc->num_queues + 1), msix_count);
8958 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
8960 num_allocated = num_requested;
8961 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
8962 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
8963 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8967 if (num_allocated < 2) { /* possible? */
8968 BLOGE(sc, "MSI-X allocation less than 2!\n");
8969 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
8970 pci_release_msi(sc->dev);
8974 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
8975 num_requested, num_allocated);
8977 /* best effort so use the number of vectors allocated to us */
8978 sc->intr_count = num_allocated;
8979 sc->num_queues = num_allocated - 1;
8981 rid = 1; /* initial resource identifier */
8983 /* allocate the MSI-X vectors */
8984 for (i = 0; i < num_allocated; i++) {
8985 sc->intr[i].rid = (rid + i);
8987 if ((sc->intr[i].resource =
8988 bus_alloc_resource_any(sc->dev,
8991 RF_ACTIVE)) == NULL) {
8992 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
8995 for (j = (i - 1); j >= 0; j--) {
8996 bus_release_resource(sc->dev,
8999 sc->intr[j].resource);
9004 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9005 pci_release_msi(sc->dev);
9009 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9013 do { /* try allocating MSI vector resources (at least 2) */
9014 if (sc->interrupt_mode != INTR_MODE_MSI) {
9018 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9020 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9024 /* ask for a single MSI vector */
9027 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9029 num_allocated = num_requested;
9030 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9031 BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9032 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9036 if (num_allocated != 1) { /* possible? */
9037 BLOGE(sc, "MSI allocation is not 1!\n");
9038 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9039 pci_release_msi(sc->dev);
9043 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9044 num_requested, num_allocated);
9046 /* best effort so use the number of vectors allocated to us */
9047 sc->intr_count = num_allocated;
9048 sc->num_queues = num_allocated;
9050 rid = 1; /* initial resource identifier */
9052 sc->intr[0].rid = rid;
9054 if ((sc->intr[0].resource =
9055 bus_alloc_resource_any(sc->dev,
9058 RF_ACTIVE)) == NULL) {
9059 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9062 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9063 pci_release_msi(sc->dev);
9067 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9070 do { /* try allocating INTx vector resources */
9071 if (sc->interrupt_mode != INTR_MODE_INTX) {
9075 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9077 /* only one vector for INTx */
9081 rid = 0; /* initial resource identifier */
9083 sc->intr[0].rid = rid;
9085 if ((sc->intr[0].resource =
9086 bus_alloc_resource_any(sc->dev,
9089 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9090 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9093 sc->interrupt_mode = -1; /* Failed! */
9097 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9100 if (sc->interrupt_mode == -1) {
9101 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9105 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9106 sc->interrupt_mode, sc->num_queues);
9114 bxe_interrupt_detach(struct bxe_softc *sc)
9116 struct bxe_fastpath *fp;
9119 /* release interrupt resources */
9120 for (i = 0; i < sc->intr_count; i++) {
9121 if (sc->intr[i].resource && sc->intr[i].tag) {
9122 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9123 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9127 for (i = 0; i < sc->num_queues; i++) {
9130 taskqueue_drain(fp->tq, &fp->tq_task);
9131 taskqueue_drain(fp->tq, &fp->tx_task);
9132 while (taskqueue_cancel_timeout(fp->tq, &fp->tx_timeout_task,
9134 taskqueue_drain_timeout(fp->tq, &fp->tx_timeout_task);
9135 taskqueue_free(fp->tq);
9142 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9143 taskqueue_free(sc->sp_tq);
9149 * Enables interrupts and attach to the ISR.
9151 * When using multiple MSI/MSI-X vectors the first vector
9152 * is used for slowpath operations while all remaining
9153 * vectors are used for fastpath operations. If only a
9154 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9155 * ISR must look for both slowpath and fastpath completions.
9158 bxe_interrupt_attach(struct bxe_softc *sc)
9160 struct bxe_fastpath *fp;
9164 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9165 "bxe%d_sp_tq", sc->unit);
9166 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9167 sc->sp_tq = taskqueue_create(sc->sp_tq_name, M_NOWAIT,
9168 taskqueue_thread_enqueue,
9170 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9171 "%s", sc->sp_tq_name);
9174 for (i = 0; i < sc->num_queues; i++) {
9176 snprintf(fp->tq_name, sizeof(fp->tq_name),
9177 "bxe%d_fp%d_tq", sc->unit, i);
9178 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9179 TASK_INIT(&fp->tx_task, 0, bxe_tx_mq_start_deferred, fp);
9180 fp->tq = taskqueue_create(fp->tq_name, M_NOWAIT,
9181 taskqueue_thread_enqueue,
9183 TIMEOUT_TASK_INIT(fp->tq, &fp->tx_timeout_task, 0,
9184 bxe_tx_mq_start_deferred, fp);
9185 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9189 /* setup interrupt handlers */
9190 if (sc->interrupt_mode == INTR_MODE_MSIX) {
9191 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9194 * Setup the interrupt handler. Note that we pass the driver instance
9195 * to the interrupt handler for the slowpath.
9197 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9198 (INTR_TYPE_NET | INTR_MPSAFE),
9199 NULL, bxe_intr_sp, sc,
9200 &sc->intr[0].tag)) != 0) {
9201 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9202 goto bxe_interrupt_attach_exit;
9205 bus_describe_intr(sc->dev, sc->intr[0].resource,
9206 sc->intr[0].tag, "sp");
9208 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9210 /* initialize the fastpath vectors (note the first was used for sp) */
9211 for (i = 0; i < sc->num_queues; i++) {
9213 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9216 * Setup the interrupt handler. Note that we pass the
9217 * fastpath context to the interrupt handler in this
9220 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9221 (INTR_TYPE_NET | INTR_MPSAFE),
9222 NULL, bxe_intr_fp, fp,
9223 &sc->intr[i + 1].tag)) != 0) {
9224 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9226 goto bxe_interrupt_attach_exit;
9229 bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9230 sc->intr[i + 1].tag, "fp%02d", i);
9232 /* bind the fastpath instance to a cpu */
9233 if (sc->num_queues > 1) {
9234 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9237 fp->state = BXE_FP_STATE_IRQ;
9239 } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9240 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9243 * Setup the interrupt handler. Note that we pass the
9244 * driver instance to the interrupt handler which
9245 * will handle both the slowpath and fastpath.
9247 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9248 (INTR_TYPE_NET | INTR_MPSAFE),
9249 NULL, bxe_intr_legacy, sc,
9250 &sc->intr[0].tag)) != 0) {
9251 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9252 goto bxe_interrupt_attach_exit;
9255 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9256 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9259 * Setup the interrupt handler. Note that we pass the
9260 * driver instance to the interrupt handler which
9261 * will handle both the slowpath and fastpath.
9263 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9264 (INTR_TYPE_NET | INTR_MPSAFE),
9265 NULL, bxe_intr_legacy, sc,
9266 &sc->intr[0].tag)) != 0) {
9267 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9268 goto bxe_interrupt_attach_exit;
9272 bxe_interrupt_attach_exit:
9277 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9278 static int bxe_init_hw_common(struct bxe_softc *sc);
9279 static int bxe_init_hw_port(struct bxe_softc *sc);
9280 static int bxe_init_hw_func(struct bxe_softc *sc);
9281 static void bxe_reset_common(struct bxe_softc *sc);
9282 static void bxe_reset_port(struct bxe_softc *sc);
9283 static void bxe_reset_func(struct bxe_softc *sc);
9284 static int bxe_gunzip_init(struct bxe_softc *sc);
9285 static void bxe_gunzip_end(struct bxe_softc *sc);
9286 static int bxe_init_firmware(struct bxe_softc *sc);
9287 static void bxe_release_firmware(struct bxe_softc *sc);
9290 ecore_func_sp_drv_ops bxe_func_sp_drv = {
9291 .init_hw_cmn_chip = bxe_init_hw_common_chip,
9292 .init_hw_cmn = bxe_init_hw_common,
9293 .init_hw_port = bxe_init_hw_port,
9294 .init_hw_func = bxe_init_hw_func,
9296 .reset_hw_cmn = bxe_reset_common,
9297 .reset_hw_port = bxe_reset_port,
9298 .reset_hw_func = bxe_reset_func,
9300 .gunzip_init = bxe_gunzip_init,
9301 .gunzip_end = bxe_gunzip_end,
9303 .init_fw = bxe_init_firmware,
9304 .release_fw = bxe_release_firmware,
9308 bxe_init_func_obj(struct bxe_softc *sc)
9312 ecore_init_func_obj(sc,
9314 BXE_SP(sc, func_rdata),
9315 BXE_SP_MAPPING(sc, func_rdata),
9316 BXE_SP(sc, func_afex_rdata),
9317 BXE_SP_MAPPING(sc, func_afex_rdata),
9322 bxe_init_hw(struct bxe_softc *sc,
9325 struct ecore_func_state_params func_params = { NULL };
9328 /* prepare the parameters for function state transitions */
9329 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9331 func_params.f_obj = &sc->func_obj;
9332 func_params.cmd = ECORE_F_CMD_HW_INIT;
9334 func_params.params.hw_init.load_phase = load_code;
9337 * Via a plethora of function pointers, we will eventually reach
9338 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9340 rc = ecore_func_state_change(sc, &func_params);
9346 bxe_fill(struct bxe_softc *sc,
9353 if (!(len % 4) && !(addr % 4)) {
9354 for (i = 0; i < len; i += 4) {
9355 REG_WR(sc, (addr + i), fill);
9358 for (i = 0; i < len; i++) {
9359 REG_WR8(sc, (addr + i), fill);
9364 /* writes FP SP data to FW - data_size in dwords */
9366 bxe_wr_fp_sb_data(struct bxe_softc *sc,
9368 uint32_t *sb_data_p,
9373 for (index = 0; index < data_size; index++) {
9375 (BAR_CSTRORM_INTMEM +
9376 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9377 (sizeof(uint32_t) * index)),
9378 *(sb_data_p + index));
9383 bxe_zero_fp_sb(struct bxe_softc *sc,
9386 struct hc_status_block_data_e2 sb_data_e2;
9387 struct hc_status_block_data_e1x sb_data_e1x;
9388 uint32_t *sb_data_p;
9389 uint32_t data_size = 0;
9391 if (!CHIP_IS_E1x(sc)) {
9392 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9393 sb_data_e2.common.state = SB_DISABLED;
9394 sb_data_e2.common.p_func.vf_valid = FALSE;
9395 sb_data_p = (uint32_t *)&sb_data_e2;
9396 data_size = (sizeof(struct hc_status_block_data_e2) /
9399 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9400 sb_data_e1x.common.state = SB_DISABLED;
9401 sb_data_e1x.common.p_func.vf_valid = FALSE;
9402 sb_data_p = (uint32_t *)&sb_data_e1x;
9403 data_size = (sizeof(struct hc_status_block_data_e1x) /
9407 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9409 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9410 0, CSTORM_STATUS_BLOCK_SIZE);
9411 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9412 0, CSTORM_SYNC_BLOCK_SIZE);
9416 bxe_wr_sp_sb_data(struct bxe_softc *sc,
9417 struct hc_sp_status_block_data *sp_sb_data)
9422 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9425 (BAR_CSTRORM_INTMEM +
9426 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9427 (i * sizeof(uint32_t))),
9428 *((uint32_t *)sp_sb_data + i));
9433 bxe_zero_sp_sb(struct bxe_softc *sc)
9435 struct hc_sp_status_block_data sp_sb_data;
9437 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9439 sp_sb_data.state = SB_DISABLED;
9440 sp_sb_data.p_func.vf_valid = FALSE;
9442 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9445 (BAR_CSTRORM_INTMEM +
9446 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9447 0, CSTORM_SP_STATUS_BLOCK_SIZE);
9449 (BAR_CSTRORM_INTMEM +
9450 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9451 0, CSTORM_SP_SYNC_BLOCK_SIZE);
9455 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9459 hc_sm->igu_sb_id = igu_sb_id;
9460 hc_sm->igu_seg_id = igu_seg_id;
9461 hc_sm->timer_value = 0xFF;
9462 hc_sm->time_to_expire = 0xFFFFFFFF;
9466 bxe_map_sb_state_machines(struct hc_index_data *index_data)
9468 /* zero out state machine indices */
9471 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9474 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9475 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9476 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9477 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9482 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9483 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9486 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9487 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9488 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9489 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9490 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9491 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9492 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9493 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9497 bxe_init_sb(struct bxe_softc *sc,
9504 struct hc_status_block_data_e2 sb_data_e2;
9505 struct hc_status_block_data_e1x sb_data_e1x;
9506 struct hc_status_block_sm *hc_sm_p;
9507 uint32_t *sb_data_p;
9511 if (CHIP_INT_MODE_IS_BC(sc)) {
9512 igu_seg_id = HC_SEG_ACCESS_NORM;
9514 igu_seg_id = IGU_SEG_ACCESS_NORM;
9517 bxe_zero_fp_sb(sc, fw_sb_id);
9519 if (!CHIP_IS_E1x(sc)) {
9520 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9521 sb_data_e2.common.state = SB_ENABLED;
9522 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9523 sb_data_e2.common.p_func.vf_id = vfid;
9524 sb_data_e2.common.p_func.vf_valid = vf_valid;
9525 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9526 sb_data_e2.common.same_igu_sb_1b = TRUE;
9527 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9528 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9529 hc_sm_p = sb_data_e2.common.state_machine;
9530 sb_data_p = (uint32_t *)&sb_data_e2;
9531 data_size = (sizeof(struct hc_status_block_data_e2) /
9533 bxe_map_sb_state_machines(sb_data_e2.index_data);
9535 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9536 sb_data_e1x.common.state = SB_ENABLED;
9537 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9538 sb_data_e1x.common.p_func.vf_id = 0xff;
9539 sb_data_e1x.common.p_func.vf_valid = FALSE;
9540 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9541 sb_data_e1x.common.same_igu_sb_1b = TRUE;
9542 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9543 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9544 hc_sm_p = sb_data_e1x.common.state_machine;
9545 sb_data_p = (uint32_t *)&sb_data_e1x;
9546 data_size = (sizeof(struct hc_status_block_data_e1x) /
9548 bxe_map_sb_state_machines(sb_data_e1x.index_data);
9551 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9552 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9554 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9556 /* write indices to HW - PCI guarantees endianity of regpairs */
9557 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9560 static inline uint8_t
9561 bxe_fp_qzone_id(struct bxe_fastpath *fp)
9563 if (CHIP_IS_E1x(fp->sc)) {
9564 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9570 static inline uint32_t
9571 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc,
9572 struct bxe_fastpath *fp)
9574 uint32_t offset = BAR_USTRORM_INTMEM;
9576 if (!CHIP_IS_E1x(sc)) {
9577 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9579 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9586 bxe_init_eth_fp(struct bxe_softc *sc,
9589 struct bxe_fastpath *fp = &sc->fp[idx];
9590 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
9591 unsigned long q_type = 0;
9597 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
9598 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
9600 fp->cl_id = (CHIP_IS_E1x(sc)) ?
9601 (SC_L_ID(sc) + idx) :
9602 /* want client ID same as IGU SB ID for non-E1 */
9604 fp->cl_qzone_id = bxe_fp_qzone_id(fp);
9606 /* setup sb indices */
9607 if (!CHIP_IS_E1x(sc)) {
9608 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
9609 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
9611 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
9612 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
9616 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
9618 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
9621 * XXX If multiple CoS is ever supported then each fastpath structure
9622 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
9624 for (cos = 0; cos < sc->max_cos; cos++) {
9627 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
9629 /* nothing more for a VF to do */
9634 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
9635 fp->fw_sb_id, fp->igu_sb_id);
9637 bxe_update_fp_sb_idx(fp);
9639 /* Configure Queue State object */
9640 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
9641 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
9643 ecore_init_queue_obj(sc,
9644 &sc->sp_objs[idx].q_obj,
9649 BXE_SP(sc, q_rdata),
9650 BXE_SP_MAPPING(sc, q_rdata),
9653 /* configure classification DBs */
9654 ecore_init_mac_obj(sc,
9655 &sc->sp_objs[idx].mac_obj,
9659 BXE_SP(sc, mac_rdata),
9660 BXE_SP_MAPPING(sc, mac_rdata),
9661 ECORE_FILTER_MAC_PENDING,
9663 ECORE_OBJ_TYPE_RX_TX,
9666 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
9667 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
9671 bxe_update_rx_prod(struct bxe_softc *sc,
9672 struct bxe_fastpath *fp,
9673 uint16_t rx_bd_prod,
9674 uint16_t rx_cq_prod,
9675 uint16_t rx_sge_prod)
9677 struct ustorm_eth_rx_producers rx_prods = { 0 };
9680 /* update producers */
9681 rx_prods.bd_prod = rx_bd_prod;
9682 rx_prods.cqe_prod = rx_cq_prod;
9683 rx_prods.sge_prod = rx_sge_prod;
9686 * Make sure that the BD and SGE data is updated before updating the
9687 * producers since FW might read the BD/SGE right after the producer
9689 * This is only applicable for weak-ordered memory model archs such
9690 * as IA-64. The following barrier is also mandatory since FW will
9691 * assumes BDs must have buffers.
9695 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
9697 (fp->ustorm_rx_prods_offset + (i * 4)),
9698 ((uint32_t *)&rx_prods)[i]);
9701 wmb(); /* keep prod updates ordered */
9704 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
9705 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
9709 bxe_init_rx_rings(struct bxe_softc *sc)
9711 struct bxe_fastpath *fp;
9714 for (i = 0; i < sc->num_queues; i++) {
9720 * Activate the BD ring...
9721 * Warning, this will generate an interrupt (to the TSTORM)
9722 * so this can only be done after the chip is initialized
9724 bxe_update_rx_prod(sc, fp,
9733 if (CHIP_IS_E1(sc)) {
9735 (BAR_USTRORM_INTMEM +
9736 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
9737 U64_LO(fp->rcq_dma.paddr));
9739 (BAR_USTRORM_INTMEM +
9740 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
9741 U64_HI(fp->rcq_dma.paddr));
9747 bxe_init_tx_ring_one(struct bxe_fastpath *fp)
9749 SET_FLAG(fp->tx_db.data.header.data, DOORBELL_HDR_T_DB_TYPE, 1);
9750 fp->tx_db.data.zero_fill1 = 0;
9751 fp->tx_db.data.prod = 0;
9753 fp->tx_pkt_prod = 0;
9754 fp->tx_pkt_cons = 0;
9757 fp->eth_q_stats.tx_pkts = 0;
9761 bxe_init_tx_rings(struct bxe_softc *sc)
9765 for (i = 0; i < sc->num_queues; i++) {
9766 bxe_init_tx_ring_one(&sc->fp[i]);
9771 bxe_init_def_sb(struct bxe_softc *sc)
9773 struct host_sp_status_block *def_sb = sc->def_sb;
9774 bus_addr_t mapping = sc->def_sb_dma.paddr;
9775 int igu_sp_sb_index;
9777 int port = SC_PORT(sc);
9778 int func = SC_FUNC(sc);
9779 int reg_offset, reg_offset_en5;
9782 struct hc_sp_status_block_data sp_sb_data;
9784 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9786 if (CHIP_INT_MODE_IS_BC(sc)) {
9787 igu_sp_sb_index = DEF_SB_IGU_ID;
9788 igu_seg_id = HC_SEG_ACCESS_DEF;
9790 igu_sp_sb_index = sc->igu_dsb_id;
9791 igu_seg_id = IGU_SEG_ACCESS_DEF;
9795 section = ((uint64_t)mapping +
9796 offsetof(struct host_sp_status_block, atten_status_block));
9797 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
9800 reg_offset = (port) ?
9801 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
9802 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
9803 reg_offset_en5 = (port) ?
9804 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
9805 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
9807 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
9808 /* take care of sig[0]..sig[4] */
9809 for (sindex = 0; sindex < 4; sindex++) {
9810 sc->attn_group[index].sig[sindex] =
9811 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
9814 if (!CHIP_IS_E1x(sc)) {
9816 * enable5 is separate from the rest of the registers,
9817 * and the address skip is 4 and not 16 between the
9820 sc->attn_group[index].sig[4] =
9821 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
9823 sc->attn_group[index].sig[4] = 0;
9827 if (sc->devinfo.int_block == INT_BLOCK_HC) {
9828 reg_offset = (port) ?
9829 HC_REG_ATTN_MSG1_ADDR_L :
9830 HC_REG_ATTN_MSG0_ADDR_L;
9831 REG_WR(sc, reg_offset, U64_LO(section));
9832 REG_WR(sc, (reg_offset + 4), U64_HI(section));
9833 } else if (!CHIP_IS_E1x(sc)) {
9834 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
9835 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
9838 section = ((uint64_t)mapping +
9839 offsetof(struct host_sp_status_block, sp_sb));
9843 /* PCI guarantees endianity of regpair */
9844 sp_sb_data.state = SB_ENABLED;
9845 sp_sb_data.host_sb_addr.lo = U64_LO(section);
9846 sp_sb_data.host_sb_addr.hi = U64_HI(section);
9847 sp_sb_data.igu_sb_id = igu_sp_sb_index;
9848 sp_sb_data.igu_seg_id = igu_seg_id;
9849 sp_sb_data.p_func.pf_id = func;
9850 sp_sb_data.p_func.vnic_id = SC_VN(sc);
9851 sp_sb_data.p_func.vf_id = 0xff;
9853 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9855 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
9859 bxe_init_sp_ring(struct bxe_softc *sc)
9861 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
9862 sc->spq_prod_idx = 0;
9863 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
9864 sc->spq_prod_bd = sc->spq;
9865 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
9869 bxe_init_eq_ring(struct bxe_softc *sc)
9871 union event_ring_elem *elem;
9874 for (i = 1; i <= NUM_EQ_PAGES; i++) {
9875 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
9877 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
9879 (i % NUM_EQ_PAGES)));
9880 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
9882 (i % NUM_EQ_PAGES)));
9886 sc->eq_prod = NUM_EQ_DESC;
9887 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
9889 atomic_store_rel_long(&sc->eq_spq_left,
9890 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
9895 bxe_init_internal_common(struct bxe_softc *sc)
9900 * Zero this manually as its initialization is currently missing
9903 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
9905 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
9909 if (!CHIP_IS_E1x(sc)) {
9910 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
9911 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
9916 bxe_init_internal(struct bxe_softc *sc,
9919 switch (load_code) {
9920 case FW_MSG_CODE_DRV_LOAD_COMMON:
9921 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
9922 bxe_init_internal_common(sc);
9925 case FW_MSG_CODE_DRV_LOAD_PORT:
9929 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
9930 /* internal memory per function is initialized inside bxe_pf_init */
9934 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
9940 storm_memset_func_cfg(struct bxe_softc *sc,
9941 struct tstorm_eth_function_common_config *tcfg,
9947 addr = (BAR_TSTRORM_INTMEM +
9948 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
9949 size = sizeof(struct tstorm_eth_function_common_config);
9950 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
9954 bxe_func_init(struct bxe_softc *sc,
9955 struct bxe_func_init_params *p)
9957 struct tstorm_eth_function_common_config tcfg = { 0 };
9959 if (CHIP_IS_E1x(sc)) {
9960 storm_memset_func_cfg(sc, &tcfg, p->func_id);
9963 /* Enable the function in the FW */
9964 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
9965 storm_memset_func_en(sc, p->func_id, 1);
9968 if (p->func_flgs & FUNC_FLG_SPQ) {
9969 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
9971 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
9977 * Calculates the sum of vn_min_rates.
9978 * It's needed for further normalizing of the min_rates.
9980 * sum of vn_min_rates.
9982 * 0 - if all the min_rates are 0.
9983 * In the later case fainess algorithm should be deactivated.
9984 * If all min rates are not zero then those that are zeroes will be set to 1.
9987 bxe_calc_vn_min(struct bxe_softc *sc,
9988 struct cmng_init_input *input)
9991 uint32_t vn_min_rate;
9995 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
9996 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
9997 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
9998 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10000 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10001 /* skip hidden VNs */
10003 } else if (!vn_min_rate) {
10004 /* If min rate is zero - set it to 100 */
10005 vn_min_rate = DEF_MIN_RATE;
10010 input->vnic_min_rate[vn] = vn_min_rate;
10013 /* if ETS or all min rates are zeros - disable fairness */
10014 if (BXE_IS_ETS_ENABLED(sc)) {
10015 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10016 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10017 } else if (all_zero) {
10018 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10019 BLOGD(sc, DBG_LOAD,
10020 "Fariness disabled (all MIN values are zeroes)\n");
10022 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10026 static inline uint16_t
10027 bxe_extract_max_cfg(struct bxe_softc *sc,
10030 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10031 FUNC_MF_CFG_MAX_BW_SHIFT);
10034 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10042 bxe_calc_vn_max(struct bxe_softc *sc,
10044 struct cmng_init_input *input)
10046 uint16_t vn_max_rate;
10047 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10050 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10053 max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10055 if (IS_MF_SI(sc)) {
10056 /* max_cfg in percents of linkspeed */
10057 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10058 } else { /* SD modes */
10059 /* max_cfg is absolute in 100Mb units */
10060 vn_max_rate = (max_cfg * 100);
10064 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10066 input->vnic_max_rate[vn] = vn_max_rate;
10070 bxe_cmng_fns_init(struct bxe_softc *sc,
10074 struct cmng_init_input input;
10077 memset(&input, 0, sizeof(struct cmng_init_input));
10079 input.port_rate = sc->link_vars.line_speed;
10081 if (cmng_type == CMNG_FNS_MINMAX) {
10082 /* read mf conf from shmem */
10084 bxe_read_mf_cfg(sc);
10087 /* get VN min rate and enable fairness if not 0 */
10088 bxe_calc_vn_min(sc, &input);
10090 /* get VN max rate */
10091 if (sc->port.pmf) {
10092 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10093 bxe_calc_vn_max(sc, vn, &input);
10097 /* always enable rate shaping and fairness */
10098 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10100 ecore_init_cmng(&input, &sc->cmng);
10104 /* rate shaping and fairness are disabled */
10105 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10109 bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10111 if (CHIP_REV_IS_SLOW(sc)) {
10112 return (CMNG_FNS_NONE);
10116 return (CMNG_FNS_MINMAX);
10119 return (CMNG_FNS_NONE);
10123 storm_memset_cmng(struct bxe_softc *sc,
10124 struct cmng_init *cmng,
10132 addr = (BAR_XSTRORM_INTMEM +
10133 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10134 size = sizeof(struct cmng_struct_per_port);
10135 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10137 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10138 func = func_by_vn(sc, vn);
10140 addr = (BAR_XSTRORM_INTMEM +
10141 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10142 size = sizeof(struct rate_shaping_vars_per_vn);
10143 ecore_storm_memset_struct(sc, addr, size,
10144 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10146 addr = (BAR_XSTRORM_INTMEM +
10147 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10148 size = sizeof(struct fairness_vars_per_vn);
10149 ecore_storm_memset_struct(sc, addr, size,
10150 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10155 bxe_pf_init(struct bxe_softc *sc)
10157 struct bxe_func_init_params func_init = { 0 };
10158 struct event_ring_data eq_data = { { 0 } };
10161 if (!CHIP_IS_E1x(sc)) {
10162 /* reset IGU PF statistics: MSIX + ATTN */
10165 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10166 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10167 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10171 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10172 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10173 (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10174 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10178 /* function setup flags */
10179 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10182 * This flag is relevant for E1x only.
10183 * E2 doesn't have a TPA configuration in a function level.
10185 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10187 func_init.func_flgs = flags;
10188 func_init.pf_id = SC_FUNC(sc);
10189 func_init.func_id = SC_FUNC(sc);
10190 func_init.spq_map = sc->spq_dma.paddr;
10191 func_init.spq_prod = sc->spq_prod_idx;
10193 bxe_func_init(sc, &func_init);
10195 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10198 * Congestion management values depend on the link rate.
10199 * There is no active link so initial link rate is set to 10Gbps.
10200 * When the link comes up the congestion management values are
10201 * re-calculated according to the actual link rate.
10203 sc->link_vars.line_speed = SPEED_10000;
10204 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10206 /* Only the PMF sets the HW */
10207 if (sc->port.pmf) {
10208 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10211 /* init Event Queue - PCI bus guarantees correct endainity */
10212 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10213 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10214 eq_data.producer = sc->eq_prod;
10215 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
10216 eq_data.sb_id = DEF_SB_ID;
10217 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10221 bxe_hc_int_enable(struct bxe_softc *sc)
10223 int port = SC_PORT(sc);
10224 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10225 uint32_t val = REG_RD(sc, addr);
10226 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10227 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10228 (sc->intr_count == 1)) ? TRUE : FALSE;
10229 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10232 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10233 HC_CONFIG_0_REG_INT_LINE_EN_0);
10234 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10235 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10237 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10240 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10241 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10243 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10245 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10246 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10247 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10248 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10250 if (!CHIP_IS_E1(sc)) {
10251 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10254 REG_WR(sc, addr, val);
10256 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10260 if (CHIP_IS_E1(sc)) {
10261 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10264 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10265 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10267 REG_WR(sc, addr, val);
10269 /* ensure that HC_CONFIG is written before leading/trailing edge config */
10272 if (!CHIP_IS_E1(sc)) {
10273 /* init leading/trailing edge */
10275 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10276 if (sc->port.pmf) {
10277 /* enable nig and gpio3 attention */
10284 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10285 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10288 /* make sure that interrupts are indeed enabled from here on */
10293 bxe_igu_int_enable(struct bxe_softc *sc)
10296 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10297 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10298 (sc->intr_count == 1)) ? TRUE : FALSE;
10299 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10301 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10304 val &= ~(IGU_PF_CONF_INT_LINE_EN |
10305 IGU_PF_CONF_SINGLE_ISR_EN);
10306 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10307 IGU_PF_CONF_ATTN_BIT_EN);
10309 val |= IGU_PF_CONF_SINGLE_ISR_EN;
10312 val &= ~IGU_PF_CONF_INT_LINE_EN;
10313 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10314 IGU_PF_CONF_ATTN_BIT_EN |
10315 IGU_PF_CONF_SINGLE_ISR_EN);
10317 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10318 val |= (IGU_PF_CONF_INT_LINE_EN |
10319 IGU_PF_CONF_ATTN_BIT_EN |
10320 IGU_PF_CONF_SINGLE_ISR_EN);
10323 /* clean previous status - need to configure igu prior to ack*/
10324 if ((!msix) || single_msix) {
10325 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10329 val |= IGU_PF_CONF_FUNC_EN;
10331 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10332 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10334 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10338 /* init leading/trailing edge */
10340 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10341 if (sc->port.pmf) {
10342 /* enable nig and gpio3 attention */
10349 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10350 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10352 /* make sure that interrupts are indeed enabled from here on */
10357 bxe_int_enable(struct bxe_softc *sc)
10359 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10360 bxe_hc_int_enable(sc);
10362 bxe_igu_int_enable(sc);
10367 bxe_hc_int_disable(struct bxe_softc *sc)
10369 int port = SC_PORT(sc);
10370 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10371 uint32_t val = REG_RD(sc, addr);
10374 * In E1 we must use only PCI configuration space to disable MSI/MSIX
10375 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10378 if (CHIP_IS_E1(sc)) {
10380 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10381 * to prevent from HC sending interrupts after we exit the function
10383 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10385 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10386 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10387 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10389 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10390 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10391 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10392 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10395 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10397 /* flush all outstanding writes */
10400 REG_WR(sc, addr, val);
10401 if (REG_RD(sc, addr) != val) {
10402 BLOGE(sc, "proper val not read from HC IGU!\n");
10407 bxe_igu_int_disable(struct bxe_softc *sc)
10409 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10411 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10412 IGU_PF_CONF_INT_LINE_EN |
10413 IGU_PF_CONF_ATTN_BIT_EN);
10415 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10417 /* flush all outstanding writes */
10420 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10421 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10422 BLOGE(sc, "proper val not read from IGU!\n");
10427 bxe_int_disable(struct bxe_softc *sc)
10429 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10430 bxe_hc_int_disable(sc);
10432 bxe_igu_int_disable(sc);
10437 bxe_nic_init(struct bxe_softc *sc,
10442 for (i = 0; i < sc->num_queues; i++) {
10443 bxe_init_eth_fp(sc, i);
10446 rmb(); /* ensure status block indices were read */
10448 bxe_init_rx_rings(sc);
10449 bxe_init_tx_rings(sc);
10455 /* initialize MOD_ABS interrupts */
10456 elink_init_mod_abs_int(sc, &sc->link_vars,
10457 sc->devinfo.chip_id,
10458 sc->devinfo.shmem_base,
10459 sc->devinfo.shmem2_base,
10462 bxe_init_def_sb(sc);
10463 bxe_update_dsb_idx(sc);
10464 bxe_init_sp_ring(sc);
10465 bxe_init_eq_ring(sc);
10466 bxe_init_internal(sc, load_code);
10468 bxe_stats_init(sc);
10470 /* flush all before enabling interrupts */
10473 bxe_int_enable(sc);
10475 /* check for SPIO5 */
10476 bxe_attn_int_deasserted0(sc,
10478 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10480 AEU_INPUTS_ATTN_BITS_SPIO5);
10484 bxe_init_objs(struct bxe_softc *sc)
10486 /* mcast rules must be added to tx if tx switching is enabled */
10487 ecore_obj_type o_type =
10488 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10491 /* RX_MODE controlling object */
10492 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10494 /* multicast configuration controlling object */
10495 ecore_init_mcast_obj(sc,
10501 BXE_SP(sc, mcast_rdata),
10502 BXE_SP_MAPPING(sc, mcast_rdata),
10503 ECORE_FILTER_MCAST_PENDING,
10507 /* Setup CAM credit pools */
10508 ecore_init_mac_credit_pool(sc,
10511 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10512 VNICS_PER_PATH(sc));
10514 ecore_init_vlan_credit_pool(sc,
10516 SC_ABS_FUNC(sc) >> 1,
10517 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10518 VNICS_PER_PATH(sc));
10520 /* RSS configuration object */
10521 ecore_init_rss_config_obj(sc,
10527 BXE_SP(sc, rss_rdata),
10528 BXE_SP_MAPPING(sc, rss_rdata),
10529 ECORE_FILTER_RSS_CONF_PENDING,
10530 &sc->sp_state, ECORE_OBJ_TYPE_RX);
10534 * Initialize the function. This must be called before sending CLIENT_SETUP
10535 * for the first client.
10538 bxe_func_start(struct bxe_softc *sc)
10540 struct ecore_func_state_params func_params = { NULL };
10541 struct ecore_func_start_params *start_params = &func_params.params.start;
10543 /* Prepare parameters for function state transitions */
10544 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10546 func_params.f_obj = &sc->func_obj;
10547 func_params.cmd = ECORE_F_CMD_START;
10549 /* Function parameters */
10550 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
10551 start_params->sd_vlan_tag = OVLAN(sc);
10553 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
10554 start_params->network_cos_mode = STATIC_COS;
10555 } else { /* CHIP_IS_E1X */
10556 start_params->network_cos_mode = FW_WRR;
10559 //start_params->gre_tunnel_mode = 0;
10560 //start_params->gre_tunnel_rss = 0;
10562 return (ecore_func_state_change(sc, &func_params));
10566 bxe_set_power_state(struct bxe_softc *sc,
10571 /* If there is no power capability, silently succeed */
10572 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
10573 BLOGW(sc, "No power capability\n");
10577 pmcsr = pci_read_config(sc->dev,
10578 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10583 pci_write_config(sc->dev,
10584 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10585 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
10587 if (pmcsr & PCIM_PSTAT_DMASK) {
10588 /* delay required during transition out of D3hot */
10595 /* XXX if there are other clients above don't shut down the power */
10597 /* don't shut down the power for emulation and FPGA */
10598 if (CHIP_REV_IS_SLOW(sc)) {
10602 pmcsr &= ~PCIM_PSTAT_DMASK;
10603 pmcsr |= PCIM_PSTAT_D3;
10606 pmcsr |= PCIM_PSTAT_PMEENABLE;
10609 pci_write_config(sc->dev,
10610 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
10614 * No more memory access after this point until device is brought back
10620 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n",
10629 /* return true if succeeded to acquire the lock */
10631 bxe_trylock_hw_lock(struct bxe_softc *sc,
10634 uint32_t lock_status;
10635 uint32_t resource_bit = (1 << resource);
10636 int func = SC_FUNC(sc);
10637 uint32_t hw_lock_control_reg;
10639 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
10641 /* Validating that the resource is within range */
10642 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
10643 BLOGD(sc, DBG_LOAD,
10644 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
10645 resource, HW_LOCK_MAX_RESOURCE_VALUE);
10650 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
10652 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
10655 /* try to acquire the lock */
10656 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
10657 lock_status = REG_RD(sc, hw_lock_control_reg);
10658 if (lock_status & resource_bit) {
10662 BLOGE(sc, "Failed to get a resource lock 0x%x func %d "
10663 "lock_status 0x%x resource_bit 0x%x\n", resource, func,
10664 lock_status, resource_bit);
10670 * Get the recovery leader resource id according to the engine this function
10671 * belongs to. Currently only only 2 engines is supported.
10674 bxe_get_leader_lock_resource(struct bxe_softc *sc)
10677 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
10679 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
10683 /* try to acquire a leader lock for current engine */
10685 bxe_trylock_leader_lock(struct bxe_softc *sc)
10687 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10691 bxe_release_leader_lock(struct bxe_softc *sc)
10693 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
10696 /* close gates #2, #3 and #4 */
10698 bxe_set_234_gates(struct bxe_softc *sc,
10703 /* gates #2 and #4a are closed/opened for "not E1" only */
10704 if (!CHIP_IS_E1(sc)) {
10706 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
10708 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
10712 if (CHIP_IS_E1x(sc)) {
10713 /* prevent interrupts from HC on both ports */
10714 val = REG_RD(sc, HC_REG_CONFIG_1);
10715 REG_WR(sc, HC_REG_CONFIG_1,
10716 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
10717 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
10719 val = REG_RD(sc, HC_REG_CONFIG_0);
10720 REG_WR(sc, HC_REG_CONFIG_0,
10721 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
10722 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
10724 /* Prevent incomming interrupts in IGU */
10725 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
10727 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
10729 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
10730 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
10733 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
10734 close ? "closing" : "opening");
10739 /* poll for pending writes bit, it should get cleared in no more than 1s */
10741 bxe_er_poll_igu_vq(struct bxe_softc *sc)
10743 uint32_t cnt = 1000;
10744 uint32_t pend_bits = 0;
10747 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
10749 if (pend_bits == 0) {
10754 } while (--cnt > 0);
10757 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
10764 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
10767 bxe_clp_reset_prep(struct bxe_softc *sc,
10768 uint32_t *magic_val)
10770 /* Do some magic... */
10771 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10772 *magic_val = val & SHARED_MF_CLP_MAGIC;
10773 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
10776 /* restore the value of the 'magic' bit */
10778 bxe_clp_reset_done(struct bxe_softc *sc,
10779 uint32_t magic_val)
10781 /* Restore the 'magic' bit value... */
10782 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
10783 MFCFG_WR(sc, shared_mf_config.clp_mb,
10784 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
10787 /* prepare for MCP reset, takes care of CLP configurations */
10789 bxe_reset_mcp_prep(struct bxe_softc *sc,
10790 uint32_t *magic_val)
10793 uint32_t validity_offset;
10795 /* set `magic' bit in order to save MF config */
10796 if (!CHIP_IS_E1(sc)) {
10797 bxe_clp_reset_prep(sc, magic_val);
10800 /* get shmem offset */
10801 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10803 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
10805 /* Clear validity map flags */
10807 REG_WR(sc, shmem + validity_offset, 0);
10811 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
10812 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
10815 bxe_mcp_wait_one(struct bxe_softc *sc)
10817 /* special handling for emulation and FPGA (10 times longer) */
10818 if (CHIP_REV_IS_SLOW(sc)) {
10819 DELAY((MCP_ONE_TIMEOUT*10) * 1000);
10821 DELAY((MCP_ONE_TIMEOUT) * 1000);
10825 /* initialize shmem_base and waits for validity signature to appear */
10827 bxe_init_shmem(struct bxe_softc *sc)
10833 sc->devinfo.shmem_base =
10834 sc->link_params.shmem_base =
10835 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
10837 if (sc->devinfo.shmem_base) {
10838 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
10839 if (val & SHR_MEM_VALIDITY_MB)
10843 bxe_mcp_wait_one(sc);
10845 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
10847 BLOGE(sc, "BAD MCP validity signature\n");
10853 bxe_reset_mcp_comp(struct bxe_softc *sc,
10854 uint32_t magic_val)
10856 int rc = bxe_init_shmem(sc);
10858 /* Restore the `magic' bit value */
10859 if (!CHIP_IS_E1(sc)) {
10860 bxe_clp_reset_done(sc, magic_val);
10867 bxe_pxp_prep(struct bxe_softc *sc)
10869 if (!CHIP_IS_E1(sc)) {
10870 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
10871 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
10877 * Reset the whole chip except for:
10879 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
10881 * - MISC (including AEU)
10886 bxe_process_kill_chip_reset(struct bxe_softc *sc,
10889 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
10890 uint32_t global_bits2, stay_reset2;
10893 * Bits that have to be set in reset_mask2 if we want to reset 'global'
10894 * (per chip) blocks.
10897 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
10898 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
10901 * Don't reset the following blocks.
10902 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
10903 * reset, as in 4 port device they might still be owned
10904 * by the MCP (there is only one leader per path).
10907 MISC_REGISTERS_RESET_REG_1_RST_HC |
10908 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
10909 MISC_REGISTERS_RESET_REG_1_RST_PXP;
10912 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
10913 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
10914 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
10915 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
10916 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
10917 MISC_REGISTERS_RESET_REG_2_RST_GRC |
10918 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
10919 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
10920 MISC_REGISTERS_RESET_REG_2_RST_ATC |
10921 MISC_REGISTERS_RESET_REG_2_PGLC |
10922 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
10923 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
10924 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
10925 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
10926 MISC_REGISTERS_RESET_REG_2_UMAC0 |
10927 MISC_REGISTERS_RESET_REG_2_UMAC1;
10930 * Keep the following blocks in reset:
10931 * - all xxMACs are handled by the elink code.
10934 MISC_REGISTERS_RESET_REG_2_XMAC |
10935 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
10937 /* Full reset masks according to the chip */
10938 reset_mask1 = 0xffffffff;
10940 if (CHIP_IS_E1(sc))
10941 reset_mask2 = 0xffff;
10942 else if (CHIP_IS_E1H(sc))
10943 reset_mask2 = 0x1ffff;
10944 else if (CHIP_IS_E2(sc))
10945 reset_mask2 = 0xfffff;
10946 else /* CHIP_IS_E3 */
10947 reset_mask2 = 0x3ffffff;
10949 /* Don't reset global blocks unless we need to */
10951 reset_mask2 &= ~global_bits2;
10954 * In case of attention in the QM, we need to reset PXP
10955 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
10956 * because otherwise QM reset would release 'close the gates' shortly
10957 * before resetting the PXP, then the PSWRQ would send a write
10958 * request to PGLUE. Then when PXP is reset, PGLUE would try to
10959 * read the payload data from PSWWR, but PSWWR would not
10960 * respond. The write queue in PGLUE would stuck, dmae commands
10961 * would not return. Therefore it's important to reset the second
10962 * reset register (containing the
10963 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
10964 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
10967 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
10968 reset_mask2 & (~not_reset_mask2));
10970 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
10971 reset_mask1 & (~not_reset_mask1));
10976 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
10977 reset_mask2 & (~stay_reset2));
10982 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
10987 bxe_process_kill(struct bxe_softc *sc,
10992 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
10993 uint32_t tags_63_32 = 0;
10995 /* Empty the Tetris buffer, wait for 1s */
10997 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
10998 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
10999 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11000 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11001 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11002 if (CHIP_IS_E3(sc)) {
11003 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11006 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11007 ((port_is_idle_0 & 0x1) == 0x1) &&
11008 ((port_is_idle_1 & 0x1) == 0x1) &&
11009 (pgl_exp_rom2 == 0xffffffff) &&
11010 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11013 } while (cnt-- > 0);
11016 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11017 "are still outstanding read requests after 1s! "
11018 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11019 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11020 sr_cnt, blk_cnt, port_is_idle_0,
11021 port_is_idle_1, pgl_exp_rom2);
11027 /* Close gates #2, #3 and #4 */
11028 bxe_set_234_gates(sc, TRUE);
11030 /* Poll for IGU VQs for 57712 and newer chips */
11031 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11035 /* XXX indicate that "process kill" is in progress to MCP */
11037 /* clear "unprepared" bit */
11038 REG_WR(sc, MISC_REG_UNPREPARED, 0);
11041 /* Make sure all is written to the chip before the reset */
11045 * Wait for 1ms to empty GLUE and PCI-E core queues,
11046 * PSWHST, GRC and PSWRD Tetris buffer.
11050 /* Prepare to chip reset: */
11053 bxe_reset_mcp_prep(sc, &val);
11060 /* reset the chip */
11061 bxe_process_kill_chip_reset(sc, global);
11064 /* clear errors in PGB */
11065 if (!CHIP_IS_E1(sc))
11066 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11068 /* Recover after reset: */
11070 if (global && bxe_reset_mcp_comp(sc, val)) {
11074 /* XXX add resetting the NO_MCP mode DB here */
11076 /* Open the gates #2, #3 and #4 */
11077 bxe_set_234_gates(sc, FALSE);
11080 * IGU/AEU preparation bring back the AEU/IGU to a reset state
11081 * re-enable attentions
11088 bxe_leader_reset(struct bxe_softc *sc)
11091 uint8_t global = bxe_reset_is_global(sc);
11092 uint32_t load_code;
11095 * If not going to reset MCP, load "fake" driver to reset HW while
11096 * driver is owner of the HW.
11098 if (!global && !BXE_NOMCP(sc)) {
11099 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11100 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11102 BLOGE(sc, "MCP response failure, aborting\n");
11104 goto exit_leader_reset;
11107 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11108 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11109 BLOGE(sc, "MCP unexpected response, aborting\n");
11111 goto exit_leader_reset2;
11114 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11116 BLOGE(sc, "MCP response failure, aborting\n");
11118 goto exit_leader_reset2;
11122 /* try to recover after the failure */
11123 if (bxe_process_kill(sc, global)) {
11124 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11126 goto exit_leader_reset2;
11130 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11133 bxe_set_reset_done(sc);
11135 bxe_clear_reset_global(sc);
11138 exit_leader_reset2:
11140 /* unload "fake driver" if it was loaded */
11141 if (!global && !BXE_NOMCP(sc)) {
11142 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11143 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11149 bxe_release_leader_lock(sc);
11156 * prepare INIT transition, parameters configured:
11157 * - HC configuration
11158 * - Queue's CDU context
11161 bxe_pf_q_prep_init(struct bxe_softc *sc,
11162 struct bxe_fastpath *fp,
11163 struct ecore_queue_init_params *init_params)
11166 int cxt_index, cxt_offset;
11168 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11169 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11171 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11172 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11175 init_params->rx.hc_rate =
11176 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11177 init_params->tx.hc_rate =
11178 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11181 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11183 /* CQ index among the SB indices */
11184 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11185 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11187 /* set maximum number of COSs supported by this queue */
11188 init_params->max_cos = sc->max_cos;
11190 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11191 fp->index, init_params->max_cos);
11193 /* set the context pointers queue object */
11194 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11195 /* XXX change index/cid here if ever support multiple tx CoS */
11196 /* fp->txdata[cos]->cid */
11197 cxt_index = fp->index / ILT_PAGE_CIDS;
11198 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11199 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11203 /* set flags that are common for the Tx-only and not normal connections */
11204 static unsigned long
11205 bxe_get_common_flags(struct bxe_softc *sc,
11206 struct bxe_fastpath *fp,
11207 uint8_t zero_stats)
11209 unsigned long flags = 0;
11211 /* PF driver will always initialize the Queue to an ACTIVE state */
11212 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11215 * tx only connections collect statistics (on the same index as the
11216 * parent connection). The statistics are zeroed when the parent
11217 * connection is initialized.
11220 bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11222 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11226 * tx only connections can support tx-switching, though their
11227 * CoS-ness doesn't survive the loopback
11229 if (sc->flags & BXE_TX_SWITCHING) {
11230 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11233 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11238 static unsigned long
11239 bxe_get_q_flags(struct bxe_softc *sc,
11240 struct bxe_fastpath *fp,
11243 unsigned long flags = 0;
11245 if (IS_MF_SD(sc)) {
11246 bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11249 if (sc->ifnet->if_capenable & IFCAP_LRO) {
11250 bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11251 #if __FreeBSD_version >= 800000
11252 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11257 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11258 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11261 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11263 /* merge with common flags */
11264 return (flags | bxe_get_common_flags(sc, fp, TRUE));
11268 bxe_pf_q_prep_general(struct bxe_softc *sc,
11269 struct bxe_fastpath *fp,
11270 struct ecore_general_setup_params *gen_init,
11273 gen_init->stat_id = bxe_stats_id(fp);
11274 gen_init->spcl_id = fp->cl_id;
11275 gen_init->mtu = sc->mtu;
11276 gen_init->cos = cos;
11280 bxe_pf_rx_q_prep(struct bxe_softc *sc,
11281 struct bxe_fastpath *fp,
11282 struct rxq_pause_params *pause,
11283 struct ecore_rxq_setup_params *rxq_init)
11285 uint8_t max_sge = 0;
11286 uint16_t sge_sz = 0;
11287 uint16_t tpa_agg_size = 0;
11289 pause->sge_th_lo = SGE_TH_LO(sc);
11290 pause->sge_th_hi = SGE_TH_HI(sc);
11292 /* validate SGE ring has enough to cross high threshold */
11293 if (sc->dropless_fc &&
11294 (pause->sge_th_hi + FW_PREFETCH_CNT) >
11295 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11296 BLOGW(sc, "sge ring threshold limit\n");
11299 /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11300 tpa_agg_size = (2 * sc->mtu);
11301 if (tpa_agg_size < sc->max_aggregation_size) {
11302 tpa_agg_size = sc->max_aggregation_size;
11305 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11306 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11307 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11308 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11310 /* pause - not for e1 */
11311 if (!CHIP_IS_E1(sc)) {
11312 pause->bd_th_lo = BD_TH_LO(sc);
11313 pause->bd_th_hi = BD_TH_HI(sc);
11315 pause->rcq_th_lo = RCQ_TH_LO(sc);
11316 pause->rcq_th_hi = RCQ_TH_HI(sc);
11318 /* validate rings have enough entries to cross high thresholds */
11319 if (sc->dropless_fc &&
11320 pause->bd_th_hi + FW_PREFETCH_CNT >
11321 sc->rx_ring_size) {
11322 BLOGW(sc, "rx bd ring threshold limit\n");
11325 if (sc->dropless_fc &&
11326 pause->rcq_th_hi + FW_PREFETCH_CNT >
11327 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11328 BLOGW(sc, "rcq ring threshold limit\n");
11331 pause->pri_map = 1;
11335 rxq_init->dscr_map = fp->rx_dma.paddr;
11336 rxq_init->sge_map = fp->rx_sge_dma.paddr;
11337 rxq_init->rcq_map = fp->rcq_dma.paddr;
11338 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11341 * This should be a maximum number of data bytes that may be
11342 * placed on the BD (not including paddings).
11344 rxq_init->buf_sz = (fp->rx_buf_size -
11345 IP_HEADER_ALIGNMENT_PADDING);
11347 rxq_init->cl_qzone_id = fp->cl_qzone_id;
11348 rxq_init->tpa_agg_sz = tpa_agg_size;
11349 rxq_init->sge_buf_sz = sge_sz;
11350 rxq_init->max_sges_pkt = max_sge;
11351 rxq_init->rss_engine_id = SC_FUNC(sc);
11352 rxq_init->mcast_engine_id = SC_FUNC(sc);
11355 * Maximum number or simultaneous TPA aggregation for this Queue.
11356 * For PF Clients it should be the maximum available number.
11357 * VF driver(s) may want to define it to a smaller value.
11359 rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11361 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11362 rxq_init->fw_sb_id = fp->fw_sb_id;
11364 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11367 * configure silent vlan removal
11368 * if multi function mode is afex, then mask default vlan
11370 if (IS_MF_AFEX(sc)) {
11371 rxq_init->silent_removal_value =
11372 sc->devinfo.mf_info.afex_def_vlan_tag;
11373 rxq_init->silent_removal_mask = EVL_VLID_MASK;
11378 bxe_pf_tx_q_prep(struct bxe_softc *sc,
11379 struct bxe_fastpath *fp,
11380 struct ecore_txq_setup_params *txq_init,
11384 * XXX If multiple CoS is ever supported then each fastpath structure
11385 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11386 * fp->txdata[cos]->tx_dma.paddr;
11388 txq_init->dscr_map = fp->tx_dma.paddr;
11389 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11390 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11391 txq_init->fw_sb_id = fp->fw_sb_id;
11394 * set the TSS leading client id for TX classfication to the
11395 * leading RSS client id
11397 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11401 * This function performs 2 steps in a queue state machine:
11406 bxe_setup_queue(struct bxe_softc *sc,
11407 struct bxe_fastpath *fp,
11410 struct ecore_queue_state_params q_params = { NULL };
11411 struct ecore_queue_setup_params *setup_params =
11412 &q_params.params.setup;
11415 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11417 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11419 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11421 /* we want to wait for completion in this context */
11422 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11424 /* prepare the INIT parameters */
11425 bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11427 /* Set the command */
11428 q_params.cmd = ECORE_Q_CMD_INIT;
11430 /* Change the state to INIT */
11431 rc = ecore_queue_state_change(sc, &q_params);
11433 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc);
11437 BLOGD(sc, DBG_LOAD, "init complete\n");
11439 /* now move the Queue to the SETUP state */
11440 memset(setup_params, 0, sizeof(*setup_params));
11442 /* set Queue flags */
11443 setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11445 /* set general SETUP parameters */
11446 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11447 FIRST_TX_COS_INDEX);
11449 bxe_pf_rx_q_prep(sc, fp,
11450 &setup_params->pause_params,
11451 &setup_params->rxq_params);
11453 bxe_pf_tx_q_prep(sc, fp,
11454 &setup_params->txq_params,
11455 FIRST_TX_COS_INDEX);
11457 /* Set the command */
11458 q_params.cmd = ECORE_Q_CMD_SETUP;
11460 /* change the state to SETUP */
11461 rc = ecore_queue_state_change(sc, &q_params);
11463 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc);
11471 bxe_setup_leading(struct bxe_softc *sc)
11473 return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11477 bxe_config_rss_pf(struct bxe_softc *sc,
11478 struct ecore_rss_config_obj *rss_obj,
11479 uint8_t config_hash)
11481 struct ecore_config_rss_params params = { NULL };
11485 * Although RSS is meaningless when there is a single HW queue we
11486 * still need it enabled in order to have HW Rx hash generated.
11489 params.rss_obj = rss_obj;
11491 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
11493 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
11495 /* RSS configuration */
11496 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
11497 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
11498 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
11499 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
11500 if (rss_obj->udp_rss_v4) {
11501 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
11503 if (rss_obj->udp_rss_v6) {
11504 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
11508 params.rss_result_mask = MULTI_MASK;
11510 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11514 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
11515 params.rss_key[i] = arc4random();
11518 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
11521 return (ecore_config_rss(sc, ¶ms));
11525 bxe_config_rss_eth(struct bxe_softc *sc,
11526 uint8_t config_hash)
11528 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
11532 bxe_init_rss_pf(struct bxe_softc *sc)
11534 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
11538 * Prepare the initial contents of the indirection table if
11541 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
11542 sc->rss_conf_obj.ind_table[i] =
11543 (sc->fp->cl_id + (i % num_eth_queues));
11547 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
11551 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
11552 * per-port, so if explicit configuration is needed, do it only
11555 * For 57712 and newer it's a per-function configuration.
11557 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
11561 bxe_set_mac_one(struct bxe_softc *sc,
11563 struct ecore_vlan_mac_obj *obj,
11566 unsigned long *ramrod_flags)
11568 struct ecore_vlan_mac_ramrod_params ramrod_param;
11571 memset(&ramrod_param, 0, sizeof(ramrod_param));
11573 /* fill in general parameters */
11574 ramrod_param.vlan_mac_obj = obj;
11575 ramrod_param.ramrod_flags = *ramrod_flags;
11577 /* fill a user request section if needed */
11578 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
11579 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
11581 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
11583 /* Set the command: ADD or DEL */
11584 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
11585 ECORE_VLAN_MAC_DEL;
11588 rc = ecore_config_vlan_mac(sc, &ramrod_param);
11590 if (rc == ECORE_EXISTS) {
11591 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
11592 /* do not treat adding same MAC as error */
11594 } else if (rc < 0) {
11595 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
11602 bxe_set_eth_mac(struct bxe_softc *sc,
11605 unsigned long ramrod_flags = 0;
11607 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
11609 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11611 /* Eth MAC is set on RSS leading client (fp[0]) */
11612 return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
11613 &sc->sp_objs->mac_obj,
11614 set, ECORE_ETH_MAC, &ramrod_flags));
11618 bxe_get_cur_phy_idx(struct bxe_softc *sc)
11620 uint32_t sel_phy_idx = 0;
11622 if (sc->link_params.num_phys <= 1) {
11623 return (ELINK_INT_PHY);
11626 if (sc->link_vars.link_up) {
11627 sel_phy_idx = ELINK_EXT_PHY1;
11628 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
11629 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
11630 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
11631 ELINK_SUPPORTED_FIBRE))
11632 sel_phy_idx = ELINK_EXT_PHY2;
11634 switch (elink_phy_selection(&sc->link_params)) {
11635 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11636 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11637 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11638 sel_phy_idx = ELINK_EXT_PHY1;
11640 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11641 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11642 sel_phy_idx = ELINK_EXT_PHY2;
11647 return (sel_phy_idx);
11651 bxe_get_link_cfg_idx(struct bxe_softc *sc)
11653 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
11656 * The selected activated PHY is always after swapping (in case PHY
11657 * swapping is enabled). So when swapping is enabled, we need to reverse
11658 * the configuration
11661 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
11662 if (sel_phy_idx == ELINK_EXT_PHY1)
11663 sel_phy_idx = ELINK_EXT_PHY2;
11664 else if (sel_phy_idx == ELINK_EXT_PHY2)
11665 sel_phy_idx = ELINK_EXT_PHY1;
11668 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
11672 bxe_set_requested_fc(struct bxe_softc *sc)
11675 * Initialize link parameters structure variables
11676 * It is recommended to turn off RX FC for jumbo frames
11677 * for better performance
11679 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
11680 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
11682 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
11687 bxe_calc_fc_adv(struct bxe_softc *sc)
11689 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
11692 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
11695 switch (sc->link_vars.ieee_fc &
11696 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
11698 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
11699 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
11703 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
11704 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
11714 bxe_get_mf_speed(struct bxe_softc *sc)
11716 uint16_t line_speed = sc->link_vars.line_speed;
11719 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
11721 /* calculate the current MAX line speed limit for the MF devices */
11722 if (IS_MF_SI(sc)) {
11723 line_speed = (line_speed * maxCfg) / 100;
11724 } else { /* SD mode */
11725 uint16_t vn_max_rate = maxCfg * 100;
11727 if (vn_max_rate < line_speed) {
11728 line_speed = vn_max_rate;
11733 return (line_speed);
11737 bxe_fill_report_data(struct bxe_softc *sc,
11738 struct bxe_link_report_data *data)
11740 uint16_t line_speed = bxe_get_mf_speed(sc);
11742 memset(data, 0, sizeof(*data));
11744 /* fill the report data with the effective line speed */
11745 data->line_speed = line_speed;
11748 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
11749 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
11753 if (sc->link_vars.duplex == DUPLEX_FULL) {
11754 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
11757 /* Rx Flow Control is ON */
11758 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
11759 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
11762 /* Tx Flow Control is ON */
11763 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
11764 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
11768 /* report link status to OS, should be called under phy_lock */
11770 bxe_link_report_locked(struct bxe_softc *sc)
11772 struct bxe_link_report_data cur_data;
11774 /* reread mf_cfg */
11775 if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
11776 bxe_read_mf_cfg(sc);
11779 /* Read the current link report info */
11780 bxe_fill_report_data(sc, &cur_data);
11782 /* Don't report link down or exactly the same link status twice */
11783 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
11784 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11785 &sc->last_reported_link.link_report_flags) &&
11786 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11787 &cur_data.link_report_flags))) {
11791 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x\n",
11792 cur_data.link_report_flags, sc->last_reported_link.link_report_flags);
11795 ELINK_DEBUG_P1(sc, "link status change count = %x\n", sc->link_cnt);
11796 /* report new link params and remember the state for the next time */
11797 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
11799 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
11800 &cur_data.link_report_flags)) {
11801 if_link_state_change(sc->ifnet, LINK_STATE_DOWN);
11803 const char *duplex;
11806 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
11807 &cur_data.link_report_flags)) {
11809 ELINK_DEBUG_P0(sc, "link set to full duplex\n");
11812 ELINK_DEBUG_P0(sc, "link set to half duplex\n");
11816 * Handle the FC at the end so that only these flags would be
11817 * possibly set. This way we may easily check if there is no FC
11820 if (cur_data.link_report_flags) {
11821 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11822 &cur_data.link_report_flags) &&
11823 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11824 &cur_data.link_report_flags)) {
11825 flow = "ON - receive & transmit";
11826 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11827 &cur_data.link_report_flags) &&
11828 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11829 &cur_data.link_report_flags)) {
11830 flow = "ON - receive";
11831 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
11832 &cur_data.link_report_flags) &&
11833 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
11834 &cur_data.link_report_flags)) {
11835 flow = "ON - transmit";
11837 flow = "none"; /* possible? */
11843 if_link_state_change(sc->ifnet, LINK_STATE_UP);
11844 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
11845 cur_data.line_speed, duplex, flow);
11850 bxe_link_report(struct bxe_softc *sc)
11852 bxe_acquire_phy_lock(sc);
11853 bxe_link_report_locked(sc);
11854 bxe_release_phy_lock(sc);
11858 bxe_link_status_update(struct bxe_softc *sc)
11860 if (sc->state != BXE_STATE_OPEN) {
11864 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
11865 elink_link_status_update(&sc->link_params, &sc->link_vars);
11867 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
11868 ELINK_SUPPORTED_10baseT_Full |
11869 ELINK_SUPPORTED_100baseT_Half |
11870 ELINK_SUPPORTED_100baseT_Full |
11871 ELINK_SUPPORTED_1000baseT_Full |
11872 ELINK_SUPPORTED_2500baseX_Full |
11873 ELINK_SUPPORTED_10000baseT_Full |
11874 ELINK_SUPPORTED_TP |
11875 ELINK_SUPPORTED_FIBRE |
11876 ELINK_SUPPORTED_Autoneg |
11877 ELINK_SUPPORTED_Pause |
11878 ELINK_SUPPORTED_Asym_Pause);
11879 sc->port.advertising[0] = sc->port.supported[0];
11881 sc->link_params.sc = sc;
11882 sc->link_params.port = SC_PORT(sc);
11883 sc->link_params.req_duplex[0] = DUPLEX_FULL;
11884 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
11885 sc->link_params.req_line_speed[0] = SPEED_10000;
11886 sc->link_params.speed_cap_mask[0] = 0x7f0000;
11887 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
11889 if (CHIP_REV_IS_FPGA(sc)) {
11890 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
11891 sc->link_vars.line_speed = ELINK_SPEED_1000;
11892 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11893 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
11895 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
11896 sc->link_vars.line_speed = ELINK_SPEED_10000;
11897 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
11898 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
11901 sc->link_vars.link_up = 1;
11903 sc->link_vars.duplex = DUPLEX_FULL;
11904 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
11907 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
11908 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11909 bxe_link_report(sc);
11914 if (sc->link_vars.link_up) {
11915 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11917 bxe_stats_handle(sc, STATS_EVENT_STOP);
11919 bxe_link_report(sc);
11921 bxe_link_report(sc);
11922 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11927 bxe_initial_phy_init(struct bxe_softc *sc,
11930 int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
11931 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
11932 struct elink_params *lp = &sc->link_params;
11934 bxe_set_requested_fc(sc);
11936 if (CHIP_REV_IS_SLOW(sc)) {
11937 uint32_t bond = CHIP_BOND_ID(sc);
11940 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
11941 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11942 } else if (bond & 0x4) {
11943 if (CHIP_IS_E3(sc)) {
11944 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
11946 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
11948 } else if (bond & 0x8) {
11949 if (CHIP_IS_E3(sc)) {
11950 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
11952 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11956 /* disable EMAC for E3 and above */
11958 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
11961 sc->link_params.feature_config_flags |= feat;
11964 bxe_acquire_phy_lock(sc);
11966 if (load_mode == LOAD_DIAG) {
11967 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
11968 /* Prefer doing PHY loopback at 10G speed, if possible */
11969 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
11970 if (lp->speed_cap_mask[cfg_idx] &
11971 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
11972 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
11974 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
11979 if (load_mode == LOAD_LOOPBACK_EXT) {
11980 lp->loopback_mode = ELINK_LOOPBACK_EXT;
11983 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
11985 bxe_release_phy_lock(sc);
11987 bxe_calc_fc_adv(sc);
11989 if (sc->link_vars.link_up) {
11990 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
11991 bxe_link_report(sc);
11994 if (!CHIP_REV_IS_SLOW(sc)) {
11995 bxe_periodic_start(sc);
11998 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12002 /* must be called under IF_ADDR_LOCK */
12004 bxe_init_mcast_macs_list(struct bxe_softc *sc,
12005 struct ecore_mcast_ramrod_params *p)
12007 struct ifnet *ifp = sc->ifnet;
12009 struct ifmultiaddr *ifma;
12010 struct ecore_mcast_list_elem *mc_mac;
12012 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12013 if (ifma->ifma_addr->sa_family != AF_LINK) {
12020 ECORE_LIST_INIT(&p->mcast_list);
12021 p->mcast_list_len = 0;
12027 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF,
12028 (M_NOWAIT | M_ZERO));
12030 BLOGE(sc, "Failed to allocate temp mcast list\n");
12033 bzero(mc_mac, (sizeof(*mc_mac) * mc_count));
12035 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12036 if (ifma->ifma_addr->sa_family != AF_LINK) {
12040 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
12041 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list);
12043 BLOGD(sc, DBG_LOAD,
12044 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X and mc_count %d\n",
12045 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2],
12046 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5], mc_count);
12050 p->mcast_list_len = mc_count;
12057 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
12059 struct ecore_mcast_list_elem *mc_mac =
12060 ECORE_LIST_FIRST_ENTRY(&p->mcast_list,
12061 struct ecore_mcast_list_elem,
12065 /* only a single free as all mc_macs are in the same heap array */
12066 free(mc_mac, M_DEVBUF);
12071 bxe_set_mc_list(struct bxe_softc *sc)
12073 struct ecore_mcast_ramrod_params rparam = { NULL };
12076 rparam.mcast_obj = &sc->mcast_obj;
12078 BXE_MCAST_LOCK(sc);
12080 /* first, clear all configured multicast MACs */
12081 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12083 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12084 /* Manual backport parts of FreeBSD upstream r284470. */
12085 BXE_MCAST_UNLOCK(sc);
12089 /* configure a new MACs list */
12090 rc = bxe_init_mcast_macs_list(sc, &rparam);
12092 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc);
12093 BXE_MCAST_UNLOCK(sc);
12097 /* Now add the new MACs */
12098 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12100 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12103 bxe_free_mcast_macs_list(&rparam);
12105 BXE_MCAST_UNLOCK(sc);
12111 bxe_set_uc_list(struct bxe_softc *sc)
12113 struct ifnet *ifp = sc->ifnet;
12114 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12115 struct ifaddr *ifa;
12116 unsigned long ramrod_flags = 0;
12119 #if __FreeBSD_version < 800000
12122 if_addr_rlock(ifp);
12125 /* first schedule a cleanup up of old configuration */
12126 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12128 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12129 #if __FreeBSD_version < 800000
12130 IF_ADDR_UNLOCK(ifp);
12132 if_addr_runlock(ifp);
12137 ifa = ifp->if_addr;
12139 if (ifa->ifa_addr->sa_family != AF_LINK) {
12140 ifa = TAILQ_NEXT(ifa, ifa_link);
12144 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr),
12145 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags);
12146 if (rc == -EEXIST) {
12147 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12148 /* do not treat adding same MAC as an error */
12150 } else if (rc < 0) {
12151 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc);
12152 #if __FreeBSD_version < 800000
12153 IF_ADDR_UNLOCK(ifp);
12155 if_addr_runlock(ifp);
12160 ifa = TAILQ_NEXT(ifa, ifa_link);
12163 #if __FreeBSD_version < 800000
12164 IF_ADDR_UNLOCK(ifp);
12166 if_addr_runlock(ifp);
12169 /* Execute the pending commands */
12170 bit_set(&ramrod_flags, RAMROD_CONT);
12171 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12172 ECORE_UC_LIST_MAC, &ramrod_flags));
12176 bxe_set_rx_mode(struct bxe_softc *sc)
12178 struct ifnet *ifp = sc->ifnet;
12179 uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12181 if (sc->state != BXE_STATE_OPEN) {
12182 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12186 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags);
12188 if (ifp->if_flags & IFF_PROMISC) {
12189 rx_mode = BXE_RX_MODE_PROMISC;
12190 } else if ((ifp->if_flags & IFF_ALLMULTI) ||
12191 ((ifp->if_amcount > BXE_MAX_MULTICAST) &&
12193 rx_mode = BXE_RX_MODE_ALLMULTI;
12196 /* some multicasts */
12197 if (bxe_set_mc_list(sc) < 0) {
12198 rx_mode = BXE_RX_MODE_ALLMULTI;
12200 if (bxe_set_uc_list(sc) < 0) {
12201 rx_mode = BXE_RX_MODE_PROMISC;
12206 sc->rx_mode = rx_mode;
12208 /* schedule the rx_mode command */
12209 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12210 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12211 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12216 bxe_set_storm_rx_mode(sc);
12221 /* update flags in shmem */
12223 bxe_update_drv_flags(struct bxe_softc *sc,
12227 uint32_t drv_flags;
12229 if (SHMEM2_HAS(sc, drv_flags)) {
12230 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12231 drv_flags = SHMEM2_RD(sc, drv_flags);
12234 SET_FLAGS(drv_flags, flags);
12236 RESET_FLAGS(drv_flags, flags);
12239 SHMEM2_WR(sc, drv_flags, drv_flags);
12240 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12242 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12246 /* periodic timer callout routine, only runs when the interface is up */
12249 bxe_periodic_callout_func(void *xsc)
12251 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12254 if (!BXE_CORE_TRYLOCK(sc)) {
12255 /* just bail and try again next time */
12257 if ((sc->state == BXE_STATE_OPEN) &&
12258 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12259 /* schedule the next periodic callout */
12260 callout_reset(&sc->periodic_callout, hz,
12261 bxe_periodic_callout_func, sc);
12267 if ((sc->state != BXE_STATE_OPEN) ||
12268 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12269 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12270 BXE_CORE_UNLOCK(sc);
12275 /* Check for TX timeouts on any fastpath. */
12276 FOR_EACH_QUEUE(sc, i) {
12277 if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12278 /* Ruh-Roh, chip was reset! */
12283 if (!CHIP_REV_IS_SLOW(sc)) {
12285 * This barrier is needed to ensure the ordering between the writing
12286 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12287 * the reading here.
12290 if (sc->port.pmf) {
12291 bxe_acquire_phy_lock(sc);
12292 elink_period_func(&sc->link_params, &sc->link_vars);
12293 bxe_release_phy_lock(sc);
12297 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) {
12298 int mb_idx = SC_FW_MB_IDX(sc);
12299 uint32_t drv_pulse;
12300 uint32_t mcp_pulse;
12302 ++sc->fw_drv_pulse_wr_seq;
12303 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12305 drv_pulse = sc->fw_drv_pulse_wr_seq;
12308 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12309 MCP_PULSE_SEQ_MASK);
12312 * The delta between driver pulse and mcp response should
12313 * be 1 (before mcp response) or 0 (after mcp response).
12315 if ((drv_pulse != mcp_pulse) &&
12316 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12317 /* someone lost a heartbeat... */
12318 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12319 drv_pulse, mcp_pulse);
12323 /* state is BXE_STATE_OPEN */
12324 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12326 BXE_CORE_UNLOCK(sc);
12328 if ((sc->state == BXE_STATE_OPEN) &&
12329 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12330 /* schedule the next periodic callout */
12331 callout_reset(&sc->periodic_callout, hz,
12332 bxe_periodic_callout_func, sc);
12337 bxe_periodic_start(struct bxe_softc *sc)
12339 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12340 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12344 bxe_periodic_stop(struct bxe_softc *sc)
12346 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12347 callout_drain(&sc->periodic_callout);
12350 /* start the controller */
12351 static __noinline int
12352 bxe_nic_load(struct bxe_softc *sc,
12359 BXE_CORE_LOCK_ASSERT(sc);
12361 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12363 sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12366 /* must be called before memory allocation and HW init */
12367 bxe_ilt_set_info(sc);
12370 sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12372 bxe_set_fp_rx_buf_size(sc);
12374 if (bxe_alloc_fp_buffers(sc) != 0) {
12375 BLOGE(sc, "Failed to allocate fastpath memory\n");
12376 sc->state = BXE_STATE_CLOSED;
12378 goto bxe_nic_load_error0;
12381 if (bxe_alloc_mem(sc) != 0) {
12382 sc->state = BXE_STATE_CLOSED;
12384 goto bxe_nic_load_error0;
12387 if (bxe_alloc_fw_stats_mem(sc) != 0) {
12388 sc->state = BXE_STATE_CLOSED;
12390 goto bxe_nic_load_error0;
12394 /* set pf load just before approaching the MCP */
12395 bxe_set_pf_load(sc);
12397 /* if MCP exists send load request and analyze response */
12398 if (!BXE_NOMCP(sc)) {
12399 /* attempt to load pf */
12400 if (bxe_nic_load_request(sc, &load_code) != 0) {
12401 sc->state = BXE_STATE_CLOSED;
12403 goto bxe_nic_load_error1;
12406 /* what did the MCP say? */
12407 if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12408 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12409 sc->state = BXE_STATE_CLOSED;
12411 goto bxe_nic_load_error2;
12414 BLOGI(sc, "Device has no MCP!\n");
12415 load_code = bxe_nic_load_no_mcp(sc);
12418 /* mark PMF if applicable */
12419 bxe_nic_load_pmf(sc, load_code);
12421 /* Init Function state controlling object */
12422 bxe_init_func_obj(sc);
12424 /* Initialize HW */
12425 if (bxe_init_hw(sc, load_code) != 0) {
12426 BLOGE(sc, "HW init failed\n");
12427 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12428 sc->state = BXE_STATE_CLOSED;
12430 goto bxe_nic_load_error2;
12434 /* set ALWAYS_ALIVE bit in shmem */
12435 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
12437 sc->flags |= BXE_NO_PULSE;
12439 /* attach interrupts */
12440 if (bxe_interrupt_attach(sc) != 0) {
12441 sc->state = BXE_STATE_CLOSED;
12443 goto bxe_nic_load_error2;
12446 bxe_nic_init(sc, load_code);
12448 /* Init per-function objects */
12451 // XXX bxe_iov_nic_init(sc);
12453 /* set AFEX default VLAN tag to an invalid value */
12454 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12455 // XXX bxe_nic_load_afex_dcc(sc, load_code);
12457 sc->state = BXE_STATE_OPENING_WAITING_PORT;
12458 rc = bxe_func_start(sc);
12460 BLOGE(sc, "Function start failed! rc = %d\n", rc);
12461 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12462 sc->state = BXE_STATE_ERROR;
12463 goto bxe_nic_load_error3;
12466 /* send LOAD_DONE command to MCP */
12467 if (!BXE_NOMCP(sc)) {
12468 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12470 BLOGE(sc, "MCP response failure, aborting\n");
12471 sc->state = BXE_STATE_ERROR;
12473 goto bxe_nic_load_error3;
12477 rc = bxe_setup_leading(sc);
12479 BLOGE(sc, "Setup leading failed! rc = %d\n", rc);
12480 sc->state = BXE_STATE_ERROR;
12481 goto bxe_nic_load_error3;
12484 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12485 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12487 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc);
12488 sc->state = BXE_STATE_ERROR;
12489 goto bxe_nic_load_error3;
12493 rc = bxe_init_rss_pf(sc);
12495 BLOGE(sc, "PF RSS init failed\n");
12496 sc->state = BXE_STATE_ERROR;
12497 goto bxe_nic_load_error3;
12502 /* now when Clients are configured we are ready to work */
12503 sc->state = BXE_STATE_OPEN;
12505 /* Configure a ucast MAC */
12507 rc = bxe_set_eth_mac(sc, TRUE);
12510 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc);
12511 sc->state = BXE_STATE_ERROR;
12512 goto bxe_nic_load_error3;
12515 if (sc->port.pmf) {
12516 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
12518 sc->state = BXE_STATE_ERROR;
12519 goto bxe_nic_load_error3;
12523 sc->link_params.feature_config_flags &=
12524 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
12526 /* start fast path */
12528 /* Initialize Rx filter */
12529 bxe_set_rx_mode(sc);
12532 switch (/* XXX load_mode */LOAD_OPEN) {
12538 case LOAD_LOOPBACK_EXT:
12539 sc->state = BXE_STATE_DIAG;
12546 if (sc->port.pmf) {
12547 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
12549 bxe_link_status_update(sc);
12552 /* start the periodic timer callout */
12553 bxe_periodic_start(sc);
12555 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
12556 /* mark driver is loaded in shmem2 */
12557 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
12558 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
12560 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
12561 DRV_FLAGS_CAPABILITIES_LOADED_L2));
12564 /* wait for all pending SP commands to complete */
12565 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
12566 BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
12567 bxe_periodic_stop(sc);
12568 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
12572 /* Tell the stack the driver is running! */
12573 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING;
12575 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
12579 bxe_nic_load_error3:
12582 bxe_int_disable_sync(sc, 1);
12584 /* clean out queued objects */
12585 bxe_squeeze_objects(sc);
12588 bxe_interrupt_detach(sc);
12590 bxe_nic_load_error2:
12592 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
12593 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
12594 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
12599 bxe_nic_load_error1:
12601 /* clear pf_load status, as it was already set */
12603 bxe_clear_pf_load(sc);
12606 bxe_nic_load_error0:
12608 bxe_free_fw_stats_mem(sc);
12609 bxe_free_fp_buffers(sc);
12616 bxe_init_locked(struct bxe_softc *sc)
12618 int other_engine = SC_PATH(sc) ? 0 : 1;
12619 uint8_t other_load_status, load_status;
12620 uint8_t global = FALSE;
12623 BXE_CORE_LOCK_ASSERT(sc);
12625 /* check if the driver is already running */
12626 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
12627 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
12631 bxe_set_power_state(sc, PCI_PM_D0);
12634 * If parity occurred during the unload, then attentions and/or
12635 * RECOVERY_IN_PROGRES may still be set. If so we want the first function
12636 * loaded on the current engine to complete the recovery. Parity recovery
12637 * is only relevant for PF driver.
12640 other_load_status = bxe_get_load_status(sc, other_engine);
12641 load_status = bxe_get_load_status(sc, SC_PATH(sc));
12643 if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
12644 bxe_chk_parity_attn(sc, &global, TRUE)) {
12647 * If there are attentions and they are in global blocks, set
12648 * the GLOBAL_RESET bit regardless whether it will be this
12649 * function that will complete the recovery or not.
12652 bxe_set_reset_global(sc);
12656 * Only the first function on the current engine should try
12657 * to recover in open. In case of attentions in global blocks
12658 * only the first in the chip should try to recover.
12660 if ((!load_status && (!global || !other_load_status)) &&
12661 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
12662 BLOGI(sc, "Recovered during init\n");
12666 /* recovery has failed... */
12667 bxe_set_power_state(sc, PCI_PM_D3hot);
12668 sc->recovery_state = BXE_RECOVERY_FAILED;
12670 BLOGE(sc, "Recovery flow hasn't properly "
12671 "completed yet, try again later. "
12672 "If you still see this message after a "
12673 "few retries then power cycle is required.\n");
12676 goto bxe_init_locked_done;
12681 sc->recovery_state = BXE_RECOVERY_DONE;
12683 rc = bxe_nic_load(sc, LOAD_OPEN);
12685 bxe_init_locked_done:
12688 /* Tell the stack the driver is NOT running! */
12689 BLOGE(sc, "Initialization failed, "
12690 "stack notified driver is NOT running!\n");
12691 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
12698 bxe_stop_locked(struct bxe_softc *sc)
12700 BXE_CORE_LOCK_ASSERT(sc);
12701 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
12705 * Handles controller initialization when called from an unlocked routine.
12706 * ifconfig calls this function.
12712 bxe_init(void *xsc)
12714 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12717 bxe_init_locked(sc);
12718 BXE_CORE_UNLOCK(sc);
12722 bxe_init_ifnet(struct bxe_softc *sc)
12726 /* ifconfig entrypoint for media type/status reporting */
12727 ifmedia_init(&sc->ifmedia, IFM_IMASK,
12728 bxe_ifmedia_update,
12729 bxe_ifmedia_status);
12731 /* set the default interface values */
12732 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
12733 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
12734 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
12736 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
12737 BLOGI(sc, "IFMEDIA flags : %x\n", sc->ifmedia.ifm_media);
12739 /* allocate the ifnet structure */
12740 if ((ifp = if_alloc(IFT_ETHER)) == NULL) {
12741 BLOGE(sc, "Interface allocation failed!\n");
12745 ifp->if_softc = sc;
12746 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
12747 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
12748 ifp->if_ioctl = bxe_ioctl;
12749 ifp->if_start = bxe_tx_start;
12750 #if __FreeBSD_version >= 901504
12751 ifp->if_transmit = bxe_tx_mq_start;
12752 ifp->if_qflush = bxe_mq_flush;
12757 ifp->if_init = bxe_init;
12758 ifp->if_mtu = sc->mtu;
12759 ifp->if_hwassist = (CSUM_IP |
12765 ifp->if_capabilities =
12766 #if __FreeBSD_version < 700000
12768 IFCAP_VLAN_HWTAGGING |
12774 IFCAP_VLAN_HWTAGGING |
12776 IFCAP_VLAN_HWFILTER |
12777 IFCAP_VLAN_HWCSUM |
12785 ifp->if_capenable = ifp->if_capabilities;
12786 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */
12787 #if __FreeBSD_version < 1000025
12788 ifp->if_baudrate = 1000000000;
12790 if_initbaudrate(ifp, IF_Gbps(10));
12792 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
12794 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
12795 IFQ_SET_READY(&ifp->if_snd);
12799 /* attach to the Ethernet interface list */
12800 ether_ifattach(ifp, sc->link_params.mac_addr);
12806 bxe_deallocate_bars(struct bxe_softc *sc)
12810 for (i = 0; i < MAX_BARS; i++) {
12811 if (sc->bar[i].resource != NULL) {
12812 bus_release_resource(sc->dev,
12815 sc->bar[i].resource);
12816 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
12823 bxe_allocate_bars(struct bxe_softc *sc)
12828 memset(sc->bar, 0, sizeof(sc->bar));
12830 for (i = 0; i < MAX_BARS; i++) {
12832 /* memory resources reside at BARs 0, 2, 4 */
12833 /* Run `pciconf -lb` to see mappings */
12834 if ((i != 0) && (i != 2) && (i != 4)) {
12838 sc->bar[i].rid = PCIR_BAR(i);
12842 flags |= RF_SHAREABLE;
12845 if ((sc->bar[i].resource =
12846 bus_alloc_resource_any(sc->dev,
12853 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource);
12854 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
12855 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
12857 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n",
12859 (void *)rman_get_start(sc->bar[i].resource),
12860 (void *)rman_get_end(sc->bar[i].resource),
12861 rman_get_size(sc->bar[i].resource),
12862 (void *)sc->bar[i].kva);
12869 bxe_get_function_num(struct bxe_softc *sc)
12874 * Read the ME register to get the function number. The ME register
12875 * holds the relative-function number and absolute-function number. The
12876 * absolute-function number appears only in E2 and above. Before that
12877 * these bits always contained zero, therefore we cannot blindly use them.
12880 val = REG_RD(sc, BAR_ME_REGISTER);
12883 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
12885 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
12887 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
12888 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
12890 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
12893 BLOGD(sc, DBG_LOAD,
12894 "Relative function %d, Absolute function %d, Path %d\n",
12895 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
12899 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
12901 uint32_t shmem2_size;
12903 uint32_t mf_cfg_offset_value;
12906 offset = (SHMEM_RD(sc, func_mb) +
12907 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
12910 if (sc->devinfo.shmem2_base != 0) {
12911 shmem2_size = SHMEM2_RD(sc, size);
12912 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
12913 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
12914 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
12915 offset = mf_cfg_offset_value;
12924 bxe_pcie_capability_read(struct bxe_softc *sc,
12930 /* ensure PCIe capability is enabled */
12931 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
12932 if (pcie_reg != 0) {
12933 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
12934 return (pci_read_config(sc->dev, (pcie_reg + reg), width));
12938 BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
12944 bxe_is_pcie_pending(struct bxe_softc *sc)
12946 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) &
12947 PCIM_EXP_STA_TRANSACTION_PND);
12951 * Walk the PCI capabiites list for the device to find what features are
12952 * supported. These capabilites may be enabled/disabled by firmware so it's
12953 * best to walk the list rather than make assumptions.
12956 bxe_probe_pci_caps(struct bxe_softc *sc)
12958 uint16_t link_status;
12961 /* check if PCI Power Management is enabled */
12962 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) {
12964 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
12966 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
12967 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
12971 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2);
12973 /* handle PCIe 2.0 workarounds for 57710 */
12974 if (CHIP_IS_E1(sc)) {
12975 /* workaround for 57710 errata E4_57710_27462 */
12976 sc->devinfo.pcie_link_speed =
12977 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
12979 /* workaround for 57710 errata E4_57710_27488 */
12980 sc->devinfo.pcie_link_width =
12981 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
12982 if (sc->devinfo.pcie_link_speed > 1) {
12983 sc->devinfo.pcie_link_width =
12984 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1;
12987 sc->devinfo.pcie_link_speed =
12988 (link_status & PCIM_LINK_STA_SPEED);
12989 sc->devinfo.pcie_link_width =
12990 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
12993 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
12994 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
12996 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
12997 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
12999 /* check if MSI capability is enabled */
13000 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) {
13002 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13004 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13005 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13009 /* check if MSI-X capability is enabled */
13010 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) {
13012 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13014 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13015 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13021 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13023 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13026 /* get the outer vlan if we're in switch-dependent mode */
13028 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13029 mf_info->ext_id = (uint16_t)val;
13031 mf_info->multi_vnics_mode = 1;
13033 if (!VALID_OVLAN(mf_info->ext_id)) {
13034 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13038 /* get the capabilities */
13039 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13040 FUNC_MF_CFG_PROTOCOL_ISCSI) {
13041 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13042 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13043 FUNC_MF_CFG_PROTOCOL_FCOE) {
13044 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13046 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13049 mf_info->vnics_per_port =
13050 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13056 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13058 uint32_t retval = 0;
13061 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13063 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13064 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13065 retval |= MF_PROTO_SUPPORT_ETHERNET;
13067 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13068 retval |= MF_PROTO_SUPPORT_ISCSI;
13070 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13071 retval |= MF_PROTO_SUPPORT_FCOE;
13079 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13081 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13085 * There is no outer vlan if we're in switch-independent mode.
13086 * If the mac is valid then assume multi-function.
13089 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13091 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13093 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13095 mf_info->vnics_per_port =
13096 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13102 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13104 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13105 uint32_t e1hov_tag;
13106 uint32_t func_config;
13107 uint32_t niv_config;
13109 mf_info->multi_vnics_mode = 1;
13111 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13112 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13113 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13116 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13117 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13119 mf_info->default_vlan =
13120 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13121 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13123 mf_info->niv_allowed_priorities =
13124 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13125 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13127 mf_info->niv_default_cos =
13128 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13129 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13131 mf_info->afex_vlan_mode =
13132 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13133 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13135 mf_info->niv_mba_enabled =
13136 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13137 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13139 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13141 mf_info->vnics_per_port =
13142 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13148 bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13150 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13157 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13159 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13160 mf_info->mf_config[SC_VN(sc)]);
13161 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13162 mf_info->multi_vnics_mode);
13163 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13164 mf_info->vnics_per_port);
13165 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13167 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13168 mf_info->min_bw[0], mf_info->min_bw[1],
13169 mf_info->min_bw[2], mf_info->min_bw[3]);
13170 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13171 mf_info->max_bw[0], mf_info->max_bw[1],
13172 mf_info->max_bw[2], mf_info->max_bw[3]);
13173 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13176 /* various MF mode sanity checks... */
13178 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13179 BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13184 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13185 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13186 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13190 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13191 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13192 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13193 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13194 SC_VN(sc), OVLAN(sc));
13198 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13199 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13200 mf_info->multi_vnics_mode, OVLAN(sc));
13205 * Verify all functions are either MF or SF mode. If MF, make sure
13206 * sure that all non-hidden functions have a valid ovlan. If SF,
13207 * make sure that all non-hidden functions have an invalid ovlan.
13209 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13210 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13211 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13212 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13213 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13214 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13215 BLOGE(sc, "mf_mode=SD function %d MF config "
13216 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13217 i, mf_info->multi_vnics_mode, ovlan1);
13222 /* Verify all funcs on the same port each have a different ovlan. */
13223 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13224 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13225 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13226 /* iterate from the next function on the port to the max func */
13227 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13228 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13229 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13230 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13231 VALID_OVLAN(ovlan1) &&
13232 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13233 VALID_OVLAN(ovlan2) &&
13234 (ovlan1 == ovlan2)) {
13235 BLOGE(sc, "mf_mode=SD functions %d and %d "
13236 "have the same ovlan (%d)\n",
13242 } /* MULTI_FUNCTION_SD */
13248 bxe_get_mf_cfg_info(struct bxe_softc *sc)
13250 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13251 uint32_t val, mac_upper;
13254 /* initialize mf_info defaults */
13255 mf_info->vnics_per_port = 1;
13256 mf_info->multi_vnics_mode = FALSE;
13257 mf_info->path_has_ovlan = FALSE;
13258 mf_info->mf_mode = SINGLE_FUNCTION;
13260 if (!CHIP_IS_MF_CAP(sc)) {
13264 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13265 BLOGE(sc, "Invalid mf_cfg_base!\n");
13269 /* get the MF mode (switch dependent / independent / single-function) */
13271 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13273 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13275 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13277 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13279 /* check for legal upper mac bytes */
13280 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13281 mf_info->mf_mode = MULTI_FUNCTION_SI;
13283 BLOGE(sc, "Invalid config for Switch Independent mode\n");
13288 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13289 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13291 /* get outer vlan configuration */
13292 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13294 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13295 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13296 mf_info->mf_mode = MULTI_FUNCTION_SD;
13298 BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13303 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13305 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13308 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13311 * Mark MF mode as NIV if MCP version includes NPAR-SD support
13312 * and the MAC address is valid.
13314 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13316 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13317 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13318 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13320 BLOGE(sc, "Invalid config for AFEX mode\n");
13327 BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13328 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13333 /* set path mf_mode (which could be different than function mf_mode) */
13334 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13335 mf_info->path_has_ovlan = TRUE;
13336 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13338 * Decide on path multi vnics mode. If we're not in MF mode and in
13339 * 4-port mode, this is good enough to check vnic-0 of the other port
13342 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13343 uint8_t other_port = !(PORT_ID(sc) & 1);
13344 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13346 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13348 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13352 if (mf_info->mf_mode == SINGLE_FUNCTION) {
13353 /* invalid MF config */
13354 if (SC_VN(sc) >= 1) {
13355 BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13362 /* get the MF configuration */
13363 mf_info->mf_config[SC_VN(sc)] =
13364 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13366 switch(mf_info->mf_mode)
13368 case MULTI_FUNCTION_SD:
13370 bxe_get_shmem_mf_cfg_info_sd(sc);
13373 case MULTI_FUNCTION_SI:
13375 bxe_get_shmem_mf_cfg_info_si(sc);
13378 case MULTI_FUNCTION_AFEX:
13380 bxe_get_shmem_mf_cfg_info_niv(sc);
13385 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13390 /* get the congestion management parameters */
13393 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13394 /* get min/max bw */
13395 val = MFCFG_RD(sc, func_mf_config[i].config);
13396 mf_info->min_bw[vnic] =
13397 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13398 mf_info->max_bw[vnic] =
13399 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13403 return (bxe_check_valid_mf_cfg(sc));
13407 bxe_get_shmem_info(struct bxe_softc *sc)
13410 uint32_t mac_hi, mac_lo, val;
13412 port = SC_PORT(sc);
13413 mac_hi = mac_lo = 0;
13415 sc->link_params.sc = sc;
13416 sc->link_params.port = port;
13418 /* get the hardware config info */
13419 sc->devinfo.hw_config =
13420 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13421 sc->devinfo.hw_config2 =
13422 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13424 sc->link_params.hw_led_mode =
13425 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13426 SHARED_HW_CFG_LED_MODE_SHIFT);
13428 /* get the port feature config */
13430 SHMEM_RD(sc, dev_info.port_feature_config[port].config),
13432 /* get the link params */
13433 sc->link_params.speed_cap_mask[0] =
13434 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13435 sc->link_params.speed_cap_mask[1] =
13436 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13438 /* get the lane config */
13439 sc->link_params.lane_config =
13440 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13442 /* get the link config */
13443 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13444 sc->port.link_config[ELINK_INT_PHY] = val;
13445 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13446 sc->port.link_config[ELINK_EXT_PHY1] =
13447 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13449 /* get the override preemphasis flag and enable it or turn it off */
13450 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13451 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13452 sc->link_params.feature_config_flags |=
13453 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13455 sc->link_params.feature_config_flags &=
13456 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
13459 /* get the initial value of the link params */
13460 sc->link_params.multi_phy_config =
13461 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
13463 /* get external phy info */
13464 sc->port.ext_phy_config =
13465 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
13467 /* get the multifunction configuration */
13468 bxe_get_mf_cfg_info(sc);
13470 /* get the mac address */
13472 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13473 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
13475 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
13476 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
13479 if ((mac_lo == 0) && (mac_hi == 0)) {
13480 *sc->mac_addr_str = 0;
13481 BLOGE(sc, "No Ethernet address programmed!\n");
13483 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
13484 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
13485 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
13486 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
13487 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
13488 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
13489 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
13490 "%02x:%02x:%02x:%02x:%02x:%02x",
13491 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
13492 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
13493 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
13494 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
13501 bxe_get_tunable_params(struct bxe_softc *sc)
13503 /* sanity checks */
13505 if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
13506 (bxe_interrupt_mode != INTR_MODE_MSI) &&
13507 (bxe_interrupt_mode != INTR_MODE_MSIX)) {
13508 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
13509 bxe_interrupt_mode = INTR_MODE_MSIX;
13512 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
13513 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
13514 bxe_queue_count = 0;
13517 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
13518 if (bxe_max_rx_bufs == 0) {
13519 bxe_max_rx_bufs = RX_BD_USABLE;
13521 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
13522 bxe_max_rx_bufs = 2048;
13526 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
13527 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
13528 bxe_hc_rx_ticks = 25;
13531 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
13532 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
13533 bxe_hc_tx_ticks = 50;
13536 if (bxe_max_aggregation_size == 0) {
13537 bxe_max_aggregation_size = TPA_AGG_SIZE;
13540 if (bxe_max_aggregation_size > 0xffff) {
13541 BLOGW(sc, "invalid max_aggregation_size (%d)\n",
13542 bxe_max_aggregation_size);
13543 bxe_max_aggregation_size = TPA_AGG_SIZE;
13546 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
13547 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
13551 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
13552 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
13553 bxe_autogreeen = 0;
13556 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
13557 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
13561 /* pull in user settings */
13563 sc->interrupt_mode = bxe_interrupt_mode;
13564 sc->max_rx_bufs = bxe_max_rx_bufs;
13565 sc->hc_rx_ticks = bxe_hc_rx_ticks;
13566 sc->hc_tx_ticks = bxe_hc_tx_ticks;
13567 sc->max_aggregation_size = bxe_max_aggregation_size;
13568 sc->mrrs = bxe_mrrs;
13569 sc->autogreeen = bxe_autogreeen;
13570 sc->udp_rss = bxe_udp_rss;
13572 if (bxe_interrupt_mode == INTR_MODE_INTX) {
13573 sc->num_queues = 1;
13574 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
13576 min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
13578 if (sc->num_queues > mp_ncpus) {
13579 sc->num_queues = mp_ncpus;
13583 BLOGD(sc, DBG_LOAD,
13586 "interrupt_mode=%d "
13591 "max_aggregation_size=%d "
13596 sc->interrupt_mode,
13601 sc->max_aggregation_size,
13608 bxe_media_detect(struct bxe_softc *sc)
13611 uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
13613 switch (sc->link_params.phy[phy_idx].media_type) {
13614 case ELINK_ETH_PHY_SFPP_10G_FIBER:
13615 case ELINK_ETH_PHY_XFP_FIBER:
13616 BLOGI(sc, "Found 10Gb Fiber media.\n");
13617 sc->media = IFM_10G_SR;
13618 port_type = PORT_FIBRE;
13620 case ELINK_ETH_PHY_SFP_1G_FIBER:
13621 BLOGI(sc, "Found 1Gb Fiber media.\n");
13622 sc->media = IFM_1000_SX;
13623 port_type = PORT_FIBRE;
13625 case ELINK_ETH_PHY_KR:
13626 case ELINK_ETH_PHY_CX4:
13627 BLOGI(sc, "Found 10GBase-CX4 media.\n");
13628 sc->media = IFM_10G_CX4;
13629 port_type = PORT_FIBRE;
13631 case ELINK_ETH_PHY_DA_TWINAX:
13632 BLOGI(sc, "Found 10Gb Twinax media.\n");
13633 sc->media = IFM_10G_TWINAX;
13634 port_type = PORT_DA;
13636 case ELINK_ETH_PHY_BASE_T:
13637 if (sc->link_params.speed_cap_mask[0] &
13638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
13639 BLOGI(sc, "Found 10GBase-T media.\n");
13640 sc->media = IFM_10G_T;
13641 port_type = PORT_TP;
13643 BLOGI(sc, "Found 1000Base-T media.\n");
13644 sc->media = IFM_1000_T;
13645 port_type = PORT_TP;
13648 case ELINK_ETH_PHY_NOT_PRESENT:
13649 BLOGI(sc, "Media not present.\n");
13651 port_type = PORT_OTHER;
13653 case ELINK_ETH_PHY_UNSPECIFIED:
13655 BLOGI(sc, "Unknown media!\n");
13657 port_type = PORT_OTHER;
13663 #define GET_FIELD(value, fname) \
13664 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
13665 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
13666 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
13669 bxe_get_igu_cam_info(struct bxe_softc *sc)
13671 int pfid = SC_FUNC(sc);
13674 uint8_t fid, igu_sb_cnt = 0;
13676 sc->igu_base_sb = 0xff;
13678 if (CHIP_INT_MODE_IS_BC(sc)) {
13679 int vn = SC_VN(sc);
13680 igu_sb_cnt = sc->igu_sb_cnt;
13681 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
13683 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
13684 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
13688 /* IGU in normal mode - read CAM */
13689 for (igu_sb_id = 0;
13690 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
13692 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
13693 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
13696 fid = IGU_FID(val);
13697 if ((fid & IGU_FID_ENCODE_IS_PF)) {
13698 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
13701 if (IGU_VEC(val) == 0) {
13702 /* default status block */
13703 sc->igu_dsb_id = igu_sb_id;
13705 if (sc->igu_base_sb == 0xff) {
13706 sc->igu_base_sb = igu_sb_id;
13714 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
13715 * that number of CAM entries will not be equal to the value advertised in
13716 * PCI. Driver should use the minimal value of both as the actual status
13719 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
13721 if (igu_sb_cnt == 0) {
13722 BLOGE(sc, "CAM configuration error\n");
13730 * Gather various information from the device config space, the device itself,
13731 * shmem, and the user input.
13734 bxe_get_device_info(struct bxe_softc *sc)
13739 /* Get the data for the device */
13740 sc->devinfo.vendor_id = pci_get_vendor(sc->dev);
13741 sc->devinfo.device_id = pci_get_device(sc->dev);
13742 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
13743 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
13745 /* get the chip revision (chip metal comes from pci config space) */
13746 sc->devinfo.chip_id =
13747 sc->link_params.chip_id =
13748 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
13749 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
13750 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
13751 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
13753 /* force 57811 according to MISC register */
13754 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
13755 if (CHIP_IS_57810(sc)) {
13756 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
13757 (sc->devinfo.chip_id & 0x0000ffff));
13758 } else if (CHIP_IS_57810_MF(sc)) {
13759 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
13760 (sc->devinfo.chip_id & 0x0000ffff));
13762 sc->devinfo.chip_id |= 0x1;
13765 BLOGD(sc, DBG_LOAD,
13766 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
13767 sc->devinfo.chip_id,
13768 ((sc->devinfo.chip_id >> 16) & 0xffff),
13769 ((sc->devinfo.chip_id >> 12) & 0xf),
13770 ((sc->devinfo.chip_id >> 4) & 0xff),
13771 ((sc->devinfo.chip_id >> 0) & 0xf));
13773 val = (REG_RD(sc, 0x2874) & 0x55);
13774 if ((sc->devinfo.chip_id & 0x1) ||
13775 (CHIP_IS_E1(sc) && val) ||
13776 (CHIP_IS_E1H(sc) && (val == 0x55))) {
13777 sc->flags |= BXE_ONE_PORT_FLAG;
13778 BLOGD(sc, DBG_LOAD, "single port device\n");
13781 /* set the doorbell size */
13782 sc->doorbell_size = (1 << BXE_DB_SHIFT);
13784 /* determine whether the device is in 2 port or 4 port mode */
13785 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
13786 if (CHIP_IS_E2E3(sc)) {
13788 * Read port4mode_en_ovwr[0]:
13789 * If 1, four port mode is in port4mode_en_ovwr[1].
13790 * If 0, four port mode is in port4mode_en[0].
13792 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
13794 val = ((val >> 1) & 1);
13796 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
13799 sc->devinfo.chip_port_mode =
13800 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
13802 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
13805 /* get the function and path info for the device */
13806 bxe_get_function_num(sc);
13808 /* get the shared memory base address */
13809 sc->devinfo.shmem_base =
13810 sc->link_params.shmem_base =
13811 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
13812 sc->devinfo.shmem2_base =
13813 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
13814 MISC_REG_GENERIC_CR_0));
13816 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
13817 sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
13819 if (!sc->devinfo.shmem_base) {
13820 /* this should ONLY prevent upcoming shmem reads */
13821 BLOGI(sc, "MCP not active\n");
13822 sc->flags |= BXE_NO_MCP_FLAG;
13826 /* make sure the shared memory contents are valid */
13827 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
13828 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
13829 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
13830 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
13833 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
13835 /* get the bootcode version */
13836 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
13837 snprintf(sc->devinfo.bc_ver_str,
13838 sizeof(sc->devinfo.bc_ver_str),
13840 ((sc->devinfo.bc_ver >> 24) & 0xff),
13841 ((sc->devinfo.bc_ver >> 16) & 0xff),
13842 ((sc->devinfo.bc_ver >> 8) & 0xff));
13843 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
13845 /* get the bootcode shmem address */
13846 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
13847 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
13849 /* clean indirect addresses as they're not used */
13850 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
13852 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
13853 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
13854 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
13855 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
13856 if (CHIP_IS_E1x(sc)) {
13857 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
13858 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
13859 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
13860 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
13864 * Enable internal target-read (in case we are probed after PF
13865 * FLR). Must be done prior to any BAR read access. Only for
13868 if (!CHIP_IS_E1x(sc)) {
13869 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
13873 /* get the nvram size */
13874 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
13875 sc->devinfo.flash_size =
13876 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
13877 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
13879 /* get PCI capabilites */
13880 bxe_probe_pci_caps(sc);
13882 bxe_set_power_state(sc, PCI_PM_D0);
13884 /* get various configuration parameters from shmem */
13885 bxe_get_shmem_info(sc);
13887 if (sc->devinfo.pcie_msix_cap_reg != 0) {
13888 val = pci_read_config(sc->dev,
13889 (sc->devinfo.pcie_msix_cap_reg +
13892 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
13894 sc->igu_sb_cnt = 1;
13897 sc->igu_base_addr = BAR_IGU_INTMEM;
13899 /* initialize IGU parameters */
13900 if (CHIP_IS_E1x(sc)) {
13901 sc->devinfo.int_block = INT_BLOCK_HC;
13902 sc->igu_dsb_id = DEF_SB_IGU_ID;
13903 sc->igu_base_sb = 0;
13905 sc->devinfo.int_block = INT_BLOCK_IGU;
13907 /* do not allow device reset during IGU info preocessing */
13908 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13910 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
13912 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
13915 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
13917 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
13918 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
13919 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
13921 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
13926 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
13927 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
13928 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13933 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
13934 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
13935 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
13937 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
13940 rc = bxe_get_igu_cam_info(sc);
13942 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
13950 * Get base FW non-default (fast path) status block ID. This value is
13951 * used to initialize the fw_sb_id saved on the fp/queue structure to
13952 * determine the id used by the FW.
13954 if (CHIP_IS_E1x(sc)) {
13955 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
13958 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
13959 * the same queue are indicated on the same IGU SB). So we prefer
13960 * FW and IGU SBs to be the same value.
13962 sc->base_fw_ndsb = sc->igu_base_sb;
13965 BLOGD(sc, DBG_LOAD,
13966 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
13967 sc->igu_dsb_id, sc->igu_base_sb,
13968 sc->igu_sb_cnt, sc->base_fw_ndsb);
13970 elink_phy_probe(&sc->link_params);
13976 bxe_link_settings_supported(struct bxe_softc *sc,
13977 uint32_t switch_cfg)
13979 uint32_t cfg_size = 0;
13981 uint8_t port = SC_PORT(sc);
13983 /* aggregation of supported attributes of all external phys */
13984 sc->port.supported[0] = 0;
13985 sc->port.supported[1] = 0;
13987 switch (sc->link_params.num_phys) {
13989 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
13993 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
13997 if (sc->link_params.multi_phy_config &
13998 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
13999 sc->port.supported[1] =
14000 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14001 sc->port.supported[0] =
14002 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14004 sc->port.supported[0] =
14005 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14006 sc->port.supported[1] =
14007 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14013 if (!(sc->port.supported[0] || sc->port.supported[1])) {
14014 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14016 dev_info.port_hw_config[port].external_phy_config),
14018 dev_info.port_hw_config[port].external_phy_config2));
14022 if (CHIP_IS_E3(sc))
14023 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14025 switch (switch_cfg) {
14026 case ELINK_SWITCH_CFG_1G:
14027 sc->port.phy_addr =
14028 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14030 case ELINK_SWITCH_CFG_10G:
14031 sc->port.phy_addr =
14032 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14035 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14036 sc->port.link_config[0]);
14041 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14043 /* mask what we support according to speed_cap_mask per configuration */
14044 for (idx = 0; idx < cfg_size; idx++) {
14045 if (!(sc->link_params.speed_cap_mask[idx] &
14046 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14047 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14050 if (!(sc->link_params.speed_cap_mask[idx] &
14051 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14052 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14055 if (!(sc->link_params.speed_cap_mask[idx] &
14056 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14057 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14060 if (!(sc->link_params.speed_cap_mask[idx] &
14061 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14062 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14065 if (!(sc->link_params.speed_cap_mask[idx] &
14066 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14067 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14070 if (!(sc->link_params.speed_cap_mask[idx] &
14071 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14072 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14075 if (!(sc->link_params.speed_cap_mask[idx] &
14076 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14077 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14080 if (!(sc->link_params.speed_cap_mask[idx] &
14081 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14082 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14086 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14087 sc->port.supported[0], sc->port.supported[1]);
14088 ELINK_DEBUG_P2(sc, "PHY supported 0=0x%08x 1=0x%08x\n",
14089 sc->port.supported[0], sc->port.supported[1]);
14093 bxe_link_settings_requested(struct bxe_softc *sc)
14095 uint32_t link_config;
14097 uint32_t cfg_size = 0;
14099 sc->port.advertising[0] = 0;
14100 sc->port.advertising[1] = 0;
14102 switch (sc->link_params.num_phys) {
14112 for (idx = 0; idx < cfg_size; idx++) {
14113 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14114 link_config = sc->port.link_config[idx];
14116 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14117 case PORT_FEATURE_LINK_SPEED_AUTO:
14118 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14119 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14120 sc->port.advertising[idx] |= sc->port.supported[idx];
14121 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14122 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14123 sc->port.advertising[idx] |=
14124 (ELINK_SUPPORTED_100baseT_Half |
14125 ELINK_SUPPORTED_100baseT_Full);
14127 /* force 10G, no AN */
14128 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14129 sc->port.advertising[idx] |=
14130 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14135 case PORT_FEATURE_LINK_SPEED_10M_FULL:
14136 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14137 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14138 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14141 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14142 "speed_cap_mask=0x%08x\n",
14143 link_config, sc->link_params.speed_cap_mask[idx]);
14148 case PORT_FEATURE_LINK_SPEED_10M_HALF:
14149 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14150 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14151 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14152 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14154 ELINK_DEBUG_P1(sc, "driver requesting DUPLEX_HALF req_duplex = %x!\n",
14155 sc->link_params.req_duplex[idx]);
14157 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14158 "speed_cap_mask=0x%08x\n",
14159 link_config, sc->link_params.speed_cap_mask[idx]);
14164 case PORT_FEATURE_LINK_SPEED_100M_FULL:
14165 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14166 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14167 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14170 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14171 "speed_cap_mask=0x%08x\n",
14172 link_config, sc->link_params.speed_cap_mask[idx]);
14177 case PORT_FEATURE_LINK_SPEED_100M_HALF:
14178 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14179 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14180 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14181 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14184 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14185 "speed_cap_mask=0x%08x\n",
14186 link_config, sc->link_params.speed_cap_mask[idx]);
14191 case PORT_FEATURE_LINK_SPEED_1G:
14192 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14193 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14194 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14197 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14198 "speed_cap_mask=0x%08x\n",
14199 link_config, sc->link_params.speed_cap_mask[idx]);
14204 case PORT_FEATURE_LINK_SPEED_2_5G:
14205 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14206 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14207 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14210 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14211 "speed_cap_mask=0x%08x\n",
14212 link_config, sc->link_params.speed_cap_mask[idx]);
14217 case PORT_FEATURE_LINK_SPEED_10G_CX4:
14218 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14219 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14220 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14223 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14224 "speed_cap_mask=0x%08x\n",
14225 link_config, sc->link_params.speed_cap_mask[idx]);
14230 case PORT_FEATURE_LINK_SPEED_20G:
14231 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14235 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14236 "speed_cap_mask=0x%08x\n",
14237 link_config, sc->link_params.speed_cap_mask[idx]);
14238 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14239 sc->port.advertising[idx] = sc->port.supported[idx];
14243 sc->link_params.req_flow_ctrl[idx] =
14244 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14246 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14247 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14248 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14250 bxe_set_requested_fc(sc);
14254 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14255 "req_flow_ctrl=0x%x advertising=0x%x\n",
14256 sc->link_params.req_line_speed[idx],
14257 sc->link_params.req_duplex[idx],
14258 sc->link_params.req_flow_ctrl[idx],
14259 sc->port.advertising[idx]);
14260 ELINK_DEBUG_P3(sc, "req_line_speed=%d req_duplex=%d "
14261 "advertising=0x%x\n",
14262 sc->link_params.req_line_speed[idx],
14263 sc->link_params.req_duplex[idx],
14264 sc->port.advertising[idx]);
14269 bxe_get_phy_info(struct bxe_softc *sc)
14271 uint8_t port = SC_PORT(sc);
14272 uint32_t config = sc->port.config;
14275 /* shmem data already read in bxe_get_shmem_info() */
14277 ELINK_DEBUG_P3(sc, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14278 "link_config0=0x%08x\n",
14279 sc->link_params.lane_config,
14280 sc->link_params.speed_cap_mask[0],
14281 sc->port.link_config[0]);
14284 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14285 bxe_link_settings_requested(sc);
14287 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14288 sc->link_params.feature_config_flags |=
14289 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14290 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14291 sc->link_params.feature_config_flags &=
14292 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14293 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14294 sc->link_params.feature_config_flags |=
14295 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14298 /* configure link feature according to nvram value */
14300 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14301 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14302 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14303 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14304 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14305 ELINK_EEE_MODE_ENABLE_LPI |
14306 ELINK_EEE_MODE_OUTPUT_TIME);
14308 sc->link_params.eee_mode = 0;
14311 /* get the media type */
14312 bxe_media_detect(sc);
14313 ELINK_DEBUG_P1(sc, "detected media type\n", sc->media);
14317 bxe_get_params(struct bxe_softc *sc)
14319 /* get user tunable params */
14320 bxe_get_tunable_params(sc);
14322 /* select the RX and TX ring sizes */
14323 sc->tx_ring_size = TX_BD_USABLE;
14324 sc->rx_ring_size = RX_BD_USABLE;
14326 /* XXX disable WoL */
14331 bxe_set_modes_bitmap(struct bxe_softc *sc)
14333 uint32_t flags = 0;
14335 if (CHIP_REV_IS_FPGA(sc)) {
14336 SET_FLAGS(flags, MODE_FPGA);
14337 } else if (CHIP_REV_IS_EMUL(sc)) {
14338 SET_FLAGS(flags, MODE_EMUL);
14340 SET_FLAGS(flags, MODE_ASIC);
14343 if (CHIP_IS_MODE_4_PORT(sc)) {
14344 SET_FLAGS(flags, MODE_PORT4);
14346 SET_FLAGS(flags, MODE_PORT2);
14349 if (CHIP_IS_E2(sc)) {
14350 SET_FLAGS(flags, MODE_E2);
14351 } else if (CHIP_IS_E3(sc)) {
14352 SET_FLAGS(flags, MODE_E3);
14353 if (CHIP_REV(sc) == CHIP_REV_Ax) {
14354 SET_FLAGS(flags, MODE_E3_A0);
14355 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14356 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14361 SET_FLAGS(flags, MODE_MF);
14362 switch (sc->devinfo.mf_info.mf_mode) {
14363 case MULTI_FUNCTION_SD:
14364 SET_FLAGS(flags, MODE_MF_SD);
14366 case MULTI_FUNCTION_SI:
14367 SET_FLAGS(flags, MODE_MF_SI);
14369 case MULTI_FUNCTION_AFEX:
14370 SET_FLAGS(flags, MODE_MF_AFEX);
14374 SET_FLAGS(flags, MODE_SF);
14377 #if defined(__LITTLE_ENDIAN)
14378 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14379 #else /* __BIG_ENDIAN */
14380 SET_FLAGS(flags, MODE_BIG_ENDIAN);
14383 INIT_MODE_FLAGS(sc) = flags;
14387 bxe_alloc_hsi_mem(struct bxe_softc *sc)
14389 struct bxe_fastpath *fp;
14390 bus_addr_t busaddr;
14391 int max_agg_queues;
14393 bus_size_t max_size;
14394 bus_size_t max_seg_size;
14399 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14401 /* allocate the parent bus DMA tag */
14402 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14404 0, /* boundary limit */
14405 BUS_SPACE_MAXADDR, /* restricted low */
14406 BUS_SPACE_MAXADDR, /* restricted hi */
14407 NULL, /* addr filter() */
14408 NULL, /* addr filter() arg */
14409 BUS_SPACE_MAXSIZE_32BIT, /* max map size */
14410 BUS_SPACE_UNRESTRICTED, /* num discontinuous */
14411 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
14414 NULL, /* lock() arg */
14415 &sc->parent_dma_tag); /* returned dma tag */
14417 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14421 /************************/
14422 /* DEFAULT STATUS BLOCK */
14423 /************************/
14425 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14426 &sc->def_sb_dma, "default status block") != 0) {
14428 bus_dma_tag_destroy(sc->parent_dma_tag);
14432 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14438 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14439 &sc->eq_dma, "event queue") != 0) {
14441 bxe_dma_free(sc, &sc->def_sb_dma);
14443 bus_dma_tag_destroy(sc->parent_dma_tag);
14447 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14453 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14454 &sc->sp_dma, "slow path") != 0) {
14456 bxe_dma_free(sc, &sc->eq_dma);
14458 bxe_dma_free(sc, &sc->def_sb_dma);
14460 bus_dma_tag_destroy(sc->parent_dma_tag);
14464 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
14466 /*******************/
14467 /* SLOW PATH QUEUE */
14468 /*******************/
14470 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14471 &sc->spq_dma, "slow path queue") != 0) {
14473 bxe_dma_free(sc, &sc->sp_dma);
14475 bxe_dma_free(sc, &sc->eq_dma);
14477 bxe_dma_free(sc, &sc->def_sb_dma);
14479 bus_dma_tag_destroy(sc->parent_dma_tag);
14483 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
14485 /***************************/
14486 /* FW DECOMPRESSION BUFFER */
14487 /***************************/
14489 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
14490 "fw decompression buffer") != 0) {
14492 bxe_dma_free(sc, &sc->spq_dma);
14494 bxe_dma_free(sc, &sc->sp_dma);
14496 bxe_dma_free(sc, &sc->eq_dma);
14498 bxe_dma_free(sc, &sc->def_sb_dma);
14500 bus_dma_tag_destroy(sc->parent_dma_tag);
14504 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
14507 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
14509 bxe_dma_free(sc, &sc->gz_buf_dma);
14511 bxe_dma_free(sc, &sc->spq_dma);
14513 bxe_dma_free(sc, &sc->sp_dma);
14515 bxe_dma_free(sc, &sc->eq_dma);
14517 bxe_dma_free(sc, &sc->def_sb_dma);
14519 bus_dma_tag_destroy(sc->parent_dma_tag);
14527 /* allocate DMA memory for each fastpath structure */
14528 for (i = 0; i < sc->num_queues; i++) {
14533 /*******************/
14534 /* FP STATUS BLOCK */
14535 /*******************/
14537 snprintf(buf, sizeof(buf), "fp %d status block", i);
14538 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
14539 &fp->sb_dma, buf) != 0) {
14540 /* XXX unwind and free previous fastpath allocations */
14541 BLOGE(sc, "Failed to alloc %s\n", buf);
14544 if (CHIP_IS_E2E3(sc)) {
14545 fp->status_block.e2_sb =
14546 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
14548 fp->status_block.e1x_sb =
14549 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
14553 /******************/
14554 /* FP TX BD CHAIN */
14555 /******************/
14557 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
14558 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
14559 &fp->tx_dma, buf) != 0) {
14560 /* XXX unwind and free previous fastpath allocations */
14561 BLOGE(sc, "Failed to alloc %s\n", buf);
14564 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
14567 /* link together the tx bd chain pages */
14568 for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
14569 /* index into the tx bd chain array to last entry per page */
14570 struct eth_tx_next_bd *tx_next_bd =
14571 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
14572 /* point to the next page and wrap from last page */
14573 busaddr = (fp->tx_dma.paddr +
14574 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
14575 tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
14576 tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
14579 /******************/
14580 /* FP RX BD CHAIN */
14581 /******************/
14583 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
14584 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
14585 &fp->rx_dma, buf) != 0) {
14586 /* XXX unwind and free previous fastpath allocations */
14587 BLOGE(sc, "Failed to alloc %s\n", buf);
14590 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
14593 /* link together the rx bd chain pages */
14594 for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
14595 /* index into the rx bd chain array to last entry per page */
14596 struct eth_rx_bd *rx_bd =
14597 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
14598 /* point to the next page and wrap from last page */
14599 busaddr = (fp->rx_dma.paddr +
14600 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
14601 rx_bd->addr_hi = htole32(U64_HI(busaddr));
14602 rx_bd->addr_lo = htole32(U64_LO(busaddr));
14605 /*******************/
14606 /* FP RX RCQ CHAIN */
14607 /*******************/
14609 snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
14610 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
14611 &fp->rcq_dma, buf) != 0) {
14612 /* XXX unwind and free previous fastpath allocations */
14613 BLOGE(sc, "Failed to alloc %s\n", buf);
14616 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
14619 /* link together the rcq chain pages */
14620 for (j = 1; j <= RCQ_NUM_PAGES; j++) {
14621 /* index into the rcq chain array to last entry per page */
14622 struct eth_rx_cqe_next_page *rx_cqe_next =
14623 (struct eth_rx_cqe_next_page *)
14624 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
14625 /* point to the next page and wrap from last page */
14626 busaddr = (fp->rcq_dma.paddr +
14627 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
14628 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
14629 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
14632 /*******************/
14633 /* FP RX SGE CHAIN */
14634 /*******************/
14636 snprintf(buf, sizeof(buf), "fp %d sge chain", i);
14637 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
14638 &fp->rx_sge_dma, buf) != 0) {
14639 /* XXX unwind and free previous fastpath allocations */
14640 BLOGE(sc, "Failed to alloc %s\n", buf);
14643 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
14646 /* link together the sge chain pages */
14647 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
14648 /* index into the rcq chain array to last entry per page */
14649 struct eth_rx_sge *rx_sge =
14650 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
14651 /* point to the next page and wrap from last page */
14652 busaddr = (fp->rx_sge_dma.paddr +
14653 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
14654 rx_sge->addr_hi = htole32(U64_HI(busaddr));
14655 rx_sge->addr_lo = htole32(U64_LO(busaddr));
14658 /***********************/
14659 /* FP TX MBUF DMA MAPS */
14660 /***********************/
14662 /* set required sizes before mapping to conserve resources */
14663 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
14664 max_size = BXE_TSO_MAX_SIZE;
14665 max_segments = BXE_TSO_MAX_SEGMENTS;
14666 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
14668 max_size = (MCLBYTES * BXE_MAX_SEGMENTS);
14669 max_segments = BXE_MAX_SEGMENTS;
14670 max_seg_size = MCLBYTES;
14673 /* create a dma tag for the tx mbufs */
14674 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14676 0, /* boundary limit */
14677 BUS_SPACE_MAXADDR, /* restricted low */
14678 BUS_SPACE_MAXADDR, /* restricted hi */
14679 NULL, /* addr filter() */
14680 NULL, /* addr filter() arg */
14681 max_size, /* max map size */
14682 max_segments, /* num discontinuous */
14683 max_seg_size, /* max seg size */
14686 NULL, /* lock() arg */
14687 &fp->tx_mbuf_tag); /* returned dma tag */
14689 /* XXX unwind and free previous fastpath allocations */
14690 BLOGE(sc, "Failed to create dma tag for "
14691 "'fp %d tx mbufs' (%d)\n", i, rc);
14695 /* create dma maps for each of the tx mbuf clusters */
14696 for (j = 0; j < TX_BD_TOTAL; j++) {
14697 if (bus_dmamap_create(fp->tx_mbuf_tag,
14699 &fp->tx_mbuf_chain[j].m_map)) {
14700 /* XXX unwind and free previous fastpath allocations */
14701 BLOGE(sc, "Failed to create dma map for "
14702 "'fp %d tx mbuf %d' (%d)\n", i, j, rc);
14707 /***********************/
14708 /* FP RX MBUF DMA MAPS */
14709 /***********************/
14711 /* create a dma tag for the rx mbufs */
14712 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14714 0, /* boundary limit */
14715 BUS_SPACE_MAXADDR, /* restricted low */
14716 BUS_SPACE_MAXADDR, /* restricted hi */
14717 NULL, /* addr filter() */
14718 NULL, /* addr filter() arg */
14719 MJUM9BYTES, /* max map size */
14720 1, /* num discontinuous */
14721 MJUM9BYTES, /* max seg size */
14724 NULL, /* lock() arg */
14725 &fp->rx_mbuf_tag); /* returned dma tag */
14727 /* XXX unwind and free previous fastpath allocations */
14728 BLOGE(sc, "Failed to create dma tag for "
14729 "'fp %d rx mbufs' (%d)\n", i, rc);
14733 /* create dma maps for each of the rx mbuf clusters */
14734 for (j = 0; j < RX_BD_TOTAL; j++) {
14735 if (bus_dmamap_create(fp->rx_mbuf_tag,
14737 &fp->rx_mbuf_chain[j].m_map)) {
14738 /* XXX unwind and free previous fastpath allocations */
14739 BLOGE(sc, "Failed to create dma map for "
14740 "'fp %d rx mbuf %d' (%d)\n", i, j, rc);
14745 /* create dma map for the spare rx mbuf cluster */
14746 if (bus_dmamap_create(fp->rx_mbuf_tag,
14748 &fp->rx_mbuf_spare_map)) {
14749 /* XXX unwind and free previous fastpath allocations */
14750 BLOGE(sc, "Failed to create dma map for "
14751 "'fp %d spare rx mbuf' (%d)\n", i, rc);
14755 /***************************/
14756 /* FP RX SGE MBUF DMA MAPS */
14757 /***************************/
14759 /* create a dma tag for the rx sge mbufs */
14760 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
14762 0, /* boundary limit */
14763 BUS_SPACE_MAXADDR, /* restricted low */
14764 BUS_SPACE_MAXADDR, /* restricted hi */
14765 NULL, /* addr filter() */
14766 NULL, /* addr filter() arg */
14767 BCM_PAGE_SIZE, /* max map size */
14768 1, /* num discontinuous */
14769 BCM_PAGE_SIZE, /* max seg size */
14772 NULL, /* lock() arg */
14773 &fp->rx_sge_mbuf_tag); /* returned dma tag */
14775 /* XXX unwind and free previous fastpath allocations */
14776 BLOGE(sc, "Failed to create dma tag for "
14777 "'fp %d rx sge mbufs' (%d)\n", i, rc);
14781 /* create dma maps for the rx sge mbuf clusters */
14782 for (j = 0; j < RX_SGE_TOTAL; j++) {
14783 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14785 &fp->rx_sge_mbuf_chain[j].m_map)) {
14786 /* XXX unwind and free previous fastpath allocations */
14787 BLOGE(sc, "Failed to create dma map for "
14788 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc);
14793 /* create dma map for the spare rx sge mbuf cluster */
14794 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
14796 &fp->rx_sge_mbuf_spare_map)) {
14797 /* XXX unwind and free previous fastpath allocations */
14798 BLOGE(sc, "Failed to create dma map for "
14799 "'fp %d spare rx sge mbuf' (%d)\n", i, rc);
14803 /***************************/
14804 /* FP RX TPA MBUF DMA MAPS */
14805 /***************************/
14807 /* create dma maps for the rx tpa mbuf clusters */
14808 max_agg_queues = MAX_AGG_QS(sc);
14810 for (j = 0; j < max_agg_queues; j++) {
14811 if (bus_dmamap_create(fp->rx_mbuf_tag,
14813 &fp->rx_tpa_info[j].bd.m_map)) {
14814 /* XXX unwind and free previous fastpath allocations */
14815 BLOGE(sc, "Failed to create dma map for "
14816 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc);
14821 /* create dma map for the spare rx tpa mbuf cluster */
14822 if (bus_dmamap_create(fp->rx_mbuf_tag,
14824 &fp->rx_tpa_info_mbuf_spare_map)) {
14825 /* XXX unwind and free previous fastpath allocations */
14826 BLOGE(sc, "Failed to create dma map for "
14827 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc);
14831 bxe_init_sge_ring_bit_mask(fp);
14838 bxe_free_hsi_mem(struct bxe_softc *sc)
14840 struct bxe_fastpath *fp;
14841 int max_agg_queues;
14844 if (sc->parent_dma_tag == NULL) {
14845 return; /* assume nothing was allocated */
14848 for (i = 0; i < sc->num_queues; i++) {
14851 /*******************/
14852 /* FP STATUS BLOCK */
14853 /*******************/
14855 bxe_dma_free(sc, &fp->sb_dma);
14856 memset(&fp->status_block, 0, sizeof(fp->status_block));
14858 /******************/
14859 /* FP TX BD CHAIN */
14860 /******************/
14862 bxe_dma_free(sc, &fp->tx_dma);
14863 fp->tx_chain = NULL;
14865 /******************/
14866 /* FP RX BD CHAIN */
14867 /******************/
14869 bxe_dma_free(sc, &fp->rx_dma);
14870 fp->rx_chain = NULL;
14872 /*******************/
14873 /* FP RX RCQ CHAIN */
14874 /*******************/
14876 bxe_dma_free(sc, &fp->rcq_dma);
14877 fp->rcq_chain = NULL;
14879 /*******************/
14880 /* FP RX SGE CHAIN */
14881 /*******************/
14883 bxe_dma_free(sc, &fp->rx_sge_dma);
14884 fp->rx_sge_chain = NULL;
14886 /***********************/
14887 /* FP TX MBUF DMA MAPS */
14888 /***********************/
14890 if (fp->tx_mbuf_tag != NULL) {
14891 for (j = 0; j < TX_BD_TOTAL; j++) {
14892 if (fp->tx_mbuf_chain[j].m_map != NULL) {
14893 bus_dmamap_unload(fp->tx_mbuf_tag,
14894 fp->tx_mbuf_chain[j].m_map);
14895 bus_dmamap_destroy(fp->tx_mbuf_tag,
14896 fp->tx_mbuf_chain[j].m_map);
14900 bus_dma_tag_destroy(fp->tx_mbuf_tag);
14901 fp->tx_mbuf_tag = NULL;
14904 /***********************/
14905 /* FP RX MBUF DMA MAPS */
14906 /***********************/
14908 if (fp->rx_mbuf_tag != NULL) {
14909 for (j = 0; j < RX_BD_TOTAL; j++) {
14910 if (fp->rx_mbuf_chain[j].m_map != NULL) {
14911 bus_dmamap_unload(fp->rx_mbuf_tag,
14912 fp->rx_mbuf_chain[j].m_map);
14913 bus_dmamap_destroy(fp->rx_mbuf_tag,
14914 fp->rx_mbuf_chain[j].m_map);
14918 if (fp->rx_mbuf_spare_map != NULL) {
14919 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14920 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
14923 /***************************/
14924 /* FP RX TPA MBUF DMA MAPS */
14925 /***************************/
14927 max_agg_queues = MAX_AGG_QS(sc);
14929 for (j = 0; j < max_agg_queues; j++) {
14930 if (fp->rx_tpa_info[j].bd.m_map != NULL) {
14931 bus_dmamap_unload(fp->rx_mbuf_tag,
14932 fp->rx_tpa_info[j].bd.m_map);
14933 bus_dmamap_destroy(fp->rx_mbuf_tag,
14934 fp->rx_tpa_info[j].bd.m_map);
14938 if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
14939 bus_dmamap_unload(fp->rx_mbuf_tag,
14940 fp->rx_tpa_info_mbuf_spare_map);
14941 bus_dmamap_destroy(fp->rx_mbuf_tag,
14942 fp->rx_tpa_info_mbuf_spare_map);
14945 bus_dma_tag_destroy(fp->rx_mbuf_tag);
14946 fp->rx_mbuf_tag = NULL;
14949 /***************************/
14950 /* FP RX SGE MBUF DMA MAPS */
14951 /***************************/
14953 if (fp->rx_sge_mbuf_tag != NULL) {
14954 for (j = 0; j < RX_SGE_TOTAL; j++) {
14955 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
14956 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
14957 fp->rx_sge_mbuf_chain[j].m_map);
14958 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
14959 fp->rx_sge_mbuf_chain[j].m_map);
14963 if (fp->rx_sge_mbuf_spare_map != NULL) {
14964 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
14965 fp->rx_sge_mbuf_spare_map);
14966 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
14967 fp->rx_sge_mbuf_spare_map);
14970 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
14971 fp->rx_sge_mbuf_tag = NULL;
14975 /***************************/
14976 /* FW DECOMPRESSION BUFFER */
14977 /***************************/
14979 bxe_dma_free(sc, &sc->gz_buf_dma);
14981 free(sc->gz_strm, M_DEVBUF);
14982 sc->gz_strm = NULL;
14984 /*******************/
14985 /* SLOW PATH QUEUE */
14986 /*******************/
14988 bxe_dma_free(sc, &sc->spq_dma);
14995 bxe_dma_free(sc, &sc->sp_dma);
15002 bxe_dma_free(sc, &sc->eq_dma);
15005 /************************/
15006 /* DEFAULT STATUS BLOCK */
15007 /************************/
15009 bxe_dma_free(sc, &sc->def_sb_dma);
15012 bus_dma_tag_destroy(sc->parent_dma_tag);
15013 sc->parent_dma_tag = NULL;
15017 * Previous driver DMAE transaction may have occurred when pre-boot stage
15018 * ended and boot began. This would invalidate the addresses of the
15019 * transaction, resulting in was-error bit set in the PCI causing all
15020 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15021 * the interrupt which detected this from the pglueb and the was-done bit
15024 bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15028 if (!CHIP_IS_E1x(sc)) {
15029 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15030 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15031 BLOGD(sc, DBG_LOAD,
15032 "Clearing 'was-error' bit that was set in pglueb");
15033 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15039 bxe_prev_mcp_done(struct bxe_softc *sc)
15041 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15042 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15044 BLOGE(sc, "MCP response failure, aborting\n");
15051 static struct bxe_prev_list_node *
15052 bxe_prev_path_get_entry(struct bxe_softc *sc)
15054 struct bxe_prev_list_node *tmp;
15056 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15057 if ((sc->pcie_bus == tmp->bus) &&
15058 (sc->pcie_device == tmp->slot) &&
15059 (SC_PATH(sc) == tmp->path)) {
15068 bxe_prev_is_path_marked(struct bxe_softc *sc)
15070 struct bxe_prev_list_node *tmp;
15073 mtx_lock(&bxe_prev_mtx);
15075 tmp = bxe_prev_path_get_entry(sc);
15078 BLOGD(sc, DBG_LOAD,
15079 "Path %d/%d/%d was marked by AER\n",
15080 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15083 BLOGD(sc, DBG_LOAD,
15084 "Path %d/%d/%d was already cleaned from previous drivers\n",
15085 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15089 mtx_unlock(&bxe_prev_mtx);
15095 bxe_prev_mark_path(struct bxe_softc *sc,
15096 uint8_t after_undi)
15098 struct bxe_prev_list_node *tmp;
15100 mtx_lock(&bxe_prev_mtx);
15102 /* Check whether the entry for this path already exists */
15103 tmp = bxe_prev_path_get_entry(sc);
15106 BLOGD(sc, DBG_LOAD,
15107 "Re-marking AER in path %d/%d/%d\n",
15108 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15110 BLOGD(sc, DBG_LOAD,
15111 "Removing AER indication from path %d/%d/%d\n",
15112 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15116 mtx_unlock(&bxe_prev_mtx);
15120 mtx_unlock(&bxe_prev_mtx);
15122 /* Create an entry for this path and add it */
15123 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15124 (M_NOWAIT | M_ZERO));
15126 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15130 tmp->bus = sc->pcie_bus;
15131 tmp->slot = sc->pcie_device;
15132 tmp->path = SC_PATH(sc);
15134 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15136 mtx_lock(&bxe_prev_mtx);
15138 BLOGD(sc, DBG_LOAD,
15139 "Marked path %d/%d/%d - finished previous unload\n",
15140 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15141 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15143 mtx_unlock(&bxe_prev_mtx);
15149 bxe_do_flr(struct bxe_softc *sc)
15153 /* only E2 and onwards support FLR */
15154 if (CHIP_IS_E1x(sc)) {
15155 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15159 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15160 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15161 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15162 sc->devinfo.bc_ver);
15166 /* Wait for Transaction Pending bit clean */
15167 for (i = 0; i < 4; i++) {
15169 DELAY(((1 << (i - 1)) * 100) * 1000);
15172 if (!bxe_is_pcie_pending(sc)) {
15177 BLOGE(sc, "PCIE transaction is not cleared, "
15178 "proceeding with reset anyway\n");
15182 BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15183 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15188 struct bxe_mac_vals {
15189 uint32_t xmac_addr;
15191 uint32_t emac_addr;
15193 uint32_t umac_addr;
15195 uint32_t bmac_addr;
15196 uint32_t bmac_val[2];
15200 bxe_prev_unload_close_mac(struct bxe_softc *sc,
15201 struct bxe_mac_vals *vals)
15203 uint32_t val, base_addr, offset, mask, reset_reg;
15204 uint8_t mac_stopped = FALSE;
15205 uint8_t port = SC_PORT(sc);
15206 uint32_t wb_data[2];
15208 /* reset addresses as they also mark which values were changed */
15209 vals->bmac_addr = 0;
15210 vals->umac_addr = 0;
15211 vals->xmac_addr = 0;
15212 vals->emac_addr = 0;
15214 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15216 if (!CHIP_IS_E3(sc)) {
15217 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15218 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15219 if ((mask & reset_reg) && val) {
15220 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15221 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15222 : NIG_REG_INGRESS_BMAC0_MEM;
15223 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15224 : BIGMAC_REGISTER_BMAC_CONTROL;
15227 * use rd/wr since we cannot use dmae. This is safe
15228 * since MCP won't access the bus due to the request
15229 * to unload, and no function on the path can be
15230 * loaded at this time.
15232 wb_data[0] = REG_RD(sc, base_addr + offset);
15233 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15234 vals->bmac_addr = base_addr + offset;
15235 vals->bmac_val[0] = wb_data[0];
15236 vals->bmac_val[1] = wb_data[1];
15237 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15238 REG_WR(sc, vals->bmac_addr, wb_data[0]);
15239 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15242 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15243 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15244 vals->emac_val = REG_RD(sc, vals->emac_addr);
15245 REG_WR(sc, vals->emac_addr, 0);
15246 mac_stopped = TRUE;
15248 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15249 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15250 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15251 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15252 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15253 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15254 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15255 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15256 REG_WR(sc, vals->xmac_addr, 0);
15257 mac_stopped = TRUE;
15260 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15261 if (mask & reset_reg) {
15262 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15263 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15264 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15265 vals->umac_val = REG_RD(sc, vals->umac_addr);
15266 REG_WR(sc, vals->umac_addr, 0);
15267 mac_stopped = TRUE;
15276 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15277 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15278 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15279 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15282 bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15287 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15289 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15290 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15292 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15293 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15295 BLOGD(sc, DBG_LOAD,
15296 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15301 bxe_prev_unload_common(struct bxe_softc *sc)
15303 uint32_t reset_reg, tmp_reg = 0, rc;
15304 uint8_t prev_undi = FALSE;
15305 struct bxe_mac_vals mac_vals;
15306 uint32_t timer_count = 1000;
15310 * It is possible a previous function received 'common' answer,
15311 * but hasn't loaded yet, therefore creating a scenario of
15312 * multiple functions receiving 'common' on the same path.
15314 BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15316 memset(&mac_vals, 0, sizeof(mac_vals));
15318 if (bxe_prev_is_path_marked(sc)) {
15319 return (bxe_prev_mcp_done(sc));
15322 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15324 /* Reset should be performed after BRB is emptied */
15325 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15326 /* Close the MAC Rx to prevent BRB from filling up */
15327 bxe_prev_unload_close_mac(sc, &mac_vals);
15329 /* close LLH filters towards the BRB */
15330 elink_set_rx_filter(&sc->link_params, 0);
15333 * Check if the UNDI driver was previously loaded.
15334 * UNDI driver initializes CID offset for normal bell to 0x7
15336 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15337 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15338 if (tmp_reg == 0x7) {
15339 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15341 /* clear the UNDI indication */
15342 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15343 /* clear possible idle check errors */
15344 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15348 /* wait until BRB is empty */
15349 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15350 while (timer_count) {
15351 prev_brb = tmp_reg;
15353 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15358 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15360 /* reset timer as long as BRB actually gets emptied */
15361 if (prev_brb > tmp_reg) {
15362 timer_count = 1000;
15367 /* If UNDI resides in memory, manually increment it */
15369 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15375 if (!timer_count) {
15376 BLOGE(sc, "Failed to empty BRB\n");
15380 /* No packets are in the pipeline, path is ready for reset */
15381 bxe_reset_common(sc);
15383 if (mac_vals.xmac_addr) {
15384 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15386 if (mac_vals.umac_addr) {
15387 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15389 if (mac_vals.emac_addr) {
15390 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15392 if (mac_vals.bmac_addr) {
15393 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15394 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15397 rc = bxe_prev_mark_path(sc, prev_undi);
15399 bxe_prev_mcp_done(sc);
15403 return (bxe_prev_mcp_done(sc));
15407 bxe_prev_unload_uncommon(struct bxe_softc *sc)
15411 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15413 /* Test if previous unload process was already finished for this path */
15414 if (bxe_prev_is_path_marked(sc)) {
15415 return (bxe_prev_mcp_done(sc));
15418 BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15421 * If function has FLR capabilities, and existing FW version matches
15422 * the one required, then FLR will be sufficient to clean any residue
15423 * left by previous driver
15425 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15427 /* fw version is good */
15428 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15429 rc = bxe_do_flr(sc);
15433 /* FLR was performed */
15434 BLOGD(sc, DBG_LOAD, "FLR successful\n");
15438 BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15440 /* Close the MCP request, return failure*/
15441 rc = bxe_prev_mcp_done(sc);
15443 rc = BXE_PREV_WAIT_NEEDED;
15450 bxe_prev_unload(struct bxe_softc *sc)
15452 int time_counter = 10;
15453 uint32_t fw, hw_lock_reg, hw_lock_val;
15457 * Clear HW from errors which may have resulted from an interrupted
15458 * DMAE transaction.
15460 bxe_prev_interrupted_dmae(sc);
15462 /* Release previously held locks */
15464 (SC_FUNC(sc) <= 5) ?
15465 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
15466 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
15468 hw_lock_val = (REG_RD(sc, hw_lock_reg));
15470 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
15471 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
15472 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
15473 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
15475 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
15476 REG_WR(sc, hw_lock_reg, 0xffffffff);
15478 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
15481 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
15482 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
15483 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
15487 /* Lock MCP using an unload request */
15488 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
15490 BLOGE(sc, "MCP response failure, aborting\n");
15495 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
15496 rc = bxe_prev_unload_common(sc);
15500 /* non-common reply from MCP night require looping */
15501 rc = bxe_prev_unload_uncommon(sc);
15502 if (rc != BXE_PREV_WAIT_NEEDED) {
15507 } while (--time_counter);
15509 if (!time_counter || rc) {
15510 BLOGE(sc, "Failed to unload previous driver!"
15511 " time_counter %d rc %d\n", time_counter, rc);
15519 bxe_dcbx_set_state(struct bxe_softc *sc,
15521 uint32_t dcbx_enabled)
15523 if (!CHIP_IS_E1x(sc)) {
15524 sc->dcb_state = dcb_on;
15525 sc->dcbx_enabled = dcbx_enabled;
15527 sc->dcb_state = FALSE;
15528 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
15530 BLOGD(sc, DBG_LOAD,
15531 "DCB state [%s:%s]\n",
15532 dcb_on ? "ON" : "OFF",
15533 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
15534 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
15535 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
15536 "on-chip with negotiation" : "invalid");
15539 /* must be called after sriov-enable */
15541 bxe_set_qm_cid_count(struct bxe_softc *sc)
15543 int cid_count = BXE_L2_MAX_CID(sc);
15545 if (IS_SRIOV(sc)) {
15546 cid_count += BXE_VF_CIDS;
15549 if (CNIC_SUPPORT(sc)) {
15550 cid_count += CNIC_CID_MAX;
15553 return (roundup(cid_count, QM_CID_ROUND));
15557 bxe_init_multi_cos(struct bxe_softc *sc)
15561 uint32_t pri_map = 0; /* XXX change to user config */
15563 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
15564 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
15565 if (cos < sc->max_cos) {
15566 sc->prio_to_cos[pri] = cos;
15568 BLOGW(sc, "Invalid COS %d for priority %d "
15569 "(max COS is %d), setting to 0\n",
15570 cos, pri, (sc->max_cos - 1));
15571 sc->prio_to_cos[pri] = 0;
15577 bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
15579 struct bxe_softc *sc;
15583 error = sysctl_handle_int(oidp, &result, 0, req);
15585 if (error || !req->newptr) {
15591 sc = (struct bxe_softc *)arg1;
15593 BLOGI(sc, "... dumping driver state ...\n");
15594 temp = SHMEM2_RD(sc, temperature_in_half_celsius);
15595 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2));
15602 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
15604 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15605 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
15607 uint64_t value = 0;
15608 int index = (int)arg2;
15610 if (index >= BXE_NUM_ETH_STATS) {
15611 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
15615 offset = (eth_stats + bxe_eth_stats_arr[index].offset);
15617 switch (bxe_eth_stats_arr[index].size) {
15619 value = (uint64_t)*offset;
15622 value = HILO_U64(*offset, *(offset + 1));
15625 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
15626 index, bxe_eth_stats_arr[index].size);
15630 return (sysctl_handle_64(oidp, &value, 0, req));
15634 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
15636 struct bxe_softc *sc = (struct bxe_softc *)arg1;
15637 uint32_t *eth_stats;
15639 uint64_t value = 0;
15640 uint32_t q_stat = (uint32_t)arg2;
15641 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
15642 uint32_t index = (q_stat & 0xffff);
15644 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
15646 if (index >= BXE_NUM_ETH_Q_STATS) {
15647 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
15651 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
15653 switch (bxe_eth_q_stats_arr[index].size) {
15655 value = (uint64_t)*offset;
15658 value = HILO_U64(*offset, *(offset + 1));
15661 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
15662 index, bxe_eth_q_stats_arr[index].size);
15666 return (sysctl_handle_64(oidp, &value, 0, req));
15669 static void bxe_force_link_reset(struct bxe_softc *sc)
15672 bxe_acquire_phy_lock(sc);
15673 elink_link_reset(&sc->link_params, &sc->link_vars, 1);
15674 bxe_release_phy_lock(sc);
15678 bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS)
15680 struct bxe_softc *sc = (struct bxe_softc *)arg1;;
15681 uint32_t cfg_idx = bxe_get_link_cfg_idx(sc);
15687 error = sysctl_handle_int(oidp, &sc->bxe_pause_param, 0, req);
15689 if (error || !req->newptr) {
15692 if ((sc->bxe_pause_param < 0) || (sc->bxe_pause_param > 8)) {
15693 BLOGW(sc, "invalid pause param (%d) - use intergers between 1 & 8\n",sc->bxe_pause_param);
15694 sc->bxe_pause_param = 8;
15697 result = (sc->bxe_pause_param << PORT_FEATURE_FLOW_CONTROL_SHIFT);
15700 if((result & 0x400) && !(sc->port.supported[cfg_idx] & ELINK_SUPPORTED_Autoneg)) {
15701 BLOGW(sc, "Does not support Autoneg pause_param %d\n", sc->bxe_pause_param);
15707 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_AUTO;
15708 if(result & ELINK_FLOW_CTRL_RX)
15709 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_RX;
15711 if(result & ELINK_FLOW_CTRL_TX)
15712 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_TX;
15713 if(sc->link_params.req_flow_ctrl[cfg_idx] == ELINK_FLOW_CTRL_AUTO)
15714 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_NONE;
15716 if(result & 0x400) {
15717 if (sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) {
15718 sc->link_params.req_flow_ctrl[cfg_idx] =
15719 ELINK_FLOW_CTRL_AUTO;
15721 sc->link_params.req_fc_auto_adv = 0;
15722 if (result & ELINK_FLOW_CTRL_RX)
15723 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_RX;
15725 if (result & ELINK_FLOW_CTRL_TX)
15726 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_TX;
15727 if (!sc->link_params.req_fc_auto_adv)
15728 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_NONE;
15731 if (sc->link_vars.link_up) {
15732 bxe_stats_handle(sc, STATS_EVENT_STOP);
15734 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
15735 bxe_force_link_reset(sc);
15736 bxe_acquire_phy_lock(sc);
15738 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
15740 bxe_release_phy_lock(sc);
15742 bxe_calc_fc_adv(sc);
15750 bxe_add_sysctls(struct bxe_softc *sc)
15752 struct sysctl_ctx_list *ctx;
15753 struct sysctl_oid_list *children;
15754 struct sysctl_oid *queue_top, *queue;
15755 struct sysctl_oid_list *queue_top_children, *queue_children;
15756 char queue_num_buf[32];
15760 ctx = device_get_sysctl_ctx(sc->dev);
15761 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
15763 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
15764 CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
15767 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
15768 BCM_5710_FW_MAJOR_VERSION,
15769 BCM_5710_FW_MINOR_VERSION,
15770 BCM_5710_FW_REVISION_VERSION,
15771 BCM_5710_FW_ENGINEERING_VERSION);
15773 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
15774 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" :
15775 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" :
15776 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" :
15777 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
15779 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
15780 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
15781 "multifunction vnics per port");
15783 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
15784 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
15785 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
15786 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
15788 sc->devinfo.pcie_link_width);
15790 sc->debug = bxe_debug;
15792 #if __FreeBSD_version >= 900000
15793 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15794 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
15795 "bootcode version");
15796 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15797 CTLFLAG_RD, sc->fw_ver_str, 0,
15798 "firmware version");
15799 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15800 CTLFLAG_RD, sc->mf_mode_str, 0,
15801 "multifunction mode");
15802 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15803 CTLFLAG_RD, sc->mac_addr_str, 0,
15805 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15806 CTLFLAG_RD, sc->pci_link_str, 0,
15807 "pci link status");
15808 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug",
15809 CTLFLAG_RW, &sc->debug,
15810 "debug logging mode");
15812 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
15813 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0,
15814 "bootcode version");
15815 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
15816 CTLFLAG_RD, &sc->fw_ver_str, 0,
15817 "firmware version");
15818 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
15819 CTLFLAG_RD, &sc->mf_mode_str, 0,
15820 "multifunction mode");
15821 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
15822 CTLFLAG_RD, &sc->mac_addr_str, 0,
15824 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
15825 CTLFLAG_RD, &sc->pci_link_str, 0,
15826 "pci link status");
15827 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug",
15828 CTLFLAG_RW, &sc->debug, 0,
15829 "debug logging mode");
15830 #endif /* #if __FreeBSD_version >= 900000 */
15832 sc->trigger_grcdump = 0;
15833 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "trigger_grcdump",
15834 CTLFLAG_RW, &sc->trigger_grcdump, 0,
15835 "trigger grcdump should be invoked"
15836 " before collecting grcdump");
15838 sc->grcdump_started = 0;
15839 sc->grcdump_done = 0;
15840 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "grcdump_done",
15841 CTLFLAG_RD, &sc->grcdump_done, 0,
15842 "set by driver when grcdump is done");
15844 sc->rx_budget = bxe_rx_budget;
15845 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
15846 CTLFLAG_RW, &sc->rx_budget, 0,
15847 "rx processing budget");
15849 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_param",
15850 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15851 bxe_sysctl_pauseparam, "IU",
15852 "need pause frames- DEF:0/TX:1/RX:2/BOTH:3/AUTO:4/AUTOTX:5/AUTORX:6/AUTORXTX:7/NONE:8");
15855 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
15856 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
15857 bxe_sysctl_state, "IU", "dump driver state");
15859 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
15860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
15861 bxe_eth_stats_arr[i].string,
15862 CTLTYPE_U64 | CTLFLAG_RD, sc, i,
15863 bxe_sysctl_eth_stat, "LU",
15864 bxe_eth_stats_arr[i].string);
15867 /* add a new parent node for all queues "dev.bxe.#.queue" */
15868 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
15869 CTLFLAG_RD, NULL, "queue");
15870 queue_top_children = SYSCTL_CHILDREN(queue_top);
15872 for (i = 0; i < sc->num_queues; i++) {
15873 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
15874 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
15875 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
15876 queue_num_buf, CTLFLAG_RD, NULL,
15878 queue_children = SYSCTL_CHILDREN(queue);
15880 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
15881 q_stat = ((i << 16) | j);
15882 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
15883 bxe_eth_q_stats_arr[j].string,
15884 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat,
15885 bxe_sysctl_eth_q_stat, "LU",
15886 bxe_eth_q_stats_arr[j].string);
15892 bxe_alloc_buf_rings(struct bxe_softc *sc)
15894 #if __FreeBSD_version >= 901504
15897 struct bxe_fastpath *fp;
15899 for (i = 0; i < sc->num_queues; i++) {
15903 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
15904 M_NOWAIT, &fp->tx_mtx);
15905 if (fp->tx_br == NULL)
15913 bxe_free_buf_rings(struct bxe_softc *sc)
15915 #if __FreeBSD_version >= 901504
15918 struct bxe_fastpath *fp;
15920 for (i = 0; i < sc->num_queues; i++) {
15925 buf_ring_free(fp->tx_br, M_DEVBUF);
15934 bxe_init_fp_mutexs(struct bxe_softc *sc)
15937 struct bxe_fastpath *fp;
15939 for (i = 0; i < sc->num_queues; i++) {
15943 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
15944 "bxe%d_fp%d_tx_lock", sc->unit, i);
15945 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
15947 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
15948 "bxe%d_fp%d_rx_lock", sc->unit, i);
15949 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
15954 bxe_destroy_fp_mutexs(struct bxe_softc *sc)
15957 struct bxe_fastpath *fp;
15959 for (i = 0; i < sc->num_queues; i++) {
15963 if (mtx_initialized(&fp->tx_mtx)) {
15964 mtx_destroy(&fp->tx_mtx);
15967 if (mtx_initialized(&fp->rx_mtx)) {
15968 mtx_destroy(&fp->rx_mtx);
15975 * Device attach function.
15977 * Allocates device resources, performs secondary chip identification, and
15978 * initializes driver instance variables. This function is called from driver
15979 * load after a successful probe.
15982 * 0 = Success, >0 = Failure
15985 bxe_attach(device_t dev)
15987 struct bxe_softc *sc;
15989 sc = device_get_softc(dev);
15991 BLOGD(sc, DBG_LOAD, "Starting attach...\n");
15993 sc->state = BXE_STATE_CLOSED;
15996 sc->unit = device_get_unit(dev);
15998 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16000 sc->pcie_bus = pci_get_bus(dev);
16001 sc->pcie_device = pci_get_slot(dev);
16002 sc->pcie_func = pci_get_function(dev);
16004 /* enable bus master capability */
16005 pci_enable_busmaster(dev);
16008 if (bxe_allocate_bars(sc) != 0) {
16012 /* initialize the mutexes */
16013 bxe_init_mutexes(sc);
16015 /* prepare the periodic callout */
16016 callout_init(&sc->periodic_callout, 0);
16018 /* prepare the chip taskqueue */
16019 sc->chip_tq_flags = CHIP_TQ_NONE;
16020 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16021 "bxe%d_chip_tq", sc->unit);
16022 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16023 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16024 taskqueue_thread_enqueue,
16026 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16027 "%s", sc->chip_tq_name);
16029 /* get device info and set params */
16030 if (bxe_get_device_info(sc) != 0) {
16031 BLOGE(sc, "getting device info\n");
16032 bxe_deallocate_bars(sc);
16033 pci_disable_busmaster(dev);
16037 /* get final misc params */
16038 bxe_get_params(sc);
16040 /* set the default MTU (changed via ifconfig) */
16041 sc->mtu = ETHERMTU;
16043 bxe_set_modes_bitmap(sc);
16046 * If in AFEX mode and the function is configured for FCoE
16047 * then bail... no L2 allowed.
16050 /* get phy settings from shmem and 'and' against admin settings */
16051 bxe_get_phy_info(sc);
16053 /* initialize the FreeBSD ifnet interface */
16054 if (bxe_init_ifnet(sc) != 0) {
16055 bxe_release_mutexes(sc);
16056 bxe_deallocate_bars(sc);
16057 pci_disable_busmaster(dev);
16061 if (bxe_add_cdev(sc) != 0) {
16062 if (sc->ifnet != NULL) {
16063 ether_ifdetach(sc->ifnet);
16065 ifmedia_removeall(&sc->ifmedia);
16066 bxe_release_mutexes(sc);
16067 bxe_deallocate_bars(sc);
16068 pci_disable_busmaster(dev);
16072 /* allocate device interrupts */
16073 if (bxe_interrupt_alloc(sc) != 0) {
16075 if (sc->ifnet != NULL) {
16076 ether_ifdetach(sc->ifnet);
16078 ifmedia_removeall(&sc->ifmedia);
16079 bxe_release_mutexes(sc);
16080 bxe_deallocate_bars(sc);
16081 pci_disable_busmaster(dev);
16085 bxe_init_fp_mutexs(sc);
16087 if (bxe_alloc_buf_rings(sc) != 0) {
16088 bxe_free_buf_rings(sc);
16089 bxe_interrupt_free(sc);
16091 if (sc->ifnet != NULL) {
16092 ether_ifdetach(sc->ifnet);
16094 ifmedia_removeall(&sc->ifmedia);
16095 bxe_release_mutexes(sc);
16096 bxe_deallocate_bars(sc);
16097 pci_disable_busmaster(dev);
16102 if (bxe_alloc_ilt_mem(sc) != 0) {
16103 bxe_free_buf_rings(sc);
16104 bxe_interrupt_free(sc);
16106 if (sc->ifnet != NULL) {
16107 ether_ifdetach(sc->ifnet);
16109 ifmedia_removeall(&sc->ifmedia);
16110 bxe_release_mutexes(sc);
16111 bxe_deallocate_bars(sc);
16112 pci_disable_busmaster(dev);
16116 /* allocate the host hardware/software hsi structures */
16117 if (bxe_alloc_hsi_mem(sc) != 0) {
16118 bxe_free_ilt_mem(sc);
16119 bxe_free_buf_rings(sc);
16120 bxe_interrupt_free(sc);
16122 if (sc->ifnet != NULL) {
16123 ether_ifdetach(sc->ifnet);
16125 ifmedia_removeall(&sc->ifmedia);
16126 bxe_release_mutexes(sc);
16127 bxe_deallocate_bars(sc);
16128 pci_disable_busmaster(dev);
16132 /* need to reset chip if UNDI was active */
16133 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16136 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16137 DRV_MSG_SEQ_NUMBER_MASK);
16138 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16139 bxe_prev_unload(sc);
16144 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16146 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16147 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16148 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16149 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16150 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16151 bxe_dcbx_init_params(sc);
16153 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16157 /* calculate qm_cid_count */
16158 sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16159 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16162 bxe_init_multi_cos(sc);
16164 bxe_add_sysctls(sc);
16170 * Device detach function.
16172 * Stops the controller, resets the controller, and releases resources.
16175 * 0 = Success, >0 = Failure
16178 bxe_detach(device_t dev)
16180 struct bxe_softc *sc;
16183 sc = device_get_softc(dev);
16185 BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16188 if (ifp != NULL && ifp->if_vlantrunk != NULL) {
16189 BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16195 /* stop the periodic callout */
16196 bxe_periodic_stop(sc);
16198 /* stop the chip taskqueue */
16199 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16201 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16202 taskqueue_free(sc->chip_tq);
16203 sc->chip_tq = NULL;
16206 /* stop and reset the controller if it was open */
16207 if (sc->state != BXE_STATE_CLOSED) {
16209 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16210 sc->state = BXE_STATE_DISABLED;
16211 BXE_CORE_UNLOCK(sc);
16214 /* release the network interface */
16216 ether_ifdetach(ifp);
16218 ifmedia_removeall(&sc->ifmedia);
16220 /* XXX do the following based on driver state... */
16222 /* free the host hardware/software hsi structures */
16223 bxe_free_hsi_mem(sc);
16226 bxe_free_ilt_mem(sc);
16228 bxe_free_buf_rings(sc);
16230 /* release the interrupts */
16231 bxe_interrupt_free(sc);
16233 /* Release the mutexes*/
16234 bxe_destroy_fp_mutexs(sc);
16235 bxe_release_mutexes(sc);
16238 /* Release the PCIe BAR mapped memory */
16239 bxe_deallocate_bars(sc);
16241 /* Release the FreeBSD interface. */
16242 if (sc->ifnet != NULL) {
16243 if_free(sc->ifnet);
16246 pci_disable_busmaster(dev);
16252 * Device shutdown function.
16254 * Stops and resets the controller.
16260 bxe_shutdown(device_t dev)
16262 struct bxe_softc *sc;
16264 sc = device_get_softc(dev);
16266 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16268 /* stop the periodic callout */
16269 bxe_periodic_stop(sc);
16272 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16273 BXE_CORE_UNLOCK(sc);
16279 bxe_igu_ack_sb(struct bxe_softc *sc,
16286 uint32_t igu_addr = sc->igu_base_addr;
16287 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16288 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16292 bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16297 uint32_t data, ctl, cnt = 100;
16298 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16299 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16300 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16301 uint32_t sb_bit = 1 << (idu_sb_id%32);
16302 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16303 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16305 /* Not supported in BC mode */
16306 if (CHIP_INT_MODE_IS_BC(sc)) {
16310 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16311 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16312 IGU_REGULAR_CLEANUP_SET |
16313 IGU_REGULAR_BCLEANUP);
16315 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16316 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16317 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16319 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16320 data, igu_addr_data);
16321 REG_WR(sc, igu_addr_data, data);
16323 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16324 BUS_SPACE_BARRIER_WRITE);
16327 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16328 ctl, igu_addr_ctl);
16329 REG_WR(sc, igu_addr_ctl, ctl);
16331 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16332 BUS_SPACE_BARRIER_WRITE);
16335 /* wait for clean up to finish */
16336 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16340 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16341 BLOGD(sc, DBG_LOAD,
16342 "Unable to finish IGU cleanup: "
16343 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16344 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16349 bxe_igu_clear_sb(struct bxe_softc *sc,
16352 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16361 /*******************/
16362 /* ECORE CALLBACKS */
16363 /*******************/
16366 bxe_reset_common(struct bxe_softc *sc)
16368 uint32_t val = 0x1400;
16371 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16373 if (CHIP_IS_E3(sc)) {
16374 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16375 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16378 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16382 bxe_common_init_phy(struct bxe_softc *sc)
16384 uint32_t shmem_base[2];
16385 uint32_t shmem2_base[2];
16387 /* Avoid common init in case MFW supports LFA */
16388 if (SHMEM2_RD(sc, size) >
16389 (uint32_t)offsetof(struct shmem2_region,
16390 lfa_host_addr[SC_PORT(sc)])) {
16394 shmem_base[0] = sc->devinfo.shmem_base;
16395 shmem2_base[0] = sc->devinfo.shmem2_base;
16397 if (!CHIP_IS_E1x(sc)) {
16398 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
16399 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16402 bxe_acquire_phy_lock(sc);
16403 elink_common_init_phy(sc, shmem_base, shmem2_base,
16404 sc->devinfo.chip_id, 0);
16405 bxe_release_phy_lock(sc);
16409 bxe_pf_disable(struct bxe_softc *sc)
16411 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16413 val &= ~IGU_PF_CONF_FUNC_EN;
16415 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16416 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16417 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16421 bxe_init_pxp(struct bxe_softc *sc)
16424 int r_order, w_order;
16426 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2);
16428 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16430 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
16432 if (sc->mrrs == -1) {
16433 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
16435 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16436 r_order = sc->mrrs;
16439 ecore_init_pxp_arb(sc, r_order, w_order);
16443 bxe_get_pretend_reg(struct bxe_softc *sc)
16445 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16446 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16447 return (base + (SC_ABS_FUNC(sc)) * stride);
16451 * Called only on E1H or E2.
16452 * When pretending to be PF, the pretend value is the function number 0..7.
16453 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16457 bxe_pretend_func(struct bxe_softc *sc,
16458 uint16_t pretend_func_val)
16460 uint32_t pretend_reg;
16462 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16466 /* get my own pretend register */
16467 pretend_reg = bxe_get_pretend_reg(sc);
16468 REG_WR(sc, pretend_reg, pretend_func_val);
16469 REG_RD(sc, pretend_reg);
16474 bxe_iov_init_dmae(struct bxe_softc *sc)
16480 bxe_iov_init_dq(struct bxe_softc *sc)
16485 /* send a NIG loopback debug packet */
16487 bxe_lb_pckt(struct bxe_softc *sc)
16489 uint32_t wb_write[3];
16491 /* Ethernet source and destination addresses */
16492 wb_write[0] = 0x55555555;
16493 wb_write[1] = 0x55555555;
16494 wb_write[2] = 0x20; /* SOP */
16495 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16497 /* NON-IP protocol */
16498 wb_write[0] = 0x09000000;
16499 wb_write[1] = 0x55555555;
16500 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
16501 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16505 * Some of the internal memories are not directly readable from the driver.
16506 * To test them we send debug packets.
16509 bxe_int_mem_test(struct bxe_softc *sc)
16515 if (CHIP_REV_IS_FPGA(sc)) {
16517 } else if (CHIP_REV_IS_EMUL(sc)) {
16523 /* disable inputs of parser neighbor blocks */
16524 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16525 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16526 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16527 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16529 /* write 0 to parser credits for CFC search request */
16530 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16532 /* send Ethernet packet */
16535 /* TODO do i reset NIG statistic? */
16536 /* Wait until NIG register shows 1 packet of size 0x10 */
16537 count = 1000 * factor;
16539 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16540 val = *BXE_SP(sc, wb_data[0]);
16550 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16554 /* wait until PRS register shows 1 packet */
16555 count = (1000 * factor);
16557 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16567 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16571 /* Reset and init BRB, PRS */
16572 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16574 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16576 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16577 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16579 /* Disable inputs of parser neighbor blocks */
16580 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16581 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16582 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16583 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16585 /* Write 0 to parser credits for CFC search request */
16586 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16588 /* send 10 Ethernet packets */
16589 for (i = 0; i < 10; i++) {
16593 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16594 count = (1000 * factor);
16596 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16597 val = *BXE_SP(sc, wb_data[0]);
16607 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16611 /* Wait until PRS register shows 2 packets */
16612 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16614 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16617 /* Write 1 to parser credits for CFC search request */
16618 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
16620 /* Wait until PRS register shows 3 packets */
16621 DELAY(10000 * factor);
16623 /* Wait until NIG register shows 1 packet of size 0x10 */
16624 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16626 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16629 /* clear NIG EOP FIFO */
16630 for (i = 0; i < 11; i++) {
16631 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
16634 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
16636 BLOGE(sc, "clear of NIG failed val=0x%x\n", val);
16640 /* Reset and init BRB, PRS, NIG */
16641 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16643 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16645 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16646 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16647 if (!CNIC_SUPPORT(sc)) {
16649 REG_WR(sc, PRS_REG_NIC_MODE, 1);
16652 /* Enable inputs of parser neighbor blocks */
16653 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
16654 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
16655 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
16656 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
16662 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
16669 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
16670 SHARED_HW_CFG_FAN_FAILURE_MASK);
16672 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
16676 * The fan failure mechanism is usually related to the PHY type since
16677 * the power consumption of the board is affected by the PHY. Currently,
16678 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
16680 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
16681 for (port = PORT_0; port < PORT_MAX; port++) {
16682 is_required |= elink_fan_failure_det_req(sc,
16683 sc->devinfo.shmem_base,
16684 sc->devinfo.shmem2_base,
16689 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
16691 if (is_required == 0) {
16695 /* Fan failure is indicated by SPIO 5 */
16696 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
16698 /* set to active low mode */
16699 val = REG_RD(sc, MISC_REG_SPIO_INT);
16700 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
16701 REG_WR(sc, MISC_REG_SPIO_INT, val);
16703 /* enable interrupt to signal the IGU */
16704 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
16705 val |= MISC_SPIO_SPIO5;
16706 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
16710 bxe_enable_blocks_attention(struct bxe_softc *sc)
16714 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16715 if (!CHIP_IS_E1x(sc)) {
16716 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
16718 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
16720 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
16721 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
16723 * mask read length error interrupts in brb for parser
16724 * (parsing unit and 'checksum and crc' unit)
16725 * these errors are legal (PU reads fixed length and CAC can cause
16726 * read length error on truncated packets)
16728 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
16729 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
16730 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
16731 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
16732 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
16733 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
16734 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
16735 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
16736 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
16737 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
16738 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
16739 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
16740 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
16741 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
16742 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
16743 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
16744 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
16745 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
16746 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
16748 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
16749 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
16750 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
16751 if (!CHIP_IS_E1x(sc)) {
16752 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
16753 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
16755 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
16757 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
16758 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
16759 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
16760 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
16762 if (!CHIP_IS_E1x(sc)) {
16763 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
16764 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
16767 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
16768 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
16769 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
16770 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
16774 * bxe_init_hw_common - initialize the HW at the COMMON phase.
16776 * @sc: driver handle
16779 bxe_init_hw_common(struct bxe_softc *sc)
16781 uint8_t abs_func_id;
16784 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
16788 * take the RESET lock to protect undi_unload flow from accessing
16789 * registers while we are resetting the chip
16791 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16793 bxe_reset_common(sc);
16795 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
16798 if (CHIP_IS_E3(sc)) {
16799 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16800 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16803 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
16805 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
16807 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
16808 BLOGD(sc, DBG_LOAD, "after misc block init\n");
16810 if (!CHIP_IS_E1x(sc)) {
16812 * 4-port mode or 2-port mode we need to turn off master-enable for
16813 * everyone. After that we turn it back on for self. So, we disregard
16814 * multi-function, and always disable all functions on the given path,
16815 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
16817 for (abs_func_id = SC_PATH(sc);
16818 abs_func_id < (E2_FUNC_MAX * 2);
16819 abs_func_id += 2) {
16820 if (abs_func_id == SC_ABS_FUNC(sc)) {
16821 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
16825 bxe_pretend_func(sc, abs_func_id);
16827 /* clear pf enable */
16828 bxe_pf_disable(sc);
16830 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
16834 BLOGD(sc, DBG_LOAD, "after pf disable\n");
16836 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
16838 if (CHIP_IS_E1(sc)) {
16840 * enable HW interrupt from PXP on USDM overflow
16841 * bit 16 on INT_MASK_0
16843 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
16846 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
16849 #ifdef __BIG_ENDIAN
16850 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
16851 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
16852 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
16853 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
16854 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
16855 /* make sure this value is 0 */
16856 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
16858 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
16859 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
16860 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
16861 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
16862 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
16865 ecore_ilt_init_page_size(sc, INITOP_SET);
16867 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
16868 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
16871 /* let the HW do it's magic... */
16874 /* finish PXP init */
16875 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
16877 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n",
16881 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
16883 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val);
16887 BLOGD(sc, DBG_LOAD, "after pxp init\n");
16890 * Timer bug workaround for E2 only. We need to set the entire ILT to have
16891 * entries with value "0" and valid bit on. This needs to be done by the
16892 * first PF that is loaded in a path (i.e. common phase)
16894 if (!CHIP_IS_E1x(sc)) {
16896 * In E2 there is a bug in the timers block that can cause function 6 / 7
16897 * (i.e. vnic3) to start even if it is marked as "scan-off".
16898 * This occurs when a different function (func2,3) is being marked
16899 * as "scan-off". Real-life scenario for example: if a driver is being
16900 * load-unloaded while func6,7 are down. This will cause the timer to access
16901 * the ilt, translate to a logical address and send a request to read/write.
16902 * Since the ilt for the function that is down is not valid, this will cause
16903 * a translation error which is unrecoverable.
16904 * The Workaround is intended to make sure that when this happens nothing
16905 * fatal will occur. The workaround:
16906 * 1. First PF driver which loads on a path will:
16907 * a. After taking the chip out of reset, by using pretend,
16908 * it will write "0" to the following registers of
16910 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16911 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
16912 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
16913 * And for itself it will write '1' to
16914 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
16915 * dmae-operations (writing to pram for example.)
16916 * note: can be done for only function 6,7 but cleaner this
16918 * b. Write zero+valid to the entire ILT.
16919 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
16920 * VNIC3 (of that port). The range allocated will be the
16921 * entire ILT. This is needed to prevent ILT range error.
16922 * 2. Any PF driver load flow:
16923 * a. ILT update with the physical addresses of the allocated
16925 * b. Wait 20msec. - note that this timeout is needed to make
16926 * sure there are no requests in one of the PXP internal
16927 * queues with "old" ILT addresses.
16928 * c. PF enable in the PGLC.
16929 * d. Clear the was_error of the PF in the PGLC. (could have
16930 * occurred while driver was down)
16931 * e. PF enable in the CFC (WEAK + STRONG)
16932 * f. Timers scan enable
16933 * 3. PF driver unload flow:
16934 * a. Clear the Timers scan_en.
16935 * b. Polling for scan_on=0 for that PF.
16936 * c. Clear the PF enable bit in the PXP.
16937 * d. Clear the PF enable in the CFC (WEAK + STRONG)
16938 * e. Write zero+valid to all ILT entries (The valid bit must
16940 * f. If this is VNIC 3 of a port then also init
16941 * first_timers_ilt_entry to zero and last_timers_ilt_entry
16942 * to the last enrty in the ILT.
16945 * Currently the PF error in the PGLC is non recoverable.
16946 * In the future the there will be a recovery routine for this error.
16947 * Currently attention is masked.
16948 * Having an MCP lock on the load/unload process does not guarantee that
16949 * there is no Timer disable during Func6/7 enable. This is because the
16950 * Timers scan is currently being cleared by the MCP on FLR.
16951 * Step 2.d can be done only for PF6/7 and the driver can also check if
16952 * there is error before clearing it. But the flow above is simpler and
16954 * All ILT entries are written by zero+valid and not just PF6/7
16955 * ILT entries since in the future the ILT entries allocation for
16956 * PF-s might be dynamic.
16958 struct ilt_client_info ilt_cli;
16959 struct ecore_ilt ilt;
16961 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
16962 memset(&ilt, 0, sizeof(struct ecore_ilt));
16964 /* initialize dummy TM client */
16966 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
16967 ilt_cli.client_num = ILT_CLIENT_TM;
16970 * Step 1: set zeroes to all ilt page entries with valid bit on
16971 * Step 2: set the timers first/last ilt entry to point
16972 * to the entire range to prevent ILT range error for 3rd/4th
16973 * vnic (this code assumes existence of the vnic)
16975 * both steps performed by call to ecore_ilt_client_init_op()
16976 * with dummy TM client
16978 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
16979 * and his brother are split registers
16982 bxe_pretend_func(sc, (SC_PATH(sc) + 6));
16983 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
16984 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
16986 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
16987 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
16988 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
16991 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
16992 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
16994 if (!CHIP_IS_E1x(sc)) {
16995 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
16996 (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
16998 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
16999 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17001 /* let the HW do it's magic... */
17004 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17005 } while (factor-- && (val != 1));
17008 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val);
17013 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17015 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17017 bxe_iov_init_dmae(sc);
17019 /* clean the DMAE memory */
17020 sc->dmae_ready = 1;
17021 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17023 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17025 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17027 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17029 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17031 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17032 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17033 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17034 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17036 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17038 /* QM queues pointers table */
17039 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17041 /* soft reset pulse */
17042 REG_WR(sc, QM_REG_SOFT_RESET, 1);
17043 REG_WR(sc, QM_REG_SOFT_RESET, 0);
17045 if (CNIC_SUPPORT(sc))
17046 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17048 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17049 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17050 if (!CHIP_REV_IS_SLOW(sc)) {
17051 /* enable hw interrupt from doorbell Q */
17052 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17055 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17057 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17058 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17060 if (!CHIP_IS_E1(sc)) {
17061 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17064 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17065 if (IS_MF_AFEX(sc)) {
17067 * configure that AFEX and VLAN headers must be
17068 * received in AFEX mode
17070 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17071 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17072 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17073 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17074 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17077 * Bit-map indicating which L2 hdrs may appear
17078 * after the basic Ethernet header
17080 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17081 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17085 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17086 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17087 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17088 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17090 if (!CHIP_IS_E1x(sc)) {
17091 /* reset VFC memories */
17092 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17093 VFC_MEMORIES_RST_REG_CAM_RST |
17094 VFC_MEMORIES_RST_REG_RAM_RST);
17095 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17096 VFC_MEMORIES_RST_REG_CAM_RST |
17097 VFC_MEMORIES_RST_REG_RAM_RST);
17102 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17103 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17104 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17105 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17107 /* sync semi rtc */
17108 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17110 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17113 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17114 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17115 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17117 if (!CHIP_IS_E1x(sc)) {
17118 if (IS_MF_AFEX(sc)) {
17120 * configure that AFEX and VLAN headers must be
17121 * sent in AFEX mode
17123 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17124 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17125 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17126 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17127 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17129 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17130 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17134 REG_WR(sc, SRC_REG_SOFT_RST, 1);
17136 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17138 if (CNIC_SUPPORT(sc)) {
17139 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17140 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17141 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17142 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17143 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17144 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17145 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17146 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17147 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17148 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17150 REG_WR(sc, SRC_REG_SOFT_RST, 0);
17152 if (sizeof(union cdu_context) != 1024) {
17153 /* we currently assume that a context is 1024 bytes */
17154 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17155 (long)sizeof(union cdu_context));
17158 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17159 val = (4 << 24) + (0 << 12) + 1024;
17160 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17162 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17164 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17165 /* enable context validation interrupt from CFC */
17166 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17168 /* set the thresholds to prevent CFC/CDU race */
17169 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17170 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17172 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17173 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17176 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17177 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17179 /* Reset PCIE errors for debug */
17180 REG_WR(sc, 0x2814, 0xffffffff);
17181 REG_WR(sc, 0x3820, 0xffffffff);
17183 if (!CHIP_IS_E1x(sc)) {
17184 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17185 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17186 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17187 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17188 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17189 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17190 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17191 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17192 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17193 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17194 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17197 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17199 if (!CHIP_IS_E1(sc)) {
17200 /* in E3 this done in per-port section */
17201 if (!CHIP_IS_E3(sc))
17202 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17205 if (CHIP_IS_E1H(sc)) {
17206 /* not applicable for E2 (and above ...) */
17207 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17210 if (CHIP_REV_IS_SLOW(sc)) {
17214 /* finish CFC init */
17215 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17217 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val);
17220 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17222 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val);
17225 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17227 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val);
17230 REG_WR(sc, CFC_REG_DEBUG0, 0);
17232 if (CHIP_IS_E1(sc)) {
17233 /* read NIG statistic to see if this is our first up since powerup */
17234 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17235 val = *BXE_SP(sc, wb_data[0]);
17237 /* do internal memory self test */
17238 if ((val == 0) && bxe_int_mem_test(sc)) {
17239 BLOGE(sc, "internal mem self test failed val=0x%x\n", val);
17244 bxe_setup_fan_failure_detection(sc);
17246 /* clear PXP2 attentions */
17247 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17249 bxe_enable_blocks_attention(sc);
17251 if (!CHIP_REV_IS_SLOW(sc)) {
17252 ecore_enable_blocks_parity(sc);
17255 if (!BXE_NOMCP(sc)) {
17256 if (CHIP_IS_E1x(sc)) {
17257 bxe_common_init_phy(sc);
17265 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17267 * @sc: driver handle
17270 bxe_init_hw_common_chip(struct bxe_softc *sc)
17272 int rc = bxe_init_hw_common(sc);
17275 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc);
17279 /* In E2 2-PORT mode, same ext phy is used for the two paths */
17280 if (!BXE_NOMCP(sc)) {
17281 bxe_common_init_phy(sc);
17288 bxe_init_hw_port(struct bxe_softc *sc)
17290 int port = SC_PORT(sc);
17291 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17292 uint32_t low, high;
17295 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17297 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17299 ecore_init_block(sc, BLOCK_MISC, init_phase);
17300 ecore_init_block(sc, BLOCK_PXP, init_phase);
17301 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17304 * Timers bug workaround: disables the pf_master bit in pglue at
17305 * common phase, we need to enable it here before any dmae access are
17306 * attempted. Therefore we manually added the enable-master to the
17307 * port phase (it also happens in the function phase)
17309 if (!CHIP_IS_E1x(sc)) {
17310 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17313 ecore_init_block(sc, BLOCK_ATC, init_phase);
17314 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17315 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17316 ecore_init_block(sc, BLOCK_QM, init_phase);
17318 ecore_init_block(sc, BLOCK_TCM, init_phase);
17319 ecore_init_block(sc, BLOCK_UCM, init_phase);
17320 ecore_init_block(sc, BLOCK_CCM, init_phase);
17321 ecore_init_block(sc, BLOCK_XCM, init_phase);
17323 /* QM cid (connection) count */
17324 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17326 if (CNIC_SUPPORT(sc)) {
17327 ecore_init_block(sc, BLOCK_TM, init_phase);
17328 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17329 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17332 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17334 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17336 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17338 low = (BXE_ONE_PORT(sc) ? 160 : 246);
17339 } else if (sc->mtu > 4096) {
17340 if (BXE_ONE_PORT(sc)) {
17344 /* (24*1024 + val*4)/256 */
17345 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17348 low = (BXE_ONE_PORT(sc) ? 80 : 160);
17350 high = (low + 56); /* 14*1024/256 */
17351 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17352 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17355 if (CHIP_IS_MODE_4_PORT(sc)) {
17356 REG_WR(sc, SC_PORT(sc) ?
17357 BRB1_REG_MAC_GUARANTIED_1 :
17358 BRB1_REG_MAC_GUARANTIED_0, 40);
17361 ecore_init_block(sc, BLOCK_PRS, init_phase);
17362 if (CHIP_IS_E3B0(sc)) {
17363 if (IS_MF_AFEX(sc)) {
17364 /* configure headers for AFEX mode */
17365 REG_WR(sc, SC_PORT(sc) ?
17366 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17367 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17368 REG_WR(sc, SC_PORT(sc) ?
17369 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17370 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17371 REG_WR(sc, SC_PORT(sc) ?
17372 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17373 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17375 /* Ovlan exists only if we are in multi-function +
17376 * switch-dependent mode, in switch-independent there
17377 * is no ovlan headers
17379 REG_WR(sc, SC_PORT(sc) ?
17380 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17381 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17382 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17386 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17387 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17388 ecore_init_block(sc, BLOCK_USDM, init_phase);
17389 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17391 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17392 ecore_init_block(sc, BLOCK_USEM, init_phase);
17393 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17394 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17396 ecore_init_block(sc, BLOCK_UPB, init_phase);
17397 ecore_init_block(sc, BLOCK_XPB, init_phase);
17399 ecore_init_block(sc, BLOCK_PBF, init_phase);
17401 if (CHIP_IS_E1x(sc)) {
17402 /* configure PBF to work without PAUSE mtu 9000 */
17403 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17405 /* update threshold */
17406 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17407 /* update init credit */
17408 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17410 /* probe changes */
17411 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17413 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17416 if (CNIC_SUPPORT(sc)) {
17417 ecore_init_block(sc, BLOCK_SRC, init_phase);
17420 ecore_init_block(sc, BLOCK_CDU, init_phase);
17421 ecore_init_block(sc, BLOCK_CFC, init_phase);
17423 if (CHIP_IS_E1(sc)) {
17424 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17425 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17427 ecore_init_block(sc, BLOCK_HC, init_phase);
17429 ecore_init_block(sc, BLOCK_IGU, init_phase);
17431 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17432 /* init aeu_mask_attn_func_0/1:
17433 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17434 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17435 * bits 4-7 are used for "per vn group attention" */
17436 val = IS_MF(sc) ? 0xF7 : 0x7;
17437 /* Enable DCBX attention for all but E1 */
17438 val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17439 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17441 ecore_init_block(sc, BLOCK_NIG, init_phase);
17443 if (!CHIP_IS_E1x(sc)) {
17444 /* Bit-map indicating which L2 hdrs may appear after the
17445 * basic Ethernet header
17447 if (IS_MF_AFEX(sc)) {
17448 REG_WR(sc, SC_PORT(sc) ?
17449 NIG_REG_P1_HDRS_AFTER_BASIC :
17450 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17452 REG_WR(sc, SC_PORT(sc) ?
17453 NIG_REG_P1_HDRS_AFTER_BASIC :
17454 NIG_REG_P0_HDRS_AFTER_BASIC,
17455 IS_MF_SD(sc) ? 7 : 6);
17458 if (CHIP_IS_E3(sc)) {
17459 REG_WR(sc, SC_PORT(sc) ?
17460 NIG_REG_LLH1_MF_MODE :
17461 NIG_REG_LLH_MF_MODE, IS_MF(sc));
17464 if (!CHIP_IS_E3(sc)) {
17465 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17468 if (!CHIP_IS_E1(sc)) {
17469 /* 0x2 disable mf_ov, 0x1 enable */
17470 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17471 (IS_MF_SD(sc) ? 0x1 : 0x2));
17473 if (!CHIP_IS_E1x(sc)) {
17475 switch (sc->devinfo.mf_info.mf_mode) {
17476 case MULTI_FUNCTION_SD:
17479 case MULTI_FUNCTION_SI:
17480 case MULTI_FUNCTION_AFEX:
17485 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17486 NIG_REG_LLH0_CLS_TYPE), val);
17488 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17489 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17490 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17493 /* If SPIO5 is set to generate interrupts, enable it for this port */
17494 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17495 if (val & MISC_SPIO_SPIO5) {
17496 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17497 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17498 val = REG_RD(sc, reg_addr);
17499 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17500 REG_WR(sc, reg_addr, val);
17507 bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17510 uint32_t poll_count)
17512 uint32_t cur_cnt = poll_count;
17515 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17516 DELAY(FLR_WAIT_INTERVAL);
17523 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17528 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17531 BLOGE(sc, "%s usage count=%d\n", msg, val);
17538 /* Common routines with VF FLR cleanup */
17540 bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17542 /* adjust polling timeout */
17543 if (CHIP_REV_IS_EMUL(sc)) {
17544 return (FLR_POLL_CNT * 2000);
17547 if (CHIP_REV_IS_FPGA(sc)) {
17548 return (FLR_POLL_CNT * 120);
17551 return (FLR_POLL_CNT);
17555 bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17558 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17559 if (bxe_flr_clnup_poll_hw_counter(sc,
17560 CFC_REG_NUM_LCIDS_INSIDE_PF,
17561 "CFC PF usage counter timed out",
17566 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17567 if (bxe_flr_clnup_poll_hw_counter(sc,
17568 DORQ_REG_PF_USAGE_CNT,
17569 "DQ PF usage counter timed out",
17574 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17575 if (bxe_flr_clnup_poll_hw_counter(sc,
17576 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17577 "QM PF usage counter timed out",
17582 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17583 if (bxe_flr_clnup_poll_hw_counter(sc,
17584 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17585 "Timers VNIC usage counter timed out",
17590 if (bxe_flr_clnup_poll_hw_counter(sc,
17591 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17592 "Timers NUM_SCANS usage counter timed out",
17597 /* Wait DMAE PF usage counter to zero */
17598 if (bxe_flr_clnup_poll_hw_counter(sc,
17599 dmae_reg_go_c[INIT_DMAE_C(sc)],
17600 "DMAE dommand register timed out",
17608 #define OP_GEN_PARAM(param) \
17609 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17610 #define OP_GEN_TYPE(type) \
17611 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17612 #define OP_GEN_AGG_VECT(index) \
17613 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17616 bxe_send_final_clnup(struct bxe_softc *sc,
17617 uint8_t clnup_func,
17620 uint32_t op_gen_command = 0;
17621 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
17622 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
17625 if (REG_RD(sc, comp_addr)) {
17626 BLOGE(sc, "Cleanup complete was not 0 before sending\n");
17630 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
17631 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
17632 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
17633 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
17635 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
17636 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
17638 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
17639 BLOGE(sc, "FW final cleanup did not succeed\n");
17640 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
17641 (REG_RD(sc, comp_addr)));
17642 bxe_panic(sc, ("FLR cleanup failed\n"));
17646 /* Zero completion for nxt FLR */
17647 REG_WR(sc, comp_addr, 0);
17653 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc,
17654 struct pbf_pN_buf_regs *regs,
17655 uint32_t poll_count)
17657 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
17658 uint32_t cur_cnt = poll_count;
17660 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
17661 crd = crd_start = REG_RD(sc, regs->crd);
17662 init_crd = REG_RD(sc, regs->init_crd);
17664 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
17665 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd);
17666 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
17668 while ((crd != init_crd) &&
17669 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
17670 (init_crd - crd_start))) {
17672 DELAY(FLR_WAIT_INTERVAL);
17673 crd = REG_RD(sc, regs->crd);
17674 crd_freed = REG_RD(sc, regs->crd_freed);
17676 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
17677 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd);
17678 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
17683 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
17684 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17688 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc,
17689 struct pbf_pN_cmd_regs *regs,
17690 uint32_t poll_count)
17692 uint32_t occup, to_free, freed, freed_start;
17693 uint32_t cur_cnt = poll_count;
17695 occup = to_free = REG_RD(sc, regs->lines_occup);
17696 freed = freed_start = REG_RD(sc, regs->lines_freed);
17698 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17699 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17702 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
17704 DELAY(FLR_WAIT_INTERVAL);
17705 occup = REG_RD(sc, regs->lines_occup);
17706 freed = REG_RD(sc, regs->lines_freed);
17708 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
17709 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
17710 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
17715 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
17716 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
17720 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
17722 struct pbf_pN_cmd_regs cmd_regs[] = {
17723 {0, (CHIP_IS_E3B0(sc)) ?
17724 PBF_REG_TQ_OCCUPANCY_Q0 :
17725 PBF_REG_P0_TQ_OCCUPANCY,
17726 (CHIP_IS_E3B0(sc)) ?
17727 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
17728 PBF_REG_P0_TQ_LINES_FREED_CNT},
17729 {1, (CHIP_IS_E3B0(sc)) ?
17730 PBF_REG_TQ_OCCUPANCY_Q1 :
17731 PBF_REG_P1_TQ_OCCUPANCY,
17732 (CHIP_IS_E3B0(sc)) ?
17733 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
17734 PBF_REG_P1_TQ_LINES_FREED_CNT},
17735 {4, (CHIP_IS_E3B0(sc)) ?
17736 PBF_REG_TQ_OCCUPANCY_LB_Q :
17737 PBF_REG_P4_TQ_OCCUPANCY,
17738 (CHIP_IS_E3B0(sc)) ?
17739 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
17740 PBF_REG_P4_TQ_LINES_FREED_CNT}
17743 struct pbf_pN_buf_regs buf_regs[] = {
17744 {0, (CHIP_IS_E3B0(sc)) ?
17745 PBF_REG_INIT_CRD_Q0 :
17746 PBF_REG_P0_INIT_CRD ,
17747 (CHIP_IS_E3B0(sc)) ?
17748 PBF_REG_CREDIT_Q0 :
17750 (CHIP_IS_E3B0(sc)) ?
17751 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
17752 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
17753 {1, (CHIP_IS_E3B0(sc)) ?
17754 PBF_REG_INIT_CRD_Q1 :
17755 PBF_REG_P1_INIT_CRD,
17756 (CHIP_IS_E3B0(sc)) ?
17757 PBF_REG_CREDIT_Q1 :
17759 (CHIP_IS_E3B0(sc)) ?
17760 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
17761 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
17762 {4, (CHIP_IS_E3B0(sc)) ?
17763 PBF_REG_INIT_CRD_LB_Q :
17764 PBF_REG_P4_INIT_CRD,
17765 (CHIP_IS_E3B0(sc)) ?
17766 PBF_REG_CREDIT_LB_Q :
17768 (CHIP_IS_E3B0(sc)) ?
17769 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
17770 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
17775 /* Verify the command queues are flushed P0, P1, P4 */
17776 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
17777 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
17780 /* Verify the transmission buffers are flushed P0, P1, P4 */
17781 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
17782 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
17787 bxe_hw_enable_status(struct bxe_softc *sc)
17791 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
17792 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
17794 val = REG_RD(sc, PBF_REG_DISABLE_PF);
17795 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
17797 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
17798 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
17800 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
17801 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
17803 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
17804 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
17806 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
17807 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
17809 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
17810 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
17812 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
17813 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
17817 bxe_pf_flr_clnup(struct bxe_softc *sc)
17819 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
17821 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
17823 /* Re-enable PF target read access */
17824 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
17826 /* Poll HW usage counters */
17827 BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
17828 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
17832 /* Zero the igu 'trailing edge' and 'leading edge' */
17834 /* Send the FW cleanup command */
17835 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
17841 /* Verify TX hw is flushed */
17842 bxe_tx_hw_flushed(sc, poll_cnt);
17844 /* Wait 100ms (not adjusted according to platform) */
17847 /* Verify no pending pci transactions */
17848 if (bxe_is_pcie_pending(sc)) {
17849 BLOGE(sc, "PCIE Transactions still pending\n");
17853 bxe_hw_enable_status(sc);
17856 * Master enable - Due to WB DMAE writes performed before this
17857 * register is re-initialized as part of the regular function init
17859 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17865 bxe_init_hw_func(struct bxe_softc *sc)
17867 int port = SC_PORT(sc);
17868 int func = SC_FUNC(sc);
17869 int init_phase = PHASE_PF0 + func;
17870 struct ecore_ilt *ilt = sc->ilt;
17871 uint16_t cdu_ilt_start;
17872 uint32_t addr, val;
17873 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
17874 int i, main_mem_width, rc;
17876 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
17879 if (!CHIP_IS_E1x(sc)) {
17880 rc = bxe_pf_flr_clnup(sc);
17882 BLOGE(sc, "FLR cleanup failed!\n");
17883 // XXX bxe_fw_dump(sc);
17884 // XXX bxe_idle_chk(sc);
17889 /* set MSI reconfigure capability */
17890 if (sc->devinfo.int_block == INT_BLOCK_HC) {
17891 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
17892 val = REG_RD(sc, addr);
17893 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
17894 REG_WR(sc, addr, val);
17897 ecore_init_block(sc, BLOCK_PXP, init_phase);
17898 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17901 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
17903 for (i = 0; i < L2_ILT_LINES(sc); i++) {
17904 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
17905 ilt->lines[cdu_ilt_start + i].page_mapping =
17906 sc->context[i].vcxt_dma.paddr;
17907 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
17909 ecore_ilt_init_op(sc, INITOP_SET);
17912 REG_WR(sc, PRS_REG_NIC_MODE, 1);
17913 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
17915 if (!CHIP_IS_E1x(sc)) {
17916 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
17918 /* Turn on a single ISR mode in IGU if driver is going to use
17921 if (sc->interrupt_mode != INTR_MODE_MSIX) {
17922 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
17926 * Timers workaround bug: function init part.
17927 * Need to wait 20msec after initializing ILT,
17928 * needed to make sure there are no requests in
17929 * one of the PXP internal queues with "old" ILT addresses
17934 * Master enable - Due to WB DMAE writes performed before this
17935 * register is re-initialized as part of the regular function
17938 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17939 /* Enable the function in IGU */
17940 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
17943 sc->dmae_ready = 1;
17945 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17947 if (!CHIP_IS_E1x(sc))
17948 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
17950 ecore_init_block(sc, BLOCK_ATC, init_phase);
17951 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17952 ecore_init_block(sc, BLOCK_NIG, init_phase);
17953 ecore_init_block(sc, BLOCK_SRC, init_phase);
17954 ecore_init_block(sc, BLOCK_MISC, init_phase);
17955 ecore_init_block(sc, BLOCK_TCM, init_phase);
17956 ecore_init_block(sc, BLOCK_UCM, init_phase);
17957 ecore_init_block(sc, BLOCK_CCM, init_phase);
17958 ecore_init_block(sc, BLOCK_XCM, init_phase);
17959 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17960 ecore_init_block(sc, BLOCK_USEM, init_phase);
17961 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17962 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17964 if (!CHIP_IS_E1x(sc))
17965 REG_WR(sc, QM_REG_PF_EN, 1);
17967 if (!CHIP_IS_E1x(sc)) {
17968 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17969 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17970 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17971 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
17973 ecore_init_block(sc, BLOCK_QM, init_phase);
17975 ecore_init_block(sc, BLOCK_TM, init_phase);
17976 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17978 bxe_iov_init_dq(sc);
17980 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17981 ecore_init_block(sc, BLOCK_PRS, init_phase);
17982 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17983 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17984 ecore_init_block(sc, BLOCK_USDM, init_phase);
17985 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17986 ecore_init_block(sc, BLOCK_UPB, init_phase);
17987 ecore_init_block(sc, BLOCK_XPB, init_phase);
17988 ecore_init_block(sc, BLOCK_PBF, init_phase);
17989 if (!CHIP_IS_E1x(sc))
17990 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
17992 ecore_init_block(sc, BLOCK_CDU, init_phase);
17994 ecore_init_block(sc, BLOCK_CFC, init_phase);
17996 if (!CHIP_IS_E1x(sc))
17997 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18000 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18001 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18004 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18006 /* HC init per function */
18007 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18008 if (CHIP_IS_E1H(sc)) {
18009 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18011 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18012 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18014 ecore_init_block(sc, BLOCK_HC, init_phase);
18017 int num_segs, sb_idx, prod_offset;
18019 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18021 if (!CHIP_IS_E1x(sc)) {
18022 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18023 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18026 ecore_init_block(sc, BLOCK_IGU, init_phase);
18028 if (!CHIP_IS_E1x(sc)) {
18032 * E2 mode: address 0-135 match to the mapping memory;
18033 * 136 - PF0 default prod; 137 - PF1 default prod;
18034 * 138 - PF2 default prod; 139 - PF3 default prod;
18035 * 140 - PF0 attn prod; 141 - PF1 attn prod;
18036 * 142 - PF2 attn prod; 143 - PF3 attn prod;
18037 * 144-147 reserved.
18039 * E1.5 mode - In backward compatible mode;
18040 * for non default SB; each even line in the memory
18041 * holds the U producer and each odd line hold
18042 * the C producer. The first 128 producers are for
18043 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18044 * producers are for the DSB for each PF.
18045 * Each PF has five segments: (the order inside each
18046 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18047 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18048 * 144-147 attn prods;
18050 /* non-default-status-blocks */
18051 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18052 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18053 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18054 prod_offset = (sc->igu_base_sb + sb_idx) *
18057 for (i = 0; i < num_segs; i++) {
18058 addr = IGU_REG_PROD_CONS_MEMORY +
18059 (prod_offset + i) * 4;
18060 REG_WR(sc, addr, 0);
18062 /* send consumer update with value 0 */
18063 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18064 USTORM_ID, 0, IGU_INT_NOP, 1);
18065 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18068 /* default-status-blocks */
18069 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18070 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18072 if (CHIP_IS_MODE_4_PORT(sc))
18073 dsb_idx = SC_FUNC(sc);
18075 dsb_idx = SC_VN(sc);
18077 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18078 IGU_BC_BASE_DSB_PROD + dsb_idx :
18079 IGU_NORM_BASE_DSB_PROD + dsb_idx);
18082 * igu prods come in chunks of E1HVN_MAX (4) -
18083 * does not matters what is the current chip mode
18085 for (i = 0; i < (num_segs * E1HVN_MAX);
18087 addr = IGU_REG_PROD_CONS_MEMORY +
18088 (prod_offset + i)*4;
18089 REG_WR(sc, addr, 0);
18091 /* send consumer update with 0 */
18092 if (CHIP_INT_MODE_IS_BC(sc)) {
18093 bxe_ack_sb(sc, sc->igu_dsb_id,
18094 USTORM_ID, 0, IGU_INT_NOP, 1);
18095 bxe_ack_sb(sc, sc->igu_dsb_id,
18096 CSTORM_ID, 0, IGU_INT_NOP, 1);
18097 bxe_ack_sb(sc, sc->igu_dsb_id,
18098 XSTORM_ID, 0, IGU_INT_NOP, 1);
18099 bxe_ack_sb(sc, sc->igu_dsb_id,
18100 TSTORM_ID, 0, IGU_INT_NOP, 1);
18101 bxe_ack_sb(sc, sc->igu_dsb_id,
18102 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18104 bxe_ack_sb(sc, sc->igu_dsb_id,
18105 USTORM_ID, 0, IGU_INT_NOP, 1);
18106 bxe_ack_sb(sc, sc->igu_dsb_id,
18107 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18109 bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18111 /* !!! these should become driver const once
18112 rf-tool supports split-68 const */
18113 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18114 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18115 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18116 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18117 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18118 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18122 /* Reset PCIE errors for debug */
18123 REG_WR(sc, 0x2114, 0xffffffff);
18124 REG_WR(sc, 0x2120, 0xffffffff);
18126 if (CHIP_IS_E1x(sc)) {
18127 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18128 main_mem_base = HC_REG_MAIN_MEMORY +
18129 SC_PORT(sc) * (main_mem_size * 4);
18130 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18131 main_mem_width = 8;
18133 val = REG_RD(sc, main_mem_prty_clr);
18135 BLOGD(sc, DBG_LOAD,
18136 "Parity errors in HC block during function init (0x%x)!\n",
18140 /* Clear "false" parity errors in MSI-X table */
18141 for (i = main_mem_base;
18142 i < main_mem_base + main_mem_size * 4;
18143 i += main_mem_width) {
18144 bxe_read_dmae(sc, i, main_mem_width / 4);
18145 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18146 i, main_mem_width / 4);
18148 /* Clear HC parity attention */
18149 REG_RD(sc, main_mem_prty_clr);
18153 /* Enable STORMs SP logging */
18154 REG_WR8(sc, BAR_USTRORM_INTMEM +
18155 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18156 REG_WR8(sc, BAR_TSTRORM_INTMEM +
18157 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18158 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18159 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18160 REG_WR8(sc, BAR_XSTRORM_INTMEM +
18161 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18164 elink_phy_probe(&sc->link_params);
18170 bxe_link_reset(struct bxe_softc *sc)
18172 if (!BXE_NOMCP(sc)) {
18173 bxe_acquire_phy_lock(sc);
18174 elink_lfa_reset(&sc->link_params, &sc->link_vars);
18175 bxe_release_phy_lock(sc);
18177 if (!CHIP_REV_IS_SLOW(sc)) {
18178 BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18184 bxe_reset_port(struct bxe_softc *sc)
18186 int port = SC_PORT(sc);
18189 ELINK_DEBUG_P0(sc, "bxe_reset_port called\n");
18190 /* reset physical Link */
18191 bxe_link_reset(sc);
18193 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18195 /* Do not rcv packets to BRB */
18196 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18197 /* Do not direct rcv packets that are not for MCP to the BRB */
18198 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18199 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18201 /* Configure AEU */
18202 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18206 /* Check for BRB port occupancy */
18207 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18209 BLOGD(sc, DBG_LOAD,
18210 "BRB1 is not empty, %d blocks are occupied\n", val);
18213 /* TODO: Close Doorbell port? */
18217 bxe_ilt_wr(struct bxe_softc *sc,
18222 uint32_t wb_write[2];
18224 if (CHIP_IS_E1(sc)) {
18225 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18227 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18230 wb_write[0] = ONCHIP_ADDR1(addr);
18231 wb_write[1] = ONCHIP_ADDR2(addr);
18232 REG_WR_DMAE(sc, reg, wb_write, 2);
18236 bxe_clear_func_ilt(struct bxe_softc *sc,
18239 uint32_t i, base = FUNC_ILT_BASE(func);
18240 for (i = base; i < base + ILT_PER_FUNC; i++) {
18241 bxe_ilt_wr(sc, i, 0);
18246 bxe_reset_func(struct bxe_softc *sc)
18248 struct bxe_fastpath *fp;
18249 int port = SC_PORT(sc);
18250 int func = SC_FUNC(sc);
18253 /* Disable the function in the FW */
18254 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18255 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18256 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18257 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18260 FOR_EACH_ETH_QUEUE(sc, i) {
18262 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18263 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18268 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18269 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18272 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18273 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18276 /* Configure IGU */
18277 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18278 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18279 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18281 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18282 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18285 if (CNIC_LOADED(sc)) {
18286 /* Disable Timer scan */
18287 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18289 * Wait for at least 10ms and up to 2 second for the timers
18292 for (i = 0; i < 200; i++) {
18294 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18300 bxe_clear_func_ilt(sc, func);
18303 * Timers workaround bug for E2: if this is vnic-3,
18304 * we need to set the entire ilt range for this timers.
18306 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18307 struct ilt_client_info ilt_cli;
18308 /* use dummy TM client */
18309 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18311 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18312 ilt_cli.client_num = ILT_CLIENT_TM;
18314 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18317 /* this assumes that reset_port() called before reset_func()*/
18318 if (!CHIP_IS_E1x(sc)) {
18319 bxe_pf_disable(sc);
18322 sc->dmae_ready = 0;
18326 bxe_gunzip_init(struct bxe_softc *sc)
18332 bxe_gunzip_end(struct bxe_softc *sc)
18338 bxe_init_firmware(struct bxe_softc *sc)
18340 if (CHIP_IS_E1(sc)) {
18341 ecore_init_e1_firmware(sc);
18342 sc->iro_array = e1_iro_arr;
18343 } else if (CHIP_IS_E1H(sc)) {
18344 ecore_init_e1h_firmware(sc);
18345 sc->iro_array = e1h_iro_arr;
18346 } else if (!CHIP_IS_E1x(sc)) {
18347 ecore_init_e2_firmware(sc);
18348 sc->iro_array = e2_iro_arr;
18350 BLOGE(sc, "Unsupported chip revision\n");
18358 bxe_release_firmware(struct bxe_softc *sc)
18365 ecore_gunzip(struct bxe_softc *sc,
18366 const uint8_t *zbuf,
18369 /* XXX : Implement... */
18370 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18375 ecore_reg_wr_ind(struct bxe_softc *sc,
18379 bxe_reg_wr_ind(sc, addr, val);
18383 ecore_write_dmae_phys_len(struct bxe_softc *sc,
18384 bus_addr_t phys_addr,
18388 bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18392 ecore_storm_memset_struct(struct bxe_softc *sc,
18398 for (i = 0; i < size/4; i++) {
18399 REG_WR(sc, addr + (i * 4), data[i]);
18405 * character device - ioctl interface definitions
18409 #include "bxe_dump.h"
18410 #include "bxe_ioctl.h"
18411 #include <sys/conf.h>
18413 static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
18414 struct thread *td);
18416 static struct cdevsw bxe_cdevsw = {
18417 .d_version = D_VERSION,
18418 .d_ioctl = bxe_eioctl,
18419 .d_name = "bxecnic",
18422 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1))
18425 #define DUMP_ALL_PRESETS 0x1FFF
18426 #define DUMP_MAX_PRESETS 13
18427 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
18428 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
18429 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
18430 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
18431 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
18433 #define IS_REG_IN_PRESET(presets, idx) \
18434 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
18438 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset)
18440 if (CHIP_IS_E1(sc))
18441 return dump_num_registers[0][preset-1];
18442 else if (CHIP_IS_E1H(sc))
18443 return dump_num_registers[1][preset-1];
18444 else if (CHIP_IS_E2(sc))
18445 return dump_num_registers[2][preset-1];
18446 else if (CHIP_IS_E3A0(sc))
18447 return dump_num_registers[3][preset-1];
18448 else if (CHIP_IS_E3B0(sc))
18449 return dump_num_registers[4][preset-1];
18455 bxe_get_total_regs_len32(struct bxe_softc *sc)
18457 uint32_t preset_idx;
18458 int regdump_len32 = 0;
18461 /* Calculate the total preset regs length */
18462 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18463 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx);
18466 return regdump_len32;
18469 static const uint32_t *
18470 __bxe_get_page_addr_ar(struct bxe_softc *sc)
18472 if (CHIP_IS_E2(sc))
18473 return page_vals_e2;
18474 else if (CHIP_IS_E3(sc))
18475 return page_vals_e3;
18481 __bxe_get_page_reg_num(struct bxe_softc *sc)
18483 if (CHIP_IS_E2(sc))
18484 return PAGE_MODE_VALUES_E2;
18485 else if (CHIP_IS_E3(sc))
18486 return PAGE_MODE_VALUES_E3;
18491 static const uint32_t *
18492 __bxe_get_page_write_ar(struct bxe_softc *sc)
18494 if (CHIP_IS_E2(sc))
18495 return page_write_regs_e2;
18496 else if (CHIP_IS_E3(sc))
18497 return page_write_regs_e3;
18503 __bxe_get_page_write_num(struct bxe_softc *sc)
18505 if (CHIP_IS_E2(sc))
18506 return PAGE_WRITE_REGS_E2;
18507 else if (CHIP_IS_E3(sc))
18508 return PAGE_WRITE_REGS_E3;
18513 static const struct reg_addr *
18514 __bxe_get_page_read_ar(struct bxe_softc *sc)
18516 if (CHIP_IS_E2(sc))
18517 return page_read_regs_e2;
18518 else if (CHIP_IS_E3(sc))
18519 return page_read_regs_e3;
18525 __bxe_get_page_read_num(struct bxe_softc *sc)
18527 if (CHIP_IS_E2(sc))
18528 return PAGE_READ_REGS_E2;
18529 else if (CHIP_IS_E3(sc))
18530 return PAGE_READ_REGS_E3;
18536 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info)
18538 if (CHIP_IS_E1(sc))
18539 return IS_E1_REG(reg_info->chips);
18540 else if (CHIP_IS_E1H(sc))
18541 return IS_E1H_REG(reg_info->chips);
18542 else if (CHIP_IS_E2(sc))
18543 return IS_E2_REG(reg_info->chips);
18544 else if (CHIP_IS_E3A0(sc))
18545 return IS_E3A0_REG(reg_info->chips);
18546 else if (CHIP_IS_E3B0(sc))
18547 return IS_E3B0_REG(reg_info->chips);
18553 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info)
18555 if (CHIP_IS_E1(sc))
18556 return IS_E1_REG(wreg_info->chips);
18557 else if (CHIP_IS_E1H(sc))
18558 return IS_E1H_REG(wreg_info->chips);
18559 else if (CHIP_IS_E2(sc))
18560 return IS_E2_REG(wreg_info->chips);
18561 else if (CHIP_IS_E3A0(sc))
18562 return IS_E3A0_REG(wreg_info->chips);
18563 else if (CHIP_IS_E3B0(sc))
18564 return IS_E3B0_REG(wreg_info->chips);
18570 * bxe_read_pages_regs - read "paged" registers
18572 * @bp device handle
18575 * Reads "paged" memories: memories that may only be read by first writing to a
18576 * specific address ("write address") and then reading from a specific address
18577 * ("read address"). There may be more than one write address per "page" and
18578 * more than one read address per write address.
18581 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18583 uint32_t i, j, k, n;
18585 /* addresses of the paged registers */
18586 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc);
18587 /* number of paged registers */
18588 int num_pages = __bxe_get_page_reg_num(sc);
18589 /* write addresses */
18590 const uint32_t *write_addr = __bxe_get_page_write_ar(sc);
18591 /* number of write addresses */
18592 int write_num = __bxe_get_page_write_num(sc);
18593 /* read addresses info */
18594 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc);
18595 /* number of read addresses */
18596 int read_num = __bxe_get_page_read_num(sc);
18597 uint32_t addr, size;
18599 for (i = 0; i < num_pages; i++) {
18600 for (j = 0; j < write_num; j++) {
18601 REG_WR(sc, write_addr[j], page_addr[i]);
18603 for (k = 0; k < read_num; k++) {
18604 if (IS_REG_IN_PRESET(read_addr[k].presets, preset)) {
18605 size = read_addr[k].size;
18606 for (n = 0; n < size; n++) {
18607 addr = read_addr[k].addr + n*4;
18608 *p++ = REG_RD(sc, addr);
18619 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset)
18621 uint32_t i, j, addr;
18622 const struct wreg_addr *wreg_addr_p = NULL;
18624 if (CHIP_IS_E1(sc))
18625 wreg_addr_p = &wreg_addr_e1;
18626 else if (CHIP_IS_E1H(sc))
18627 wreg_addr_p = &wreg_addr_e1h;
18628 else if (CHIP_IS_E2(sc))
18629 wreg_addr_p = &wreg_addr_e2;
18630 else if (CHIP_IS_E3A0(sc))
18631 wreg_addr_p = &wreg_addr_e3;
18632 else if (CHIP_IS_E3B0(sc))
18633 wreg_addr_p = &wreg_addr_e3b0;
18637 /* Read the idle_chk registers */
18638 for (i = 0; i < IDLE_REGS_COUNT; i++) {
18639 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) &&
18640 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
18641 for (j = 0; j < idle_reg_addrs[i].size; j++)
18642 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);
18646 /* Read the regular registers */
18647 for (i = 0; i < REGS_COUNT; i++) {
18648 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) &&
18649 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
18650 for (j = 0; j < reg_addrs[i].size; j++)
18651 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4);
18655 /* Read the CAM registers */
18656 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) &&
18657 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
18658 for (i = 0; i < wreg_addr_p->size; i++) {
18659 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4);
18661 /* In case of wreg_addr register, read additional
18662 registers from read_regs array
18664 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
18665 addr = *(wreg_addr_p->read_regs);
18666 *p++ = REG_RD(sc, addr + j*4);
18671 /* Paged registers are supported in E2 & E3 only */
18672 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
18673 /* Read "paged" registers */
18674 bxe_read_pages_regs(sc, p, preset);
18681 bxe_grc_dump(struct bxe_softc *sc)
18684 uint32_t preset_idx;
18687 struct dump_header *d_hdr;
18691 uint32_t cmd_offset;
18692 struct ecore_ilt *ilt = SC_ILT(sc);
18693 struct bxe_fastpath *fp;
18694 struct ilt_client_info *ilt_cli;
18698 if (sc->grcdump_done || sc->grcdump_started)
18701 sc->grcdump_started = 1;
18702 BLOGI(sc, "Started collecting grcdump\n");
18704 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
18705 sizeof(struct dump_header);
18707 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT);
18709 if (sc->grc_dump == NULL) {
18710 BLOGW(sc, "Unable to allocate memory for grcdump collection\n");
18716 /* Disable parity attentions as long as following dump may
18717 * cause false alarms by reading never written registers. We
18718 * will re-enable parity attentions right after the dump.
18721 /* Disable parity on path 0 */
18722 bxe_pretend_func(sc, 0);
18724 ecore_disable_blocks_parity(sc);
18726 /* Disable parity on path 1 */
18727 bxe_pretend_func(sc, 1);
18728 ecore_disable_blocks_parity(sc);
18730 /* Return to current function */
18731 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18733 buf = sc->grc_dump;
18734 d_hdr = sc->grc_dump;
18736 d_hdr->header_size = (sizeof(struct dump_header) >> 2) - 1;
18737 d_hdr->version = BNX2X_DUMP_VERSION;
18738 d_hdr->preset = DUMP_ALL_PRESETS;
18740 if (CHIP_IS_E1(sc)) {
18741 d_hdr->dump_meta_data = DUMP_CHIP_E1;
18742 } else if (CHIP_IS_E1H(sc)) {
18743 d_hdr->dump_meta_data = DUMP_CHIP_E1H;
18744 } else if (CHIP_IS_E2(sc)) {
18745 d_hdr->dump_meta_data = DUMP_CHIP_E2 |
18746 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18747 } else if (CHIP_IS_E3A0(sc)) {
18748 d_hdr->dump_meta_data = DUMP_CHIP_E3A0 |
18749 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18750 } else if (CHIP_IS_E3B0(sc)) {
18751 d_hdr->dump_meta_data = DUMP_CHIP_E3B0 |
18752 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0);
18755 buf += sizeof(struct dump_header);
18757 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
18759 /* Skip presets with IOR */
18760 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) ||
18761 (preset_idx == 11))
18764 rval = bxe_get_preset_regs(sc, (uint32_t *)buf, preset_idx);
18769 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t));
18774 bxe_pretend_func(sc, 0);
18775 ecore_clear_blocks_parity(sc);
18776 ecore_enable_blocks_parity(sc);
18778 bxe_pretend_func(sc, 1);
18779 ecore_clear_blocks_parity(sc);
18780 ecore_enable_blocks_parity(sc);
18782 /* Return to current function */
18783 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
18787 if(sc->state == BXE_STATE_OPEN) {
18788 if(sc->fw_stats_req != NULL) {
18789 BLOGI(sc, "fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n",
18790 (uintmax_t)sc->fw_stats_req_mapping,
18791 (uintmax_t)sc->fw_stats_data_mapping,
18792 sc->fw_stats_req, (sc->fw_stats_req_size + sc->fw_stats_data_size));
18794 if(sc->def_sb != NULL) {
18795 BLOGI(sc, "def_status_block paddr %p vaddr %p size 0x%zx\n",
18796 (void *)sc->def_sb_dma.paddr, sc->def_sb,
18797 sizeof(struct host_sp_status_block));
18799 if(sc->eq_dma.vaddr != NULL) {
18800 BLOGI(sc, "event_queue paddr %#jx vaddr %p size 0x%x\n",
18801 (uintmax_t)sc->eq_dma.paddr, sc->eq_dma.vaddr, BCM_PAGE_SIZE);
18803 if(sc->sp_dma.vaddr != NULL) {
18804 BLOGI(sc, "slow path paddr %#jx vaddr %p size 0x%zx\n",
18805 (uintmax_t)sc->sp_dma.paddr, sc->sp_dma.vaddr,
18806 sizeof(struct bxe_slowpath));
18808 if(sc->spq_dma.vaddr != NULL) {
18809 BLOGI(sc, "slow path queue paddr %#jx vaddr %p size 0x%x\n",
18810 (uintmax_t)sc->spq_dma.paddr, sc->spq_dma.vaddr, BCM_PAGE_SIZE);
18812 if(sc->gz_buf_dma.vaddr != NULL) {
18813 BLOGI(sc, "fw_buf paddr %#jx vaddr %p size 0x%x\n",
18814 (uintmax_t)sc->gz_buf_dma.paddr, sc->gz_buf_dma.vaddr,
18817 for (i = 0; i < sc->num_queues; i++) {
18819 if(fp->sb_dma.vaddr != NULL && fp->tx_dma.vaddr != NULL &&
18820 fp->rx_dma.vaddr != NULL && fp->rcq_dma.vaddr != NULL &&
18821 fp->rx_sge_dma.vaddr != NULL) {
18823 BLOGI(sc, "FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
18824 (uintmax_t)fp->sb_dma.paddr, fp->sb_dma.vaddr,
18825 sizeof(union bxe_host_hc_status_block));
18826 BLOGI(sc, "TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18827 (uintmax_t)fp->tx_dma.paddr, fp->tx_dma.vaddr,
18828 (BCM_PAGE_SIZE * TX_BD_NUM_PAGES));
18829 BLOGI(sc, "RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18830 (uintmax_t)fp->rx_dma.paddr, fp->rx_dma.vaddr,
18831 (BCM_PAGE_SIZE * RX_BD_NUM_PAGES));
18832 BLOGI(sc, "RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i,
18833 (uintmax_t)fp->rcq_dma.paddr, fp->rcq_dma.vaddr,
18834 (BCM_PAGE_SIZE * RCQ_NUM_PAGES));
18835 BLOGI(sc, "RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i,
18836 (uintmax_t)fp->rx_sge_dma.paddr, fp->rx_sge_dma.vaddr,
18837 (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES));
18841 ilt_cli = &ilt->clients[1];
18842 if(ilt->lines != NULL) {
18843 for (i = ilt_cli->start; i <= ilt_cli->end; i++) {
18844 BLOGI(sc, "ECORE_ILT paddr %#jx vaddr %p size 0x%x\n",
18845 (uintmax_t)(((struct bxe_dma *)((&ilt->lines[i])->page))->paddr),
18846 ((struct bxe_dma *)((&ilt->lines[i])->page))->vaddr, BCM_PAGE_SIZE);
18852 cmd_offset = DMAE_REG_CMD_MEM;
18853 for (i = 0; i < 224; i++) {
18854 reg_addr = (cmd_offset +(i * 4));
18855 reg_val = REG_RD(sc, reg_addr);
18856 BLOGI(sc, "DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i,
18857 reg_addr, reg_val);
18861 BLOGI(sc, "Collection of grcdump done\n");
18862 sc->grcdump_done = 1;
18867 bxe_add_cdev(struct bxe_softc *sc)
18869 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT);
18871 if (sc->eeprom == NULL) {
18872 BLOGW(sc, "Unable to alloc for eeprom size buffer\n");
18876 sc->ioctl_dev = make_dev(&bxe_cdevsw,
18877 sc->ifnet->if_dunit,
18882 if_name(sc->ifnet));
18884 if (sc->ioctl_dev == NULL) {
18885 free(sc->eeprom, M_DEVBUF);
18890 sc->ioctl_dev->si_drv1 = sc;
18896 bxe_del_cdev(struct bxe_softc *sc)
18898 if (sc->ioctl_dev != NULL)
18899 destroy_dev(sc->ioctl_dev);
18901 if (sc->eeprom != NULL) {
18902 free(sc->eeprom, M_DEVBUF);
18905 sc->ioctl_dev = NULL;
18910 static bool bxe_is_nvram_accessible(struct bxe_softc *sc)
18913 if ((sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) == 0)
18921 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18925 if(!bxe_is_nvram_accessible(sc)) {
18926 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18929 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len);
18936 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len)
18940 if(!bxe_is_nvram_accessible(sc)) {
18941 BLOGW(sc, "Cannot access eeprom when interface is down\n");
18944 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len);
18950 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom)
18954 switch (eeprom->eeprom_cmd) {
18956 case BXE_EEPROM_CMD_SET_EEPROM:
18958 rval = copyin(eeprom->eeprom_data, sc->eeprom,
18959 eeprom->eeprom_data_len);
18964 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18965 eeprom->eeprom_data_len);
18968 case BXE_EEPROM_CMD_GET_EEPROM:
18970 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset,
18971 eeprom->eeprom_data_len);
18977 rval = copyout(sc->eeprom, eeprom->eeprom_data,
18978 eeprom->eeprom_data_len);
18987 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval);
18994 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p)
18996 uint32_t ext_phy_config;
18997 int port = SC_PORT(sc);
18998 int cfg_idx = bxe_get_link_cfg_idx(sc);
19000 dev_p->supported = sc->port.supported[cfg_idx] |
19001 (sc->port.supported[cfg_idx ^ 1] &
19002 (ELINK_SUPPORTED_TP | ELINK_SUPPORTED_FIBRE));
19003 dev_p->advertising = sc->port.advertising[cfg_idx];
19004 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type ==
19005 ELINK_ETH_PHY_SFP_1G_FIBER) {
19006 dev_p->supported = ~(ELINK_SUPPORTED_10000baseT_Full);
19007 dev_p->advertising &= ~(ADVERTISED_10000baseT_Full);
19009 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up &&
19010 !(sc->flags & BXE_MF_FUNC_DIS)) {
19011 dev_p->duplex = sc->link_vars.duplex;
19012 if (IS_MF(sc) && !BXE_NOMCP(sc))
19013 dev_p->speed = bxe_get_mf_speed(sc);
19015 dev_p->speed = sc->link_vars.line_speed;
19017 dev_p->duplex = DUPLEX_UNKNOWN;
19018 dev_p->speed = SPEED_UNKNOWN;
19021 dev_p->port = bxe_media_detect(sc);
19023 ext_phy_config = SHMEM_RD(sc,
19024 dev_info.port_hw_config[port].external_phy_config);
19025 if((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) ==
19026 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
19027 dev_p->phy_address = sc->port.phy_addr;
19028 else if(((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
19030 ((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) !=
19031 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
19032 dev_p->phy_address = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
19034 dev_p->phy_address = 0;
19036 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG)
19037 dev_p->autoneg = AUTONEG_ENABLE;
19039 dev_p->autoneg = AUTONEG_DISABLE;
19046 bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
19049 struct bxe_softc *sc;
19052 bxe_grcdump_t *dump = NULL;
19054 bxe_drvinfo_t *drv_infop = NULL;
19055 bxe_dev_setting_t *dev_p;
19056 bxe_dev_setting_t dev_set;
19057 bxe_get_regs_t *reg_p;
19058 bxe_reg_rdw_t *reg_rdw_p;
19059 bxe_pcicfg_rdw_t *cfg_rdw_p;
19060 bxe_perm_mac_addr_t *mac_addr_p;
19063 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL)
19068 dump = (bxe_grcdump_t *)data;
19072 case BXE_GRC_DUMP_SIZE:
19073 dump->pci_func = sc->pcie_func;
19074 dump->grcdump_size =
19075 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19076 sizeof(struct dump_header);
19081 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) +
19082 sizeof(struct dump_header);
19083 if ((!sc->trigger_grcdump) || (dump->grcdump == NULL) ||
19084 (dump->grcdump_size < grc_dump_size)) {
19089 if((sc->trigger_grcdump) && (!sc->grcdump_done) &&
19090 (!sc->grcdump_started)) {
19091 rval = bxe_grc_dump(sc);
19094 if((!rval) && (sc->grcdump_done) && (sc->grcdump_started) &&
19095 (sc->grc_dump != NULL)) {
19096 dump->grcdump_dwords = grc_dump_size >> 2;
19097 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size);
19098 free(sc->grc_dump, M_DEVBUF);
19099 sc->grc_dump = NULL;
19100 sc->grcdump_started = 0;
19101 sc->grcdump_done = 0;
19107 drv_infop = (bxe_drvinfo_t *)data;
19108 snprintf(drv_infop->drv_name, BXE_DRV_NAME_LENGTH, "%s", "bxe");
19109 snprintf(drv_infop->drv_version, BXE_DRV_VERSION_LENGTH, "v:%s",
19110 BXE_DRIVER_VERSION);
19111 snprintf(drv_infop->mfw_version, BXE_MFW_VERSION_LENGTH, "%s",
19112 sc->devinfo.bc_ver_str);
19113 snprintf(drv_infop->stormfw_version, BXE_STORMFW_VERSION_LENGTH,
19114 "%s", sc->fw_ver_str);
19115 drv_infop->eeprom_dump_len = sc->devinfo.flash_size;
19116 drv_infop->reg_dump_len =
19117 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t))
19118 + sizeof(struct dump_header);
19119 snprintf(drv_infop->bus_info, BXE_BUS_INFO_LENGTH, "%d:%d:%d",
19120 sc->pcie_bus, sc->pcie_device, sc->pcie_func);
19123 case BXE_DEV_SETTING:
19124 dev_p = (bxe_dev_setting_t *)data;
19125 bxe_get_settings(sc, &dev_set);
19126 dev_p->supported = dev_set.supported;
19127 dev_p->advertising = dev_set.advertising;
19128 dev_p->speed = dev_set.speed;
19129 dev_p->duplex = dev_set.duplex;
19130 dev_p->port = dev_set.port;
19131 dev_p->phy_address = dev_set.phy_address;
19132 dev_p->autoneg = dev_set.autoneg;
19138 reg_p = (bxe_get_regs_t *)data;
19139 grc_dump_size = reg_p->reg_buf_len;
19141 if((!sc->grcdump_done) && (!sc->grcdump_started)) {
19144 if((sc->grcdump_done) && (sc->grcdump_started) &&
19145 (sc->grc_dump != NULL)) {
19146 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size);
19147 free(sc->grc_dump, M_DEVBUF);
19148 sc->grc_dump = NULL;
19149 sc->grcdump_started = 0;
19150 sc->grcdump_done = 0;
19156 reg_rdw_p = (bxe_reg_rdw_t *)data;
19157 if((reg_rdw_p->reg_cmd == BXE_READ_REG_CMD) &&
19158 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19159 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);
19161 if((reg_rdw_p->reg_cmd == BXE_WRITE_REG_CMD) &&
19162 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT))
19163 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val);
19167 case BXE_RDW_PCICFG:
19168 cfg_rdw_p = (bxe_pcicfg_rdw_t *)data;
19169 if(cfg_rdw_p->cfg_cmd == BXE_READ_PCICFG) {
19171 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id,
19172 cfg_rdw_p->cfg_width);
19174 } else if(cfg_rdw_p->cfg_cmd == BXE_WRITE_PCICFG) {
19175 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val,
19176 cfg_rdw_p->cfg_width);
19178 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n");
19183 mac_addr_p = (bxe_perm_mac_addr_t *)data;
19184 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s",
19189 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data);