2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #define BXE_DRIVER_VERSION "1.78.78"
34 #include "ecore_init.h"
35 #include "ecore_init_ops.h"
37 #include "57710_int_offsets.h"
38 #include "57711_int_offsets.h"
39 #include "57712_int_offsets.h"
42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these
43 * explicitly here for older kernels that don't include this changeset.
46 #define CTLTYPE_U64 CTLTYPE_QUAD
47 #define sysctl_handle_64 sysctl_handle_quad
51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these
52 * here as zero(0) for older kernels that don't include this changeset
53 * thereby masking the functionality.
56 #define CSUM_TCP_IPV6 0
57 #define CSUM_UDP_IPV6 0
61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap
62 * for older kernels that don't include this changeset.
64 #if __FreeBSD_version < 900035
65 #define pci_find_cap pci_find_extcap
68 #define BXE_DEF_SB_ATT_IDX 0x0001
69 #define BXE_DEF_SB_IDX 0x0002
72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per
73 * function HW initialization.
75 #define FLR_WAIT_USEC 10000 /* 10 msecs */
76 #define FLR_WAIT_INTERVAL 50 /* usecs */
77 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */
79 struct pbf_pN_buf_regs {
86 struct pbf_pN_cmd_regs {
93 * PCI Device ID Table used by bxe_probe().
95 #define BXE_DEVDESC_MAX 64
96 static struct bxe_device_type bxe_devs[] = {
100 PCI_ANY_ID, PCI_ANY_ID,
101 "QLogic NetXtreme II BCM57710 10GbE"
106 PCI_ANY_ID, PCI_ANY_ID,
107 "QLogic NetXtreme II BCM57711 10GbE"
112 PCI_ANY_ID, PCI_ANY_ID,
113 "QLogic NetXtreme II BCM57711E 10GbE"
118 PCI_ANY_ID, PCI_ANY_ID,
119 "QLogic NetXtreme II BCM57712 10GbE"
124 PCI_ANY_ID, PCI_ANY_ID,
125 "QLogic NetXtreme II BCM57712 MF 10GbE"
131 PCI_ANY_ID, PCI_ANY_ID,
132 "QLogic NetXtreme II BCM57712 VF 10GbE"
138 PCI_ANY_ID, PCI_ANY_ID,
139 "QLogic NetXtreme II BCM57800 10GbE"
144 PCI_ANY_ID, PCI_ANY_ID,
145 "QLogic NetXtreme II BCM57800 MF 10GbE"
151 PCI_ANY_ID, PCI_ANY_ID,
152 "QLogic NetXtreme II BCM57800 VF 10GbE"
158 PCI_ANY_ID, PCI_ANY_ID,
159 "QLogic NetXtreme II BCM57810 10GbE"
164 PCI_ANY_ID, PCI_ANY_ID,
165 "QLogic NetXtreme II BCM57810 MF 10GbE"
171 PCI_ANY_ID, PCI_ANY_ID,
172 "QLogic NetXtreme II BCM57810 VF 10GbE"
178 PCI_ANY_ID, PCI_ANY_ID,
179 "QLogic NetXtreme II BCM57811 10GbE"
184 PCI_ANY_ID, PCI_ANY_ID,
185 "QLogic NetXtreme II BCM57811 MF 10GbE"
191 PCI_ANY_ID, PCI_ANY_ID,
192 "QLogic NetXtreme II BCM57811 VF 10GbE"
198 PCI_ANY_ID, PCI_ANY_ID,
199 "QLogic NetXtreme II BCM57840 4x10GbE"
205 PCI_ANY_ID, PCI_ANY_ID,
206 "QLogic NetXtreme II BCM57840 2x20GbE"
212 PCI_ANY_ID, PCI_ANY_ID,
213 "QLogic NetXtreme II BCM57840 MF 10GbE"
219 PCI_ANY_ID, PCI_ANY_ID,
220 "QLogic NetXtreme II BCM57840 VF 10GbE"
228 MALLOC_DECLARE(M_BXE_ILT);
229 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer");
232 * FreeBSD device entry points.
234 static int bxe_probe(device_t);
235 static int bxe_attach(device_t);
236 static int bxe_detach(device_t);
237 static int bxe_shutdown(device_t);
240 * FreeBSD KLD module/device interface event handler method.
242 static device_method_t bxe_methods[] = {
243 /* Device interface (device_if.h) */
244 DEVMETHOD(device_probe, bxe_probe),
245 DEVMETHOD(device_attach, bxe_attach),
246 DEVMETHOD(device_detach, bxe_detach),
247 DEVMETHOD(device_shutdown, bxe_shutdown),
249 DEVMETHOD(device_suspend, bxe_suspend),
250 DEVMETHOD(device_resume, bxe_resume),
252 /* Bus interface (bus_if.h) */
253 DEVMETHOD(bus_print_child, bus_generic_print_child),
254 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
259 * FreeBSD KLD Module data declaration
261 static driver_t bxe_driver = {
262 "bxe", /* module name */
263 bxe_methods, /* event handler */
264 sizeof(struct bxe_softc) /* extra data */
268 * FreeBSD dev class is needed to manage dev instances and
269 * to associate with a bus type
271 static devclass_t bxe_devclass;
273 MODULE_DEPEND(bxe, pci, 1, 1, 1);
274 MODULE_DEPEND(bxe, ether, 1, 1, 1);
275 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
277 /* resources needed for unloading a previously loaded device */
279 #define BXE_PREV_WAIT_NEEDED 1
280 struct mtx bxe_prev_mtx;
281 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF);
282 struct bxe_prev_list_node {
283 LIST_ENTRY(bxe_prev_list_node) node;
287 uint8_t aer; /* XXX automatic error recovery */
290 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list);
292 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
294 /* Tunable device values... */
296 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
299 unsigned long bxe_debug = 0;
300 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug);
301 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN),
302 &bxe_debug, 0, "Debug logging mode");
304 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
305 static int bxe_interrupt_mode = INTR_MODE_MSIX;
306 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode);
307 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN,
308 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode");
310 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */
311 static int bxe_queue_count = 4;
312 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
313 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN,
314 &bxe_queue_count, 0, "Multi-Queue queue count");
316 /* max number of buffers per queue (default RX_BD_USABLE) */
317 static int bxe_max_rx_bufs = 0;
318 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs);
319 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN,
320 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue");
322 /* Host interrupt coalescing RX tick timer (usecs) */
323 static int bxe_hc_rx_ticks = 25;
324 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks);
325 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN,
326 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks");
328 /* Host interrupt coalescing TX tick timer (usecs) */
329 static int bxe_hc_tx_ticks = 50;
330 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks);
331 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN,
332 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks");
334 /* Maximum number of Rx packets to process at a time */
335 static int bxe_rx_budget = 0xffffffff;
336 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget);
337 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN,
338 &bxe_rx_budget, 0, "Rx processing budget");
340 /* Maximum LRO aggregation size */
341 static int bxe_max_aggregation_size = 0;
342 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size);
343 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN,
344 &bxe_max_aggregation_size, 0, "max aggregation size");
346 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */
347 static int bxe_mrrs = -1;
348 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
349 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN,
350 &bxe_mrrs, 0, "PCIe maximum read request size");
352 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */
353 static int bxe_autogreeen = 0;
354 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen);
355 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN,
356 &bxe_autogreeen, 0, "AutoGrEEEn support");
358 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */
359 static int bxe_udp_rss = 0;
360 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss);
361 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN,
362 &bxe_udp_rss, 0, "UDP RSS support");
365 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */
367 #define STATS_OFFSET32(stat_name) \
368 (offsetof(struct bxe_eth_stats, stat_name) / 4)
370 #define Q_STATS_OFFSET32(stat_name) \
371 (offsetof(struct bxe_eth_q_stats, stat_name) / 4)
373 static const struct {
377 #define STATS_FLAGS_PORT 1
378 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */
379 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
380 char string[STAT_NAME_LEN];
381 } bxe_eth_stats_arr[] = {
382 { STATS_OFFSET32(total_bytes_received_hi),
383 8, STATS_FLAGS_BOTH, "rx_bytes" },
384 { STATS_OFFSET32(error_bytes_received_hi),
385 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
386 { STATS_OFFSET32(total_unicast_packets_received_hi),
387 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
388 { STATS_OFFSET32(total_multicast_packets_received_hi),
389 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
390 { STATS_OFFSET32(total_broadcast_packets_received_hi),
391 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
392 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
393 8, STATS_FLAGS_PORT, "rx_crc_errors" },
394 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
395 8, STATS_FLAGS_PORT, "rx_align_errors" },
396 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
397 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
398 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
399 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
400 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
401 8, STATS_FLAGS_PORT, "rx_fragments" },
402 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
403 8, STATS_FLAGS_PORT, "rx_jabbers" },
404 { STATS_OFFSET32(no_buff_discard_hi),
405 8, STATS_FLAGS_BOTH, "rx_discards" },
406 { STATS_OFFSET32(mac_filter_discard),
407 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
408 { STATS_OFFSET32(mf_tag_discard),
409 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
410 { STATS_OFFSET32(pfc_frames_received_hi),
411 8, STATS_FLAGS_PORT, "pfc_frames_received" },
412 { STATS_OFFSET32(pfc_frames_sent_hi),
413 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
414 { STATS_OFFSET32(brb_drop_hi),
415 8, STATS_FLAGS_PORT, "rx_brb_discard" },
416 { STATS_OFFSET32(brb_truncate_hi),
417 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
418 { STATS_OFFSET32(pause_frames_received_hi),
419 8, STATS_FLAGS_PORT, "rx_pause_frames" },
420 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
421 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
422 { STATS_OFFSET32(nig_timer_max),
423 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
424 { STATS_OFFSET32(total_bytes_transmitted_hi),
425 8, STATS_FLAGS_BOTH, "tx_bytes" },
426 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
427 8, STATS_FLAGS_PORT, "tx_error_bytes" },
428 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
429 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
430 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
431 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
432 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
433 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
434 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
435 8, STATS_FLAGS_PORT, "tx_mac_errors" },
436 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
437 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
438 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
439 8, STATS_FLAGS_PORT, "tx_single_collisions" },
440 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
441 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
442 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
443 8, STATS_FLAGS_PORT, "tx_deferred" },
444 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
445 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
446 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
447 8, STATS_FLAGS_PORT, "tx_late_collisions" },
448 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
449 8, STATS_FLAGS_PORT, "tx_total_collisions" },
450 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
451 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
452 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
453 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
454 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
455 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
456 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
457 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
458 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
459 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
460 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
461 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
462 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
463 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
464 { STATS_OFFSET32(pause_frames_sent_hi),
465 8, STATS_FLAGS_PORT, "tx_pause_frames" },
466 { STATS_OFFSET32(total_tpa_aggregations_hi),
467 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
468 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
469 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
470 { STATS_OFFSET32(total_tpa_bytes_hi),
471 8, STATS_FLAGS_FUNC, "tpa_bytes"},
473 { STATS_OFFSET32(recoverable_error),
474 4, STATS_FLAGS_FUNC, "recoverable_errors" },
475 { STATS_OFFSET32(unrecoverable_error),
476 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
478 { STATS_OFFSET32(eee_tx_lpi),
479 4, STATS_FLAGS_PORT, "eee_tx_lpi"},
480 { STATS_OFFSET32(rx_calls),
481 4, STATS_FLAGS_FUNC, "rx_calls"},
482 { STATS_OFFSET32(rx_pkts),
483 4, STATS_FLAGS_FUNC, "rx_pkts"},
484 { STATS_OFFSET32(rx_tpa_pkts),
485 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"},
486 { STATS_OFFSET32(rx_soft_errors),
487 4, STATS_FLAGS_FUNC, "rx_soft_errors"},
488 { STATS_OFFSET32(rx_hw_csum_errors),
489 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"},
490 { STATS_OFFSET32(rx_ofld_frames_csum_ip),
491 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"},
492 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
493 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"},
494 { STATS_OFFSET32(rx_budget_reached),
495 4, STATS_FLAGS_FUNC, "rx_budget_reached"},
496 { STATS_OFFSET32(tx_pkts),
497 4, STATS_FLAGS_FUNC, "tx_pkts"},
498 { STATS_OFFSET32(tx_soft_errors),
499 4, STATS_FLAGS_FUNC, "tx_soft_errors"},
500 { STATS_OFFSET32(tx_ofld_frames_csum_ip),
501 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"},
502 { STATS_OFFSET32(tx_ofld_frames_csum_tcp),
503 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"},
504 { STATS_OFFSET32(tx_ofld_frames_csum_udp),
505 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"},
506 { STATS_OFFSET32(tx_ofld_frames_lso),
507 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"},
508 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
509 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"},
510 { STATS_OFFSET32(tx_encap_failures),
511 4, STATS_FLAGS_FUNC, "tx_encap_failures"},
512 { STATS_OFFSET32(tx_hw_queue_full),
513 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"},
514 { STATS_OFFSET32(tx_hw_max_queue_depth),
515 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"},
516 { STATS_OFFSET32(tx_dma_mapping_failure),
517 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"},
518 { STATS_OFFSET32(tx_max_drbr_queue_depth),
519 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"},
520 { STATS_OFFSET32(tx_window_violation_std),
521 4, STATS_FLAGS_FUNC, "tx_window_violation_std"},
522 { STATS_OFFSET32(tx_window_violation_tso),
523 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"},
525 { STATS_OFFSET32(tx_unsupported_tso_request_ipv6),
526 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_ipv6"},
527 { STATS_OFFSET32(tx_unsupported_tso_request_not_tcp),
528 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_not_tcp"},
530 { STATS_OFFSET32(tx_chain_lost_mbuf),
531 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"},
532 { STATS_OFFSET32(tx_frames_deferred),
533 4, STATS_FLAGS_FUNC, "tx_frames_deferred"},
534 { STATS_OFFSET32(tx_queue_xoff),
535 4, STATS_FLAGS_FUNC, "tx_queue_xoff"},
536 { STATS_OFFSET32(mbuf_defrag_attempts),
537 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"},
538 { STATS_OFFSET32(mbuf_defrag_failures),
539 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"},
540 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
541 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"},
542 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
543 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"},
544 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
545 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"},
546 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
547 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"},
548 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
549 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"},
550 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
551 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"},
552 { STATS_OFFSET32(mbuf_alloc_tx),
553 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"},
554 { STATS_OFFSET32(mbuf_alloc_rx),
555 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"},
556 { STATS_OFFSET32(mbuf_alloc_sge),
557 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"},
558 { STATS_OFFSET32(mbuf_alloc_tpa),
559 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"}
562 static const struct {
565 char string[STAT_NAME_LEN];
566 } bxe_eth_q_stats_arr[] = {
567 { Q_STATS_OFFSET32(total_bytes_received_hi),
569 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
570 8, "rx_ucast_packets" },
571 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
572 8, "rx_mcast_packets" },
573 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
574 8, "rx_bcast_packets" },
575 { Q_STATS_OFFSET32(no_buff_discard_hi),
577 { Q_STATS_OFFSET32(total_bytes_transmitted_hi),
579 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
580 8, "tx_ucast_packets" },
581 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
582 8, "tx_mcast_packets" },
583 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
584 8, "tx_bcast_packets" },
585 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
586 8, "tpa_aggregations" },
587 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
588 8, "tpa_aggregated_frames"},
589 { Q_STATS_OFFSET32(total_tpa_bytes_hi),
591 { Q_STATS_OFFSET32(rx_calls),
593 { Q_STATS_OFFSET32(rx_pkts),
595 { Q_STATS_OFFSET32(rx_tpa_pkts),
597 { Q_STATS_OFFSET32(rx_soft_errors),
598 4, "rx_soft_errors"},
599 { Q_STATS_OFFSET32(rx_hw_csum_errors),
600 4, "rx_hw_csum_errors"},
601 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip),
602 4, "rx_ofld_frames_csum_ip"},
603 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp),
604 4, "rx_ofld_frames_csum_tcp_udp"},
605 { Q_STATS_OFFSET32(rx_budget_reached),
606 4, "rx_budget_reached"},
607 { Q_STATS_OFFSET32(tx_pkts),
609 { Q_STATS_OFFSET32(tx_soft_errors),
610 4, "tx_soft_errors"},
611 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip),
612 4, "tx_ofld_frames_csum_ip"},
613 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp),
614 4, "tx_ofld_frames_csum_tcp"},
615 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp),
616 4, "tx_ofld_frames_csum_udp"},
617 { Q_STATS_OFFSET32(tx_ofld_frames_lso),
618 4, "tx_ofld_frames_lso"},
619 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits),
620 4, "tx_ofld_frames_lso_hdr_splits"},
621 { Q_STATS_OFFSET32(tx_encap_failures),
622 4, "tx_encap_failures"},
623 { Q_STATS_OFFSET32(tx_hw_queue_full),
624 4, "tx_hw_queue_full"},
625 { Q_STATS_OFFSET32(tx_hw_max_queue_depth),
626 4, "tx_hw_max_queue_depth"},
627 { Q_STATS_OFFSET32(tx_dma_mapping_failure),
628 4, "tx_dma_mapping_failure"},
629 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth),
630 4, "tx_max_drbr_queue_depth"},
631 { Q_STATS_OFFSET32(tx_window_violation_std),
632 4, "tx_window_violation_std"},
633 { Q_STATS_OFFSET32(tx_window_violation_tso),
634 4, "tx_window_violation_tso"},
636 { Q_STATS_OFFSET32(tx_unsupported_tso_request_ipv6),
637 4, "tx_unsupported_tso_request_ipv6"},
638 { Q_STATS_OFFSET32(tx_unsupported_tso_request_not_tcp),
639 4, "tx_unsupported_tso_request_not_tcp"},
641 { Q_STATS_OFFSET32(tx_chain_lost_mbuf),
642 4, "tx_chain_lost_mbuf"},
643 { Q_STATS_OFFSET32(tx_frames_deferred),
644 4, "tx_frames_deferred"},
645 { Q_STATS_OFFSET32(tx_queue_xoff),
647 { Q_STATS_OFFSET32(mbuf_defrag_attempts),
648 4, "mbuf_defrag_attempts"},
649 { Q_STATS_OFFSET32(mbuf_defrag_failures),
650 4, "mbuf_defrag_failures"},
651 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed),
652 4, "mbuf_rx_bd_alloc_failed"},
653 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed),
654 4, "mbuf_rx_bd_mapping_failed"},
655 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed),
656 4, "mbuf_rx_tpa_alloc_failed"},
657 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed),
658 4, "mbuf_rx_tpa_mapping_failed"},
659 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed),
660 4, "mbuf_rx_sge_alloc_failed"},
661 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed),
662 4, "mbuf_rx_sge_mapping_failed"},
663 { Q_STATS_OFFSET32(mbuf_alloc_tx),
665 { Q_STATS_OFFSET32(mbuf_alloc_rx),
667 { Q_STATS_OFFSET32(mbuf_alloc_sge),
668 4, "mbuf_alloc_sge"},
669 { Q_STATS_OFFSET32(mbuf_alloc_tpa),
673 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr)
674 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr)
677 static void bxe_cmng_fns_init(struct bxe_softc *sc,
680 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc);
681 static void storm_memset_cmng(struct bxe_softc *sc,
682 struct cmng_init *cmng,
684 static void bxe_set_reset_global(struct bxe_softc *sc);
685 static void bxe_set_reset_in_progress(struct bxe_softc *sc);
686 static uint8_t bxe_reset_is_done(struct bxe_softc *sc,
688 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc);
689 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc,
692 static void bxe_int_disable(struct bxe_softc *sc);
693 static int bxe_release_leader_lock(struct bxe_softc *sc);
694 static void bxe_pf_disable(struct bxe_softc *sc);
695 static void bxe_free_fp_buffers(struct bxe_softc *sc);
696 static inline void bxe_update_rx_prod(struct bxe_softc *sc,
697 struct bxe_fastpath *fp,
700 uint16_t rx_sge_prod);
701 static void bxe_link_report_locked(struct bxe_softc *sc);
702 static void bxe_link_report(struct bxe_softc *sc);
703 static void bxe_link_status_update(struct bxe_softc *sc);
704 static void bxe_periodic_callout_func(void *xsc);
705 static void bxe_periodic_start(struct bxe_softc *sc);
706 static void bxe_periodic_stop(struct bxe_softc *sc);
707 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
710 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
712 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
714 static uint8_t bxe_txeof(struct bxe_softc *sc,
715 struct bxe_fastpath *fp);
716 static void bxe_task_fp(struct bxe_fastpath *fp);
717 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc,
720 static int bxe_alloc_mem(struct bxe_softc *sc);
721 static void bxe_free_mem(struct bxe_softc *sc);
722 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc);
723 static void bxe_free_fw_stats_mem(struct bxe_softc *sc);
724 static int bxe_interrupt_attach(struct bxe_softc *sc);
725 static void bxe_interrupt_detach(struct bxe_softc *sc);
726 static void bxe_set_rx_mode(struct bxe_softc *sc);
727 static int bxe_init_locked(struct bxe_softc *sc);
728 static int bxe_stop_locked(struct bxe_softc *sc);
729 static __noinline int bxe_nic_load(struct bxe_softc *sc,
731 static __noinline int bxe_nic_unload(struct bxe_softc *sc,
732 uint32_t unload_mode,
735 static void bxe_handle_sp_tq(void *context, int pending);
736 static void bxe_handle_rx_mode_tq(void *context, int pending);
737 static void bxe_handle_fp_tq(void *context, int pending);
740 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */
742 calc_crc32(uint8_t *crc32_packet,
743 uint32_t crc32_length,
752 uint8_t current_byte = 0;
753 uint32_t crc32_result = crc32_seed;
754 const uint32_t CRC32_POLY = 0x1edc6f41;
756 if ((crc32_packet == NULL) ||
757 (crc32_length == 0) ||
758 ((crc32_length % 8) != 0))
760 return (crc32_result);
763 for (byte = 0; byte < crc32_length; byte = byte + 1)
765 current_byte = crc32_packet[byte];
766 for (bit = 0; bit < 8; bit = bit + 1)
768 /* msb = crc32_result[31]; */
769 msb = (uint8_t)(crc32_result >> 31);
771 crc32_result = crc32_result << 1;
773 /* it (msb != current_byte[bit]) */
774 if (msb != (0x1 & (current_byte >> bit)))
776 crc32_result = crc32_result ^ CRC32_POLY;
777 /* crc32_result[0] = 1 */
784 * 1. "mirror" every bit
785 * 2. swap the 4 bytes
786 * 3. complement each bit
791 shft = sizeof(crc32_result) * 8 - 1;
793 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1)
796 temp |= crc32_result & 1;
800 /* temp[31-bit] = crc32_result[bit] */
804 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */
806 uint32_t t0, t1, t2, t3;
807 t0 = (0x000000ff & (temp >> 24));
808 t1 = (0x0000ff00 & (temp >> 8));
809 t2 = (0x00ff0000 & (temp << 8));
810 t3 = (0xff000000 & (temp << 24));
811 crc32_result = t0 | t1 | t2 | t3;
817 crc32_result = ~crc32_result;
820 return (crc32_result);
825 volatile unsigned long *addr)
827 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0);
831 bxe_set_bit(unsigned int nr,
832 volatile unsigned long *addr)
834 atomic_set_acq_long(addr, (1 << nr));
838 bxe_clear_bit(int nr,
839 volatile unsigned long *addr)
841 atomic_clear_acq_long(addr, (1 << nr));
845 bxe_test_and_set_bit(int nr,
846 volatile unsigned long *addr)
852 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0);
853 // if (x & nr) bit_was_set; else bit_was_not_set;
858 bxe_test_and_clear_bit(int nr,
859 volatile unsigned long *addr)
865 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0);
866 // if (x & nr) bit_was_set; else bit_was_not_set;
871 bxe_cmpxchg(volatile int *addr,
878 } while (atomic_cmpset_acq_int(addr, old, new) == 0);
883 * Get DMA memory from the OS.
885 * Validates that the OS has provided DMA buffers in response to a
886 * bus_dmamap_load call and saves the physical address of those buffers.
887 * When the callback is used the OS will return 0 for the mapping function
888 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
889 * failures back to the caller.
895 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
897 struct bxe_dma *dma = arg;
902 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error);
904 dma->paddr = segs->ds_addr;
907 BLOGD(dma->sc, DBG_LOAD,
908 "DMA alloc '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n",
909 dma->msg, dma->vaddr, (void *)dma->paddr,
910 dma->nseg, dma->size);
916 * Allocate a block of memory and map it for DMA. No partial completions
917 * allowed and release any resources acquired if we can't acquire all
921 * 0 = Success, !0 = Failure
924 bxe_dma_alloc(struct bxe_softc *sc,
932 BLOGE(sc, "dma block '%s' already has size %lu\n", msg,
933 (unsigned long)dma->size);
937 memset(dma, 0, sizeof(*dma)); /* sanity */
940 snprintf(dma->msg, sizeof(dma->msg), "%s", msg);
942 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
943 BCM_PAGE_SIZE, /* alignment */
944 0, /* boundary limit */
945 BUS_SPACE_MAXADDR, /* restricted low */
946 BUS_SPACE_MAXADDR, /* restricted hi */
947 NULL, /* addr filter() */
948 NULL, /* addr filter() arg */
949 size, /* max map size */
950 1, /* num discontinuous */
951 size, /* max seg size */
952 BUS_DMA_ALLOCNOW, /* flags */
954 NULL, /* lock() arg */
955 &dma->tag); /* returned dma tag */
957 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc);
958 memset(dma, 0, sizeof(*dma));
962 rc = bus_dmamem_alloc(dma->tag,
963 (void **)&dma->vaddr,
964 (BUS_DMA_NOWAIT | BUS_DMA_ZERO),
967 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc);
968 bus_dma_tag_destroy(dma->tag);
969 memset(dma, 0, sizeof(*dma));
973 rc = bus_dmamap_load(dma->tag,
977 bxe_dma_map_addr, /* BLOGD in here */
981 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc);
982 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
983 bus_dma_tag_destroy(dma->tag);
984 memset(dma, 0, sizeof(*dma));
992 bxe_dma_free(struct bxe_softc *sc,
998 "DMA free '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n",
999 dma->msg, dma->vaddr, (void *)dma->paddr,
1000 dma->nseg, dma->size);
1003 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL"));
1005 bus_dmamap_sync(dma->tag, dma->map,
1006 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE));
1007 bus_dmamap_unload(dma->tag, dma->map);
1008 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1009 bus_dma_tag_destroy(dma->tag);
1012 memset(dma, 0, sizeof(*dma));
1016 * These indirect read and write routines are only during init.
1017 * The locking is handled by the MCP.
1021 bxe_reg_wr_ind(struct bxe_softc *sc,
1025 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1026 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
1027 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1031 bxe_reg_rd_ind(struct bxe_softc *sc,
1036 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4);
1037 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
1038 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
1044 void bxe_dp_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int msglvl)
1046 uint32_t src_type = dmae->opcode & DMAE_COMMAND_SRC;
1048 switch (dmae->opcode & DMAE_COMMAND_DST) {
1049 case DMAE_CMD_DST_PCI:
1050 if (src_type == DMAE_CMD_SRC_PCI)
1051 DP(msglvl, "DMAE: opcode 0x%08x\n"
1052 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
1053 "comp_addr [%x:%08x], comp_val 0x%08x\n",
1054 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1055 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
1056 dmae->comp_addr_hi, dmae->comp_addr_lo,
1059 DP(msglvl, "DMAE: opcode 0x%08x\n"
1060 "src [%08x], len [%d*4], dst [%x:%08x]\n"
1061 "comp_addr [%x:%08x], comp_val 0x%08x\n",
1062 dmae->opcode, dmae->src_addr_lo >> 2,
1063 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
1064 dmae->comp_addr_hi, dmae->comp_addr_lo,
1067 case DMAE_CMD_DST_GRC:
1068 if (src_type == DMAE_CMD_SRC_PCI)
1069 DP(msglvl, "DMAE: opcode 0x%08x\n"
1070 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
1071 "comp_addr [%x:%08x], comp_val 0x%08x\n",
1072 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1073 dmae->len, dmae->dst_addr_lo >> 2,
1074 dmae->comp_addr_hi, dmae->comp_addr_lo,
1077 DP(msglvl, "DMAE: opcode 0x%08x\n"
1078 "src [%08x], len [%d*4], dst [%08x]\n"
1079 "comp_addr [%x:%08x], comp_val 0x%08x\n",
1080 dmae->opcode, dmae->src_addr_lo >> 2,
1081 dmae->len, dmae->dst_addr_lo >> 2,
1082 dmae->comp_addr_hi, dmae->comp_addr_lo,
1086 if (src_type == DMAE_CMD_SRC_PCI)
1087 DP(msglvl, "DMAE: opcode 0x%08x\n"
1088 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
1089 "comp_addr [%x:%08x] comp_val 0x%08x\n",
1090 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
1091 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
1094 DP(msglvl, "DMAE: opcode 0x%08x\n"
1095 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
1096 "comp_addr [%x:%08x] comp_val 0x%08x\n",
1097 dmae->opcode, dmae->src_addr_lo >> 2,
1098 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
1107 bxe_acquire_hw_lock(struct bxe_softc *sc,
1110 uint32_t lock_status;
1111 uint32_t resource_bit = (1 << resource);
1112 int func = SC_FUNC(sc);
1113 uint32_t hw_lock_control_reg;
1116 /* validate the resource is within range */
1117 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1118 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource);
1123 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1125 hw_lock_control_reg =
1126 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1129 /* validate the resource is not already taken */
1130 lock_status = REG_RD(sc, hw_lock_control_reg);
1131 if (lock_status & resource_bit) {
1132 BLOGE(sc, "resource in use (status 0x%x bit 0x%x)\n",
1133 lock_status, resource_bit);
1137 /* try every 5ms for 5 seconds */
1138 for (cnt = 0; cnt < 1000; cnt++) {
1139 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit);
1140 lock_status = REG_RD(sc, hw_lock_control_reg);
1141 if (lock_status & resource_bit) {
1147 BLOGE(sc, "Resource lock timeout!\n");
1152 bxe_release_hw_lock(struct bxe_softc *sc,
1155 uint32_t lock_status;
1156 uint32_t resource_bit = (1 << resource);
1157 int func = SC_FUNC(sc);
1158 uint32_t hw_lock_control_reg;
1160 /* validate the resource is within range */
1161 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1162 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource);
1167 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8));
1169 hw_lock_control_reg =
1170 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8));
1173 /* validate the resource is currently taken */
1174 lock_status = REG_RD(sc, hw_lock_control_reg);
1175 if (!(lock_status & resource_bit)) {
1176 BLOGE(sc, "resource not in use (status 0x%x bit 0x%x)\n",
1177 lock_status, resource_bit);
1181 REG_WR(sc, hw_lock_control_reg, resource_bit);
1186 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise,
1187 * had we done things the other way around, if two pfs from the same port
1188 * would attempt to access nvram at the same time, we could run into a
1190 * pf A takes the port lock.
1191 * pf B succeeds in taking the same lock since they are from the same port.
1192 * pf A takes the per pf misc lock. Performs eeprom access.
1193 * pf A finishes. Unlocks the per pf misc lock.
1194 * Pf B takes the lock and proceeds to perform it's own access.
1195 * pf A unlocks the per port lock, while pf B is still working (!).
1196 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1197 * access corrupted by pf B).*
1200 bxe_acquire_nvram_lock(struct bxe_softc *sc)
1202 int port = SC_PORT(sc);
1206 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1207 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1209 /* adjust timeout for emulation/FPGA */
1210 count = NVRAM_TIMEOUT_COUNT;
1211 if (CHIP_REV_IS_SLOW(sc)) {
1215 /* request access to nvram interface */
1216 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1217 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1219 for (i = 0; i < count*10; i++) {
1220 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1221 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1228 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1229 BLOGE(sc, "Cannot get access to nvram interface\n");
1237 bxe_release_nvram_lock(struct bxe_softc *sc)
1239 int port = SC_PORT(sc);
1243 /* adjust timeout for emulation/FPGA */
1244 count = NVRAM_TIMEOUT_COUNT;
1245 if (CHIP_REV_IS_SLOW(sc)) {
1249 /* relinquish nvram interface */
1250 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
1251 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1253 for (i = 0; i < count*10; i++) {
1254 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
1255 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1262 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1263 BLOGE(sc, "Cannot free access to nvram interface\n");
1267 /* release HW lock: protect against other PFs in PF Direct Assignment */
1268 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM);
1274 bxe_enable_nvram_access(struct bxe_softc *sc)
1278 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1280 /* enable both bits, even on read */
1281 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1282 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN));
1286 bxe_disable_nvram_access(struct bxe_softc *sc)
1290 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1292 /* disable both bits, even after read */
1293 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1294 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1295 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1299 bxe_nvram_read_dword(struct bxe_softc *sc,
1307 /* build the command word */
1308 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1310 /* need to clear DONE bit separately */
1311 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1313 /* address of the NVRAM to read from */
1314 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1315 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1317 /* issue a read command */
1318 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1320 /* adjust timeout for emulation/FPGA */
1321 count = NVRAM_TIMEOUT_COUNT;
1322 if (CHIP_REV_IS_SLOW(sc)) {
1326 /* wait for completion */
1329 for (i = 0; i < count; i++) {
1331 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1333 if (val & MCPR_NVM_COMMAND_DONE) {
1334 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
1335 /* we read nvram data in cpu order
1336 * but ethtool sees it as an array of bytes
1337 * converting to big-endian will do the work
1339 *ret_val = htobe32(val);
1346 BLOGE(sc, "nvram read timeout expired\n");
1353 bxe_nvram_read(struct bxe_softc *sc,
1362 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1363 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1368 if ((offset + buf_size) > sc->devinfo.flash_size) {
1369 BLOGE(sc, "Invalid parameter, "
1370 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1371 offset, buf_size, sc->devinfo.flash_size);
1375 /* request access to nvram interface */
1376 rc = bxe_acquire_nvram_lock(sc);
1381 /* enable access to nvram interface */
1382 bxe_enable_nvram_access(sc);
1384 /* read the first word(s) */
1385 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1386 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
1387 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1388 memcpy(ret_buf, &val, 4);
1390 /* advance to the next dword */
1391 offset += sizeof(uint32_t);
1392 ret_buf += sizeof(uint32_t);
1393 buf_size -= sizeof(uint32_t);
1398 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1399 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
1400 memcpy(ret_buf, &val, 4);
1403 /* disable access to nvram interface */
1404 bxe_disable_nvram_access(sc);
1405 bxe_release_nvram_lock(sc);
1411 bxe_nvram_write_dword(struct bxe_softc *sc,
1418 /* build the command word */
1419 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR);
1421 /* need to clear DONE bit separately */
1422 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1424 /* write the data */
1425 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
1427 /* address of the NVRAM to write to */
1428 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
1429 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1431 /* issue the write command */
1432 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1434 /* adjust timeout for emulation/FPGA */
1435 count = NVRAM_TIMEOUT_COUNT;
1436 if (CHIP_REV_IS_SLOW(sc)) {
1440 /* wait for completion */
1442 for (i = 0; i < count; i++) {
1444 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
1445 if (val & MCPR_NVM_COMMAND_DONE) {
1452 BLOGE(sc, "nvram write timeout expired\n");
1458 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1461 bxe_nvram_write1(struct bxe_softc *sc,
1467 uint32_t align_offset;
1471 if ((offset + buf_size) > sc->devinfo.flash_size) {
1472 BLOGE(sc, "Invalid parameter, "
1473 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1474 offset, buf_size, sc->devinfo.flash_size);
1478 /* request access to nvram interface */
1479 rc = bxe_acquire_nvram_lock(sc);
1484 /* enable access to nvram interface */
1485 bxe_enable_nvram_access(sc);
1487 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1488 align_offset = (offset & ~0x03);
1489 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
1492 val &= ~(0xff << BYTE_OFFSET(offset));
1493 val |= (*data_buf << BYTE_OFFSET(offset));
1495 /* nvram data is returned as an array of bytes
1496 * convert it back to cpu order
1500 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
1503 /* disable access to nvram interface */
1504 bxe_disable_nvram_access(sc);
1505 bxe_release_nvram_lock(sc);
1511 bxe_nvram_write(struct bxe_softc *sc,
1518 uint32_t written_so_far;
1521 if (buf_size == 1) {
1522 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
1525 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) {
1526 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n",
1531 if (buf_size == 0) {
1532 return (0); /* nothing to do */
1535 if ((offset + buf_size) > sc->devinfo.flash_size) {
1536 BLOGE(sc, "Invalid parameter, "
1537 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n",
1538 offset, buf_size, sc->devinfo.flash_size);
1542 /* request access to nvram interface */
1543 rc = bxe_acquire_nvram_lock(sc);
1548 /* enable access to nvram interface */
1549 bxe_enable_nvram_access(sc);
1552 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1553 while ((written_so_far < buf_size) && (rc == 0)) {
1554 if (written_so_far == (buf_size - sizeof(uint32_t))) {
1555 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1556 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) {
1557 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1558 } else if ((offset % NVRAM_PAGE_SIZE) == 0) {
1559 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1562 memcpy(&val, data_buf, 4);
1564 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
1566 /* advance to the next dword */
1567 offset += sizeof(uint32_t);
1568 data_buf += sizeof(uint32_t);
1569 written_so_far += sizeof(uint32_t);
1573 /* disable access to nvram interface */
1574 bxe_disable_nvram_access(sc);
1575 bxe_release_nvram_lock(sc);
1580 /* copy command into DMAE command memory and set DMAE command Go */
1582 bxe_post_dmae(struct bxe_softc *sc,
1583 struct dmae_command *dmae,
1586 uint32_t cmd_offset;
1589 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx));
1590 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) {
1591 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i));
1594 REG_WR(sc, dmae_reg_go_c[idx], 1);
1598 bxe_dmae_opcode_add_comp(uint32_t opcode,
1601 return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
1602 DMAE_COMMAND_C_TYPE_ENABLE));
1606 bxe_dmae_opcode_clr_src_reset(uint32_t opcode)
1608 return (opcode & ~DMAE_COMMAND_SRC_RESET);
1612 bxe_dmae_opcode(struct bxe_softc *sc,
1618 uint32_t opcode = 0;
1620 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
1621 (dst_type << DMAE_COMMAND_DST_SHIFT));
1623 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET);
1625 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
1627 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) |
1628 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT));
1630 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
1633 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
1635 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
1639 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type);
1646 bxe_prep_dmae_with_comp(struct bxe_softc *sc,
1647 struct dmae_command *dmae,
1651 memset(dmae, 0, sizeof(struct dmae_command));
1653 /* set the opcode */
1654 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type,
1655 TRUE, DMAE_COMP_PCI);
1657 /* fill in the completion parameters */
1658 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
1659 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
1660 dmae->comp_val = DMAE_COMP_VAL;
1663 /* issue a DMAE command over the init channel and wait for completion */
1665 bxe_issue_dmae_with_comp(struct bxe_softc *sc,
1666 struct dmae_command *dmae)
1668 uint32_t *wb_comp = BXE_SP(sc, wb_comp);
1669 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000;
1673 /* reset completion */
1676 /* post the command on the channel used for initializations */
1677 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
1679 /* wait for completion */
1682 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
1684 (sc->recovery_state != BXE_RECOVERY_DONE &&
1685 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) {
1686 BLOGE(sc, "DMAE timeout!\n");
1687 BXE_DMAE_UNLOCK(sc);
1688 return (DMAE_TIMEOUT);
1695 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
1696 BLOGE(sc, "DMAE PCI error!\n");
1697 BXE_DMAE_UNLOCK(sc);
1698 return (DMAE_PCI_ERROR);
1701 BXE_DMAE_UNLOCK(sc);
1706 bxe_read_dmae(struct bxe_softc *sc,
1710 struct dmae_command dmae;
1714 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32));
1716 if (!sc->dmae_ready) {
1717 data = BXE_SP(sc, wb_data[0]);
1719 for (i = 0; i < len32; i++) {
1720 data[i] = (CHIP_IS_E1(sc)) ?
1721 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) :
1722 REG_RD(sc, (src_addr + (i * 4)));
1728 /* set opcode and fixed command fields */
1729 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
1731 /* fill in addresses and len */
1732 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */
1733 dmae.src_addr_hi = 0;
1734 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
1735 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
1738 /* issue the command and wait for completion */
1739 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1740 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1745 bxe_write_dmae(struct bxe_softc *sc,
1746 bus_addr_t dma_addr,
1750 struct dmae_command dmae;
1753 if (!sc->dmae_ready) {
1754 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32));
1756 if (CHIP_IS_E1(sc)) {
1757 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1759 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32);
1765 /* set opcode and fixed command fields */
1766 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
1768 /* fill in addresses and len */
1769 dmae.src_addr_lo = U64_LO(dma_addr);
1770 dmae.src_addr_hi = U64_HI(dma_addr);
1771 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */
1772 dmae.dst_addr_hi = 0;
1775 /* issue the command and wait for completion */
1776 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) {
1777 bxe_panic(sc, ("DMAE failed (%d)\n", rc));
1782 bxe_write_dmae_phys_len(struct bxe_softc *sc,
1783 bus_addr_t phys_addr,
1787 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
1790 while (len > dmae_wr_max) {
1792 (phys_addr + offset), /* src DMA address */
1793 (addr + offset), /* dst GRC address */
1795 offset += (dmae_wr_max * 4);
1800 (phys_addr + offset), /* src DMA address */
1801 (addr + offset), /* dst GRC address */
1806 bxe_set_ctx_validation(struct bxe_softc *sc,
1807 struct eth_context *cxt,
1810 /* ustorm cxt validation */
1811 cxt->ustorm_ag_context.cdu_usage =
1812 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1813 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
1814 /* xcontext validation */
1815 cxt->xstorm_ag_context.cdu_reserved =
1816 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid),
1817 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
1821 bxe_storm_memset_hc_timeout(struct bxe_softc *sc,
1828 (BAR_CSTRORM_INTMEM +
1829 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index));
1831 REG_WR8(sc, addr, ticks);
1834 "port %d fw_sb_id %d sb_index %d ticks %d\n",
1835 port, fw_sb_id, sb_index, ticks);
1839 bxe_storm_memset_hc_disable(struct bxe_softc *sc,
1845 uint32_t enable_flag =
1846 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
1848 (BAR_CSTRORM_INTMEM +
1849 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index));
1853 flags = REG_RD8(sc, addr);
1854 flags &= ~HC_INDEX_DATA_HC_ENABLED;
1855 flags |= enable_flag;
1856 REG_WR8(sc, addr, flags);
1859 "port %d fw_sb_id %d sb_index %d disable %d\n",
1860 port, fw_sb_id, sb_index, disable);
1864 bxe_update_coalesce_sb_index(struct bxe_softc *sc,
1870 int port = SC_PORT(sc);
1871 uint8_t ticks = (usec / 4); /* XXX ??? */
1873 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks);
1875 disable = (disable) ? 1 : ((usec) ? 0 : 1);
1876 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable);
1880 elink_cb_udelay(struct bxe_softc *sc,
1887 elink_cb_reg_read(struct bxe_softc *sc,
1890 return (REG_RD(sc, reg_addr));
1894 elink_cb_reg_write(struct bxe_softc *sc,
1898 REG_WR(sc, reg_addr, val);
1902 elink_cb_reg_wb_write(struct bxe_softc *sc,
1907 REG_WR_DMAE(sc, offset, wb_write, len);
1911 elink_cb_reg_wb_read(struct bxe_softc *sc,
1916 REG_RD_DMAE(sc, offset, wb_write, len);
1920 elink_cb_path_id(struct bxe_softc *sc)
1922 return (SC_PATH(sc));
1926 elink_cb_event_log(struct bxe_softc *sc,
1927 const elink_log_id_t elink_log_id,
1933 va_start(ap, elink_log_id);
1934 _XXX_(sc, lm_log_id, ap);
1937 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id);
1941 bxe_set_spio(struct bxe_softc *sc,
1947 /* Only 2 SPIOs are configurable */
1948 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
1949 BLOGE(sc, "Invalid SPIO 0x%x\n", spio);
1953 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1955 /* read SPIO and mask except the float bits */
1956 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
1959 case MISC_SPIO_OUTPUT_LOW:
1960 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio);
1961 /* clear FLOAT and set CLR */
1962 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1963 spio_reg |= (spio << MISC_SPIO_CLR_POS);
1966 case MISC_SPIO_OUTPUT_HIGH:
1967 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio);
1968 /* clear FLOAT and set SET */
1969 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
1970 spio_reg |= (spio << MISC_SPIO_SET_POS);
1973 case MISC_SPIO_INPUT_HI_Z:
1974 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio);
1976 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
1983 REG_WR(sc, MISC_REG_SPIO, spio_reg);
1984 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
1990 bxe_gpio_read(struct bxe_softc *sc,
1994 /* The GPIO should be swapped if swap register is set and active */
1995 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
1996 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
1997 int gpio_shift = (gpio_num +
1998 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
1999 uint32_t gpio_mask = (1 << gpio_shift);
2002 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2003 BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2007 /* read GPIO value */
2008 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2010 /* get the requested pin value */
2011 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0;
2015 bxe_gpio_write(struct bxe_softc *sc,
2020 /* The GPIO should be swapped if swap register is set and active */
2021 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2022 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2023 int gpio_shift = (gpio_num +
2024 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2025 uint32_t gpio_mask = (1 << gpio_shift);
2028 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2029 BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2033 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2035 /* read GPIO and mask except the float bits */
2036 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2039 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2041 "Set GPIO %d (shift %d) -> output low\n",
2042 gpio_num, gpio_shift);
2043 /* clear FLOAT and set CLR */
2044 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2045 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2048 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2050 "Set GPIO %d (shift %d) -> output high\n",
2051 gpio_num, gpio_shift);
2052 /* clear FLOAT and set SET */
2053 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2054 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2057 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2059 "Set GPIO %d (shift %d) -> input\n",
2060 gpio_num, gpio_shift);
2062 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2069 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2070 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2076 bxe_gpio_mult_write(struct bxe_softc *sc,
2082 /* any port swapping should be handled by caller */
2084 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2086 /* read GPIO and mask except the float bits */
2087 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
2088 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2089 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2090 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2093 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2094 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins);
2096 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2099 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2100 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins);
2102 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2105 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2106 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins);
2108 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2112 BLOGE(sc, "Invalid GPIO mode assignment %d\n", mode);
2113 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2117 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
2118 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2124 bxe_gpio_int_write(struct bxe_softc *sc,
2129 /* The GPIO should be swapped if swap register is set and active */
2130 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&
2131 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);
2132 int gpio_shift = (gpio_num +
2133 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0));
2134 uint32_t gpio_mask = (1 << gpio_shift);
2137 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2138 BLOGE(sc, "Invalid GPIO %d\n", gpio_num);
2142 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2145 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
2148 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2150 "Clear GPIO INT %d (shift %d) -> output low\n",
2151 gpio_num, gpio_shift);
2152 /* clear SET and set CLR */
2153 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2154 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2157 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2159 "Set GPIO INT %d (shift %d) -> output high\n",
2160 gpio_num, gpio_shift);
2161 /* clear CLR and set SET */
2162 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2163 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2170 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
2171 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
2177 elink_cb_gpio_read(struct bxe_softc *sc,
2181 return (bxe_gpio_read(sc, gpio_num, port));
2185 elink_cb_gpio_write(struct bxe_softc *sc,
2187 uint8_t mode, /* 0=low 1=high */
2190 return (bxe_gpio_write(sc, gpio_num, mode, port));
2194 elink_cb_gpio_mult_write(struct bxe_softc *sc,
2196 uint8_t mode) /* 0=low 1=high */
2198 return (bxe_gpio_mult_write(sc, pins, mode));
2202 elink_cb_gpio_int_write(struct bxe_softc *sc,
2204 uint8_t mode, /* 0=low 1=high */
2207 return (bxe_gpio_int_write(sc, gpio_num, mode, port));
2211 elink_cb_notify_link_changed(struct bxe_softc *sc)
2213 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 +
2214 (SC_FUNC(sc) * sizeof(uint32_t))), 1);
2217 /* send the MCP a request, block until there is a reply */
2219 elink_cb_fw_command(struct bxe_softc *sc,
2223 int mb_idx = SC_FW_MB_IDX(sc);
2227 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10;
2232 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param);
2233 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq));
2236 "wrote command 0x%08x to FW MB param 0x%08x\n",
2237 (command | seq), param);
2239 /* Let the FW do it's magic. GIve it up to 5 seconds... */
2241 DELAY(delay * 1000);
2242 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header);
2243 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2246 "[after %d ms] read 0x%x seq 0x%x from FW MB\n",
2247 cnt*delay, rc, seq);
2249 /* is this a reply to our command? */
2250 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
2251 rc &= FW_MSG_CODE_MASK;
2254 BLOGE(sc, "FW failed to respond!\n");
2255 // XXX bxe_fw_dump(sc);
2259 BXE_FWMB_UNLOCK(sc);
2264 bxe_fw_command(struct bxe_softc *sc,
2268 return (elink_cb_fw_command(sc, command, param));
2272 __storm_memset_dma_mapping(struct bxe_softc *sc,
2276 REG_WR(sc, addr, U64_LO(mapping));
2277 REG_WR(sc, (addr + 4), U64_HI(mapping));
2281 storm_memset_spq_addr(struct bxe_softc *sc,
2285 uint32_t addr = (XSEM_REG_FAST_MEMORY +
2286 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid));
2287 __storm_memset_dma_mapping(sc, addr, mapping);
2291 storm_memset_vf_to_pf(struct bxe_softc *sc,
2295 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2296 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2297 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2298 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id);
2302 storm_memset_func_en(struct bxe_softc *sc,
2306 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2307 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2308 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2309 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable);
2313 storm_memset_eq_data(struct bxe_softc *sc,
2314 struct event_ring_data *eq_data,
2320 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid));
2321 size = sizeof(struct event_ring_data);
2322 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data);
2326 storm_memset_eq_prod(struct bxe_softc *sc,
2330 uint32_t addr = (BAR_CSTRORM_INTMEM +
2331 CSTORM_EVENT_RING_PROD_OFFSET(pfid));
2332 REG_WR16(sc, addr, eq_prod);
2336 * Post a slowpath command.
2338 * A slowpath command is used to propogate a configuration change through
2339 * the controller in a controlled manner, allowing each STORM processor and
2340 * other H/W blocks to phase in the change. The commands sent on the
2341 * slowpath are referred to as ramrods. Depending on the ramrod used the
2342 * completion of the ramrod will occur in different ways. Here's a
2343 * breakdown of ramrods and how they complete:
2345 * RAMROD_CMD_ID_ETH_PORT_SETUP
2346 * Used to setup the leading connection on a port. Completes on the
2347 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
2349 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
2350 * Used to setup an additional connection on a port. Completes on the
2351 * RCQ of the multi-queue/RSS connection being initialized.
2353 * RAMROD_CMD_ID_ETH_STAT_QUERY
2354 * Used to force the storm processors to update the statistics database
2355 * in host memory. This ramrod is send on the leading connection CID and
2356 * completes as an index increment of the CSTORM on the default status
2359 * RAMROD_CMD_ID_ETH_UPDATE
2360 * Used to update the state of the leading connection, usually to udpate
2361 * the RSS indirection table. Completes on the RCQ of the leading
2362 * connection. (Not currently used under FreeBSD until OS support becomes
2365 * RAMROD_CMD_ID_ETH_HALT
2366 * Used when tearing down a connection prior to driver unload. Completes
2367 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
2368 * use this on the leading connection.
2370 * RAMROD_CMD_ID_ETH_SET_MAC
2371 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
2372 * the RCQ of the leading connection.
2374 * RAMROD_CMD_ID_ETH_CFC_DEL
2375 * Used when tearing down a conneciton prior to driver unload. Completes
2376 * on the RCQ of the leading connection (since the current connection
2377 * has been completely removed from controller memory).
2379 * RAMROD_CMD_ID_ETH_PORT_DEL
2380 * Used to tear down the leading connection prior to driver unload,
2381 * typically fp[0]. Completes as an index increment of the CSTORM on the
2382 * default status block.
2384 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
2385 * Used for connection offload. Completes on the RCQ of the multi-queue
2386 * RSS connection that is being offloaded. (Not currently used under
2389 * There can only be one command pending per function.
2392 * 0 = Success, !0 = Failure.
2395 /* must be called under the spq lock */
2397 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc)
2399 struct eth_spe *next_spe = sc->spq_prod_bd;
2401 if (sc->spq_prod_bd == sc->spq_last_bd) {
2402 /* wrap back to the first eth_spq */
2403 sc->spq_prod_bd = sc->spq;
2404 sc->spq_prod_idx = 0;
2413 /* must be called under the spq lock */
2415 void bxe_sp_prod_update(struct bxe_softc *sc)
2417 int func = SC_FUNC(sc);
2420 * Make sure that BD data is updated before writing the producer.
2421 * BD data is written to the memory, the producer is read from the
2422 * memory, thus we need a full memory barrier to ensure the ordering.
2426 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)),
2429 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
2430 BUS_SPACE_BARRIER_WRITE);
2434 * bxe_is_contextless_ramrod - check if the current command ends on EQ
2436 * @cmd: command to check
2437 * @cmd_type: command type
2440 int bxe_is_contextless_ramrod(int cmd,
2443 if ((cmd_type == NONE_CONNECTION_TYPE) ||
2444 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
2445 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
2446 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
2447 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
2448 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
2449 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) {
2457 * bxe_sp_post - place a single command on an SP ring
2459 * @sc: driver handle
2460 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
2461 * @cid: SW CID the command is related to
2462 * @data_hi: command private data address (high 32 bits)
2463 * @data_lo: command private data address (low 32 bits)
2464 * @cmd_type: command type (e.g. NONE, ETH)
2466 * SP data is handled as if it's always an address pair, thus data fields are
2467 * not swapped to little endian in upper functions. Instead this function swaps
2468 * data as if it's two uint32 fields.
2471 bxe_sp_post(struct bxe_softc *sc,
2478 struct eth_spe *spe;
2482 common = bxe_is_contextless_ramrod(command, cmd_type);
2487 if (!atomic_load_acq_long(&sc->eq_spq_left)) {
2488 BLOGE(sc, "EQ ring is full!\n");
2493 if (!atomic_load_acq_long(&sc->cq_spq_left)) {
2494 BLOGE(sc, "SPQ ring is full!\n");
2500 spe = bxe_sp_get_next(sc);
2502 /* CID needs port number to be encoded int it */
2503 spe->hdr.conn_and_cmd_data =
2504 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid));
2506 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
2508 /* TBD: Check if it works for VFs */
2509 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) &
2510 SPE_HDR_FUNCTION_ID);
2512 spe->hdr.type = htole16(type);
2514 spe->data.update_data_addr.hi = htole32(data_hi);
2515 spe->data.update_data_addr.lo = htole32(data_lo);
2518 * It's ok if the actual decrement is issued towards the memory
2519 * somewhere between the lock and unlock. Thus no more explict
2520 * memory barrier is needed.
2523 atomic_subtract_acq_long(&sc->eq_spq_left, 1);
2525 atomic_subtract_acq_long(&sc->cq_spq_left, 1);
2528 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr);
2529 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n",
2530 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata));
2532 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n",
2534 (uint32_t)U64_HI(sc->spq_dma.paddr),
2535 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq),
2542 atomic_load_acq_long(&sc->cq_spq_left),
2543 atomic_load_acq_long(&sc->eq_spq_left));
2545 bxe_sp_prod_update(sc);
2552 * bxe_debug_print_ind_table - prints the indirection table configuration.
2554 * @sc: driver hanlde
2555 * @p: pointer to rss configuration
2559 bxe_debug_print_ind_table(struct bxe_softc *sc,
2560 struct ecore_config_rss_params *p)
2564 BLOGD(sc, DBG_LOAD, "Setting indirection table to:\n");
2565 BLOGD(sc, DBG_LOAD, " 0x0000: ");
2566 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2567 BLOGD(sc, DBG_LOAD, "0x%02x ", p->ind_table[i]);
2569 /* Print 4 bytes in a line */
2570 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) &&
2571 (((i + 1) & 0x3) == 0)) {
2572 BLOGD(sc, DBG_LOAD, "\n");
2573 BLOGD(sc, DBG_LOAD, "0x%04x: ", i + 1);
2577 BLOGD(sc, DBG_LOAD, "\n");
2582 * FreeBSD Device probe function.
2584 * Compares the device found to the driver's list of supported devices and
2585 * reports back to the bsd loader whether this is the right driver for the device.
2586 * This is the driver entry function called from the "kldload" command.
2589 * BUS_PROBE_DEFAULT on success, positive value on failure.
2592 bxe_probe(device_t dev)
2594 struct bxe_softc *sc;
2595 struct bxe_device_type *t;
2597 uint16_t did, sdid, svid, vid;
2599 /* Find our device structure */
2600 sc = device_get_softc(dev);
2604 /* Get the data for the device to be probed. */
2605 vid = pci_get_vendor(dev);
2606 did = pci_get_device(dev);
2607 svid = pci_get_subvendor(dev);
2608 sdid = pci_get_subdevice(dev);
2611 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
2612 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
2614 /* Look through the list of known devices for a match. */
2615 while (t->bxe_name != NULL) {
2616 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
2617 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
2618 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
2619 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
2620 if (descbuf == NULL)
2623 /* Print out the device identity. */
2624 snprintf(descbuf, BXE_DEVDESC_MAX,
2625 "%s (%c%d) BXE v:%s\n", t->bxe_name,
2626 (((pci_read_config(dev, PCIR_REVID, 4) &
2628 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
2629 BXE_DRIVER_VERSION);
2631 device_set_desc_copy(dev, descbuf);
2632 free(descbuf, M_TEMP);
2633 return (BUS_PROBE_DEFAULT);
2642 bxe_init_mutexes(struct bxe_softc *sc)
2644 #ifdef BXE_CORE_LOCK_SX
2645 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name),
2646 "bxe%d_core_lock", sc->unit);
2647 sx_init(&sc->core_sx, sc->core_sx_name);
2649 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name),
2650 "bxe%d_core_lock", sc->unit);
2651 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF);
2654 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name),
2655 "bxe%d_sp_lock", sc->unit);
2656 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF);
2658 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name),
2659 "bxe%d_dmae_lock", sc->unit);
2660 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF);
2662 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name),
2663 "bxe%d_phy_lock", sc->unit);
2664 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF);
2666 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name),
2667 "bxe%d_fwmb_lock", sc->unit);
2668 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF);
2670 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name),
2671 "bxe%d_print_lock", sc->unit);
2672 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF);
2674 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name),
2675 "bxe%d_stats_lock", sc->unit);
2676 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF);
2678 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name),
2679 "bxe%d_mcast_lock", sc->unit);
2680 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF);
2684 bxe_release_mutexes(struct bxe_softc *sc)
2686 #ifdef BXE_CORE_LOCK_SX
2687 sx_destroy(&sc->core_sx);
2689 if (mtx_initialized(&sc->core_mtx)) {
2690 mtx_destroy(&sc->core_mtx);
2694 if (mtx_initialized(&sc->sp_mtx)) {
2695 mtx_destroy(&sc->sp_mtx);
2698 if (mtx_initialized(&sc->dmae_mtx)) {
2699 mtx_destroy(&sc->dmae_mtx);
2702 if (mtx_initialized(&sc->port.phy_mtx)) {
2703 mtx_destroy(&sc->port.phy_mtx);
2706 if (mtx_initialized(&sc->fwmb_mtx)) {
2707 mtx_destroy(&sc->fwmb_mtx);
2710 if (mtx_initialized(&sc->print_mtx)) {
2711 mtx_destroy(&sc->print_mtx);
2714 if (mtx_initialized(&sc->stats_mtx)) {
2715 mtx_destroy(&sc->stats_mtx);
2718 if (mtx_initialized(&sc->mcast_mtx)) {
2719 mtx_destroy(&sc->mcast_mtx);
2724 bxe_tx_disable(struct bxe_softc* sc)
2726 struct ifnet *ifp = sc->ifnet;
2728 /* tell the stack the driver is stopped and TX queue is full */
2730 ifp->if_drv_flags = 0;
2735 bxe_drv_pulse(struct bxe_softc *sc)
2737 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb,
2738 sc->fw_drv_pulse_wr_seq);
2741 static inline uint16_t
2742 bxe_tx_avail(struct bxe_softc *sc,
2743 struct bxe_fastpath *fp)
2749 prod = fp->tx_bd_prod;
2750 cons = fp->tx_bd_cons;
2752 used = SUB_S16(prod, cons);
2755 KASSERT((used < 0), ("used tx bds < 0"));
2756 KASSERT((used > sc->tx_ring_size), ("used tx bds > tx_ring_size"));
2757 KASSERT(((sc->tx_ring_size - used) > MAX_TX_AVAIL),
2758 ("invalid number of tx bds used"));
2761 return (int16_t)(sc->tx_ring_size) - used;
2765 bxe_tx_queue_has_work(struct bxe_fastpath *fp)
2769 mb(); /* status block fields can change */
2770 hw_cons = le16toh(*fp->tx_cons_sb);
2771 return (hw_cons != fp->tx_pkt_cons);
2774 static inline uint8_t
2775 bxe_has_tx_work(struct bxe_fastpath *fp)
2777 /* expand this for multi-cos if ever supported */
2778 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE;
2782 bxe_has_rx_work(struct bxe_fastpath *fp)
2784 uint16_t rx_cq_cons_sb;
2786 mb(); /* status block fields can change */
2787 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb);
2788 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX)
2790 return (fp->rx_cq_cons != rx_cq_cons_sb);
2794 bxe_sp_event(struct bxe_softc *sc,
2795 struct bxe_fastpath *fp,
2796 union eth_rx_cqe *rr_cqe)
2798 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2799 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
2800 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX;
2801 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
2803 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n",
2804 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type);
2808 * If cid is within VF range, replace the slowpath object with the
2809 * one corresponding to this VF
2811 if ((cid >= BXE_FIRST_VF_CID) && (cid < BXE_FIRST_VF_CID + BXE_VF_CIDS)) {
2812 bxe_iov_set_queue_sp_obj(sc, cid, &q_obj);
2817 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
2818 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid);
2819 drv_cmd = ECORE_Q_CMD_UPDATE;
2822 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
2823 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid);
2824 drv_cmd = ECORE_Q_CMD_SETUP;
2827 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
2828 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
2829 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY;
2832 case (RAMROD_CMD_ID_ETH_HALT):
2833 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid);
2834 drv_cmd = ECORE_Q_CMD_HALT;
2837 case (RAMROD_CMD_ID_ETH_TERMINATE):
2838 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid);
2839 drv_cmd = ECORE_Q_CMD_TERMINATE;
2842 case (RAMROD_CMD_ID_ETH_EMPTY):
2843 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid);
2844 drv_cmd = ECORE_Q_CMD_EMPTY;
2848 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n",
2849 command, fp->index);
2853 if ((drv_cmd != ECORE_Q_CMD_MAX) &&
2854 q_obj->complete_cmd(sc, q_obj, drv_cmd)) {
2856 * q_obj->complete_cmd() failure means that this was
2857 * an unexpected completion.
2859 * In this case we don't want to increase the sc->spq_left
2860 * because apparently we haven't sent this command the first
2863 // bxe_panic(sc, ("Unexpected SP completion\n"));
2868 /* SRIOV: reschedule any 'in_progress' operations */
2869 bxe_iov_sp_event(sc, cid, TRUE);
2872 atomic_add_acq_long(&sc->cq_spq_left, 1);
2874 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n",
2875 atomic_load_acq_long(&sc->cq_spq_left));
2878 if ((drv_cmd == ECORE_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
2879 (!!bxe_test_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state))) {
2881 * If Queue update ramrod is completed for last Queue in AFEX VIF set
2882 * flow, then ACK MCP at the end. Mark pending ACK to MCP bit to
2883 * prevent case that both bits are cleared. At the end of load/unload
2884 * driver checks that sp_state is cleared and this order prevents
2887 bxe_set_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, &sc->sp_state);
2889 bxe_clear_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state);
2891 /* schedule the sp task as MCP ack is required */
2892 bxe_schedule_sp_task(sc);
2898 * The current mbuf is part of an aggregation. Move the mbuf into the TPA
2899 * aggregation queue, put an empty mbuf back onto the receive chain, and mark
2900 * the current aggregation queue as in-progress.
2903 bxe_tpa_start(struct bxe_softc *sc,
2904 struct bxe_fastpath *fp,
2908 struct eth_fast_path_rx_cqe *cqe)
2910 struct bxe_sw_rx_bd tmp_bd;
2911 struct bxe_sw_rx_bd *rx_buf;
2912 struct eth_rx_bd *rx_bd;
2914 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
2917 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START "
2918 "cons=%d prod=%d\n",
2919 fp->index, queue, cons, prod);
2921 max_agg_queues = MAX_AGG_QS(sc);
2923 KASSERT((queue < max_agg_queues),
2924 ("fp[%02d] invalid aggr queue (%d >= %d)!",
2925 fp->index, queue, max_agg_queues));
2927 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP),
2928 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!",
2931 /* copy the existing mbuf and mapping from the TPA pool */
2932 tmp_bd = tpa_info->bd;
2934 if (tmp_bd.m == NULL) {
2935 BLOGE(sc, "fp[%02d].tpa[%02d] mbuf not allocated!\n",
2937 /* XXX Error handling? */
2941 /* change the TPA queue to the start state */
2942 tpa_info->state = BXE_TPA_STATE_START;
2943 tpa_info->placement_offset = cqe->placement_offset;
2944 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags);
2945 tpa_info->vlan_tag = le16toh(cqe->vlan_tag);
2946 tpa_info->len_on_bd = le16toh(cqe->len_on_bd);
2948 fp->rx_tpa_queue_used |= (1 << queue);
2951 * If all the buffer descriptors are filled with mbufs then fill in
2952 * the current consumer index with a new BD. Else if a maximum Rx
2953 * buffer limit is imposed then fill in the next producer index.
2955 index = (sc->max_rx_bufs != RX_BD_USABLE) ?
2958 /* move the received mbuf and mapping to TPA pool */
2959 tpa_info->bd = fp->rx_mbuf_chain[cons];
2961 /* release any existing RX BD mbuf mappings */
2962 if (cons != index) {
2963 rx_buf = &fp->rx_mbuf_chain[cons];
2965 if (rx_buf->m_map != NULL) {
2966 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
2967 BUS_DMASYNC_POSTREAD);
2968 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
2972 * We get here when the maximum number of rx buffers is less than
2973 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL
2974 * it out here without concern of a memory leak.
2976 fp->rx_mbuf_chain[cons].m = NULL;
2979 /* update the Rx SW BD with the mbuf info from the TPA pool */
2980 fp->rx_mbuf_chain[index] = tmp_bd;
2982 /* update the Rx BD with the empty mbuf phys address from the TPA pool */
2983 rx_bd = &fp->rx_chain[index];
2984 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr));
2985 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr));
2989 * When a TPA aggregation is completed, loop through the individual mbufs
2990 * of the aggregation, combining them into a single mbuf which will be sent
2991 * up the stack. Refill all freed SGEs with mbufs as we go along.
2994 bxe_fill_frag_mbuf(struct bxe_softc *sc,
2995 struct bxe_fastpath *fp,
2996 struct bxe_sw_tpa_info *tpa_info,
3000 struct eth_end_agg_rx_cqe *cqe,
3003 struct mbuf *m_frag;
3004 uint32_t frag_len, frag_size, i;
3009 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd;
3012 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n",
3013 fp->index, queue, tpa_info->len_on_bd, frag_size, pages);
3015 /* make sure the aggregated frame is not too big to handle */
3016 if (pages > 8 * PAGES_PER_SGE) {
3017 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! "
3018 "pkt_len=%d len_on_bd=%d frag_size=%d\n",
3019 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len),
3020 tpa_info->len_on_bd, frag_size);
3021 bxe_panic(sc, ("sge page count error\n"));
3026 * Scan through the scatter gather list pulling individual mbufs into a
3027 * single mbuf for the host stack.
3029 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
3030 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j]));
3033 * Firmware gives the indices of the SGE as if the ring is an array
3034 * (meaning that the "next" element will consume 2 indices).
3036 frag_len = min(frag_size, (uint32_t)(SGE_PAGES));
3038 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d "
3039 "sge_idx=%d frag_size=%d frag_len=%d\n",
3040 fp->index, queue, i, j, sge_idx, frag_size, frag_len);
3042 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m;
3044 /* allocate a new mbuf for the SGE */
3045 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
3047 /* Leave all remaining SGEs in the ring! */
3051 /* update the fragment length */
3052 m_frag->m_len = frag_len;
3054 /* concatenate the fragment to the head mbuf */
3056 fp->eth_q_stats.mbuf_alloc_sge--;
3058 /* update the TPA mbuf size and remaining fragment size */
3059 m->m_pkthdr.len += frag_len;
3060 frag_size -= frag_len;
3064 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n",
3065 fp->index, queue, frag_size);
3071 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
3075 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) {
3076 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1;
3078 for (j = 0; j < 2; j++) {
3079 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
3086 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
3088 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */
3089 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
3092 * Clear the two last indices in the page to 1. These are the indices that
3093 * correspond to the "next" element, hence will never be indicated and
3094 * should be removed from the calculations.
3096 bxe_clear_sge_mask_next_elems(fp);
3100 bxe_update_last_max_sge(struct bxe_fastpath *fp,
3103 uint16_t last_max = fp->last_max_sge;
3105 if (SUB_S16(idx, last_max) > 0) {
3106 fp->last_max_sge = idx;
3111 bxe_update_sge_prod(struct bxe_softc *sc,
3112 struct bxe_fastpath *fp,
3114 struct eth_end_agg_rx_cqe *cqe)
3116 uint16_t last_max, last_elem, first_elem;
3124 /* first mark all used pages */
3125 for (i = 0; i < sge_len; i++) {
3126 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
3127 RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[i])));
3131 "fp[%02d] fp_cqe->sgl[%d] = %d\n",
3132 fp->index, sge_len - 1,
3133 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
3135 /* assume that the last SGE index is the biggest */
3136 bxe_update_last_max_sge(fp,
3137 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
3139 last_max = RX_SGE(fp->last_max_sge);
3140 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
3141 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
3143 /* if ring is not full */
3144 if (last_elem + 1 != first_elem) {
3148 /* now update the prod */
3149 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) {
3150 if (__predict_true(fp->sge_mask[i])) {
3154 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
3155 delta += BIT_VEC64_ELEM_SZ;
3159 fp->rx_sge_prod += delta;
3160 /* clear page-end entries */
3161 bxe_clear_sge_mask_next_elems(fp);
3165 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n",
3166 fp->index, fp->last_max_sge, fp->rx_sge_prod);
3170 * The aggregation on the current TPA queue has completed. Pull the individual
3171 * mbuf fragments together into a single mbuf, perform all necessary checksum
3172 * calculations, and send the resuting mbuf to the stack.
3175 bxe_tpa_stop(struct bxe_softc *sc,
3176 struct bxe_fastpath *fp,
3177 struct bxe_sw_tpa_info *tpa_info,
3180 struct eth_end_agg_rx_cqe *cqe,
3183 struct ifnet *ifp = sc->ifnet;
3188 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n",
3189 fp->index, queue, tpa_info->placement_offset,
3190 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag);
3194 /* allocate a replacement before modifying existing mbuf */
3195 rc = bxe_alloc_rx_tpa_mbuf(fp, queue);
3197 /* drop the frame and log an error */
3198 fp->eth_q_stats.rx_soft_errors++;
3199 goto bxe_tpa_stop_exit;
3202 /* we have a replacement, fixup the current mbuf */
3203 m_adj(m, tpa_info->placement_offset);
3204 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd;
3206 /* mark the checksums valid (taken care of by the firmware) */
3207 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3208 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3209 m->m_pkthdr.csum_data = 0xffff;
3210 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED |
3215 /* aggregate all of the SGEs into a single mbuf */
3216 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx);
3218 /* drop the packet and log an error */
3219 fp->eth_q_stats.rx_soft_errors++;
3222 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) {
3223 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag;
3224 m->m_flags |= M_VLANTAG;
3227 /* assign packet to this interface interface */
3228 m->m_pkthdr.rcvif = ifp;
3230 #if __FreeBSD_version >= 800000
3231 /* specify what RSS queue was used for this flow */
3232 m->m_pkthdr.flowid = fp->index;
3233 m->m_flags |= M_FLOWID;
3237 fp->eth_q_stats.rx_tpa_pkts++;
3239 /* pass the frame to the stack */
3240 (*ifp->if_input)(ifp, m);
3243 /* we passed an mbuf up the stack or dropped the frame */
3244 fp->eth_q_stats.mbuf_alloc_tpa--;
3248 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP;
3249 fp->rx_tpa_queue_used &= ~(1 << queue);
3253 bxe_rxeof(struct bxe_softc *sc,
3254 struct bxe_fastpath *fp)
3256 struct ifnet *ifp = sc->ifnet;
3257 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
3258 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod;
3264 /* CQ "next element" is of the size of the regular element */
3265 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb);
3266 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) {
3270 bd_cons = fp->rx_bd_cons;
3271 bd_prod = fp->rx_bd_prod;
3272 bd_prod_fw = bd_prod;
3273 sw_cq_cons = fp->rx_cq_cons;
3274 sw_cq_prod = fp->rx_cq_prod;
3277 * Memory barrier necessary as speculative reads of the rx
3278 * buffer can be ahead of the index in the status block
3283 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n",
3284 fp->index, hw_cq_cons, sw_cq_cons);
3286 while (sw_cq_cons != hw_cq_cons) {
3287 struct bxe_sw_rx_bd *rx_buf = NULL;
3288 union eth_rx_cqe *cqe;
3289 struct eth_fast_path_rx_cqe *cqe_fp;
3290 uint8_t cqe_fp_flags;
3291 enum eth_rx_cqe_type cqe_fp_type;
3293 struct mbuf *m = NULL;
3295 comp_ring_cons = RCQ(sw_cq_cons);
3296 bd_prod = RX_BD(bd_prod);
3297 bd_cons = RX_BD(bd_cons);
3299 cqe = &fp->rcq_chain[comp_ring_cons];
3300 cqe_fp = &cqe->fast_path_cqe;
3301 cqe_fp_flags = cqe_fp->type_error_flags;
3302 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
3305 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d "
3306 "BD prod=%d cons=%d CQE type=0x%x err=0x%x "
3307 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u\n",
3313 CQE_TYPE(cqe_fp_flags),
3315 cqe_fp->status_flags,
3316 le32toh(cqe_fp->rss_hash_result),
3317 le16toh(cqe_fp->vlan_tag),
3318 le16toh(cqe_fp->pkt_len_or_gro_seg_len));
3320 /* is this a slowpath msg? */
3321 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) {
3322 bxe_sp_event(sc, fp, cqe);
3326 rx_buf = &fp->rx_mbuf_chain[bd_cons];
3328 if (!CQE_TYPE_FAST(cqe_fp_type)) {
3329 struct bxe_sw_tpa_info *tpa_info;
3330 uint16_t frag_size, pages;
3335 if (!fp->tpa_enable &&
3336 (CQE_TYPE_START(cqe_fp_type) || CQE_TYPE_STOP(cqe_fp_type))) {
3337 BLOGE(sc, "START/STOP packet while !tpa_enable type (0x%x)\n",
3338 CQE_TYPE(cqe_fp_type));
3342 if (CQE_TYPE_START(cqe_fp_type)) {
3343 bxe_tpa_start(sc, fp, cqe_fp->queue_index,
3344 bd_cons, bd_prod, cqe_fp);
3345 m = NULL; /* packet not ready yet */
3349 KASSERT(CQE_TYPE_STOP(cqe_fp_type),
3350 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type));
3352 queue = cqe->end_agg_cqe.queue_index;
3353 tpa_info = &fp->rx_tpa_info[queue];
3355 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n",
3358 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) -
3359 tpa_info->len_on_bd);
3360 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
3362 bxe_tpa_stop(sc, fp, tpa_info, queue, pages,
3363 &cqe->end_agg_cqe, comp_ring_cons);
3365 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe);
3372 /* is this an error packet? */
3373 if (__predict_false(cqe_fp_flags &
3374 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) {
3375 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons);
3376 fp->eth_q_stats.rx_soft_errors++;
3380 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len);
3381 pad = cqe_fp->placement_offset;
3385 if (__predict_false(m == NULL)) {
3386 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n",
3387 bd_cons, fp->index);
3391 /* XXX double copy if packet length under a threshold */
3394 * If all the buffer descriptors are filled with mbufs then fill in
3395 * the current consumer index with a new BD. Else if a maximum Rx
3396 * buffer limit is imposed then fill in the next producer index.
3398 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons,
3399 (sc->max_rx_bufs != RX_BD_USABLE) ?
3402 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
3404 fp->eth_q_stats.rx_soft_errors++;
3406 if (sc->max_rx_bufs != RX_BD_USABLE) {
3407 /* copy this consumer index to the producer index */
3408 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf,
3409 sizeof(struct bxe_sw_rx_bd));
3410 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd));
3416 /* current mbuf was detached from the bd */
3417 fp->eth_q_stats.mbuf_alloc_rx--;
3419 /* we allocated a replacement mbuf, fixup the current one */
3421 m->m_pkthdr.len = m->m_len = len;
3423 /* assign packet to this interface interface */
3424 m->m_pkthdr.rcvif = ifp;
3426 /* assume no hardware checksum has complated */
3427 m->m_pkthdr.csum_flags = 0;
3429 /* validate checksum if offload enabled */
3430 if (ifp->if_capenable & IFCAP_RXCSUM) {
3431 /* check for a valid IP frame */
3432 if (!(cqe->fast_path_cqe.status_flags &
3433 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
3434 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3435 if (__predict_false(cqe_fp_flags &
3436 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
3437 fp->eth_q_stats.rx_hw_csum_errors++;
3439 fp->eth_q_stats.rx_ofld_frames_csum_ip++;
3440 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3444 /* check for a valid TCP/UDP frame */
3445 if (!(cqe->fast_path_cqe.status_flags &
3446 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
3447 if (__predict_false(cqe_fp_flags &
3448 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
3449 fp->eth_q_stats.rx_hw_csum_errors++;
3451 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++;
3452 m->m_pkthdr.csum_data = 0xFFFF;
3453 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID |
3459 /* if there is a VLAN tag then flag that info */
3460 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_VLAN) {
3461 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag;
3462 m->m_flags |= M_VLANTAG;
3465 #if __FreeBSD_version >= 800000
3466 /* specify what RSS queue was used for this flow */
3467 m->m_pkthdr.flowid = fp->index;
3468 m->m_flags |= M_FLOWID;
3473 bd_cons = RX_BD_NEXT(bd_cons);
3474 bd_prod = RX_BD_NEXT(bd_prod);
3475 bd_prod_fw = RX_BD_NEXT(bd_prod_fw);
3477 /* pass the frame to the stack */
3478 if (__predict_true(m != NULL)) {
3481 (*ifp->if_input)(ifp, m);
3486 sw_cq_prod = RCQ_NEXT(sw_cq_prod);
3487 sw_cq_cons = RCQ_NEXT(sw_cq_cons);
3489 /* limit spinning on the queue */
3490 if (rx_pkts == sc->rx_budget) {
3491 fp->eth_q_stats.rx_budget_reached++;
3494 } /* while work to do */
3496 fp->rx_bd_cons = bd_cons;
3497 fp->rx_bd_prod = bd_prod_fw;
3498 fp->rx_cq_cons = sw_cq_cons;
3499 fp->rx_cq_prod = sw_cq_prod;
3501 /* Update producers */
3502 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod);
3504 fp->eth_q_stats.rx_pkts += rx_pkts;
3505 fp->eth_q_stats.rx_calls++;
3507 BXE_FP_RX_UNLOCK(fp);
3509 return (sw_cq_cons != hw_cq_cons);
3513 bxe_free_tx_pkt(struct bxe_softc *sc,
3514 struct bxe_fastpath *fp,
3517 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx];
3518 struct eth_tx_start_bd *tx_start_bd;
3519 uint16_t bd_idx = TX_BD(tx_buf->first_bd);
3523 /* unmap the mbuf from non-paged memory */
3524 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
3526 tx_start_bd = &fp->tx_chain[bd_idx].start_bd;
3527 nbd = le16toh(tx_start_bd->nbd) - 1;
3530 if ((nbd - 1) > (MAX_MBUF_FRAGS + 2)) {
3531 bxe_panic(sc, ("BAD nbd!\n"));
3535 new_cons = (tx_buf->first_bd + nbd);
3538 struct eth_tx_bd *tx_data_bd;
3541 * The following code doesn't do anything but is left here
3542 * for clarity on what the new value of new_cons skipped.
3545 /* get the next bd */
3546 bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3548 /* skip the parse bd */
3550 bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3552 /* skip the TSO split header bd since they have no mapping */
3553 if (tx_buf->flags & BXE_TSO_SPLIT_BD) {
3555 bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3558 /* now free frags */
3560 tx_data_bd = &fp->tx_chain[bd_idx].reg_bd;
3562 bd_idx = TX_BD(TX_BD_NEXT(bd_idx));
3568 if (__predict_true(tx_buf->m != NULL)) {
3570 fp->eth_q_stats.mbuf_alloc_tx--;
3572 fp->eth_q_stats.tx_chain_lost_mbuf++;
3576 tx_buf->first_bd = 0;
3581 /* transmit timeout watchdog */
3583 bxe_watchdog(struct bxe_softc *sc,
3584 struct bxe_fastpath *fp)
3588 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) {
3589 BXE_FP_TX_UNLOCK(fp);
3593 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index);
3595 BXE_FP_TX_UNLOCK(fp);
3597 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
3598 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
3603 /* processes transmit completions */
3605 bxe_txeof(struct bxe_softc *sc,
3606 struct bxe_fastpath *fp)
3608 struct ifnet *ifp = sc->ifnet;
3609 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons;
3610 uint16_t tx_bd_avail;
3612 BXE_FP_TX_LOCK_ASSERT(fp);
3614 bd_cons = fp->tx_bd_cons;
3615 hw_cons = le16toh(*fp->tx_cons_sb);
3616 sw_cons = fp->tx_pkt_cons;
3618 while (sw_cons != hw_cons) {
3619 pkt_cons = TX_BD(sw_cons);
3622 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n",
3623 fp->index, hw_cons, sw_cons, pkt_cons);
3625 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons);
3630 fp->tx_pkt_cons = sw_cons;
3631 fp->tx_bd_cons = bd_cons;
3634 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n",
3635 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod);
3639 tx_bd_avail = bxe_tx_avail(sc, fp);
3641 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
3642 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3644 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3647 if (fp->tx_pkt_prod != fp->tx_pkt_cons) {
3648 /* reset the watchdog timer if there are pending transmits */
3649 fp->watchdog_timer = BXE_TX_TIMEOUT;
3652 /* clear watchdog when there are no pending transmits */
3653 fp->watchdog_timer = 0;
3659 bxe_drain_tx_queues(struct bxe_softc *sc)
3661 struct bxe_fastpath *fp;
3664 /* wait until all TX fastpath tasks have completed */
3665 for (i = 0; i < sc->num_queues; i++) {
3670 while (bxe_has_tx_work(fp)) {
3674 BXE_FP_TX_UNLOCK(fp);
3677 BLOGE(sc, "Timeout waiting for fp[%d] "
3678 "transmits to complete!\n", i);
3679 bxe_panic(sc, ("tx drain failure\n"));
3693 bxe_del_all_macs(struct bxe_softc *sc,
3694 struct ecore_vlan_mac_obj *mac_obj,
3696 uint8_t wait_for_comp)
3698 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
3701 /* wait for completion of requested */
3702 if (wait_for_comp) {
3703 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
3706 /* Set the mac type of addresses we want to clear */
3707 bxe_set_bit(mac_type, &vlan_mac_flags);
3709 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);
3711 BLOGE(sc, "Failed to delete MACs (%d)\n", rc);
3718 bxe_fill_accept_flags(struct bxe_softc *sc,
3720 unsigned long *rx_accept_flags,
3721 unsigned long *tx_accept_flags)
3723 /* Clear the flags first */
3724 *rx_accept_flags = 0;
3725 *tx_accept_flags = 0;
3728 case BXE_RX_MODE_NONE:
3730 * 'drop all' supersedes any accept flags that may have been
3731 * passed to the function.
3735 case BXE_RX_MODE_NORMAL:
3736 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3737 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);
3738 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3740 /* internal switching mode */
3741 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3742 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);
3743 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3747 case BXE_RX_MODE_ALLMULTI:
3748 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3749 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3750 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3752 /* internal switching mode */
3753 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3754 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3755 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3759 case BXE_RX_MODE_PROMISC:
3761 * According to deffinition of SI mode, iface in promisc mode
3762 * should receive matched and unmatched (in resolution of port)
3765 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);
3766 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);
3767 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);
3768 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);
3770 /* internal switching mode */
3771 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);
3772 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);
3775 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);
3777 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);
3783 BLOGE(sc, "Unknown rx_mode (%d)\n", rx_mode);
3787 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
3788 if (rx_mode != BXE_RX_MODE_NONE) {
3789 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);
3790 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);
3797 bxe_set_q_rx_mode(struct bxe_softc *sc,
3799 unsigned long rx_mode_flags,
3800 unsigned long rx_accept_flags,
3801 unsigned long tx_accept_flags,
3802 unsigned long ramrod_flags)
3804 struct ecore_rx_mode_ramrod_params ramrod_param;
3807 memset(&ramrod_param, 0, sizeof(ramrod_param));
3809 /* Prepare ramrod parameters */
3810 ramrod_param.cid = 0;
3811 ramrod_param.cl_id = cl_id;
3812 ramrod_param.rx_mode_obj = &sc->rx_mode_obj;
3813 ramrod_param.func_id = SC_FUNC(sc);
3815 ramrod_param.pstate = &sc->sp_state;
3816 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING;
3818 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata);
3819 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata);
3821 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
3823 ramrod_param.ramrod_flags = ramrod_flags;
3824 ramrod_param.rx_mode_flags = rx_mode_flags;
3826 ramrod_param.rx_accept_flags = rx_accept_flags;
3827 ramrod_param.tx_accept_flags = tx_accept_flags;
3829 rc = ecore_config_rx_mode(sc, &ramrod_param);
3831 BLOGE(sc, "Set rx_mode %d failed\n", sc->rx_mode);
3839 bxe_set_storm_rx_mode(struct bxe_softc *sc)
3841 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
3842 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
3845 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,
3851 bxe_set_bit(RAMROD_RX, &ramrod_flags);
3852 bxe_set_bit(RAMROD_TX, &ramrod_flags);
3854 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */
3855 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,
3856 rx_accept_flags, tx_accept_flags,
3860 /* returns the "mcp load_code" according to global load_count array */
3862 bxe_nic_load_no_mcp(struct bxe_softc *sc)
3864 int path = SC_PATH(sc);
3865 int port = SC_PORT(sc);
3867 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3868 path, load_count[path][0], load_count[path][1],
3869 load_count[path][2]);
3870 load_count[path][0]++;
3871 load_count[path][1 + port]++;
3872 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3873 path, load_count[path][0], load_count[path][1],
3874 load_count[path][2]);
3875 if (load_count[path][0] == 1) {
3876 return (FW_MSG_CODE_DRV_LOAD_COMMON);
3877 } else if (load_count[path][1 + port] == 1) {
3878 return (FW_MSG_CODE_DRV_LOAD_PORT);
3880 return (FW_MSG_CODE_DRV_LOAD_FUNCTION);
3884 /* returns the "mcp load_code" according to global load_count array */
3886 bxe_nic_unload_no_mcp(struct bxe_softc *sc)
3888 int port = SC_PORT(sc);
3889 int path = SC_PATH(sc);
3891 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n",
3892 path, load_count[path][0], load_count[path][1],
3893 load_count[path][2]);
3894 load_count[path][0]--;
3895 load_count[path][1 + port]--;
3896 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n",
3897 path, load_count[path][0], load_count[path][1],
3898 load_count[path][2]);
3899 if (load_count[path][0] == 0) {
3900 return (FW_MSG_CODE_DRV_UNLOAD_COMMON);
3901 } else if (load_count[path][1 + port] == 0) {
3902 return (FW_MSG_CODE_DRV_UNLOAD_PORT);
3904 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
3908 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */
3910 bxe_send_unload_req(struct bxe_softc *sc,
3913 uint32_t reset_code = 0;
3915 int port = SC_PORT(sc);
3916 int path = SC_PATH(sc);
3919 /* Select the UNLOAD request mode */
3920 if (unload_mode == UNLOAD_NORMAL) {
3921 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3924 else if (sc->flags & BXE_NO_WOL_FLAG) {
3925 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
3926 } else if (sc->wol) {
3927 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3928 uint8_t *mac_addr = sc->dev->dev_addr;
3933 * The mac address is written to entries 1-4 to
3934 * preserve entry 0 which is used by the PMF
3936 uint8_t entry = (SC_VN(sc) + 1)*8;
3938 val = (mac_addr[0] << 8) | mac_addr[1];
3939 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val);
3941 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
3942 (mac_addr[4] << 8) | mac_addr[5];
3943 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
3945 /* Enable the PME and clear the status */
3946 pmc = pci_read_config(sc->dev,
3947 (sc->devinfo.pcie_pm_cap_reg +
3950 pmc |= PCIM_PSTAT_PMEENABLE | PCIM_PSTAT_PME;
3951 pci_write_config(sc->dev,
3952 (sc->devinfo.pcie_pm_cap_reg +
3956 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
3960 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3963 /* Send the request to the MCP */
3964 if (!BXE_NOMCP(sc)) {
3965 reset_code = bxe_fw_command(sc, reset_code, 0);
3967 reset_code = bxe_nic_unload_no_mcp(sc);
3970 return (reset_code);
3973 /* send UNLOAD_DONE command to the MCP */
3975 bxe_send_unload_done(struct bxe_softc *sc,
3978 uint32_t reset_param =
3979 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
3981 /* Report UNLOAD_DONE to MCP */
3982 if (!BXE_NOMCP(sc)) {
3983 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
3988 bxe_func_wait_started(struct bxe_softc *sc)
3992 if (!sc->port.pmf) {
3997 * (assumption: No Attention from MCP at this stage)
3998 * PMF probably in the middle of TX disable/enable transaction
3999 * 1. Sync IRS for default SB
4000 * 2. Sync SP queue - this guarantees us that attention handling started
4001 * 3. Wait, that TX disable/enable transaction completes
4003 * 1+2 guarantee that if DCBX attention was scheduled it already changed
4004 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
4005 * received completion for the transaction the state is TX_STOPPED.
4006 * State will return to STARTED after completion of TX_STOPPED-->STARTED
4010 /* XXX make sure default SB ISR is done */
4011 /* need a way to synchronize an irq (intr_mtx?) */
4013 /* XXX flush any work queues */
4015 while (ecore_func_get_state(sc, &sc->func_obj) !=
4016 ECORE_F_STATE_STARTED && tout--) {
4020 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) {
4022 * Failed to complete the transaction in a "good way"
4023 * Force both transactions with CLR bit.
4025 struct ecore_func_state_params func_params = { NULL };
4027 BLOGE(sc, "Unexpected function state! "
4028 "Forcing STARTED-->TX_STOPPED-->STARTED\n");
4030 func_params.f_obj = &sc->func_obj;
4031 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4033 /* STARTED-->TX_STOPPED */
4034 func_params.cmd = ECORE_F_CMD_TX_STOP;
4035 ecore_func_state_change(sc, &func_params);
4037 /* TX_STOPPED-->STARTED */
4038 func_params.cmd = ECORE_F_CMD_TX_START;
4039 return (ecore_func_state_change(sc, &func_params));
4046 bxe_stop_queue(struct bxe_softc *sc,
4049 struct bxe_fastpath *fp = &sc->fp[index];
4050 struct ecore_queue_state_params q_params = { NULL };
4053 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index);
4055 q_params.q_obj = &sc->sp_objs[fp->index].q_obj;
4056 /* We want to wait for completion in this context */
4057 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
4059 /* Stop the primary connection: */
4061 /* ...halt the connection */
4062 q_params.cmd = ECORE_Q_CMD_HALT;
4063 rc = ecore_queue_state_change(sc, &q_params);
4068 /* ...terminate the connection */
4069 q_params.cmd = ECORE_Q_CMD_TERMINATE;
4070 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate));
4071 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
4072 rc = ecore_queue_state_change(sc, &q_params);
4077 /* ...delete cfc entry */
4078 q_params.cmd = ECORE_Q_CMD_CFC_DEL;
4079 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del));
4080 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
4081 return (ecore_queue_state_change(sc, &q_params));
4084 /* wait for the outstanding SP commands */
4085 static inline uint8_t
4086 bxe_wait_sp_comp(struct bxe_softc *sc,
4090 int tout = 5000; /* wait for 5 secs tops */
4094 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) {
4103 tmp = atomic_load_acq_long(&sc->sp_state);
4105 BLOGE(sc, "Filtering completion timed out: "
4106 "sp_state 0x%lx, mask 0x%lx\n",
4115 bxe_func_stop(struct bxe_softc *sc)
4117 struct ecore_func_state_params func_params = { NULL };
4120 /* prepare parameters for function state transitions */
4121 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4122 func_params.f_obj = &sc->func_obj;
4123 func_params.cmd = ECORE_F_CMD_STOP;
4126 * Try to stop the function the 'good way'. If it fails (in case
4127 * of a parity error during bxe_chip_cleanup()) and we are
4128 * not in a debug mode, perform a state transaction in order to
4129 * enable further HW_RESET transaction.
4131 rc = ecore_func_state_change(sc, &func_params);
4133 BLOGE(sc, "FUNC_STOP ramrod failed. "
4134 "Running a dry transaction\n");
4135 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
4136 return (ecore_func_state_change(sc, &func_params));
4143 bxe_reset_hw(struct bxe_softc *sc,
4146 struct ecore_func_state_params func_params = { NULL };
4148 /* Prepare parameters for function state transitions */
4149 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
4151 func_params.f_obj = &sc->func_obj;
4152 func_params.cmd = ECORE_F_CMD_HW_RESET;
4154 func_params.params.hw_init.load_phase = load_code;
4156 return (ecore_func_state_change(sc, &func_params));
4160 bxe_int_disable_sync(struct bxe_softc *sc,
4164 /* prevent the HW from sending interrupts */
4165 bxe_int_disable(sc);
4168 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */
4169 /* make sure all ISRs are done */
4171 /* XXX make sure sp_task is not running */
4172 /* cancel and flush work queues */
4176 bxe_chip_cleanup(struct bxe_softc *sc,
4177 uint32_t unload_mode,
4180 int port = SC_PORT(sc);
4181 struct ecore_mcast_ramrod_params rparam = { NULL };
4182 uint32_t reset_code;
4185 bxe_drain_tx_queues(sc);
4187 /* give HW time to discard old tx messages */
4190 /* Clean all ETH MACs */
4191 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE);
4193 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc);
4196 /* Clean up UC list */
4197 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE);
4199 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc);
4203 if (!CHIP_IS_E1(sc)) {
4204 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
4207 /* Set "drop all" to stop Rx */
4210 * We need to take the BXE_MCAST_LOCK() here in order to prevent
4211 * a race between the completion code and this code.
4215 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
4216 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
4218 bxe_set_storm_rx_mode(sc);
4221 /* Clean up multicast configuration */
4222 rparam.mcast_obj = &sc->mcast_obj;
4223 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4225 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4228 BXE_MCAST_UNLOCK(sc);
4230 // XXX bxe_iov_chip_cleanup(sc);
4233 * Send the UNLOAD_REQUEST to the MCP. This will return if
4234 * this function should perform FUNCTION, PORT, or COMMON HW
4237 reset_code = bxe_send_unload_req(sc, unload_mode);
4240 * (assumption: No Attention from MCP at this stage)
4241 * PMF probably in the middle of TX disable/enable transaction
4243 rc = bxe_func_wait_started(sc);
4245 BLOGE(sc, "bxe_func_wait_started failed\n");
4249 * Close multi and leading connections
4250 * Completions for ramrods are collected in a synchronous way
4252 for (i = 0; i < sc->num_queues; i++) {
4253 if (bxe_stop_queue(sc, i)) {
4259 * If SP settings didn't get completed so far - something
4260 * very wrong has happen.
4262 if (!bxe_wait_sp_comp(sc, ~0x0UL)) {
4263 BLOGE(sc, "Common slow path ramrods got stuck!\n");
4268 rc = bxe_func_stop(sc);
4270 BLOGE(sc, "Function stop failed!\n");
4273 /* disable HW interrupts */
4274 bxe_int_disable_sync(sc, TRUE);
4276 /* detach interrupts */
4277 bxe_interrupt_detach(sc);
4279 /* Reset the chip */
4280 rc = bxe_reset_hw(sc, reset_code);
4282 BLOGE(sc, "Hardware reset failed\n");
4285 /* Report UNLOAD_DONE to MCP */
4286 bxe_send_unload_done(sc, keep_link);
4290 bxe_disable_close_the_gate(struct bxe_softc *sc)
4293 int port = SC_PORT(sc);
4296 "Disabling 'close the gates'\n");
4298 if (CHIP_IS_E1(sc)) {
4299 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4300 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4301 val = REG_RD(sc, addr);
4303 REG_WR(sc, addr, val);
4305 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);
4306 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
4307 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
4308 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val);
4313 * Cleans the object that have internal lists without sending
4314 * ramrods. Should be run when interrutps are disabled.
4317 bxe_squeeze_objects(struct bxe_softc *sc)
4319 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
4320 struct ecore_mcast_ramrod_params rparam = { NULL };
4321 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
4324 /* Cleanup MACs' object first... */
4326 /* Wait for completion of requested */
4327 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
4328 /* Perform a dry cleanup */
4329 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
4331 /* Clean ETH primary MAC */
4332 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);
4333 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,
4336 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc);
4339 /* Cleanup UC list */
4341 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);
4342 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags,
4345 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc);
4348 /* Now clean mcast object... */
4350 rparam.mcast_obj = &sc->mcast_obj;
4351 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
4353 /* Add a DEL command... */
4354 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
4356 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc);
4359 /* now wait until all pending commands are cleared */
4361 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4364 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc);
4368 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
4372 /* stop the controller */
4373 static __noinline int
4374 bxe_nic_unload(struct bxe_softc *sc,
4375 uint32_t unload_mode,
4378 uint8_t global = FALSE;
4381 BXE_CORE_LOCK_ASSERT(sc);
4383 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n");
4385 /* mark driver as unloaded in shmem2 */
4386 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
4387 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
4388 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
4389 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
4392 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE &&
4393 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) {
4395 * We can get here if the driver has been unloaded
4396 * during parity error recovery and is either waiting for a
4397 * leader to complete or for other functions to unload and
4398 * then ifconfig down has been issued. In this case we want to
4399 * unload and let other functions to complete a recovery
4402 sc->recovery_state = BXE_RECOVERY_DONE;
4404 bxe_release_leader_lock(sc);
4407 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n");
4408 BLOGE(sc, "Can't unload in closed or error state\n");
4413 * Nothing to do during unload if previous bxe_nic_load()
4414 * did not completed succesfully - all resourses are released.
4416 if ((sc->state == BXE_STATE_CLOSED) ||
4417 (sc->state == BXE_STATE_ERROR)) {
4421 sc->state = BXE_STATE_CLOSING_WAITING_HALT;
4427 sc->rx_mode = BXE_RX_MODE_NONE;
4428 /* XXX set rx mode ??? */
4431 /* set ALWAYS_ALIVE bit in shmem */
4432 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
4436 bxe_stats_handle(sc, STATS_EVENT_STOP);
4437 bxe_save_statistics(sc);
4440 /* wait till consumers catch up with producers in all queues */
4441 bxe_drain_tx_queues(sc);
4443 /* if VF indicate to PF this function is going down (PF will delete sp
4444 * elements and clear initializations
4447 ; /* bxe_vfpf_close_vf(sc); */
4448 } else if (unload_mode != UNLOAD_RECOVERY) {
4449 /* if this is a normal/close unload need to clean up chip */
4450 bxe_chip_cleanup(sc, unload_mode, keep_link);
4452 /* Send the UNLOAD_REQUEST to the MCP */
4453 bxe_send_unload_req(sc, unload_mode);
4456 * Prevent transactions to host from the functions on the
4457 * engine that doesn't reset global blocks in case of global
4458 * attention once gloabl blocks are reset and gates are opened
4459 * (the engine which leader will perform the recovery
4462 if (!CHIP_IS_E1x(sc)) {
4466 /* disable HW interrupts */
4467 bxe_int_disable_sync(sc, TRUE);
4469 /* detach interrupts */
4470 bxe_interrupt_detach(sc);
4472 /* Report UNLOAD_DONE to MCP */
4473 bxe_send_unload_done(sc, FALSE);
4477 * At this stage no more interrupts will arrive so we may safely clean
4478 * the queue'able objects here in case they failed to get cleaned so far.
4481 bxe_squeeze_objects(sc);
4484 /* There should be no more pending SP commands at this stage */
4489 bxe_free_fp_buffers(sc);
4495 bxe_free_fw_stats_mem(sc);
4497 sc->state = BXE_STATE_CLOSED;
4500 * Check if there are pending parity attentions. If there are - set
4501 * RECOVERY_IN_PROGRESS.
4503 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) {
4504 bxe_set_reset_in_progress(sc);
4506 /* Set RESET_IS_GLOBAL if needed */
4508 bxe_set_reset_global(sc);
4513 * The last driver must disable a "close the gate" if there is no
4514 * parity attention or "process kill" pending.
4516 if (IS_PF(sc) && !bxe_clear_pf_load(sc) &&
4517 bxe_reset_is_done(sc, SC_PATH(sc))) {
4518 bxe_disable_close_the_gate(sc);
4521 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n");
4527 * Called by the OS to set various media options (i.e. link, speed, etc.) when
4528 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...".
4531 bxe_ifmedia_update(struct ifnet *ifp)
4533 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc;
4534 struct ifmedia *ifm;
4538 /* We only support Ethernet media type. */
4539 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
4543 switch (IFM_SUBTYPE(ifm->ifm_media)) {
4549 case IFM_10G_TWINAX:
4551 /* We don't support changing the media type. */
4552 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n",
4553 IFM_SUBTYPE(ifm->ifm_media));
4561 * Called by the OS to get the current media status (i.e. link, speed, etc.).
4564 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
4566 struct bxe_softc *sc = ifp->if_softc;
4568 /* Report link down if the driver isn't running. */
4569 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
4570 ifmr->ifm_active |= IFM_NONE;
4574 /* Setup the default interface info. */
4575 ifmr->ifm_status = IFM_AVALID;
4576 ifmr->ifm_active = IFM_ETHER;
4578 if (sc->link_vars.link_up) {
4579 ifmr->ifm_status |= IFM_ACTIVE;
4581 ifmr->ifm_active |= IFM_NONE;
4585 ifmr->ifm_active |= sc->media;
4587 if (sc->link_vars.duplex == DUPLEX_FULL) {
4588 ifmr->ifm_active |= IFM_FDX;
4590 ifmr->ifm_active |= IFM_HDX;
4595 bxe_ioctl_nvram(struct bxe_softc *sc,
4599 struct bxe_nvram_data nvdata_base;
4600 struct bxe_nvram_data *nvdata;
4604 copyin(ifr->ifr_data, &nvdata_base, sizeof(nvdata_base));
4606 len = (sizeof(struct bxe_nvram_data) +
4610 if (len > sizeof(struct bxe_nvram_data)) {
4611 if ((nvdata = (struct bxe_nvram_data *)
4612 malloc(len, M_DEVBUF,
4613 (M_NOWAIT | M_ZERO))) == NULL) {
4614 BLOGE(sc, "BXE_IOC_RD_NVRAM malloc failed\n");
4617 memcpy(nvdata, &nvdata_base, sizeof(struct bxe_nvram_data));
4619 nvdata = &nvdata_base;
4622 if (priv_op == BXE_IOC_RD_NVRAM) {
4623 BLOGD(sc, DBG_IOCTL, "IOC_RD_NVRAM 0x%x %d\n",
4624 nvdata->offset, nvdata->len);
4625 error = bxe_nvram_read(sc,
4627 (uint8_t *)nvdata->value,
4629 copyout(nvdata, ifr->ifr_data, len);
4630 } else { /* BXE_IOC_WR_NVRAM */
4631 BLOGD(sc, DBG_IOCTL, "IOC_WR_NVRAM 0x%x %d\n",
4632 nvdata->offset, nvdata->len);
4633 copyin(ifr->ifr_data, nvdata, len);
4634 error = bxe_nvram_write(sc,
4636 (uint8_t *)nvdata->value,
4640 if (len > sizeof(struct bxe_nvram_data)) {
4641 free(nvdata, M_DEVBUF);
4648 bxe_ioctl_stats_show(struct bxe_softc *sc,
4652 const size_t str_size = (BXE_NUM_ETH_STATS * STAT_NAME_LEN);
4653 const size_t stats_size = (BXE_NUM_ETH_STATS * sizeof(uint64_t));
4660 case BXE_IOC_STATS_SHOW_NUM:
4661 memset(ifr->ifr_data, 0, sizeof(union bxe_stats_show_data));
4662 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.num =
4664 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.len =
4668 case BXE_IOC_STATS_SHOW_STR:
4669 memset(ifr->ifr_data, 0, str_size);
4670 p_tmp = ifr->ifr_data;
4671 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4672 strcpy(p_tmp, bxe_eth_stats_arr[i].string);
4673 p_tmp += STAT_NAME_LEN;
4677 case BXE_IOC_STATS_SHOW_CNT:
4678 memset(ifr->ifr_data, 0, stats_size);
4679 p_tmp = ifr->ifr_data;
4680 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
4681 offset = ((uint32_t *)&sc->eth_stats +
4682 bxe_eth_stats_arr[i].offset);
4683 switch (bxe_eth_stats_arr[i].size) {
4685 *((uint64_t *)p_tmp) = (uint64_t)*offset;
4688 *((uint64_t *)p_tmp) = HILO_U64(*offset, *(offset + 1));
4691 *((uint64_t *)p_tmp) = 0;
4693 p_tmp += sizeof(uint64_t);
4703 bxe_handle_chip_tq(void *context,
4706 struct bxe_softc *sc = (struct bxe_softc *)context;
4707 long work = atomic_load_acq_long(&sc->chip_tq_flags);
4712 if ((sc->ifnet->if_flags & IFF_UP) &&
4713 !(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4714 /* start the interface */
4715 BLOGD(sc, DBG_LOAD, "Starting the interface...\n");
4717 bxe_init_locked(sc);
4718 BXE_CORE_UNLOCK(sc);
4723 if (!(sc->ifnet->if_flags & IFF_UP) &&
4724 (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4725 /* bring down the interface */
4726 BLOGD(sc, DBG_LOAD, "Stopping the interface...\n");
4727 bxe_periodic_stop(sc);
4729 bxe_stop_locked(sc);
4730 BXE_CORE_UNLOCK(sc);
4734 case CHIP_TQ_REINIT:
4735 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
4736 /* restart the interface */
4737 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n");
4738 bxe_periodic_stop(sc);
4740 bxe_stop_locked(sc);
4741 bxe_init_locked(sc);
4742 BXE_CORE_UNLOCK(sc);
4752 * Handles any IOCTL calls from the operating system.
4755 * 0 = Success, >0 Failure
4758 bxe_ioctl(struct ifnet *ifp,
4762 struct bxe_softc *sc = ifp->if_softc;
4763 struct ifreq *ifr = (struct ifreq *)data;
4764 struct bxe_nvram_data *nvdata;
4770 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN);
4771 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING);
4776 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n",
4779 if (sc->mtu == ifr->ifr_mtu) {
4780 /* nothing to change */
4784 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) {
4785 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n",
4786 ifr->ifr_mtu, mtu_min, mtu_max);
4791 atomic_store_rel_int((volatile unsigned int *)&sc->mtu,
4792 (unsigned long)ifr->ifr_mtu);
4793 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu,
4794 (unsigned long)ifr->ifr_mtu);
4800 /* toggle the interface state up or down */
4801 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n");
4803 /* check if the interface is up */
4804 if (ifp->if_flags & IFF_UP) {
4805 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4806 /* set the receive mode flags */
4807 bxe_set_rx_mode(sc);
4809 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_START);
4810 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
4813 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4814 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_STOP);
4815 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
4823 /* add/delete multicast addresses */
4824 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n");
4826 /* check if the interface is up */
4827 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
4828 /* set the receive mode flags */
4829 bxe_set_rx_mode(sc);
4835 /* find out which capabilities have changed */
4836 mask = (ifr->ifr_reqcap ^ ifp->if_capenable);
4838 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n",
4841 /* toggle the LRO capabilites enable flag */
4842 if (mask & IFCAP_LRO) {
4843 ifp->if_capenable ^= IFCAP_LRO;
4844 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n",
4845 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF");
4849 /* toggle the TXCSUM checksum capabilites enable flag */
4850 if (mask & IFCAP_TXCSUM) {
4851 ifp->if_capenable ^= IFCAP_TXCSUM;
4852 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n",
4853 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF");
4854 if (ifp->if_capenable & IFCAP_TXCSUM) {
4855 ifp->if_hwassist = (CSUM_IP |
4862 ifp->if_hwassist = 0;
4866 /* toggle the RXCSUM checksum capabilities enable flag */
4867 if (mask & IFCAP_RXCSUM) {
4868 ifp->if_capenable ^= IFCAP_RXCSUM;
4869 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n",
4870 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF");
4871 if (ifp->if_capenable & IFCAP_RXCSUM) {
4872 ifp->if_hwassist = (CSUM_IP |
4879 ifp->if_hwassist = 0;
4883 /* toggle TSO4 capabilities enabled flag */
4884 if (mask & IFCAP_TSO4) {
4885 ifp->if_capenable ^= IFCAP_TSO4;
4886 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n",
4887 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF");
4890 /* toggle TSO6 capabilities enabled flag */
4891 if (mask & IFCAP_TSO6) {
4892 ifp->if_capenable ^= IFCAP_TSO6;
4893 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n",
4894 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF");
4897 /* toggle VLAN_HWTSO capabilities enabled flag */
4898 if (mask & IFCAP_VLAN_HWTSO) {
4899 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
4900 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n",
4901 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF");
4904 /* toggle VLAN_HWCSUM capabilities enabled flag */
4905 if (mask & IFCAP_VLAN_HWCSUM) {
4906 /* XXX investigate this... */
4907 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n");
4911 /* toggle VLAN_MTU capabilities enable flag */
4912 if (mask & IFCAP_VLAN_MTU) {
4913 /* XXX investigate this... */
4914 BLOGE(sc, "Changing VLAN_MTU is not supported!\n");
4918 /* toggle VLAN_HWTAGGING capabilities enabled flag */
4919 if (mask & IFCAP_VLAN_HWTAGGING) {
4920 /* XXX investigate this... */
4921 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n");
4925 /* toggle VLAN_HWFILTER capabilities enabled flag */
4926 if (mask & IFCAP_VLAN_HWFILTER) {
4927 /* XXX investigate this... */
4928 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n");
4940 /* set/get interface media */
4941 BLOGD(sc, DBG_IOCTL,
4942 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n",
4944 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
4947 case SIOCGPRIVATE_0:
4948 copyin(ifr->ifr_data, &priv_op, sizeof(priv_op));
4952 case BXE_IOC_RD_NVRAM:
4953 case BXE_IOC_WR_NVRAM:
4954 nvdata = (struct bxe_nvram_data *)ifr->ifr_data;
4955 BLOGD(sc, DBG_IOCTL,
4956 "Received Private NVRAM ioctl addr=0x%x size=%u\n",
4957 nvdata->offset, nvdata->len);
4958 error = bxe_ioctl_nvram(sc, priv_op, ifr);
4961 case BXE_IOC_STATS_SHOW_NUM:
4962 case BXE_IOC_STATS_SHOW_STR:
4963 case BXE_IOC_STATS_SHOW_CNT:
4964 BLOGD(sc, DBG_IOCTL, "Received Private Stats ioctl (%d)\n",
4966 error = bxe_ioctl_stats_show(sc, priv_op, ifr);
4970 BLOGW(sc, "Received Private Unknown ioctl (%d)\n", priv_op);
4978 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n",
4980 error = ether_ioctl(ifp, command, data);
4984 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
4985 BLOGD(sc, DBG_LOAD | DBG_IOCTL,
4986 "Re-initializing hardware from IOCTL change\n");
4987 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT);
4988 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task);
4994 static __noinline void
4995 bxe_dump_mbuf(struct bxe_softc *sc,
5002 if (!(sc->debug & DBG_MBUF)) {
5007 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n");
5013 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n",
5014 i, m, m->m_len, m->m_flags,
5015 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
5017 if (m->m_flags & M_PKTHDR) {
5019 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n",
5020 i, m->m_pkthdr.len, m->m_flags,
5021 "\20\12M_BCAST\13M_MCAST\14M_FRAG"
5022 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
5023 "\22M_PROMISC\23M_NOFREE",
5024 (int)m->m_pkthdr.csum_flags,
5025 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
5026 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
5027 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
5028 "\14CSUM_PSEUDO_HDR");
5031 if (m->m_flags & M_EXT) {
5032 switch (m->m_ext.ext_type) {
5033 case EXT_CLUSTER: type = "EXT_CLUSTER"; break;
5034 case EXT_SFBUF: type = "EXT_SFBUF"; break;
5035 case EXT_JUMBOP: type = "EXT_JUMBOP"; break;
5036 case EXT_JUMBO9: type = "EXT_JUMBO9"; break;
5037 case EXT_JUMBO16: type = "EXT_JUMBO16"; break;
5038 case EXT_PACKET: type = "EXT_PACKET"; break;
5039 case EXT_MBUF: type = "EXT_MBUF"; break;
5040 case EXT_NET_DRV: type = "EXT_NET_DRV"; break;
5041 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break;
5042 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break;
5043 case EXT_EXTREF: type = "EXT_EXTREF"; break;
5044 default: type = "UNKNOWN"; break;
5048 "%02d: - m_ext: %p ext_size=%d type=%s\n",
5049 i, m->m_ext.ext_buf, m->m_ext.ext_size, type);
5053 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE);
5062 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
5063 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS.
5064 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD
5065 * The headers comes in a seperate bd in FreeBSD so 13-3=10.
5066 * Returns: 0 if OK to send, 1 if packet needs further defragmentation
5069 bxe_chktso_window(struct bxe_softc *sc,
5071 bus_dma_segment_t *segs,
5074 uint32_t num_wnds, wnd_size, wnd_sum;
5075 int32_t frag_idx, wnd_idx;
5076 unsigned short lso_mss;
5082 num_wnds = nsegs - wnd_size;
5083 lso_mss = htole16(m->m_pkthdr.tso_segsz);
5086 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the
5087 * first window sum of data while skipping the first assuming it is the
5088 * header in FreeBSD.
5090 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) {
5091 wnd_sum += htole16(segs[frag_idx].ds_len);
5094 /* check the first 10 bd window size */
5095 if (wnd_sum < lso_mss) {
5099 /* run through the windows */
5100 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
5101 /* subtract the first mbuf->m_len of the last wndw(-header) */
5102 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
5103 /* add the next mbuf len to the len of our new window */
5104 wnd_sum += htole16(segs[frag_idx].ds_len);
5105 if (wnd_sum < lso_mss) {
5114 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp,
5116 uint32_t *parsing_data)
5118 struct ether_vlan_header *eh = NULL;
5119 struct ip *ip4 = NULL;
5120 struct ip6_hdr *ip6 = NULL;
5122 struct tcphdr *th = NULL;
5123 int e_hlen, ip_hlen, l4_off;
5126 if (m->m_pkthdr.csum_flags == CSUM_IP) {
5127 /* no L4 checksum offload needed */
5131 /* get the Ethernet header */
5132 eh = mtod(m, struct ether_vlan_header *);
5134 /* handle VLAN encapsulation if present */
5135 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
5136 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
5137 proto = ntohs(eh->evl_proto);
5139 e_hlen = ETHER_HDR_LEN;
5140 proto = ntohs(eh->evl_encap_proto);
5145 /* get the IP header, if mbuf len < 20 then header in next mbuf */
5146 ip4 = (m->m_len < sizeof(struct ip)) ?
5147 (struct ip *)m->m_next->m_data :
5148 (struct ip *)(m->m_data + e_hlen);
5149 /* ip_hl is number of 32-bit words */
5150 ip_hlen = (ip4->ip_hl << 2);
5153 case ETHERTYPE_IPV6:
5154 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
5155 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5156 (struct ip6_hdr *)m->m_next->m_data :
5157 (struct ip6_hdr *)(m->m_data + e_hlen);
5158 /* XXX cannot support offload with IPv6 extensions */
5159 ip_hlen = sizeof(struct ip6_hdr);
5163 /* We can't offload in this case... */
5164 /* XXX error stat ??? */
5168 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5169 l4_off = (e_hlen + ip_hlen);
5172 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) &
5173 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W);
5175 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5178 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5179 th = (struct tcphdr *)(ip + ip_hlen);
5180 /* th_off is number of 32-bit words */
5181 *parsing_data |= ((th->th_off <<
5182 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
5183 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW);
5184 return (l4_off + (th->th_off << 2)); /* entire header length */
5185 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5187 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5188 return (l4_off + sizeof(struct udphdr)); /* entire header length */
5190 /* XXX error stat ??? */
5196 bxe_set_pbd_csum(struct bxe_fastpath *fp,
5198 struct eth_tx_parse_bd_e1x *pbd)
5200 struct ether_vlan_header *eh = NULL;
5201 struct ip *ip4 = NULL;
5202 struct ip6_hdr *ip6 = NULL;
5204 struct tcphdr *th = NULL;
5205 struct udphdr *uh = NULL;
5206 int e_hlen, ip_hlen;
5212 /* get the Ethernet header */
5213 eh = mtod(m, struct ether_vlan_header *);
5215 /* handle VLAN encapsulation if present */
5216 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
5217 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
5218 proto = ntohs(eh->evl_proto);
5220 e_hlen = ETHER_HDR_LEN;
5221 proto = ntohs(eh->evl_encap_proto);
5226 /* get the IP header, if mbuf len < 20 then header in next mbuf */
5227 ip4 = (m->m_len < sizeof(struct ip)) ?
5228 (struct ip *)m->m_next->m_data :
5229 (struct ip *)(m->m_data + e_hlen);
5230 /* ip_hl is number of 32-bit words */
5231 ip_hlen = (ip4->ip_hl << 1);
5234 case ETHERTYPE_IPV6:
5235 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */
5236 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ?
5237 (struct ip6_hdr *)m->m_next->m_data :
5238 (struct ip6_hdr *)(m->m_data + e_hlen);
5239 /* XXX cannot support offload with IPv6 extensions */
5240 ip_hlen = (sizeof(struct ip6_hdr) >> 1);
5244 /* We can't offload in this case... */
5245 /* XXX error stat ??? */
5249 hlen = (e_hlen >> 1);
5251 /* note that rest of global_data is indirectly zeroed here */
5252 if (m->m_flags & M_VLANTAG) {
5254 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
5256 pbd->global_data = htole16(hlen);
5259 pbd->ip_hlen_w = ip_hlen;
5261 hlen += pbd->ip_hlen_w;
5263 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */
5265 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5268 th = (struct tcphdr *)(ip + (ip_hlen << 1));
5269 /* th_off is number of 32-bit words */
5270 hlen += (uint16_t)(th->th_off << 1);
5271 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5273 uh = (struct udphdr *)(ip + (ip_hlen << 1));
5274 hlen += (sizeof(struct udphdr) / 2);
5276 /* valid case as only CSUM_IP was set */
5280 pbd->total_hlen_w = htole16(hlen);
5282 if (m->m_pkthdr.csum_flags & (CSUM_TCP |
5285 fp->eth_q_stats.tx_ofld_frames_csum_tcp++;
5286 pbd->tcp_pseudo_csum = ntohs(th->th_sum);
5287 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP |
5289 fp->eth_q_stats.tx_ofld_frames_csum_udp++;
5292 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP
5293 * checksums and does not know anything about the UDP header and where
5294 * the checksum field is located. It only knows about TCP. Therefore
5295 * we "lie" to the hardware for outgoing UDP packets w/ checksum
5296 * offload. Since the checksum field offset for TCP is 16 bytes and
5297 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10
5298 * bytes less than the start of the UDP header. This allows the
5299 * hardware to write the checksum in the correct spot. But the
5300 * hardware will compute a checksum which includes the last 10 bytes
5301 * of the IP header. To correct this we tweak the stack computed
5302 * pseudo checksum by folding in the calculation of the inverse
5303 * checksum for those final 10 bytes of the IP header. This allows
5304 * the correct checksum to be computed by the hardware.
5307 /* set pointer 10 bytes before UDP header */
5308 tmp_uh = (uint32_t *)((uint8_t *)uh - 10);
5310 /* calculate a pseudo header checksum over the first 10 bytes */
5311 tmp_csum = in_pseudo(*tmp_uh,
5313 *(uint16_t *)(tmp_uh + 2));
5315 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum));
5318 return (hlen * 2); /* entire header length, number of bytes */
5322 bxe_set_pbd_lso_e2(struct mbuf *m,
5323 uint32_t *parsing_data)
5325 *parsing_data |= ((m->m_pkthdr.tso_segsz <<
5326 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
5327 ETH_TX_PARSE_BD_E2_LSO_MSS);
5329 /* XXX test for IPv6 with extension header... */
5331 struct ip6_hdr *ip6;
5332 if (ip6 && ip6->ip6_nxt == 'some ipv6 extension header')
5333 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
5338 bxe_set_pbd_lso(struct mbuf *m,
5339 struct eth_tx_parse_bd_e1x *pbd)
5341 struct ether_vlan_header *eh = NULL;
5342 struct ip *ip = NULL;
5343 struct tcphdr *th = NULL;
5346 /* get the Ethernet header */
5347 eh = mtod(m, struct ether_vlan_header *);
5349 /* handle VLAN encapsulation if present */
5350 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ?
5351 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN;
5353 /* get the IP and TCP header, with LSO entire header in first mbuf */
5354 /* XXX assuming IPv4 */
5355 ip = (struct ip *)(m->m_data + e_hlen);
5356 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
5358 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz);
5359 pbd->tcp_send_seq = ntohl(th->th_seq);
5360 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff);
5364 pbd->ip_id = ntohs(ip->ip_id);
5365 pbd->tcp_pseudo_csum =
5366 ntohs(in_pseudo(ip->ip_src.s_addr,
5368 htons(IPPROTO_TCP)));
5371 pbd->tcp_pseudo_csum =
5372 ntohs(in_pseudo(&ip6->ip6_src,
5374 htons(IPPROTO_TCP)));
5378 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
5382 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory
5383 * visible to the controller.
5385 * If an mbuf is submitted to this routine and cannot be given to the
5386 * controller (e.g. it has too many fragments) then the function may free
5387 * the mbuf and return to the caller.
5390 * 0 = Success, !0 = Failure
5391 * Note the side effect that an mbuf may be freed if it causes a problem.
5394 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
5396 bus_dma_segment_t segs[32];
5398 struct bxe_sw_tx_bd *tx_buf;
5399 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
5400 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
5401 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */
5402 struct eth_tx_bd *tx_data_bd;
5403 struct eth_tx_bd *tx_total_pkt_size_bd;
5404 struct eth_tx_start_bd *tx_start_bd;
5405 uint16_t bd_prod, pkt_prod, total_pkt_size;
5407 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan;
5408 struct bxe_softc *sc;
5409 uint16_t tx_bd_avail;
5410 struct ether_vlan_header *eh;
5411 uint32_t pbd_e2_parsing_data = 0;
5418 M_ASSERTPKTHDR(*m_head);
5421 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
5424 tx_total_pkt_size_bd = NULL;
5426 /* get the H/W pointer for packets and BDs */
5427 pkt_prod = fp->tx_pkt_prod;
5428 bd_prod = fp->tx_bd_prod;
5430 mac_type = UNICAST_ADDRESS;
5432 /* map the mbuf into the next open DMAable memory */
5433 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)];
5434 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5436 segs, &nsegs, BUS_DMA_NOWAIT);
5438 /* mapping errors */
5439 if(__predict_false(error != 0)) {
5440 fp->eth_q_stats.tx_dma_mapping_failure++;
5441 if (error == ENOMEM) {
5442 /* resource issue, try again later */
5444 } else if (error == EFBIG) {
5445 /* possibly recoverable with defragmentation */
5446 fp->eth_q_stats.mbuf_defrag_attempts++;
5447 m0 = m_defrag(*m_head, M_DONTWAIT);
5449 fp->eth_q_stats.mbuf_defrag_failures++;
5452 /* defrag successful, try mapping again */
5454 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5456 segs, &nsegs, BUS_DMA_NOWAIT);
5458 fp->eth_q_stats.tx_dma_mapping_failure++;
5463 /* unknown, unrecoverable mapping error */
5464 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error);
5465 bxe_dump_mbuf(sc, m0, FALSE);
5469 goto bxe_tx_encap_continue;
5472 tx_bd_avail = bxe_tx_avail(sc, fp);
5474 /* make sure there is enough room in the send queue */
5475 if (__predict_false(tx_bd_avail < (nsegs + 2))) {
5476 /* Recoverable, try again later. */
5477 fp->eth_q_stats.tx_hw_queue_full++;
5478 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5480 goto bxe_tx_encap_continue;
5483 /* capture the current H/W TX chain high watermark */
5484 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth <
5485 (TX_BD_USABLE - tx_bd_avail))) {
5486 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail);
5489 /* make sure it fits in the packet window */
5490 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5492 * The mbuf may be to big for the controller to handle. If the frame
5493 * is a TSO frame we'll need to do an additional check.
5495 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5496 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) {
5497 goto bxe_tx_encap_continue; /* OK to send */
5499 fp->eth_q_stats.tx_window_violation_tso++;
5502 fp->eth_q_stats.tx_window_violation_std++;
5505 /* lets try to defragment this mbuf and remap it */
5506 fp->eth_q_stats.mbuf_defrag_attempts++;
5507 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5509 m0 = m_defrag(*m_head, M_DONTWAIT);
5511 fp->eth_q_stats.mbuf_defrag_failures++;
5512 /* Ugh, just drop the frame... :( */
5515 /* defrag successful, try mapping again */
5517 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag,
5519 segs, &nsegs, BUS_DMA_NOWAIT);
5521 fp->eth_q_stats.tx_dma_mapping_failure++;
5522 /* No sense in trying to defrag/copy chain, drop it. :( */
5526 /* if the chain is still too long then drop it */
5527 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) {
5528 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map);
5535 bxe_tx_encap_continue:
5537 /* Check for errors */
5540 /* recoverable try again later */
5542 fp->eth_q_stats.tx_soft_errors++;
5543 fp->eth_q_stats.mbuf_alloc_tx--;
5551 /* set flag according to packet type (UNICAST_ADDRESS is default) */
5552 if (m0->m_flags & M_BCAST) {
5553 mac_type = BROADCAST_ADDRESS;
5554 } else if (m0->m_flags & M_MCAST) {
5555 mac_type = MULTICAST_ADDRESS;
5558 /* store the mbuf into the mbuf ring */
5560 tx_buf->first_bd = fp->tx_bd_prod;
5563 /* prepare the first transmit (start) BD for the mbuf */
5564 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd;
5567 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n",
5568 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd);
5570 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
5571 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
5572 tx_start_bd->nbytes = htole16(segs[0].ds_len);
5573 total_pkt_size += tx_start_bd->nbytes;
5574 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
5576 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
5578 /* all frames have at least Start BD + Parsing BD */
5580 tx_start_bd->nbd = htole16(nbds);
5582 if (m0->m_flags & M_VLANTAG) {
5583 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag);
5584 tx_start_bd->bd_flags.as_bitfield |=
5585 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
5587 /* vf tx, start bd must hold the ethertype for fw to enforce it */
5589 /* map ethernet header to find type and header length */
5590 eh = mtod(m0, struct ether_vlan_header *);
5591 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto;
5593 /* used by FW for packet accounting */
5594 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod);
5597 * If NPAR-SD is active then FW should do the tagging regardless
5598 * of value of priority. Otherwise, if priority indicates this is
5599 * a control packet we need to indicate to FW to avoid tagging.
5601 if (!IS_MF_AFEX(sc) && (mbuf priority == PRIO_CONTROL)) {
5602 SET_FLAG(tx_start_bd->general_data,
5603 ETH_TX_START_BD_FORCE_VLAN_MODE, 1);
5610 * add a parsing BD from the chain. The parsing BD is always added
5611 * though it is only used for TSO and chksum
5613 bd_prod = TX_BD_NEXT(bd_prod);
5615 if (m0->m_pkthdr.csum_flags) {
5616 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
5617 fp->eth_q_stats.tx_ofld_frames_csum_ip++;
5618 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
5621 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) {
5622 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5623 ETH_TX_BD_FLAGS_L4_CSUM);
5624 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) {
5625 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 |
5626 ETH_TX_BD_FLAGS_IS_UDP |
5627 ETH_TX_BD_FLAGS_L4_CSUM);
5628 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) ||
5629 (m0->m_pkthdr.csum_flags & CSUM_TSO)) {
5630 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
5631 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
5632 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM |
5633 ETH_TX_BD_FLAGS_IS_UDP);
5637 if (!CHIP_IS_E1x(sc)) {
5638 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2;
5639 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
5641 if (m0->m_pkthdr.csum_flags) {
5642 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data);
5647 * Add the MACs to the parsing BD if the module param was
5648 * explicitly set, if this is a vf, or in switch independent
5651 if (sc->flags & BXE_TX_SWITCHING || IS_VF(sc) || IS_MF_SI(sc)) {
5652 eh = mtod(m0, struct ether_vlan_header *);
5653 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
5654 &pbd_e2->data.mac_addr.src_mid,
5655 &pbd_e2->data.mac_addr.src_lo,
5657 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
5658 &pbd_e2->data.mac_addr.dst_mid,
5659 &pbd_e2->data.mac_addr.dst_lo,
5664 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE,
5667 uint16_t global_data = 0;
5669 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x;
5670 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
5672 if (m0->m_pkthdr.csum_flags) {
5673 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x);
5676 SET_FLAG(global_data,
5677 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
5678 pbd_e1x->global_data |= htole16(global_data);
5681 /* setup the parsing BD with TSO specific info */
5682 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
5683 fp->eth_q_stats.tx_ofld_frames_lso++;
5684 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
5686 if (__predict_false(tx_start_bd->nbytes > hlen)) {
5687 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++;
5689 /* split the first BD into header/data making the fw job easy */
5691 tx_start_bd->nbd = htole16(nbds);
5692 tx_start_bd->nbytes = htole16(hlen);
5694 bd_prod = TX_BD_NEXT(bd_prod);
5696 /* new transmit BD after the tx_parse_bd */
5697 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5698 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen));
5699 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen));
5700 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen);
5701 if (tx_total_pkt_size_bd == NULL) {
5702 tx_total_pkt_size_bd = tx_data_bd;
5706 "TSO split header size is %d (%x:%x) nbds %d\n",
5707 le16toh(tx_start_bd->nbytes),
5708 le32toh(tx_start_bd->addr_hi),
5709 le32toh(tx_start_bd->addr_lo),
5713 if (!CHIP_IS_E1x(sc)) {
5714 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data);
5716 bxe_set_pbd_lso(m0, pbd_e1x);
5720 if (pbd_e2_parsing_data) {
5721 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data);
5724 /* prepare remaining BDs, start tx bd contains first seg/frag */
5725 for (i = 1; i < nsegs ; i++) {
5726 bd_prod = TX_BD_NEXT(bd_prod);
5727 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd;
5728 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
5729 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
5730 tx_data_bd->nbytes = htole16(segs[i].ds_len);
5731 if (tx_total_pkt_size_bd == NULL) {
5732 tx_total_pkt_size_bd = tx_data_bd;
5734 total_pkt_size += tx_data_bd->nbytes;
5737 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd);
5739 if (tx_total_pkt_size_bd != NULL) {
5740 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
5743 if (__predict_false(sc->debug & DBG_TX)) {
5744 tmp_bd = tx_buf->first_bd;
5745 for (i = 0; i < nbds; i++)
5749 "TX Strt: %p bd=%d nbd=%d vlan=0x%x "
5750 "bd_flags=0x%x hdr_nbds=%d\n",
5753 le16toh(tx_start_bd->nbd),
5754 le16toh(tx_start_bd->vlan_or_ethertype),
5755 tx_start_bd->bd_flags.as_bitfield,
5756 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS));
5757 } else if (i == 1) {
5760 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u "
5761 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x "
5762 "tcp_seq=%u total_hlen_w=%u\n",
5765 pbd_e1x->global_data,
5770 pbd_e1x->tcp_pseudo_csum,
5771 pbd_e1x->tcp_send_seq,
5772 le16toh(pbd_e1x->total_hlen_w));
5773 } else { /* if (pbd_e2) */
5775 "-> Parse: %p bd=%d dst=%02x:%02x:%02x "
5776 "src=%02x:%02x:%02x parsing_data=0x%x\n",
5779 pbd_e2->data.mac_addr.dst_hi,
5780 pbd_e2->data.mac_addr.dst_mid,
5781 pbd_e2->data.mac_addr.dst_lo,
5782 pbd_e2->data.mac_addr.src_hi,
5783 pbd_e2->data.mac_addr.src_mid,
5784 pbd_e2->data.mac_addr.src_lo,
5785 pbd_e2->parsing_data);
5789 if (i != 1) { /* skip parse db as it doesn't hold data */
5790 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd;
5792 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n",
5795 le16toh(tx_data_bd->nbytes),
5796 le32toh(tx_data_bd->addr_hi),
5797 le32toh(tx_data_bd->addr_lo));
5800 tmp_bd = TX_BD_NEXT(tmp_bd);
5804 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod);
5806 /* update TX BD producer index value for next TX */
5807 bd_prod = TX_BD_NEXT(bd_prod);
5810 * If the chain of tx_bd's describing this frame is adjacent to or spans
5811 * an eth_tx_next_bd element then we need to increment the nbds value.
5813 if (TX_BD_IDX(bd_prod) < nbds) {
5817 /* don't allow reordering of writes for nbd and packets */
5820 fp->tx_db.data.prod += nbds;
5822 /* producer points to the next free tx_bd at this point */
5824 fp->tx_bd_prod = bd_prod;
5826 DOORBELL(sc, fp->index, fp->tx_db.raw);
5828 fp->eth_q_stats.tx_pkts++;
5830 /* Prevent speculative reads from getting ahead of the status block. */
5831 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle,
5832 0, 0, BUS_SPACE_BARRIER_READ);
5834 /* Prevent speculative reads from getting ahead of the doorbell. */
5835 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle,
5836 0, 0, BUS_SPACE_BARRIER_READ);
5842 bxe_tx_start_locked(struct bxe_softc *sc,
5844 struct bxe_fastpath *fp)
5846 struct mbuf *m = NULL;
5848 uint16_t tx_bd_avail;
5850 BXE_FP_TX_LOCK_ASSERT(fp);
5852 /* keep adding entries while there are frames to send */
5853 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5856 * check for any frames to send
5857 * dequeue can still be NULL even if queue is not empty
5859 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
5860 if (__predict_false(m == NULL)) {
5864 /* the mbuf now belongs to us */
5865 fp->eth_q_stats.mbuf_alloc_tx++;
5868 * Put the frame into the transmit ring. If we don't have room,
5869 * place the mbuf back at the head of the TX queue, set the
5870 * OACTIVE flag, and wait for the NIC to drain the chain.
5872 if (__predict_false(bxe_tx_encap(fp, &m))) {
5873 fp->eth_q_stats.tx_encap_failures++;
5875 /* mark the TX queue as full and return the frame */
5876 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5877 IFQ_DRV_PREPEND(&ifp->if_snd, m);
5878 fp->eth_q_stats.mbuf_alloc_tx--;
5879 fp->eth_q_stats.tx_queue_xoff++;
5882 /* stop looking for more work */
5886 /* the frame was enqueued successfully */
5889 /* send a copy of the frame to any BPF listeners. */
5892 tx_bd_avail = bxe_tx_avail(sc, fp);
5894 /* handle any completions if we're running low */
5895 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
5896 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
5898 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5904 /* all TX packets were dequeued and/or the tx ring is full */
5906 /* reset the TX watchdog timeout timer */
5907 fp->watchdog_timer = BXE_TX_TIMEOUT;
5911 /* Legacy (non-RSS) dispatch routine */
5913 bxe_tx_start(struct ifnet *ifp)
5915 struct bxe_softc *sc;
5916 struct bxe_fastpath *fp;
5920 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
5921 BLOGW(sc, "Interface not running, ignoring transmit request\n");
5925 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
5926 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n");
5930 if (!sc->link_vars.link_up) {
5931 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
5938 bxe_tx_start_locked(sc, ifp, fp);
5939 BXE_FP_TX_UNLOCK(fp);
5942 #if __FreeBSD_version >= 800000
5945 bxe_tx_mq_start_locked(struct bxe_softc *sc,
5947 struct bxe_fastpath *fp,
5950 struct buf_ring *tx_br = fp->tx_br;
5952 int depth, rc, tx_count;
5953 uint16_t tx_bd_avail;
5958 BLOGE(sc, "Multiqueue TX and no buf_ring!\n");
5962 /* fetch the depth of the driver queue */
5963 depth = drbr_inuse(ifp, tx_br);
5964 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) {
5965 fp->eth_q_stats.tx_max_drbr_queue_depth = depth;
5968 BXE_FP_TX_LOCK_ASSERT(fp);
5971 /* no new work, check for pending frames */
5972 next = drbr_dequeue(ifp, tx_br);
5973 } else if (drbr_needs_enqueue(ifp, tx_br)) {
5974 /* have both new and pending work, maintain packet order */
5975 rc = drbr_enqueue(ifp, tx_br, m);
5977 fp->eth_q_stats.tx_soft_errors++;
5978 goto bxe_tx_mq_start_locked_exit;
5980 next = drbr_dequeue(ifp, tx_br);
5982 /* new work only and nothing pending */
5986 /* keep adding entries while there are frames to send */
5987 while (next != NULL) {
5989 /* the mbuf now belongs to us */
5990 fp->eth_q_stats.mbuf_alloc_tx++;
5993 * Put the frame into the transmit ring. If we don't have room,
5994 * place the mbuf back at the head of the TX queue, set the
5995 * OACTIVE flag, and wait for the NIC to drain the chain.
5997 rc = bxe_tx_encap(fp, &next);
5998 if (__predict_false(rc != 0)) {
5999 fp->eth_q_stats.tx_encap_failures++;
6001 /* mark the TX queue as full and save the frame */
6002 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
6003 /* XXX this may reorder the frame */
6004 rc = drbr_enqueue(ifp, tx_br, next);
6005 fp->eth_q_stats.mbuf_alloc_tx--;
6006 fp->eth_q_stats.tx_frames_deferred++;
6009 /* stop looking for more work */
6013 /* the transmit frame was enqueued successfully */
6016 /* send a copy of the frame to any BPF listeners */
6017 BPF_MTAP(ifp, next);
6019 tx_bd_avail = bxe_tx_avail(sc, fp);
6021 /* handle any completions if we're running low */
6022 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) {
6023 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */
6025 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
6030 next = drbr_dequeue(ifp, tx_br);
6033 /* all TX packets were dequeued and/or the tx ring is full */
6035 /* reset the TX watchdog timeout timer */
6036 fp->watchdog_timer = BXE_TX_TIMEOUT;
6039 bxe_tx_mq_start_locked_exit:
6044 /* Multiqueue (TSS) dispatch routine. */
6046 bxe_tx_mq_start(struct ifnet *ifp,
6049 struct bxe_softc *sc = ifp->if_softc;
6050 struct bxe_fastpath *fp;
6053 fp_index = 0; /* default is the first queue */
6055 /* change the queue if using flow ID */
6056 if ((m->m_flags & M_FLOWID) != 0) {
6057 fp_index = (m->m_pkthdr.flowid % sc->num_queues);
6060 fp = &sc->fp[fp_index];
6062 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
6063 BLOGW(sc, "Interface not running, ignoring transmit request\n");
6067 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
6068 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n");
6072 if (!sc->link_vars.link_up) {
6073 BLOGW(sc, "Interface link is down, ignoring transmit request\n");
6077 /* XXX change to TRYLOCK here and if failed then schedule taskqueue */
6080 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m);
6081 BXE_FP_TX_UNLOCK(fp);
6087 bxe_mq_flush(struct ifnet *ifp)
6089 struct bxe_softc *sc = ifp->if_softc;
6090 struct bxe_fastpath *fp;
6094 for (i = 0; i < sc->num_queues; i++) {
6097 if (fp->state != BXE_FP_STATE_OPEN) {
6098 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n",
6099 fp->index, fp->state);
6103 if (fp->tx_br != NULL) {
6104 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index);
6106 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
6109 BXE_FP_TX_UNLOCK(fp);
6116 #endif /* FreeBSD_version >= 800000 */
6119 bxe_cid_ilt_lines(struct bxe_softc *sc)
6122 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS);
6124 return (L2_ILT_LINES(sc));
6128 bxe_ilt_set_info(struct bxe_softc *sc)
6130 struct ilt_client_info *ilt_client;
6131 struct ecore_ilt *ilt = sc->ilt;
6134 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc));
6135 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line);
6138 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6139 ilt_client->client_num = ILT_CLIENT_CDU;
6140 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6141 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6142 ilt_client->start = line;
6143 line += bxe_cid_ilt_lines(sc);
6145 if (CNIC_SUPPORT(sc)) {
6146 line += CNIC_ILT_LINES;
6149 ilt_client->end = (line - 1);
6152 "ilt client[CDU]: start %d, end %d, "
6153 "psz 0x%x, flags 0x%x, hw psz %d\n",
6154 ilt_client->start, ilt_client->end,
6155 ilt_client->page_size,
6157 ilog2(ilt_client->page_size >> 12));
6160 if (QM_INIT(sc->qm_cid_count)) {
6161 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6162 ilt_client->client_num = ILT_CLIENT_QM;
6163 ilt_client->page_size = QM_ILT_PAGE_SZ;
6164 ilt_client->flags = 0;
6165 ilt_client->start = line;
6167 /* 4 bytes for each cid */
6168 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6171 ilt_client->end = (line - 1);
6174 "ilt client[QM]: start %d, end %d, "
6175 "psz 0x%x, flags 0x%x, hw psz %d\n",
6176 ilt_client->start, ilt_client->end,
6177 ilt_client->page_size, ilt_client->flags,
6178 ilog2(ilt_client->page_size >> 12));
6181 if (CNIC_SUPPORT(sc)) {
6183 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6184 ilt_client->client_num = ILT_CLIENT_SRC;
6185 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6186 ilt_client->flags = 0;
6187 ilt_client->start = line;
6188 line += SRC_ILT_LINES;
6189 ilt_client->end = (line - 1);
6192 "ilt client[SRC]: start %d, end %d, "
6193 "psz 0x%x, flags 0x%x, hw psz %d\n",
6194 ilt_client->start, ilt_client->end,
6195 ilt_client->page_size, ilt_client->flags,
6196 ilog2(ilt_client->page_size >> 12));
6199 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6200 ilt_client->client_num = ILT_CLIENT_TM;
6201 ilt_client->page_size = TM_ILT_PAGE_SZ;
6202 ilt_client->flags = 0;
6203 ilt_client->start = line;
6204 line += TM_ILT_LINES;
6205 ilt_client->end = (line - 1);
6208 "ilt client[TM]: start %d, end %d, "
6209 "psz 0x%x, flags 0x%x, hw psz %d\n",
6210 ilt_client->start, ilt_client->end,
6211 ilt_client->page_size, ilt_client->flags,
6212 ilog2(ilt_client->page_size >> 12));
6215 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!"));
6219 bxe_set_fp_rx_buf_size(struct bxe_softc *sc)
6223 BLOGD(sc, DBG_LOAD, "mtu = %d\n", sc->mtu);
6225 for (i = 0; i < sc->num_queues; i++) {
6226 /* get the Rx buffer size for RX frames */
6227 sc->fp[i].rx_buf_size =
6228 (IP_HEADER_ALIGNMENT_PADDING +
6232 BLOGD(sc, DBG_LOAD, "rx_buf_size for fp[%02d] = %d\n",
6233 i, sc->fp[i].rx_buf_size);
6235 /* get the mbuf allocation size for RX frames */
6236 if (sc->fp[i].rx_buf_size <= MCLBYTES) {
6237 sc->fp[i].mbuf_alloc_size = MCLBYTES;
6238 } else if (sc->fp[i].rx_buf_size <= BCM_PAGE_SIZE) {
6239 sc->fp[i].mbuf_alloc_size = PAGE_SIZE;
6241 sc->fp[i].mbuf_alloc_size = MJUM9BYTES;
6244 BLOGD(sc, DBG_LOAD, "mbuf_alloc_size for fp[%02d] = %d\n",
6245 i, sc->fp[i].mbuf_alloc_size);
6250 bxe_alloc_ilt_mem(struct bxe_softc *sc)
6255 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt),
6257 (M_NOWAIT | M_ZERO))) == NULL) {
6265 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc)
6269 if ((sc->ilt->lines =
6270 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES),
6272 (M_NOWAIT | M_ZERO))) == NULL) {
6280 bxe_free_ilt_mem(struct bxe_softc *sc)
6282 if (sc->ilt != NULL) {
6283 free(sc->ilt, M_BXE_ILT);
6289 bxe_free_ilt_lines_mem(struct bxe_softc *sc)
6291 if (sc->ilt->lines != NULL) {
6292 free(sc->ilt->lines, M_BXE_ILT);
6293 sc->ilt->lines = NULL;
6298 bxe_free_mem(struct bxe_softc *sc)
6303 if (!CONFIGURE_NIC_MODE(sc)) {
6304 /* free searcher T2 table */
6305 bxe_dma_free(sc, &sc->t2);
6309 for (i = 0; i < L2_ILT_LINES(sc); i++) {
6310 bxe_dma_free(sc, &sc->context[i].vcxt_dma);
6311 sc->context[i].vcxt = NULL;
6312 sc->context[i].size = 0;
6315 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE);
6317 bxe_free_ilt_lines_mem(sc);
6320 bxe_iov_free_mem(sc);
6325 bxe_alloc_mem(struct bxe_softc *sc)
6332 if (!CONFIGURE_NIC_MODE(sc)) {
6333 /* allocate searcher T2 table */
6334 if (bxe_dma_alloc(sc, SRC_T2_SZ,
6335 &sc->t2, "searcher t2 table") != 0) {
6342 * Allocate memory for CDU context:
6343 * This memory is allocated separately and not in the generic ILT
6344 * functions because CDU differs in few aspects:
6345 * 1. There can be multiple entities allocating memory for context -
6346 * regular L2, CNIC, and SRIOV drivers. Each separately controls
6347 * its own ILT lines.
6348 * 2. Since CDU page-size is not a single 4KB page (which is the case
6349 * for the other ILT clients), to be efficient we want to support
6350 * allocation of sub-page-size in the last entry.
6351 * 3. Context pointers are used by the driver to pass to FW / update
6352 * the context (for the other ILT clients the pointers are used just to
6353 * free the memory during unload).
6355 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc));
6356 for (i = 0, allocated = 0; allocated < context_size; i++) {
6357 sc->context[i].size = min(CDU_ILT_PAGE_SZ,
6358 (context_size - allocated));
6360 if (bxe_dma_alloc(sc, sc->context[i].size,
6361 &sc->context[i].vcxt_dma,
6362 "cdu context") != 0) {
6367 sc->context[i].vcxt =
6368 (union cdu_context *)sc->context[i].vcxt_dma.vaddr;
6370 allocated += sc->context[i].size;
6373 bxe_alloc_ilt_lines_mem(sc);
6375 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n",
6376 sc->ilt, sc->ilt->start_line, sc->ilt->lines);
6378 for (i = 0; i < 4; i++) {
6380 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n",
6382 sc->ilt->clients[i].page_size,
6383 sc->ilt->clients[i].start,
6384 sc->ilt->clients[i].end,
6385 sc->ilt->clients[i].client_num,
6386 sc->ilt->clients[i].flags);
6389 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) {
6390 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n");
6396 if (bxe_iov_alloc_mem(sc)) {
6397 BLOGE(sc, "Failed to allocate memory for SRIOV\n");
6407 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
6409 struct bxe_softc *sc;
6414 if (fp->rx_mbuf_tag == NULL) {
6418 /* free all mbufs and unload all maps */
6419 for (i = 0; i < RX_BD_TOTAL; i++) {
6420 if (fp->rx_mbuf_chain[i].m_map != NULL) {
6421 bus_dmamap_sync(fp->rx_mbuf_tag,
6422 fp->rx_mbuf_chain[i].m_map,
6423 BUS_DMASYNC_POSTREAD);
6424 bus_dmamap_unload(fp->rx_mbuf_tag,
6425 fp->rx_mbuf_chain[i].m_map);
6428 if (fp->rx_mbuf_chain[i].m != NULL) {
6429 m_freem(fp->rx_mbuf_chain[i].m);
6430 fp->rx_mbuf_chain[i].m = NULL;
6431 fp->eth_q_stats.mbuf_alloc_rx--;
6437 bxe_free_tpa_pool(struct bxe_fastpath *fp)
6439 struct bxe_softc *sc;
6440 int i, max_agg_queues;
6444 if (fp->rx_mbuf_tag == NULL) {
6448 max_agg_queues = MAX_AGG_QS(sc);
6450 /* release all mbufs and unload all DMA maps in the TPA pool */
6451 for (i = 0; i < max_agg_queues; i++) {
6452 if (fp->rx_tpa_info[i].bd.m_map != NULL) {
6453 bus_dmamap_sync(fp->rx_mbuf_tag,
6454 fp->rx_tpa_info[i].bd.m_map,
6455 BUS_DMASYNC_POSTREAD);
6456 bus_dmamap_unload(fp->rx_mbuf_tag,
6457 fp->rx_tpa_info[i].bd.m_map);
6460 if (fp->rx_tpa_info[i].bd.m != NULL) {
6461 m_freem(fp->rx_tpa_info[i].bd.m);
6462 fp->rx_tpa_info[i].bd.m = NULL;
6463 fp->eth_q_stats.mbuf_alloc_tpa--;
6469 bxe_free_sge_chain(struct bxe_fastpath *fp)
6471 struct bxe_softc *sc;
6476 if (fp->rx_sge_mbuf_tag == NULL) {
6480 /* rree all mbufs and unload all maps */
6481 for (i = 0; i < RX_SGE_TOTAL; i++) {
6482 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) {
6483 bus_dmamap_sync(fp->rx_sge_mbuf_tag,
6484 fp->rx_sge_mbuf_chain[i].m_map,
6485 BUS_DMASYNC_POSTREAD);
6486 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
6487 fp->rx_sge_mbuf_chain[i].m_map);
6490 if (fp->rx_sge_mbuf_chain[i].m != NULL) {
6491 m_freem(fp->rx_sge_mbuf_chain[i].m);
6492 fp->rx_sge_mbuf_chain[i].m = NULL;
6493 fp->eth_q_stats.mbuf_alloc_sge--;
6499 bxe_free_fp_buffers(struct bxe_softc *sc)
6501 struct bxe_fastpath *fp;
6504 for (i = 0; i < sc->num_queues; i++) {
6507 #if __FreeBSD_version >= 800000
6508 if (fp->tx_br != NULL) {
6510 /* just in case bxe_mq_flush() wasn't called */
6511 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) {
6514 buf_ring_free(fp->tx_br, M_DEVBUF);
6519 /* free all RX buffers */
6520 bxe_free_rx_bd_chain(fp);
6521 bxe_free_tpa_pool(fp);
6522 bxe_free_sge_chain(fp);
6524 if (fp->eth_q_stats.mbuf_alloc_rx != 0) {
6525 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n",
6526 fp->eth_q_stats.mbuf_alloc_rx);
6529 if (fp->eth_q_stats.mbuf_alloc_sge != 0) {
6530 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6531 fp->eth_q_stats.mbuf_alloc_sge);
6534 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) {
6535 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n",
6536 fp->eth_q_stats.mbuf_alloc_tpa);
6539 if (fp->eth_q_stats.mbuf_alloc_tx != 0) {
6540 BLOGE(sc, "failed to release tx mbufs (%d left)\n",
6541 fp->eth_q_stats.mbuf_alloc_tx);
6544 /* XXX verify all mbufs were reclaimed */
6546 if (mtx_initialized(&fp->tx_mtx)) {
6547 mtx_destroy(&fp->tx_mtx);
6550 if (mtx_initialized(&fp->rx_mtx)) {
6551 mtx_destroy(&fp->rx_mtx);
6557 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp,
6558 uint16_t prev_index,
6561 struct bxe_sw_rx_bd *rx_buf;
6562 struct eth_rx_bd *rx_bd;
6563 bus_dma_segment_t segs[1];
6570 /* allocate the new RX BD mbuf */
6571 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6572 if (__predict_false(m == NULL)) {
6573 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++;
6577 fp->eth_q_stats.mbuf_alloc_rx++;
6579 /* initialize the mbuf buffer length */
6580 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6582 /* map the mbuf into non-paged pool */
6583 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6584 fp->rx_mbuf_spare_map,
6585 m, segs, &nsegs, BUS_DMA_NOWAIT);
6586 if (__predict_false(rc != 0)) {
6587 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++;
6589 fp->eth_q_stats.mbuf_alloc_rx--;
6593 /* all mbufs must map to a single segment */
6594 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6596 /* release any existing RX BD mbuf mappings */
6598 if (prev_index != index) {
6599 rx_buf = &fp->rx_mbuf_chain[prev_index];
6601 if (rx_buf->m_map != NULL) {
6602 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6603 BUS_DMASYNC_POSTREAD);
6604 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6608 * We only get here from bxe_rxeof() when the maximum number
6609 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already
6610 * holds the mbuf in the prev_index so it's OK to NULL it out
6611 * here without concern of a memory leak.
6613 fp->rx_mbuf_chain[prev_index].m = NULL;
6616 rx_buf = &fp->rx_mbuf_chain[index];
6618 if (rx_buf->m_map != NULL) {
6619 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6620 BUS_DMASYNC_POSTREAD);
6621 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map);
6624 /* save the mbuf and mapping info for a future packet */
6625 map = (prev_index != index) ?
6626 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map;
6627 rx_buf->m_map = fp->rx_mbuf_spare_map;
6628 fp->rx_mbuf_spare_map = map;
6629 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map,
6630 BUS_DMASYNC_PREREAD);
6633 rx_bd = &fp->rx_chain[index];
6634 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6635 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6641 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp,
6644 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue];
6645 bus_dma_segment_t segs[1];
6651 /* allocate the new TPA mbuf */
6652 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size);
6653 if (__predict_false(m == NULL)) {
6654 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++;
6658 fp->eth_q_stats.mbuf_alloc_tpa++;
6660 /* initialize the mbuf buffer length */
6661 m->m_pkthdr.len = m->m_len = fp->rx_buf_size;
6663 /* map the mbuf into non-paged pool */
6664 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
6665 fp->rx_tpa_info_mbuf_spare_map,
6666 m, segs, &nsegs, BUS_DMA_NOWAIT);
6667 if (__predict_false(rc != 0)) {
6668 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++;
6670 fp->eth_q_stats.mbuf_alloc_tpa--;
6674 /* all mbufs must map to a single segment */
6675 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6677 /* release any existing TPA mbuf mapping */
6678 if (tpa_info->bd.m_map != NULL) {
6679 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6680 BUS_DMASYNC_POSTREAD);
6681 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map);
6684 /* save the mbuf and mapping info for the TPA mbuf */
6685 map = tpa_info->bd.m_map;
6686 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map;
6687 fp->rx_tpa_info_mbuf_spare_map = map;
6688 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map,
6689 BUS_DMASYNC_PREREAD);
6691 tpa_info->seg = segs[0];
6697 * Allocate an mbuf and assign it to the receive scatter gather chain. The
6698 * caller must take care to save a copy of the existing mbuf in the SG mbuf
6702 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp,
6705 struct bxe_sw_rx_bd *sge_buf;
6706 struct eth_rx_sge *sge;
6707 bus_dma_segment_t segs[1];
6713 /* allocate a new SGE mbuf */
6714 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
6715 if (__predict_false(m == NULL)) {
6716 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++;
6720 fp->eth_q_stats.mbuf_alloc_sge++;
6722 /* initialize the mbuf buffer length */
6723 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
6725 /* map the SGE mbuf into non-paged pool */
6726 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag,
6727 fp->rx_sge_mbuf_spare_map,
6728 m, segs, &nsegs, BUS_DMA_NOWAIT);
6729 if (__predict_false(rc != 0)) {
6730 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++;
6732 fp->eth_q_stats.mbuf_alloc_sge--;
6736 /* all mbufs must map to a single segment */
6737 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs));
6739 sge_buf = &fp->rx_sge_mbuf_chain[index];
6741 /* release any existing SGE mbuf mapping */
6742 if (sge_buf->m_map != NULL) {
6743 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6744 BUS_DMASYNC_POSTREAD);
6745 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map);
6748 /* save the mbuf and mapping info for a future packet */
6749 map = sge_buf->m_map;
6750 sge_buf->m_map = fp->rx_sge_mbuf_spare_map;
6751 fp->rx_sge_mbuf_spare_map = map;
6752 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map,
6753 BUS_DMASYNC_PREREAD);
6756 sge = &fp->rx_sge_chain[index];
6757 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
6758 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
6763 static __noinline int
6764 bxe_alloc_fp_buffers(struct bxe_softc *sc)
6766 struct bxe_fastpath *fp;
6768 int ring_prod, cqe_ring_prod;
6771 for (i = 0; i < sc->num_queues; i++) {
6774 #if __FreeBSD_version >= 800000
6775 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF,
6776 M_DONTWAIT, &fp->tx_mtx);
6777 if (fp->tx_br == NULL) {
6778 BLOGE(sc, "buf_ring alloc fail for fp[%02d]\n", i);
6779 goto bxe_alloc_fp_buffers_error;
6783 ring_prod = cqe_ring_prod = 0;
6787 /* allocate buffers for the RX BDs in RX BD chain */
6788 for (j = 0; j < sc->max_rx_bufs; j++) {
6789 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod);
6791 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n",
6793 goto bxe_alloc_fp_buffers_error;
6796 ring_prod = RX_BD_NEXT(ring_prod);
6797 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod);
6800 fp->rx_bd_prod = ring_prod;
6801 fp->rx_cq_prod = cqe_ring_prod;
6802 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0;
6804 if (sc->ifnet->if_capenable & IFCAP_LRO) {
6805 max_agg_queues = MAX_AGG_QS(sc);
6807 fp->tpa_enable = TRUE;
6809 /* fill the TPA pool */
6810 for (j = 0; j < max_agg_queues; j++) {
6811 rc = bxe_alloc_rx_tpa_mbuf(fp, j);
6813 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n",
6815 fp->tpa_enable = FALSE;
6816 goto bxe_alloc_fp_buffers_error;
6819 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP;
6822 if (fp->tpa_enable) {
6823 /* fill the RX SGE chain */
6825 for (j = 0; j < RX_SGE_USABLE; j++) {
6826 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod);
6828 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n",
6830 fp->tpa_enable = FALSE;
6832 goto bxe_alloc_fp_buffers_error;
6835 ring_prod = RX_SGE_NEXT(ring_prod);
6838 fp->rx_sge_prod = ring_prod;
6845 bxe_alloc_fp_buffers_error:
6847 /* unwind what was already allocated */
6848 bxe_free_rx_bd_chain(fp);
6849 bxe_free_tpa_pool(fp);
6850 bxe_free_sge_chain(fp);
6856 bxe_free_fw_stats_mem(struct bxe_softc *sc)
6858 bxe_dma_free(sc, &sc->fw_stats_dma);
6860 sc->fw_stats_num = 0;
6862 sc->fw_stats_req_size = 0;
6863 sc->fw_stats_req = NULL;
6864 sc->fw_stats_req_mapping = 0;
6866 sc->fw_stats_data_size = 0;
6867 sc->fw_stats_data = NULL;
6868 sc->fw_stats_data_mapping = 0;
6872 bxe_alloc_fw_stats_mem(struct bxe_softc *sc)
6874 uint8_t num_queue_stats;
6877 /* number of queues for statistics is number of eth queues */
6878 num_queue_stats = BXE_NUM_ETH_QUEUES(sc);
6881 * Total number of FW statistics requests =
6882 * 1 for port stats + 1 for PF stats + num of queues
6884 sc->fw_stats_num = (2 + num_queue_stats);
6887 * Request is built from stats_query_header and an array of
6888 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT
6889 * rules. The real number or requests is configured in the
6890 * stats_query_header.
6893 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) +
6894 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0));
6896 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n",
6897 sc->fw_stats_num, num_groups);
6899 sc->fw_stats_req_size =
6900 (sizeof(struct stats_query_header) +
6901 (num_groups * sizeof(struct stats_query_cmd_group)));
6904 * Data for statistics requests + stats_counter.
6905 * stats_counter holds per-STORM counters that are incremented when
6906 * STORM has finished with the current request. Memory for FCoE
6907 * offloaded statistics are counted anyway, even if they will not be sent.
6908 * VF stats are not accounted for here as the data of VF stats is stored
6909 * in memory allocated by the VF, not here.
6911 sc->fw_stats_data_size =
6912 (sizeof(struct stats_counter) +
6913 sizeof(struct per_port_stats) +
6914 sizeof(struct per_pf_stats) +
6915 /* sizeof(struct fcoe_statistics_params) + */
6916 (sizeof(struct per_queue_stats) * num_queue_stats));
6918 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size),
6919 &sc->fw_stats_dma, "fw stats") != 0) {
6920 bxe_free_fw_stats_mem(sc);
6924 /* set up the shortcuts */
6927 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr;
6928 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr;
6931 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr +
6932 sc->fw_stats_req_size);
6933 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr +
6934 sc->fw_stats_req_size);
6936 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n",
6937 (uintmax_t)sc->fw_stats_req_mapping);
6939 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n",
6940 (uintmax_t)sc->fw_stats_data_mapping);
6947 * 0-7 - Engine0 load counter.
6948 * 8-15 - Engine1 load counter.
6949 * 16 - Engine0 RESET_IN_PROGRESS bit.
6950 * 17 - Engine1 RESET_IN_PROGRESS bit.
6951 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active
6952 * function on the engine
6953 * 19 - Engine1 ONE_IS_LOADED.
6954 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
6955 * leader to complete (check for both RESET_IN_PROGRESS bits and not
6956 * for just the one belonging to its engine).
6958 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
6959 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff
6960 #define BXE_PATH0_LOAD_CNT_SHIFT 0
6961 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00
6962 #define BXE_PATH1_LOAD_CNT_SHIFT 8
6963 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000
6964 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000
6965 #define BXE_GLOBAL_RESET_BIT 0x00040000
6967 /* set the GLOBAL_RESET bit, should be run under rtnl lock */
6969 bxe_set_reset_global(struct bxe_softc *sc)
6972 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6973 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6974 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT);
6975 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6978 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */
6980 bxe_clear_reset_global(struct bxe_softc *sc)
6983 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6984 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6985 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT));
6986 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
6989 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */
6991 bxe_reset_is_global(struct bxe_softc *sc)
6993 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
6994 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val);
6995 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE;
6998 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */
7000 bxe_set_reset_done(struct bxe_softc *sc)
7003 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
7004 BXE_PATH0_RST_IN_PROG_BIT;
7006 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7008 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7011 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7013 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7016 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */
7018 bxe_set_reset_in_progress(struct bxe_softc *sc)
7021 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT :
7022 BXE_PATH0_RST_IN_PROG_BIT;
7024 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7026 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7029 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7031 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7034 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */
7036 bxe_reset_is_done(struct bxe_softc *sc,
7039 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7040 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT :
7041 BXE_PATH0_RST_IN_PROG_BIT;
7043 /* return false if bit is set */
7044 return (val & bit) ? FALSE : TRUE;
7047 /* get the load status for an engine, should be run under rtnl lock */
7049 bxe_get_load_status(struct bxe_softc *sc,
7052 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK :
7053 BXE_PATH0_LOAD_CNT_MASK;
7054 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT :
7055 BXE_PATH0_LOAD_CNT_SHIFT;
7056 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7058 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
7060 val = ((val & mask) >> shift);
7062 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val);
7067 /* set pf load mark */
7068 /* XXX needs to be under rtnl lock */
7070 bxe_set_pf_load(struct bxe_softc *sc)
7074 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
7075 BXE_PATH0_LOAD_CNT_MASK;
7076 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
7077 BXE_PATH0_LOAD_CNT_SHIFT;
7079 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7081 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7082 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val);
7084 /* get the current counter value */
7085 val1 = ((val & mask) >> shift);
7087 /* set bit of this PF */
7088 val1 |= (1 << SC_ABS_FUNC(sc));
7090 /* clear the old value */
7093 /* set the new one */
7094 val |= ((val1 << shift) & mask);
7096 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7098 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7101 /* clear pf load mark */
7102 /* XXX needs to be under rtnl lock */
7104 bxe_clear_pf_load(struct bxe_softc *sc)
7107 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK :
7108 BXE_PATH0_LOAD_CNT_MASK;
7109 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT :
7110 BXE_PATH0_LOAD_CNT_SHIFT;
7112 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7113 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);
7114 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val);
7116 /* get the current counter value */
7117 val1 = (val & mask) >> shift;
7119 /* clear bit of that PF */
7120 val1 &= ~(1 << SC_ABS_FUNC(sc));
7122 /* clear the old value */
7125 /* set the new one */
7126 val |= ((val1 << shift) & mask);
7128 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val);
7129 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG);
7133 /* send load requrest to mcp and analyze response */
7135 bxe_nic_load_request(struct bxe_softc *sc,
7136 uint32_t *load_code)
7140 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
7141 DRV_MSG_SEQ_NUMBER_MASK);
7143 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq);
7145 /* get the current FW pulse sequence */
7146 sc->fw_drv_pulse_wr_seq =
7147 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) &
7148 DRV_PULSE_SEQ_MASK);
7150 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n",
7151 sc->fw_drv_pulse_wr_seq);
7154 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
7155 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
7157 /* if the MCP fails to respond we must abort */
7158 if (!(*load_code)) {
7159 BLOGE(sc, "MCP response failure!\n");
7163 /* if MCP refused then must abort */
7164 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
7165 BLOGE(sc, "MCP refused load request\n");
7173 * Check whether another PF has already loaded FW to chip. In virtualized
7174 * environments a pf from anoth VM may have already initialized the device
7175 * including loading FW.
7178 bxe_nic_load_analyze_req(struct bxe_softc *sc,
7181 uint32_t my_fw, loaded_fw;
7183 /* is another pf loaded on this engine? */
7184 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
7185 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
7186 /* build my FW version dword */
7187 my_fw = (BCM_5710_FW_MAJOR_VERSION +
7188 (BCM_5710_FW_MINOR_VERSION << 8 ) +
7189 (BCM_5710_FW_REVISION_VERSION << 16) +
7190 (BCM_5710_FW_ENGINEERING_VERSION << 24));
7192 /* read loaded FW from chip */
7193 loaded_fw = REG_RD(sc, XSEM_REG_PRAM);
7194 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n",
7197 /* abort nic load if version mismatch */
7198 if (my_fw != loaded_fw) {
7199 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)",
7208 /* mark PMF if applicable */
7210 bxe_nic_load_pmf(struct bxe_softc *sc,
7213 uint32_t ncsi_oem_data_addr;
7215 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
7216 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
7217 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
7219 * Barrier here for ordering between the writing to sc->port.pmf here
7220 * and reading it from the periodic task.
7228 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf);
7231 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) {
7232 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) {
7233 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr);
7234 if (ncsi_oem_data_addr) {
7236 (ncsi_oem_data_addr +
7237 offsetof(struct glob_ncsi_oem_data, driver_version)),
7245 bxe_read_mf_cfg(struct bxe_softc *sc)
7247 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1);
7251 if (BXE_NOMCP(sc)) {
7252 return; /* what should be the default bvalue in this case */
7256 * The formula for computing the absolute function number is...
7257 * For 2 port configuration (4 functions per port):
7258 * abs_func = 2 * vn + SC_PORT + SC_PATH
7259 * For 4 port configuration (2 functions per port):
7260 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH
7262 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
7263 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
7264 if (abs_func >= E1H_FUNC_MAX) {
7267 sc->devinfo.mf_info.mf_config[vn] =
7268 MFCFG_RD(sc, func_mf_config[abs_func].config);
7271 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] &
7272 FUNC_MF_CFG_FUNC_DISABLED) {
7273 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n");
7274 sc->flags |= BXE_MF_FUNC_DIS;
7276 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n");
7277 sc->flags &= ~BXE_MF_FUNC_DIS;
7281 /* acquire split MCP access lock register */
7282 static int bxe_acquire_alr(struct bxe_softc *sc)
7286 for (j = 0; j < 1000; j++) {
7288 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
7289 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
7290 if (val & (1L << 31))
7296 if (!(val & (1L << 31))) {
7297 BLOGE(sc, "Cannot acquire MCP access lock register\n");
7304 /* release split MCP access lock register */
7305 static void bxe_release_alr(struct bxe_softc *sc)
7307 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
7311 bxe_fan_failure(struct bxe_softc *sc)
7313 int port = SC_PORT(sc);
7314 uint32_t ext_phy_config;
7316 /* mark the failure */
7318 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
7320 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
7321 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
7322 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
7325 /* log the failure */
7326 BLOGW(sc, "Fan Failure has caused the driver to shutdown "
7327 "the card to prevent permanent damage. "
7328 "Please contact OEM Support for assistance\n");
7332 bxe_panic(sc, ("Schedule task to handle fan failure\n"));
7335 * Schedule device reset (unload)
7336 * This is due to some boards consuming sufficient power when driver is
7337 * up to overheat if fan fails.
7339 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state);
7340 schedule_delayed_work(&sc->sp_rtnl_task, 0);
7344 /* this function is called upon a link interrupt */
7346 bxe_link_attn(struct bxe_softc *sc)
7348 uint32_t pause_enabled = 0;
7349 struct host_port_stats *pstats;
7352 /* Make sure that we are synced with the current statistics */
7353 bxe_stats_handle(sc, STATS_EVENT_STOP);
7355 elink_link_update(&sc->link_params, &sc->link_vars);
7357 if (sc->link_vars.link_up) {
7359 /* dropless flow control */
7360 if (!CHIP_IS_E1(sc) && sc->dropless_fc) {
7363 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
7368 (BAR_USTRORM_INTMEM +
7369 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
7373 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) {
7374 pstats = BXE_SP(sc, port_stats);
7375 /* reset old mac stats */
7376 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx));
7379 if (sc->state == BXE_STATE_OPEN) {
7380 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
7384 if (sc->link_vars.link_up && sc->link_vars.line_speed) {
7385 cmng_fns = bxe_get_cmng_fns_mode(sc);
7387 if (cmng_fns != CMNG_FNS_NONE) {
7388 bxe_cmng_fns_init(sc, FALSE, cmng_fns);
7389 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7391 /* rate shaping and fairness are disabled */
7392 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n");
7396 bxe_link_report_locked(sc);
7399 ; // XXX bxe_link_sync_notify(sc);
7404 bxe_attn_int_asserted(struct bxe_softc *sc,
7407 int port = SC_PORT(sc);
7408 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7409 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7410 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
7411 NIG_REG_MASK_INTERRUPT_PORT0;
7413 uint32_t nig_mask = 0;
7418 if (sc->attn_state & asserted) {
7419 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted);
7422 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7424 aeu_mask = REG_RD(sc, aeu_addr);
7426 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n",
7427 aeu_mask, asserted);
7429 aeu_mask &= ~(asserted & 0x3ff);
7431 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
7433 REG_WR(sc, aeu_addr, aeu_mask);
7435 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7437 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
7438 sc->attn_state |= asserted;
7439 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
7441 if (asserted & ATTN_HARD_WIRED_MASK) {
7442 if (asserted & ATTN_NIG_FOR_FUNC) {
7446 /* save nig interrupt mask */
7447 nig_mask = REG_RD(sc, nig_int_mask_addr);
7449 /* If nig_mask is not set, no need to call the update function */
7451 REG_WR(sc, nig_int_mask_addr, 0);
7456 /* handle unicore attn? */
7459 if (asserted & ATTN_SW_TIMER_4_FUNC) {
7460 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n");
7463 if (asserted & GPIO_2_FUNC) {
7464 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n");
7467 if (asserted & GPIO_3_FUNC) {
7468 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n");
7471 if (asserted & GPIO_4_FUNC) {
7472 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n");
7476 if (asserted & ATTN_GENERAL_ATTN_1) {
7477 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n");
7478 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
7480 if (asserted & ATTN_GENERAL_ATTN_2) {
7481 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n");
7482 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
7484 if (asserted & ATTN_GENERAL_ATTN_3) {
7485 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n");
7486 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
7489 if (asserted & ATTN_GENERAL_ATTN_4) {
7490 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n");
7491 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
7493 if (asserted & ATTN_GENERAL_ATTN_5) {
7494 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n");
7495 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
7497 if (asserted & ATTN_GENERAL_ATTN_6) {
7498 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n");
7499 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
7504 if (sc->devinfo.int_block == INT_BLOCK_HC) {
7505 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET);
7507 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
7510 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n",
7512 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
7513 REG_WR(sc, reg_addr, asserted);
7515 /* now set back the mask */
7516 if (asserted & ATTN_NIG_FOR_FUNC) {
7518 * Verify that IGU ack through BAR was written before restoring
7519 * NIG mask. This loop should exit after 2-3 iterations max.
7521 if (sc->devinfo.int_block != INT_BLOCK_HC) {
7525 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);
7526 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
7527 (++cnt < MAX_IGU_ATTN_ACK_TO));
7530 BLOGE(sc, "Failed to verify IGU ack on time\n");
7536 REG_WR(sc, nig_int_mask_addr, nig_mask);
7543 bxe_print_next_block(struct bxe_softc *sc,
7547 BLOGI(sc, "%s%s", idx ? ", " : "", blk);
7551 bxe_check_blocks_with_parity0(struct bxe_softc *sc,
7556 uint32_t cur_bit = 0;
7559 for (i = 0; sig; i++) {
7560 cur_bit = ((uint32_t)0x1 << i);
7561 if (sig & cur_bit) {
7563 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
7565 bxe_print_next_block(sc, par_num++, "BRB");
7567 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
7569 bxe_print_next_block(sc, par_num++, "PARSER");
7571 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
7573 bxe_print_next_block(sc, par_num++, "TSDM");
7575 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
7577 bxe_print_next_block(sc, par_num++, "SEARCHER");
7579 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
7581 bxe_print_next_block(sc, par_num++, "TCM");
7583 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
7585 bxe_print_next_block(sc, par_num++, "TSEMI");
7587 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
7589 bxe_print_next_block(sc, par_num++, "XPB");
7602 bxe_check_blocks_with_parity1(struct bxe_softc *sc,
7609 uint32_t cur_bit = 0;
7610 for (i = 0; sig; i++) {
7611 cur_bit = ((uint32_t)0x1 << i);
7612 if (sig & cur_bit) {
7614 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
7616 bxe_print_next_block(sc, par_num++, "PBF");
7618 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
7620 bxe_print_next_block(sc, par_num++, "QM");
7622 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
7624 bxe_print_next_block(sc, par_num++, "TM");
7626 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
7628 bxe_print_next_block(sc, par_num++, "XSDM");
7630 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
7632 bxe_print_next_block(sc, par_num++, "XCM");
7634 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
7636 bxe_print_next_block(sc, par_num++, "XSEMI");
7638 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
7640 bxe_print_next_block(sc, par_num++, "DOORBELLQ");
7642 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
7644 bxe_print_next_block(sc, par_num++, "NIG");
7646 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
7648 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE");
7651 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
7653 bxe_print_next_block(sc, par_num++, "DEBUG");
7655 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
7657 bxe_print_next_block(sc, par_num++, "USDM");
7659 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
7661 bxe_print_next_block(sc, par_num++, "UCM");
7663 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
7665 bxe_print_next_block(sc, par_num++, "USEMI");
7667 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
7669 bxe_print_next_block(sc, par_num++, "UPB");
7671 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
7673 bxe_print_next_block(sc, par_num++, "CSDM");
7675 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
7677 bxe_print_next_block(sc, par_num++, "CCM");
7690 bxe_check_blocks_with_parity2(struct bxe_softc *sc,
7695 uint32_t cur_bit = 0;
7698 for (i = 0; sig; i++) {
7699 cur_bit = ((uint32_t)0x1 << i);
7700 if (sig & cur_bit) {
7702 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
7704 bxe_print_next_block(sc, par_num++, "CSEMI");
7706 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
7708 bxe_print_next_block(sc, par_num++, "PXP");
7710 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
7712 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT");
7714 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
7716 bxe_print_next_block(sc, par_num++, "CFC");
7718 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
7720 bxe_print_next_block(sc, par_num++, "CDU");
7722 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
7724 bxe_print_next_block(sc, par_num++, "DMAE");
7726 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
7728 bxe_print_next_block(sc, par_num++, "IGU");
7730 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
7732 bxe_print_next_block(sc, par_num++, "MISC");
7745 bxe_check_blocks_with_parity3(struct bxe_softc *sc,
7751 uint32_t cur_bit = 0;
7754 for (i = 0; sig; i++) {
7755 cur_bit = ((uint32_t)0x1 << i);
7756 if (sig & cur_bit) {
7758 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
7760 bxe_print_next_block(sc, par_num++, "MCP ROM");
7763 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
7765 bxe_print_next_block(sc, par_num++,
7769 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
7771 bxe_print_next_block(sc, par_num++,
7775 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
7777 bxe_print_next_block(sc, par_num++,
7792 bxe_check_blocks_with_parity4(struct bxe_softc *sc,
7797 uint32_t cur_bit = 0;
7800 for (i = 0; sig; i++) {
7801 cur_bit = ((uint32_t)0x1 << i);
7802 if (sig & cur_bit) {
7804 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
7806 bxe_print_next_block(sc, par_num++, "PGLUE_B");
7808 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
7810 bxe_print_next_block(sc, par_num++, "ATC");
7823 bxe_parity_attn(struct bxe_softc *sc,
7830 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
7831 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
7832 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
7833 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
7834 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
7835 BLOGE(sc, "Parity error: HW block parity attention:\n"
7836 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
7837 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0),
7838 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1),
7839 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2),
7840 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3),
7841 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4));
7844 BLOGI(sc, "Parity errors detected in blocks: ");
7847 bxe_check_blocks_with_parity0(sc, sig[0] &
7848 HW_PRTY_ASSERT_SET_0,
7851 bxe_check_blocks_with_parity1(sc, sig[1] &
7852 HW_PRTY_ASSERT_SET_1,
7853 par_num, global, print);
7855 bxe_check_blocks_with_parity2(sc, sig[2] &
7856 HW_PRTY_ASSERT_SET_2,
7859 bxe_check_blocks_with_parity3(sc, sig[3] &
7860 HW_PRTY_ASSERT_SET_3,
7861 par_num, global, print);
7863 bxe_check_blocks_with_parity4(sc, sig[4] &
7864 HW_PRTY_ASSERT_SET_4,
7877 bxe_chk_parity_attn(struct bxe_softc *sc,
7881 struct attn_route attn = { {0} };
7882 int port = SC_PORT(sc);
7884 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
7885 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
7886 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
7887 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
7889 if (!CHIP_IS_E1x(sc))
7890 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
7892 return (bxe_parity_attn(sc, global, print, attn.sig));
7896 bxe_attn_int_deasserted4(struct bxe_softc *sc,
7901 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
7902 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
7903 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val);
7904 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
7905 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
7906 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
7907 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
7908 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
7909 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
7910 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
7911 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
7912 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
7913 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
7914 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
7915 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
7916 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
7917 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
7918 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
7919 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
7920 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
7921 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
7924 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
7925 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);
7926 BLOGE(sc, "ATC hw attention 0x%08x\n", val);
7927 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
7928 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
7929 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
7930 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
7931 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
7932 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
7933 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
7934 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
7935 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
7936 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
7937 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
7938 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
7941 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7942 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
7943 BLOGE(sc, "FATAL parity attention set4 0x%08x\n",
7944 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
7945 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
7950 bxe_e1h_disable(struct bxe_softc *sc)
7952 int port = SC_PORT(sc);
7956 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7960 bxe_e1h_enable(struct bxe_softc *sc)
7962 int port = SC_PORT(sc);
7964 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7966 // XXX bxe_tx_enable(sc);
7970 * called due to MCP event (on pmf):
7971 * reread new bandwidth configuration
7973 * notify others function about the change
7976 bxe_config_mf_bw(struct bxe_softc *sc)
7978 if (sc->link_vars.link_up) {
7979 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX);
7980 // XXX bxe_link_sync_notify(sc);
7983 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
7987 bxe_set_mf_bw(struct bxe_softc *sc)
7989 bxe_config_mf_bw(sc);
7990 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
7994 bxe_handle_eee_event(struct bxe_softc *sc)
7996 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n");
7997 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
8000 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
8003 bxe_drv_info_ether_stat(struct bxe_softc *sc)
8005 struct eth_stats_info *ether_stat =
8006 &sc->sp->drv_info_to_mcp.ether_stat;
8008 strlcpy(ether_stat->version, BXE_DRIVER_VERSION,
8009 ETH_STAT_INFO_VERSION_LEN);
8011 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */
8012 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj,
8013 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
8014 ether_stat->mac_local + MAC_PAD,
8017 ether_stat->mtu_size = sc->mtu;
8019 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
8020 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
8021 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
8024 // XXX ether_stat->feature_flags |= ???;
8026 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0;
8028 ether_stat->txq_size = sc->tx_ring_size;
8029 ether_stat->rxq_size = sc->rx_ring_size;
8033 bxe_handle_drv_info_req(struct bxe_softc *sc)
8035 enum drv_info_opcode op_code;
8036 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control);
8038 /* if drv_info version supported by MFW doesn't match - send NACK */
8039 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
8040 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
8044 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
8045 DRV_INFO_CONTROL_OP_CODE_SHIFT);
8047 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp));
8050 case ETH_STATS_OPCODE:
8051 bxe_drv_info_ether_stat(sc);
8053 case FCOE_STATS_OPCODE:
8054 case ISCSI_STATS_OPCODE:
8056 /* if op code isn't supported - send NACK */
8057 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0);
8062 * If we got drv_info attn from MFW then these fields are defined in
8065 SHMEM2_WR(sc, drv_info_host_addr_lo,
8066 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
8067 SHMEM2_WR(sc, drv_info_host_addr_hi,
8068 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp)));
8070 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0);
8074 bxe_dcc_event(struct bxe_softc *sc,
8077 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event);
8079 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
8081 * This is the only place besides the function initialization
8082 * where the sc->flags can change so it is done without any
8085 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
8086 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n");
8087 sc->flags |= BXE_MF_FUNC_DIS;
8088 bxe_e1h_disable(sc);
8090 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n");
8091 sc->flags &= ~BXE_MF_FUNC_DIS;
8094 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
8097 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
8098 bxe_config_mf_bw(sc);
8099 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
8102 /* Report results to MCP */
8104 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0);
8106 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0);
8110 bxe_pmf_update(struct bxe_softc *sc)
8112 int port = SC_PORT(sc);
8116 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf);
8119 * We need the mb() to ensure the ordering between the writing to
8120 * sc->port.pmf here and reading it from the bxe_periodic_task().
8124 /* queue a periodic task */
8125 // XXX schedule task...
8127 // XXX bxe_dcbx_pmf_update(sc);
8129 /* enable nig attention */
8130 val = (0xff0f | (1 << (SC_VN(sc) + 4)));
8131 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8132 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val);
8133 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val);
8134 } else if (!CHIP_IS_E1x(sc)) {
8135 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
8136 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
8139 bxe_stats_handle(sc, STATS_EVENT_PMF);
8143 bxe_mc_assert(struct bxe_softc *sc)
8147 uint32_t row0, row1, row2, row3;
8150 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET);
8152 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8154 /* print the asserts */
8155 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8157 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));
8158 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);
8159 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);
8160 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);
8162 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8163 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8164 i, row3, row2, row1, row0);
8172 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET);
8174 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8177 /* print the asserts */
8178 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8180 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));
8181 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);
8182 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);
8183 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);
8185 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8186 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8187 i, row3, row2, row1, row0);
8195 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET);
8197 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8200 /* print the asserts */
8201 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8203 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));
8204 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);
8205 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);
8206 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);
8208 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8209 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8210 i, row3, row2, row1, row0);
8218 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET);
8220 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
8223 /* print the asserts */
8224 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
8226 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));
8227 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);
8228 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);
8229 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);
8231 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
8232 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
8233 i, row3, row2, row1, row0);
8244 bxe_attn_int_deasserted3(struct bxe_softc *sc,
8247 int func = SC_FUNC(sc);
8250 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
8252 if (attn & BXE_PMF_LINK_ASSERT(sc)) {
8254 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8255 bxe_read_mf_cfg(sc);
8256 sc->devinfo.mf_info.mf_config[SC_VN(sc)] =
8257 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
8258 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status);
8260 if (val & DRV_STATUS_DCC_EVENT_MASK)
8261 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK));
8263 if (val & DRV_STATUS_SET_MF_BW)
8266 if (val & DRV_STATUS_DRV_INFO_REQ)
8267 bxe_handle_drv_info_req(sc);
8270 if (val & DRV_STATUS_VF_DISABLED)
8271 bxe_vf_handle_flr_event(sc);
8274 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
8279 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
8280 (sc->dcbx_enabled > 0))
8281 /* start dcbx state machine */
8282 bxe_dcbx_set_params(sc, BXE_DCBX_STATE_NEG_RECEIVED);
8286 if (val & DRV_STATUS_AFEX_EVENT_MASK)
8287 bxe_handle_afex_cmd(sc, val & DRV_STATUS_AFEX_EVENT_MASK);
8290 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
8291 bxe_handle_eee_event(sc);
8293 if (sc->link_vars.periodic_flags &
8294 ELINK_PERIODIC_FLAGS_LINK_EVENT) {
8295 /* sync with link */
8297 sc->link_vars.periodic_flags &=
8298 ~ELINK_PERIODIC_FLAGS_LINK_EVENT;
8301 ; // XXX bxe_link_sync_notify(sc);
8302 bxe_link_report(sc);
8306 * Always call it here: bxe_link_report() will
8307 * prevent the link indication duplication.
8309 bxe_link_status_update(sc);
8311 } else if (attn & BXE_MC_ASSERT_BITS) {
8313 BLOGE(sc, "MC assert!\n");
8315 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
8316 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
8317 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
8318 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
8319 bxe_panic(sc, ("MC assert!\n"));
8321 } else if (attn & BXE_MCP_ASSERT) {
8323 BLOGE(sc, "MCP assert!\n");
8324 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
8325 // XXX bxe_fw_dump(sc);
8328 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn);
8332 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
8333 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn);
8334 if (attn & BXE_GRC_TIMEOUT) {
8335 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);
8336 BLOGE(sc, "GRC time-out 0x%08x\n", val);
8338 if (attn & BXE_GRC_RSV) {
8339 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);
8340 BLOGE(sc, "GRC reserved 0x%08x\n", val);
8342 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
8347 bxe_attn_int_deasserted2(struct bxe_softc *sc,
8350 int port = SC_PORT(sc);
8352 uint32_t val0, mask0, val1, mask1;
8355 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
8356 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
8357 BLOGE(sc, "CFC hw attention 0x%08x\n", val);
8358 /* CFC error attention */
8360 BLOGE(sc, "FATAL error from CFC\n");
8364 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
8365 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
8366 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val);
8367 /* RQ_USDMDP_FIFO_OVERFLOW */
8368 if (val & 0x18000) {
8369 BLOGE(sc, "FATAL error from PXP\n");
8372 if (!CHIP_IS_E1x(sc)) {
8373 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);
8374 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val);
8378 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR
8379 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT
8381 if (attn & AEU_PXP2_HW_INT_BIT) {
8382 /* CQ47854 workaround do not panic on
8383 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8385 if (!CHIP_IS_E1x(sc)) {
8386 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);
8387 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);
8388 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);
8389 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);
8391 * If the olny PXP2_EOP_ERROR_BIT is set in
8392 * STS0 and STS1 - clear it
8394 * probably we lose additional attentions between
8395 * STS0 and STS_CLR0, in this case user will not
8396 * be notified about them
8398 if (val0 & mask0 & PXP2_EOP_ERROR_BIT &&
8400 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
8402 /* print the register, since no one can restore it */
8403 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0);
8406 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR
8409 if (val0 & PXP2_EOP_ERROR_BIT) {
8410 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n");
8413 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is
8414 * set then clear attention from PXP2 block without panic
8416 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) &&
8417 ((val1 & mask1) == 0))
8418 attn &= ~AEU_PXP2_HW_INT_BIT;
8423 if (attn & HW_INTERRUT_ASSERT_SET_2) {
8424 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
8425 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
8427 val = REG_RD(sc, reg_offset);
8428 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
8429 REG_WR(sc, reg_offset, val);
8431 BLOGE(sc, "FATAL HW block attention set2 0x%x\n",
8432 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2));
8433 bxe_panic(sc, ("HW block attention set2\n"));
8438 bxe_attn_int_deasserted1(struct bxe_softc *sc,
8441 int port = SC_PORT(sc);
8445 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
8446 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
8447 BLOGE(sc, "DB hw attention 0x%08x\n", val);
8448 /* DORQ discard attention */
8450 BLOGE(sc, "FATAL error from DORQ\n");
8454 if (attn & HW_INTERRUT_ASSERT_SET_1) {
8455 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
8456 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
8458 val = REG_RD(sc, reg_offset);
8459 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
8460 REG_WR(sc, reg_offset, val);
8462 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n",
8463 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1));
8464 bxe_panic(sc, ("HW block attention set1\n"));
8469 bxe_attn_int_deasserted0(struct bxe_softc *sc,
8472 int port = SC_PORT(sc);
8476 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
8477 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
8479 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
8480 val = REG_RD(sc, reg_offset);
8481 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
8482 REG_WR(sc, reg_offset, val);
8484 BLOGW(sc, "SPIO5 hw attention\n");
8486 /* Fan failure attention */
8487 elink_hw_reset_phy(&sc->link_params);
8488 bxe_fan_failure(sc);
8491 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) {
8493 elink_handle_module_detect_int(&sc->link_params);
8497 if (attn & HW_INTERRUT_ASSERT_SET_0) {
8498 val = REG_RD(sc, reg_offset);
8499 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
8500 REG_WR(sc, reg_offset, val);
8502 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n",
8503 (attn & HW_INTERRUT_ASSERT_SET_0)));
8508 bxe_attn_int_deasserted(struct bxe_softc *sc,
8509 uint32_t deasserted)
8511 struct attn_route attn;
8512 struct attn_route *group_mask;
8513 int port = SC_PORT(sc);
8518 uint8_t global = FALSE;
8521 * Need to take HW lock because MCP or other port might also
8522 * try to handle this event.
8524 bxe_acquire_alr(sc);
8526 if (bxe_chk_parity_attn(sc, &global, TRUE)) {
8528 * In case of parity errors don't handle attentions so that
8529 * other function would "see" parity errors.
8531 sc->recovery_state = BXE_RECOVERY_INIT;
8532 // XXX schedule a recovery task...
8533 /* disable HW interrupts */
8534 bxe_int_disable(sc);
8535 bxe_release_alr(sc);
8539 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
8540 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
8541 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
8542 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
8543 if (!CHIP_IS_E1x(sc)) {
8544 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
8549 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
8550 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
8552 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
8553 if (deasserted & (1 << index)) {
8554 group_mask = &sc->attn_group[index];
8557 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index,
8558 group_mask->sig[0], group_mask->sig[1],
8559 group_mask->sig[2], group_mask->sig[3],
8560 group_mask->sig[4]);
8562 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]);
8563 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]);
8564 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]);
8565 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]);
8566 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]);
8570 bxe_release_alr(sc);
8572 if (sc->devinfo.int_block == INT_BLOCK_HC) {
8573 reg_addr = (HC_REG_COMMAND_REG + port*32 +
8574 COMMAND_REG_ATTN_BITS_CLR);
8576 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
8581 "about to mask 0x%08x at %s addr 0x%08x\n", val,
8582 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
8583 REG_WR(sc, reg_addr, val);
8585 if (~sc->attn_state & deasserted) {
8586 BLOGE(sc, "IGU error\n");
8589 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8590 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8592 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8594 aeu_mask = REG_RD(sc, reg_addr);
8596 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n",
8597 aeu_mask, deasserted);
8598 aeu_mask |= (deasserted & 0x3ff);
8599 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask);
8601 REG_WR(sc, reg_addr, aeu_mask);
8602 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
8604 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state);
8605 sc->attn_state &= ~deasserted;
8606 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state);
8610 bxe_attn_int(struct bxe_softc *sc)
8612 /* read local copy of bits */
8613 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
8614 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
8615 uint32_t attn_state = sc->attn_state;
8617 /* look for changed bits */
8618 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state;
8619 uint32_t deasserted = ~attn_bits & attn_ack & attn_state;
8622 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n",
8623 attn_bits, attn_ack, asserted, deasserted);
8625 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) {
8626 BLOGE(sc, "BAD attention state\n");
8629 /* handle bits that were raised */
8631 bxe_attn_int_asserted(sc, asserted);
8635 bxe_attn_int_deasserted(sc, deasserted);
8640 bxe_update_dsb_idx(struct bxe_softc *sc)
8642 struct host_sp_status_block *def_sb = sc->def_sb;
8645 mb(); /* status block is written to by the chip */
8647 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
8648 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index;
8649 rc |= BXE_DEF_SB_ATT_IDX;
8652 if (sc->def_idx != def_sb->sp_sb.running_index) {
8653 sc->def_idx = def_sb->sp_sb.running_index;
8654 rc |= BXE_DEF_SB_IDX;
8662 static inline struct ecore_queue_sp_obj *
8663 bxe_cid_to_q_obj(struct bxe_softc *sc,
8666 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid);
8667 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj);
8671 bxe_handle_mcast_eqe(struct bxe_softc *sc)
8673 struct ecore_mcast_ramrod_params rparam;
8676 memset(&rparam, 0, sizeof(rparam));
8678 rparam.mcast_obj = &sc->mcast_obj;
8682 /* clear pending state for the last command */
8683 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw);
8685 /* if there are pending mcast commands - send them */
8686 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) {
8687 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT);
8690 "ERROR: Failed to send pending mcast commands (%d)\n",
8695 BXE_MCAST_UNLOCK(sc);
8699 bxe_handle_classification_eqe(struct bxe_softc *sc,
8700 union event_ring_elem *elem)
8702 unsigned long ramrod_flags = 0;
8704 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8705 struct ecore_vlan_mac_obj *vlan_mac_obj;
8707 /* always push next commands out, don't wait here */
8708 bit_set(&ramrod_flags, RAMROD_CONT);
8710 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) {
8711 case ECORE_FILTER_MAC_PENDING:
8712 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n");
8713 vlan_mac_obj = &sc->sp_objs[cid].mac_obj;
8716 case ECORE_FILTER_MCAST_PENDING:
8717 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n");
8719 * This is only relevant for 57710 where multicast MACs are
8720 * configured as unicast MACs using the same ramrod.
8722 bxe_handle_mcast_eqe(sc);
8726 BLOGE(sc, "Unsupported classification command: %d\n",
8727 elem->message.data.eth_event.echo);
8731 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags);
8734 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc);
8735 } else if (rc > 0) {
8736 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n");
8741 bxe_handle_rx_mode_eqe(struct bxe_softc *sc,
8742 union event_ring_elem *elem)
8744 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);
8746 /* send rx_mode command again if was requested */
8747 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED,
8749 bxe_set_storm_rx_mode(sc);
8752 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_START_SCHED,
8754 bxe_set_iscsi_eth_rx_mode(sc, TRUE);
8756 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_STOP_SCHED,
8758 bxe_set_iscsi_eth_rx_mode(sc, FALSE);
8764 bxe_update_eq_prod(struct bxe_softc *sc,
8767 storm_memset_eq_prod(sc, prod, SC_FUNC(sc));
8768 wmb(); /* keep prod updates ordered */
8772 bxe_eq_int(struct bxe_softc *sc)
8774 uint16_t hw_cons, sw_cons, sw_prod;
8775 union event_ring_elem *elem;
8780 struct ecore_queue_sp_obj *q_obj;
8781 struct ecore_func_sp_obj *f_obj = &sc->func_obj;
8782 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw;
8784 hw_cons = le16toh(*sc->eq_cons_sb);
8787 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256.
8788 * when we get to the next-page we need to adjust so the loop
8789 * condition below will be met. The next element is the size of a
8790 * regular element and hence incrementing by 1
8792 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) {
8797 * This function may never run in parallel with itself for a
8798 * specific sc and no need for a read memory barrier here.
8800 sw_cons = sc->eq_cons;
8801 sw_prod = sc->eq_prod;
8803 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n",
8804 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left));
8808 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
8810 elem = &sc->eq[EQ_DESC(sw_cons)];
8814 rc = bxe_iov_eq_sp_event(sc, elem);
8816 BLOGE(sc, "bxe_iov_eq_sp_event returned %d\n", rc);
8821 /* elem CID originates from FW, actually LE */
8822 cid = SW_CID(elem->message.data.cfc_del_event.cid);
8823 opcode = elem->message.opcode;
8825 /* handle eq element */
8828 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
8829 BLOGD(sc, DBG_SP, "vf/pf channel element on eq\n");
8830 bxe_vf_mbx(sc, &elem->message.data.vf_pf_event);
8834 case EVENT_RING_OPCODE_STAT_QUERY:
8835 BLOGD(sc, DBG_SP, "got statistics completion event %d\n",
8837 /* nothing to do with stats comp */
8840 case EVENT_RING_OPCODE_CFC_DEL:
8841 /* handle according to cid range */
8842 /* we may want to verify here that the sc state is HALTING */
8843 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid);
8844 q_obj = bxe_cid_to_q_obj(sc, cid);
8845 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) {
8850 case EVENT_RING_OPCODE_STOP_TRAFFIC:
8851 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n");
8852 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) {
8855 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED);
8858 case EVENT_RING_OPCODE_START_TRAFFIC:
8859 BLOGD(sc, DBG_SP, "got START TRAFFIC\n");
8860 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) {
8863 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED);
8866 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
8867 echo = elem->message.data.function_update_event.echo;
8868 if (echo == SWITCH_UPDATE) {
8869 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n");
8870 if (f_obj->complete_cmd(sc, f_obj,
8871 ECORE_F_CMD_SWITCH_UPDATE)) {
8877 "AFEX: ramrod completed FUNCTION_UPDATE\n");
8879 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_UPDATE);
8881 * We will perform the queues update from the sp_core_task as
8882 * all queue SP operations should run with CORE_LOCK.
8884 bxe_set_bit(BXE_SP_CORE_AFEX_F_UPDATE, &sc->sp_core_state);
8885 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task);
8891 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
8892 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_VIFLISTS);
8893 bxe_after_afex_vif_lists(sc, elem);
8897 case EVENT_RING_OPCODE_FORWARD_SETUP:
8898 q_obj = &bxe_fwd_sp_obj(sc, q_obj);
8899 if (q_obj->complete_cmd(sc, q_obj,
8900 ECORE_Q_CMD_SETUP_TX_ONLY)) {
8905 case EVENT_RING_OPCODE_FUNCTION_START:
8906 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n");
8907 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) {
8912 case EVENT_RING_OPCODE_FUNCTION_STOP:
8913 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n");
8914 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) {
8920 switch (opcode | sc->state) {
8921 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN):
8922 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT):
8923 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK;
8924 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid);
8925 rss_raw->clear_pending(rss_raw);
8928 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN):
8929 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG):
8930 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT):
8931 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN):
8932 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG):
8933 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8934 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n");
8935 bxe_handle_classification_eqe(sc, elem);
8938 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN):
8939 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG):
8940 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8941 BLOGD(sc, DBG_SP, "got mcast ramrod\n");
8942 bxe_handle_mcast_eqe(sc);
8945 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN):
8946 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG):
8947 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT):
8948 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n");
8949 bxe_handle_rx_mode_eqe(sc, elem);
8953 /* unknown event log error and continue */
8954 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n",
8955 elem->message.opcode, sc->state);
8963 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt);
8965 sc->eq_cons = sw_cons;
8966 sc->eq_prod = sw_prod;
8968 /* make sure that above mem writes were issued towards the memory */
8971 /* update producer */
8972 bxe_update_eq_prod(sc, sc->eq_prod);
8976 bxe_handle_sp_tq(void *context,
8979 struct bxe_softc *sc = (struct bxe_softc *)context;
8982 BLOGD(sc, DBG_SP, "---> SP TASK <---\n");
8984 /* what work needs to be performed? */
8985 status = bxe_update_dsb_idx(sc);
8987 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status);
8990 if (status & BXE_DEF_SB_ATT_IDX) {
8991 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n");
8993 status &= ~BXE_DEF_SB_ATT_IDX;
8996 /* SP events: STAT_QUERY and others */
8997 if (status & BXE_DEF_SB_IDX) {
8998 /* handle EQ completions */
8999 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n");
9001 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID,
9002 le16toh(sc->def_idx), IGU_INT_NOP, 1);
9003 status &= ~BXE_DEF_SB_IDX;
9006 /* if status is non zero then something went wrong */
9007 if (__predict_false(status)) {
9008 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status);
9011 /* ack status block only if something was actually handled */
9012 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID,
9013 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1);
9016 * Must be called after the EQ processing (since eq leads to sriov
9017 * ramrod completion flows).
9018 * This flow may have been scheduled by the arrival of a ramrod
9019 * completion, or by the sriov code rescheduling itself.
9021 // XXX bxe_iov_sp_task(sc);
9024 /* AFEX - poll to check if VIFSET_ACK should be sent to MFW */
9025 if (bxe_test_and_clear_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK,
9027 bxe_link_report(sc);
9028 bxe_fw_command(sc, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
9034 bxe_handle_fp_tq(void *context,
9037 struct bxe_fastpath *fp = (struct bxe_fastpath *)context;
9038 struct bxe_softc *sc = fp->sc;
9039 uint8_t more_tx = FALSE;
9040 uint8_t more_rx = FALSE;
9042 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index);
9045 * IFF_DRV_RUNNING state can't be checked here since we process
9046 * slowpath events on a client queue during setup. Instead
9047 * we need to add a "process/continue" flag here that the driver
9048 * can use to tell the task here not to do anything.
9051 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) {
9056 /* update the fastpath index */
9057 bxe_update_fp_sb_idx(fp);
9059 /* XXX add loop here if ever support multiple tx CoS */
9060 /* fp->txdata[cos] */
9061 if (bxe_has_tx_work(fp)) {
9063 more_tx = bxe_txeof(sc, fp);
9064 BXE_FP_TX_UNLOCK(fp);
9067 if (bxe_has_rx_work(fp)) {
9068 more_rx = bxe_rxeof(sc, fp);
9071 if (more_rx /*|| more_tx*/) {
9072 /* still more work to do */
9073 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
9077 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
9078 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
9082 bxe_task_fp(struct bxe_fastpath *fp)
9084 struct bxe_softc *sc = fp->sc;
9085 uint8_t more_tx = FALSE;
9086 uint8_t more_rx = FALSE;
9088 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index);
9090 /* update the fastpath index */
9091 bxe_update_fp_sb_idx(fp);
9093 /* XXX add loop here if ever support multiple tx CoS */
9094 /* fp->txdata[cos] */
9095 if (bxe_has_tx_work(fp)) {
9097 more_tx = bxe_txeof(sc, fp);
9098 BXE_FP_TX_UNLOCK(fp);
9101 if (bxe_has_rx_work(fp)) {
9102 more_rx = bxe_rxeof(sc, fp);
9105 if (more_rx /*|| more_tx*/) {
9106 /* still more work to do, bail out if this ISR and process later */
9107 taskqueue_enqueue_fast(fp->tq, &fp->tq_task);
9112 * Here we write the fastpath index taken before doing any tx or rx work.
9113 * It is very well possible other hw events occurred up to this point and
9114 * they were actually processed accordingly above. Since we're going to
9115 * write an older fastpath index, an interrupt is coming which we might
9116 * not do any work in.
9118 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID,
9119 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1);
9123 * Legacy interrupt entry point.
9125 * Verifies that the controller generated the interrupt and
9126 * then calls a separate routine to handle the various
9127 * interrupt causes: link, RX, and TX.
9130 bxe_intr_legacy(void *xsc)
9132 struct bxe_softc *sc = (struct bxe_softc *)xsc;
9133 struct bxe_fastpath *fp;
9134 uint16_t status, mask;
9137 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n");
9140 /* Don't handle any interrupts if we're not ready. */
9141 if (__predict_false(sc->intr_sem != 0)) {
9147 * 0 for ustorm, 1 for cstorm
9148 * the bits returned from ack_int() are 0-15
9149 * bit 0 = attention status block
9150 * bit 1 = fast path status block
9151 * a mask of 0x2 or more = tx/rx event
9152 * a mask of 1 = slow path event
9155 status = bxe_ack_int(sc);
9157 /* the interrupt is not for us */
9158 if (__predict_false(status == 0)) {
9159 BLOGD(sc, DBG_INTR, "Not our interrupt!\n");
9163 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status);
9165 FOR_EACH_ETH_QUEUE(sc, i) {
9167 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc)));
9168 if (status & mask) {
9169 /* acknowledge and disable further fastpath interrupts */
9170 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9177 if (CNIC_SUPPORT(sc)) {
9179 if (status & (mask | 0x1)) {
9186 if (__predict_false(status & 0x1)) {
9187 /* acknowledge and disable further slowpath interrupts */
9188 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9190 /* schedule slowpath handler */
9191 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
9196 if (__predict_false(status)) {
9197 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status);
9201 /* slowpath interrupt entry point */
9203 bxe_intr_sp(void *xsc)
9205 struct bxe_softc *sc = (struct bxe_softc *)xsc;
9207 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n");
9209 /* acknowledge and disable further slowpath interrupts */
9210 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9212 /* schedule slowpath handler */
9213 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task);
9216 /* fastpath interrupt entry point */
9218 bxe_intr_fp(void *xfp)
9220 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp;
9221 struct bxe_softc *sc = fp->sc;
9223 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index);
9226 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n",
9227 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id);
9230 /* Don't handle any interrupts if we're not ready. */
9231 if (__predict_false(sc->intr_sem != 0)) {
9236 /* acknowledge and disable further fastpath interrupts */
9237 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9242 /* Release all interrupts allocated by the driver. */
9244 bxe_interrupt_free(struct bxe_softc *sc)
9248 switch (sc->interrupt_mode) {
9249 case INTR_MODE_INTX:
9250 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n");
9251 if (sc->intr[0].resource != NULL) {
9252 bus_release_resource(sc->dev,
9255 sc->intr[0].resource);
9259 for (i = 0; i < sc->intr_count; i++) {
9260 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i);
9261 if (sc->intr[i].resource && sc->intr[i].rid) {
9262 bus_release_resource(sc->dev,
9265 sc->intr[i].resource);
9268 pci_release_msi(sc->dev);
9270 case INTR_MODE_MSIX:
9271 for (i = 0; i < sc->intr_count; i++) {
9272 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i);
9273 if (sc->intr[i].resource && sc->intr[i].rid) {
9274 bus_release_resource(sc->dev,
9277 sc->intr[i].resource);
9280 pci_release_msi(sc->dev);
9283 /* nothing to do as initial allocation failed */
9289 * This function determines and allocates the appropriate
9290 * interrupt based on system capabilites and user request.
9292 * The user may force a particular interrupt mode, specify
9293 * the number of receive queues, specify the method for
9294 * distribuitng received frames to receive queues, or use
9295 * the default settings which will automatically select the
9296 * best supported combination. In addition, the OS may or
9297 * may not support certain combinations of these settings.
9298 * This routine attempts to reconcile the settings requested
9299 * by the user with the capabilites available from the system
9300 * to select the optimal combination of features.
9303 * 0 = Success, !0 = Failure.
9306 bxe_interrupt_alloc(struct bxe_softc *sc)
9310 int num_requested = 0;
9311 int num_allocated = 0;
9315 /* get the number of available MSI/MSI-X interrupts from the OS */
9316 if (sc->interrupt_mode > 0) {
9317 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) {
9318 msix_count = pci_msix_count(sc->dev);
9321 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) {
9322 msi_count = pci_msi_count(sc->dev);
9325 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n",
9326 msi_count, msix_count);
9329 do { /* try allocating MSI-X interrupt resources (at least 2) */
9330 if (sc->interrupt_mode != INTR_MODE_MSIX) {
9334 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) ||
9336 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9340 /* ask for the necessary number of MSI-X vectors */
9341 num_requested = min((sc->num_queues + 1), msix_count);
9343 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested);
9345 num_allocated = num_requested;
9346 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) {
9347 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc);
9348 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9352 if (num_allocated < 2) { /* possible? */
9353 BLOGE(sc, "MSI-X allocation less than 2!\n");
9354 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9355 pci_release_msi(sc->dev);
9359 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n",
9360 num_requested, num_allocated);
9362 /* best effort so use the number of vectors allocated to us */
9363 sc->intr_count = num_allocated;
9364 sc->num_queues = num_allocated - 1;
9366 rid = 1; /* initial resource identifier */
9368 /* allocate the MSI-X vectors */
9369 for (i = 0; i < num_allocated; i++) {
9370 sc->intr[i].rid = (rid + i);
9372 if ((sc->intr[i].resource =
9373 bus_alloc_resource_any(sc->dev,
9376 RF_ACTIVE)) == NULL) {
9377 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n",
9380 for (j = (i - 1); j >= 0; j--) {
9381 bus_release_resource(sc->dev,
9384 sc->intr[j].resource);
9389 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */
9390 pci_release_msi(sc->dev);
9394 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i));
9398 do { /* try allocating MSI vector resources (at least 2) */
9399 if (sc->interrupt_mode != INTR_MODE_MSI) {
9403 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) ||
9405 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9409 /* ask for a single MSI vector */
9412 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested);
9414 num_allocated = num_requested;
9415 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) {
9416 BLOGE(sc, "MSI alloc failed (%d)!\n", rc);
9417 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9421 if (num_allocated != 1) { /* possible? */
9422 BLOGE(sc, "MSI allocation is not 1!\n");
9423 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9424 pci_release_msi(sc->dev);
9428 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n",
9429 num_requested, num_allocated);
9431 /* best effort so use the number of vectors allocated to us */
9432 sc->intr_count = num_allocated;
9433 sc->num_queues = num_allocated;
9435 rid = 1; /* initial resource identifier */
9437 sc->intr[0].rid = rid;
9439 if ((sc->intr[0].resource =
9440 bus_alloc_resource_any(sc->dev,
9443 RF_ACTIVE)) == NULL) {
9444 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid);
9447 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */
9448 pci_release_msi(sc->dev);
9452 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid);
9455 do { /* try allocating INTx vector resources */
9456 if (sc->interrupt_mode != INTR_MODE_INTX) {
9460 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n");
9462 /* only one vector for INTx */
9466 rid = 0; /* initial resource identifier */
9468 sc->intr[0].rid = rid;
9470 if ((sc->intr[0].resource =
9471 bus_alloc_resource_any(sc->dev,
9474 (RF_ACTIVE | RF_SHAREABLE))) == NULL) {
9475 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid);
9478 sc->interrupt_mode = -1; /* Failed! */
9482 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid);
9485 if (sc->interrupt_mode == -1) {
9486 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n");
9490 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n",
9491 sc->interrupt_mode, sc->num_queues);
9499 bxe_interrupt_detach(struct bxe_softc *sc)
9501 struct bxe_fastpath *fp;
9504 /* release interrupt resources */
9505 for (i = 0; i < sc->intr_count; i++) {
9506 if (sc->intr[i].resource && sc->intr[i].tag) {
9507 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i);
9508 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag);
9512 for (i = 0; i < sc->num_queues; i++) {
9515 taskqueue_drain(fp->tq, &fp->tq_task);
9516 taskqueue_free(fp->tq);
9521 if (sc->rx_mode_tq) {
9522 taskqueue_drain(sc->rx_mode_tq, &sc->rx_mode_tq_task);
9523 taskqueue_free(sc->rx_mode_tq);
9524 sc->rx_mode_tq = NULL;
9528 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task);
9529 taskqueue_free(sc->sp_tq);
9535 * Enables interrupts and attach to the ISR.
9537 * When using multiple MSI/MSI-X vectors the first vector
9538 * is used for slowpath operations while all remaining
9539 * vectors are used for fastpath operations. If only a
9540 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
9541 * ISR must look for both slowpath and fastpath completions.
9544 bxe_interrupt_attach(struct bxe_softc *sc)
9546 struct bxe_fastpath *fp;
9550 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name),
9551 "bxe%d_sp_tq", sc->unit);
9552 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc);
9553 sc->sp_tq = taskqueue_create_fast(sc->sp_tq_name, M_NOWAIT,
9554 taskqueue_thread_enqueue,
9556 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */
9557 "%s", sc->sp_tq_name);
9559 snprintf(sc->rx_mode_tq_name, sizeof(sc->rx_mode_tq_name),
9560 "bxe%d_rx_mode_tq", sc->unit);
9561 TASK_INIT(&sc->rx_mode_tq_task, 0, bxe_handle_rx_mode_tq, sc);
9562 sc->rx_mode_tq = taskqueue_create_fast(sc->rx_mode_tq_name, M_NOWAIT,
9563 taskqueue_thread_enqueue,
9565 taskqueue_start_threads(&sc->rx_mode_tq, 1, PWAIT, /* lower priority */
9566 "%s", sc->rx_mode_tq_name);
9568 for (i = 0; i < sc->num_queues; i++) {
9570 snprintf(fp->tq_name, sizeof(fp->tq_name),
9571 "bxe%d_fp%d_tq", sc->unit, i);
9572 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp);
9573 fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT,
9574 taskqueue_thread_enqueue,
9576 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */
9580 /* setup interrupt handlers */
9581 if (sc->interrupt_mode == INTR_MODE_MSIX) {
9582 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n");
9585 * Setup the interrupt handler. Note that we pass the driver instance
9586 * to the interrupt handler for the slowpath.
9588 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9589 (INTR_TYPE_NET | INTR_MPSAFE),
9590 NULL, bxe_intr_sp, sc,
9591 &sc->intr[0].tag)) != 0) {
9592 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc);
9593 goto bxe_interrupt_attach_exit;
9596 bus_describe_intr(sc->dev, sc->intr[0].resource,
9597 sc->intr[0].tag, "sp");
9599 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */
9601 /* initialize the fastpath vectors (note the first was used for sp) */
9602 for (i = 0; i < sc->num_queues; i++) {
9604 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1));
9607 * Setup the interrupt handler. Note that we pass the
9608 * fastpath context to the interrupt handler in this
9611 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource,
9612 (INTR_TYPE_NET | INTR_MPSAFE),
9613 NULL, bxe_intr_fp, fp,
9614 &sc->intr[i + 1].tag)) != 0) {
9615 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n",
9617 goto bxe_interrupt_attach_exit;
9620 bus_describe_intr(sc->dev, sc->intr[i + 1].resource,
9621 sc->intr[i + 1].tag, "fp%02d", i);
9623 /* bind the fastpath instance to a cpu */
9624 if (sc->num_queues > 1) {
9625 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i);
9628 fp->state = BXE_FP_STATE_IRQ;
9630 } else if (sc->interrupt_mode == INTR_MODE_MSI) {
9631 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n");
9634 * Setup the interrupt handler. Note that we pass the
9635 * driver instance to the interrupt handler which
9636 * will handle both the slowpath and fastpath.
9638 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9639 (INTR_TYPE_NET | INTR_MPSAFE),
9640 NULL, bxe_intr_legacy, sc,
9641 &sc->intr[0].tag)) != 0) {
9642 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc);
9643 goto bxe_interrupt_attach_exit;
9646 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */
9647 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n");
9650 * Setup the interrupt handler. Note that we pass the
9651 * driver instance to the interrupt handler which
9652 * will handle both the slowpath and fastpath.
9654 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource,
9655 (INTR_TYPE_NET | INTR_MPSAFE),
9656 NULL, bxe_intr_legacy, sc,
9657 &sc->intr[0].tag)) != 0) {
9658 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc);
9659 goto bxe_interrupt_attach_exit;
9663 bxe_interrupt_attach_exit:
9668 static int bxe_init_hw_common_chip(struct bxe_softc *sc);
9669 static int bxe_init_hw_common(struct bxe_softc *sc);
9670 static int bxe_init_hw_port(struct bxe_softc *sc);
9671 static int bxe_init_hw_func(struct bxe_softc *sc);
9672 static void bxe_reset_common(struct bxe_softc *sc);
9673 static void bxe_reset_port(struct bxe_softc *sc);
9674 static void bxe_reset_func(struct bxe_softc *sc);
9675 static int bxe_gunzip_init(struct bxe_softc *sc);
9676 static void bxe_gunzip_end(struct bxe_softc *sc);
9677 static int bxe_init_firmware(struct bxe_softc *sc);
9678 static void bxe_release_firmware(struct bxe_softc *sc);
9681 ecore_func_sp_drv_ops bxe_func_sp_drv = {
9682 .init_hw_cmn_chip = bxe_init_hw_common_chip,
9683 .init_hw_cmn = bxe_init_hw_common,
9684 .init_hw_port = bxe_init_hw_port,
9685 .init_hw_func = bxe_init_hw_func,
9687 .reset_hw_cmn = bxe_reset_common,
9688 .reset_hw_port = bxe_reset_port,
9689 .reset_hw_func = bxe_reset_func,
9691 .gunzip_init = bxe_gunzip_init,
9692 .gunzip_end = bxe_gunzip_end,
9694 .init_fw = bxe_init_firmware,
9695 .release_fw = bxe_release_firmware,
9699 bxe_init_func_obj(struct bxe_softc *sc)
9703 ecore_init_func_obj(sc,
9705 BXE_SP(sc, func_rdata),
9706 BXE_SP_MAPPING(sc, func_rdata),
9707 BXE_SP(sc, func_afex_rdata),
9708 BXE_SP_MAPPING(sc, func_afex_rdata),
9713 bxe_init_hw(struct bxe_softc *sc,
9716 struct ecore_func_state_params func_params = { NULL };
9719 /* prepare the parameters for function state transitions */
9720 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
9722 func_params.f_obj = &sc->func_obj;
9723 func_params.cmd = ECORE_F_CMD_HW_INIT;
9725 func_params.params.hw_init.load_phase = load_code;
9728 * Via a plethora of function pointers, we will eventually reach
9729 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func().
9731 rc = ecore_func_state_change(sc, &func_params);
9737 bxe_fill(struct bxe_softc *sc,
9744 if (!(len % 4) && !(addr % 4)) {
9745 for (i = 0; i < len; i += 4) {
9746 REG_WR(sc, (addr + i), fill);
9749 for (i = 0; i < len; i++) {
9750 REG_WR8(sc, (addr + i), fill);
9755 /* writes FP SP data to FW - data_size in dwords */
9757 bxe_wr_fp_sb_data(struct bxe_softc *sc,
9759 uint32_t *sb_data_p,
9764 for (index = 0; index < data_size; index++) {
9766 (BAR_CSTRORM_INTMEM +
9767 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
9768 (sizeof(uint32_t) * index)),
9769 *(sb_data_p + index));
9774 bxe_zero_fp_sb(struct bxe_softc *sc,
9777 struct hc_status_block_data_e2 sb_data_e2;
9778 struct hc_status_block_data_e1x sb_data_e1x;
9779 uint32_t *sb_data_p;
9780 uint32_t data_size = 0;
9782 if (!CHIP_IS_E1x(sc)) {
9783 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9784 sb_data_e2.common.state = SB_DISABLED;
9785 sb_data_e2.common.p_func.vf_valid = FALSE;
9786 sb_data_p = (uint32_t *)&sb_data_e2;
9787 data_size = (sizeof(struct hc_status_block_data_e2) /
9790 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9791 sb_data_e1x.common.state = SB_DISABLED;
9792 sb_data_e1x.common.p_func.vf_valid = FALSE;
9793 sb_data_p = (uint32_t *)&sb_data_e1x;
9794 data_size = (sizeof(struct hc_status_block_data_e1x) /
9798 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9800 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)),
9801 0, CSTORM_STATUS_BLOCK_SIZE);
9802 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)),
9803 0, CSTORM_SYNC_BLOCK_SIZE);
9807 bxe_wr_sp_sb_data(struct bxe_softc *sc,
9808 struct hc_sp_status_block_data *sp_sb_data)
9813 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t));
9816 (BAR_CSTRORM_INTMEM +
9817 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) +
9818 (i * sizeof(uint32_t))),
9819 *((uint32_t *)sp_sb_data + i));
9824 bxe_zero_sp_sb(struct bxe_softc *sc)
9826 struct hc_sp_status_block_data sp_sb_data;
9828 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
9830 sp_sb_data.state = SB_DISABLED;
9831 sp_sb_data.p_func.vf_valid = FALSE;
9833 bxe_wr_sp_sb_data(sc, &sp_sb_data);
9836 (BAR_CSTRORM_INTMEM +
9837 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))),
9838 0, CSTORM_SP_STATUS_BLOCK_SIZE);
9840 (BAR_CSTRORM_INTMEM +
9841 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))),
9842 0, CSTORM_SP_SYNC_BLOCK_SIZE);
9846 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
9850 hc_sm->igu_sb_id = igu_sb_id;
9851 hc_sm->igu_seg_id = igu_seg_id;
9852 hc_sm->timer_value = 0xFF;
9853 hc_sm->time_to_expire = 0xFFFFFFFF;
9857 bxe_map_sb_state_machines(struct hc_index_data *index_data)
9859 /* zero out state machine indices */
9862 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9865 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
9866 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
9867 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
9868 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
9873 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
9874 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9877 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
9878 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9879 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
9880 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9881 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
9882 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9883 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
9884 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT);
9888 bxe_init_sb(struct bxe_softc *sc,
9895 struct hc_status_block_data_e2 sb_data_e2;
9896 struct hc_status_block_data_e1x sb_data_e1x;
9897 struct hc_status_block_sm *hc_sm_p;
9898 uint32_t *sb_data_p;
9902 if (CHIP_INT_MODE_IS_BC(sc)) {
9903 igu_seg_id = HC_SEG_ACCESS_NORM;
9905 igu_seg_id = IGU_SEG_ACCESS_NORM;
9908 bxe_zero_fp_sb(sc, fw_sb_id);
9910 if (!CHIP_IS_E1x(sc)) {
9911 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
9912 sb_data_e2.common.state = SB_ENABLED;
9913 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc);
9914 sb_data_e2.common.p_func.vf_id = vfid;
9915 sb_data_e2.common.p_func.vf_valid = vf_valid;
9916 sb_data_e2.common.p_func.vnic_id = SC_VN(sc);
9917 sb_data_e2.common.same_igu_sb_1b = TRUE;
9918 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr);
9919 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr);
9920 hc_sm_p = sb_data_e2.common.state_machine;
9921 sb_data_p = (uint32_t *)&sb_data_e2;
9922 data_size = (sizeof(struct hc_status_block_data_e2) /
9924 bxe_map_sb_state_machines(sb_data_e2.index_data);
9926 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x));
9927 sb_data_e1x.common.state = SB_ENABLED;
9928 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc);
9929 sb_data_e1x.common.p_func.vf_id = 0xff;
9930 sb_data_e1x.common.p_func.vf_valid = FALSE;
9931 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc);
9932 sb_data_e1x.common.same_igu_sb_1b = TRUE;
9933 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr);
9934 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr);
9935 hc_sm_p = sb_data_e1x.common.state_machine;
9936 sb_data_p = (uint32_t *)&sb_data_e1x;
9937 data_size = (sizeof(struct hc_status_block_data_e1x) /
9939 bxe_map_sb_state_machines(sb_data_e1x.index_data);
9942 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id);
9943 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id);
9945 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id);
9947 /* write indices to HW - PCI guarantees endianity of regpairs */
9948 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size);
9951 static inline uint8_t
9952 bxe_fp_qzone_id(struct bxe_fastpath *fp)
9954 if (CHIP_IS_E1x(fp->sc)) {
9955 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
9961 static inline uint32_t
9962 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc,
9963 struct bxe_fastpath *fp)
9965 uint32_t offset = BAR_USTRORM_INTMEM;
9969 return (PXP_VF_ADDR_USDM_QUEUES_START +
9970 (sc->acquire_resp.resc.hw_qid[fp->index] *
9971 sizeof(struct ustorm_queue_zone_data)));
9974 if (!CHIP_IS_E1x(sc)) {
9975 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
9977 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
9984 bxe_init_eth_fp(struct bxe_softc *sc,
9987 struct bxe_fastpath *fp = &sc->fp[idx];
9988 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 };
9989 unsigned long q_type = 0;
9995 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name),
9996 "bxe%d_fp%d_tx_lock", sc->unit, idx);
9997 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF);
9999 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name),
10000 "bxe%d_fp%d_rx_lock", sc->unit, idx);
10001 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF);
10003 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc));
10004 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc));
10006 fp->cl_id = (CHIP_IS_E1x(sc)) ?
10007 (SC_L_ID(sc) + idx) :
10008 /* want client ID same as IGU SB ID for non-E1 */
10010 fp->cl_qzone_id = bxe_fp_qzone_id(fp);
10012 /* setup sb indices */
10013 if (!CHIP_IS_E1x(sc)) {
10014 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values;
10015 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index;
10017 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values;
10018 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index;
10021 /* init shortcut */
10022 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp);
10024 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS];
10027 * XXX If multiple CoS is ever supported then each fastpath structure
10028 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
10030 for (cos = 0; cos < sc->max_cos; cos++) {
10033 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0];
10035 /* nothing more for a VF to do */
10040 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE,
10041 fp->fw_sb_id, fp->igu_sb_id);
10043 bxe_update_fp_sb_idx(fp);
10045 /* Configure Queue State object */
10046 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX);
10047 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX);
10049 ecore_init_queue_obj(sc,
10050 &sc->sp_objs[idx].q_obj,
10055 BXE_SP(sc, q_rdata),
10056 BXE_SP_MAPPING(sc, q_rdata),
10059 /* configure classification DBs */
10060 ecore_init_mac_obj(sc,
10061 &sc->sp_objs[idx].mac_obj,
10065 BXE_SP(sc, mac_rdata),
10066 BXE_SP_MAPPING(sc, mac_rdata),
10067 ECORE_FILTER_MAC_PENDING,
10069 ECORE_OBJ_TYPE_RX_TX,
10072 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n",
10073 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id);
10077 bxe_update_rx_prod(struct bxe_softc *sc,
10078 struct bxe_fastpath *fp,
10079 uint16_t rx_bd_prod,
10080 uint16_t rx_cq_prod,
10081 uint16_t rx_sge_prod)
10083 struct ustorm_eth_rx_producers rx_prods = { 0 };
10086 /* update producers */
10087 rx_prods.bd_prod = rx_bd_prod;
10088 rx_prods.cqe_prod = rx_cq_prod;
10089 rx_prods.sge_prod = rx_sge_prod;
10092 * Make sure that the BD and SGE data is updated before updating the
10093 * producers since FW might read the BD/SGE right after the producer
10095 * This is only applicable for weak-ordered memory model archs such
10096 * as IA-64. The following barrier is also mandatory since FW will
10097 * assumes BDs must have buffers.
10101 for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
10103 (fp->ustorm_rx_prods_offset + (i * 4)),
10104 ((uint32_t *)&rx_prods)[i]);
10107 wmb(); /* keep prod updates ordered */
10110 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n",
10111 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod);
10115 bxe_init_rx_rings(struct bxe_softc *sc)
10117 struct bxe_fastpath *fp;
10120 for (i = 0; i < sc->num_queues; i++) {
10123 fp->rx_bd_cons = 0;
10126 * Activate the BD ring...
10127 * Warning, this will generate an interrupt (to the TSTORM)
10128 * so this can only be done after the chip is initialized
10130 bxe_update_rx_prod(sc, fp,
10139 if (CHIP_IS_E1(sc)) {
10141 (BAR_USTRORM_INTMEM +
10142 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))),
10143 U64_LO(fp->rcq_dma.paddr));
10145 (BAR_USTRORM_INTMEM +
10146 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4),
10147 U64_HI(fp->rcq_dma.paddr));
10153 bxe_init_tx_ring_one(struct bxe_fastpath *fp)
10155 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
10156 fp->tx_db.data.zero_fill1 = 0;
10157 fp->tx_db.data.prod = 0;
10159 fp->tx_pkt_prod = 0;
10160 fp->tx_pkt_cons = 0;
10161 fp->tx_bd_prod = 0;
10162 fp->tx_bd_cons = 0;
10163 fp->eth_q_stats.tx_pkts = 0;
10167 bxe_init_tx_rings(struct bxe_softc *sc)
10171 for (i = 0; i < sc->num_queues; i++) {
10174 for (cos = 0; cos < sc->max_cos; cos++) {
10175 bxe_init_tx_ring_one(&sc->fp[i].txdata[cos]);
10178 bxe_init_tx_ring_one(&sc->fp[i]);
10184 bxe_init_def_sb(struct bxe_softc *sc)
10186 struct host_sp_status_block *def_sb = sc->def_sb;
10187 bus_addr_t mapping = sc->def_sb_dma.paddr;
10188 int igu_sp_sb_index;
10190 int port = SC_PORT(sc);
10191 int func = SC_FUNC(sc);
10192 int reg_offset, reg_offset_en5;
10195 struct hc_sp_status_block_data sp_sb_data;
10197 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
10199 if (CHIP_INT_MODE_IS_BC(sc)) {
10200 igu_sp_sb_index = DEF_SB_IGU_ID;
10201 igu_seg_id = HC_SEG_ACCESS_DEF;
10203 igu_sp_sb_index = sc->igu_dsb_id;
10204 igu_seg_id = IGU_SEG_ACCESS_DEF;
10208 section = ((uint64_t)mapping +
10209 offsetof(struct host_sp_status_block, atten_status_block));
10210 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
10211 sc->attn_state = 0;
10213 reg_offset = (port) ?
10214 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10215 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
10216 reg_offset_en5 = (port) ?
10217 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
10218 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0;
10220 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
10221 /* take care of sig[0]..sig[4] */
10222 for (sindex = 0; sindex < 4; sindex++) {
10223 sc->attn_group[index].sig[sindex] =
10224 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));
10227 if (!CHIP_IS_E1x(sc)) {
10229 * enable5 is separate from the rest of the registers,
10230 * and the address skip is 4 and not 16 between the
10233 sc->attn_group[index].sig[4] =
10234 REG_RD(sc, (reg_offset_en5 + (0x4 * index)));
10236 sc->attn_group[index].sig[4] = 0;
10240 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10241 reg_offset = (port) ?
10242 HC_REG_ATTN_MSG1_ADDR_L :
10243 HC_REG_ATTN_MSG0_ADDR_L;
10244 REG_WR(sc, reg_offset, U64_LO(section));
10245 REG_WR(sc, (reg_offset + 4), U64_HI(section));
10246 } else if (!CHIP_IS_E1x(sc)) {
10247 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
10248 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
10251 section = ((uint64_t)mapping +
10252 offsetof(struct host_sp_status_block, sp_sb));
10254 bxe_zero_sp_sb(sc);
10256 /* PCI guarantees endianity of regpair */
10257 sp_sb_data.state = SB_ENABLED;
10258 sp_sb_data.host_sb_addr.lo = U64_LO(section);
10259 sp_sb_data.host_sb_addr.hi = U64_HI(section);
10260 sp_sb_data.igu_sb_id = igu_sp_sb_index;
10261 sp_sb_data.igu_seg_id = igu_seg_id;
10262 sp_sb_data.p_func.pf_id = func;
10263 sp_sb_data.p_func.vnic_id = SC_VN(sc);
10264 sp_sb_data.p_func.vf_id = 0xff;
10266 bxe_wr_sp_sb_data(sc, &sp_sb_data);
10268 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
10272 bxe_init_sp_ring(struct bxe_softc *sc)
10274 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING);
10275 sc->spq_prod_idx = 0;
10276 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS];
10277 sc->spq_prod_bd = sc->spq;
10278 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT);
10282 bxe_init_eq_ring(struct bxe_softc *sc)
10284 union event_ring_elem *elem;
10287 for (i = 1; i <= NUM_EQ_PAGES; i++) {
10288 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1];
10290 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr +
10292 (i % NUM_EQ_PAGES)));
10293 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr +
10295 (i % NUM_EQ_PAGES)));
10299 sc->eq_prod = NUM_EQ_DESC;
10300 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS];
10302 atomic_store_rel_long(&sc->eq_spq_left,
10303 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING),
10304 NUM_EQ_DESC) - 1));
10308 bxe_init_internal_common(struct bxe_softc *sc)
10312 if (IS_MF_SI(sc)) {
10314 * In switch independent mode, the TSTORM needs to accept
10315 * packets that failed classification, since approximate match
10316 * mac addresses aren't written to NIG LLH.
10319 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET),
10321 } else if (!CHIP_IS_E1(sc)) { /* 57710 doesn't support MF */
10323 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET),
10328 * Zero this manually as its initialization is currently missing
10331 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) {
10333 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)),
10337 if (!CHIP_IS_E1x(sc)) {
10338 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET),
10339 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
10344 bxe_init_internal(struct bxe_softc *sc,
10345 uint32_t load_code)
10347 switch (load_code) {
10348 case FW_MSG_CODE_DRV_LOAD_COMMON:
10349 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
10350 bxe_init_internal_common(sc);
10353 case FW_MSG_CODE_DRV_LOAD_PORT:
10354 /* nothing to do */
10357 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
10358 /* internal memory per function is initialized inside bxe_pf_init */
10362 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code);
10368 storm_memset_func_cfg(struct bxe_softc *sc,
10369 struct tstorm_eth_function_common_config *tcfg,
10375 addr = (BAR_TSTRORM_INTMEM +
10376 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid));
10377 size = sizeof(struct tstorm_eth_function_common_config);
10378 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg);
10382 bxe_func_init(struct bxe_softc *sc,
10383 struct bxe_func_init_params *p)
10385 struct tstorm_eth_function_common_config tcfg = { 0 };
10387 if (CHIP_IS_E1x(sc)) {
10388 storm_memset_func_cfg(sc, &tcfg, p->func_id);
10391 /* Enable the function in the FW */
10392 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id);
10393 storm_memset_func_en(sc, p->func_id, 1);
10396 if (p->func_flgs & FUNC_FLG_SPQ) {
10397 storm_memset_spq_addr(sc, p->spq_map, p->func_id);
10399 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)),
10405 * Calculates the sum of vn_min_rates.
10406 * It's needed for further normalizing of the min_rates.
10408 * sum of vn_min_rates.
10410 * 0 - if all the min_rates are 0.
10411 * In the later case fainess algorithm should be deactivated.
10412 * If all min rates are not zero then those that are zeroes will be set to 1.
10415 bxe_calc_vn_min(struct bxe_softc *sc,
10416 struct cmng_init_input *input)
10419 uint32_t vn_min_rate;
10423 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10424 vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10425 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
10426 FUNC_MF_CFG_MIN_BW_SHIFT) * 100);
10428 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10429 /* skip hidden VNs */
10431 } else if (!vn_min_rate) {
10432 /* If min rate is zero - set it to 100 */
10433 vn_min_rate = DEF_MIN_RATE;
10438 input->vnic_min_rate[vn] = vn_min_rate;
10441 /* if ETS or all min rates are zeros - disable fairness */
10442 if (BXE_IS_ETS_ENABLED(sc)) {
10443 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10444 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n");
10445 } else if (all_zero) {
10446 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10447 BLOGD(sc, DBG_LOAD,
10448 "Fariness disabled (all MIN values are zeroes)\n");
10450 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
10454 static inline uint16_t
10455 bxe_extract_max_cfg(struct bxe_softc *sc,
10458 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
10459 FUNC_MF_CFG_MAX_BW_SHIFT);
10462 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n");
10470 bxe_calc_vn_max(struct bxe_softc *sc,
10472 struct cmng_init_input *input)
10474 uint16_t vn_max_rate;
10475 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn];
10478 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
10481 max_cfg = bxe_extract_max_cfg(sc, vn_cfg);
10483 if (IS_MF_SI(sc)) {
10484 /* max_cfg in percents of linkspeed */
10485 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100);
10486 } else { /* SD modes */
10487 /* max_cfg is absolute in 100Mb units */
10488 vn_max_rate = (max_cfg * 100);
10492 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
10494 input->vnic_max_rate[vn] = vn_max_rate;
10498 bxe_cmng_fns_init(struct bxe_softc *sc,
10502 struct cmng_init_input input;
10505 memset(&input, 0, sizeof(struct cmng_init_input));
10507 input.port_rate = sc->link_vars.line_speed;
10509 if (cmng_type == CMNG_FNS_MINMAX) {
10510 /* read mf conf from shmem */
10512 bxe_read_mf_cfg(sc);
10515 /* get VN min rate and enable fairness if not 0 */
10516 bxe_calc_vn_min(sc, &input);
10518 /* get VN max rate */
10519 if (sc->port.pmf) {
10520 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10521 bxe_calc_vn_max(sc, vn, &input);
10525 /* always enable rate shaping and fairness */
10526 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
10528 ecore_init_cmng(&input, &sc->cmng);
10532 /* rate shaping and fairness are disabled */
10533 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n");
10537 bxe_get_cmng_fns_mode(struct bxe_softc *sc)
10539 if (CHIP_REV_IS_SLOW(sc)) {
10540 return (CMNG_FNS_NONE);
10544 return (CMNG_FNS_MINMAX);
10547 return (CMNG_FNS_NONE);
10551 storm_memset_cmng(struct bxe_softc *sc,
10552 struct cmng_init *cmng,
10560 addr = (BAR_XSTRORM_INTMEM +
10561 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port));
10562 size = sizeof(struct cmng_struct_per_port);
10563 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port);
10565 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) {
10566 func = func_by_vn(sc, vn);
10568 addr = (BAR_XSTRORM_INTMEM +
10569 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func));
10570 size = sizeof(struct rate_shaping_vars_per_vn);
10571 ecore_storm_memset_struct(sc, addr, size,
10572 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]);
10574 addr = (BAR_XSTRORM_INTMEM +
10575 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func));
10576 size = sizeof(struct fairness_vars_per_vn);
10577 ecore_storm_memset_struct(sc, addr, size,
10578 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]);
10583 bxe_pf_init(struct bxe_softc *sc)
10585 struct bxe_func_init_params func_init = { 0 };
10586 struct event_ring_data eq_data = { { 0 } };
10589 if (!CHIP_IS_E1x(sc)) {
10590 /* reset IGU PF statistics: MSIX + ATTN */
10593 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10594 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10595 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10599 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
10600 (BXE_IGU_STAS_MSG_VF_CNT * 4) +
10601 (BXE_IGU_STAS_MSG_PF_CNT * 4) +
10602 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)),
10606 /* function setup flags */
10607 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
10610 * This flag is relevant for E1x only.
10611 * E2 doesn't have a TPA configuration in a function level.
10613 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0;
10615 func_init.func_flgs = flags;
10616 func_init.pf_id = SC_FUNC(sc);
10617 func_init.func_id = SC_FUNC(sc);
10618 func_init.spq_map = sc->spq_dma.paddr;
10619 func_init.spq_prod = sc->spq_prod_idx;
10621 bxe_func_init(sc, &func_init);
10623 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port));
10626 * Congestion management values depend on the link rate.
10627 * There is no active link so initial link rate is set to 10Gbps.
10628 * When the link comes up the congestion management values are
10629 * re-calculated according to the actual link rate.
10631 sc->link_vars.line_speed = SPEED_10000;
10632 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc));
10634 /* Only the PMF sets the HW */
10635 if (sc->port.pmf) {
10636 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
10639 /* init Event Queue - PCI bus guarantees correct endainity */
10640 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr);
10641 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr);
10642 eq_data.producer = sc->eq_prod;
10643 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
10644 eq_data.sb_id = DEF_SB_ID;
10645 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc));
10649 bxe_hc_int_enable(struct bxe_softc *sc)
10651 int port = SC_PORT(sc);
10652 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10653 uint32_t val = REG_RD(sc, addr);
10654 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10655 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10656 (sc->intr_count == 1)) ? TRUE : FALSE;
10657 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10660 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10661 HC_CONFIG_0_REG_INT_LINE_EN_0);
10662 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10663 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10665 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
10668 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
10669 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10670 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10671 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10673 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10674 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10675 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10676 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10678 if (!CHIP_IS_E1(sc)) {
10679 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n",
10682 REG_WR(sc, addr, val);
10684 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
10688 if (CHIP_IS_E1(sc)) {
10689 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF);
10692 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
10693 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10695 REG_WR(sc, addr, val);
10697 /* ensure that HC_CONFIG is written before leading/trailing edge config */
10700 if (!CHIP_IS_E1(sc)) {
10701 /* init leading/trailing edge */
10703 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10704 if (sc->port.pmf) {
10705 /* enable nig and gpio3 attention */
10712 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val);
10713 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val);
10716 /* make sure that interrupts are indeed enabled from here on */
10721 bxe_igu_int_enable(struct bxe_softc *sc)
10724 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE;
10725 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) &&
10726 (sc->intr_count == 1)) ? TRUE : FALSE;
10727 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE;
10729 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10732 val &= ~(IGU_PF_CONF_INT_LINE_EN |
10733 IGU_PF_CONF_SINGLE_ISR_EN);
10734 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10735 IGU_PF_CONF_ATTN_BIT_EN);
10737 val |= IGU_PF_CONF_SINGLE_ISR_EN;
10740 val &= ~IGU_PF_CONF_INT_LINE_EN;
10741 val |= (IGU_PF_CONF_MSI_MSIX_EN |
10742 IGU_PF_CONF_ATTN_BIT_EN |
10743 IGU_PF_CONF_SINGLE_ISR_EN);
10745 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
10746 val |= (IGU_PF_CONF_INT_LINE_EN |
10747 IGU_PF_CONF_ATTN_BIT_EN |
10748 IGU_PF_CONF_SINGLE_ISR_EN);
10751 /* clean previous status - need to configure igu prior to ack*/
10752 if ((!msix) || single_msix) {
10753 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10757 val |= IGU_PF_CONF_FUNC_EN;
10759 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n",
10760 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx")));
10762 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10766 /* init leading/trailing edge */
10768 val = (0xee0f | (1 << (SC_VN(sc) + 4)));
10769 if (sc->port.pmf) {
10770 /* enable nig and gpio3 attention */
10777 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val);
10778 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val);
10780 /* make sure that interrupts are indeed enabled from here on */
10785 bxe_int_enable(struct bxe_softc *sc)
10787 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10788 bxe_hc_int_enable(sc);
10790 bxe_igu_int_enable(sc);
10795 bxe_hc_int_disable(struct bxe_softc *sc)
10797 int port = SC_PORT(sc);
10798 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
10799 uint32_t val = REG_RD(sc, addr);
10802 * In E1 we must use only PCI configuration space to disable MSI/MSIX
10803 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC
10806 if (CHIP_IS_E1(sc)) {
10808 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register
10809 * to prevent from HC sending interrupts after we exit the function
10811 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0);
10813 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10814 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10815 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10817 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
10818 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
10819 HC_CONFIG_0_REG_INT_LINE_EN_0 |
10820 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
10823 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr);
10825 /* flush all outstanding writes */
10828 REG_WR(sc, addr, val);
10829 if (REG_RD(sc, addr) != val) {
10830 BLOGE(sc, "proper val not read from HC IGU!\n");
10835 bxe_igu_int_disable(struct bxe_softc *sc)
10837 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
10839 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
10840 IGU_PF_CONF_INT_LINE_EN |
10841 IGU_PF_CONF_ATTN_BIT_EN);
10843 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val);
10845 /* flush all outstanding writes */
10848 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
10849 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {
10850 BLOGE(sc, "proper val not read from IGU!\n");
10855 bxe_int_disable(struct bxe_softc *sc)
10857 if (sc->devinfo.int_block == INT_BLOCK_HC) {
10858 bxe_hc_int_disable(sc);
10860 bxe_igu_int_disable(sc);
10865 bxe_nic_init(struct bxe_softc *sc,
10870 for (i = 0; i < sc->num_queues; i++) {
10871 bxe_init_eth_fp(sc, i);
10874 rmb(); /* ensure status block indices were read */
10876 bxe_init_rx_rings(sc);
10877 bxe_init_tx_rings(sc);
10883 /* initialize MOD_ABS interrupts */
10884 elink_init_mod_abs_int(sc, &sc->link_vars,
10885 sc->devinfo.chip_id,
10886 sc->devinfo.shmem_base,
10887 sc->devinfo.shmem2_base,
10890 bxe_init_def_sb(sc);
10891 bxe_update_dsb_idx(sc);
10892 bxe_init_sp_ring(sc);
10893 bxe_init_eq_ring(sc);
10894 bxe_init_internal(sc, load_code);
10896 bxe_stats_init(sc);
10898 /* flush all before enabling interrupts */
10901 bxe_int_enable(sc);
10903 /* check for SPIO5 */
10904 bxe_attn_int_deasserted0(sc,
10906 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
10908 AEU_INPUTS_ATTN_BITS_SPIO5);
10912 bxe_init_objs(struct bxe_softc *sc)
10914 /* mcast rules must be added to tx if tx switching is enabled */
10915 ecore_obj_type o_type =
10916 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX :
10919 /* RX_MODE controlling object */
10920 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj);
10922 /* multicast configuration controlling object */
10923 ecore_init_mcast_obj(sc,
10929 BXE_SP(sc, mcast_rdata),
10930 BXE_SP_MAPPING(sc, mcast_rdata),
10931 ECORE_FILTER_MCAST_PENDING,
10935 /* Setup CAM credit pools */
10936 ecore_init_mac_credit_pool(sc,
10939 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10940 VNICS_PER_PATH(sc));
10942 ecore_init_vlan_credit_pool(sc,
10944 SC_ABS_FUNC(sc) >> 1,
10945 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) :
10946 VNICS_PER_PATH(sc));
10948 /* RSS configuration object */
10949 ecore_init_rss_config_obj(sc,
10955 BXE_SP(sc, rss_rdata),
10956 BXE_SP_MAPPING(sc, rss_rdata),
10957 ECORE_FILTER_RSS_CONF_PENDING,
10958 &sc->sp_state, ECORE_OBJ_TYPE_RX);
10962 * Initialize the function. This must be called before sending CLIENT_SETUP
10963 * for the first client.
10966 bxe_func_start(struct bxe_softc *sc)
10968 struct ecore_func_state_params func_params = { NULL };
10969 struct ecore_func_start_params *start_params = &func_params.params.start;
10971 /* Prepare parameters for function state transitions */
10972 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT);
10974 func_params.f_obj = &sc->func_obj;
10975 func_params.cmd = ECORE_F_CMD_START;
10977 /* Function parameters */
10978 start_params->mf_mode = sc->devinfo.mf_info.mf_mode;
10979 start_params->sd_vlan_tag = OVLAN(sc);
10981 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) {
10982 start_params->network_cos_mode = STATIC_COS;
10983 } else { /* CHIP_IS_E1X */
10984 start_params->network_cos_mode = FW_WRR;
10987 start_params->gre_tunnel_mode = 0;
10988 start_params->gre_tunnel_rss = 0;
10990 return (ecore_func_state_change(sc, &func_params));
10994 bxe_set_power_state(struct bxe_softc *sc,
10999 /* If there is no power capability, silently succeed */
11000 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) {
11001 BLOGW(sc, "No power capability\n");
11005 pmcsr = pci_read_config(sc->dev,
11006 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11011 pci_write_config(sc->dev,
11012 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11013 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2);
11015 if (pmcsr & PCIM_PSTAT_DMASK) {
11016 /* delay required during transition out of D3hot */
11023 /* XXX if there are other clients above don't shut down the power */
11025 /* don't shut down the power for emulation and FPGA */
11026 if (CHIP_REV_IS_SLOW(sc)) {
11030 pmcsr &= ~PCIM_PSTAT_DMASK;
11031 pmcsr |= PCIM_PSTAT_D3;
11034 pmcsr |= PCIM_PSTAT_PMEENABLE;
11037 pci_write_config(sc->dev,
11038 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS),
11042 * No more memory access after this point until device is brought back
11048 BLOGE(sc, "Can't support PCI power state = %d\n", state);
11056 /* return true if succeeded to acquire the lock */
11058 bxe_trylock_hw_lock(struct bxe_softc *sc,
11061 uint32_t lock_status;
11062 uint32_t resource_bit = (1 << resource);
11063 int func = SC_FUNC(sc);
11064 uint32_t hw_lock_control_reg;
11066 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource);
11068 /* Validating that the resource is within range */
11069 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
11070 BLOGD(sc, DBG_LOAD,
11071 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
11072 resource, HW_LOCK_MAX_RESOURCE_VALUE);
11077 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
11079 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
11082 /* try to acquire the lock */
11083 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
11084 lock_status = REG_RD(sc, hw_lock_control_reg);
11085 if (lock_status & resource_bit) {
11089 BLOGE(sc, "Failed to get a resource lock 0x%x\n", resource);
11095 * Get the recovery leader resource id according to the engine this function
11096 * belongs to. Currently only only 2 engines is supported.
11099 bxe_get_leader_lock_resource(struct bxe_softc *sc)
11102 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1);
11104 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0);
11108 /* try to acquire a leader lock for current engine */
11110 bxe_trylock_leader_lock(struct bxe_softc *sc)
11112 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
11116 bxe_release_leader_lock(struct bxe_softc *sc)
11118 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc)));
11121 /* close gates #2, #3 and #4 */
11123 bxe_set_234_gates(struct bxe_softc *sc,
11128 /* gates #2 and #4a are closed/opened for "not E1" only */
11129 if (!CHIP_IS_E1(sc)) {
11131 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
11133 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
11137 if (CHIP_IS_E1x(sc)) {
11138 /* prevent interrupts from HC on both ports */
11139 val = REG_RD(sc, HC_REG_CONFIG_1);
11140 REG_WR(sc, HC_REG_CONFIG_1,
11141 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
11142 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
11144 val = REG_RD(sc, HC_REG_CONFIG_0);
11145 REG_WR(sc, HC_REG_CONFIG_0,
11146 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
11147 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
11149 /* Prevent incomming interrupts in IGU */
11150 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
11152 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION,
11154 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
11155 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
11158 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n",
11159 close ? "closing" : "opening");
11164 /* poll for pending writes bit, it should get cleared in no more than 1s */
11166 bxe_er_poll_igu_vq(struct bxe_softc *sc)
11168 uint32_t cnt = 1000;
11169 uint32_t pend_bits = 0;
11172 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);
11174 if (pend_bits == 0) {
11179 } while (--cnt > 0);
11182 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits);
11189 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */
11192 bxe_clp_reset_prep(struct bxe_softc *sc,
11193 uint32_t *magic_val)
11195 /* Do some magic... */
11196 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
11197 *magic_val = val & SHARED_MF_CLP_MAGIC;
11198 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
11201 /* restore the value of the 'magic' bit */
11203 bxe_clp_reset_done(struct bxe_softc *sc,
11204 uint32_t magic_val)
11206 /* Restore the 'magic' bit value... */
11207 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb);
11208 MFCFG_WR(sc, shared_mf_config.clp_mb,
11209 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
11212 /* prepare for MCP reset, takes care of CLP configurations */
11214 bxe_reset_mcp_prep(struct bxe_softc *sc,
11215 uint32_t *magic_val)
11218 uint32_t validity_offset;
11220 /* set `magic' bit in order to save MF config */
11221 if (!CHIP_IS_E1(sc)) {
11222 bxe_clp_reset_prep(sc, magic_val);
11225 /* get shmem offset */
11226 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
11228 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
11230 /* Clear validity map flags */
11232 REG_WR(sc, shmem + validity_offset, 0);
11236 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
11237 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
11240 bxe_mcp_wait_one(struct bxe_softc *sc)
11242 /* special handling for emulation and FPGA (10 times longer) */
11243 if (CHIP_REV_IS_SLOW(sc)) {
11244 DELAY((MCP_ONE_TIMEOUT*10) * 1000);
11246 DELAY((MCP_ONE_TIMEOUT) * 1000);
11250 /* initialize shmem_base and waits for validity signature to appear */
11252 bxe_init_shmem(struct bxe_softc *sc)
11258 sc->devinfo.shmem_base =
11259 sc->link_params.shmem_base =
11260 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
11262 if (sc->devinfo.shmem_base) {
11263 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
11264 if (val & SHR_MEM_VALIDITY_MB)
11268 bxe_mcp_wait_one(sc);
11270 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
11272 BLOGE(sc, "BAD MCP validity signature\n");
11278 bxe_reset_mcp_comp(struct bxe_softc *sc,
11279 uint32_t magic_val)
11281 int rc = bxe_init_shmem(sc);
11283 /* Restore the `magic' bit value */
11284 if (!CHIP_IS_E1(sc)) {
11285 bxe_clp_reset_done(sc, magic_val);
11292 bxe_pxp_prep(struct bxe_softc *sc)
11294 if (!CHIP_IS_E1(sc)) {
11295 REG_WR(sc, PXP2_REG_RD_START_INIT, 0);
11296 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0);
11302 * Reset the whole chip except for:
11304 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit)
11306 * - MISC (including AEU)
11311 bxe_process_kill_chip_reset(struct bxe_softc *sc,
11314 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
11315 uint32_t global_bits2, stay_reset2;
11318 * Bits that have to be set in reset_mask2 if we want to reset 'global'
11319 * (per chip) blocks.
11322 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
11323 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
11326 * Don't reset the following blocks.
11327 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
11328 * reset, as in 4 port device they might still be owned
11329 * by the MCP (there is only one leader per path).
11332 MISC_REGISTERS_RESET_REG_1_RST_HC |
11333 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
11334 MISC_REGISTERS_RESET_REG_1_RST_PXP;
11337 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
11338 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
11339 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
11340 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
11341 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
11342 MISC_REGISTERS_RESET_REG_2_RST_GRC |
11343 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
11344 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
11345 MISC_REGISTERS_RESET_REG_2_RST_ATC |
11346 MISC_REGISTERS_RESET_REG_2_PGLC |
11347 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
11348 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
11349 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
11350 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
11351 MISC_REGISTERS_RESET_REG_2_UMAC0 |
11352 MISC_REGISTERS_RESET_REG_2_UMAC1;
11355 * Keep the following blocks in reset:
11356 * - all xxMACs are handled by the elink code.
11359 MISC_REGISTERS_RESET_REG_2_XMAC |
11360 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
11362 /* Full reset masks according to the chip */
11363 reset_mask1 = 0xffffffff;
11365 if (CHIP_IS_E1(sc))
11366 reset_mask2 = 0xffff;
11367 else if (CHIP_IS_E1H(sc))
11368 reset_mask2 = 0x1ffff;
11369 else if (CHIP_IS_E2(sc))
11370 reset_mask2 = 0xfffff;
11371 else /* CHIP_IS_E3 */
11372 reset_mask2 = 0x3ffffff;
11374 /* Don't reset global blocks unless we need to */
11376 reset_mask2 &= ~global_bits2;
11379 * In case of attention in the QM, we need to reset PXP
11380 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
11381 * because otherwise QM reset would release 'close the gates' shortly
11382 * before resetting the PXP, then the PSWRQ would send a write
11383 * request to PGLUE. Then when PXP is reset, PGLUE would try to
11384 * read the payload data from PSWWR, but PSWWR would not
11385 * respond. The write queue in PGLUE would stuck, dmae commands
11386 * would not return. Therefore it's important to reset the second
11387 * reset register (containing the
11388 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
11389 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
11392 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11393 reset_mask2 & (~not_reset_mask2));
11395 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
11396 reset_mask1 & (~not_reset_mask1));
11401 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
11402 reset_mask2 & (~stay_reset2));
11407 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
11412 bxe_process_kill(struct bxe_softc *sc,
11417 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
11418 uint32_t tags_63_32 = 0;
11420 /* Empty the Tetris buffer, wait for 1s */
11422 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);
11423 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);
11424 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);
11425 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);
11426 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);
11427 if (CHIP_IS_E3(sc)) {
11428 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);
11431 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
11432 ((port_is_idle_0 & 0x1) == 0x1) &&
11433 ((port_is_idle_1 & 0x1) == 0x1) &&
11434 (pgl_exp_rom2 == 0xffffffff) &&
11435 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff)))
11438 } while (cnt-- > 0);
11441 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there "
11442 "are still outstanding read requests after 1s! "
11443 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, "
11444 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
11445 sr_cnt, blk_cnt, port_is_idle_0,
11446 port_is_idle_1, pgl_exp_rom2);
11452 /* Close gates #2, #3 and #4 */
11453 bxe_set_234_gates(sc, TRUE);
11455 /* Poll for IGU VQs for 57712 and newer chips */
11456 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) {
11460 /* XXX indicate that "process kill" is in progress to MCP */
11462 /* clear "unprepared" bit */
11463 REG_WR(sc, MISC_REG_UNPREPARED, 0);
11466 /* Make sure all is written to the chip before the reset */
11470 * Wait for 1ms to empty GLUE and PCI-E core queues,
11471 * PSWHST, GRC and PSWRD Tetris buffer.
11475 /* Prepare to chip reset: */
11478 bxe_reset_mcp_prep(sc, &val);
11485 /* reset the chip */
11486 bxe_process_kill_chip_reset(sc, global);
11489 /* clear errors in PGB */
11490 if (!CHIP_IS_E1(sc))
11491 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
11493 /* Recover after reset: */
11495 if (global && bxe_reset_mcp_comp(sc, val)) {
11499 /* XXX add resetting the NO_MCP mode DB here */
11501 /* Open the gates #2, #3 and #4 */
11502 bxe_set_234_gates(sc, FALSE);
11505 * IGU/AEU preparation bring back the AEU/IGU to a reset state
11506 * re-enable attentions
11513 bxe_leader_reset(struct bxe_softc *sc)
11516 uint8_t global = bxe_reset_is_global(sc);
11517 uint32_t load_code;
11520 * If not going to reset MCP, load "fake" driver to reset HW while
11521 * driver is owner of the HW.
11523 if (!global && !BXE_NOMCP(sc)) {
11524 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ,
11525 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
11527 BLOGE(sc, "MCP response failure, aborting\n");
11529 goto exit_leader_reset;
11532 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
11533 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
11534 BLOGE(sc, "MCP unexpected response, aborting\n");
11536 goto exit_leader_reset2;
11539 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
11541 BLOGE(sc, "MCP response failure, aborting\n");
11543 goto exit_leader_reset2;
11547 /* try to recover after the failure */
11548 if (bxe_process_kill(sc, global)) {
11549 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc));
11551 goto exit_leader_reset2;
11555 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver
11558 bxe_set_reset_done(sc);
11560 bxe_clear_reset_global(sc);
11563 exit_leader_reset2:
11565 /* unload "fake driver" if it was loaded */
11566 if (!global && !BXE_NOMCP(sc)) {
11567 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
11568 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
11574 bxe_release_leader_lock(sc);
11581 * prepare INIT transition, parameters configured:
11582 * - HC configuration
11583 * - Queue's CDU context
11586 bxe_pf_q_prep_init(struct bxe_softc *sc,
11587 struct bxe_fastpath *fp,
11588 struct ecore_queue_init_params *init_params)
11591 int cxt_index, cxt_offset;
11593 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);
11594 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);
11596 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);
11597 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);
11600 init_params->rx.hc_rate =
11601 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0;
11602 init_params->tx.hc_rate =
11603 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0;
11606 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id;
11608 /* CQ index among the SB indices */
11609 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11610 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
11612 /* set maximum number of COSs supported by this queue */
11613 init_params->max_cos = sc->max_cos;
11615 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n",
11616 fp->index, init_params->max_cos);
11618 /* set the context pointers queue object */
11619 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
11620 /* XXX change index/cid here if ever support multiple tx CoS */
11621 /* fp->txdata[cos]->cid */
11622 cxt_index = fp->index / ILT_PAGE_CIDS;
11623 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS);
11624 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth;
11628 /* set flags that are common for the Tx-only and not normal connections */
11629 static unsigned long
11630 bxe_get_common_flags(struct bxe_softc *sc,
11631 struct bxe_fastpath *fp,
11632 uint8_t zero_stats)
11634 unsigned long flags = 0;
11636 /* PF driver will always initialize the Queue to an ACTIVE state */
11637 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags);
11640 * tx only connections collect statistics (on the same index as the
11641 * parent connection). The statistics are zeroed when the parent
11642 * connection is initialized.
11645 bxe_set_bit(ECORE_Q_FLG_STATS, &flags);
11647 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);
11651 * tx only connections can support tx-switching, though their
11652 * CoS-ness doesn't survive the loopback
11654 if (sc->flags & BXE_TX_SWITCHING) {
11655 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);
11658 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);
11663 static unsigned long
11664 bxe_get_q_flags(struct bxe_softc *sc,
11665 struct bxe_fastpath *fp,
11668 unsigned long flags = 0;
11670 if (IS_MF_SD(sc)) {
11671 bxe_set_bit(ECORE_Q_FLG_OV, &flags);
11674 if (sc->ifnet->if_capenable & IFCAP_LRO) {
11675 bxe_set_bit(ECORE_Q_FLG_TPA, &flags);
11676 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags);
11678 if (fp->mode == TPA_MODE_GRO)
11679 __set_bit(ECORE_Q_FLG_TPA_GRO, &flags);
11684 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);
11685 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags);
11688 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags);
11691 /* configure silent vlan removal */
11692 if (IS_MF_AFEX(sc)) {
11693 bxe_set_bit(ECORE_Q_FLG_SILENT_VLAN_REM, &flags);
11697 /* merge with common flags */
11698 return (flags | bxe_get_common_flags(sc, fp, TRUE));
11702 bxe_pf_q_prep_general(struct bxe_softc *sc,
11703 struct bxe_fastpath *fp,
11704 struct ecore_general_setup_params *gen_init,
11707 gen_init->stat_id = bxe_stats_id(fp);
11708 gen_init->spcl_id = fp->cl_id;
11709 gen_init->mtu = sc->mtu;
11710 gen_init->cos = cos;
11714 bxe_pf_rx_q_prep(struct bxe_softc *sc,
11715 struct bxe_fastpath *fp,
11716 struct rxq_pause_params *pause,
11717 struct ecore_rxq_setup_params *rxq_init)
11719 uint8_t max_sge = 0;
11720 uint16_t sge_sz = 0;
11721 uint16_t tpa_agg_size = 0;
11723 if (sc->ifnet->if_capenable & IFCAP_LRO) {
11724 pause->sge_th_lo = SGE_TH_LO(sc);
11725 pause->sge_th_hi = SGE_TH_HI(sc);
11727 /* validate SGE ring has enough to cross high threshold */
11728 if (sc->dropless_fc &&
11729 (pause->sge_th_hi + FW_PREFETCH_CNT) >
11730 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) {
11731 BLOGW(sc, "sge ring threshold limit\n");
11734 /* minimum max_aggregation_size is 2*MTU (two full buffers) */
11735 tpa_agg_size = (2 * sc->mtu);
11736 if (tpa_agg_size < sc->max_aggregation_size) {
11737 tpa_agg_size = sc->max_aggregation_size;
11740 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT;
11741 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
11742 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11743 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff);
11746 /* pause - not for e1 */
11747 if (!CHIP_IS_E1(sc)) {
11748 pause->bd_th_lo = BD_TH_LO(sc);
11749 pause->bd_th_hi = BD_TH_HI(sc);
11751 pause->rcq_th_lo = RCQ_TH_LO(sc);
11752 pause->rcq_th_hi = RCQ_TH_HI(sc);
11754 /* validate rings have enough entries to cross high thresholds */
11755 if (sc->dropless_fc &&
11756 pause->bd_th_hi + FW_PREFETCH_CNT >
11757 sc->rx_ring_size) {
11758 BLOGW(sc, "rx bd ring threshold limit\n");
11761 if (sc->dropless_fc &&
11762 pause->rcq_th_hi + FW_PREFETCH_CNT >
11763 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) {
11764 BLOGW(sc, "rcq ring threshold limit\n");
11767 pause->pri_map = 1;
11771 rxq_init->dscr_map = fp->rx_dma.paddr;
11772 rxq_init->sge_map = fp->rx_sge_dma.paddr;
11773 rxq_init->rcq_map = fp->rcq_dma.paddr;
11774 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE);
11777 * This should be a maximum number of data bytes that may be
11778 * placed on the BD (not including paddings).
11780 rxq_init->buf_sz = (fp->rx_buf_size -
11781 IP_HEADER_ALIGNMENT_PADDING);
11783 rxq_init->cl_qzone_id = fp->cl_qzone_id;
11784 rxq_init->tpa_agg_sz = tpa_agg_size;
11785 rxq_init->sge_buf_sz = sge_sz;
11786 rxq_init->max_sges_pkt = max_sge;
11787 rxq_init->rss_engine_id = SC_FUNC(sc);
11788 rxq_init->mcast_engine_id = SC_FUNC(sc);
11791 * Maximum number or simultaneous TPA aggregation for this Queue.
11792 * For PF Clients it should be the maximum available number.
11793 * VF driver(s) may want to define it to a smaller value.
11795 rxq_init->max_tpa_queues = MAX_AGG_QS(sc);
11797 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT;
11798 rxq_init->fw_sb_id = fp->fw_sb_id;
11800 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
11803 * configure silent vlan removal
11804 * if multi function mode is afex, then mask default vlan
11806 if (IS_MF_AFEX(sc)) {
11807 rxq_init->silent_removal_value =
11808 sc->devinfo.mf_info.afex_def_vlan_tag;
11809 rxq_init->silent_removal_mask = EVL_VLID_MASK;
11814 bxe_pf_tx_q_prep(struct bxe_softc *sc,
11815 struct bxe_fastpath *fp,
11816 struct ecore_txq_setup_params *txq_init,
11820 * XXX If multiple CoS is ever supported then each fastpath structure
11821 * will need to maintain tx producer/consumer/dma/etc values *per* CoS.
11822 * fp->txdata[cos]->tx_dma.paddr;
11824 txq_init->dscr_map = fp->tx_dma.paddr;
11825 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
11826 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
11827 txq_init->fw_sb_id = fp->fw_sb_id;
11830 * set the TSS leading client id for TX classfication to the
11831 * leading RSS client id
11833 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id);
11837 * This function performs 2 steps in a queue state machine:
11842 bxe_setup_queue(struct bxe_softc *sc,
11843 struct bxe_fastpath *fp,
11846 struct ecore_queue_state_params q_params = { NULL };
11847 struct ecore_queue_setup_params *setup_params =
11848 &q_params.params.setup;
11850 struct ecore_queue_setup_tx_only_params *tx_only_params =
11851 &q_params.params.tx_only;
11856 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index);
11858 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
11860 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj;
11862 /* we want to wait for completion in this context */
11863 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
11865 /* prepare the INIT parameters */
11866 bxe_pf_q_prep_init(sc, fp, &q_params.params.init);
11868 /* Set the command */
11869 q_params.cmd = ECORE_Q_CMD_INIT;
11871 /* Change the state to INIT */
11872 rc = ecore_queue_state_change(sc, &q_params);
11874 BLOGE(sc, "Queue(%d) INIT failed\n", fp->index);
11878 BLOGD(sc, DBG_LOAD, "init complete\n");
11880 /* now move the Queue to the SETUP state */
11881 memset(setup_params, 0, sizeof(*setup_params));
11883 /* set Queue flags */
11884 setup_params->flags = bxe_get_q_flags(sc, fp, leading);
11886 /* set general SETUP parameters */
11887 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params,
11888 FIRST_TX_COS_INDEX);
11890 bxe_pf_rx_q_prep(sc, fp,
11891 &setup_params->pause_params,
11892 &setup_params->rxq_params);
11894 bxe_pf_tx_q_prep(sc, fp,
11895 &setup_params->txq_params,
11896 FIRST_TX_COS_INDEX);
11898 /* Set the command */
11899 q_params.cmd = ECORE_Q_CMD_SETUP;
11901 /* change the state to SETUP */
11902 rc = ecore_queue_state_change(sc, &q_params);
11904 BLOGE(sc, "Queue(%d) SETUP failed\n", fp->index);
11909 /* loop through the relevant tx-only indices */
11910 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
11911 tx_index < sc->max_cos;
11913 /* prepare and send tx-only ramrod*/
11914 rc = bxe_setup_tx_only(sc, fp, &q_params,
11915 tx_only_params, tx_index, leading);
11917 BLOGE(sc, "Queue(%d.%d) TX_ONLY_SETUP failed\n",
11918 fp->index, tx_index);
11928 bxe_setup_leading(struct bxe_softc *sc)
11930 return (bxe_setup_queue(sc, &sc->fp[0], TRUE));
11934 bxe_config_rss_pf(struct bxe_softc *sc,
11935 struct ecore_rss_config_obj *rss_obj,
11936 uint8_t config_hash)
11938 struct ecore_config_rss_params params = { NULL };
11942 * Although RSS is meaningless when there is a single HW queue we
11943 * still need it enabled in order to have HW Rx hash generated.
11946 params.rss_obj = rss_obj;
11948 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
11950 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags);
11952 /* RSS configuration */
11953 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags);
11954 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags);
11955 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags);
11956 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags);
11957 if (rss_obj->udp_rss_v4) {
11958 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags);
11960 if (rss_obj->udp_rss_v6) {
11961 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags);
11965 params.rss_result_mask = MULTI_MASK;
11967 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
11971 for (i = 0; i < sizeof(params.rss_key) / 4; i++) {
11972 params.rss_key[i] = arc4random();
11975 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags);
11978 return (ecore_config_rss(sc, ¶ms));
11982 bxe_config_rss_eth(struct bxe_softc *sc,
11983 uint8_t config_hash)
11985 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash));
11989 bxe_init_rss_pf(struct bxe_softc *sc)
11991 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc);
11995 * Prepare the initial contents of the indirection table if
11998 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) {
11999 sc->rss_conf_obj.ind_table[i] =
12000 (sc->fp->cl_id + (i % num_eth_queues));
12004 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1;
12008 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
12009 * per-port, so if explicit configuration is needed, do it only
12012 * For 57712 and newer it's a per-function configuration.
12014 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc)));
12018 bxe_set_mac_one(struct bxe_softc *sc,
12020 struct ecore_vlan_mac_obj *obj,
12023 unsigned long *ramrod_flags)
12025 struct ecore_vlan_mac_ramrod_params ramrod_param;
12028 memset(&ramrod_param, 0, sizeof(ramrod_param));
12030 /* fill in general parameters */
12031 ramrod_param.vlan_mac_obj = obj;
12032 ramrod_param.ramrod_flags = *ramrod_flags;
12034 /* fill a user request section if needed */
12035 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) {
12036 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
12038 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
12040 /* Set the command: ADD or DEL */
12041 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :
12042 ECORE_VLAN_MAC_DEL;
12045 rc = ecore_config_vlan_mac(sc, &ramrod_param);
12047 if (rc == ECORE_EXISTS) {
12048 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12049 /* do not treat adding same MAC as error */
12051 } else if (rc < 0) {
12052 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc);
12059 bxe_set_eth_mac(struct bxe_softc *sc,
12062 unsigned long ramrod_flags = 0;
12064 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n");
12066 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12068 /* Eth MAC is set on RSS leading client (fp[0]) */
12069 return (bxe_set_mac_one(sc, sc->link_params.mac_addr,
12070 &sc->sp_objs->mac_obj,
12071 set, ECORE_ETH_MAC, &ramrod_flags));
12076 bxe_update_max_mf_config(struct bxe_softc *sc,
12079 /* load old values */
12080 uint32_t mf_cfg = sc->devinfo.mf_info.mf_config[SC_VN(sc)];
12082 if (value != bxe_extract_max_cfg(sc, mf_cfg)) {
12083 /* leave all but MAX value */
12084 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
12086 /* set new MAX value */
12087 mf_cfg |= ((value << FUNC_MF_CFG_MAX_BW_SHIFT) &
12088 FUNC_MF_CFG_MAX_BW_MASK);
12090 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
12096 bxe_get_cur_phy_idx(struct bxe_softc *sc)
12098 uint32_t sel_phy_idx = 0;
12100 if (sc->link_params.num_phys <= 1) {
12101 return (ELINK_INT_PHY);
12104 if (sc->link_vars.link_up) {
12105 sel_phy_idx = ELINK_EXT_PHY1;
12106 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */
12107 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
12108 (sc->link_params.phy[ELINK_EXT_PHY2].supported &
12109 ELINK_SUPPORTED_FIBRE))
12110 sel_phy_idx = ELINK_EXT_PHY2;
12112 switch (elink_phy_selection(&sc->link_params)) {
12113 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
12114 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12115 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12116 sel_phy_idx = ELINK_EXT_PHY1;
12118 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12119 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12120 sel_phy_idx = ELINK_EXT_PHY2;
12125 return (sel_phy_idx);
12129 bxe_get_link_cfg_idx(struct bxe_softc *sc)
12131 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc);
12134 * The selected activated PHY is always after swapping (in case PHY
12135 * swapping is enabled). So when swapping is enabled, we need to reverse
12136 * the configuration
12139 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
12140 if (sel_phy_idx == ELINK_EXT_PHY1)
12141 sel_phy_idx = ELINK_EXT_PHY2;
12142 else if (sel_phy_idx == ELINK_EXT_PHY2)
12143 sel_phy_idx = ELINK_EXT_PHY1;
12146 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx));
12150 bxe_set_requested_fc(struct bxe_softc *sc)
12153 * Initialize link parameters structure variables
12154 * It is recommended to turn off RX FC for jumbo frames
12155 * for better performance
12157 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) {
12158 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX;
12160 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH;
12165 bxe_calc_fc_adv(struct bxe_softc *sc)
12167 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc);
12168 switch (sc->link_vars.ieee_fc &
12169 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
12170 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
12172 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
12176 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
12177 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
12181 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
12182 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
12188 bxe_get_mf_speed(struct bxe_softc *sc)
12190 uint16_t line_speed = sc->link_vars.line_speed;
12193 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]);
12195 /* calculate the current MAX line speed limit for the MF devices */
12196 if (IS_MF_SI(sc)) {
12197 line_speed = (line_speed * maxCfg) / 100;
12198 } else { /* SD mode */
12199 uint16_t vn_max_rate = maxCfg * 100;
12201 if (vn_max_rate < line_speed) {
12202 line_speed = vn_max_rate;
12207 return (line_speed);
12211 bxe_fill_report_data(struct bxe_softc *sc,
12212 struct bxe_link_report_data *data)
12214 uint16_t line_speed = bxe_get_mf_speed(sc);
12216 memset(data, 0, sizeof(*data));
12218 /* fill the report data with the effective line speed */
12219 data->line_speed = line_speed;
12222 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) {
12223 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags);
12227 if (sc->link_vars.duplex == DUPLEX_FULL) {
12228 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags);
12231 /* Rx Flow Control is ON */
12232 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {
12233 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
12236 /* Tx Flow Control is ON */
12237 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {
12238 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
12242 /* report link status to OS, should be called under phy_lock */
12244 bxe_link_report_locked(struct bxe_softc *sc)
12246 struct bxe_link_report_data cur_data;
12248 /* reread mf_cfg */
12249 if (IS_PF(sc) && !CHIP_IS_E1(sc)) {
12250 bxe_read_mf_cfg(sc);
12253 /* Read the current link report info */
12254 bxe_fill_report_data(sc, &cur_data);
12256 /* Don't report link down or exactly the same link status twice */
12257 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||
12258 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12259 &sc->last_reported_link.link_report_flags) &&
12260 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12261 &cur_data.link_report_flags))) {
12267 /* report new link params and remember the state for the next time */
12268 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));
12270 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN,
12271 &cur_data.link_report_flags)) {
12272 if_link_state_change(sc->ifnet, LINK_STATE_DOWN);
12273 BLOGI(sc, "NIC Link is Down\n");
12275 const char *duplex;
12278 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX,
12279 &cur_data.link_report_flags)) {
12286 * Handle the FC at the end so that only these flags would be
12287 * possibly set. This way we may easily check if there is no FC
12290 if (cur_data.link_report_flags) {
12291 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12292 &cur_data.link_report_flags) &&
12293 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12294 &cur_data.link_report_flags)) {
12295 flow = "ON - receive & transmit";
12296 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12297 &cur_data.link_report_flags) &&
12298 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12299 &cur_data.link_report_flags)) {
12300 flow = "ON - receive";
12301 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON,
12302 &cur_data.link_report_flags) &&
12303 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON,
12304 &cur_data.link_report_flags)) {
12305 flow = "ON - transmit";
12307 flow = "none"; /* possible? */
12313 if_link_state_change(sc->ifnet, LINK_STATE_UP);
12314 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
12315 cur_data.line_speed, duplex, flow);
12320 bxe_link_report(struct bxe_softc *sc)
12323 bxe_link_report_locked(sc);
12324 BXE_PHY_UNLOCK(sc);
12328 bxe_link_status_update(struct bxe_softc *sc)
12330 if (sc->state != BXE_STATE_OPEN) {
12335 /* read updated dcb configuration */
12337 bxe_dcbx_pmf_update(sc);
12340 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) {
12341 elink_link_status_update(&sc->link_params, &sc->link_vars);
12343 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half |
12344 ELINK_SUPPORTED_10baseT_Full |
12345 ELINK_SUPPORTED_100baseT_Half |
12346 ELINK_SUPPORTED_100baseT_Full |
12347 ELINK_SUPPORTED_1000baseT_Full |
12348 ELINK_SUPPORTED_2500baseX_Full |
12349 ELINK_SUPPORTED_10000baseT_Full |
12350 ELINK_SUPPORTED_TP |
12351 ELINK_SUPPORTED_FIBRE |
12352 ELINK_SUPPORTED_Autoneg |
12353 ELINK_SUPPORTED_Pause |
12354 ELINK_SUPPORTED_Asym_Pause);
12355 sc->port.advertising[0] = sc->port.supported[0];
12357 sc->link_params.sc = sc;
12358 sc->link_params.port = SC_PORT(sc);
12359 sc->link_params.req_duplex[0] = DUPLEX_FULL;
12360 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE;
12361 sc->link_params.req_line_speed[0] = SPEED_10000;
12362 sc->link_params.speed_cap_mask[0] = 0x7f0000;
12363 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G;
12365 if (CHIP_REV_IS_FPGA(sc)) {
12366 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC;
12367 sc->link_vars.line_speed = ELINK_SPEED_1000;
12368 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
12369 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD);
12371 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC;
12372 sc->link_vars.line_speed = ELINK_SPEED_10000;
12373 sc->link_vars.link_status = (LINK_STATUS_LINK_UP |
12374 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
12377 sc->link_vars.link_up = 1;
12379 sc->link_vars.duplex = DUPLEX_FULL;
12380 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE;
12383 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0);
12384 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12385 bxe_link_report(sc);
12390 if (sc->link_vars.link_up) {
12391 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12393 bxe_stats_handle(sc, STATS_EVENT_STOP);
12395 bxe_link_report(sc);
12397 bxe_link_report(sc);
12398 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12403 bxe_initial_phy_init(struct bxe_softc *sc,
12406 int rc, cfg_idx = bxe_get_link_cfg_idx(sc);
12407 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx];
12408 struct elink_params *lp = &sc->link_params;
12410 bxe_set_requested_fc(sc);
12412 if (CHIP_REV_IS_SLOW(sc)) {
12413 uint32_t bond = CHIP_BOND_ID(sc);
12416 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) {
12417 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
12418 } else if (bond & 0x4) {
12419 if (CHIP_IS_E3(sc)) {
12420 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC;
12422 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC;
12424 } else if (bond & 0x8) {
12425 if (CHIP_IS_E3(sc)) {
12426 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC;
12428 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
12432 /* disable EMAC for E3 and above */
12434 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC;
12437 sc->link_params.feature_config_flags |= feat;
12442 if (load_mode == LOAD_DIAG) {
12443 lp->loopback_mode = ELINK_LOOPBACK_XGXS;
12444 /* Prefer doing PHY loopback at 10G speed, if possible */
12445 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) {
12446 if (lp->speed_cap_mask[cfg_idx] &
12447 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
12448 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000;
12450 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000;
12455 if (load_mode == LOAD_LOOPBACK_EXT) {
12456 lp->loopback_mode = ELINK_LOOPBACK_EXT;
12459 rc = elink_phy_init(&sc->link_params, &sc->link_vars);
12461 BXE_PHY_UNLOCK(sc);
12463 bxe_calc_fc_adv(sc);
12465 if (sc->link_vars.link_up) {
12466 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
12467 bxe_link_report(sc);
12470 if (!CHIP_REV_IS_SLOW(sc)) {
12471 bxe_periodic_start(sc);
12474 sc->link_params.req_line_speed[cfg_idx] = req_line_speed;
12478 /* must be called under IF_ADDR_LOCK */
12480 bxe_init_mcast_macs_list(struct bxe_softc *sc,
12481 struct ecore_mcast_ramrod_params *p)
12483 struct ifnet *ifp = sc->ifnet;
12485 struct ifmultiaddr *ifma;
12486 struct ecore_mcast_list_elem *mc_mac;
12488 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12489 if (ifma->ifma_addr->sa_family != AF_LINK) {
12496 ECORE_LIST_INIT(&p->mcast_list);
12497 p->mcast_list_len = 0;
12503 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF,
12504 (M_NOWAIT | M_ZERO));
12506 BLOGE(sc, "Failed to allocate temp mcast list\n");
12510 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
12511 if (ifma->ifma_addr->sa_family != AF_LINK) {
12515 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
12516 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list);
12518 BLOGD(sc, DBG_LOAD,
12519 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X\n",
12520 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2],
12521 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5]);
12526 p->mcast_list_len = mc_count;
12532 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p)
12534 struct ecore_mcast_list_elem *mc_mac =
12535 ECORE_LIST_FIRST_ENTRY(&p->mcast_list,
12536 struct ecore_mcast_list_elem,
12540 /* only a single free as all mc_macs are in the same heap array */
12541 free(mc_mac, M_DEVBUF);
12546 bxe_set_mc_list(struct bxe_softc *sc)
12548 struct ecore_mcast_ramrod_params rparam = { NULL };
12551 rparam.mcast_obj = &sc->mcast_obj;
12553 BXE_MCAST_LOCK(sc);
12555 /* first, clear all configured multicast MACs */
12556 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);
12558 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc);
12562 /* configure a new MACs list */
12563 rc = bxe_init_mcast_macs_list(sc, &rparam);
12565 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc);
12566 BXE_MCAST_UNLOCK(sc);
12570 /* Now add the new MACs */
12571 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD);
12573 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc);
12576 bxe_free_mcast_macs_list(&rparam);
12578 BXE_MCAST_UNLOCK(sc);
12584 bxe_set_uc_list(struct bxe_softc *sc)
12586 struct ifnet *ifp = sc->ifnet;
12587 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;
12588 struct ifaddr *ifa;
12589 unsigned long ramrod_flags = 0;
12592 #if __FreeBSD_version < 800000
12595 if_addr_rlock(ifp);
12598 /* first schedule a cleanup up of old configuration */
12599 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE);
12601 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc);
12602 #if __FreeBSD_version < 800000
12603 IF_ADDR_UNLOCK(ifp);
12605 if_addr_runlock(ifp);
12610 ifa = ifp->if_addr;
12612 if (ifa->ifa_addr->sa_family != AF_LINK) {
12613 ifa = TAILQ_NEXT(ifa, ifa_link);
12617 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr),
12618 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags);
12619 if (rc == -EEXIST) {
12620 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n");
12621 /* do not treat adding same MAC as an error */
12623 } else if (rc < 0) {
12624 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc);
12625 #if __FreeBSD_version < 800000
12626 IF_ADDR_UNLOCK(ifp);
12628 if_addr_runlock(ifp);
12633 ifa = TAILQ_NEXT(ifa, ifa_link);
12636 #if __FreeBSD_version < 800000
12637 IF_ADDR_UNLOCK(ifp);
12639 if_addr_runlock(ifp);
12642 /* Execute the pending commands */
12643 bit_set(&ramrod_flags, RAMROD_CONT);
12644 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */,
12645 ECORE_UC_LIST_MAC, &ramrod_flags));
12649 bxe_handle_rx_mode_tq(void *context,
12652 struct bxe_softc *sc = (struct bxe_softc *)context;
12653 struct ifnet *ifp = sc->ifnet;
12654 uint32_t rx_mode = BXE_RX_MODE_NORMAL;
12658 if (sc->state != BXE_STATE_OPEN) {
12659 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state);
12660 BXE_CORE_UNLOCK(sc);
12664 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags);
12666 if (ifp->if_flags & IFF_PROMISC) {
12667 rx_mode = BXE_RX_MODE_PROMISC;
12668 } else if ((ifp->if_flags & IFF_ALLMULTI) ||
12669 ((ifp->if_amcount > BXE_MAX_MULTICAST) &&
12671 rx_mode = BXE_RX_MODE_ALLMULTI;
12674 /* some multicasts */
12675 if (bxe_set_mc_list(sc) < 0) {
12676 rx_mode = BXE_RX_MODE_ALLMULTI;
12678 if (bxe_set_uc_list(sc) < 0) {
12679 rx_mode = BXE_RX_MODE_PROMISC;
12685 * Configuring mcast to a VF involves sleeping (when we
12686 * wait for the PF's response). Since this function is
12687 * called from a non sleepable context we must schedule
12688 * a work item for this purpose
12690 bxe_set_bit(BXE_SP_RTNL_VFPF_MCAST, &sc->sp_rtnl_state);
12691 schedule_delayed_work(&sc->sp_rtnl_task, 0);
12696 sc->rx_mode = rx_mode;
12698 /* schedule the rx_mode command */
12699 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {
12700 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n");
12701 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);
12702 BXE_CORE_UNLOCK(sc);
12707 bxe_set_storm_rx_mode(sc);
12712 * Configuring mcast to a VF involves sleeping (when we
12713 * wait for the PF's response). Since this function is
12714 * called from a non sleepable context we must schedule
12715 * a work item for this purpose
12717 bxe_set_bit(BXE_SP_RTNL_VFPF_STORM_RX_MODE, &sc->sp_rtnl_state);
12718 schedule_delayed_work(&sc->sp_rtnl_task, 0);
12722 BXE_CORE_UNLOCK(sc);
12726 bxe_set_rx_mode(struct bxe_softc *sc)
12728 taskqueue_enqueue(sc->rx_mode_tq, &sc->rx_mode_tq_task);
12731 /* update flags in shmem */
12733 bxe_update_drv_flags(struct bxe_softc *sc,
12737 uint32_t drv_flags;
12739 if (SHMEM2_HAS(sc, drv_flags)) {
12740 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12741 drv_flags = SHMEM2_RD(sc, drv_flags);
12744 SET_FLAGS(drv_flags, flags);
12746 RESET_FLAGS(drv_flags, flags);
12749 SHMEM2_WR(sc, drv_flags, drv_flags);
12750 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags);
12752 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS);
12756 /* periodic timer callout routine, only runs when the interface is up */
12759 bxe_periodic_callout_func(void *xsc)
12761 struct bxe_softc *sc = (struct bxe_softc *)xsc;
12764 if (!BXE_CORE_TRYLOCK(sc)) {
12765 /* just bail and try again next time */
12767 if ((sc->state == BXE_STATE_OPEN) &&
12768 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12769 /* schedule the next periodic callout */
12770 callout_reset(&sc->periodic_callout, hz,
12771 bxe_periodic_callout_func, sc);
12777 if ((sc->state != BXE_STATE_OPEN) ||
12778 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) {
12779 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state);
12780 BXE_CORE_UNLOCK(sc);
12784 /* Check for TX timeouts on any fastpath. */
12785 FOR_EACH_QUEUE(sc, i) {
12786 if (bxe_watchdog(sc, &sc->fp[i]) != 0) {
12787 /* Ruh-Roh, chip was reset! */
12792 if (!CHIP_REV_IS_SLOW(sc)) {
12794 * This barrier is needed to ensure the ordering between the writing
12795 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and
12796 * the reading here.
12799 if (sc->port.pmf) {
12801 elink_period_func(&sc->link_params, &sc->link_vars);
12802 BXE_PHY_UNLOCK(sc);
12806 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
12807 int mb_idx = SC_FW_MB_IDX(sc);
12808 uint32_t drv_pulse;
12809 uint32_t mcp_pulse;
12811 ++sc->fw_drv_pulse_wr_seq;
12812 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
12814 drv_pulse = sc->fw_drv_pulse_wr_seq;
12817 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) &
12818 MCP_PULSE_SEQ_MASK);
12821 * The delta between driver pulse and mcp response should
12822 * be 1 (before mcp response) or 0 (after mcp response).
12824 if ((drv_pulse != mcp_pulse) &&
12825 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
12826 /* someone lost a heartbeat... */
12827 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
12828 drv_pulse, mcp_pulse);
12832 /* state is BXE_STATE_OPEN */
12833 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
12836 /* sample VF bulletin board for new posts from PF */
12838 bxe_sample_bulletin(sc);
12842 BXE_CORE_UNLOCK(sc);
12844 if ((sc->state == BXE_STATE_OPEN) &&
12845 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) {
12846 /* schedule the next periodic callout */
12847 callout_reset(&sc->periodic_callout, hz,
12848 bxe_periodic_callout_func, sc);
12853 bxe_periodic_start(struct bxe_softc *sc)
12855 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO);
12856 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc);
12860 bxe_periodic_stop(struct bxe_softc *sc)
12862 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP);
12863 callout_drain(&sc->periodic_callout);
12866 /* start the controller */
12867 static __noinline int
12868 bxe_nic_load(struct bxe_softc *sc,
12875 BXE_CORE_LOCK_ASSERT(sc);
12877 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n");
12879 sc->state = BXE_STATE_OPENING_WAITING_LOAD;
12882 /* must be called before memory allocation and HW init */
12883 bxe_ilt_set_info(sc);
12886 sc->last_reported_link_state = LINK_STATE_UNKNOWN;
12888 bxe_set_fp_rx_buf_size(sc);
12890 if (bxe_alloc_fp_buffers(sc) != 0) {
12891 BLOGE(sc, "Failed to allocate fastpath memory\n");
12892 sc->state = BXE_STATE_CLOSED;
12894 goto bxe_nic_load_error0;
12897 if (bxe_alloc_mem(sc) != 0) {
12898 sc->state = BXE_STATE_CLOSED;
12900 goto bxe_nic_load_error0;
12903 if (bxe_alloc_fw_stats_mem(sc) != 0) {
12904 sc->state = BXE_STATE_CLOSED;
12906 goto bxe_nic_load_error0;
12910 /* set pf load just before approaching the MCP */
12911 bxe_set_pf_load(sc);
12913 /* if MCP exists send load request and analyze response */
12914 if (!BXE_NOMCP(sc)) {
12915 /* attempt to load pf */
12916 if (bxe_nic_load_request(sc, &load_code) != 0) {
12917 sc->state = BXE_STATE_CLOSED;
12919 goto bxe_nic_load_error1;
12922 /* what did the MCP say? */
12923 if (bxe_nic_load_analyze_req(sc, load_code) != 0) {
12924 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12925 sc->state = BXE_STATE_CLOSED;
12927 goto bxe_nic_load_error2;
12930 BLOGI(sc, "Device has no MCP!\n");
12931 load_code = bxe_nic_load_no_mcp(sc);
12934 /* mark PMF if applicable */
12935 bxe_nic_load_pmf(sc, load_code);
12937 /* Init Function state controlling object */
12938 bxe_init_func_obj(sc);
12940 /* Initialize HW */
12941 if (bxe_init_hw(sc, load_code) != 0) {
12942 BLOGE(sc, "HW init failed\n");
12943 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12944 sc->state = BXE_STATE_CLOSED;
12946 goto bxe_nic_load_error2;
12950 /* attach interrupts */
12951 if (bxe_interrupt_attach(sc) != 0) {
12952 sc->state = BXE_STATE_CLOSED;
12954 goto bxe_nic_load_error2;
12957 bxe_nic_init(sc, load_code);
12959 /* Init per-function objects */
12962 // XXX bxe_iov_nic_init(sc);
12964 /* set AFEX default VLAN tag to an invalid value */
12965 sc->devinfo.mf_info.afex_def_vlan_tag = -1;
12966 // XXX bxe_nic_load_afex_dcc(sc, load_code);
12968 sc->state = BXE_STATE_OPENING_WAITING_PORT;
12969 rc = bxe_func_start(sc);
12971 BLOGE(sc, "Function start failed!\n");
12972 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12973 sc->state = BXE_STATE_ERROR;
12974 goto bxe_nic_load_error3;
12977 /* send LOAD_DONE command to MCP */
12978 if (!BXE_NOMCP(sc)) {
12979 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0);
12981 BLOGE(sc, "MCP response failure, aborting\n");
12982 sc->state = BXE_STATE_ERROR;
12984 goto bxe_nic_load_error3;
12988 rc = bxe_setup_leading(sc);
12990 BLOGE(sc, "Setup leading failed!\n");
12991 sc->state = BXE_STATE_ERROR;
12992 goto bxe_nic_load_error3;
12995 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) {
12996 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE);
12998 BLOGE(sc, "Queue(%d) setup failed\n", i);
12999 sc->state = BXE_STATE_ERROR;
13000 goto bxe_nic_load_error3;
13004 rc = bxe_init_rss_pf(sc);
13006 BLOGE(sc, "PF RSS init failed\n");
13007 sc->state = BXE_STATE_ERROR;
13008 goto bxe_nic_load_error3;
13014 FOR_EACH_ETH_QUEUE(sc, i) {
13015 rc = bxe_vfpf_setup_q(sc, i);
13017 BLOGE(sc, "Queue(%d) setup failed\n", i);
13018 sc->state = BXE_STATE_ERROR;
13019 goto bxe_nic_load_error3;
13025 /* now when Clients are configured we are ready to work */
13026 sc->state = BXE_STATE_OPEN;
13028 /* Configure a ucast MAC */
13030 rc = bxe_set_eth_mac(sc, TRUE);
13033 else { /* IS_VF(sc) */
13034 rc = bxe_vfpf_set_mac(sc);
13038 BLOGE(sc, "Setting Ethernet MAC failed\n");
13039 sc->state = BXE_STATE_ERROR;
13040 goto bxe_nic_load_error3;
13044 if (IS_PF(sc) && sc->pending_max) {
13046 bxe_update_max_mf_config(sc, sc->pending_max);
13047 sc->pending_max = 0;
13051 if (sc->port.pmf) {
13052 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN);
13054 sc->state = BXE_STATE_ERROR;
13055 goto bxe_nic_load_error3;
13059 sc->link_params.feature_config_flags &=
13060 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN;
13062 /* start fast path */
13064 /* Initialize Rx filter */
13065 bxe_set_rx_mode(sc);
13068 switch (/* XXX load_mode */LOAD_OPEN) {
13074 case LOAD_LOOPBACK_EXT:
13075 sc->state = BXE_STATE_DIAG;
13082 if (sc->port.pmf) {
13083 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0);
13085 bxe_link_status_update(sc);
13088 /* start the periodic timer callout */
13089 bxe_periodic_start(sc);
13091 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) {
13092 /* mark driver is loaded in shmem2 */
13093 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]);
13094 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)],
13096 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
13097 DRV_FLAGS_CAPABILITIES_LOADED_L2));
13100 /* wait for all pending SP commands to complete */
13101 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) {
13102 BLOGE(sc, "Timeout waiting for all SPs to complete!\n");
13103 bxe_periodic_stop(sc);
13104 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE);
13109 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
13110 if (sc->port.pmf && (sc->state != BXE_STATE_DIAG)) {
13111 bxe_dcbx_init(sc, FALSE);
13115 /* Tell the stack the driver is running! */
13116 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING;
13118 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n");
13122 bxe_nic_load_error3:
13125 bxe_int_disable_sync(sc, 1);
13127 /* clean out queued objects */
13128 bxe_squeeze_objects(sc);
13131 bxe_interrupt_detach(sc);
13133 bxe_nic_load_error2:
13135 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
13136 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
13137 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0);
13142 bxe_nic_load_error1:
13144 /* clear pf_load status, as it was already set */
13146 bxe_clear_pf_load(sc);
13149 bxe_nic_load_error0:
13151 bxe_free_fw_stats_mem(sc);
13152 bxe_free_fp_buffers(sc);
13159 bxe_init_locked(struct bxe_softc *sc)
13161 int other_engine = SC_PATH(sc) ? 0 : 1;
13162 uint8_t other_load_status, load_status;
13163 uint8_t global = FALSE;
13166 BXE_CORE_LOCK_ASSERT(sc);
13168 /* check if the driver is already running */
13169 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) {
13170 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n");
13174 bxe_set_power_state(sc, PCI_PM_D0);
13177 * If parity occurred during the unload, then attentions and/or
13178 * RECOVERY_IN_PROGRES may still be set. If so we want the first function
13179 * loaded on the current engine to complete the recovery. Parity recovery
13180 * is only relevant for PF driver.
13183 other_load_status = bxe_get_load_status(sc, other_engine);
13184 load_status = bxe_get_load_status(sc, SC_PATH(sc));
13186 if (!bxe_reset_is_done(sc, SC_PATH(sc)) ||
13187 bxe_chk_parity_attn(sc, &global, TRUE)) {
13190 * If there are attentions and they are in global blocks, set
13191 * the GLOBAL_RESET bit regardless whether it will be this
13192 * function that will complete the recovery or not.
13195 bxe_set_reset_global(sc);
13199 * Only the first function on the current engine should try
13200 * to recover in open. In case of attentions in global blocks
13201 * only the first in the chip should try to recover.
13203 if ((!load_status && (!global || !other_load_status)) &&
13204 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) {
13205 BLOGI(sc, "Recovered during init\n");
13209 /* recovery has failed... */
13210 bxe_set_power_state(sc, PCI_PM_D3hot);
13211 sc->recovery_state = BXE_RECOVERY_FAILED;
13213 BLOGE(sc, "Recovery flow hasn't properly "
13214 "completed yet, try again later. "
13215 "If you still see this message after a "
13216 "few retries then power cycle is required.\n");
13219 goto bxe_init_locked_done;
13224 sc->recovery_state = BXE_RECOVERY_DONE;
13226 rc = bxe_nic_load(sc, LOAD_OPEN);
13228 bxe_init_locked_done:
13231 /* Tell the stack the driver is NOT running! */
13232 BLOGE(sc, "Initialization failed, "
13233 "stack notified driver is NOT running!\n");
13234 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING;
13241 bxe_stop_locked(struct bxe_softc *sc)
13243 BXE_CORE_LOCK_ASSERT(sc);
13244 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE));
13248 * Handles controller initialization when called from an unlocked routine.
13249 * ifconfig calls this function.
13255 bxe_init(void *xsc)
13257 struct bxe_softc *sc = (struct bxe_softc *)xsc;
13260 bxe_init_locked(sc);
13261 BXE_CORE_UNLOCK(sc);
13265 bxe_init_ifnet(struct bxe_softc *sc)
13269 /* ifconfig entrypoint for media type/status reporting */
13270 ifmedia_init(&sc->ifmedia, IFM_IMASK,
13271 bxe_ifmedia_update,
13272 bxe_ifmedia_status);
13274 /* set the default interface values */
13275 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL);
13276 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL);
13277 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO));
13279 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */
13281 /* allocate the ifnet structure */
13282 if ((ifp = if_alloc(IFT_ETHER)) == NULL) {
13283 BLOGE(sc, "Interface allocation failed!\n");
13287 ifp->if_softc = sc;
13288 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
13289 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
13290 ifp->if_ioctl = bxe_ioctl;
13291 ifp->if_start = bxe_tx_start;
13292 #if __FreeBSD_version >= 800000
13293 ifp->if_transmit = bxe_tx_mq_start;
13294 ifp->if_qflush = bxe_mq_flush;
13299 ifp->if_init = bxe_init;
13300 ifp->if_mtu = sc->mtu;
13301 ifp->if_hwassist = (CSUM_IP |
13307 ifp->if_capabilities =
13308 #if __FreeBSD_version < 700000
13310 IFCAP_VLAN_HWTAGGING |
13316 IFCAP_VLAN_HWTAGGING |
13318 IFCAP_VLAN_HWFILTER |
13319 IFCAP_VLAN_HWCSUM |
13327 ifp->if_capenable = ifp->if_capabilities;
13328 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */
13329 #if __FreeBSD_version < 1000025
13330 ifp->if_baudrate = 1000000000;
13332 if_initbaudrate(ifp, IF_Gbps(10));
13334 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
13336 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
13337 IFQ_SET_READY(&ifp->if_snd);
13341 /* attach to the Ethernet interface list */
13342 ether_ifattach(ifp, sc->link_params.mac_addr);
13348 bxe_deallocate_bars(struct bxe_softc *sc)
13352 for (i = 0; i < MAX_BARS; i++) {
13353 if (sc->bar[i].resource != NULL) {
13354 bus_release_resource(sc->dev,
13357 sc->bar[i].resource);
13358 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n",
13365 bxe_allocate_bars(struct bxe_softc *sc)
13370 memset(sc->bar, 0, sizeof(sc->bar));
13372 for (i = 0; i < MAX_BARS; i++) {
13374 /* memory resources reside at BARs 0, 2, 4 */
13375 /* Run `pciconf -lb` to see mappings */
13376 if ((i != 0) && (i != 2) && (i != 4)) {
13380 sc->bar[i].rid = PCIR_BAR(i);
13384 flags |= RF_SHAREABLE;
13387 if ((sc->bar[i].resource =
13388 bus_alloc_resource_any(sc->dev,
13393 /* BAR4 doesn't exist for E1 */
13394 BLOGE(sc, "PCI BAR%d [%02x] memory allocation failed\n",
13400 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource);
13401 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource);
13402 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource);
13404 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n",
13406 (void *)rman_get_start(sc->bar[i].resource),
13407 (void *)rman_get_end(sc->bar[i].resource),
13408 rman_get_size(sc->bar[i].resource),
13409 (void *)sc->bar[i].kva);
13416 bxe_get_function_num(struct bxe_softc *sc)
13421 * Read the ME register to get the function number. The ME register
13422 * holds the relative-function number and absolute-function number. The
13423 * absolute-function number appears only in E2 and above. Before that
13424 * these bits always contained zero, therefore we cannot blindly use them.
13427 val = REG_RD(sc, BAR_ME_REGISTER);
13430 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT);
13432 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1;
13434 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13435 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id);
13437 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id);
13440 BLOGD(sc, DBG_LOAD,
13441 "Relative function %d, Absolute function %d, Path %d\n",
13442 sc->pfunc_rel, sc->pfunc_abs, sc->path_id);
13446 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc)
13448 uint32_t shmem2_size;
13450 uint32_t mf_cfg_offset_value;
13453 offset = (SHMEM_RD(sc, func_mb) +
13454 (MAX_FUNC_NUM * sizeof(struct drv_func_mb)));
13457 if (sc->devinfo.shmem2_base != 0) {
13458 shmem2_size = SHMEM2_RD(sc, size);
13459 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) {
13460 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr);
13461 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) {
13462 offset = mf_cfg_offset_value;
13471 bxe_pcie_capability_read(struct bxe_softc *sc,
13477 /* ensure PCIe capability is enabled */
13478 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) {
13479 if (pcie_reg != 0) {
13480 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg);
13481 return (pci_read_config(sc->dev, (pcie_reg + reg), width));
13485 BLOGE(sc, "PCIe capability NOT FOUND!!!\n");
13491 bxe_is_pcie_pending(struct bxe_softc *sc)
13493 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) &
13494 PCIM_EXP_STA_TRANSACTION_PND);
13498 * Walk the PCI capabiites list for the device to find what features are
13499 * supported. These capabilites may be enabled/disabled by firmware so it's
13500 * best to walk the list rather than make assumptions.
13503 bxe_probe_pci_caps(struct bxe_softc *sc)
13505 uint16_t link_status;
13508 /* check if PCI Power Management is enabled */
13509 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) {
13511 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg);
13513 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG;
13514 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg;
13518 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2);
13520 /* handle PCIe 2.0 workarounds for 57710 */
13521 if (CHIP_IS_E1(sc)) {
13522 /* workaround for 57710 errata E4_57710_27462 */
13523 sc->devinfo.pcie_link_speed =
13524 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
13526 /* workaround for 57710 errata E4_57710_27488 */
13527 sc->devinfo.pcie_link_width =
13528 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13529 if (sc->devinfo.pcie_link_speed > 1) {
13530 sc->devinfo.pcie_link_width =
13531 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1;
13534 sc->devinfo.pcie_link_speed =
13535 (link_status & PCIM_LINK_STA_SPEED);
13536 sc->devinfo.pcie_link_width =
13537 ((link_status & PCIM_LINK_STA_WIDTH) >> 4);
13540 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n",
13541 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width);
13543 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
13544 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg;
13546 /* check if MSI capability is enabled */
13547 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) {
13549 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg);
13551 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG;
13552 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg;
13556 /* check if MSI-X capability is enabled */
13557 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) {
13559 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg);
13561 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
13562 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg;
13568 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc)
13570 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13573 /* get the outer vlan if we're in switch-dependent mode */
13575 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13576 mf_info->ext_id = (uint16_t)val;
13578 mf_info->multi_vnics_mode = 1;
13580 if (!VALID_OVLAN(mf_info->ext_id)) {
13581 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id);
13585 /* get the capabilities */
13586 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13587 FUNC_MF_CFG_PROTOCOL_ISCSI) {
13588 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI;
13589 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) ==
13590 FUNC_MF_CFG_PROTOCOL_FCOE) {
13591 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE;
13593 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET;
13596 mf_info->vnics_per_port =
13597 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13603 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc)
13605 uint32_t retval = 0;
13608 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13610 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) {
13611 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) {
13612 retval |= MF_PROTO_SUPPORT_ETHERNET;
13614 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
13615 retval |= MF_PROTO_SUPPORT_ISCSI;
13617 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
13618 retval |= MF_PROTO_SUPPORT_FCOE;
13626 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc)
13628 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13632 * There is no outer vlan if we're in switch-independent mode.
13633 * If the mac is valid then assume multi-function.
13636 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg);
13638 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0);
13640 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13642 mf_info->vnics_per_port =
13643 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13649 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc)
13651 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13652 uint32_t e1hov_tag;
13653 uint32_t func_config;
13654 uint32_t niv_config;
13656 mf_info->multi_vnics_mode = 1;
13658 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13659 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13660 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config);
13663 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >>
13664 FUNC_MF_CFG_E1HOV_TAG_SHIFT);
13666 mf_info->default_vlan =
13667 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >>
13668 FUNC_MF_CFG_AFEX_VLAN_SHIFT);
13670 mf_info->niv_allowed_priorities =
13671 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
13672 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT);
13674 mf_info->niv_default_cos =
13675 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
13676 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT);
13678 mf_info->afex_vlan_mode =
13679 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
13680 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT);
13682 mf_info->niv_mba_enabled =
13683 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >>
13684 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT);
13686 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc);
13688 mf_info->vnics_per_port =
13689 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4;
13695 bxe_check_valid_mf_cfg(struct bxe_softc *sc)
13697 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13704 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n",
13706 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n",
13707 mf_info->mf_config[SC_VN(sc)]);
13708 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n",
13709 mf_info->multi_vnics_mode);
13710 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n",
13711 mf_info->vnics_per_port);
13712 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n",
13714 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n",
13715 mf_info->min_bw[0], mf_info->min_bw[1],
13716 mf_info->min_bw[2], mf_info->min_bw[3]);
13717 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n",
13718 mf_info->max_bw[0], mf_info->max_bw[1],
13719 mf_info->max_bw[2], mf_info->max_bw[3]);
13720 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n",
13723 /* various MF mode sanity checks... */
13725 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) {
13726 BLOGE(sc, "Enumerated function %d is marked as hidden\n",
13731 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) {
13732 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n",
13733 mf_info->vnics_per_port, mf_info->multi_vnics_mode);
13737 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13738 /* vnic id > 0 must have valid ovlan in switch-dependent mode */
13739 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) {
13740 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n",
13741 SC_VN(sc), OVLAN(sc));
13745 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) {
13746 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n",
13747 mf_info->multi_vnics_mode, OVLAN(sc));
13752 * Verify all functions are either MF or SF mode. If MF, make sure
13753 * sure that all non-hidden functions have a valid ovlan. If SF,
13754 * make sure that all non-hidden functions have an invalid ovlan.
13756 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13757 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13758 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13759 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13760 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) ||
13761 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) {
13762 BLOGE(sc, "mf_mode=SD function %d MF config "
13763 "mismatch, multi_vnics_mode=%d ovlan=%d\n",
13764 i, mf_info->multi_vnics_mode, ovlan1);
13769 /* Verify all funcs on the same port each have a different ovlan. */
13770 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13771 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config);
13772 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag);
13773 /* iterate from the next function on the port to the max func */
13774 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) {
13775 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config);
13776 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag);
13777 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) &&
13778 VALID_OVLAN(ovlan1) &&
13779 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) &&
13780 VALID_OVLAN(ovlan2) &&
13781 (ovlan1 == ovlan2)) {
13782 BLOGE(sc, "mf_mode=SD functions %d and %d "
13783 "have the same ovlan (%d)\n",
13789 } /* MULTI_FUNCTION_SD */
13795 bxe_get_mf_cfg_info(struct bxe_softc *sc)
13797 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info;
13798 uint32_t val, mac_upper;
13801 /* initialize mf_info defaults */
13802 mf_info->vnics_per_port = 1;
13803 mf_info->multi_vnics_mode = FALSE;
13804 mf_info->path_has_ovlan = FALSE;
13805 mf_info->mf_mode = SINGLE_FUNCTION;
13807 if (!CHIP_IS_MF_CAP(sc)) {
13811 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) {
13812 BLOGE(sc, "Invalid mf_cfg_base!\n");
13816 /* get the MF mode (switch dependent / independent / single-function) */
13818 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13820 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)
13822 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
13824 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13826 /* check for legal upper mac bytes */
13827 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) {
13828 mf_info->mf_mode = MULTI_FUNCTION_SI;
13830 BLOGE(sc, "Invalid config for Switch Independent mode\n");
13835 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
13836 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4:
13838 /* get outer vlan configuration */
13839 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag);
13841 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) !=
13842 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
13843 mf_info->mf_mode = MULTI_FUNCTION_SD;
13845 BLOGE(sc, "Invalid config for Switch Dependent mode\n");
13850 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
13852 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */
13855 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
13858 * Mark MF mode as NIV if MCP version includes NPAR-SD support
13859 * and the MAC address is valid.
13861 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
13863 if ((SHMEM2_HAS(sc, afex_driver_support)) &&
13864 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) {
13865 mf_info->mf_mode = MULTI_FUNCTION_AFEX;
13867 BLOGE(sc, "Invalid config for AFEX mode\n");
13874 BLOGE(sc, "Unknown MF mode (0x%08x)\n",
13875 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK));
13880 /* set path mf_mode (which could be different than function mf_mode) */
13881 if (mf_info->mf_mode == MULTI_FUNCTION_SD) {
13882 mf_info->path_has_ovlan = TRUE;
13883 } else if (mf_info->mf_mode == SINGLE_FUNCTION) {
13885 * Decide on path multi vnics mode. If we're not in MF mode and in
13886 * 4-port mode, this is good enough to check vnic-0 of the other port
13889 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) {
13890 uint8_t other_port = !(PORT_ID(sc) & 1);
13891 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port));
13893 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag);
13895 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0;
13899 if (mf_info->mf_mode == SINGLE_FUNCTION) {
13900 /* invalid MF config */
13901 if (SC_VN(sc) >= 1) {
13902 BLOGE(sc, "VNIC ID >= 1 in SF mode\n");
13909 /* get the MF configuration */
13910 mf_info->mf_config[SC_VN(sc)] =
13911 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config);
13913 switch(mf_info->mf_mode)
13915 case MULTI_FUNCTION_SD:
13917 bxe_get_shmem_mf_cfg_info_sd(sc);
13920 case MULTI_FUNCTION_SI:
13922 bxe_get_shmem_mf_cfg_info_si(sc);
13925 case MULTI_FUNCTION_AFEX:
13927 bxe_get_shmem_mf_cfg_info_niv(sc);
13932 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n",
13937 /* get the congestion management parameters */
13940 FOREACH_ABS_FUNC_IN_PORT(sc, i) {
13941 /* get min/max bw */
13942 val = MFCFG_RD(sc, func_mf_config[i].config);
13943 mf_info->min_bw[vnic] =
13944 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT);
13945 mf_info->max_bw[vnic] =
13946 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT);
13950 return (bxe_check_valid_mf_cfg(sc));
13954 bxe_get_shmem_info(struct bxe_softc *sc)
13957 uint32_t mac_hi, mac_lo, val;
13959 port = SC_PORT(sc);
13960 mac_hi = mac_lo = 0;
13962 sc->link_params.sc = sc;
13963 sc->link_params.port = port;
13965 /* get the hardware config info */
13966 sc->devinfo.hw_config =
13967 SHMEM_RD(sc, dev_info.shared_hw_config.config);
13968 sc->devinfo.hw_config2 =
13969 SHMEM_RD(sc, dev_info.shared_hw_config.config2);
13971 sc->link_params.hw_led_mode =
13972 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >>
13973 SHARED_HW_CFG_LED_MODE_SHIFT);
13975 /* get the port feature config */
13977 SHMEM_RD(sc, dev_info.port_feature_config[port].config),
13979 /* get the link params */
13980 sc->link_params.speed_cap_mask[0] =
13981 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
13982 sc->link_params.speed_cap_mask[1] =
13983 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2);
13985 /* get the lane config */
13986 sc->link_params.lane_config =
13987 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
13989 /* get the link config */
13990 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
13991 sc->port.link_config[ELINK_INT_PHY] = val;
13992 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK);
13993 sc->port.link_config[ELINK_EXT_PHY1] =
13994 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2);
13996 /* get the override preemphasis flag and enable it or turn it off */
13997 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
13998 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) {
13999 sc->link_params.feature_config_flags |=
14000 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
14002 sc->link_params.feature_config_flags &=
14003 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
14006 /* get the initial value of the link params */
14007 sc->link_params.multi_phy_config =
14008 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config);
14010 /* get external phy info */
14011 sc->port.ext_phy_config =
14012 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
14014 /* get the multifunction configuration */
14015 bxe_get_mf_cfg_info(sc);
14017 /* get the mac address */
14019 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper);
14020 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower);
14022 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
14023 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
14026 if ((mac_lo == 0) && (mac_hi == 0)) {
14027 *sc->mac_addr_str = 0;
14028 BLOGE(sc, "No Ethernet address programmed!\n");
14030 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8);
14031 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi);
14032 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24);
14033 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16);
14034 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8);
14035 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo);
14036 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str),
14037 "%02x:%02x:%02x:%02x:%02x:%02x",
14038 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1],
14039 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3],
14040 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]);
14041 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str);
14046 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
14047 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE)) {
14048 sc->flags |= BXE_NO_ISCSI;
14051 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
14052 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI)) {
14053 sc->flags |= BXE_NO_FCOE_FLAG;
14061 bxe_get_tunable_params(struct bxe_softc *sc)
14063 /* sanity checks */
14065 if ((bxe_interrupt_mode != INTR_MODE_INTX) &&
14066 (bxe_interrupt_mode != INTR_MODE_MSI) &&
14067 (bxe_interrupt_mode != INTR_MODE_MSIX)) {
14068 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode);
14069 bxe_interrupt_mode = INTR_MODE_MSIX;
14072 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) {
14073 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count);
14074 bxe_queue_count = 0;
14077 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) {
14078 if (bxe_max_rx_bufs == 0) {
14079 bxe_max_rx_bufs = RX_BD_USABLE;
14081 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs);
14082 bxe_max_rx_bufs = 2048;
14086 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) {
14087 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks);
14088 bxe_hc_rx_ticks = 25;
14091 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) {
14092 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks);
14093 bxe_hc_tx_ticks = 50;
14096 if (bxe_max_aggregation_size == 0) {
14097 bxe_max_aggregation_size = TPA_AGG_SIZE;
14100 if (bxe_max_aggregation_size > 0xffff) {
14101 BLOGW(sc, "invalid max_aggregation_size (%d)\n",
14102 bxe_max_aggregation_size);
14103 bxe_max_aggregation_size = TPA_AGG_SIZE;
14106 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) {
14107 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs);
14111 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) {
14112 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen);
14113 bxe_autogreeen = 0;
14116 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) {
14117 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss);
14121 /* pull in user settings */
14123 sc->interrupt_mode = bxe_interrupt_mode;
14124 sc->max_rx_bufs = bxe_max_rx_bufs;
14125 sc->hc_rx_ticks = bxe_hc_rx_ticks;
14126 sc->hc_tx_ticks = bxe_hc_tx_ticks;
14127 sc->max_aggregation_size = bxe_max_aggregation_size;
14128 sc->mrrs = bxe_mrrs;
14129 sc->autogreeen = bxe_autogreeen;
14130 sc->udp_rss = bxe_udp_rss;
14132 if (bxe_interrupt_mode == INTR_MODE_INTX) {
14133 sc->num_queues = 1;
14134 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */
14136 min((bxe_queue_count ? bxe_queue_count : mp_ncpus),
14138 if (sc->num_queues > mp_ncpus) {
14139 sc->num_queues = mp_ncpus;
14143 BLOGD(sc, DBG_LOAD,
14146 "interrupt_mode=%d "
14151 "max_aggregation_size=%d "
14156 sc->interrupt_mode,
14161 sc->max_aggregation_size,
14168 bxe_media_detect(struct bxe_softc *sc)
14170 uint32_t phy_idx = bxe_get_cur_phy_idx(sc);
14171 switch (sc->link_params.phy[phy_idx].media_type) {
14172 case ELINK_ETH_PHY_SFPP_10G_FIBER:
14173 case ELINK_ETH_PHY_XFP_FIBER:
14174 BLOGI(sc, "Found 10Gb Fiber media.\n");
14175 sc->media = IFM_10G_SR;
14177 case ELINK_ETH_PHY_SFP_1G_FIBER:
14178 BLOGI(sc, "Found 1Gb Fiber media.\n");
14179 sc->media = IFM_1000_SX;
14181 case ELINK_ETH_PHY_KR:
14182 case ELINK_ETH_PHY_CX4:
14183 BLOGI(sc, "Found 10GBase-CX4 media.\n");
14184 sc->media = IFM_10G_CX4;
14186 case ELINK_ETH_PHY_DA_TWINAX:
14187 BLOGI(sc, "Found 10Gb Twinax media.\n");
14188 sc->media = IFM_10G_TWINAX;
14190 case ELINK_ETH_PHY_BASE_T:
14191 if (sc->link_params.speed_cap_mask[0] &
14192 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
14193 BLOGI(sc, "Found 10GBase-T media.\n");
14194 sc->media = IFM_10G_T;
14196 BLOGI(sc, "Found 1000Base-T media.\n");
14197 sc->media = IFM_1000_T;
14200 case ELINK_ETH_PHY_NOT_PRESENT:
14201 BLOGI(sc, "Media not present.\n");
14204 case ELINK_ETH_PHY_UNSPECIFIED:
14206 BLOGI(sc, "Unknown media!\n");
14212 #define GET_FIELD(value, fname) \
14213 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
14214 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
14215 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
14218 bxe_get_igu_cam_info(struct bxe_softc *sc)
14220 int pfid = SC_FUNC(sc);
14223 uint8_t fid, igu_sb_cnt = 0;
14225 sc->igu_base_sb = 0xff;
14227 if (CHIP_INT_MODE_IS_BC(sc)) {
14228 int vn = SC_VN(sc);
14229 igu_sb_cnt = sc->igu_sb_cnt;
14230 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) *
14232 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x +
14233 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn));
14237 /* IGU in normal mode - read CAM */
14238 for (igu_sb_id = 0;
14239 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
14241 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
14242 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) {
14245 fid = IGU_FID(val);
14246 if ((fid & IGU_FID_ENCODE_IS_PF)) {
14247 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) {
14250 if (IGU_VEC(val) == 0) {
14251 /* default status block */
14252 sc->igu_dsb_id = igu_sb_id;
14254 if (sc->igu_base_sb == 0xff) {
14255 sc->igu_base_sb = igu_sb_id;
14263 * Due to new PF resource allocation by MFW T7.4 and above, it's optional
14264 * that number of CAM entries will not be equal to the value advertised in
14265 * PCI. Driver should use the minimal value of both as the actual status
14268 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt);
14270 if (igu_sb_cnt == 0) {
14271 BLOGE(sc, "CAM configuration error\n");
14279 * Gather various information from the device config space, the device itself,
14280 * shmem, and the user input.
14283 bxe_get_device_info(struct bxe_softc *sc)
14288 /* Get the data for the device */
14289 sc->devinfo.vendor_id = pci_get_vendor(sc->dev);
14290 sc->devinfo.device_id = pci_get_device(sc->dev);
14291 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev);
14292 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev);
14294 /* get the chip revision (chip metal comes from pci config space) */
14295 sc->devinfo.chip_id =
14296 sc->link_params.chip_id =
14297 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
14298 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |
14299 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |
14300 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));
14302 /* force 57811 according to MISC register */
14303 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
14304 if (CHIP_IS_57810(sc)) {
14305 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) |
14306 (sc->devinfo.chip_id & 0x0000ffff));
14307 } else if (CHIP_IS_57810_MF(sc)) {
14308 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) |
14309 (sc->devinfo.chip_id & 0x0000ffff));
14311 sc->devinfo.chip_id |= 0x1;
14314 BLOGD(sc, DBG_LOAD,
14315 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n",
14316 sc->devinfo.chip_id,
14317 ((sc->devinfo.chip_id >> 16) & 0xffff),
14318 ((sc->devinfo.chip_id >> 12) & 0xf),
14319 ((sc->devinfo.chip_id >> 4) & 0xff),
14320 ((sc->devinfo.chip_id >> 0) & 0xf));
14322 val = (REG_RD(sc, 0x2874) & 0x55);
14323 if ((sc->devinfo.chip_id & 0x1) ||
14324 (CHIP_IS_E1(sc) && val) ||
14325 (CHIP_IS_E1H(sc) && (val == 0x55))) {
14326 sc->flags |= BXE_ONE_PORT_FLAG;
14327 BLOGD(sc, DBG_LOAD, "single port device\n");
14330 /* set the doorbell size */
14331 sc->doorbell_size = (1 << BXE_DB_SHIFT);
14333 /* determine whether the device is in 2 port or 4 port mode */
14334 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/
14335 if (CHIP_IS_E2E3(sc)) {
14337 * Read port4mode_en_ovwr[0]:
14338 * If 1, four port mode is in port4mode_en_ovwr[1].
14339 * If 0, four port mode is in port4mode_en[0].
14341 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
14343 val = ((val >> 1) & 1);
14345 val = REG_RD(sc, MISC_REG_PORT4MODE_EN);
14348 sc->devinfo.chip_port_mode =
14349 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE;
14351 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2");
14354 /* get the function and path info for the device */
14355 bxe_get_function_num(sc);
14357 /* get the shared memory base address */
14358 sc->devinfo.shmem_base =
14359 sc->link_params.shmem_base =
14360 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
14361 sc->devinfo.shmem2_base =
14362 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :
14363 MISC_REG_GENERIC_CR_0));
14365 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n",
14366 sc->devinfo.shmem_base, sc->devinfo.shmem2_base);
14368 if (!sc->devinfo.shmem_base) {
14369 /* this should ONLY prevent upcoming shmem reads */
14370 BLOGI(sc, "MCP not active\n");
14371 sc->flags |= BXE_NO_MCP_FLAG;
14375 /* make sure the shared memory contents are valid */
14376 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
14377 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
14378 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
14379 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val);
14382 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val);
14384 /* get the bootcode version */
14385 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev);
14386 snprintf(sc->devinfo.bc_ver_str,
14387 sizeof(sc->devinfo.bc_ver_str),
14389 ((sc->devinfo.bc_ver >> 24) & 0xff),
14390 ((sc->devinfo.bc_ver >> 16) & 0xff),
14391 ((sc->devinfo.bc_ver >> 8) & 0xff));
14392 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str);
14394 /* get the bootcode shmem address */
14395 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc);
14396 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base);
14398 /* clean indirect addresses as they're not used */
14399 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4);
14401 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0);
14402 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0);
14403 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0);
14404 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0);
14405 if (CHIP_IS_E1x(sc)) {
14406 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0);
14407 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0);
14408 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0);
14409 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0);
14413 * Enable internal target-read (in case we are probed after PF
14414 * FLR). Must be done prior to any BAR read access. Only for
14417 if (!CHIP_IS_E1x(sc)) {
14418 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
14422 /* get the nvram size */
14423 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
14424 sc->devinfo.flash_size =
14425 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE));
14426 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size);
14428 /* get PCI capabilites */
14429 bxe_probe_pci_caps(sc);
14431 bxe_set_power_state(sc, PCI_PM_D0);
14433 /* get various configuration parameters from shmem */
14434 bxe_get_shmem_info(sc);
14436 if (sc->devinfo.pcie_msix_cap_reg != 0) {
14437 val = pci_read_config(sc->dev,
14438 (sc->devinfo.pcie_msix_cap_reg +
14441 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE);
14443 sc->igu_sb_cnt = 1;
14446 sc->igu_base_addr = BAR_IGU_INTMEM;
14448 /* initialize IGU parameters */
14449 if (CHIP_IS_E1x(sc)) {
14450 sc->devinfo.int_block = INT_BLOCK_HC;
14451 sc->igu_dsb_id = DEF_SB_IGU_ID;
14452 sc->igu_base_sb = 0;
14454 sc->devinfo.int_block = INT_BLOCK_IGU;
14456 /* do not allow device reset during IGU info preocessing */
14457 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14459 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);
14461 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14464 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n");
14466 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
14467 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val);
14468 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f);
14470 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14475 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {
14476 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n");
14477 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14482 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
14483 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n");
14484 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP;
14486 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n");
14489 rc = bxe_get_igu_cam_info(sc);
14491 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
14499 * Get base FW non-default (fast path) status block ID. This value is
14500 * used to initialize the fw_sb_id saved on the fp/queue structure to
14501 * determine the id used by the FW.
14503 if (CHIP_IS_E1x(sc)) {
14504 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
14507 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of
14508 * the same queue are indicated on the same IGU SB). So we prefer
14509 * FW and IGU SBs to be the same value.
14511 sc->base_fw_ndsb = sc->igu_base_sb;
14514 BLOGD(sc, DBG_LOAD,
14515 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n",
14516 sc->igu_dsb_id, sc->igu_base_sb,
14517 sc->igu_sb_cnt, sc->base_fw_ndsb);
14519 elink_phy_probe(&sc->link_params);
14525 bxe_link_settings_supported(struct bxe_softc *sc,
14526 uint32_t switch_cfg)
14528 uint32_t cfg_size = 0;
14530 uint8_t port = SC_PORT(sc);
14532 /* aggregation of supported attributes of all external phys */
14533 sc->port.supported[0] = 0;
14534 sc->port.supported[1] = 0;
14536 switch (sc->link_params.num_phys) {
14538 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported;
14542 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported;
14546 if (sc->link_params.multi_phy_config &
14547 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
14548 sc->port.supported[1] =
14549 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14550 sc->port.supported[0] =
14551 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14553 sc->port.supported[0] =
14554 sc->link_params.phy[ELINK_EXT_PHY1].supported;
14555 sc->port.supported[1] =
14556 sc->link_params.phy[ELINK_EXT_PHY2].supported;
14562 if (!(sc->port.supported[0] || sc->port.supported[1])) {
14563 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n",
14565 dev_info.port_hw_config[port].external_phy_config),
14567 dev_info.port_hw_config[port].external_phy_config2));
14571 if (CHIP_IS_E3(sc))
14572 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);
14574 switch (switch_cfg) {
14575 case ELINK_SWITCH_CFG_1G:
14576 sc->port.phy_addr =
14577 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
14579 case ELINK_SWITCH_CFG_10G:
14580 sc->port.phy_addr =
14581 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
14584 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n",
14585 sc->port.link_config[0]);
14590 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr);
14592 /* mask what we support according to speed_cap_mask per configuration */
14593 for (idx = 0; idx < cfg_size; idx++) {
14594 if (!(sc->link_params.speed_cap_mask[idx] &
14595 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
14596 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half;
14599 if (!(sc->link_params.speed_cap_mask[idx] &
14600 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) {
14601 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full;
14604 if (!(sc->link_params.speed_cap_mask[idx] &
14605 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
14606 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half;
14609 if (!(sc->link_params.speed_cap_mask[idx] &
14610 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) {
14611 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full;
14614 if (!(sc->link_params.speed_cap_mask[idx] &
14615 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) {
14616 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full;
14619 if (!(sc->link_params.speed_cap_mask[idx] &
14620 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) {
14621 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full;
14624 if (!(sc->link_params.speed_cap_mask[idx] &
14625 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
14626 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full;
14629 if (!(sc->link_params.speed_cap_mask[idx] &
14630 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) {
14631 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full;
14635 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n",
14636 sc->port.supported[0], sc->port.supported[1]);
14640 bxe_link_settings_requested(struct bxe_softc *sc)
14642 uint32_t link_config;
14644 uint32_t cfg_size = 0;
14646 sc->port.advertising[0] = 0;
14647 sc->port.advertising[1] = 0;
14649 switch (sc->link_params.num_phys) {
14659 for (idx = 0; idx < cfg_size; idx++) {
14660 sc->link_params.req_duplex[idx] = DUPLEX_FULL;
14661 link_config = sc->port.link_config[idx];
14663 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
14664 case PORT_FEATURE_LINK_SPEED_AUTO:
14665 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) {
14666 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14667 sc->port.advertising[idx] |= sc->port.supported[idx];
14668 if (sc->link_params.phy[ELINK_EXT_PHY1].type ==
14669 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
14670 sc->port.advertising[idx] |=
14671 (ELINK_SUPPORTED_100baseT_Half |
14672 ELINK_SUPPORTED_100baseT_Full);
14674 /* force 10G, no AN */
14675 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14676 sc->port.advertising[idx] |=
14677 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE);
14682 case PORT_FEATURE_LINK_SPEED_10M_FULL:
14683 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) {
14684 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14685 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full |
14688 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14689 "speed_cap_mask=0x%08x\n",
14690 link_config, sc->link_params.speed_cap_mask[idx]);
14695 case PORT_FEATURE_LINK_SPEED_10M_HALF:
14696 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) {
14697 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10;
14698 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14699 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half |
14702 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14703 "speed_cap_mask=0x%08x\n",
14704 link_config, sc->link_params.speed_cap_mask[idx]);
14709 case PORT_FEATURE_LINK_SPEED_100M_FULL:
14710 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) {
14711 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14712 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full |
14715 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14716 "speed_cap_mask=0x%08x\n",
14717 link_config, sc->link_params.speed_cap_mask[idx]);
14722 case PORT_FEATURE_LINK_SPEED_100M_HALF:
14723 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) {
14724 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100;
14725 sc->link_params.req_duplex[idx] = DUPLEX_HALF;
14726 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half |
14729 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14730 "speed_cap_mask=0x%08x\n",
14731 link_config, sc->link_params.speed_cap_mask[idx]);
14736 case PORT_FEATURE_LINK_SPEED_1G:
14737 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) {
14738 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000;
14739 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full |
14742 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14743 "speed_cap_mask=0x%08x\n",
14744 link_config, sc->link_params.speed_cap_mask[idx]);
14749 case PORT_FEATURE_LINK_SPEED_2_5G:
14750 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) {
14751 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500;
14752 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full |
14755 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14756 "speed_cap_mask=0x%08x\n",
14757 link_config, sc->link_params.speed_cap_mask[idx]);
14762 case PORT_FEATURE_LINK_SPEED_10G_CX4:
14763 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) {
14764 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000;
14765 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full |
14768 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14769 "speed_cap_mask=0x%08x\n",
14770 link_config, sc->link_params.speed_cap_mask[idx]);
14775 case PORT_FEATURE_LINK_SPEED_20G:
14776 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000;
14780 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x "
14781 "speed_cap_mask=0x%08x\n",
14782 link_config, sc->link_params.speed_cap_mask[idx]);
14783 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG;
14784 sc->port.advertising[idx] = sc->port.supported[idx];
14788 sc->link_params.req_flow_ctrl[idx] =
14789 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK);
14791 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) {
14792 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) {
14793 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE;
14795 bxe_set_requested_fc(sc);
14799 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d "
14800 "req_flow_ctrl=0x%x advertising=0x%x\n",
14801 sc->link_params.req_line_speed[idx],
14802 sc->link_params.req_duplex[idx],
14803 sc->link_params.req_flow_ctrl[idx],
14804 sc->port.advertising[idx]);
14809 bxe_get_phy_info(struct bxe_softc *sc)
14811 uint8_t port = SC_PORT(sc);
14812 uint32_t config = sc->port.config;
14815 /* shmem data already read in bxe_get_shmem_info() */
14817 BLOGD(sc, DBG_LOAD, "lane_config=0x%08x speed_cap_mask0=0x%08x "
14818 "link_config0=0x%08x\n",
14819 sc->link_params.lane_config,
14820 sc->link_params.speed_cap_mask[0],
14821 sc->port.link_config[0]);
14823 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
14824 bxe_link_settings_requested(sc);
14826 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) {
14827 sc->link_params.feature_config_flags |=
14828 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14829 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) {
14830 sc->link_params.feature_config_flags &=
14831 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14832 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) {
14833 sc->link_params.feature_config_flags |=
14834 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED;
14837 /* configure link feature according to nvram value */
14839 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) &
14840 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
14841 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
14842 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
14843 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI |
14844 ELINK_EEE_MODE_ENABLE_LPI |
14845 ELINK_EEE_MODE_OUTPUT_TIME);
14847 sc->link_params.eee_mode = 0;
14850 /* get the media type */
14851 bxe_media_detect(sc);
14855 bxe_get_params(struct bxe_softc *sc)
14857 /* get user tunable params */
14858 bxe_get_tunable_params(sc);
14860 /* select the RX and TX ring sizes */
14861 sc->tx_ring_size = TX_BD_USABLE;
14862 sc->rx_ring_size = RX_BD_USABLE;
14864 /* XXX disable WoL */
14869 bxe_set_modes_bitmap(struct bxe_softc *sc)
14871 uint32_t flags = 0;
14873 if (CHIP_REV_IS_FPGA(sc)) {
14874 SET_FLAGS(flags, MODE_FPGA);
14875 } else if (CHIP_REV_IS_EMUL(sc)) {
14876 SET_FLAGS(flags, MODE_EMUL);
14878 SET_FLAGS(flags, MODE_ASIC);
14881 if (CHIP_IS_MODE_4_PORT(sc)) {
14882 SET_FLAGS(flags, MODE_PORT4);
14884 SET_FLAGS(flags, MODE_PORT2);
14887 if (CHIP_IS_E2(sc)) {
14888 SET_FLAGS(flags, MODE_E2);
14889 } else if (CHIP_IS_E3(sc)) {
14890 SET_FLAGS(flags, MODE_E3);
14891 if (CHIP_REV(sc) == CHIP_REV_Ax) {
14892 SET_FLAGS(flags, MODE_E3_A0);
14893 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ {
14894 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
14899 SET_FLAGS(flags, MODE_MF);
14900 switch (sc->devinfo.mf_info.mf_mode) {
14901 case MULTI_FUNCTION_SD:
14902 SET_FLAGS(flags, MODE_MF_SD);
14904 case MULTI_FUNCTION_SI:
14905 SET_FLAGS(flags, MODE_MF_SI);
14907 case MULTI_FUNCTION_AFEX:
14908 SET_FLAGS(flags, MODE_MF_AFEX);
14912 SET_FLAGS(flags, MODE_SF);
14915 #if defined(__LITTLE_ENDIAN)
14916 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
14917 #else /* __BIG_ENDIAN */
14918 SET_FLAGS(flags, MODE_BIG_ENDIAN);
14921 INIT_MODE_FLAGS(sc) = flags;
14925 bxe_alloc_hsi_mem(struct bxe_softc *sc)
14927 struct bxe_fastpath *fp;
14928 bus_addr_t busaddr;
14929 int max_agg_queues;
14931 bus_size_t max_size;
14932 bus_size_t max_seg_size;
14937 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */
14939 /* allocate the parent bus DMA tag */
14940 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */
14942 0, /* boundary limit */
14943 BUS_SPACE_MAXADDR, /* restricted low */
14944 BUS_SPACE_MAXADDR, /* restricted hi */
14945 NULL, /* addr filter() */
14946 NULL, /* addr filter() arg */
14947 BUS_SPACE_MAXSIZE_32BIT, /* max map size */
14948 BUS_SPACE_UNRESTRICTED, /* num discontinuous */
14949 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
14952 NULL, /* lock() arg */
14953 &sc->parent_dma_tag); /* returned dma tag */
14955 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc);
14959 /************************/
14960 /* DEFAULT STATUS BLOCK */
14961 /************************/
14963 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block),
14964 &sc->def_sb_dma, "default status block") != 0) {
14966 bus_dma_tag_destroy(sc->parent_dma_tag);
14970 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr;
14976 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
14977 &sc->eq_dma, "event queue") != 0) {
14979 bxe_dma_free(sc, &sc->def_sb_dma);
14981 bus_dma_tag_destroy(sc->parent_dma_tag);
14985 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr;
14991 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath),
14992 &sc->sp_dma, "slow path") != 0) {
14994 bxe_dma_free(sc, &sc->eq_dma);
14996 bxe_dma_free(sc, &sc->def_sb_dma);
14998 bus_dma_tag_destroy(sc->parent_dma_tag);
15002 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr;
15004 /*******************/
15005 /* SLOW PATH QUEUE */
15006 /*******************/
15008 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE,
15009 &sc->spq_dma, "slow path queue") != 0) {
15011 bxe_dma_free(sc, &sc->sp_dma);
15013 bxe_dma_free(sc, &sc->eq_dma);
15015 bxe_dma_free(sc, &sc->def_sb_dma);
15017 bus_dma_tag_destroy(sc->parent_dma_tag);
15021 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr;
15023 /***************************/
15024 /* FW DECOMPRESSION BUFFER */
15025 /***************************/
15027 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma,
15028 "fw decompression buffer") != 0) {
15030 bxe_dma_free(sc, &sc->spq_dma);
15032 bxe_dma_free(sc, &sc->sp_dma);
15034 bxe_dma_free(sc, &sc->eq_dma);
15036 bxe_dma_free(sc, &sc->def_sb_dma);
15038 bus_dma_tag_destroy(sc->parent_dma_tag);
15042 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr;
15045 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) {
15047 bxe_dma_free(sc, &sc->gz_buf_dma);
15049 bxe_dma_free(sc, &sc->spq_dma);
15051 bxe_dma_free(sc, &sc->sp_dma);
15053 bxe_dma_free(sc, &sc->eq_dma);
15055 bxe_dma_free(sc, &sc->def_sb_dma);
15057 bus_dma_tag_destroy(sc->parent_dma_tag);
15065 /* allocate DMA memory for each fastpath structure */
15066 for (i = 0; i < sc->num_queues; i++) {
15071 /*******************/
15072 /* FP STATUS BLOCK */
15073 /*******************/
15075 snprintf(buf, sizeof(buf), "fp %d status block", i);
15076 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block),
15077 &fp->sb_dma, buf) != 0) {
15078 /* XXX unwind and free previous fastpath allocations */
15079 BLOGE(sc, "Failed to alloc %s\n", buf);
15082 if (CHIP_IS_E2E3(sc)) {
15083 fp->status_block.e2_sb =
15084 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr;
15086 fp->status_block.e1x_sb =
15087 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr;
15091 /******************/
15092 /* FP TX BD CHAIN */
15093 /******************/
15095 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i);
15096 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES),
15097 &fp->tx_dma, buf) != 0) {
15098 /* XXX unwind and free previous fastpath allocations */
15099 BLOGE(sc, "Failed to alloc %s\n", buf);
15102 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr;
15105 /* link together the tx bd chain pages */
15106 for (j = 1; j <= TX_BD_NUM_PAGES; j++) {
15107 /* index into the tx bd chain array to last entry per page */
15108 struct eth_tx_next_bd *tx_next_bd =
15109 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd;
15110 /* point to the next page and wrap from last page */
15111 busaddr = (fp->tx_dma.paddr +
15112 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES)));
15113 tx_next_bd->addr_hi = htole32(U64_HI(busaddr));
15114 tx_next_bd->addr_lo = htole32(U64_LO(busaddr));
15117 /******************/
15118 /* FP RX BD CHAIN */
15119 /******************/
15121 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i);
15122 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES),
15123 &fp->rx_dma, buf) != 0) {
15124 /* XXX unwind and free previous fastpath allocations */
15125 BLOGE(sc, "Failed to alloc %s\n", buf);
15128 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr;
15131 /* link together the rx bd chain pages */
15132 for (j = 1; j <= RX_BD_NUM_PAGES; j++) {
15133 /* index into the rx bd chain array to last entry per page */
15134 struct eth_rx_bd *rx_bd =
15135 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2];
15136 /* point to the next page and wrap from last page */
15137 busaddr = (fp->rx_dma.paddr +
15138 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES)));
15139 rx_bd->addr_hi = htole32(U64_HI(busaddr));
15140 rx_bd->addr_lo = htole32(U64_LO(busaddr));
15143 /*******************/
15144 /* FP RX RCQ CHAIN */
15145 /*******************/
15147 snprintf(buf, sizeof(buf), "fp %d rcq chain", i);
15148 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES),
15149 &fp->rcq_dma, buf) != 0) {
15150 /* XXX unwind and free previous fastpath allocations */
15151 BLOGE(sc, "Failed to alloc %s\n", buf);
15154 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr;
15157 /* link together the rcq chain pages */
15158 for (j = 1; j <= RCQ_NUM_PAGES; j++) {
15159 /* index into the rcq chain array to last entry per page */
15160 struct eth_rx_cqe_next_page *rx_cqe_next =
15161 (struct eth_rx_cqe_next_page *)
15162 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1];
15163 /* point to the next page and wrap from last page */
15164 busaddr = (fp->rcq_dma.paddr +
15165 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES)));
15166 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr));
15167 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr));
15170 /*******************/
15171 /* FP RX SGE CHAIN */
15172 /*******************/
15174 snprintf(buf, sizeof(buf), "fp %d sge chain", i);
15175 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES),
15176 &fp->rx_sge_dma, buf) != 0) {
15177 /* XXX unwind and free previous fastpath allocations */
15178 BLOGE(sc, "Failed to alloc %s\n", buf);
15181 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr;
15184 /* link together the sge chain pages */
15185 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) {
15186 /* index into the rcq chain array to last entry per page */
15187 struct eth_rx_sge *rx_sge =
15188 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2];
15189 /* point to the next page and wrap from last page */
15190 busaddr = (fp->rx_sge_dma.paddr +
15191 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES)));
15192 rx_sge->addr_hi = htole32(U64_HI(busaddr));
15193 rx_sge->addr_lo = htole32(U64_LO(busaddr));
15196 /***********************/
15197 /* FP TX MBUF DMA MAPS */
15198 /***********************/
15200 /* set required sizes before mapping to conserve resources */
15201 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) {
15202 max_size = BXE_TSO_MAX_SIZE;
15203 max_segments = BXE_TSO_MAX_SEGMENTS;
15204 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
15206 max_size = (MCLBYTES * BXE_MAX_SEGMENTS);
15207 max_segments = BXE_MAX_SEGMENTS;
15208 max_seg_size = MCLBYTES;
15211 /* create a dma tag for the tx mbufs */
15212 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15214 0, /* boundary limit */
15215 BUS_SPACE_MAXADDR, /* restricted low */
15216 BUS_SPACE_MAXADDR, /* restricted hi */
15217 NULL, /* addr filter() */
15218 NULL, /* addr filter() arg */
15219 max_size, /* max map size */
15220 max_segments, /* num discontinuous */
15221 max_seg_size, /* max seg size */
15224 NULL, /* lock() arg */
15225 &fp->tx_mbuf_tag); /* returned dma tag */
15227 /* XXX unwind and free previous fastpath allocations */
15228 BLOGE(sc, "Failed to create dma tag for "
15229 "'fp %d tx mbufs' (%d)\n",
15234 /* create dma maps for each of the tx mbuf clusters */
15235 for (j = 0; j < TX_BD_TOTAL; j++) {
15236 if (bus_dmamap_create(fp->tx_mbuf_tag,
15238 &fp->tx_mbuf_chain[j].m_map)) {
15239 /* XXX unwind and free previous fastpath allocations */
15240 BLOGE(sc, "Failed to create dma map for "
15241 "'fp %d tx mbuf %d' (%d)\n",
15247 /***********************/
15248 /* FP RX MBUF DMA MAPS */
15249 /***********************/
15251 /* create a dma tag for the rx mbufs */
15252 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15254 0, /* boundary limit */
15255 BUS_SPACE_MAXADDR, /* restricted low */
15256 BUS_SPACE_MAXADDR, /* restricted hi */
15257 NULL, /* addr filter() */
15258 NULL, /* addr filter() arg */
15259 MJUM9BYTES, /* max map size */
15260 1, /* num discontinuous */
15261 MJUM9BYTES, /* max seg size */
15264 NULL, /* lock() arg */
15265 &fp->rx_mbuf_tag); /* returned dma tag */
15267 /* XXX unwind and free previous fastpath allocations */
15268 BLOGE(sc, "Failed to create dma tag for "
15269 "'fp %d rx mbufs' (%d)\n",
15274 /* create dma maps for each of the rx mbuf clusters */
15275 for (j = 0; j < RX_BD_TOTAL; j++) {
15276 if (bus_dmamap_create(fp->rx_mbuf_tag,
15278 &fp->rx_mbuf_chain[j].m_map)) {
15279 /* XXX unwind and free previous fastpath allocations */
15280 BLOGE(sc, "Failed to create dma map for "
15281 "'fp %d rx mbuf %d' (%d)\n",
15287 /* create dma map for the spare rx mbuf cluster */
15288 if (bus_dmamap_create(fp->rx_mbuf_tag,
15290 &fp->rx_mbuf_spare_map)) {
15291 /* XXX unwind and free previous fastpath allocations */
15292 BLOGE(sc, "Failed to create dma map for "
15293 "'fp %d spare rx mbuf' (%d)\n",
15298 /***************************/
15299 /* FP RX SGE MBUF DMA MAPS */
15300 /***************************/
15302 /* create a dma tag for the rx sge mbufs */
15303 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */
15305 0, /* boundary limit */
15306 BUS_SPACE_MAXADDR, /* restricted low */
15307 BUS_SPACE_MAXADDR, /* restricted hi */
15308 NULL, /* addr filter() */
15309 NULL, /* addr filter() arg */
15310 BCM_PAGE_SIZE, /* max map size */
15311 1, /* num discontinuous */
15312 BCM_PAGE_SIZE, /* max seg size */
15315 NULL, /* lock() arg */
15316 &fp->rx_sge_mbuf_tag); /* returned dma tag */
15318 /* XXX unwind and free previous fastpath allocations */
15319 BLOGE(sc, "Failed to create dma tag for "
15320 "'fp %d rx sge mbufs' (%d)\n",
15325 /* create dma maps for the rx sge mbuf clusters */
15326 for (j = 0; j < RX_SGE_TOTAL; j++) {
15327 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15329 &fp->rx_sge_mbuf_chain[j].m_map)) {
15330 /* XXX unwind and free previous fastpath allocations */
15331 BLOGE(sc, "Failed to create dma map for "
15332 "'fp %d rx sge mbuf %d' (%d)\n",
15338 /* create dma map for the spare rx sge mbuf cluster */
15339 if (bus_dmamap_create(fp->rx_sge_mbuf_tag,
15341 &fp->rx_sge_mbuf_spare_map)) {
15342 /* XXX unwind and free previous fastpath allocations */
15343 BLOGE(sc, "Failed to create dma map for "
15344 "'fp %d spare rx sge mbuf' (%d)\n",
15349 /***************************/
15350 /* FP RX TPA MBUF DMA MAPS */
15351 /***************************/
15353 /* create dma maps for the rx tpa mbuf clusters */
15354 max_agg_queues = MAX_AGG_QS(sc);
15356 for (j = 0; j < max_agg_queues; j++) {
15357 if (bus_dmamap_create(fp->rx_mbuf_tag,
15359 &fp->rx_tpa_info[j].bd.m_map)) {
15360 /* XXX unwind and free previous fastpath allocations */
15361 BLOGE(sc, "Failed to create dma map for "
15362 "'fp %d rx tpa mbuf %d' (%d)\n",
15368 /* create dma map for the spare rx tpa mbuf cluster */
15369 if (bus_dmamap_create(fp->rx_mbuf_tag,
15371 &fp->rx_tpa_info_mbuf_spare_map)) {
15372 /* XXX unwind and free previous fastpath allocations */
15373 BLOGE(sc, "Failed to create dma map for "
15374 "'fp %d spare rx tpa mbuf' (%d)\n",
15379 bxe_init_sge_ring_bit_mask(fp);
15386 bxe_free_hsi_mem(struct bxe_softc *sc)
15388 struct bxe_fastpath *fp;
15389 int max_agg_queues;
15392 if (sc->parent_dma_tag == NULL) {
15393 return; /* assume nothing was allocated */
15396 for (i = 0; i < sc->num_queues; i++) {
15399 /*******************/
15400 /* FP STATUS BLOCK */
15401 /*******************/
15403 bxe_dma_free(sc, &fp->sb_dma);
15404 memset(&fp->status_block, 0, sizeof(fp->status_block));
15406 /******************/
15407 /* FP TX BD CHAIN */
15408 /******************/
15410 bxe_dma_free(sc, &fp->tx_dma);
15411 fp->tx_chain = NULL;
15413 /******************/
15414 /* FP RX BD CHAIN */
15415 /******************/
15417 bxe_dma_free(sc, &fp->rx_dma);
15418 fp->rx_chain = NULL;
15420 /*******************/
15421 /* FP RX RCQ CHAIN */
15422 /*******************/
15424 bxe_dma_free(sc, &fp->rcq_dma);
15425 fp->rcq_chain = NULL;
15427 /*******************/
15428 /* FP RX SGE CHAIN */
15429 /*******************/
15431 bxe_dma_free(sc, &fp->rx_sge_dma);
15432 fp->rx_sge_chain = NULL;
15434 /***********************/
15435 /* FP TX MBUF DMA MAPS */
15436 /***********************/
15438 if (fp->tx_mbuf_tag != NULL) {
15439 for (j = 0; j < TX_BD_TOTAL; j++) {
15440 if (fp->tx_mbuf_chain[j].m_map != NULL) {
15441 bus_dmamap_unload(fp->tx_mbuf_tag,
15442 fp->tx_mbuf_chain[j].m_map);
15443 bus_dmamap_destroy(fp->tx_mbuf_tag,
15444 fp->tx_mbuf_chain[j].m_map);
15448 bus_dma_tag_destroy(fp->tx_mbuf_tag);
15449 fp->tx_mbuf_tag = NULL;
15452 /***********************/
15453 /* FP RX MBUF DMA MAPS */
15454 /***********************/
15456 if (fp->rx_mbuf_tag != NULL) {
15457 for (j = 0; j < RX_BD_TOTAL; j++) {
15458 if (fp->rx_mbuf_chain[j].m_map != NULL) {
15459 bus_dmamap_unload(fp->rx_mbuf_tag,
15460 fp->rx_mbuf_chain[j].m_map);
15461 bus_dmamap_destroy(fp->rx_mbuf_tag,
15462 fp->rx_mbuf_chain[j].m_map);
15466 if (fp->rx_mbuf_spare_map != NULL) {
15467 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15468 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map);
15471 /***************************/
15472 /* FP RX TPA MBUF DMA MAPS */
15473 /***************************/
15475 max_agg_queues = MAX_AGG_QS(sc);
15477 for (j = 0; j < max_agg_queues; j++) {
15478 if (fp->rx_tpa_info[j].bd.m_map != NULL) {
15479 bus_dmamap_unload(fp->rx_mbuf_tag,
15480 fp->rx_tpa_info[j].bd.m_map);
15481 bus_dmamap_destroy(fp->rx_mbuf_tag,
15482 fp->rx_tpa_info[j].bd.m_map);
15486 if (fp->rx_tpa_info_mbuf_spare_map != NULL) {
15487 bus_dmamap_unload(fp->rx_mbuf_tag,
15488 fp->rx_tpa_info_mbuf_spare_map);
15489 bus_dmamap_destroy(fp->rx_mbuf_tag,
15490 fp->rx_tpa_info_mbuf_spare_map);
15493 bus_dma_tag_destroy(fp->rx_mbuf_tag);
15494 fp->rx_mbuf_tag = NULL;
15497 /***************************/
15498 /* FP RX SGE MBUF DMA MAPS */
15499 /***************************/
15501 if (fp->rx_sge_mbuf_tag != NULL) {
15502 for (j = 0; j < RX_SGE_TOTAL; j++) {
15503 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) {
15504 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15505 fp->rx_sge_mbuf_chain[j].m_map);
15506 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15507 fp->rx_sge_mbuf_chain[j].m_map);
15511 if (fp->rx_sge_mbuf_spare_map != NULL) {
15512 bus_dmamap_unload(fp->rx_sge_mbuf_tag,
15513 fp->rx_sge_mbuf_spare_map);
15514 bus_dmamap_destroy(fp->rx_sge_mbuf_tag,
15515 fp->rx_sge_mbuf_spare_map);
15518 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag);
15519 fp->rx_sge_mbuf_tag = NULL;
15523 /***************************/
15524 /* FW DECOMPRESSION BUFFER */
15525 /***************************/
15527 bxe_dma_free(sc, &sc->gz_buf_dma);
15529 free(sc->gz_strm, M_DEVBUF);
15530 sc->gz_strm = NULL;
15532 /*******************/
15533 /* SLOW PATH QUEUE */
15534 /*******************/
15536 bxe_dma_free(sc, &sc->spq_dma);
15543 bxe_dma_free(sc, &sc->sp_dma);
15550 bxe_dma_free(sc, &sc->eq_dma);
15553 /************************/
15554 /* DEFAULT STATUS BLOCK */
15555 /************************/
15557 bxe_dma_free(sc, &sc->def_sb_dma);
15560 bus_dma_tag_destroy(sc->parent_dma_tag);
15561 sc->parent_dma_tag = NULL;
15565 * Previous driver DMAE transaction may have occurred when pre-boot stage
15566 * ended and boot began. This would invalidate the addresses of the
15567 * transaction, resulting in was-error bit set in the PCI causing all
15568 * hw-to-host PCIe transactions to timeout. If this happened we want to clear
15569 * the interrupt which detected this from the pglueb and the was-done bit
15572 bxe_prev_interrupted_dmae(struct bxe_softc *sc)
15576 if (!CHIP_IS_E1x(sc)) {
15577 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);
15578 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
15579 BLOGD(sc, DBG_LOAD,
15580 "Clearing 'was-error' bit that was set in pglueb");
15581 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc));
15587 bxe_prev_mcp_done(struct bxe_softc *sc)
15589 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE,
15590 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
15592 BLOGE(sc, "MCP response failure, aborting\n");
15599 static struct bxe_prev_list_node *
15600 bxe_prev_path_get_entry(struct bxe_softc *sc)
15602 struct bxe_prev_list_node *tmp;
15604 LIST_FOREACH(tmp, &bxe_prev_list, node) {
15605 if ((sc->pcie_bus == tmp->bus) &&
15606 (sc->pcie_device == tmp->slot) &&
15607 (SC_PATH(sc) == tmp->path)) {
15616 bxe_prev_is_path_marked(struct bxe_softc *sc)
15618 struct bxe_prev_list_node *tmp;
15621 mtx_lock(&bxe_prev_mtx);
15623 tmp = bxe_prev_path_get_entry(sc);
15626 BLOGD(sc, DBG_LOAD,
15627 "Path %d/%d/%d was marked by AER\n",
15628 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15631 BLOGD(sc, DBG_LOAD,
15632 "Path %d/%d/%d was already cleaned from previous drivers\n",
15633 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15637 mtx_unlock(&bxe_prev_mtx);
15643 bxe_prev_mark_path(struct bxe_softc *sc,
15644 uint8_t after_undi)
15646 struct bxe_prev_list_node *tmp;
15648 mtx_lock(&bxe_prev_mtx);
15650 /* Check whether the entry for this path already exists */
15651 tmp = bxe_prev_path_get_entry(sc);
15654 BLOGD(sc, DBG_LOAD,
15655 "Re-marking AER in path %d/%d/%d\n",
15656 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15658 BLOGD(sc, DBG_LOAD,
15659 "Removing AER indication from path %d/%d/%d\n",
15660 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15664 mtx_unlock(&bxe_prev_mtx);
15668 mtx_unlock(&bxe_prev_mtx);
15670 /* Create an entry for this path and add it */
15671 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF,
15672 (M_NOWAIT | M_ZERO));
15674 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n");
15678 tmp->bus = sc->pcie_bus;
15679 tmp->slot = sc->pcie_device;
15680 tmp->path = SC_PATH(sc);
15682 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
15684 mtx_lock(&bxe_prev_mtx);
15686 BLOGD(sc, DBG_LOAD,
15687 "Marked path %d/%d/%d - finished previous unload\n",
15688 sc->pcie_bus, sc->pcie_device, SC_PATH(sc));
15689 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node);
15691 mtx_unlock(&bxe_prev_mtx);
15697 bxe_do_flr(struct bxe_softc *sc)
15701 /* only E2 and onwards support FLR */
15702 if (CHIP_IS_E1x(sc)) {
15703 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n");
15707 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
15708 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
15709 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n",
15710 sc->devinfo.bc_ver);
15714 /* Wait for Transaction Pending bit clean */
15715 for (i = 0; i < 4; i++) {
15717 DELAY(((1 << (i - 1)) * 100) * 1000);
15720 if (!bxe_is_pcie_pending(sc)) {
15725 BLOGE(sc, "PCIE transaction is not cleared, "
15726 "proceeding with reset anyway\n");
15730 BLOGD(sc, DBG_LOAD, "Initiating FLR\n");
15731 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0);
15736 struct bxe_mac_vals {
15737 uint32_t xmac_addr;
15739 uint32_t emac_addr;
15741 uint32_t umac_addr;
15743 uint32_t bmac_addr;
15744 uint32_t bmac_val[2];
15748 bxe_prev_unload_close_mac(struct bxe_softc *sc,
15749 struct bxe_mac_vals *vals)
15751 uint32_t val, base_addr, offset, mask, reset_reg;
15752 uint8_t mac_stopped = FALSE;
15753 uint8_t port = SC_PORT(sc);
15754 uint32_t wb_data[2];
15756 /* reset addresses as they also mark which values were changed */
15757 vals->bmac_addr = 0;
15758 vals->umac_addr = 0;
15759 vals->xmac_addr = 0;
15760 vals->emac_addr = 0;
15762 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);
15764 if (!CHIP_IS_E3(sc)) {
15765 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
15766 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
15767 if ((mask & reset_reg) && val) {
15768 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n");
15769 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
15770 : NIG_REG_INGRESS_BMAC0_MEM;
15771 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL
15772 : BIGMAC_REGISTER_BMAC_CONTROL;
15775 * use rd/wr since we cannot use dmae. This is safe
15776 * since MCP won't access the bus due to the request
15777 * to unload, and no function on the path can be
15778 * loaded at this time.
15780 wb_data[0] = REG_RD(sc, base_addr + offset);
15781 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);
15782 vals->bmac_addr = base_addr + offset;
15783 vals->bmac_val[0] = wb_data[0];
15784 vals->bmac_val[1] = wb_data[1];
15785 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
15786 REG_WR(sc, vals->bmac_addr, wb_data[0]);
15787 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]);
15790 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n");
15791 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
15792 vals->emac_val = REG_RD(sc, vals->emac_addr);
15793 REG_WR(sc, vals->emac_addr, 0);
15794 mac_stopped = TRUE;
15796 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
15797 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n");
15798 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
15799 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);
15800 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1));
15801 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1));
15802 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
15803 vals->xmac_val = REG_RD(sc, vals->xmac_addr);
15804 REG_WR(sc, vals->xmac_addr, 0);
15805 mac_stopped = TRUE;
15808 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
15809 if (mask & reset_reg) {
15810 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n");
15811 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
15812 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
15813 vals->umac_val = REG_RD(sc, vals->umac_addr);
15814 REG_WR(sc, vals->umac_addr, 0);
15815 mac_stopped = TRUE;
15824 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
15825 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff)
15826 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
15827 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
15830 bxe_prev_unload_undi_inc(struct bxe_softc *sc,
15835 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));
15837 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc;
15838 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc;
15840 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd);
15841 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg);
15843 BLOGD(sc, DBG_LOAD,
15844 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
15849 bxe_prev_unload_common(struct bxe_softc *sc)
15851 uint32_t reset_reg, tmp_reg = 0, rc;
15852 uint8_t prev_undi = FALSE;
15853 struct bxe_mac_vals mac_vals;
15854 uint32_t timer_count = 1000;
15858 * It is possible a previous function received 'common' answer,
15859 * but hasn't loaded yet, therefore creating a scenario of
15860 * multiple functions receiving 'common' on the same path.
15862 BLOGD(sc, DBG_LOAD, "Common unload Flow\n");
15864 memset(&mac_vals, 0, sizeof(mac_vals));
15866 if (bxe_prev_is_path_marked(sc)) {
15867 return (bxe_prev_mcp_done(sc));
15870 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);
15872 /* Reset should be performed after BRB is emptied */
15873 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
15874 /* Close the MAC Rx to prevent BRB from filling up */
15875 bxe_prev_unload_close_mac(sc, &mac_vals);
15877 /* close LLH filters towards the BRB */
15878 elink_set_rx_filter(&sc->link_params, 0);
15881 * Check if the UNDI driver was previously loaded.
15882 * UNDI driver initializes CID offset for normal bell to 0x7
15884 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
15885 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
15886 if (tmp_reg == 0x7) {
15887 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n");
15889 /* clear the UNDI indication */
15890 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
15891 /* clear possible idle check errors */
15892 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);
15896 /* wait until BRB is empty */
15897 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15898 while (timer_count) {
15899 prev_brb = tmp_reg;
15901 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);
15906 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg);
15908 /* reset timer as long as BRB actually gets emptied */
15909 if (prev_brb > tmp_reg) {
15910 timer_count = 1000;
15915 /* If UNDI resides in memory, manually increment it */
15917 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
15923 if (!timer_count) {
15924 BLOGE(sc, "Failed to empty BRB\n");
15928 /* No packets are in the pipeline, path is ready for reset */
15929 bxe_reset_common(sc);
15931 if (mac_vals.xmac_addr) {
15932 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val);
15934 if (mac_vals.umac_addr) {
15935 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val);
15937 if (mac_vals.emac_addr) {
15938 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val);
15940 if (mac_vals.bmac_addr) {
15941 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
15942 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
15945 rc = bxe_prev_mark_path(sc, prev_undi);
15947 bxe_prev_mcp_done(sc);
15951 return (bxe_prev_mcp_done(sc));
15955 bxe_prev_unload_uncommon(struct bxe_softc *sc)
15959 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n");
15961 /* Test if previous unload process was already finished for this path */
15962 if (bxe_prev_is_path_marked(sc)) {
15963 return (bxe_prev_mcp_done(sc));
15966 BLOGD(sc, DBG_LOAD, "Path is unmarked\n");
15969 * If function has FLR capabilities, and existing FW version matches
15970 * the one required, then FLR will be sufficient to clean any residue
15971 * left by previous driver
15973 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION);
15975 /* fw version is good */
15976 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n");
15977 rc = bxe_do_flr(sc);
15981 /* FLR was performed */
15982 BLOGD(sc, DBG_LOAD, "FLR successful\n");
15986 BLOGD(sc, DBG_LOAD, "Could not FLR\n");
15988 /* Close the MCP request, return failure*/
15989 rc = bxe_prev_mcp_done(sc);
15991 rc = BXE_PREV_WAIT_NEEDED;
15998 bxe_prev_unload(struct bxe_softc *sc)
16000 int time_counter = 10;
16001 uint32_t fw, hw_lock_reg, hw_lock_val;
16005 * Clear HW from errors which may have resulted from an interrupted
16006 * DMAE transaction.
16008 bxe_prev_interrupted_dmae(sc);
16010 /* Release previously held locks */
16012 (SC_FUNC(sc) <= 5) ?
16013 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) :
16014 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8);
16016 hw_lock_val = (REG_RD(sc, hw_lock_reg));
16018 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
16019 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n");
16020 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
16021 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
16023 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n");
16024 REG_WR(sc, hw_lock_reg, 0xffffffff);
16026 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n");
16029 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {
16030 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n");
16031 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0);
16035 /* Lock MCP using an unload request */
16036 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
16038 BLOGE(sc, "MCP response failure, aborting\n");
16043 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
16044 rc = bxe_prev_unload_common(sc);
16048 /* non-common reply from MCP night require looping */
16049 rc = bxe_prev_unload_uncommon(sc);
16050 if (rc != BXE_PREV_WAIT_NEEDED) {
16055 } while (--time_counter);
16057 if (!time_counter || rc) {
16058 BLOGE(sc, "Failed to unload previous driver!\n");
16066 bxe_dcbx_set_state(struct bxe_softc *sc,
16068 uint32_t dcbx_enabled)
16070 if (!CHIP_IS_E1x(sc)) {
16071 sc->dcb_state = dcb_on;
16072 sc->dcbx_enabled = dcbx_enabled;
16074 sc->dcb_state = FALSE;
16075 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID;
16077 BLOGD(sc, DBG_LOAD,
16078 "DCB state [%s:%s]\n",
16079 dcb_on ? "ON" : "OFF",
16080 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" :
16081 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" :
16082 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ?
16083 "on-chip with negotiation" : "invalid");
16086 /* must be called after sriov-enable */
16088 bxe_set_qm_cid_count(struct bxe_softc *sc)
16090 int cid_count = BXE_L2_MAX_CID(sc);
16092 if (IS_SRIOV(sc)) {
16093 cid_count += BXE_VF_CIDS;
16096 if (CNIC_SUPPORT(sc)) {
16097 cid_count += CNIC_CID_MAX;
16100 return (roundup(cid_count, QM_CID_ROUND));
16104 bxe_init_multi_cos(struct bxe_softc *sc)
16108 uint32_t pri_map = 0; /* XXX change to user config */
16110 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) {
16111 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4));
16112 if (cos < sc->max_cos) {
16113 sc->prio_to_cos[pri] = cos;
16115 BLOGW(sc, "Invalid COS %d for priority %d "
16116 "(max COS is %d), setting to 0\n",
16117 cos, pri, (sc->max_cos - 1));
16118 sc->prio_to_cos[pri] = 0;
16124 bxe_sysctl_state(SYSCTL_HANDLER_ARGS)
16126 struct bxe_softc *sc;
16130 error = sysctl_handle_int(oidp, &result, 0, req);
16132 if (error || !req->newptr) {
16137 sc = (struct bxe_softc *)arg1;
16138 BLOGI(sc, "... dumping driver state ...\n");
16146 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS)
16148 struct bxe_softc *sc = (struct bxe_softc *)arg1;
16149 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats;
16151 uint64_t value = 0;
16152 int index = (int)arg2;
16154 if (index >= BXE_NUM_ETH_STATS) {
16155 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index);
16159 offset = (eth_stats + bxe_eth_stats_arr[index].offset);
16161 switch (bxe_eth_stats_arr[index].size) {
16163 value = (uint64_t)*offset;
16166 value = HILO_U64(*offset, *(offset + 1));
16169 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n",
16170 index, bxe_eth_stats_arr[index].size);
16174 return (sysctl_handle_64(oidp, &value, 0, req));
16178 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS)
16180 struct bxe_softc *sc = (struct bxe_softc *)arg1;
16181 uint32_t *eth_stats;
16183 uint64_t value = 0;
16184 uint32_t q_stat = (uint32_t)arg2;
16185 uint32_t fp_index = ((q_stat >> 16) & 0xffff);
16186 uint32_t index = (q_stat & 0xffff);
16188 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats;
16190 if (index >= BXE_NUM_ETH_Q_STATS) {
16191 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index);
16195 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset);
16197 switch (bxe_eth_q_stats_arr[index].size) {
16199 value = (uint64_t)*offset;
16202 value = HILO_U64(*offset, *(offset + 1));
16205 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n",
16206 index, bxe_eth_q_stats_arr[index].size);
16210 return (sysctl_handle_64(oidp, &value, 0, req));
16214 bxe_add_sysctls(struct bxe_softc *sc)
16216 struct sysctl_ctx_list *ctx;
16217 struct sysctl_oid_list *children;
16218 struct sysctl_oid *queue_top, *queue;
16219 struct sysctl_oid_list *queue_top_children, *queue_children;
16220 char queue_num_buf[32];
16224 ctx = device_get_sysctl_ctx(sc->dev);
16225 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
16227 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version",
16228 CTLFLAG_RD, BXE_DRIVER_VERSION, 0,
16231 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version",
16232 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0,
16233 "bootcode version");
16235 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d",
16236 BCM_5710_FW_MAJOR_VERSION,
16237 BCM_5710_FW_MINOR_VERSION,
16238 BCM_5710_FW_REVISION_VERSION,
16239 BCM_5710_FW_ENGINEERING_VERSION);
16240 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version",
16241 CTLFLAG_RD, sc->fw_ver_str, 0,
16242 "firmware version");
16244 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s",
16245 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" :
16246 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" :
16247 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" :
16248 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" :
16250 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode",
16251 CTLFLAG_RD, sc->mf_mode_str, 0,
16252 "multifunction mode");
16254 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics",
16255 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0,
16256 "multifunction vnics per port");
16258 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr",
16259 CTLFLAG_RD, sc->mac_addr_str, 0,
16262 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d",
16263 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" :
16264 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" :
16265 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" :
16267 sc->devinfo.pcie_link_width);
16268 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link",
16269 CTLFLAG_RD, sc->pci_link_str, 0,
16270 "pci link status");
16272 sc->debug = bxe_debug;
16273 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug",
16274 CTLFLAG_RW, &sc->debug,
16275 "debug logging mode");
16277 sc->rx_budget = bxe_rx_budget;
16278 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget",
16279 CTLFLAG_RW, &sc->rx_budget, 0,
16280 "rx processing budget");
16282 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state",
16283 CTLTYPE_UINT | CTLFLAG_RW, sc, 0,
16284 bxe_sysctl_state, "IU", "dump driver state");
16286 for (i = 0; i < BXE_NUM_ETH_STATS; i++) {
16287 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
16288 bxe_eth_stats_arr[i].string,
16289 CTLTYPE_U64 | CTLFLAG_RD, sc, i,
16290 bxe_sysctl_eth_stat, "LU",
16291 bxe_eth_stats_arr[i].string);
16294 /* add a new parent node for all queues "dev.bxe.#.queue" */
16295 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue",
16296 CTLFLAG_RD, NULL, "queue");
16297 queue_top_children = SYSCTL_CHILDREN(queue_top);
16299 for (i = 0; i < sc->num_queues; i++) {
16300 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */
16301 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i);
16302 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO,
16303 queue_num_buf, CTLFLAG_RD, NULL,
16305 queue_children = SYSCTL_CHILDREN(queue);
16307 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) {
16308 q_stat = ((i << 16) | j);
16309 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO,
16310 bxe_eth_q_stats_arr[j].string,
16311 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat,
16312 bxe_sysctl_eth_q_stat, "LU",
16313 bxe_eth_q_stats_arr[j].string);
16319 * Device attach function.
16321 * Allocates device resources, performs secondary chip identification, and
16322 * initializes driver instance variables. This function is called from driver
16323 * load after a successful probe.
16326 * 0 = Success, >0 = Failure
16329 bxe_attach(device_t dev)
16331 struct bxe_softc *sc;
16333 sc = device_get_softc(dev);
16335 BLOGD(sc, DBG_LOAD, "Starting attach...\n");
16337 sc->state = BXE_STATE_CLOSED;
16340 sc->unit = device_get_unit(dev);
16342 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc);
16344 sc->pcie_bus = pci_get_bus(dev);
16345 sc->pcie_device = pci_get_slot(dev);
16346 sc->pcie_func = pci_get_function(dev);
16348 /* enable bus master capability */
16349 pci_enable_busmaster(dev);
16352 if (bxe_allocate_bars(sc) != 0) {
16356 /* initialize the mutexes */
16357 bxe_init_mutexes(sc);
16359 /* prepare the periodic callout */
16360 callout_init(&sc->periodic_callout, 0);
16362 /* prepare the chip taskqueue */
16363 sc->chip_tq_flags = CHIP_TQ_NONE;
16364 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name),
16365 "bxe%d_chip_tq", sc->unit);
16366 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc);
16367 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT,
16368 taskqueue_thread_enqueue,
16370 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */
16371 "%s", sc->chip_tq_name);
16373 /* get device info and set params */
16374 if (bxe_get_device_info(sc) != 0) {
16375 BLOGE(sc, "getting device info\n");
16376 bxe_deallocate_bars(sc);
16377 pci_disable_busmaster(dev);
16381 /* get final misc params */
16382 bxe_get_params(sc);
16384 /* set the default MTU (changed via ifconfig) */
16385 sc->mtu = ETHERMTU;
16387 bxe_set_modes_bitmap(sc);
16390 * If in AFEX mode and the function is configured for FCoE
16391 * then bail... no L2 allowed.
16394 /* get phy settings from shmem and 'and' against admin settings */
16395 bxe_get_phy_info(sc);
16397 /* initialize the FreeBSD ifnet interface */
16398 if (bxe_init_ifnet(sc) != 0) {
16399 bxe_release_mutexes(sc);
16400 bxe_deallocate_bars(sc);
16401 pci_disable_busmaster(dev);
16405 /* allocate device interrupts */
16406 if (bxe_interrupt_alloc(sc) != 0) {
16407 if (sc->ifnet != NULL) {
16408 ether_ifdetach(sc->ifnet);
16410 ifmedia_removeall(&sc->ifmedia);
16411 bxe_release_mutexes(sc);
16412 bxe_deallocate_bars(sc);
16413 pci_disable_busmaster(dev);
16418 if (bxe_alloc_ilt_mem(sc) != 0) {
16419 bxe_interrupt_free(sc);
16420 if (sc->ifnet != NULL) {
16421 ether_ifdetach(sc->ifnet);
16423 ifmedia_removeall(&sc->ifmedia);
16424 bxe_release_mutexes(sc);
16425 bxe_deallocate_bars(sc);
16426 pci_disable_busmaster(dev);
16430 /* allocate the host hardware/software hsi structures */
16431 if (bxe_alloc_hsi_mem(sc) != 0) {
16432 bxe_free_ilt_mem(sc);
16433 bxe_interrupt_free(sc);
16434 if (sc->ifnet != NULL) {
16435 ether_ifdetach(sc->ifnet);
16437 ifmedia_removeall(&sc->ifmedia);
16438 bxe_release_mutexes(sc);
16439 bxe_deallocate_bars(sc);
16440 pci_disable_busmaster(dev);
16444 /* need to reset chip if UNDI was active */
16445 if (IS_PF(sc) && !BXE_NOMCP(sc)) {
16448 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) &
16449 DRV_MSG_SEQ_NUMBER_MASK);
16450 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq);
16451 bxe_prev_unload(sc);
16456 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16458 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) &&
16459 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) &&
16460 SHMEM2_RD(sc, dcbx_lldp_params_offset) &&
16461 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) {
16462 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON);
16463 bxe_dcbx_init_params(sc);
16465 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF);
16469 /* calculate qm_cid_count */
16470 sc->qm_cid_count = bxe_set_qm_cid_count(sc);
16471 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count);
16474 bxe_init_multi_cos(sc);
16476 bxe_add_sysctls(sc);
16482 * Device detach function.
16484 * Stops the controller, resets the controller, and releases resources.
16487 * 0 = Success, >0 = Failure
16490 bxe_detach(device_t dev)
16492 struct bxe_softc *sc;
16495 sc = device_get_softc(dev);
16497 BLOGD(sc, DBG_LOAD, "Starting detach...\n");
16500 if (ifp != NULL && ifp->if_vlantrunk != NULL) {
16501 BLOGE(sc, "Cannot detach while VLANs are in use.\n");
16505 /* stop the periodic callout */
16506 bxe_periodic_stop(sc);
16508 /* stop the chip taskqueue */
16509 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE);
16511 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task);
16512 taskqueue_free(sc->chip_tq);
16513 sc->chip_tq = NULL;
16516 /* stop and reset the controller if it was open */
16517 if (sc->state != BXE_STATE_CLOSED) {
16519 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE);
16520 BXE_CORE_UNLOCK(sc);
16523 /* release the network interface */
16525 ether_ifdetach(ifp);
16527 ifmedia_removeall(&sc->ifmedia);
16529 /* XXX do the following based on driver state... */
16531 /* free the host hardware/software hsi structures */
16532 bxe_free_hsi_mem(sc);
16535 bxe_free_ilt_mem(sc);
16537 /* release the interrupts */
16538 bxe_interrupt_free(sc);
16540 /* Release the mutexes*/
16541 bxe_release_mutexes(sc);
16543 /* Release the PCIe BAR mapped memory */
16544 bxe_deallocate_bars(sc);
16546 /* Release the FreeBSD interface. */
16547 if (sc->ifnet != NULL) {
16548 if_free(sc->ifnet);
16551 pci_disable_busmaster(dev);
16557 * Device shutdown function.
16559 * Stops and resets the controller.
16565 bxe_shutdown(device_t dev)
16567 struct bxe_softc *sc;
16569 sc = device_get_softc(dev);
16571 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n");
16573 /* stop the periodic callout */
16574 bxe_periodic_stop(sc);
16577 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE);
16578 BXE_CORE_UNLOCK(sc);
16584 bxe_igu_ack_sb(struct bxe_softc *sc,
16591 uint32_t igu_addr = sc->igu_base_addr;
16592 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
16593 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr);
16597 bxe_igu_clear_sb_gen(struct bxe_softc *sc,
16602 uint32_t data, ctl, cnt = 100;
16603 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
16604 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
16605 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
16606 uint32_t sb_bit = 1 << (idu_sb_id%32);
16607 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
16608 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
16610 /* Not supported in BC mode */
16611 if (CHIP_INT_MODE_IS_BC(sc)) {
16615 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup <<
16616 IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
16617 IGU_REGULAR_CLEANUP_SET |
16618 IGU_REGULAR_BCLEANUP);
16620 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) |
16621 (func_encode << IGU_CTRL_REG_FID_SHIFT) |
16622 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT));
16624 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16625 data, igu_addr_data);
16626 REG_WR(sc, igu_addr_data, data);
16628 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16629 BUS_SPACE_BARRIER_WRITE);
16632 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
16633 ctl, igu_addr_ctl);
16634 REG_WR(sc, igu_addr_ctl, ctl);
16636 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0,
16637 BUS_SPACE_BARRIER_WRITE);
16640 /* wait for clean up to finish */
16641 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {
16645 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {
16646 BLOGD(sc, DBG_LOAD,
16647 "Unable to finish IGU cleanup: "
16648 "idu_sb_id %d offset %d bit %d (cnt %d)\n",
16649 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
16654 bxe_igu_clear_sb(struct bxe_softc *sc,
16657 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/);
16666 /*******************/
16667 /* ECORE CALLBACKS */
16668 /*******************/
16671 bxe_reset_common(struct bxe_softc *sc)
16673 uint32_t val = 0x1400;
16676 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f);
16678 if (CHIP_IS_E3(sc)) {
16679 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
16680 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
16683 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val);
16687 bxe_common_init_phy(struct bxe_softc *sc)
16689 uint32_t shmem_base[2];
16690 uint32_t shmem2_base[2];
16692 /* Avoid common init in case MFW supports LFA */
16693 if (SHMEM2_RD(sc, size) >
16694 (uint32_t)offsetof(struct shmem2_region,
16695 lfa_host_addr[SC_PORT(sc)])) {
16699 shmem_base[0] = sc->devinfo.shmem_base;
16700 shmem2_base[0] = sc->devinfo.shmem2_base;
16702 if (!CHIP_IS_E1x(sc)) {
16703 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr);
16704 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr);
16708 elink_common_init_phy(sc, shmem_base, shmem2_base,
16709 sc->devinfo.chip_id, 0);
16710 BXE_PHY_UNLOCK(sc);
16714 bxe_pf_disable(struct bxe_softc *sc)
16716 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);
16718 val &= ~IGU_PF_CONF_FUNC_EN;
16720 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val);
16721 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
16722 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0);
16726 bxe_init_pxp(struct bxe_softc *sc)
16729 int r_order, w_order;
16731 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2);
16733 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl);
16735 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5);
16737 if (sc->mrrs == -1) {
16738 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12);
16740 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs);
16741 r_order = sc->mrrs;
16744 ecore_init_pxp_arb(sc, r_order, w_order);
16748 bxe_get_pretend_reg(struct bxe_softc *sc)
16750 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0;
16751 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base);
16752 return (base + (SC_ABS_FUNC(sc)) * stride);
16756 * Called only on E1H or E2.
16757 * When pretending to be PF, the pretend value is the function number 0..7.
16758 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
16762 bxe_pretend_func(struct bxe_softc *sc,
16763 uint16_t pretend_func_val)
16765 uint32_t pretend_reg;
16767 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) {
16771 /* get my own pretend register */
16772 pretend_reg = bxe_get_pretend_reg(sc);
16773 REG_WR(sc, pretend_reg, pretend_func_val);
16774 REG_RD(sc, pretend_reg);
16779 bxe_iov_init_dmae(struct bxe_softc *sc)
16783 BLOGD(sc, DBG_LOAD, "SRIOV is %s\n", IS_SRIOV(sc) ? "ON" : "OFF");
16785 if (!IS_SRIOV(sc)) {
16789 REG_WR(sc, DMAE_REG_BACKWARD_COMP_EN, 0);
16795 bxe_iov_init_ilt(struct bxe_softc *sc,
16801 struct ecore_ilt* ilt = sc->ilt;
16803 if (!IS_SRIOV(sc)) {
16807 /* set vfs ilt lines */
16808 for (i = 0; i < BXE_VF_CIDS/ILT_PAGE_CIDS ; i++) {
16809 struct hw_dma *hw_cxt = SC_VF_CXT_PAGE(sc,i);
16810 ilt->lines[line+i].page = hw_cxt->addr;
16811 ilt->lines[line+i].page_mapping = hw_cxt->mapping;
16812 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */
16820 bxe_iov_init_dq(struct bxe_softc *sc)
16824 if (!IS_SRIOV(sc)) {
16828 /* Set the DQ such that the CID reflect the abs_vfid */
16829 REG_WR(sc, DORQ_REG_VF_NORM_VF_BASE, 0);
16830 REG_WR(sc, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));
16833 * Set VFs starting CID. If its > 0 the preceding CIDs are belong to
16836 REG_WR(sc, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);
16838 /* The VF window size is the log2 of the max number of CIDs per VF */
16839 REG_WR(sc, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);
16842 * The VF doorbell size 0 - *B, 4 - 128B. We set it here to match
16843 * the Pf doorbell size although the 2 are independent.
16845 REG_WR(sc, DORQ_REG_VF_NORM_CID_OFST,
16846 BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT);
16849 * No security checks for now -
16850 * configure single rule (out of 16) mask = 0x1, value = 0x0,
16851 * CID range 0 - 0x1ffff
16853 REG_WR(sc, DORQ_REG_VF_TYPE_MASK_0, 1);
16854 REG_WR(sc, DORQ_REG_VF_TYPE_VALUE_0, 0);
16855 REG_WR(sc, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);
16856 REG_WR(sc, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);
16858 /* set the number of VF alllowed doorbells to the full DQ range */
16859 REG_WR(sc, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000);
16861 /* set the VF doorbell threshold */
16862 REG_WR(sc, DORQ_REG_VF_USAGE_CT_LIMIT, 4);
16866 /* send a NIG loopback debug packet */
16868 bxe_lb_pckt(struct bxe_softc *sc)
16870 uint32_t wb_write[3];
16872 /* Ethernet source and destination addresses */
16873 wb_write[0] = 0x55555555;
16874 wb_write[1] = 0x55555555;
16875 wb_write[2] = 0x20; /* SOP */
16876 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16878 /* NON-IP protocol */
16879 wb_write[0] = 0x09000000;
16880 wb_write[1] = 0x55555555;
16881 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
16882 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
16886 * Some of the internal memories are not directly readable from the driver.
16887 * To test them we send debug packets.
16890 bxe_int_mem_test(struct bxe_softc *sc)
16896 if (CHIP_REV_IS_FPGA(sc)) {
16898 } else if (CHIP_REV_IS_EMUL(sc)) {
16904 /* disable inputs of parser neighbor blocks */
16905 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16906 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16907 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16908 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16910 /* write 0 to parser credits for CFC search request */
16911 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16913 /* send Ethernet packet */
16916 /* TODO do i reset NIG statistic? */
16917 /* Wait until NIG register shows 1 packet of size 0x10 */
16918 count = 1000 * factor;
16920 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16921 val = *BXE_SP(sc, wb_data[0]);
16931 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16935 /* wait until PRS register shows 1 packet */
16936 count = (1000 * factor);
16938 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16948 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16952 /* Reset and init BRB, PRS */
16953 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
16955 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
16957 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
16958 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
16960 /* Disable inputs of parser neighbor blocks */
16961 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
16962 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
16963 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
16964 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
16966 /* Write 0 to parser credits for CFC search request */
16967 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
16969 /* send 10 Ethernet packets */
16970 for (i = 0; i < 10; i++) {
16974 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */
16975 count = (1000 * factor);
16977 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
16978 val = *BXE_SP(sc, wb_data[0]);
16988 BLOGE(sc, "NIG timeout val=0x%x\n", val);
16992 /* Wait until PRS register shows 2 packets */
16993 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
16995 BLOGE(sc, "PRS timeout val=0x%x\n", val);
16998 /* Write 1 to parser credits for CFC search request */
16999 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
17001 /* Wait until PRS register shows 3 packets */
17002 DELAY(10000 * factor);
17004 /* Wait until NIG register shows 1 packet of size 0x10 */
17005 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
17007 BLOGE(sc, "PRS timeout val=0x%x\n", val);
17010 /* clear NIG EOP FIFO */
17011 for (i = 0; i < 11; i++) {
17012 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
17015 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
17017 BLOGE(sc, "clear of NIG failed\n");
17021 /* Reset and init BRB, PRS, NIG */
17022 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
17024 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
17026 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17027 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17028 if (!CNIC_SUPPORT(sc)) {
17030 REG_WR(sc, PRS_REG_NIC_MODE, 1);
17033 /* Enable inputs of parser neighbor blocks */
17034 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
17035 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
17036 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
17037 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
17043 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
17050 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
17051 SHARED_HW_CFG_FAN_FAILURE_MASK);
17053 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) {
17057 * The fan failure mechanism is usually related to the PHY type since
17058 * the power consumption of the board is affected by the PHY. Currently,
17059 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
17061 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) {
17062 for (port = PORT_0; port < PORT_MAX; port++) {
17063 is_required |= elink_fan_failure_det_req(sc,
17064 sc->devinfo.shmem_base,
17065 sc->devinfo.shmem2_base,
17070 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required);
17072 if (is_required == 0) {
17076 /* Fan failure is indicated by SPIO 5 */
17077 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
17079 /* set to active low mode */
17080 val = REG_RD(sc, MISC_REG_SPIO_INT);
17081 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
17082 REG_WR(sc, MISC_REG_SPIO_INT, val);
17084 /* enable interrupt to signal the IGU */
17085 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17086 val |= MISC_SPIO_SPIO5;
17087 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
17091 bxe_enable_blocks_attention(struct bxe_softc *sc)
17095 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
17096 if (!CHIP_IS_E1x(sc)) {
17097 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40);
17099 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
17101 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17102 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17104 * mask read length error interrupts in brb for parser
17105 * (parsing unit and 'checksum and crc' unit)
17106 * these errors are legal (PU reads fixed length and CAC can cause
17107 * read length error on truncated packets)
17109 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00);
17110 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
17111 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
17112 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
17113 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
17114 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
17115 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */
17116 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */
17117 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
17118 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
17119 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
17120 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */
17121 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */
17122 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
17123 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
17124 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
17125 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
17126 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */
17127 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */
17129 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
17130 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
17131 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN);
17132 if (!CHIP_IS_E1x(sc)) {
17133 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
17134 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED);
17136 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val);
17138 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
17139 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
17140 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
17141 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */
17143 if (!CHIP_IS_E1x(sc)) {
17144 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
17145 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
17148 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
17149 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
17150 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */
17151 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
17155 * bxe_init_hw_common - initialize the HW at the COMMON phase.
17157 * @sc: driver handle
17160 bxe_init_hw_common(struct bxe_softc *sc)
17162 uint8_t abs_func_id;
17165 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n",
17169 * take the RESET lock to protect undi_unload flow from accessing
17170 * registers while we are resetting the chip
17172 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17174 bxe_reset_common(sc);
17176 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff);
17179 if (CHIP_IS_E3(sc)) {
17180 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
17181 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
17184 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val);
17186 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET);
17188 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON);
17189 BLOGD(sc, DBG_LOAD, "after misc block init\n");
17191 if (!CHIP_IS_E1x(sc)) {
17193 * 4-port mode or 2-port mode we need to turn off master-enable for
17194 * everyone. After that we turn it back on for self. So, we disregard
17195 * multi-function, and always disable all functions on the given path,
17196 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1
17198 for (abs_func_id = SC_PATH(sc);
17199 abs_func_id < (E2_FUNC_MAX * 2);
17200 abs_func_id += 2) {
17201 if (abs_func_id == SC_ABS_FUNC(sc)) {
17202 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17206 bxe_pretend_func(sc, abs_func_id);
17208 /* clear pf enable */
17209 bxe_pf_disable(sc);
17211 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17215 BLOGD(sc, DBG_LOAD, "after pf disable\n");
17217 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON);
17219 if (CHIP_IS_E1(sc)) {
17221 * enable HW interrupt from PXP on USDM overflow
17222 * bit 16 on INT_MASK_0
17224 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
17227 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON);
17230 #ifdef __BIG_ENDIAN
17231 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
17232 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
17233 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
17234 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
17235 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
17236 /* make sure this value is 0 */
17237 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
17239 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1);
17240 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
17241 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
17242 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
17243 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
17246 ecore_ilt_init_page_size(sc, INITOP_SET);
17248 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) {
17249 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
17252 /* let the HW do it's magic... */
17255 /* finish PXP init */
17256 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
17258 BLOGE(sc, "PXP2 CFG failed\n");
17261 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
17263 BLOGE(sc, "PXP2 RD_INIT failed\n");
17267 BLOGD(sc, DBG_LOAD, "after pxp init\n");
17270 * Timer bug workaround for E2 only. We need to set the entire ILT to have
17271 * entries with value "0" and valid bit on. This needs to be done by the
17272 * first PF that is loaded in a path (i.e. common phase)
17274 if (!CHIP_IS_E1x(sc)) {
17276 * In E2 there is a bug in the timers block that can cause function 6 / 7
17277 * (i.e. vnic3) to start even if it is marked as "scan-off".
17278 * This occurs when a different function (func2,3) is being marked
17279 * as "scan-off". Real-life scenario for example: if a driver is being
17280 * load-unloaded while func6,7 are down. This will cause the timer to access
17281 * the ilt, translate to a logical address and send a request to read/write.
17282 * Since the ilt for the function that is down is not valid, this will cause
17283 * a translation error which is unrecoverable.
17284 * The Workaround is intended to make sure that when this happens nothing
17285 * fatal will occur. The workaround:
17286 * 1. First PF driver which loads on a path will:
17287 * a. After taking the chip out of reset, by using pretend,
17288 * it will write "0" to the following registers of
17290 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
17291 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
17292 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
17293 * And for itself it will write '1' to
17294 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
17295 * dmae-operations (writing to pram for example.)
17296 * note: can be done for only function 6,7 but cleaner this
17298 * b. Write zero+valid to the entire ILT.
17299 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
17300 * VNIC3 (of that port). The range allocated will be the
17301 * entire ILT. This is needed to prevent ILT range error.
17302 * 2. Any PF driver load flow:
17303 * a. ILT update with the physical addresses of the allocated
17305 * b. Wait 20msec. - note that this timeout is needed to make
17306 * sure there are no requests in one of the PXP internal
17307 * queues with "old" ILT addresses.
17308 * c. PF enable in the PGLC.
17309 * d. Clear the was_error of the PF in the PGLC. (could have
17310 * occurred while driver was down)
17311 * e. PF enable in the CFC (WEAK + STRONG)
17312 * f. Timers scan enable
17313 * 3. PF driver unload flow:
17314 * a. Clear the Timers scan_en.
17315 * b. Polling for scan_on=0 for that PF.
17316 * c. Clear the PF enable bit in the PXP.
17317 * d. Clear the PF enable in the CFC (WEAK + STRONG)
17318 * e. Write zero+valid to all ILT entries (The valid bit must
17320 * f. If this is VNIC 3 of a port then also init
17321 * first_timers_ilt_entry to zero and last_timers_ilt_entry
17322 * to the last enrty in the ILT.
17325 * Currently the PF error in the PGLC is non recoverable.
17326 * In the future the there will be a recovery routine for this error.
17327 * Currently attention is masked.
17328 * Having an MCP lock on the load/unload process does not guarantee that
17329 * there is no Timer disable during Func6/7 enable. This is because the
17330 * Timers scan is currently being cleared by the MCP on FLR.
17331 * Step 2.d can be done only for PF6/7 and the driver can also check if
17332 * there is error before clearing it. But the flow above is simpler and
17334 * All ILT entries are written by zero+valid and not just PF6/7
17335 * ILT entries since in the future the ILT entries allocation for
17336 * PF-s might be dynamic.
17338 struct ilt_client_info ilt_cli;
17339 struct ecore_ilt ilt;
17341 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
17342 memset(&ilt, 0, sizeof(struct ecore_ilt));
17344 /* initialize dummy TM client */
17346 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
17347 ilt_cli.client_num = ILT_CLIENT_TM;
17350 * Step 1: set zeroes to all ilt page entries with valid bit on
17351 * Step 2: set the timers first/last ilt entry to point
17352 * to the entire range to prevent ILT range error for 3rd/4th
17353 * vnic (this code assumes existence of the vnic)
17355 * both steps performed by call to ecore_ilt_client_init_op()
17356 * with dummy TM client
17358 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
17359 * and his brother are split registers
17362 bxe_pretend_func(sc, (SC_PATH(sc) + 6));
17363 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR);
17364 bxe_pretend_func(sc, SC_ABS_FUNC(sc));
17366 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN);
17367 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN);
17368 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
17371 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
17372 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
17374 if (!CHIP_IS_E1x(sc)) {
17375 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 :
17376 (CHIP_REV_IS_FPGA(sc) ? 400 : 0);
17378 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON);
17379 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON);
17381 /* let the HW do it's magic... */
17384 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);
17385 } while (factor-- && (val != 1));
17388 BLOGE(sc, "ATC_INIT failed\n");
17393 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n");
17395 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON);
17397 bxe_iov_init_dmae(sc);
17399 /* clean the DMAE memory */
17400 sc->dmae_ready = 1;
17401 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1);
17403 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON);
17405 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON);
17407 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON);
17409 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON);
17411 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
17412 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
17413 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
17414 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
17416 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON);
17418 /* QM queues pointers table */
17419 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET);
17421 /* soft reset pulse */
17422 REG_WR(sc, QM_REG_SOFT_RESET, 1);
17423 REG_WR(sc, QM_REG_SOFT_RESET, 0);
17425 if (CNIC_SUPPORT(sc))
17426 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON);
17428 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON);
17429 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT);
17430 if (!CHIP_REV_IS_SLOW(sc)) {
17431 /* enable hw interrupt from doorbell Q */
17432 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
17435 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON);
17437 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON);
17438 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
17440 if (!CHIP_IS_E1(sc)) {
17441 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan);
17444 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) {
17445 if (IS_MF_AFEX(sc)) {
17447 * configure that AFEX and VLAN headers must be
17448 * received in AFEX mode
17450 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE);
17451 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA);
17452 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
17453 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
17454 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4);
17457 * Bit-map indicating which L2 hdrs may appear
17458 * after the basic Ethernet header
17460 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC,
17461 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17465 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON);
17466 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON);
17467 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON);
17468 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON);
17470 if (!CHIP_IS_E1x(sc)) {
17471 /* reset VFC memories */
17472 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17473 VFC_MEMORIES_RST_REG_CAM_RST |
17474 VFC_MEMORIES_RST_REG_RAM_RST);
17475 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
17476 VFC_MEMORIES_RST_REG_CAM_RST |
17477 VFC_MEMORIES_RST_REG_RAM_RST);
17482 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON);
17483 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON);
17484 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON);
17485 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON);
17487 /* sync semi rtc */
17488 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
17490 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
17493 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON);
17494 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON);
17495 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON);
17497 if (!CHIP_IS_E1x(sc)) {
17498 if (IS_MF_AFEX(sc)) {
17500 * configure that AFEX and VLAN headers must be
17501 * sent in AFEX mode
17503 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE);
17504 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA);
17505 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
17506 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
17507 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4);
17509 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC,
17510 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6);
17514 REG_WR(sc, SRC_REG_SOFT_RST, 1);
17516 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON);
17518 if (CNIC_SUPPORT(sc)) {
17519 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672);
17520 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
17521 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b);
17522 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a);
17523 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116);
17524 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
17525 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf);
17526 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
17527 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f);
17528 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7);
17530 REG_WR(sc, SRC_REG_SOFT_RST, 0);
17532 if (sizeof(union cdu_context) != 1024) {
17533 /* we currently assume that a context is 1024 bytes */
17534 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n",
17535 (long)sizeof(union cdu_context));
17538 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON);
17539 val = (4 << 24) + (0 << 12) + 1024;
17540 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
17542 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON);
17544 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
17545 /* enable context validation interrupt from CFC */
17546 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
17548 /* set the thresholds to prevent CFC/CDU race */
17549 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
17550 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON);
17552 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) {
17553 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36);
17556 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON);
17557 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON);
17559 /* Reset PCIE errors for debug */
17560 REG_WR(sc, 0x2814, 0xffffffff);
17561 REG_WR(sc, 0x3820, 0xffffffff);
17563 if (!CHIP_IS_E1x(sc)) {
17564 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
17565 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
17566 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
17567 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
17568 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
17569 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
17570 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
17571 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
17572 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
17573 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
17574 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
17577 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON);
17579 if (!CHIP_IS_E1(sc)) {
17580 /* in E3 this done in per-port section */
17581 if (!CHIP_IS_E3(sc))
17582 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc));
17585 if (CHIP_IS_E1H(sc)) {
17586 /* not applicable for E2 (and above ...) */
17587 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc));
17590 if (CHIP_REV_IS_SLOW(sc)) {
17594 /* finish CFC init */
17595 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
17597 BLOGE(sc, "CFC LL_INIT failed\n");
17600 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
17602 BLOGE(sc, "CFC AC_INIT failed\n");
17605 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
17607 BLOGE(sc, "CFC CAM_INIT failed\n");
17610 REG_WR(sc, CFC_REG_DEBUG0, 0);
17612 if (CHIP_IS_E1(sc)) {
17613 /* read NIG statistic to see if this is our first up since powerup */
17614 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
17615 val = *BXE_SP(sc, wb_data[0]);
17617 /* do internal memory self test */
17618 if ((val == 0) && bxe_int_mem_test(sc)) {
17619 BLOGE(sc, "internal mem self test failed\n");
17624 bxe_setup_fan_failure_detection(sc);
17626 /* clear PXP2 attentions */
17627 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
17629 bxe_enable_blocks_attention(sc);
17631 if (!CHIP_REV_IS_SLOW(sc)) {
17632 ecore_enable_blocks_parity(sc);
17635 if (!BXE_NOMCP(sc)) {
17636 if (CHIP_IS_E1x(sc)) {
17637 bxe_common_init_phy(sc);
17645 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase.
17647 * @sc: driver handle
17650 bxe_init_hw_common_chip(struct bxe_softc *sc)
17652 int rc = bxe_init_hw_common(sc);
17658 /* In E2 2-PORT mode, same ext phy is used for the two paths */
17659 if (!BXE_NOMCP(sc)) {
17660 bxe_common_init_phy(sc);
17667 bxe_init_hw_port(struct bxe_softc *sc)
17669 int port = SC_PORT(sc);
17670 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
17671 uint32_t low, high;
17674 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port);
17676 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
17678 ecore_init_block(sc, BLOCK_MISC, init_phase);
17679 ecore_init_block(sc, BLOCK_PXP, init_phase);
17680 ecore_init_block(sc, BLOCK_PXP2, init_phase);
17683 * Timers bug workaround: disables the pf_master bit in pglue at
17684 * common phase, we need to enable it here before any dmae access are
17685 * attempted. Therefore we manually added the enable-master to the
17686 * port phase (it also happens in the function phase)
17688 if (!CHIP_IS_E1x(sc)) {
17689 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
17692 ecore_init_block(sc, BLOCK_ATC, init_phase);
17693 ecore_init_block(sc, BLOCK_DMAE, init_phase);
17694 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
17695 ecore_init_block(sc, BLOCK_QM, init_phase);
17697 ecore_init_block(sc, BLOCK_TCM, init_phase);
17698 ecore_init_block(sc, BLOCK_UCM, init_phase);
17699 ecore_init_block(sc, BLOCK_CCM, init_phase);
17700 ecore_init_block(sc, BLOCK_XCM, init_phase);
17702 /* QM cid (connection) count */
17703 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET);
17705 if (CNIC_SUPPORT(sc)) {
17706 ecore_init_block(sc, BLOCK_TM, init_phase);
17707 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20);
17708 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
17711 ecore_init_block(sc, BLOCK_DORQ, init_phase);
17713 ecore_init_block(sc, BLOCK_BRB1, init_phase);
17715 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) {
17717 low = (BXE_ONE_PORT(sc) ? 160 : 246);
17718 } else if (sc->mtu > 4096) {
17719 if (BXE_ONE_PORT(sc)) {
17723 /* (24*1024 + val*4)/256 */
17724 low = (96 + (val / 64) + ((val % 64) ? 1 : 0));
17727 low = (BXE_ONE_PORT(sc) ? 80 : 160);
17729 high = (low + 56); /* 14*1024/256 */
17730 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
17731 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
17734 if (CHIP_IS_MODE_4_PORT(sc)) {
17735 REG_WR(sc, SC_PORT(sc) ?
17736 BRB1_REG_MAC_GUARANTIED_1 :
17737 BRB1_REG_MAC_GUARANTIED_0, 40);
17740 ecore_init_block(sc, BLOCK_PRS, init_phase);
17741 if (CHIP_IS_E3B0(sc)) {
17742 if (IS_MF_AFEX(sc)) {
17743 /* configure headers for AFEX mode */
17744 REG_WR(sc, SC_PORT(sc) ?
17745 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17746 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
17747 REG_WR(sc, SC_PORT(sc) ?
17748 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
17749 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
17750 REG_WR(sc, SC_PORT(sc) ?
17751 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
17752 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
17754 /* Ovlan exists only if we are in multi-function +
17755 * switch-dependent mode, in switch-independent there
17756 * is no ovlan headers
17758 REG_WR(sc, SC_PORT(sc) ?
17759 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
17760 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
17761 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6));
17765 ecore_init_block(sc, BLOCK_TSDM, init_phase);
17766 ecore_init_block(sc, BLOCK_CSDM, init_phase);
17767 ecore_init_block(sc, BLOCK_USDM, init_phase);
17768 ecore_init_block(sc, BLOCK_XSDM, init_phase);
17770 ecore_init_block(sc, BLOCK_TSEM, init_phase);
17771 ecore_init_block(sc, BLOCK_USEM, init_phase);
17772 ecore_init_block(sc, BLOCK_CSEM, init_phase);
17773 ecore_init_block(sc, BLOCK_XSEM, init_phase);
17775 ecore_init_block(sc, BLOCK_UPB, init_phase);
17776 ecore_init_block(sc, BLOCK_XPB, init_phase);
17778 ecore_init_block(sc, BLOCK_PBF, init_phase);
17780 if (CHIP_IS_E1x(sc)) {
17781 /* configure PBF to work without PAUSE mtu 9000 */
17782 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
17784 /* update threshold */
17785 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
17786 /* update init credit */
17787 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
17789 /* probe changes */
17790 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1);
17792 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0);
17795 if (CNIC_SUPPORT(sc)) {
17796 ecore_init_block(sc, BLOCK_SRC, init_phase);
17799 ecore_init_block(sc, BLOCK_CDU, init_phase);
17800 ecore_init_block(sc, BLOCK_CFC, init_phase);
17802 if (CHIP_IS_E1(sc)) {
17803 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
17804 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
17806 ecore_init_block(sc, BLOCK_HC, init_phase);
17808 ecore_init_block(sc, BLOCK_IGU, init_phase);
17810 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
17811 /* init aeu_mask_attn_func_0/1:
17812 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
17813 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
17814 * bits 4-7 are used for "per vn group attention" */
17815 val = IS_MF(sc) ? 0xF7 : 0x7;
17816 /* Enable DCBX attention for all but E1 */
17817 val |= CHIP_IS_E1(sc) ? 0 : 0x10;
17818 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
17820 ecore_init_block(sc, BLOCK_NIG, init_phase);
17822 if (!CHIP_IS_E1x(sc)) {
17823 /* Bit-map indicating which L2 hdrs may appear after the
17824 * basic Ethernet header
17826 if (IS_MF_AFEX(sc)) {
17827 REG_WR(sc, SC_PORT(sc) ?
17828 NIG_REG_P1_HDRS_AFTER_BASIC :
17829 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
17831 REG_WR(sc, SC_PORT(sc) ?
17832 NIG_REG_P1_HDRS_AFTER_BASIC :
17833 NIG_REG_P0_HDRS_AFTER_BASIC,
17834 IS_MF_SD(sc) ? 7 : 6);
17837 if (CHIP_IS_E3(sc)) {
17838 REG_WR(sc, SC_PORT(sc) ?
17839 NIG_REG_LLH1_MF_MODE :
17840 NIG_REG_LLH_MF_MODE, IS_MF(sc));
17843 if (!CHIP_IS_E3(sc)) {
17844 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
17847 if (!CHIP_IS_E1(sc)) {
17848 /* 0x2 disable mf_ov, 0x1 enable */
17849 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
17850 (IS_MF_SD(sc) ? 0x1 : 0x2));
17852 if (!CHIP_IS_E1x(sc)) {
17854 switch (sc->devinfo.mf_info.mf_mode) {
17855 case MULTI_FUNCTION_SD:
17858 case MULTI_FUNCTION_SI:
17859 case MULTI_FUNCTION_AFEX:
17864 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
17865 NIG_REG_LLH0_CLS_TYPE), val);
17867 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
17868 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
17869 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
17872 /* If SPIO5 is set to generate interrupts, enable it for this port */
17873 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
17874 if (val & MISC_SPIO_SPIO5) {
17875 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
17876 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
17877 val = REG_RD(sc, reg_addr);
17878 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
17879 REG_WR(sc, reg_addr, val);
17886 bxe_flr_clnup_reg_poll(struct bxe_softc *sc,
17889 uint32_t poll_count)
17891 uint32_t cur_cnt = poll_count;
17894 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {
17895 DELAY(FLR_WAIT_INTERVAL);
17902 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc,
17907 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt);
17910 BLOGE(sc, "%s usage count=%d\n", msg, val);
17917 /* Common routines with VF FLR cleanup */
17919 bxe_flr_clnup_poll_count(struct bxe_softc *sc)
17921 /* adjust polling timeout */
17922 if (CHIP_REV_IS_EMUL(sc)) {
17923 return (FLR_POLL_CNT * 2000);
17926 if (CHIP_REV_IS_FPGA(sc)) {
17927 return (FLR_POLL_CNT * 120);
17930 return (FLR_POLL_CNT);
17934 bxe_poll_hw_usage_counters(struct bxe_softc *sc,
17937 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
17938 if (bxe_flr_clnup_poll_hw_counter(sc,
17939 CFC_REG_NUM_LCIDS_INSIDE_PF,
17940 "CFC PF usage counter timed out",
17945 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
17946 if (bxe_flr_clnup_poll_hw_counter(sc,
17947 DORQ_REG_PF_USAGE_CNT,
17948 "DQ PF usage counter timed out",
17953 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
17954 if (bxe_flr_clnup_poll_hw_counter(sc,
17955 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc),
17956 "QM PF usage counter timed out",
17961 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
17962 if (bxe_flr_clnup_poll_hw_counter(sc,
17963 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
17964 "Timers VNIC usage counter timed out",
17969 if (bxe_flr_clnup_poll_hw_counter(sc,
17970 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
17971 "Timers NUM_SCANS usage counter timed out",
17976 /* Wait DMAE PF usage counter to zero */
17977 if (bxe_flr_clnup_poll_hw_counter(sc,
17978 dmae_reg_go_c[INIT_DMAE_C(sc)],
17979 "DMAE dommand register timed out",
17987 #define OP_GEN_PARAM(param) \
17988 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
17989 #define OP_GEN_TYPE(type) \
17990 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
17991 #define OP_GEN_AGG_VECT(index) \
17992 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
17995 bxe_send_final_clnup(struct bxe_softc *sc,
17996 uint8_t clnup_func,
17999 uint32_t op_gen_command = 0;
18000 uint32_t comp_addr = (BAR_CSTRORM_INTMEM +
18001 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func));
18004 if (REG_RD(sc, comp_addr)) {
18005 BLOGE(sc, "Cleanup complete was not 0 before sending\n");
18009 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
18010 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
18011 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
18012 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
18014 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n");
18015 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command);
18017 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) {
18018 BLOGE(sc, "FW final cleanup did not succeed\n");
18019 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n",
18020 (REG_RD(sc, comp_addr)));
18021 bxe_panic(sc, ("FLR cleanup failed\n"));
18025 /* Zero completion for nxt FLR */
18026 REG_WR(sc, comp_addr, 0);
18032 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc,
18033 struct pbf_pN_buf_regs *regs,
18034 uint32_t poll_count)
18036 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start;
18037 uint32_t cur_cnt = poll_count;
18039 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);
18040 crd = crd_start = REG_RD(sc, regs->crd);
18041 init_crd = REG_RD(sc, regs->init_crd);
18043 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
18044 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd);
18045 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
18047 while ((crd != init_crd) &&
18048 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) <
18049 (init_crd - crd_start))) {
18051 DELAY(FLR_WAIT_INTERVAL);
18052 crd = REG_RD(sc, regs->crd);
18053 crd_freed = REG_RD(sc, regs->crd_freed);
18055 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN);
18056 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd);
18057 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed);
18062 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n",
18063 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
18067 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc,
18068 struct pbf_pN_cmd_regs *regs,
18069 uint32_t poll_count)
18071 uint32_t occup, to_free, freed, freed_start;
18072 uint32_t cur_cnt = poll_count;
18074 occup = to_free = REG_RD(sc, regs->lines_occup);
18075 freed = freed_start = REG_RD(sc, regs->lines_freed);
18077 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
18078 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
18081 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) {
18083 DELAY(FLR_WAIT_INTERVAL);
18084 occup = REG_RD(sc, regs->lines_occup);
18085 freed = REG_RD(sc, regs->lines_freed);
18087 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN);
18088 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
18089 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
18094 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n",
18095 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
18099 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count)
18101 struct pbf_pN_cmd_regs cmd_regs[] = {
18102 {0, (CHIP_IS_E3B0(sc)) ?
18103 PBF_REG_TQ_OCCUPANCY_Q0 :
18104 PBF_REG_P0_TQ_OCCUPANCY,
18105 (CHIP_IS_E3B0(sc)) ?
18106 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
18107 PBF_REG_P0_TQ_LINES_FREED_CNT},
18108 {1, (CHIP_IS_E3B0(sc)) ?
18109 PBF_REG_TQ_OCCUPANCY_Q1 :
18110 PBF_REG_P1_TQ_OCCUPANCY,
18111 (CHIP_IS_E3B0(sc)) ?
18112 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
18113 PBF_REG_P1_TQ_LINES_FREED_CNT},
18114 {4, (CHIP_IS_E3B0(sc)) ?
18115 PBF_REG_TQ_OCCUPANCY_LB_Q :
18116 PBF_REG_P4_TQ_OCCUPANCY,
18117 (CHIP_IS_E3B0(sc)) ?
18118 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
18119 PBF_REG_P4_TQ_LINES_FREED_CNT}
18122 struct pbf_pN_buf_regs buf_regs[] = {
18123 {0, (CHIP_IS_E3B0(sc)) ?
18124 PBF_REG_INIT_CRD_Q0 :
18125 PBF_REG_P0_INIT_CRD ,
18126 (CHIP_IS_E3B0(sc)) ?
18127 PBF_REG_CREDIT_Q0 :
18129 (CHIP_IS_E3B0(sc)) ?
18130 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
18131 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
18132 {1, (CHIP_IS_E3B0(sc)) ?
18133 PBF_REG_INIT_CRD_Q1 :
18134 PBF_REG_P1_INIT_CRD,
18135 (CHIP_IS_E3B0(sc)) ?
18136 PBF_REG_CREDIT_Q1 :
18138 (CHIP_IS_E3B0(sc)) ?
18139 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
18140 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
18141 {4, (CHIP_IS_E3B0(sc)) ?
18142 PBF_REG_INIT_CRD_LB_Q :
18143 PBF_REG_P4_INIT_CRD,
18144 (CHIP_IS_E3B0(sc)) ?
18145 PBF_REG_CREDIT_LB_Q :
18147 (CHIP_IS_E3B0(sc)) ?
18148 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
18149 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
18154 /* Verify the command queues are flushed P0, P1, P4 */
18155 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) {
18156 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count);
18159 /* Verify the transmission buffers are flushed P0, P1, P4 */
18160 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) {
18161 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count);
18166 bxe_hw_enable_status(struct bxe_softc *sc)
18170 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);
18171 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
18173 val = REG_RD(sc, PBF_REG_DISABLE_PF);
18174 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val);
18176 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);
18177 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
18179 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);
18180 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
18182 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
18183 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
18185 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
18186 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
18188 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
18189 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
18191 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
18192 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val);
18196 bxe_pf_flr_clnup(struct bxe_softc *sc)
18198 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc);
18200 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc));
18202 /* Re-enable PF target read access */
18203 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
18205 /* Poll HW usage counters */
18206 BLOGD(sc, DBG_LOAD, "Polling usage counters\n");
18207 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) {
18211 /* Zero the igu 'trailing edge' and 'leading edge' */
18213 /* Send the FW cleanup command */
18214 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) {
18220 /* Verify TX hw is flushed */
18221 bxe_tx_hw_flushed(sc, poll_cnt);
18223 /* Wait 100ms (not adjusted according to platform) */
18226 /* Verify no pending pci transactions */
18227 if (bxe_is_pcie_pending(sc)) {
18228 BLOGE(sc, "PCIE Transactions still pending\n");
18232 bxe_hw_enable_status(sc);
18235 * Master enable - Due to WB DMAE writes performed before this
18236 * register is re-initialized as part of the regular function init
18238 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18245 bxe_init_searcher(struct bxe_softc *sc)
18247 int port = SC_PORT(sc);
18248 ecore_src_init_t2(sc, sc->t2, sc->t2_mapping, SRC_CONN_NUM);
18249 /* T1 hash bits value determines the T1 number of entries */
18250 REG_WR(sc, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
18255 bxe_init_hw_func(struct bxe_softc *sc)
18257 int port = SC_PORT(sc);
18258 int func = SC_FUNC(sc);
18259 int init_phase = PHASE_PF0 + func;
18260 struct ecore_ilt *ilt = sc->ilt;
18261 uint16_t cdu_ilt_start;
18262 uint32_t addr, val;
18263 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr;
18264 int i, main_mem_width, rc;
18266 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func);
18269 if (!CHIP_IS_E1x(sc)) {
18270 rc = bxe_pf_flr_clnup(sc);
18272 BLOGE(sc, "FLR cleanup failed!\n");
18273 // XXX bxe_fw_dump(sc);
18274 // XXX bxe_idle_chk(sc);
18279 /* set MSI reconfigure capability */
18280 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18281 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
18282 val = REG_RD(sc, addr);
18283 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
18284 REG_WR(sc, addr, val);
18287 ecore_init_block(sc, BLOCK_PXP, init_phase);
18288 ecore_init_block(sc, BLOCK_PXP2, init_phase);
18291 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
18294 if (IS_SRIOV(sc)) {
18295 cdu_ilt_start += BXE_FIRST_VF_CID/ILT_PAGE_CIDS;
18297 cdu_ilt_start = bxe_iov_init_ilt(sc, cdu_ilt_start);
18299 #if (BXE_FIRST_VF_CID > 0)
18301 * If BXE_FIRST_VF_CID > 0 then the PF L2 cids precedes
18302 * those of the VFs, so start line should be reset
18304 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
18308 for (i = 0; i < L2_ILT_LINES(sc); i++) {
18309 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt;
18310 ilt->lines[cdu_ilt_start + i].page_mapping =
18311 sc->context[i].vcxt_dma.paddr;
18312 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size;
18314 ecore_ilt_init_op(sc, INITOP_SET);
18317 if (!CONFIGURE_NIC_MODE(sc)) {
18318 bxe_init_searcher(sc);
18319 REG_WR(sc, PRS_REG_NIC_MODE, 0);
18320 BLOGD(sc, DBG_LOAD, "NIC MODE disabled\n");
18325 REG_WR(sc, PRS_REG_NIC_MODE, 1);
18326 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n");
18329 if (!CHIP_IS_E1x(sc)) {
18330 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN;
18332 /* Turn on a single ISR mode in IGU if driver is going to use
18335 if (sc->interrupt_mode != INTR_MODE_MSIX) {
18336 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
18340 * Timers workaround bug: function init part.
18341 * Need to wait 20msec after initializing ILT,
18342 * needed to make sure there are no requests in
18343 * one of the PXP internal queues with "old" ILT addresses
18348 * Master enable - Due to WB DMAE writes performed before this
18349 * register is re-initialized as part of the regular function
18352 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
18353 /* Enable the function in IGU */
18354 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf);
18357 sc->dmae_ready = 1;
18359 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase);
18361 if (!CHIP_IS_E1x(sc))
18362 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
18364 ecore_init_block(sc, BLOCK_ATC, init_phase);
18365 ecore_init_block(sc, BLOCK_DMAE, init_phase);
18366 ecore_init_block(sc, BLOCK_NIG, init_phase);
18367 ecore_init_block(sc, BLOCK_SRC, init_phase);
18368 ecore_init_block(sc, BLOCK_MISC, init_phase);
18369 ecore_init_block(sc, BLOCK_TCM, init_phase);
18370 ecore_init_block(sc, BLOCK_UCM, init_phase);
18371 ecore_init_block(sc, BLOCK_CCM, init_phase);
18372 ecore_init_block(sc, BLOCK_XCM, init_phase);
18373 ecore_init_block(sc, BLOCK_TSEM, init_phase);
18374 ecore_init_block(sc, BLOCK_USEM, init_phase);
18375 ecore_init_block(sc, BLOCK_CSEM, init_phase);
18376 ecore_init_block(sc, BLOCK_XSEM, init_phase);
18378 if (!CHIP_IS_E1x(sc))
18379 REG_WR(sc, QM_REG_PF_EN, 1);
18381 if (!CHIP_IS_E1x(sc)) {
18382 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18383 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18384 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18385 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func);
18387 ecore_init_block(sc, BLOCK_QM, init_phase);
18389 ecore_init_block(sc, BLOCK_TM, init_phase);
18390 ecore_init_block(sc, BLOCK_DORQ, init_phase);
18392 bxe_iov_init_dq(sc);
18394 ecore_init_block(sc, BLOCK_BRB1, init_phase);
18395 ecore_init_block(sc, BLOCK_PRS, init_phase);
18396 ecore_init_block(sc, BLOCK_TSDM, init_phase);
18397 ecore_init_block(sc, BLOCK_CSDM, init_phase);
18398 ecore_init_block(sc, BLOCK_USDM, init_phase);
18399 ecore_init_block(sc, BLOCK_XSDM, init_phase);
18400 ecore_init_block(sc, BLOCK_UPB, init_phase);
18401 ecore_init_block(sc, BLOCK_XPB, init_phase);
18402 ecore_init_block(sc, BLOCK_PBF, init_phase);
18403 if (!CHIP_IS_E1x(sc))
18404 REG_WR(sc, PBF_REG_DISABLE_PF, 0);
18406 ecore_init_block(sc, BLOCK_CDU, init_phase);
18408 ecore_init_block(sc, BLOCK_CFC, init_phase);
18410 if (!CHIP_IS_E1x(sc))
18411 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1);
18414 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1);
18415 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc));
18418 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase);
18420 /* HC init per function */
18421 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18422 if (CHIP_IS_E1H(sc)) {
18423 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18425 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18426 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18428 ecore_init_block(sc, BLOCK_HC, init_phase);
18431 int num_segs, sb_idx, prod_offset;
18433 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
18435 if (!CHIP_IS_E1x(sc)) {
18436 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18437 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18440 ecore_init_block(sc, BLOCK_IGU, init_phase);
18442 if (!CHIP_IS_E1x(sc)) {
18446 * E2 mode: address 0-135 match to the mapping memory;
18447 * 136 - PF0 default prod; 137 - PF1 default prod;
18448 * 138 - PF2 default prod; 139 - PF3 default prod;
18449 * 140 - PF0 attn prod; 141 - PF1 attn prod;
18450 * 142 - PF2 attn prod; 143 - PF3 attn prod;
18451 * 144-147 reserved.
18453 * E1.5 mode - In backward compatible mode;
18454 * for non default SB; each even line in the memory
18455 * holds the U producer and each odd line hold
18456 * the C producer. The first 128 producers are for
18457 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
18458 * producers are for the DSB for each PF.
18459 * Each PF has five segments: (the order inside each
18460 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
18461 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
18462 * 144-147 attn prods;
18464 /* non-default-status-blocks */
18465 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18466 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
18467 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) {
18468 prod_offset = (sc->igu_base_sb + sb_idx) *
18471 for (i = 0; i < num_segs; i++) {
18472 addr = IGU_REG_PROD_CONS_MEMORY +
18473 (prod_offset + i) * 4;
18474 REG_WR(sc, addr, 0);
18476 /* send consumer update with value 0 */
18477 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx,
18478 USTORM_ID, 0, IGU_INT_NOP, 1);
18479 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx);
18482 /* default-status-blocks */
18483 num_segs = CHIP_INT_MODE_IS_BC(sc) ?
18484 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
18486 if (CHIP_IS_MODE_4_PORT(sc))
18487 dsb_idx = SC_FUNC(sc);
18489 dsb_idx = SC_VN(sc);
18491 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ?
18492 IGU_BC_BASE_DSB_PROD + dsb_idx :
18493 IGU_NORM_BASE_DSB_PROD + dsb_idx);
18496 * igu prods come in chunks of E1HVN_MAX (4) -
18497 * does not matters what is the current chip mode
18499 for (i = 0; i < (num_segs * E1HVN_MAX);
18501 addr = IGU_REG_PROD_CONS_MEMORY +
18502 (prod_offset + i)*4;
18503 REG_WR(sc, addr, 0);
18505 /* send consumer update with 0 */
18506 if (CHIP_INT_MODE_IS_BC(sc)) {
18507 bxe_ack_sb(sc, sc->igu_dsb_id,
18508 USTORM_ID, 0, IGU_INT_NOP, 1);
18509 bxe_ack_sb(sc, sc->igu_dsb_id,
18510 CSTORM_ID, 0, IGU_INT_NOP, 1);
18511 bxe_ack_sb(sc, sc->igu_dsb_id,
18512 XSTORM_ID, 0, IGU_INT_NOP, 1);
18513 bxe_ack_sb(sc, sc->igu_dsb_id,
18514 TSTORM_ID, 0, IGU_INT_NOP, 1);
18515 bxe_ack_sb(sc, sc->igu_dsb_id,
18516 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18518 bxe_ack_sb(sc, sc->igu_dsb_id,
18519 USTORM_ID, 0, IGU_INT_NOP, 1);
18520 bxe_ack_sb(sc, sc->igu_dsb_id,
18521 ATTENTION_ID, 0, IGU_INT_NOP, 1);
18523 bxe_igu_clear_sb(sc, sc->igu_dsb_id);
18525 /* !!! these should become driver const once
18526 rf-tool supports split-68 const */
18527 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
18528 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
18529 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0);
18530 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0);
18531 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0);
18532 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0);
18536 /* Reset PCIE errors for debug */
18537 REG_WR(sc, 0x2114, 0xffffffff);
18538 REG_WR(sc, 0x2120, 0xffffffff);
18540 if (CHIP_IS_E1x(sc)) {
18541 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
18542 main_mem_base = HC_REG_MAIN_MEMORY +
18543 SC_PORT(sc) * (main_mem_size * 4);
18544 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
18545 main_mem_width = 8;
18547 val = REG_RD(sc, main_mem_prty_clr);
18549 BLOGD(sc, DBG_LOAD,
18550 "Parity errors in HC block during function init (0x%x)!\n",
18554 /* Clear "false" parity errors in MSI-X table */
18555 for (i = main_mem_base;
18556 i < main_mem_base + main_mem_size * 4;
18557 i += main_mem_width) {
18558 bxe_read_dmae(sc, i, main_mem_width / 4);
18559 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data),
18560 i, main_mem_width / 4);
18562 /* Clear HC parity attention */
18563 REG_RD(sc, main_mem_prty_clr);
18567 /* Enable STORMs SP logging */
18568 REG_WR8(sc, BAR_USTRORM_INTMEM +
18569 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18570 REG_WR8(sc, BAR_TSTRORM_INTMEM +
18571 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18572 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18573 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18574 REG_WR8(sc, BAR_XSTRORM_INTMEM +
18575 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1);
18578 elink_phy_probe(&sc->link_params);
18584 bxe_link_reset(struct bxe_softc *sc)
18586 if (!BXE_NOMCP(sc)) {
18588 elink_lfa_reset(&sc->link_params, &sc->link_vars);
18589 BXE_PHY_UNLOCK(sc);
18591 if (!CHIP_REV_IS_SLOW(sc)) {
18592 BLOGW(sc, "Bootcode is missing - cannot reset link\n");
18598 bxe_reset_port(struct bxe_softc *sc)
18600 int port = SC_PORT(sc);
18603 /* reset physical Link */
18604 bxe_link_reset(sc);
18606 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
18608 /* Do not rcv packets to BRB */
18609 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
18610 /* Do not direct rcv packets that are not for MCP to the BRB */
18611 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
18612 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
18614 /* Configure AEU */
18615 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
18619 /* Check for BRB port occupancy */
18620 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
18622 BLOGD(sc, DBG_LOAD,
18623 "BRB1 is not empty, %d blocks are occupied\n", val);
18626 /* TODO: Close Doorbell port? */
18630 bxe_ilt_wr(struct bxe_softc *sc,
18635 uint32_t wb_write[2];
18637 if (CHIP_IS_E1(sc)) {
18638 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
18640 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
18643 wb_write[0] = ONCHIP_ADDR1(addr);
18644 wb_write[1] = ONCHIP_ADDR2(addr);
18645 REG_WR_DMAE(sc, reg, wb_write, 2);
18649 bxe_clear_func_ilt(struct bxe_softc *sc,
18652 uint32_t i, base = FUNC_ILT_BASE(func);
18653 for (i = base; i < base + ILT_PER_FUNC; i++) {
18654 bxe_ilt_wr(sc, i, 0);
18659 bxe_reset_func(struct bxe_softc *sc)
18661 struct bxe_fastpath *fp;
18662 int port = SC_PORT(sc);
18663 int func = SC_FUNC(sc);
18666 /* Disable the function in the FW */
18667 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
18668 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
18669 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
18670 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
18673 FOR_EACH_ETH_QUEUE(sc, i) {
18675 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18676 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
18681 if (CNIC_LOADED(sc)) {
18683 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18684 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
18685 (bxe_cnic_fw_sb_id(sc)), SB_DISABLED);
18690 REG_WR8(sc, BAR_CSTRORM_INTMEM +
18691 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
18694 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) {
18695 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0);
18698 /* Configure IGU */
18699 if (sc->devinfo.int_block == INT_BLOCK_HC) {
18700 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0);
18701 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0);
18703 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0);
18704 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0);
18707 if (CNIC_LOADED(sc)) {
18708 /* Disable Timer scan */
18709 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
18711 * Wait for at least 10ms and up to 2 second for the timers
18714 for (i = 0; i < 200; i++) {
18716 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))
18722 bxe_clear_func_ilt(sc, func);
18725 * Timers workaround bug for E2: if this is vnic-3,
18726 * we need to set the entire ilt range for this timers.
18728 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) {
18729 struct ilt_client_info ilt_cli;
18730 /* use dummy TM client */
18731 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
18733 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
18734 ilt_cli.client_num = ILT_CLIENT_TM;
18736 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR);
18739 /* this assumes that reset_port() called before reset_func()*/
18740 if (!CHIP_IS_E1x(sc)) {
18741 bxe_pf_disable(sc);
18744 sc->dmae_ready = 0;
18748 bxe_gunzip_init(struct bxe_softc *sc)
18754 bxe_gunzip_end(struct bxe_softc *sc)
18760 bxe_init_firmware(struct bxe_softc *sc)
18762 if (CHIP_IS_E1(sc)) {
18763 ecore_init_e1_firmware(sc);
18764 sc->iro_array = e1_iro_arr;
18765 } else if (CHIP_IS_E1H(sc)) {
18766 ecore_init_e1h_firmware(sc);
18767 sc->iro_array = e1h_iro_arr;
18768 } else if (!CHIP_IS_E1x(sc)) {
18769 ecore_init_e2_firmware(sc);
18770 sc->iro_array = e2_iro_arr;
18772 BLOGE(sc, "Unsupported chip revision\n");
18780 bxe_release_firmware(struct bxe_softc *sc)
18787 ecore_gunzip(struct bxe_softc *sc,
18788 const uint8_t *zbuf,
18791 /* XXX : Implement... */
18792 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n");
18797 ecore_reg_wr_ind(struct bxe_softc *sc,
18801 bxe_reg_wr_ind(sc, addr, val);
18805 ecore_write_dmae_phys_len(struct bxe_softc *sc,
18806 bus_addr_t phys_addr,
18810 bxe_write_dmae_phys_len(sc, phys_addr, addr, len);
18814 ecore_storm_memset_struct(struct bxe_softc *sc,
18820 for (i = 0; i < size/4; i++) {
18821 REG_WR(sc, addr + (i * 4), data[i]);