1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82541EI Gigabit Ethernet Controller
37 * 82541ER Gigabit Ethernet Controller
38 * 82541GI Gigabit Ethernet Controller
39 * 82541PI Gigabit Ethernet Controller
40 * 82547EI Gigabit Ethernet Controller
41 * 82547GI Gigabit Ethernet Controller
44 #include "e1000_api.h"
46 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
47 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
48 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
49 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
50 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
51 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
53 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
54 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
55 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
56 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
57 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
59 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
60 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
62 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw);
63 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
65 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
66 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
68 static const u16 e1000_igp_cable_length_table[] =
69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
78 (sizeof(e1000_igp_cable_length_table) / \
79 sizeof(e1000_igp_cable_length_table[0]))
82 * e1000_init_phy_params_82541 - Init PHY func ptrs.
83 * @hw: pointer to the HW structure
85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
87 struct e1000_phy_info *phy = &hw->phy;
88 s32 ret_val = E1000_SUCCESS;
90 DEBUGFUNC("e1000_init_phy_params_82541");
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 phy->reset_delay_us = 10000;
95 phy->type = e1000_phy_igp;
97 /* Function Pointers */
98 phy->ops.check_polarity = e1000_check_polarity_igp;
99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
102 phy->ops.get_info = e1000_get_phy_info_igp;
103 phy->ops.read_reg = e1000_read_phy_reg_igp;
104 phy->ops.reset = e1000_phy_hw_reset_82541;
105 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
106 phy->ops.write_reg = e1000_write_phy_reg_igp;
107 phy->ops.power_up = e1000_power_up_phy_copper;
108 phy->ops.power_down = e1000_power_down_phy_copper_82541;
110 ret_val = e1000_get_phy_id(hw);
115 if (phy->id != IGP01E1000_I_PHY_ID) {
116 ret_val = -E1000_ERR_PHY;
125 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
126 * @hw: pointer to the HW structure
128 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
130 struct e1000_nvm_info *nvm = &hw->nvm;
131 s32 ret_val = E1000_SUCCESS;
132 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
135 DEBUGFUNC("e1000_init_nvm_params_82541");
137 switch (nvm->override) {
138 case e1000_nvm_override_spi_large:
139 nvm->type = e1000_nvm_eeprom_spi;
140 eecd |= E1000_EECD_ADDR_BITS;
142 case e1000_nvm_override_spi_small:
143 nvm->type = e1000_nvm_eeprom_spi;
144 eecd &= ~E1000_EECD_ADDR_BITS;
146 case e1000_nvm_override_microwire_large:
147 nvm->type = e1000_nvm_eeprom_microwire;
148 eecd |= E1000_EECD_SIZE;
150 case e1000_nvm_override_microwire_small:
151 nvm->type = e1000_nvm_eeprom_microwire;
152 eecd &= ~E1000_EECD_SIZE;
155 nvm->type = eecd & E1000_EECD_TYPE
156 ? e1000_nvm_eeprom_spi
157 : e1000_nvm_eeprom_microwire;
161 if (nvm->type == e1000_nvm_eeprom_spi) {
162 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
165 nvm->opcode_bits = 8;
166 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
169 /* Function Pointers */
170 nvm->ops.acquire = e1000_acquire_nvm_generic;
171 nvm->ops.read = e1000_read_nvm_spi;
172 nvm->ops.release = e1000_release_nvm_generic;
173 nvm->ops.update = e1000_update_nvm_checksum_generic;
174 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
175 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
176 nvm->ops.write = e1000_write_nvm_spi;
179 * nvm->word_size must be discovered after the pointers
180 * are set so we can verify the size from the nvm image
181 * itself. Temporarily set it to a dummy value so the
185 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
188 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
190 * if size != 0, it can be added to a constant and become
191 * the left-shift value to set the word_size. Otherwise,
192 * word_size stays at 64.
195 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
196 nvm->word_size = 1 << size;
199 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
201 nvm->delay_usec = 50;
202 nvm->opcode_bits = 3;
203 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
206 /* Function Pointers */
207 nvm->ops.acquire = e1000_acquire_nvm_generic;
208 nvm->ops.read = e1000_read_nvm_microwire;
209 nvm->ops.release = e1000_release_nvm_generic;
210 nvm->ops.update = e1000_update_nvm_checksum_generic;
211 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
212 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
213 nvm->ops.write = e1000_write_nvm_microwire;
221 * e1000_init_mac_params_82541 - Init MAC func ptrs.
222 * @hw: pointer to the HW structure
224 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
226 struct e1000_mac_info *mac = &hw->mac;
228 DEBUGFUNC("e1000_init_mac_params_82541");
231 hw->phy.media_type = e1000_media_type_copper;
232 /* Set mta register count */
233 mac->mta_reg_count = 128;
234 /* Set rar entry count */
235 mac->rar_entry_count = E1000_RAR_ENTRIES;
236 /* Set if part includes ASF firmware */
237 mac->asf_firmware_present = TRUE;
239 /* Function Pointers */
241 /* bus type/speed/width */
242 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
244 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
246 mac->ops.reset_hw = e1000_reset_hw_82541;
247 /* hw initialization */
248 mac->ops.init_hw = e1000_init_hw_82541;
250 mac->ops.setup_link = e1000_setup_link_generic;
251 /* physical interface link setup */
252 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
254 mac->ops.check_for_link = e1000_check_for_link_82541;
256 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
257 /* multicast address update */
258 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
260 mac->ops.write_vfta = e1000_write_vfta_generic;
262 mac->ops.clear_vfta = e1000_clear_vfta_generic;
263 /* read mac address */
264 mac->ops.read_mac_addr = e1000_read_mac_addr_82541;
266 mac->ops.id_led_init = e1000_id_led_init_generic;
268 mac->ops.setup_led = e1000_setup_led_82541;
270 mac->ops.cleanup_led = e1000_cleanup_led_82541;
271 /* turn on/off LED */
272 mac->ops.led_on = e1000_led_on_generic;
273 mac->ops.led_off = e1000_led_off_generic;
274 /* clear hardware counters */
275 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
277 return E1000_SUCCESS;
281 * e1000_init_function_pointers_82541 - Init func ptrs.
282 * @hw: pointer to the HW structure
284 * Called to initialize all function pointers and parameters.
286 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
288 DEBUGFUNC("e1000_init_function_pointers_82541");
290 hw->mac.ops.init_params = e1000_init_mac_params_82541;
291 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
292 hw->phy.ops.init_params = e1000_init_phy_params_82541;
296 * e1000_reset_hw_82541 - Reset hardware
297 * @hw: pointer to the HW structure
299 * This resets the hardware into a known state.
301 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
303 u32 ledctl, ctrl, manc;
305 DEBUGFUNC("e1000_reset_hw_82541");
307 DEBUGOUT("Masking off all interrupts\n");
308 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
310 E1000_WRITE_REG(hw, E1000_RCTL, 0);
311 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
312 E1000_WRITE_FLUSH(hw);
315 * Delay to allow any outstanding PCI transactions to complete
316 * before resetting the device.
320 ctrl = E1000_READ_REG(hw, E1000_CTRL);
322 /* Must reset the Phy before resetting the MAC */
323 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
324 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
328 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
329 switch (hw->mac.type) {
331 case e1000_82541_rev_2:
333 * These controllers can't ack the 64-bit write when
334 * issuing the reset, so we use IO-mapping as a
335 * workaround to issue the reset.
337 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
340 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
344 /* Wait for NVM reload */
347 /* Disable HW ARPs on ASF enabled adapters */
348 manc = E1000_READ_REG(hw, E1000_MANC);
349 manc &= ~E1000_MANC_ARP_EN;
350 E1000_WRITE_REG(hw, E1000_MANC, manc);
352 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
353 e1000_phy_init_script_82541(hw);
355 /* Configure activity LED after Phy reset */
356 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
357 ledctl &= IGP_ACTIVITY_LED_MASK;
358 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
359 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
362 /* Once again, mask the interrupts */
363 DEBUGOUT("Masking off all interrupts\n");
364 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
366 /* Clear any pending interrupt events. */
367 E1000_READ_REG(hw, E1000_ICR);
369 return E1000_SUCCESS;
373 * e1000_init_hw_82541 - Initialize hardware
374 * @hw: pointer to the HW structure
376 * This inits the hardware readying it for operation.
378 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
380 struct e1000_mac_info *mac = &hw->mac;
381 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
385 DEBUGFUNC("e1000_init_hw_82541");
387 /* Initialize identification LED */
388 ret_val = mac->ops.id_led_init(hw);
390 DEBUGOUT("Error initializing identification LED\n");
391 /* This is not fatal and we should not stop init due to this */
394 /* Storing the Speed Power Down value for later use */
395 ret_val = hw->phy.ops.read_reg(hw,
396 IGP01E1000_GMII_FIFO,
397 &dev_spec->spd_default);
401 /* Disabling VLAN filtering */
402 DEBUGOUT("Initializing the IEEE VLAN\n");
403 mac->ops.clear_vfta(hw);
405 /* Setup the receive address. */
406 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
408 /* Zero out the Multicast HASH table */
409 DEBUGOUT("Zeroing the MTA\n");
410 for (i = 0; i < mac->mta_reg_count; i++) {
411 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
413 * Avoid back to back register writes by adding the register
414 * read (flush). This is to protect against some strange
415 * bridge configurations that may issue Memory Write Block
416 * (MWB) to our register space.
418 E1000_WRITE_FLUSH(hw);
421 /* Setup link and flow control */
422 ret_val = mac->ops.setup_link(hw);
424 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
425 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
426 E1000_TXDCTL_FULL_TX_DESC_WB;
427 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
430 * Clear all of the statistics registers (clear on read). It is
431 * important that we do this after we have tried to establish link
432 * because the symbol error count will increment wildly if there
435 e1000_clear_hw_cntrs_82541(hw);
442 * e1000_get_link_up_info_82541 - Report speed and duplex
443 * @hw: pointer to the HW structure
444 * @speed: pointer to speed buffer
445 * @duplex: pointer to duplex buffer
447 * Retrieve the current speed and duplex configuration.
449 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
452 struct e1000_phy_info *phy = &hw->phy;
456 DEBUGFUNC("e1000_get_link_up_info_82541");
458 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
462 if (!phy->speed_downgraded)
466 * IGP01 PHY may advertise full duplex operation after speed
467 * downgrade even if it is operating at half duplex.
468 * Here we set the duplex settings to match the duplex in the
469 * link partner's capabilities.
471 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
475 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
476 *duplex = HALF_DUPLEX;
478 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
482 if (*speed == SPEED_100) {
483 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
484 *duplex = HALF_DUPLEX;
485 } else if (*speed == SPEED_10) {
486 if (!(data & NWAY_LPAR_10T_FD_CAPS))
487 *duplex = HALF_DUPLEX;
496 * e1000_phy_hw_reset_82541 - PHY hardware reset
497 * @hw: pointer to the HW structure
499 * Verify the reset block is not blocking us from resetting. Acquire
500 * semaphore (if necessary) and read/set/write the device control reset
501 * bit in the PHY. Wait the appropriate delay time for the device to
502 * reset and release the semaphore (if necessary).
504 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
509 DEBUGFUNC("e1000_phy_hw_reset_82541");
511 ret_val = e1000_phy_hw_reset_generic(hw);
515 e1000_phy_init_script_82541(hw);
517 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
518 /* Configure activity LED after PHY reset */
519 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
520 ledctl &= IGP_ACTIVITY_LED_MASK;
521 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
522 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
530 * e1000_setup_copper_link_82541 - Configure copper link settings
531 * @hw: pointer to the HW structure
533 * Calls the appropriate function to configure the link for auto-neg or forced
534 * speed and duplex. Then we check for link, once link is established calls
535 * to configure collision distance and flow control are called. If link is
536 * not established, we return -E1000_ERR_PHY (-2).
538 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
540 struct e1000_phy_info *phy = &hw->phy;
541 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
545 DEBUGFUNC("e1000_setup_copper_link_82541");
547 ctrl = E1000_READ_REG(hw, E1000_CTRL);
548 ctrl |= E1000_CTRL_SLU;
549 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
552 hw->phy.reset_disable = FALSE;
554 /* Earlier revs of the IGP phy require us to force MDI. */
555 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
556 dev_spec->dsp_config = e1000_dsp_config_disabled;
559 dev_spec->dsp_config = e1000_dsp_config_enabled;
562 ret_val = e1000_copper_link_setup_igp(hw);
566 if (hw->mac.autoneg) {
567 if (dev_spec->ffe_config == e1000_ffe_config_active)
568 dev_spec->ffe_config = e1000_ffe_config_enabled;
571 /* Configure activity LED after Phy reset */
572 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
573 ledctl &= IGP_ACTIVITY_LED_MASK;
574 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
575 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
577 ret_val = e1000_setup_copper_link_generic(hw);
584 * e1000_check_for_link_82541 - Check/Store link connection
585 * @hw: pointer to the HW structure
587 * This checks the link condition of the adapter and stores the
588 * results in the hw->mac structure.
590 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
592 struct e1000_mac_info *mac = &hw->mac;
596 DEBUGFUNC("e1000_check_for_link_82541");
599 * We only want to go out to the PHY registers to see if Auto-Neg
600 * has completed and/or if our link status has changed. The
601 * get_link_status flag is set upon receiving a Link Status
602 * Change or Rx Sequence Error interrupt.
604 if (!mac->get_link_status) {
605 ret_val = E1000_SUCCESS;
610 * First we want to see if the MII Status Register reports
611 * link. If so, then we want to get the current speed/duplex
614 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
619 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
620 goto out; /* No link detected */
623 mac->get_link_status = FALSE;
626 * Check if there was DownShift, must be checked
627 * immediately after link-up
629 e1000_check_downshift_generic(hw);
632 * If we are forcing speed/duplex, then we simply return since
633 * we have already determined whether we have link or not.
636 ret_val = -E1000_ERR_CONFIG;
640 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
643 * Auto-Neg is enabled. Auto Speed Detection takes care
644 * of MAC speed/duplex configuration. So we only need to
645 * configure Collision Distance in the MAC.
647 e1000_config_collision_dist_generic(hw);
650 * Configure Flow Control now that Auto-Neg has completed.
651 * First, we need to restore the desired flow control
652 * settings because we may have had to re-autoneg with a
653 * different link partner.
655 ret_val = e1000_config_fc_after_link_up_generic(hw);
657 DEBUGOUT("Error configuring flow control\n");
665 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
666 * @hw: pointer to the HW structure
667 * @link_up: boolean flag for link up status
669 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
672 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
673 * gigabit link is achieved to improve link quality.
675 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
678 struct e1000_phy_info *phy = &hw->phy;
679 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
682 u16 phy_data, phy_saved_data, speed, duplex, i;
683 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
684 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
685 {IGP01E1000_PHY_AGC_PARAM_A,
686 IGP01E1000_PHY_AGC_PARAM_B,
687 IGP01E1000_PHY_AGC_PARAM_C,
688 IGP01E1000_PHY_AGC_PARAM_D};
690 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
693 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
695 DEBUGOUT("Error getting link speed and duplex\n");
699 if (speed != SPEED_1000) {
700 ret_val = E1000_SUCCESS;
704 ret_val = phy->ops.get_cable_length(hw);
708 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
709 phy->min_cable_length >= 50) {
711 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
712 ret_val = phy->ops.read_reg(hw,
718 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
720 ret_val = phy->ops.write_reg(hw,
726 dev_spec->dsp_config = e1000_dsp_config_activated;
729 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
730 (phy->min_cable_length >= 50)) {
731 ret_val = E1000_SUCCESS;
735 /* clear previous idle error counts */
736 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
740 for (i = 0; i < ffe_idle_err_timeout; i++) {
742 ret_val = phy->ops.read_reg(hw,
748 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
749 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
750 dev_spec->ffe_config = e1000_ffe_config_active;
752 ret_val = phy->ops.write_reg(hw,
753 IGP01E1000_PHY_DSP_FFE,
754 IGP01E1000_PHY_DSP_FFE_CM_CP);
761 ffe_idle_err_timeout =
762 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
765 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
767 * Save off the current value of register 0x2F5B
768 * to be restored at the end of the routines.
770 ret_val = phy->ops.read_reg(hw,
776 /* Disable the PHY transmitter */
777 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
783 ret_val = phy->ops.write_reg(hw,
785 IGP01E1000_IEEE_FORCE_GIG);
788 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
789 ret_val = phy->ops.read_reg(hw,
795 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
796 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
798 ret_val = phy->ops.write_reg(hw,
805 ret_val = phy->ops.write_reg(hw,
807 IGP01E1000_IEEE_RESTART_AUTONEG);
813 /* Now enable the transmitter */
814 ret_val = phy->ops.write_reg(hw,
820 dev_spec->dsp_config = e1000_dsp_config_enabled;
823 if (dev_spec->ffe_config != e1000_ffe_config_active) {
824 ret_val = E1000_SUCCESS;
829 * Save off the current value of register 0x2F5B
830 * to be restored at the end of the routines.
832 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
836 /* Disable the PHY transmitter */
837 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
843 ret_val = phy->ops.write_reg(hw,
845 IGP01E1000_IEEE_FORCE_GIG);
849 ret_val = phy->ops.write_reg(hw,
850 IGP01E1000_PHY_DSP_FFE,
851 IGP01E1000_PHY_DSP_FFE_DEFAULT);
855 ret_val = phy->ops.write_reg(hw,
857 IGP01E1000_IEEE_RESTART_AUTONEG);
863 /* Now enable the transmitter */
864 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
869 dev_spec->ffe_config = e1000_ffe_config_enabled;
877 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
878 * @hw: pointer to the HW structure
880 * The automatic gain control (agc) normalizes the amplitude of the
881 * received signal, adjusting for the attenuation produced by the
882 * cable. By reading the AGC registers, which represent the
883 * combination of coarse and fine gain value, the value can be put
884 * into a lookup table to obtain the approximate cable length
887 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
889 struct e1000_phy_info *phy = &hw->phy;
890 s32 ret_val = E1000_SUCCESS;
892 u16 cur_agc_value, agc_value = 0;
893 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
894 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
895 {IGP01E1000_PHY_AGC_A,
896 IGP01E1000_PHY_AGC_B,
897 IGP01E1000_PHY_AGC_C,
898 IGP01E1000_PHY_AGC_D};
900 DEBUGFUNC("e1000_get_cable_length_igp_82541");
902 /* Read the AGC registers for all channels */
903 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
904 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
908 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
910 /* Bounds checking */
911 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
912 (cur_agc_value == 0)) {
913 ret_val = -E1000_ERR_PHY;
917 agc_value += cur_agc_value;
919 if (min_agc_value > cur_agc_value)
920 min_agc_value = cur_agc_value;
923 /* Remove the minimal AGC result for length < 50m */
924 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
925 agc_value -= min_agc_value;
926 /* Average the three remaining channels for the length. */
927 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
929 /* Average the channels for the length. */
930 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
933 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
934 IGP01E1000_AGC_RANGE)
935 ? (e1000_igp_cable_length_table[agc_value] -
936 IGP01E1000_AGC_RANGE)
938 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
939 IGP01E1000_AGC_RANGE;
941 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
948 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
949 * @hw: pointer to the HW structure
950 * @active: boolean used to enable/disable lplu
952 * Success returns 0, Failure returns 1
954 * The low power link up (lplu) state is set to the power management level D3
955 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
956 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
957 * is used during Dx states where the power conservation is most important.
958 * During driver activity, SmartSpeed should be enabled so performance is
961 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
963 struct e1000_phy_info *phy = &hw->phy;
967 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
969 switch (hw->mac.type) {
970 case e1000_82541_rev_2:
971 case e1000_82547_rev_2:
974 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
979 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
984 data &= ~IGP01E1000_GMII_FLEX_SPD;
985 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
990 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
991 * during Dx states where the power conservation is most
992 * important. During driver activity we should enable
993 * SmartSpeed, so performance is maintained.
995 if (phy->smart_speed == e1000_smart_speed_on) {
996 ret_val = phy->ops.read_reg(hw,
997 IGP01E1000_PHY_PORT_CONFIG,
1002 data |= IGP01E1000_PSCFR_SMART_SPEED;
1003 ret_val = phy->ops.write_reg(hw,
1004 IGP01E1000_PHY_PORT_CONFIG,
1008 } else if (phy->smart_speed == e1000_smart_speed_off) {
1009 ret_val = phy->ops.read_reg(hw,
1010 IGP01E1000_PHY_PORT_CONFIG,
1015 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1016 ret_val = phy->ops.write_reg(hw,
1017 IGP01E1000_PHY_PORT_CONFIG,
1022 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1023 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1024 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1025 data |= IGP01E1000_GMII_FLEX_SPD;
1026 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1030 /* When LPLU is enabled, we should disable SmartSpeed */
1031 ret_val = phy->ops.read_reg(hw,
1032 IGP01E1000_PHY_PORT_CONFIG,
1037 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1038 ret_val = phy->ops.write_reg(hw,
1039 IGP01E1000_PHY_PORT_CONFIG,
1048 * e1000_setup_led_82541 - Configures SW controllable LED
1049 * @hw: pointer to the HW structure
1051 * This prepares the SW controllable LED for use and saves the current state
1052 * of the LED so it can be later restored.
1054 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1056 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1059 DEBUGFUNC("e1000_setup_led_82541");
1061 ret_val = hw->phy.ops.read_reg(hw,
1062 IGP01E1000_GMII_FIFO,
1063 &dev_spec->spd_default);
1067 ret_val = hw->phy.ops.write_reg(hw,
1068 IGP01E1000_GMII_FIFO,
1069 (u16)(dev_spec->spd_default &
1070 ~IGP01E1000_GMII_SPD));
1074 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1081 * e1000_cleanup_led_82541 - Set LED config to default operation
1082 * @hw: pointer to the HW structure
1084 * Remove the current LED configuration and set the LED configuration
1085 * to the default value, saved from the EEPROM.
1087 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1089 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1092 DEBUGFUNC("e1000_cleanup_led_82541");
1094 ret_val = hw->phy.ops.write_reg(hw,
1095 IGP01E1000_GMII_FIFO,
1096 dev_spec->spd_default);
1100 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1107 * e1000_phy_init_script_82541 - Initialize GbE PHY
1108 * @hw: pointer to the HW structure
1110 * Initializes the IGP PHY.
1112 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1114 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1118 DEBUGFUNC("e1000_phy_init_script_82541");
1120 if (!dev_spec->phy_init_script) {
1121 ret_val = E1000_SUCCESS;
1125 /* Delay after phy reset to enable NVM configuration to load */
1129 * Save off the current value of register 0x2F5B to be restored at
1130 * the end of this routine.
1132 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1134 /* Disabled the PHY transmitter */
1135 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1139 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1143 switch (hw->mac.type) {
1146 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1148 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1150 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1152 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1154 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1156 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1158 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1160 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1162 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1164 case e1000_82541_rev_2:
1165 case e1000_82547_rev_2:
1166 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1172 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1176 /* Now enable the transmitter */
1177 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1179 if (hw->mac.type == e1000_82547) {
1180 u16 fused, fine, coarse;
1182 /* Move to analog registers page */
1183 hw->phy.ops.read_reg(hw,
1184 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1187 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1188 hw->phy.ops.read_reg(hw,
1189 IGP01E1000_ANALOG_FUSE_STATUS,
1192 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1193 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1195 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1196 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1197 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1198 } else if (coarse ==
1199 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1200 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1202 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1203 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1204 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1206 hw->phy.ops.write_reg(hw,
1207 IGP01E1000_ANALOG_FUSE_CONTROL,
1209 hw->phy.ops.write_reg(hw,
1210 IGP01E1000_ANALOG_FUSE_BYPASS,
1211 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1220 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1221 * @hw: pointer to the HW structure
1222 * @state: boolean value used to enable/disable PHY init script
1224 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1227 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1229 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1231 DEBUGFUNC("e1000_init_script_state_82541");
1233 if (hw->phy.type != e1000_phy_igp) {
1234 DEBUGOUT("Initialization script not necessary.\n");
1238 dev_spec->phy_init_script = state;
1245 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1246 * @hw: pointer to the HW structure
1248 * In the case of a PHY power down to save power, or to turn off link during a
1249 * driver unload, or wake on lan is not enabled, remove the link.
1251 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1253 /* If the management interface is not enabled, then power down */
1254 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1255 e1000_power_down_phy_copper(hw);
1261 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1262 * @hw: pointer to the HW structure
1264 * Clears the hardware counters by reading the counter registers.
1266 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1268 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1270 e1000_clear_hw_cntrs_base_generic(hw);
1272 E1000_READ_REG(hw, E1000_PRC64);
1273 E1000_READ_REG(hw, E1000_PRC127);
1274 E1000_READ_REG(hw, E1000_PRC255);
1275 E1000_READ_REG(hw, E1000_PRC511);
1276 E1000_READ_REG(hw, E1000_PRC1023);
1277 E1000_READ_REG(hw, E1000_PRC1522);
1278 E1000_READ_REG(hw, E1000_PTC64);
1279 E1000_READ_REG(hw, E1000_PTC127);
1280 E1000_READ_REG(hw, E1000_PTC255);
1281 E1000_READ_REG(hw, E1000_PTC511);
1282 E1000_READ_REG(hw, E1000_PTC1023);
1283 E1000_READ_REG(hw, E1000_PTC1522);
1285 E1000_READ_REG(hw, E1000_ALGNERRC);
1286 E1000_READ_REG(hw, E1000_RXERRC);
1287 E1000_READ_REG(hw, E1000_TNCRS);
1288 E1000_READ_REG(hw, E1000_CEXTERR);
1289 E1000_READ_REG(hw, E1000_TSCTC);
1290 E1000_READ_REG(hw, E1000_TSCTFC);
1292 E1000_READ_REG(hw, E1000_MGTPRC);
1293 E1000_READ_REG(hw, E1000_MGTPDC);
1294 E1000_READ_REG(hw, E1000_MGTPTC);
1298 * e1000_read_mac_addr_82541 - Read device MAC address
1299 * @hw: pointer to the HW structure
1301 * Reads the device MAC address from the EEPROM and stores the value.
1303 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw)
1305 s32 ret_val = E1000_SUCCESS;
1306 u16 offset, nvm_data, i;
1308 DEBUGFUNC("e1000_read_mac_addr");
1310 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1312 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1314 DEBUGOUT("NVM Read Error\n");
1317 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1318 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1321 for (i = 0; i < ETH_ADDR_LEN; i++)
1322 hw->mac.addr[i] = hw->mac.perm_addr[i];