1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "e1000_api.h"
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
68 * Setups up the function pointers to no-op functions
70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.read_reg = e1000_null_read_reg;
86 phy->ops.read_reg_locked = e1000_null_read_reg;
87 phy->ops.release = e1000_null_phy_generic;
88 phy->ops.reset = e1000_null_ops_generic;
89 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
90 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
91 phy->ops.write_reg = e1000_null_write_reg;
92 phy->ops.write_reg_locked = e1000_null_write_reg;
93 phy->ops.power_up = e1000_null_phy_generic;
94 phy->ops.power_down = e1000_null_phy_generic;
95 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
99 * e1000_null_read_reg - No-op function, return 0
100 * @hw: pointer to the HW structure
102 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
104 DEBUGFUNC("e1000_null_read_reg");
105 return E1000_SUCCESS;
109 * e1000_null_phy_generic - No-op function, return void
110 * @hw: pointer to the HW structure
112 void e1000_null_phy_generic(struct e1000_hw *hw)
114 DEBUGFUNC("e1000_null_phy_generic");
119 * e1000_null_lplu_state - No-op function, return 0
120 * @hw: pointer to the HW structure
122 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
124 DEBUGFUNC("e1000_null_lplu_state");
125 return E1000_SUCCESS;
129 * e1000_null_write_reg - No-op function, return 0
130 * @hw: pointer to the HW structure
132 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
134 DEBUGFUNC("e1000_null_write_reg");
135 return E1000_SUCCESS;
139 * e1000_check_reset_block_generic - Check if PHY reset is blocked
140 * @hw: pointer to the HW structure
142 * Read the PHY management control register and check whether a PHY reset
143 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
144 * return E1000_BLK_PHY_RESET (12).
146 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
150 DEBUGFUNC("e1000_check_reset_block");
152 manc = E1000_READ_REG(hw, E1000_MANC);
154 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
155 E1000_BLK_PHY_RESET : E1000_SUCCESS;
159 * e1000_get_phy_id - Retrieve the PHY ID and revision
160 * @hw: pointer to the HW structure
162 * Reads the PHY registers and stores the PHY ID and possibly the PHY
163 * revision in the hardware structure.
165 s32 e1000_get_phy_id(struct e1000_hw *hw)
167 struct e1000_phy_info *phy = &hw->phy;
168 s32 ret_val = E1000_SUCCESS;
172 DEBUGFUNC("e1000_get_phy_id");
174 if (!(phy->ops.read_reg))
177 while (retry_count < 2) {
178 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
182 phy->id = (u32)(phy_id << 16);
184 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
188 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
189 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
191 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
201 * e1000_phy_reset_dsp_generic - Reset PHY DSP
202 * @hw: pointer to the HW structure
204 * Reset the digital signal processor.
206 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
208 s32 ret_val = E1000_SUCCESS;
210 DEBUGFUNC("e1000_phy_reset_dsp_generic");
212 if (!(hw->phy.ops.write_reg))
215 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
219 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
226 * e1000_read_phy_reg_mdic - Read MDI control register
227 * @hw: pointer to the HW structure
228 * @offset: register offset to be read
229 * @data: pointer to the read data
231 * Reads the MDI control register in the PHY at offset and stores the
232 * information read to data.
234 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
236 struct e1000_phy_info *phy = &hw->phy;
238 s32 ret_val = E1000_SUCCESS;
240 DEBUGFUNC("e1000_read_phy_reg_mdic");
242 if (offset > MAX_PHY_REG_ADDRESS) {
243 DEBUGOUT1("PHY Address %d is out of range\n", offset);
244 return -E1000_ERR_PARAM;
248 * Set up Op-code, Phy Address, and register offset in the MDI
249 * Control register. The MAC will take care of interfacing with the
250 * PHY to retrieve the desired data.
252 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
253 (phy->addr << E1000_MDIC_PHY_SHIFT) |
254 (E1000_MDIC_OP_READ));
256 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
259 * Poll the ready bit to see if the MDI read completed
260 * Increasing the time out as testing showed failures with
263 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
265 mdic = E1000_READ_REG(hw, E1000_MDIC);
266 if (mdic & E1000_MDIC_READY)
269 if (!(mdic & E1000_MDIC_READY)) {
270 DEBUGOUT("MDI Read did not complete\n");
271 ret_val = -E1000_ERR_PHY;
274 if (mdic & E1000_MDIC_ERROR) {
275 DEBUGOUT("MDI Error\n");
276 ret_val = -E1000_ERR_PHY;
282 * Allow some time after each MDIC transaction to avoid
283 * reading duplicate data in the next MDIC transaction.
285 if (hw->mac.type == e1000_pch2lan)
293 * e1000_write_phy_reg_mdic - Write MDI control register
294 * @hw: pointer to the HW structure
295 * @offset: register offset to write to
296 * @data: data to write to register at offset
298 * Writes data to MDI control register in the PHY at offset.
300 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
302 struct e1000_phy_info *phy = &hw->phy;
304 s32 ret_val = E1000_SUCCESS;
306 DEBUGFUNC("e1000_write_phy_reg_mdic");
308 if (offset > MAX_PHY_REG_ADDRESS) {
309 DEBUGOUT1("PHY Address %d is out of range\n", offset);
310 return -E1000_ERR_PARAM;
314 * Set up Op-code, Phy Address, and register offset in the MDI
315 * Control register. The MAC will take care of interfacing with the
316 * PHY to retrieve the desired data.
318 mdic = (((u32)data) |
319 (offset << E1000_MDIC_REG_SHIFT) |
320 (phy->addr << E1000_MDIC_PHY_SHIFT) |
321 (E1000_MDIC_OP_WRITE));
323 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
326 * Poll the ready bit to see if the MDI read completed
327 * Increasing the time out as testing showed failures with
330 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
332 mdic = E1000_READ_REG(hw, E1000_MDIC);
333 if (mdic & E1000_MDIC_READY)
336 if (!(mdic & E1000_MDIC_READY)) {
337 DEBUGOUT("MDI Write did not complete\n");
338 ret_val = -E1000_ERR_PHY;
341 if (mdic & E1000_MDIC_ERROR) {
342 DEBUGOUT("MDI Error\n");
343 ret_val = -E1000_ERR_PHY;
348 * Allow some time after each MDIC transaction to avoid
349 * reading duplicate data in the next MDIC transaction.
351 if (hw->mac.type == e1000_pch2lan)
359 * e1000_read_phy_reg_i2c - Read PHY register using i2c
360 * @hw: pointer to the HW structure
361 * @offset: register offset to be read
362 * @data: pointer to the read data
364 * Reads the PHY register at offset using the i2c interface and stores the
365 * retrieved information in data.
367 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
369 struct e1000_phy_info *phy = &hw->phy;
372 DEBUGFUNC("e1000_read_phy_reg_i2c");
375 * Set up Op-code, Phy Address, and register address in the I2CCMD
376 * register. The MAC will take care of interfacing with the
377 * PHY to retrieve the desired data.
379 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
380 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
381 (E1000_I2CCMD_OPCODE_READ));
383 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
385 /* Poll the ready bit to see if the I2C read completed */
386 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
388 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
389 if (i2ccmd & E1000_I2CCMD_READY)
392 if (!(i2ccmd & E1000_I2CCMD_READY)) {
393 DEBUGOUT("I2CCMD Read did not complete\n");
394 return -E1000_ERR_PHY;
396 if (i2ccmd & E1000_I2CCMD_ERROR) {
397 DEBUGOUT("I2CCMD Error bit set\n");
398 return -E1000_ERR_PHY;
401 /* Need to byte-swap the 16-bit value. */
402 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
404 return E1000_SUCCESS;
408 * e1000_write_phy_reg_i2c - Write PHY register using i2c
409 * @hw: pointer to the HW structure
410 * @offset: register offset to write to
411 * @data: data to write at register offset
413 * Writes the data to PHY register at the offset using the i2c interface.
415 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
417 struct e1000_phy_info *phy = &hw->phy;
419 u16 phy_data_swapped;
421 DEBUGFUNC("e1000_write_phy_reg_i2c");
423 /* Swap the data bytes for the I2C interface */
424 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
427 * Set up Op-code, Phy Address, and register address in the I2CCMD
428 * register. The MAC will take care of interfacing with the
429 * PHY to retrieve the desired data.
431 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
432 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
433 E1000_I2CCMD_OPCODE_WRITE |
436 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
438 /* Poll the ready bit to see if the I2C read completed */
439 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
441 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
442 if (i2ccmd & E1000_I2CCMD_READY)
445 if (!(i2ccmd & E1000_I2CCMD_READY)) {
446 DEBUGOUT("I2CCMD Write did not complete\n");
447 return -E1000_ERR_PHY;
449 if (i2ccmd & E1000_I2CCMD_ERROR) {
450 DEBUGOUT("I2CCMD Error bit set\n");
451 return -E1000_ERR_PHY;
454 return E1000_SUCCESS;
458 * e1000_read_phy_reg_m88 - Read m88 PHY register
459 * @hw: pointer to the HW structure
460 * @offset: register offset to be read
461 * @data: pointer to the read data
463 * Acquires semaphore, if necessary, then reads the PHY register at offset
464 * and storing the retrieved information in data. Release any acquired
465 * semaphores before exiting.
467 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
469 s32 ret_val = E1000_SUCCESS;
471 DEBUGFUNC("e1000_read_phy_reg_m88");
473 if (!(hw->phy.ops.acquire))
476 ret_val = hw->phy.ops.acquire(hw);
480 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
483 hw->phy.ops.release(hw);
490 * e1000_write_phy_reg_m88 - Write m88 PHY register
491 * @hw: pointer to the HW structure
492 * @offset: register offset to write to
493 * @data: data to write at register offset
495 * Acquires semaphore, if necessary, then writes the data to PHY register
496 * at the offset. Release any acquired semaphores before exiting.
498 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
500 s32 ret_val = E1000_SUCCESS;
502 DEBUGFUNC("e1000_write_phy_reg_m88");
504 if (!(hw->phy.ops.acquire))
507 ret_val = hw->phy.ops.acquire(hw);
511 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
514 hw->phy.ops.release(hw);
521 * __e1000_read_phy_reg_igp - Read igp PHY register
522 * @hw: pointer to the HW structure
523 * @offset: register offset to be read
524 * @data: pointer to the read data
525 * @locked: semaphore has already been acquired or not
527 * Acquires semaphore, if necessary, then reads the PHY register at offset
528 * and stores the retrieved information in data. Release any acquired
529 * semaphores before exiting.
531 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
534 s32 ret_val = E1000_SUCCESS;
536 DEBUGFUNC("__e1000_read_phy_reg_igp");
539 if (!(hw->phy.ops.acquire))
542 ret_val = hw->phy.ops.acquire(hw);
547 if (offset > MAX_PHY_MULTI_PAGE_REG) {
548 ret_val = e1000_write_phy_reg_mdic(hw,
549 IGP01E1000_PHY_PAGE_SELECT,
555 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
560 hw->phy.ops.release(hw);
566 * e1000_read_phy_reg_igp - Read igp PHY register
567 * @hw: pointer to the HW structure
568 * @offset: register offset to be read
569 * @data: pointer to the read data
571 * Acquires semaphore then reads the PHY register at offset and stores the
572 * retrieved information in data.
573 * Release the acquired semaphore before exiting.
575 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
577 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
581 * e1000_read_phy_reg_igp_locked - Read igp PHY register
582 * @hw: pointer to the HW structure
583 * @offset: register offset to be read
584 * @data: pointer to the read data
586 * Reads the PHY register at offset and stores the retrieved information
587 * in data. Assumes semaphore already acquired.
589 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
591 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
595 * e1000_write_phy_reg_igp - Write igp PHY register
596 * @hw: pointer to the HW structure
597 * @offset: register offset to write to
598 * @data: data to write at register offset
599 * @locked: semaphore has already been acquired or not
601 * Acquires semaphore, if necessary, then writes the data to PHY register
602 * at the offset. Release any acquired semaphores before exiting.
604 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
607 s32 ret_val = E1000_SUCCESS;
609 DEBUGFUNC("e1000_write_phy_reg_igp");
612 if (!(hw->phy.ops.acquire))
615 ret_val = hw->phy.ops.acquire(hw);
620 if (offset > MAX_PHY_MULTI_PAGE_REG) {
621 ret_val = e1000_write_phy_reg_mdic(hw,
622 IGP01E1000_PHY_PAGE_SELECT,
628 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
633 hw->phy.ops.release(hw);
640 * e1000_write_phy_reg_igp - Write igp PHY register
641 * @hw: pointer to the HW structure
642 * @offset: register offset to write to
643 * @data: data to write at register offset
645 * Acquires semaphore then writes the data to PHY register
646 * at the offset. Release any acquired semaphores before exiting.
648 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
650 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
654 * e1000_write_phy_reg_igp_locked - Write igp PHY register
655 * @hw: pointer to the HW structure
656 * @offset: register offset to write to
657 * @data: data to write at register offset
659 * Writes the data to PHY register at the offset.
660 * Assumes semaphore already acquired.
662 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
664 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
668 * __e1000_read_kmrn_reg - Read kumeran register
669 * @hw: pointer to the HW structure
670 * @offset: register offset to be read
671 * @data: pointer to the read data
672 * @locked: semaphore has already been acquired or not
674 * Acquires semaphore, if necessary. Then reads the PHY register at offset
675 * using the kumeran interface. The information retrieved is stored in data.
676 * Release any acquired semaphores before exiting.
678 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
682 s32 ret_val = E1000_SUCCESS;
684 DEBUGFUNC("__e1000_read_kmrn_reg");
687 if (!(hw->phy.ops.acquire))
690 ret_val = hw->phy.ops.acquire(hw);
695 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
696 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
697 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
701 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
702 *data = (u16)kmrnctrlsta;
705 hw->phy.ops.release(hw);
712 * e1000_read_kmrn_reg_generic - Read kumeran register
713 * @hw: pointer to the HW structure
714 * @offset: register offset to be read
715 * @data: pointer to the read data
717 * Acquires semaphore then reads the PHY register at offset using the
718 * kumeran interface. The information retrieved is stored in data.
719 * Release the acquired semaphore before exiting.
721 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
723 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
727 * e1000_read_kmrn_reg_locked - Read kumeran register
728 * @hw: pointer to the HW structure
729 * @offset: register offset to be read
730 * @data: pointer to the read data
732 * Reads the PHY register at offset using the kumeran interface. The
733 * information retrieved is stored in data.
734 * Assumes semaphore already acquired.
736 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
738 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
742 * __e1000_write_kmrn_reg - Write kumeran register
743 * @hw: pointer to the HW structure
744 * @offset: register offset to write to
745 * @data: data to write at register offset
746 * @locked: semaphore has already been acquired or not
748 * Acquires semaphore, if necessary. Then write the data to PHY register
749 * at the offset using the kumeran interface. Release any acquired semaphores
752 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
756 s32 ret_val = E1000_SUCCESS;
758 DEBUGFUNC("e1000_write_kmrn_reg_generic");
761 if (!(hw->phy.ops.acquire))
764 ret_val = hw->phy.ops.acquire(hw);
769 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
770 E1000_KMRNCTRLSTA_OFFSET) | data;
771 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
776 hw->phy.ops.release(hw);
783 * e1000_write_kmrn_reg_generic - Write kumeran register
784 * @hw: pointer to the HW structure
785 * @offset: register offset to write to
786 * @data: data to write at register offset
788 * Acquires semaphore then writes the data to the PHY register at the offset
789 * using the kumeran interface. Release the acquired semaphore before exiting.
791 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
793 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
797 * e1000_write_kmrn_reg_locked - Write kumeran register
798 * @hw: pointer to the HW structure
799 * @offset: register offset to write to
800 * @data: data to write at register offset
802 * Write the data to PHY register at the offset using the kumeran interface.
803 * Assumes semaphore already acquired.
805 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
807 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
811 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
812 * @hw: pointer to the HW structure
814 * Sets up Carrier-sense on Transmit and downshift values.
816 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
821 DEBUGFUNC("e1000_copper_link_setup_82577");
823 if (hw->phy.reset_disable) {
824 ret_val = E1000_SUCCESS;
828 if (hw->phy.type == e1000_phy_82580) {
829 ret_val = hw->phy.ops.reset(hw);
831 DEBUGOUT("Error resetting the PHY.\n");
836 /* Enable CRS on Tx. This must be set for half-duplex operation. */
837 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
841 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
843 /* Enable downshift */
844 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
846 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
853 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
854 * @hw: pointer to the HW structure
856 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
857 * and downshift values are set also.
859 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
861 struct e1000_phy_info *phy = &hw->phy;
865 DEBUGFUNC("e1000_copper_link_setup_m88");
867 if (phy->reset_disable) {
868 ret_val = E1000_SUCCESS;
872 /* Enable CRS on Tx. This must be set for half-duplex operation. */
873 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
877 /* For BM PHY this bit is downshift enable */
878 if (phy->type != e1000_phy_bm)
879 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
883 * MDI/MDI-X = 0 (default)
884 * 0 - Auto for all speeds
887 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
889 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
893 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
896 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
899 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
903 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
909 * disable_polarity_correction = 0 (default)
910 * Automatic Correction for Reversed Cable Polarity
914 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
915 if (phy->disable_polarity_correction == 1)
916 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
918 /* Enable downshift on BM (disabled by default) */
919 if (phy->type == e1000_phy_bm)
920 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
922 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
926 if ((phy->type == e1000_phy_m88) &&
927 (phy->revision < E1000_REVISION_4) &&
928 (phy->id != BME1000_E_PHY_ID_R2)) {
930 * Force TX_CLK in the Extended PHY Specific Control Register
933 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
938 phy_data |= M88E1000_EPSCR_TX_CLK_25;
940 if ((phy->revision == E1000_REVISION_2) &&
941 (phy->id == M88E1111_I_PHY_ID)) {
942 /* 82573L PHY - set the downshift counter to 5x. */
943 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
944 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
946 /* Configure Master and Slave downshift values */
947 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
948 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
949 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
950 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
952 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
958 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
959 /* Set PHY page 0, register 29 to 0x0003 */
960 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
964 /* Set PHY page 0, register 30 to 0x0000 */
965 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
970 /* Commit the changes. */
971 ret_val = phy->ops.commit(hw);
973 DEBUGOUT("Error committing the PHY changes\n");
977 if (phy->type == e1000_phy_82578) {
978 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
983 /* 82578 PHY - set the downshift count to 1x. */
984 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
985 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
986 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
997 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
998 * @hw: pointer to the HW structure
1000 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1001 * Also enables and sets the downshift parameters.
1003 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1005 struct e1000_phy_info *phy = &hw->phy;
1009 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1011 if (phy->reset_disable) {
1012 ret_val = E1000_SUCCESS;
1016 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1017 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1023 * MDI/MDI-X = 0 (default)
1024 * 0 - Auto for all speeds
1027 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1029 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1031 switch (phy->mdix) {
1033 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1036 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1039 /* M88E1112 does not support this mode) */
1040 if (phy->id != M88E1112_E_PHY_ID) {
1041 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1046 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1052 * disable_polarity_correction = 0 (default)
1053 * Automatic Correction for Reversed Cable Polarity
1057 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1058 if (phy->disable_polarity_correction == 1)
1059 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1061 /* Enable downshift and setting it to X6 */
1062 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1063 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1064 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1066 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1070 /* Commit the changes. */
1071 ret_val = phy->ops.commit(hw);
1073 DEBUGOUT("Error committing the PHY changes\n");
1082 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1083 * @hw: pointer to the HW structure
1085 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1088 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1090 struct e1000_phy_info *phy = &hw->phy;
1094 DEBUGFUNC("e1000_copper_link_setup_igp");
1096 if (phy->reset_disable) {
1097 ret_val = E1000_SUCCESS;
1101 ret_val = hw->phy.ops.reset(hw);
1103 DEBUGOUT("Error resetting the PHY.\n");
1108 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1109 * timeout issues when LFS is enabled.
1114 * The NVM settings will configure LPLU in D3 for
1117 if (phy->type == e1000_phy_igp) {
1118 /* disable lplu d3 during driver init */
1119 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE);
1121 DEBUGOUT("Error Disabling LPLU D3\n");
1126 /* disable lplu d0 during driver init */
1127 if (hw->phy.ops.set_d0_lplu_state) {
1128 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1130 DEBUGOUT("Error Disabling LPLU D0\n");
1134 /* Configure mdi-mdix settings */
1135 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1139 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1141 switch (phy->mdix) {
1143 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1146 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1150 data |= IGP01E1000_PSCR_AUTO_MDIX;
1153 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1157 /* set auto-master slave resolution settings */
1158 if (hw->mac.autoneg) {
1160 * when autonegotiation advertisement is only 1000Mbps then we
1161 * should disable SmartSpeed and enable Auto MasterSlave
1162 * resolution as hardware default.
1164 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1165 /* Disable SmartSpeed */
1166 ret_val = phy->ops.read_reg(hw,
1167 IGP01E1000_PHY_PORT_CONFIG,
1172 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1173 ret_val = phy->ops.write_reg(hw,
1174 IGP01E1000_PHY_PORT_CONFIG,
1179 /* Set auto Master/Slave resolution process */
1180 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1184 data &= ~CR_1000T_MS_ENABLE;
1185 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1190 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1194 /* load defaults for future use */
1195 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1196 ((data & CR_1000T_MS_VALUE) ?
1197 e1000_ms_force_master :
1198 e1000_ms_force_slave) :
1201 switch (phy->ms_type) {
1202 case e1000_ms_force_master:
1203 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1205 case e1000_ms_force_slave:
1206 data |= CR_1000T_MS_ENABLE;
1207 data &= ~(CR_1000T_MS_VALUE);
1210 data &= ~CR_1000T_MS_ENABLE;
1214 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1224 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1225 * @hw: pointer to the HW structure
1227 * Performs initial bounds checking on autoneg advertisement parameter, then
1228 * configure to advertise the full capability. Setup the PHY to autoneg
1229 * and restart the negotiation process between the link partner. If
1230 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1232 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1234 struct e1000_phy_info *phy = &hw->phy;
1238 DEBUGFUNC("e1000_copper_link_autoneg");
1241 * Perform some bounds checking on the autoneg advertisement
1244 phy->autoneg_advertised &= phy->autoneg_mask;
1247 * If autoneg_advertised is zero, we assume it was not defaulted
1248 * by the calling code so we set to advertise full capability.
1250 if (phy->autoneg_advertised == 0)
1251 phy->autoneg_advertised = phy->autoneg_mask;
1253 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1254 ret_val = e1000_phy_setup_autoneg(hw);
1256 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1259 DEBUGOUT("Restarting Auto-Neg\n");
1262 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1263 * the Auto Neg Restart bit in the PHY control register.
1265 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1269 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1270 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1275 * Does the user want to wait for Auto-Neg to complete here, or
1276 * check at a later time (for example, callback routine).
1278 if (phy->autoneg_wait_to_complete) {
1279 ret_val = hw->mac.ops.wait_autoneg(hw);
1281 DEBUGOUT("Error while waiting for "
1282 "autoneg to complete\n");
1287 hw->mac.get_link_status = TRUE;
1294 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1295 * @hw: pointer to the HW structure
1297 * Reads the MII auto-neg advertisement register and/or the 1000T control
1298 * register and if the PHY is already setup for auto-negotiation, then
1299 * return successful. Otherwise, setup advertisement and flow control to
1300 * the appropriate values for the wanted auto-negotiation.
1302 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1304 struct e1000_phy_info *phy = &hw->phy;
1306 u16 mii_autoneg_adv_reg;
1307 u16 mii_1000t_ctrl_reg = 0;
1309 DEBUGFUNC("e1000_phy_setup_autoneg");
1311 phy->autoneg_advertised &= phy->autoneg_mask;
1313 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1314 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1318 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1319 /* Read the MII 1000Base-T Control Register (Address 9). */
1320 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1321 &mii_1000t_ctrl_reg);
1327 * Need to parse both autoneg_advertised and fc and set up
1328 * the appropriate PHY registers. First we will parse for
1329 * autoneg_advertised software override. Since we can advertise
1330 * a plethora of combinations, we need to check each bit
1335 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1336 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1337 * the 1000Base-T Control Register (Address 9).
1339 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1340 NWAY_AR_100TX_HD_CAPS |
1341 NWAY_AR_10T_FD_CAPS |
1342 NWAY_AR_10T_HD_CAPS);
1343 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1345 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1347 /* Do we want to advertise 10 Mb Half Duplex? */
1348 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1349 DEBUGOUT("Advertise 10mb Half duplex\n");
1350 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1353 /* Do we want to advertise 10 Mb Full Duplex? */
1354 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1355 DEBUGOUT("Advertise 10mb Full duplex\n");
1356 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1359 /* Do we want to advertise 100 Mb Half Duplex? */
1360 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1361 DEBUGOUT("Advertise 100mb Half duplex\n");
1362 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1365 /* Do we want to advertise 100 Mb Full Duplex? */
1366 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1367 DEBUGOUT("Advertise 100mb Full duplex\n");
1368 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1371 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1372 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1373 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1375 /* Do we want to advertise 1000 Mb Full Duplex? */
1376 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1377 DEBUGOUT("Advertise 1000mb Full duplex\n");
1378 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1382 * Check for a software override of the flow control settings, and
1383 * setup the PHY advertisement registers accordingly. If
1384 * auto-negotiation is enabled, then software will have to set the
1385 * "PAUSE" bits to the correct value in the Auto-Negotiation
1386 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1389 * The possible values of the "fc" parameter are:
1390 * 0: Flow control is completely disabled
1391 * 1: Rx flow control is enabled (we can receive pause frames
1392 * but not send pause frames).
1393 * 2: Tx flow control is enabled (we can send pause frames
1394 * but we do not support receiving pause frames).
1395 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1396 * other: No software override. The flow control configuration
1397 * in the EEPROM is used.
1399 switch (hw->fc.current_mode) {
1402 * Flow control (Rx & Tx) is completely disabled by a
1403 * software over-ride.
1405 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1407 case e1000_fc_rx_pause:
1409 * Rx Flow control is enabled, and Tx Flow control is
1410 * disabled, by a software over-ride.
1412 * Since there really isn't a way to advertise that we are
1413 * capable of Rx Pause ONLY, we will advertise that we
1414 * support both symmetric and asymmetric Rx PAUSE. Later
1415 * (in e1000_config_fc_after_link_up) we will disable the
1416 * hw's ability to send PAUSE frames.
1418 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1420 case e1000_fc_tx_pause:
1422 * Tx Flow control is enabled, and Rx Flow control is
1423 * disabled, by a software over-ride.
1425 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1426 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1430 * Flow control (both Rx and Tx) is enabled by a software
1433 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1436 DEBUGOUT("Flow control param set incorrectly\n");
1437 ret_val = -E1000_ERR_CONFIG;
1441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1445 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1447 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1448 ret_val = phy->ops.write_reg(hw,
1450 mii_1000t_ctrl_reg);
1460 * e1000_setup_copper_link_generic - Configure copper link settings
1461 * @hw: pointer to the HW structure
1463 * Calls the appropriate function to configure the link for auto-neg or forced
1464 * speed and duplex. Then we check for link, once link is established calls
1465 * to configure collision distance and flow control are called. If link is
1466 * not established, we return -E1000_ERR_PHY (-2).
1468 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1473 DEBUGFUNC("e1000_setup_copper_link_generic");
1475 if (hw->mac.autoneg) {
1477 * Setup autoneg and flow control advertisement and perform
1480 ret_val = e1000_copper_link_autoneg(hw);
1485 * PHY will be set to 10H, 10F, 100H or 100F
1486 * depending on user settings.
1488 DEBUGOUT("Forcing Speed and Duplex\n");
1489 ret_val = hw->phy.ops.force_speed_duplex(hw);
1491 DEBUGOUT("Error Forcing Speed and Duplex\n");
1497 * Check link status. Wait up to 100 microseconds for link to become
1500 ret_val = e1000_phy_has_link_generic(hw,
1501 COPPER_LINK_UP_LIMIT,
1508 DEBUGOUT("Valid link established!!!\n");
1509 e1000_config_collision_dist_generic(hw);
1510 ret_val = e1000_config_fc_after_link_up_generic(hw);
1512 DEBUGOUT("Unable to establish link!!!\n");
1520 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1521 * @hw: pointer to the HW structure
1523 * Calls the PHY setup function to force speed and duplex. Clears the
1524 * auto-crossover to force MDI manually. Waits for link and returns
1525 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1527 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1529 struct e1000_phy_info *phy = &hw->phy;
1534 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1536 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1540 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1542 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1547 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1548 * forced whenever speed and duplex are forced.
1550 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1554 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1555 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1557 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1561 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1565 if (phy->autoneg_wait_to_complete) {
1566 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1568 ret_val = e1000_phy_has_link_generic(hw,
1576 DEBUGOUT("Link taking longer than expected.\n");
1579 ret_val = e1000_phy_has_link_generic(hw,
1592 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1593 * @hw: pointer to the HW structure
1595 * Calls the PHY setup function to force speed and duplex. Clears the
1596 * auto-crossover to force MDI manually. Resets the PHY to commit the
1597 * changes. If time expires while waiting for link up, we reset the DSP.
1598 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1599 * successful completion, else return corresponding error code.
1601 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1603 struct e1000_phy_info *phy = &hw->phy;
1608 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1611 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1612 * forced whenever speed and duplex are forced.
1614 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1618 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1619 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1623 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1625 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1629 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1631 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1635 /* Reset the phy to commit changes. */
1636 ret_val = hw->phy.ops.commit(hw);
1640 if (phy->autoneg_wait_to_complete) {
1641 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1643 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1649 if (hw->phy.type != e1000_phy_m88 ||
1650 hw->phy.id == I347AT4_E_PHY_ID ||
1651 hw->phy.id == M88E1340M_E_PHY_ID ||
1652 hw->phy.id == M88E1112_E_PHY_ID) {
1653 DEBUGOUT("Link taking longer than expected.\n");
1656 * We didn't get link.
1657 * Reset the DSP and cross our fingers.
1659 ret_val = phy->ops.write_reg(hw,
1660 M88E1000_PHY_PAGE_SELECT,
1664 ret_val = e1000_phy_reset_dsp_generic(hw);
1671 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1677 if (hw->phy.type != e1000_phy_m88 ||
1678 hw->phy.id == I347AT4_E_PHY_ID ||
1679 hw->phy.id == M88E1340M_E_PHY_ID ||
1680 hw->phy.id == M88E1112_E_PHY_ID)
1683 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1688 * Resetting the phy means we need to re-force TX_CLK in the
1689 * Extended PHY Specific Control Register to 25MHz clock from
1690 * the reset value of 2.5MHz.
1692 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1693 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1698 * In addition, we must re-enable CRS on Tx for both half and full
1701 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1705 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1706 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1713 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1714 * @hw: pointer to the HW structure
1716 * Forces the speed and duplex settings of the PHY.
1717 * This is a function pointer entry point only called by
1718 * PHY setup routines.
1720 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1722 struct e1000_phy_info *phy = &hw->phy;
1727 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1729 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1733 e1000_phy_force_speed_duplex_setup(hw, &data);
1735 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1739 /* Disable MDI-X support for 10/100 */
1740 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1744 data &= ~IFE_PMC_AUTO_MDIX;
1745 data &= ~IFE_PMC_FORCE_MDIX;
1747 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1751 DEBUGOUT1("IFE PMC: %X\n", data);
1755 if (phy->autoneg_wait_to_complete) {
1756 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1758 ret_val = e1000_phy_has_link_generic(hw,
1766 DEBUGOUT("Link taking longer than expected.\n");
1769 ret_val = e1000_phy_has_link_generic(hw,
1782 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1783 * @hw: pointer to the HW structure
1784 * @phy_ctrl: pointer to current value of PHY_CONTROL
1786 * Forces speed and duplex on the PHY by doing the following: disable flow
1787 * control, force speed/duplex on the MAC, disable auto speed detection,
1788 * disable auto-negotiation, configure duplex, configure speed, configure
1789 * the collision distance, write configuration to CTRL register. The
1790 * caller must write to the PHY_CONTROL register for these settings to
1793 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1795 struct e1000_mac_info *mac = &hw->mac;
1798 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1800 /* Turn off flow control when forcing speed/duplex */
1801 hw->fc.current_mode = e1000_fc_none;
1803 /* Force speed/duplex on the mac */
1804 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1805 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1806 ctrl &= ~E1000_CTRL_SPD_SEL;
1808 /* Disable Auto Speed Detection */
1809 ctrl &= ~E1000_CTRL_ASDE;
1811 /* Disable autoneg on the phy */
1812 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1814 /* Forcing Full or Half Duplex? */
1815 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1816 ctrl &= ~E1000_CTRL_FD;
1817 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1818 DEBUGOUT("Half Duplex\n");
1820 ctrl |= E1000_CTRL_FD;
1821 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1822 DEBUGOUT("Full Duplex\n");
1825 /* Forcing 10mb or 100mb? */
1826 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1827 ctrl |= E1000_CTRL_SPD_100;
1828 *phy_ctrl |= MII_CR_SPEED_100;
1829 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1830 DEBUGOUT("Forcing 100mb\n");
1832 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1833 *phy_ctrl |= MII_CR_SPEED_10;
1834 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1835 DEBUGOUT("Forcing 10mb\n");
1838 e1000_config_collision_dist_generic(hw);
1840 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1844 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1845 * @hw: pointer to the HW structure
1846 * @active: boolean used to enable/disable lplu
1848 * Success returns 0, Failure returns 1
1850 * The low power link up (lplu) state is set to the power management level D3
1851 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1852 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1853 * is used during Dx states where the power conservation is most important.
1854 * During driver activity, SmartSpeed should be enabled so performance is
1857 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1859 struct e1000_phy_info *phy = &hw->phy;
1860 s32 ret_val = E1000_SUCCESS;
1863 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1865 if (!(hw->phy.ops.read_reg))
1868 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1873 data &= ~IGP02E1000_PM_D3_LPLU;
1874 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1879 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1880 * during Dx states where the power conservation is most
1881 * important. During driver activity we should enable
1882 * SmartSpeed, so performance is maintained.
1884 if (phy->smart_speed == e1000_smart_speed_on) {
1885 ret_val = phy->ops.read_reg(hw,
1886 IGP01E1000_PHY_PORT_CONFIG,
1891 data |= IGP01E1000_PSCFR_SMART_SPEED;
1892 ret_val = phy->ops.write_reg(hw,
1893 IGP01E1000_PHY_PORT_CONFIG,
1897 } else if (phy->smart_speed == e1000_smart_speed_off) {
1898 ret_val = phy->ops.read_reg(hw,
1899 IGP01E1000_PHY_PORT_CONFIG,
1904 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1905 ret_val = phy->ops.write_reg(hw,
1906 IGP01E1000_PHY_PORT_CONFIG,
1911 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1912 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1913 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1914 data |= IGP02E1000_PM_D3_LPLU;
1915 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1920 /* When LPLU is enabled, we should disable SmartSpeed */
1921 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1926 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1927 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1936 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1937 * @hw: pointer to the HW structure
1939 * Success returns 0, Failure returns 1
1941 * A downshift is detected by querying the PHY link health.
1943 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1945 struct e1000_phy_info *phy = &hw->phy;
1947 u16 phy_data, offset, mask;
1949 DEBUGFUNC("e1000_check_downshift_generic");
1951 switch (phy->type) {
1953 case e1000_phy_gg82563:
1955 case e1000_phy_82578:
1956 offset = M88E1000_PHY_SPEC_STATUS;
1957 mask = M88E1000_PSSR_DOWNSHIFT;
1960 case e1000_phy_igp_2:
1961 case e1000_phy_igp_3:
1962 offset = IGP01E1000_PHY_LINK_HEALTH;
1963 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1966 /* speed downshift not supported */
1967 phy->speed_downgraded = FALSE;
1968 ret_val = E1000_SUCCESS;
1972 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1975 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1982 * e1000_check_polarity_m88 - Checks the polarity.
1983 * @hw: pointer to the HW structure
1985 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1987 * Polarity is determined based on the PHY specific status register.
1989 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1991 struct e1000_phy_info *phy = &hw->phy;
1995 DEBUGFUNC("e1000_check_polarity_m88");
1997 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2000 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
2001 ? e1000_rev_polarity_reversed
2002 : e1000_rev_polarity_normal;
2008 * e1000_check_polarity_igp - Checks the polarity.
2009 * @hw: pointer to the HW structure
2011 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2013 * Polarity is determined based on the PHY port status register, and the
2014 * current speed (since there is no polarity at 100Mbps).
2016 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2018 struct e1000_phy_info *phy = &hw->phy;
2020 u16 data, offset, mask;
2022 DEBUGFUNC("e1000_check_polarity_igp");
2025 * Polarity is determined based on the speed of
2028 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2032 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2033 IGP01E1000_PSSR_SPEED_1000MBPS) {
2034 offset = IGP01E1000_PHY_PCS_INIT_REG;
2035 mask = IGP01E1000_PHY_POLARITY_MASK;
2038 * This really only applies to 10Mbps since
2039 * there is no polarity for 100Mbps (always 0).
2041 offset = IGP01E1000_PHY_PORT_STATUS;
2042 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2045 ret_val = phy->ops.read_reg(hw, offset, &data);
2048 phy->cable_polarity = (data & mask)
2049 ? e1000_rev_polarity_reversed
2050 : e1000_rev_polarity_normal;
2057 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2058 * @hw: pointer to the HW structure
2060 * Polarity is determined on the polarity reversal feature being enabled.
2062 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2064 struct e1000_phy_info *phy = &hw->phy;
2066 u16 phy_data, offset, mask;
2068 DEBUGFUNC("e1000_check_polarity_ife");
2071 * Polarity is determined based on the reversal feature being enabled.
2073 if (phy->polarity_correction) {
2074 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2075 mask = IFE_PESC_POLARITY_REVERSED;
2077 offset = IFE_PHY_SPECIAL_CONTROL;
2078 mask = IFE_PSC_FORCE_POLARITY;
2081 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2084 phy->cable_polarity = (phy_data & mask)
2085 ? e1000_rev_polarity_reversed
2086 : e1000_rev_polarity_normal;
2092 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2093 * @hw: pointer to the HW structure
2095 * Waits for auto-negotiation to complete or for the auto-negotiation time
2096 * limit to expire, which ever happens first.
2098 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2100 s32 ret_val = E1000_SUCCESS;
2103 DEBUGFUNC("e1000_wait_autoneg_generic");
2105 if (!(hw->phy.ops.read_reg))
2106 return E1000_SUCCESS;
2108 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2109 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2110 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2113 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2116 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2122 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2129 * e1000_phy_has_link_generic - Polls PHY for link
2130 * @hw: pointer to the HW structure
2131 * @iterations: number of times to poll for link
2132 * @usec_interval: delay between polling attempts
2133 * @success: pointer to whether polling was successful or not
2135 * Polls the PHY status register for link, 'iterations' number of times.
2137 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2138 u32 usec_interval, bool *success)
2140 s32 ret_val = E1000_SUCCESS;
2143 DEBUGFUNC("e1000_phy_has_link_generic");
2145 if (!(hw->phy.ops.read_reg))
2146 return E1000_SUCCESS;
2148 for (i = 0; i < iterations; i++) {
2150 * Some PHYs require the PHY_STATUS register to be read
2151 * twice due to the link bit being sticky. No harm doing
2152 * it across the board.
2154 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2157 * If the first read fails, another entity may have
2158 * ownership of the resources, wait and try again to
2159 * see if they have relinquished the resources yet.
2161 usec_delay(usec_interval);
2162 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2165 if (phy_status & MII_SR_LINK_STATUS)
2167 if (usec_interval >= 1000)
2168 msec_delay_irq(usec_interval/1000);
2170 usec_delay(usec_interval);
2173 *success = (i < iterations) ? TRUE : FALSE;
2179 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2180 * @hw: pointer to the HW structure
2182 * Reads the PHY specific status register to retrieve the cable length
2183 * information. The cable length is determined by averaging the minimum and
2184 * maximum values to get the "average" cable length. The m88 PHY has four
2185 * possible cable length values, which are:
2186 * Register Value Cable Length
2190 * 3 110 - 140 meters
2193 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2195 struct e1000_phy_info *phy = &hw->phy;
2197 u16 phy_data, index;
2199 DEBUGFUNC("e1000_get_cable_length_m88");
2201 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2205 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2206 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2207 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2208 ret_val = -E1000_ERR_PHY;
2212 phy->min_cable_length = e1000_m88_cable_length_table[index];
2213 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2215 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2221 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2223 struct e1000_phy_info *phy = &hw->phy;
2225 u16 phy_data, phy_data2, index, default_page, is_cm;
2227 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2229 switch (hw->phy.id) {
2230 case M88E1340M_E_PHY_ID:
2231 case I347AT4_E_PHY_ID:
2232 /* Remember the original page select and set it to 7 */
2233 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2238 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2242 /* Get cable length from PHY Cable Diagnostics Control Reg */
2243 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2248 /* Check if the unit of cable length is meters or cm */
2249 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2253 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2255 /* Populate the phy structure with cable length in meters */
2256 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2257 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2258 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2260 /* Reset the page selec to its original value */
2261 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2266 case M88E1112_E_PHY_ID:
2267 /* Remember the original page select and set it to 5 */
2268 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2273 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2277 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2282 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2283 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2284 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2285 ret_val = -E1000_ERR_PHY;
2289 phy->min_cable_length = e1000_m88_cable_length_table[index];
2290 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2292 phy->cable_length = (phy->min_cable_length +
2293 phy->max_cable_length) / 2;
2295 /* Reset the page select to its original value */
2296 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2303 ret_val = -E1000_ERR_PHY;
2312 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2313 * @hw: pointer to the HW structure
2315 * The automatic gain control (agc) normalizes the amplitude of the
2316 * received signal, adjusting for the attenuation produced by the
2317 * cable. By reading the AGC registers, which represent the
2318 * combination of coarse and fine gain value, the value can be put
2319 * into a lookup table to obtain the approximate cable length
2322 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2324 struct e1000_phy_info *phy = &hw->phy;
2325 s32 ret_val = E1000_SUCCESS;
2326 u16 phy_data, i, agc_value = 0;
2327 u16 cur_agc_index, max_agc_index = 0;
2328 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2329 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2330 IGP02E1000_PHY_AGC_A,
2331 IGP02E1000_PHY_AGC_B,
2332 IGP02E1000_PHY_AGC_C,
2333 IGP02E1000_PHY_AGC_D
2336 DEBUGFUNC("e1000_get_cable_length_igp_2");
2338 /* Read the AGC registers for all channels */
2339 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2340 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2345 * Getting bits 15:9, which represent the combination of
2346 * coarse and fine gain values. The result is a number
2347 * that can be put into the lookup table to obtain the
2348 * approximate cable length.
2350 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2351 IGP02E1000_AGC_LENGTH_MASK;
2353 /* Array index bound check. */
2354 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2355 (cur_agc_index == 0)) {
2356 ret_val = -E1000_ERR_PHY;
2360 /* Remove min & max AGC values from calculation. */
2361 if (e1000_igp_2_cable_length_table[min_agc_index] >
2362 e1000_igp_2_cable_length_table[cur_agc_index])
2363 min_agc_index = cur_agc_index;
2364 if (e1000_igp_2_cable_length_table[max_agc_index] <
2365 e1000_igp_2_cable_length_table[cur_agc_index])
2366 max_agc_index = cur_agc_index;
2368 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2371 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2372 e1000_igp_2_cable_length_table[max_agc_index]);
2373 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2375 /* Calculate cable length with the error range of +/- 10 meters. */
2376 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2377 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2378 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2380 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2387 * e1000_get_phy_info_m88 - Retrieve PHY information
2388 * @hw: pointer to the HW structure
2390 * Valid for only copper links. Read the PHY status register (sticky read)
2391 * to verify that link is up. Read the PHY special control register to
2392 * determine the polarity and 10base-T extended distance. Read the PHY
2393 * special status register to determine MDI/MDIx and current speed. If
2394 * speed is 1000, then determine cable length, local and remote receiver.
2396 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2398 struct e1000_phy_info *phy = &hw->phy;
2403 DEBUGFUNC("e1000_get_phy_info_m88");
2405 if (phy->media_type != e1000_media_type_copper) {
2406 DEBUGOUT("Phy info is only valid for copper media\n");
2407 ret_val = -E1000_ERR_CONFIG;
2411 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2416 DEBUGOUT("Phy info is only valid if link is up\n");
2417 ret_val = -E1000_ERR_CONFIG;
2421 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2425 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2428 ret_val = e1000_check_polarity_m88(hw);
2432 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2436 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2438 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2439 ret_val = hw->phy.ops.get_cable_length(hw);
2443 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2447 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2448 ? e1000_1000t_rx_status_ok
2449 : e1000_1000t_rx_status_not_ok;
2451 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2452 ? e1000_1000t_rx_status_ok
2453 : e1000_1000t_rx_status_not_ok;
2455 /* Set values to "undefined" */
2456 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2457 phy->local_rx = e1000_1000t_rx_status_undefined;
2458 phy->remote_rx = e1000_1000t_rx_status_undefined;
2466 * e1000_get_phy_info_igp - Retrieve igp PHY information
2467 * @hw: pointer to the HW structure
2469 * Read PHY status to determine if link is up. If link is up, then
2470 * set/determine 10base-T extended distance and polarity correction. Read
2471 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2472 * determine on the cable length, local and remote receiver.
2474 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2476 struct e1000_phy_info *phy = &hw->phy;
2481 DEBUGFUNC("e1000_get_phy_info_igp");
2483 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2488 DEBUGOUT("Phy info is only valid if link is up\n");
2489 ret_val = -E1000_ERR_CONFIG;
2493 phy->polarity_correction = TRUE;
2495 ret_val = e1000_check_polarity_igp(hw);
2499 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2503 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2505 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2506 IGP01E1000_PSSR_SPEED_1000MBPS) {
2507 ret_val = phy->ops.get_cable_length(hw);
2511 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2515 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2516 ? e1000_1000t_rx_status_ok
2517 : e1000_1000t_rx_status_not_ok;
2519 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2520 ? e1000_1000t_rx_status_ok
2521 : e1000_1000t_rx_status_not_ok;
2523 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2524 phy->local_rx = e1000_1000t_rx_status_undefined;
2525 phy->remote_rx = e1000_1000t_rx_status_undefined;
2533 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2534 * @hw: pointer to the HW structure
2536 * Populates "phy" structure with various feature states.
2538 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2540 struct e1000_phy_info *phy = &hw->phy;
2545 DEBUGFUNC("e1000_get_phy_info_ife");
2547 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2552 DEBUGOUT("Phy info is only valid if link is up\n");
2553 ret_val = -E1000_ERR_CONFIG;
2557 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2560 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2563 if (phy->polarity_correction) {
2564 ret_val = e1000_check_polarity_ife(hw);
2568 /* Polarity is forced */
2569 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2570 ? e1000_rev_polarity_reversed
2571 : e1000_rev_polarity_normal;
2574 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2578 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2580 /* The following parameters are undefined for 10/100 operation. */
2581 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2582 phy->local_rx = e1000_1000t_rx_status_undefined;
2583 phy->remote_rx = e1000_1000t_rx_status_undefined;
2590 * e1000_phy_sw_reset_generic - PHY software reset
2591 * @hw: pointer to the HW structure
2593 * Does a software reset of the PHY by reading the PHY control register and
2594 * setting/write the control register reset bit to the PHY.
2596 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2598 s32 ret_val = E1000_SUCCESS;
2601 DEBUGFUNC("e1000_phy_sw_reset_generic");
2603 if (!(hw->phy.ops.read_reg))
2606 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2610 phy_ctrl |= MII_CR_RESET;
2611 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2622 * e1000_phy_hw_reset_generic - PHY hardware reset
2623 * @hw: pointer to the HW structure
2625 * Verify the reset block is not blocking us from resetting. Acquire
2626 * semaphore (if necessary) and read/set/write the device control reset
2627 * bit in the PHY. Wait the appropriate delay time for the device to
2628 * reset and release the semaphore (if necessary).
2630 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2632 struct e1000_phy_info *phy = &hw->phy;
2633 s32 ret_val = E1000_SUCCESS;
2636 DEBUGFUNC("e1000_phy_hw_reset_generic");
2638 ret_val = phy->ops.check_reset_block(hw);
2640 ret_val = E1000_SUCCESS;
2644 ret_val = phy->ops.acquire(hw);
2648 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2649 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2650 E1000_WRITE_FLUSH(hw);
2652 usec_delay(phy->reset_delay_us);
2654 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2655 E1000_WRITE_FLUSH(hw);
2659 phy->ops.release(hw);
2661 ret_val = phy->ops.get_cfg_done(hw);
2668 * e1000_get_cfg_done_generic - Generic configuration done
2669 * @hw: pointer to the HW structure
2671 * Generic function to wait 10 milli-seconds for configuration to complete
2672 * and return success.
2674 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2676 DEBUGFUNC("e1000_get_cfg_done_generic");
2680 return E1000_SUCCESS;
2684 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2685 * @hw: pointer to the HW structure
2687 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2689 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2691 DEBUGOUT("Running IGP 3 PHY init script\n");
2693 /* PHY init IGP 3 */
2694 /* Enable rise/fall, 10-mode work in class-A */
2695 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2696 /* Remove all caps from Replica path filter */
2697 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2698 /* Bias trimming for ADC, AFE and Driver (Default) */
2699 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2700 /* Increase Hybrid poly bias */
2701 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2702 /* Add 4% to Tx amplitude in Gig mode */
2703 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2704 /* Disable trimming (TTT) */
2705 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2706 /* Poly DC correction to 94.6% + 2% for all channels */
2707 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2708 /* ABS DC correction to 95.9% */
2709 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2710 /* BG temp curve trim */
2711 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2712 /* Increasing ADC OPAMP stage 1 currents to max */
2713 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2714 /* Force 1000 ( required for enabling PHY regs configuration) */
2715 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2716 /* Set upd_freq to 6 */
2717 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2719 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2720 /* Disable adaptive fixed FFE (Default) */
2721 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2722 /* Enable FFE hysteresis */
2723 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2724 /* Fixed FFE for short cable lengths */
2725 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2726 /* Fixed FFE for medium cable lengths */
2727 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2728 /* Fixed FFE for long cable lengths */
2729 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2730 /* Enable Adaptive Clip Threshold */
2731 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2732 /* AHT reset limit to 1 */
2733 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2734 /* Set AHT master delay to 127 msec */
2735 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2736 /* Set scan bits for AHT */
2737 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2738 /* Set AHT Preset bits */
2739 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2740 /* Change integ_factor of channel A to 3 */
2741 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2742 /* Change prop_factor of channels BCD to 8 */
2743 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2744 /* Change cg_icount + enable integbp for channels BCD */
2745 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2747 * Change cg_icount + enable integbp + change prop_factor_master
2748 * to 8 for channel A
2750 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2751 /* Disable AHT in Slave mode on channel A */
2752 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2754 * Enable LPLU and disable AN to 1000 in non-D0a states,
2757 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2758 /* Enable restart AN on an1000_dis change */
2759 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2760 /* Enable wh_fifo read clock in 10/100 modes */
2761 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2762 /* Restart AN, Speed selection is 1000 */
2763 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2765 return E1000_SUCCESS;
2769 * e1000_get_phy_type_from_id - Get PHY type from id
2770 * @phy_id: phy_id read from the phy
2772 * Returns the phy type from the id.
2774 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2776 enum e1000_phy_type phy_type = e1000_phy_unknown;
2779 case M88E1000_I_PHY_ID:
2780 case M88E1000_E_PHY_ID:
2781 case M88E1111_I_PHY_ID:
2782 case M88E1011_I_PHY_ID:
2783 case I347AT4_E_PHY_ID:
2784 case M88E1112_E_PHY_ID:
2785 case M88E1340M_E_PHY_ID:
2786 phy_type = e1000_phy_m88;
2788 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2789 phy_type = e1000_phy_igp_2;
2791 case GG82563_E_PHY_ID:
2792 phy_type = e1000_phy_gg82563;
2794 case IGP03E1000_E_PHY_ID:
2795 phy_type = e1000_phy_igp_3;
2798 case IFE_PLUS_E_PHY_ID:
2799 case IFE_C_E_PHY_ID:
2800 phy_type = e1000_phy_ife;
2802 case BME1000_E_PHY_ID:
2803 case BME1000_E_PHY_ID_R2:
2804 phy_type = e1000_phy_bm;
2806 case I82578_E_PHY_ID:
2807 phy_type = e1000_phy_82578;
2809 case I82577_E_PHY_ID:
2810 phy_type = e1000_phy_82577;
2812 case I82579_E_PHY_ID:
2813 phy_type = e1000_phy_82579;
2815 case I82580_I_PHY_ID:
2816 phy_type = e1000_phy_82580;
2819 phy_type = e1000_phy_unknown;
2826 * e1000_determine_phy_address - Determines PHY address.
2827 * @hw: pointer to the HW structure
2829 * This uses a trial and error method to loop through possible PHY
2830 * addresses. It tests each by reading the PHY ID registers and
2831 * checking for a match.
2833 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2835 s32 ret_val = -E1000_ERR_PHY_TYPE;
2838 enum e1000_phy_type phy_type = e1000_phy_unknown;
2840 hw->phy.id = phy_type;
2842 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2843 hw->phy.addr = phy_addr;
2847 e1000_get_phy_id(hw);
2848 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2851 * If phy_type is valid, break - we found our
2854 if (phy_type != e1000_phy_unknown) {
2855 ret_val = E1000_SUCCESS;
2868 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2869 * @page: page to access
2871 * Returns the phy address for the page requested.
2873 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2877 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2884 * e1000_write_phy_reg_bm - Write BM PHY register
2885 * @hw: pointer to the HW structure
2886 * @offset: register offset to write to
2887 * @data: data to write at register offset
2889 * Acquires semaphore, if necessary, then writes the data to PHY register
2890 * at the offset. Release any acquired semaphores before exiting.
2892 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2895 u32 page = offset >> IGP_PAGE_SHIFT;
2897 DEBUGFUNC("e1000_write_phy_reg_bm");
2899 ret_val = hw->phy.ops.acquire(hw);
2903 /* Page 800 works differently than the rest so it has its own func */
2904 if (page == BM_WUC_PAGE) {
2905 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2910 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2912 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2913 u32 page_shift, page_select;
2916 * Page select is register 31 for phy address 1 and 22 for
2917 * phy address 2 and 3. Page select is shifted only for
2920 if (hw->phy.addr == 1) {
2921 page_shift = IGP_PAGE_SHIFT;
2922 page_select = IGP01E1000_PHY_PAGE_SELECT;
2925 page_select = BM_PHY_PAGE_SELECT;
2928 /* Page is shifted left, PHY expects (page x 32) */
2929 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2930 (page << page_shift));
2935 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2939 hw->phy.ops.release(hw);
2944 * e1000_read_phy_reg_bm - Read BM PHY register
2945 * @hw: pointer to the HW structure
2946 * @offset: register offset to be read
2947 * @data: pointer to the read data
2949 * Acquires semaphore, if necessary, then reads the PHY register at offset
2950 * and storing the retrieved information in data. Release any acquired
2951 * semaphores before exiting.
2953 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2956 u32 page = offset >> IGP_PAGE_SHIFT;
2958 DEBUGFUNC("e1000_read_phy_reg_bm");
2960 ret_val = hw->phy.ops.acquire(hw);
2964 /* Page 800 works differently than the rest so it has its own func */
2965 if (page == BM_WUC_PAGE) {
2966 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2971 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2973 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2974 u32 page_shift, page_select;
2977 * Page select is register 31 for phy address 1 and 22 for
2978 * phy address 2 and 3. Page select is shifted only for
2981 if (hw->phy.addr == 1) {
2982 page_shift = IGP_PAGE_SHIFT;
2983 page_select = IGP01E1000_PHY_PAGE_SELECT;
2986 page_select = BM_PHY_PAGE_SELECT;
2989 /* Page is shifted left, PHY expects (page x 32) */
2990 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
2991 (page << page_shift));
2996 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2999 hw->phy.ops.release(hw);
3004 * e1000_read_phy_reg_bm2 - Read BM PHY register
3005 * @hw: pointer to the HW structure
3006 * @offset: register offset to be read
3007 * @data: pointer to the read data
3009 * Acquires semaphore, if necessary, then reads the PHY register at offset
3010 * and storing the retrieved information in data. Release any acquired
3011 * semaphores before exiting.
3013 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3016 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3018 DEBUGFUNC("e1000_write_phy_reg_bm2");
3020 ret_val = hw->phy.ops.acquire(hw);
3024 /* Page 800 works differently than the rest so it has its own func */
3025 if (page == BM_WUC_PAGE) {
3026 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3033 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3035 /* Page is shifted left, PHY expects (page x 32) */
3036 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3043 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3046 hw->phy.ops.release(hw);
3051 * e1000_write_phy_reg_bm2 - Write BM PHY register
3052 * @hw: pointer to the HW structure
3053 * @offset: register offset to write to
3054 * @data: data to write at register offset
3056 * Acquires semaphore, if necessary, then writes the data to PHY register
3057 * at the offset. Release any acquired semaphores before exiting.
3059 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3062 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3064 DEBUGFUNC("e1000_write_phy_reg_bm2");
3066 ret_val = hw->phy.ops.acquire(hw);
3070 /* Page 800 works differently than the rest so it has its own func */
3071 if (page == BM_WUC_PAGE) {
3072 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3079 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3080 /* Page is shifted left, PHY expects (page x 32) */
3081 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3088 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3092 hw->phy.ops.release(hw);
3097 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
3098 * @hw: pointer to the HW structure
3099 * @offset: register offset to be read or written
3100 * @data: pointer to the data to read or write
3101 * @read: determines if operation is read or write
3103 * Acquires semaphore, if necessary, then reads the PHY register at offset
3104 * and storing the retrieved information in data. Release any acquired
3105 * semaphores before exiting. Note that procedure to read the wakeup
3106 * registers are different. It works as such:
3107 * 1) Set page 769, register 17, bit 2 = 1
3108 * 2) Set page to 800 for host (801 if we were manageability)
3109 * 3) Write the address using the address opcode (0x11)
3110 * 4) Read or write the data using the data opcode (0x12)
3111 * 5) Restore 769_17.2 to its original value
3113 * Assumes semaphore already acquired.
3115 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3116 u16 *data, bool read)
3119 u16 reg = BM_PHY_REG_NUM(offset);
3122 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3124 /* Gig must be disabled for MDIO accesses to page 800 */
3125 if ((hw->mac.type == e1000_pchlan) &&
3126 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3127 DEBUGOUT("Attempting to access page 800 while gig enabled.\n");
3129 /* All operations in this function are phy address 1 */
3133 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3134 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3136 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
3138 DEBUGOUT("Could not read PHY page 769\n");
3142 /* First clear bit 4 to avoid a power state change */
3143 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
3144 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3146 DEBUGOUT("Could not clear PHY page 769 bit 4\n");
3150 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
3151 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
3152 phy_reg | BM_WUC_ENABLE_BIT);
3154 DEBUGOUT("Could not write PHY page 769 bit 2\n");
3158 /* Select page 800 */
3159 ret_val = e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3160 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3162 /* Write the page 800 offset value using opcode 0x11 */
3163 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3165 DEBUGOUT("Could not write address opcode to page 800\n");
3170 /* Read the page 800 value using opcode 0x12 */
3171 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3174 /* Write the page 800 value using opcode 0x12 */
3175 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3180 DEBUGOUT("Could not access data value from page 800\n");
3185 * Restore 769_17.2 to its original value
3188 e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
3189 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
3191 /* Clear 769_17.2 */
3192 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3194 DEBUGOUT("Could not clear PHY page 769 bit 2\n");
3203 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3204 * @hw: pointer to the HW structure
3206 * In the case of a PHY power down to save power, or to turn off link during a
3207 * driver unload, or wake on lan is not enabled, restore the link to previous
3210 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3214 /* The PHY will retain its settings across a power down/up cycle */
3215 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3216 mii_reg &= ~MII_CR_POWER_DOWN;
3217 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3221 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3222 * @hw: pointer to the HW structure
3224 * In the case of a PHY power down to save power, or to turn off link during a
3225 * driver unload, or wake on lan is not enabled, restore the link to previous
3228 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3232 /* The PHY will retain its settings across a power down/up cycle */
3233 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3234 mii_reg |= MII_CR_POWER_DOWN;
3235 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3240 * __e1000_read_phy_reg_hv - Read HV PHY register
3241 * @hw: pointer to the HW structure
3242 * @offset: register offset to be read
3243 * @data: pointer to the read data
3244 * @locked: semaphore has already been acquired or not
3246 * Acquires semaphore, if necessary, then reads the PHY register at offset
3247 * and stores the retrieved information in data. Release any acquired
3248 * semaphore before exiting.
3250 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3254 u16 page = BM_PHY_REG_PAGE(offset);
3255 u16 reg = BM_PHY_REG_NUM(offset);
3257 DEBUGFUNC("__e1000_read_phy_reg_hv");
3260 ret_val = hw->phy.ops.acquire(hw);
3265 /* Page 800 works differently than the rest so it has its own func */
3266 if (page == BM_WUC_PAGE) {
3267 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3272 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3273 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3278 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3280 if (page == HV_INTC_FC_PAGE_START)
3283 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3284 u32 phy_addr = hw->phy.addr;
3288 /* Page is shifted left, PHY expects (page x 32) */
3289 ret_val = e1000_write_phy_reg_mdic(hw,
3290 IGP01E1000_PHY_PAGE_SELECT,
3291 (page << IGP_PAGE_SHIFT));
3292 hw->phy.addr = phy_addr;
3298 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3302 hw->phy.ops.release(hw);
3308 * e1000_read_phy_reg_hv - Read HV PHY register
3309 * @hw: pointer to the HW structure
3310 * @offset: register offset to be read
3311 * @data: pointer to the read data
3313 * Acquires semaphore then reads the PHY register at offset and stores
3314 * the retrieved information in data. Release the acquired semaphore
3317 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3319 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE);
3323 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3324 * @hw: pointer to the HW structure
3325 * @offset: register offset to be read
3326 * @data: pointer to the read data
3328 * Reads the PHY register at offset and stores the retrieved information
3329 * in data. Assumes semaphore already acquired.
3331 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3333 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE);
3337 * __e1000_write_phy_reg_hv - Write HV PHY register
3338 * @hw: pointer to the HW structure
3339 * @offset: register offset to write to
3340 * @data: data to write at register offset
3341 * @locked: semaphore has already been acquired or not
3343 * Acquires semaphore, if necessary, then writes the data to PHY register
3344 * at the offset. Release any acquired semaphores before exiting.
3346 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3350 u16 page = BM_PHY_REG_PAGE(offset);
3351 u16 reg = BM_PHY_REG_NUM(offset);
3353 DEBUGFUNC("__e1000_write_phy_reg_hv");
3356 ret_val = hw->phy.ops.acquire(hw);
3361 /* Page 800 works differently than the rest so it has its own func */
3362 if (page == BM_WUC_PAGE) {
3363 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
3368 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3369 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3374 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3376 if (page == HV_INTC_FC_PAGE_START)
3380 * Workaround MDIO accesses being disabled after entering IEEE Power
3381 * Down (whenever bit 11 of the PHY Control register is set)
3383 if ((hw->phy.type == e1000_phy_82578) &&
3384 (hw->phy.revision >= 1) &&
3385 (hw->phy.addr == 2) &&
3386 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
3387 (data & (1 << 11))) {
3389 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
3395 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3396 u32 phy_addr = hw->phy.addr;
3400 /* Page is shifted left, PHY expects (page x 32) */
3401 ret_val = e1000_write_phy_reg_mdic(hw,
3402 IGP01E1000_PHY_PAGE_SELECT,
3403 (page << IGP_PAGE_SHIFT));
3404 hw->phy.addr = phy_addr;
3410 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3415 hw->phy.ops.release(hw);
3421 * e1000_write_phy_reg_hv - Write HV PHY register
3422 * @hw: pointer to the HW structure
3423 * @offset: register offset to write to
3424 * @data: data to write at register offset
3426 * Acquires semaphore then writes the data to PHY register at the offset.
3427 * Release the acquired semaphores before exiting.
3429 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3431 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE);
3435 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3436 * @hw: pointer to the HW structure
3437 * @offset: register offset to write to
3438 * @data: data to write at register offset
3440 * Writes the data to PHY register at the offset. Assumes semaphore
3443 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3445 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE);
3449 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3450 * @page: page to be accessed
3452 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3456 if (page >= HV_INTC_FC_PAGE_START)
3463 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3464 * @hw: pointer to the HW structure
3465 * @offset: register offset to be read or written
3466 * @data: pointer to the data to be read or written
3467 * @read: determines if operation is read or written
3469 * Reads the PHY register at offset and stores the retreived information
3470 * in data. Assumes semaphore already acquired. Note that the procedure
3471 * to read these regs uses the address port and data port to read/write.
3473 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3474 u16 *data, bool read)
3480 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3482 /* This takes care of the difference with desktop vs mobile phy */
3483 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3484 I82578_ADDR_REG : I82577_ADDR_REG;
3485 data_reg = addr_reg + 1;
3487 /* All operations in this function are phy address 2 */
3490 /* masking with 0x3F to remove the page from offset */
3491 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3493 DEBUGOUT("Could not write PHY the HV address register\n");
3497 /* Read or write the data value next */
3499 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3501 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3504 DEBUGOUT("Could not read data value from HV data register\n");
3513 * e1000_link_stall_workaround_hv - Si workaround
3514 * @hw: pointer to the HW structure
3516 * This function works around a Si bug where the link partner can get
3517 * a link up indication before the PHY does. If small packets are sent
3518 * by the link partner they can be placed in the packet buffer without
3519 * being properly accounted for by the PHY and will stall preventing
3520 * further packets from being received. The workaround is to clear the
3521 * packet buffer after the PHY detects link up.
3523 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3525 s32 ret_val = E1000_SUCCESS;
3528 DEBUGFUNC("e1000_link_stall_workaround_hv");
3530 if (hw->phy.type != e1000_phy_82578)
3533 /* Do not apply workaround if in PHY loopback bit 14 set */
3534 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3535 if (data & PHY_CONTROL_LB)
3538 /* check if link is up and at 1Gbps */
3539 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3543 data &= BM_CS_STATUS_LINK_UP |
3544 BM_CS_STATUS_RESOLVED |
3545 BM_CS_STATUS_SPEED_MASK;
3547 if (data != (BM_CS_STATUS_LINK_UP |
3548 BM_CS_STATUS_RESOLVED |
3549 BM_CS_STATUS_SPEED_1000))
3554 /* flush the packets in the fifo buffer */
3555 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3556 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3557 HV_MUX_DATA_CTRL_FORCE_SPEED);
3561 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3562 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3569 * e1000_check_polarity_82577 - Checks the polarity.
3570 * @hw: pointer to the HW structure
3572 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3574 * Polarity is determined based on the PHY specific status register.
3576 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3578 struct e1000_phy_info *phy = &hw->phy;
3582 DEBUGFUNC("e1000_check_polarity_82577");
3584 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3587 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3588 ? e1000_rev_polarity_reversed
3589 : e1000_rev_polarity_normal;
3595 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3596 * @hw: pointer to the HW structure
3598 * Calls the PHY setup function to force speed and duplex.
3600 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3602 struct e1000_phy_info *phy = &hw->phy;
3607 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3609 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3613 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3615 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3621 if (phy->autoneg_wait_to_complete) {
3622 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3624 ret_val = e1000_phy_has_link_generic(hw,
3632 DEBUGOUT("Link taking longer than expected.\n");
3635 ret_val = e1000_phy_has_link_generic(hw,
3648 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3649 * @hw: pointer to the HW structure
3651 * Read PHY status to determine if link is up. If link is up, then
3652 * set/determine 10base-T extended distance and polarity correction. Read
3653 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3654 * determine on the cable length, local and remote receiver.
3656 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3658 struct e1000_phy_info *phy = &hw->phy;
3663 DEBUGFUNC("e1000_get_phy_info_82577");
3665 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
3670 DEBUGOUT("Phy info is only valid if link is up\n");
3671 ret_val = -E1000_ERR_CONFIG;
3675 phy->polarity_correction = TRUE;
3677 ret_val = e1000_check_polarity_82577(hw);
3681 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3685 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
3687 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3688 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3689 ret_val = hw->phy.ops.get_cable_length(hw);
3693 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3697 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3698 ? e1000_1000t_rx_status_ok
3699 : e1000_1000t_rx_status_not_ok;
3701 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3702 ? e1000_1000t_rx_status_ok
3703 : e1000_1000t_rx_status_not_ok;
3705 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3706 phy->local_rx = e1000_1000t_rx_status_undefined;
3707 phy->remote_rx = e1000_1000t_rx_status_undefined;
3715 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3716 * @hw: pointer to the HW structure
3718 * Reads the diagnostic status register and verifies result is valid before
3719 * placing it in the phy_cable_length field.
3721 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3723 struct e1000_phy_info *phy = &hw->phy;
3725 u16 phy_data, length;
3727 DEBUGFUNC("e1000_get_cable_length_82577");
3729 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3733 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3734 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3736 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3737 ret_val = -E1000_ERR_PHY;
3739 phy->cable_length = length;