sys/dev/qlxgbe/ql_hw.h

   1 /*
   2  * Copyright (c) 2013-2016 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 /*
  30  * File: ql_hw.h
  31  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  32  */
  33 #ifndef _QL_HW_H_
  34 #define _QL_HW_H_
  35
  36 /*
  37  * PCIe Registers; Direct Mapped; Offsets from BAR0
  38  */
  39
  40 /*
  41  * Register offsets for QLE8030
  42  */
  43
  44 /*
  45  * Firmware Mailbox Registers
  46  *      0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
  47  */
  48 #define Q8_FW_MBOX0                     0x00000800
  49 #define Q8_FW_MBOX511                   0x00000FFC
  50
  51 /*
  52  * Host Mailbox Registers
  53  *      0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
  54  */
  55 #define Q8_HOST_MBOX0                   0x00000000
  56 #define Q8_HOST_MBOX511                 0x000007FC
  57
  58 #define Q8_MBOX_INT_ENABLE              0x00001000
  59 #define Q8_MBOX_INT_MASK_MSIX           0x00001200
  60 #define Q8_MBOX_INT_LEGACY              0x00003010
  61
  62 #define Q8_HOST_MBOX_CNTRL              0x00003038
  63 #define Q8_FW_MBOX_CNTRL                0x0000303C
  64
  65 #define Q8_PEG_HALT_STATUS1             0x000034A8
  66 #define Q8_PEG_HALT_STATUS2             0x000034AC
  67 #define Q8_FIRMWARE_HEARTBEAT           0x000034B0
  68
  69 #define Q8_FLASH_LOCK_ID                0x00003500
  70 #define Q8_DRIVER_LOCK_ID               0x00003504
  71 #define Q8_FW_CAPABILITIES              0x00003528
  72
  73 #define Q8_FW_VER_MAJOR                 0x00003550
  74 #define Q8_FW_VER_MINOR                 0x00003554
  75 #define Q8_FW_VER_SUB                   0x00003558
  76
  77 #define Q8_BOOTLD_ADDR                  0x0000355C
  78 #define Q8_BOOTLD_SIZE                  0x00003560
  79
  80 #define Q8_FW_IMAGE_ADDR                0x00003564
  81 #define Q8_FW_BUILD_NUMBER              0x00003568
  82 #define Q8_FW_IMAGE_VALID               0x000035FC
  83
  84 #define Q8_CMDPEG_STATE                 0x00003650
  85
  86 #define Q8_LINK_STATE                   0x00003698
  87 #define Q8_LINK_STATE_2                 0x0000369C
  88
  89 #define Q8_LINK_SPEED_0                 0x000036E0
  90 #define Q8_LINK_SPEED_1                 0x000036E4
  91 #define Q8_LINK_SPEED_2                 0x000036E8
  92 #define Q8_LINK_SPEED_3                 0x000036EC
  93
  94 #define Q8_MAX_LINK_SPEED_0             0x000036F0
  95 #define Q8_MAX_LINK_SPEED_1             0x000036F4
  96 #define Q8_MAX_LINK_SPEED_2             0x000036F8
  97 #define Q8_MAX_LINK_SPEED_3             0x000036FC
  98
  99 #define Q8_ASIC_TEMPERATURE             0x000037B4
 100
 101 /*
 102  * CRB Window Registers
 103  *      0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
 104  */
 105 #define Q8_CRB_WINDOW_PF0               0x00003800
 106 #define Q8_CRB_WINDOW_PF15              0x0000383C
 107
 108 #define Q8_FLASH_LOCK                   0x00003850
 109 #define Q8_FLASH_UNLOCK                 0x00003854
 110
 111 #define Q8_DRIVER_LOCK                  0x00003868
 112 #define Q8_DRIVER_UNLOCK                0x0000386C
 113
 114 #define Q8_LEGACY_INT_PTR               0x000038C0
 115 #define Q8_LEGACY_INT_TRIG              0x000038C4
 116 #define Q8_LEGACY_INT_MASK              0x000038C8
 117
 118 #define Q8_WILD_CARD                    0x000038F0
 119 #define Q8_INFORMANT                    0x000038FC
 120
 121 /*
 122  * Ethernet Interface Specific Registers
 123  */
 124 #define Q8_DRIVER_OP_MODE               0x00003570
 125 #define Q8_API_VERSION                  0x0000356C
 126 #define Q8_NPAR_STATE                   0x0000359C
 127
 128 /*
 129  * End of PCIe Registers; Direct Mapped; Offsets from BAR0
 130  */
 131
 132 /*
 133  * Indirect Registers
 134  */
 135 #define Q8_LED_DUAL_0                   0x28084C80
 136 #define Q8_LED_SINGLE_0                 0x28084C90
 137
 138 #define Q8_LED_DUAL_1                   0x28084CA0
 139 #define Q8_LED_SINGLE_1                 0x28084CB0
 140
 141 #define Q8_LED_DUAL_2                   0x28084CC0
 142 #define Q8_LED_SINGLE_2                 0x28084CD0
 143
 144 #define Q8_LED_DUAL_3                   0x28084CE0
 145 #define Q8_LED_SINGLE_3                 0x28084CF0
 146
 147 #define Q8_GPIO_1                       0x28084D00
 148 #define Q8_GPIO_2                       0x28084D10
 149 #define Q8_GPIO_3                       0x28084D20
 150 #define Q8_GPIO_4                       0x28084D40
 151 #define Q8_GPIO_5                       0x28084D50
 152 #define Q8_GPIO_6                       0x28084D60
 153 #define Q8_GPIO_7                       0x42100060
 154 #define Q8_GPIO_8                       0x42100064
 155
 156 #define Q8_FLASH_SPI_STATUS             0x2808E010
 157 #define Q8_FLASH_SPI_CONTROL            0x2808E014
 158
 159 #define Q8_FLASH_STATUS                 0x42100004
 160 #define Q8_FLASH_CONTROL                0x42110004
 161 #define Q8_FLASH_ADDRESS                0x42110008
 162 #define Q8_FLASH_WR_DATA                0x4211000C
 163 #define Q8_FLASH_RD_DATA                0x42110018
 164
 165 #define Q8_FLASH_DIRECT_WINDOW          0x42110030
 166 #define Q8_FLASH_DIRECT_DATA            0x42150000
 167
 168 #define Q8_MS_CNTRL                     0x41000090
 169
 170 #define Q8_MS_ADDR_LO                   0x41000094
 171 #define Q8_MS_ADDR_HI                   0x41000098
 172
 173 #define Q8_MS_WR_DATA_0_31              0x410000A0
 174 #define Q8_MS_WR_DATA_32_63             0x410000A4
 175 #define Q8_MS_WR_DATA_64_95             0x410000B0
 176 #define Q8_MS_WR_DATA_96_127            0x410000B4
 177
 178 #define Q8_MS_RD_DATA_0_31              0x410000A8
 179 #define Q8_MS_RD_DATA_32_63             0x410000AC
 180 #define Q8_MS_RD_DATA_64_95             0x410000B8
 181 #define Q8_MS_RD_DATA_96_127            0x410000BC
 182
 183 #define Q8_CRB_PEG_0                    0x3400003c
 184 #define Q8_CRB_PEG_1                    0x3410003c
 185 #define Q8_CRB_PEG_2                    0x3420003c
 186 #define Q8_CRB_PEG_3                    0x3430003c
 187 #define Q8_CRB_PEG_4                    0x34B0003c
 188
 189 /*
 190  * Macros for reading and writing registers
 191  */
 192
 193 #if defined(__i386__) || defined(__amd64__)
 194 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
 195 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
 196 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
 197 #else
 198 #define Q8_MB()
 199 #define Q8_WMB()
 200 #define Q8_RMB()
 201 #endif
 202
 203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
 204
 205 #define WRITE_REG32(ha, reg, val) \
 206         {\
 207                 bus_write_4((ha->pci_reg), reg, val);\
 208                 bus_read_4((ha->pci_reg), reg);\
 209         }
 210
 211 #define Q8_NUM_MBOX     512
 212
 213 #define Q8_MAX_NUM_MULTICAST_ADDRS      1022
 214 #define Q8_MAC_ADDR_LEN                 6
 215
 216 /*
 217  * Firmware Interface
 218  */
 219
 220 /*
 221  * Command Response Interface - Commands
 222  */
 223
 224 #define Q8_MBX_CONFIG_IP_ADDRESS                0x0001
 225 #define Q8_MBX_CONFIG_INTR                      0x0002
 226 #define Q8_MBX_MAP_INTR_SRC                     0x0003
 227 #define Q8_MBX_MAP_SDS_TO_RDS                   0x0006
 228 #define Q8_MBX_CREATE_RX_CNTXT                  0x0007
 229 #define Q8_MBX_DESTROY_RX_CNTXT                 0x0008
 230 #define Q8_MBX_CREATE_TX_CNTXT                  0x0009
 231 #define Q8_MBX_DESTROY_TX_CNTXT                 0x000A
 232 #define Q8_MBX_ADD_RX_RINGS                     0x000B
 233 #define Q8_MBX_CONFIG_LRO_FLOW                  0x000C
 234 #define Q8_MBX_CONFIG_MAC_LEARNING              0x000D
 235 #define Q8_MBX_GET_STATS                        0x000F
 236 #define Q8_MBX_GENERATE_INTR                    0x0011
 237 #define Q8_MBX_SET_MAX_MTU                      0x0012
 238 #define Q8_MBX_MAC_ADDR_CNTRL                   0x001F
 239 #define Q8_MBX_GET_PCI_CONFIG                   0x0020
 240 #define Q8_MBX_GET_NIC_PARTITION                0x0021
 241 #define Q8_MBX_SET_NIC_PARTITION                0x0022
 242 #define Q8_MBX_QUERY_WOL_CAP                    0x002C
 243 #define Q8_MBX_SET_WOL_CONFIG                   0x002D
 244 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE          0x002F
 245 #define Q8_MBX_GET_MINIDUMP_TMPLT               0x0030
 246 #define Q8_MBX_GET_FW_DCBX_CAPS                 0x0034
 247 #define Q8_MBX_QUERY_DCBX_SETTINGS              0x0035
 248 #define Q8_MBX_CONFIG_RSS                       0x0041
 249 #define Q8_MBX_CONFIG_RSS_TABLE                 0x0042
 250 #define Q8_MBX_CONFIG_INTR_COALESCE             0x0043
 251 #define Q8_MBX_CONFIG_LED                       0x0044
 252 #define Q8_MBX_CONFIG_MAC_ADDR                  0x0045
 253 #define Q8_MBX_CONFIG_STATISTICS                0x0046
 254 #define Q8_MBX_CONFIG_LOOPBACK                  0x0047
 255 #define Q8_MBX_LINK_EVENT_REQ                   0x0048
 256 #define Q8_MBX_CONFIG_MAC_RX_MODE               0x0049
 257 #define Q8_MBX_CONFIG_FW_LRO                    0x004A
 258 #define Q8_MBX_HW_CONFIG                        0x004C
 259 #define Q8_MBX_INIT_NIC_FUNC                    0x0060
 260 #define Q8_MBX_STOP_NIC_FUNC                    0x0061
 261 #define Q8_MBX_IDC_REQ                          0x0062
 262 #define Q8_MBX_IDC_ACK                          0x0063
 263 #define Q8_MBX_SET_PORT_CONFIG                  0x0066
 264 #define Q8_MBX_GET_PORT_CONFIG                  0x0067
 265 #define Q8_MBX_GET_LINK_STATUS                  0x0068
 266
 267
 268
 269 /*
 270  * Mailbox Command Response
 271  */
 272 #define Q8_MBX_RSP_SUCCESS                      0x0001
 273 #define Q8_MBX_RSP_RESPONSE_FAILURE             0x0002
 274 #define Q8_MBX_RSP_NO_CARD_CRB                  0x0003
 275 #define Q8_MBX_RSP_NO_CARD_MEM                  0x0004
 276 #define Q8_MBX_RSP_NO_CARD_RSRC                 0x0005
 277 #define Q8_MBX_RSP_INVALID_ARGS                 0x0006
 278 #define Q8_MBX_RSP_INVALID_ACTION               0x0007
 279 #define Q8_MBX_RSP_INVALID_STATE                0x0008
 280 #define Q8_MBX_RSP_NOT_SUPPORTED                0x0009
 281 #define Q8_MBX_RSP_NOT_PERMITTED                0x000A
 282 #define Q8_MBX_RSP_NOT_READY                    0x000B
 283 #define Q8_MBX_RSP_DOES_NOT_EXIST               0x000C
 284 #define Q8_MBX_RSP_ALREADY_EXISTS               0x000D
 285 #define Q8_MBX_RSP_BAD_SIGNATURE                0x000E
 286 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED          0x000F
 287 #define Q8_MBX_RSP_CMD_INVALID                  0x0010
 288 #define Q8_MBX_RSP_TIMEOUT                      0x0011
 289 #define Q8_MBX_RSP_CMD_FAILED                   0x0012
 290 #define Q8_MBX_RSP_FATAL_TEMP                   0x0013
 291 #define Q8_MBX_RSP_MAX_EXCEEDED                 0x0014
 292 #define Q8_MBX_RSP_UNSPECIFIED                  0x0015
 293 #define Q8_MBX_RSP_INTR_CREATE_FAILED           0x0017
 294 #define Q8_MBX_RSP_INTR_DELETE_FAILED           0x0018
 295 #define Q8_MBX_RSP_INTR_INVALID_OP              0x0019
 296 #define Q8_MBX_RSP_IDC_INTRMD_RSP               0x001A
 297
 298 #define Q8_MBX_CMD_VERSION      (0x2 << 13)
 299 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
 300 /*
 301  * Configure IP Address
 302  */
 303 typedef struct _q80_config_ip_addr {
 304         uint16_t        opcode;
 305         uint16_t        count_version;
 306
 307         uint8_t         cmd;
 308 #define         Q8_MBX_CONFIG_IP_ADD_IP 0x1
 309 #define         Q8_MBX_CONFIG_IP_DEL_IP 0x2
 310
 311         uint8_t         ip_type;
 312 #define         Q8_MBX_CONFIG_IP_V4     0x0
 313 #define         Q8_MBX_CONFIG_IP_V6     0x1
 314
 315         uint16_t        rsrvd;
 316         union {
 317                 struct {
 318                         uint32_t addr;
 319                         uint32_t rsrvd[3];
 320                 } ipv4;
 321                 uint8_t ipv6_addr[16];
 322         } u;
 323 } __packed q80_config_ip_addr_t;
 324
 325 typedef struct _q80_config_ip_addr_rsp {
 326         uint16_t        opcode;
 327         uint16_t        regcnt_status;
 328 } __packed q80_config_ip_addr_rsp_t;
 329
 330 /*
 331  * Configure Interrupt Command
 332  */
 333 typedef struct _q80_intr {
 334         uint8_t         cmd_type;
 335 #define         Q8_MBX_CONFIG_INTR_CREATE       0x1
 336 #define         Q8_MBX_CONFIG_INTR_DELETE       0x2
 337 #define         Q8_MBX_CONFIG_INTR_TYPE_LINE    (0x1 << 4)
 338 #define         Q8_MBX_CONFIG_INTR_TYPE_MSI_X   (0x3 << 4)
 339
 340         uint8_t         rsrvd;
 341         uint16_t        msix_index;
 342 } __packed q80_intr_t;
 343
 344 #define Q8_MAX_INTR_VECTORS     16
 345 typedef struct _q80_config_intr {
 346         uint16_t        opcode;
 347         uint16_t        count_version;
 348         uint8_t         nentries;
 349         uint8_t         rsrvd[3];
 350         q80_intr_t      intr[Q8_MAX_INTR_VECTORS];
 351 } __packed q80_config_intr_t;
 352
 353 typedef struct _q80_intr_rsp {
 354         uint8_t         status;
 355         uint8_t         cmd;
 356         uint16_t        intr_id;
 357         uint32_t        intr_src;
 358 } q80_intr_rsp_t;
 359
 360 typedef struct _q80_config_intr_rsp {
 361         uint16_t        opcode;
 362         uint16_t        regcnt_status;
 363         uint8_t         nentries;
 364         uint8_t         rsrvd[3];
 365         q80_intr_rsp_t  intr[Q8_MAX_INTR_VECTORS];
 366 } __packed q80_config_intr_rsp_t;
 367
 368 /*
 369  * Configure LRO Flow Command
 370  */
 371 typedef struct _q80_config_lro_flow {
 372         uint16_t        opcode;
 373         uint16_t        count_version;
 374
 375         uint8_t         cmd;
 376 #define Q8_MBX_CONFIG_LRO_FLOW_ADD      0x01
 377 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE   0x02
 378
 379         uint8_t         type_ts;
 380 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4             0x00
 381 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6             0x01
 382 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT        0x00
 383 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT       0x02
 384
 385         uint16_t        rsrvd;
 386         union {
 387                 struct {
 388                         uint32_t addr;
 389                         uint32_t rsrvd[3];
 390                 } ipv4;
 391                 uint8_t ipv6_addr[16];
 392         } dst;
 393         union {
 394                 struct {
 395                         uint32_t addr;
 396                         uint32_t rsrvd[3];
 397                 } ipv4;
 398                 uint8_t ipv6_addr[16];
 399         } src;
 400         uint16_t        dst_port;
 401         uint16_t        src_port;
 402 } __packed q80_config_lro_flow_t;
 403
 404 typedef struct _q80_config_lro_flow_rsp {
 405         uint16_t        opcode;
 406         uint16_t        regcnt_status;
 407 } __packed q80_config_lro_flow_rsp_t;
 408
 409 typedef struct _q80_set_max_mtu {
 410         uint16_t        opcode;
 411         uint16_t        count_version;
 412         uint32_t        cntxt_id;
 413         uint32_t        mtu;
 414 } __packed q80_set_max_mtu_t;
 415
 416 typedef struct _q80_set_max_mtu_rsp {
 417         uint16_t        opcode;
 418         uint16_t        regcnt_status;
 419 } __packed q80_set_max_mtu_rsp_t;
 420
 421 /*
 422  * Configure RSS
 423  */
 424 typedef struct _q80_config_rss {
 425         uint16_t        opcode;
 426         uint16_t        count_version;
 427
 428         uint16_t        cntxt_id;
 429         uint16_t        rsrvd;
 430
 431         uint8_t         hash_type;
 432 #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP            (0x1 << 4)
 433 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP           (0x2 << 4)
 434 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP        (0x3 << 4)
 435 #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP            (0x1 << 6)
 436 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP           (0x2 << 6)
 437 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP        (0x3 << 6)
 438
 439         uint8_t         flags;
 440 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS             (0x1)
 441 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE          (0x2)
 442 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS              (0x4)
 443
 444         uint16_t        indtbl_mask;
 445 #define Q8_MBX_RSS_INDTBL_MASK                  0x7F
 446 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID        0x8000
 447
 448         uint32_t        multi_rss;
 449 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN      BIT_30
 450 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES        BIT_31
 451
 452         uint64_t        rss_key[5];
 453 } __packed q80_config_rss_t;
 454
 455 typedef struct _q80_config_rss_rsp {
 456         uint16_t        opcode;
 457         uint16_t        regcnt_status;
 458 } __packed q80_config_rss_rsp_t;
 459
 460 /*
 461  * Configure RSS Indirection Table
 462  */
 463 #define Q8_RSS_IND_TBL_SIZE     40
 464 #define Q8_RSS_IND_TBL_MIN_IDX  0
 465 #define Q8_RSS_IND_TBL_MAX_IDX  127
 466
 467 typedef struct _q80_config_rss_ind_table {
 468         uint16_t        opcode;
 469         uint16_t        count_version;
 470         uint8_t         start_idx;
 471         uint8_t         end_idx;
 472         uint16_t        cntxt_id;
 473         uint8_t         ind_table[Q8_RSS_IND_TBL_SIZE];
 474 } __packed q80_config_rss_ind_table_t;
 475
 476 typedef struct _q80_config_rss_ind_table_rsp {
 477         uint16_t        opcode;
 478         uint16_t        regcnt_status;
 479 } __packed q80_config_rss_ind_table_rsp_t;
 480
 481 /*
 482  * Configure Interrupt Coalescing and Generation
 483  */
 484 typedef struct _q80_config_intr_coalesc {
 485         uint16_t        opcode;
 486         uint16_t        count_version;
 487         uint16_t        flags;
 488 #define Q8_MBX_INTRC_FLAGS_RCV          1
 489 #define Q8_MBX_INTRC_FLAGS_XMT          2
 490 #define Q8_MBX_INTRC_FLAGS_PERIODIC     (1 << 3)
 491
 492         uint16_t        cntxt_id;
 493         uint16_t        max_pkts;
 494         uint16_t        max_mswait;
 495         uint8_t         timer_type;
 496 #define Q8_MBX_INTRC_TIMER_NONE                 0
 497 #define Q8_MBX_INTRC_TIMER_SINGLE               1
 498 #define Q8_MBX_INTRC_TIMER_PERIODIC             2
 499
 500         uint16_t        sds_ring_mask;
 501
 502         uint8_t         rsrvd;
 503         uint32_t        ms_timeout;
 504 } __packed q80_config_intr_coalesc_t;
 505
 506 typedef struct _q80_config_intr_coalesc_rsp {
 507         uint16_t        opcode;
 508         uint16_t        regcnt_status;
 509 } __packed q80_config_intr_coalesc_rsp_t;
 510
 511 /*
 512  * Configure MAC Address
 513  */
 514 #define Q8_ETHER_ADDR_LEN               6
 515 typedef struct _q80_mac_addr {
 516         uint8_t         addr[Q8_ETHER_ADDR_LEN];
 517         uint16_t        vlan_tci;
 518 } __packed q80_mac_addr_t;
 519
 520 #define Q8_MAX_MAC_ADDRS        64
 521
 522 typedef struct _q80_config_mac_addr {
 523         uint16_t        opcode;
 524         uint16_t        count_version;
 525         uint8_t         cmd;
 526 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR    1
 527 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR    2
 528
 529 #define Q8_MBX_CMAC_CMD_CAM_BOTH        (0x0 << 6)
 530 #define Q8_MBX_CMAC_CMD_CAM_INGRESS     (0x1 << 6)
 531 #define Q8_MBX_CMAC_CMD_CAM_EGRESS      (0x2 << 6)
 532
 533         uint8_t         nmac_entries;
 534         uint16_t        cntxt_id;
 535         q80_mac_addr_t  mac_addr[Q8_MAX_MAC_ADDRS];
 536 } __packed q80_config_mac_addr_t;
 537
 538 typedef struct _q80_config_mac_addr_rsp {
 539         uint16_t        opcode;
 540         uint16_t        regcnt_status;
 541         uint8_t         cmd;
 542         uint8_t         nmac_entries;
 543         uint16_t        cntxt_id;
 544         uint32_t        status[Q8_MAX_MAC_ADDRS];
 545 } __packed q80_config_mac_addr_rsp_t;
 546
 547 /*
 548  * Configure MAC Receive Mode
 549  */
 550 typedef struct _q80_config_mac_rcv_mode {
 551         uint16_t        opcode;
 552         uint16_t        count_version;
 553
 554         uint8_t         mode;
 555 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE   0x1
 556 #define Q8_MBX_MAC_ALL_MULTI_ENABLE     0x2
 557
 558         uint8_t         rsrvd;
 559         uint16_t        cntxt_id;
 560 } __packed q80_config_mac_rcv_mode_t;
 561
 562 typedef struct _q80_config_mac_rcv_mode_rsp {
 563         uint16_t        opcode;
 564         uint16_t        regcnt_status;
 565 } __packed q80_config_mac_rcv_mode_rsp_t;
 566
 567 /*
 568  * Configure Firmware Controlled LRO
 569  */
 570 typedef struct _q80_config_fw_lro {
 571         uint16_t        opcode;
 572         uint16_t        count_version;
 573
 574         uint8_t         flags;
 575 #define Q8_MBX_FW_LRO_IPV4                     0x1
 576 #define Q8_MBX_FW_LRO_IPV6                     0x2
 577 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK       0x4
 578 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK       0x8
 579 #define Q8_MBX_FW_LRO_LOW_THRESHOLD            0x10
 580
 581         uint8_t         rsrvd;
 582         uint16_t        cntxt_id;
 583
 584         uint16_t        low_threshold;
 585         uint16_t        rsrvd0;
 586 } __packed q80_config_fw_lro_t;
 587
 588 typedef struct _q80_config_fw_lro_rsp {
 589         uint16_t        opcode;
 590         uint16_t        regcnt_status;
 591 } __packed q80_config_fw_lro_rsp_t;
 592
 593 /*
 594  * Minidump mailbox commands
 595  */
 596 typedef struct _q80_config_md_templ_size {
 597         uint16_t        opcode;
 598         uint16_t        count_version;
 599 } __packed q80_config_md_templ_size_t;
 600
 601 typedef struct _q80_config_md_templ_size_rsp {
 602         uint16_t        opcode;
 603         uint16_t        regcnt_status;
 604         uint32_t        rsrvd;
 605         uint32_t        templ_size;
 606         uint32_t        templ_version;
 607 } __packed q80_config_md_templ_size_rsp_t;
 608
 609 typedef struct _q80_config_md_templ_cmd {
 610         uint16_t        opcode;
 611         uint16_t        count_version;
 612         uint64_t        buf_addr; /* physical address of buffer */
 613         uint32_t        buff_size;
 614         uint32_t        offset;
 615 } __packed q80_config_md_templ_cmd_t;
 616
 617 typedef struct _q80_config_md_templ_cmd_rsp {
 618         uint16_t        opcode;
 619         uint16_t        regcnt_status;
 620         uint32_t        rsrvd;
 621         uint32_t        templ_size;
 622         uint32_t        buff_size;
 623         uint32_t        offset;
 624 } __packed q80_config_md_templ_cmd_rsp_t;
 625
 626 /*
 627  * Hardware Configuration Commands
 628  */
 629
 630 typedef struct _q80_hw_config {
 631        uint16_t        opcode;
 632        uint16_t        count_version;
 633 #define Q8_HW_CONFIG_SET_MDIO_REG_COUNT                0x06
 634 #define Q8_HW_CONFIG_GET_MDIO_REG_COUNT                0x05
 635 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03
 636 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02
 637 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT  0x03
 638 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT  0x02
 639 #define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT      0x02
 640
 641        uint32_t        cmd;
 642 #define Q8_HW_CONFIG_SET_MDIO_REG              0x01
 643 #define Q8_HW_CONFIG_GET_MDIO_REG              0x02
 644 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE       0x03
 645 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE       0x04
 646 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD                0x07
 647 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD                0x08
 648 #define Q8_HW_CONFIG_GET_ECC_COUNTS            0x0A
 649
 650        union {
 651                struct {
 652                        uint32_t phys_port_number;
 653                        uint32_t phy_dev_addr;
 654                        uint32_t reg_addr;
 655                        uint32_t data;
 656                } set_mdio;
 657
 658                struct {
 659                        uint32_t phys_port_number;
 660                        uint32_t phy_dev_addr;
 661                        uint32_t reg_addr;
 662                } get_mdio;
 663
 664                struct {
 665                        uint32_t mode;
 666 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL  0x1
 667 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO      0x2
 668
 669                } set_cam_search_mode;
 670
 671                struct {
 672                        uint32_t value;
 673                } set_temp_threshold;
 674        } u;
 675 } __packed q80_hw_config_t;
 676
 677 typedef struct _q80_hw_config_rsp {
 678         uint16_t       opcode;
 679         uint16_t       regcnt_status;
 680
 681        union {
 682                struct {
 683                        uint32_t value;
 684                } get_mdio;
 685
 686                struct {
 687                        uint32_t mode;
 688                } get_cam_search_mode;
 689
 690                struct {
 691                        uint32_t temp_warn;
 692                        uint32_t curr_temp;
 693                        uint32_t osc_ring_rate;
 694                        uint32_t core_voltage;
 695                } get_temp_threshold;
 696
 697                struct {
 698                        uint32_t ddr_ecc_error_count;
 699                        uint32_t ocm_ecc_error_count;
 700                        uint32_t l2_dcache_ecc_error_count;
 701                        uint32_t l2_icache_ecc_error_count;
 702                        uint32_t eport_ecc_error_count;
 703                } get_ecc_counts;
 704        } u;
 705 } __packed q80_hw_config_rsp_t;
 706
 707 /*
 708  * Link Event Request Command
 709  */
 710 typedef struct _q80_link_event {
 711         uint16_t        opcode;
 712         uint16_t        count_version;
 713         uint8_t         cmd;
 714 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0
 715 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC  1
 716
 717         uint8_t         flags;
 718 #define Q8_LINK_EVENT_FLAGS_SEND_RSP    1
 719
 720         uint16_t        cntxt_id;
 721 } __packed q80_link_event_t;
 722
 723 typedef struct _q80_link_event_rsp {
 724         uint16_t        opcode;
 725         uint16_t        regcnt_status;
 726 } __packed q80_link_event_rsp_t;
 727
 728 /*
 729  * Get Statistics Command
 730  */
 731 typedef struct _q80_rcv_stats {
 732         uint64_t        total_bytes;
 733         uint64_t        total_pkts;
 734         uint64_t        lro_pkt_count;
 735         uint64_t        sw_pkt_count;
 736         uint64_t        ip_chksum_err;
 737         uint64_t        pkts_wo_acntxts;
 738         uint64_t        pkts_dropped_no_sds_card;
 739         uint64_t        pkts_dropped_no_sds_host;
 740         uint64_t        oversized_pkts;
 741         uint64_t        pkts_dropped_no_rds;
 742         uint64_t        unxpctd_mcast_pkts;
 743         uint64_t        re1_fbq_error;
 744         uint64_t        invalid_mac_addr;
 745         uint64_t        rds_prime_trys;
 746         uint64_t        rds_prime_success;
 747         uint64_t        lro_flows_added;
 748         uint64_t        lro_flows_deleted;
 749         uint64_t        lro_flows_active;
 750         uint64_t        pkts_droped_unknown;
 751 } __packed q80_rcv_stats_t;
 752
 753 typedef struct _q80_xmt_stats {
 754         uint64_t        total_bytes;
 755         uint64_t        total_pkts;
 756         uint64_t        errors;
 757         uint64_t        pkts_dropped;
 758         uint64_t        switch_pkts;
 759         uint64_t        num_buffers;
 760 } __packed q80_xmt_stats_t;
 761
 762 typedef struct _q80_mac_stats {
 763         uint64_t        xmt_frames;
 764         uint64_t        xmt_bytes;
 765         uint64_t        xmt_mcast_pkts;
 766         uint64_t        xmt_bcast_pkts;
 767         uint64_t        xmt_pause_frames;
 768         uint64_t        xmt_cntrl_pkts;
 769         uint64_t        xmt_pkt_lt_64bytes;
 770         uint64_t        xmt_pkt_lt_127bytes;
 771         uint64_t        xmt_pkt_lt_255bytes;
 772         uint64_t        xmt_pkt_lt_511bytes;
 773         uint64_t        xmt_pkt_lt_1023bytes;
 774         uint64_t        xmt_pkt_lt_1518bytes;
 775         uint64_t        xmt_pkt_gt_1518bytes;
 776         uint64_t        rsrvd0[3];
 777         uint64_t        rcv_frames;
 778         uint64_t        rcv_bytes;
 779         uint64_t        rcv_mcast_pkts;
 780         uint64_t        rcv_bcast_pkts;
 781         uint64_t        rcv_pause_frames;
 782         uint64_t        rcv_cntrl_pkts;
 783         uint64_t        rcv_pkt_lt_64bytes;
 784         uint64_t        rcv_pkt_lt_127bytes;
 785         uint64_t        rcv_pkt_lt_255bytes;
 786         uint64_t        rcv_pkt_lt_511bytes;
 787         uint64_t        rcv_pkt_lt_1023bytes;
 788         uint64_t        rcv_pkt_lt_1518bytes;
 789         uint64_t        rcv_pkt_gt_1518bytes;
 790         uint64_t        rsrvd1[3];
 791         uint64_t        rcv_len_error;
 792         uint64_t        rcv_len_small;
 793         uint64_t        rcv_len_large;
 794         uint64_t        rcv_jabber;
 795         uint64_t        rcv_dropped;
 796         uint64_t        fcs_error;
 797         uint64_t        align_error;
 798         uint64_t        eswitched_frames;
 799         uint64_t        eswitched_bytes;
 800         uint64_t        eswitched_mcast_frames;
 801         uint64_t        eswitched_bcast_frames;
 802         uint64_t        eswitched_ucast_frames;
 803         uint64_t        eswitched_err_free_frames;
 804         uint64_t        eswitched_err_free_bytes;
 805 } __packed q80_mac_stats_t;
 806
 807 typedef struct _q80_get_stats {
 808         uint16_t        opcode;
 809         uint16_t        count_version;
 810
 811         uint32_t        cmd;
 812 #define Q8_GET_STATS_CMD_CLEAR          0x01
 813 #define Q8_GET_STATS_CMD_RCV            0x00
 814 #define Q8_GET_STATS_CMD_XMT            0x02
 815 #define Q8_GET_STATS_CMD_TYPE_CNTXT     0x00
 816 #define Q8_GET_STATS_CMD_TYPE_MAC       0x04
 817 #define Q8_GET_STATS_CMD_TYPE_FUNC      0x08
 818 #define Q8_GET_STATS_CMD_TYPE_VPORT     0x0C
 819 #define Q8_GET_STATS_CMD_TYPE_ALL      (0x7 << 2)
 820
 821 } __packed q80_get_stats_t;
 822
 823 typedef struct _q80_get_stats_rsp {
 824         uint16_t        opcode;
 825         uint16_t        regcnt_status;
 826         uint32_t        cmd;
 827         union {
 828                 q80_rcv_stats_t rcv;
 829                 q80_xmt_stats_t xmt;
 830                 q80_mac_stats_t mac;
 831         } u;
 832 } __packed q80_get_stats_rsp_t;
 833
 834 typedef struct _q80_get_mac_rcv_xmt_stats_rsp {
 835         uint16_t        opcode;
 836         uint16_t        regcnt_status;
 837         uint32_t        cmd;
 838         q80_mac_stats_t mac;
 839         q80_rcv_stats_t rcv;
 840         q80_xmt_stats_t xmt;
 841 } __packed q80_get_mac_rcv_xmt_stats_rsp_t;
 842
 843 /*
 844  * Init NIC Function
 845  * Used to Register DCBX Configuration Change AEN
 846  */
 847 typedef struct _q80_init_nic_func {
 848         uint16_t        opcode;
 849         uint16_t        count_version;
 850
 851         uint32_t        options;
 852 #define Q8_INIT_NIC_REG_IDC_AEN         0x01
 853 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN   0x02
 854 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN    0x04
 855
 856 } __packed q80_init_nic_func_t;
 857
 858 typedef struct _q80_init_nic_func_rsp {
 859         uint16_t        opcode;
 860         uint16_t        regcnt_status;
 861 } __packed q80_init_nic_func_rsp_t;
 862
 863 /*
 864  * Stop NIC Function
 865  * Used to DeRegister DCBX Configuration Change AEN
 866  */
 867 typedef struct _q80_stop_nic_func {
 868         uint16_t        opcode;
 869         uint16_t        count_version;
 870
 871         uint32_t        options;
 872 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
 873 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN  0x04
 874
 875 } __packed q80_stop_nic_func_t;
 876
 877 typedef struct _q80_stop_nic_func_rsp {
 878         uint16_t        opcode;
 879         uint16_t        regcnt_status;
 880 } __packed q80_stop_nic_func_rsp_t;
 881
 882 /*
 883  * Query Firmware DCBX Capabilities
 884  */
 885 typedef struct _q80_query_fw_dcbx_caps {
 886         uint16_t        opcode;
 887         uint16_t        count_version;
 888 } __packed q80_query_fw_dcbx_caps_t;
 889
 890 typedef struct _q80_query_fw_dcbx_caps_rsp {
 891         uint16_t        opcode;
 892         uint16_t        regcnt_status;
 893
 894         uint32_t        dcbx_caps;
 895 #define Q8_QUERY_FW_DCBX_CAPS_TSA               0x00000001
 896 #define Q8_QUERY_FW_DCBX_CAPS_ETS               0x00000002
 897 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01     0x00000004
 898 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0     0x00000008
 899 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK            0x00F00000
 900 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK        0x0F000000
 901 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK        0xF0000000
 902
 903 } __packed q80_query_fw_dcbx_caps_rsp_t;
 904
 905 /*
 906  * IDC Ack Cmd
 907  */
 908
 909 typedef struct _q80_idc_ack {
 910         uint16_t        opcode;
 911         uint16_t        count_version;
 912
 913         uint32_t        aen_mb1;
 914         uint32_t        aen_mb2;
 915         uint32_t        aen_mb3;
 916         uint32_t        aen_mb4;
 917
 918 } __packed q80_idc_ack_t;
 919
 920 typedef struct _q80_idc_ack_rsp {
 921         uint16_t        opcode;
 922         uint16_t        regcnt_status;
 923 } __packed q80_idc_ack_rsp_t;
 924
 925
 926 /*
 927  * Set Port Configuration command
 928  * Used to set Ethernet Standard Pause values
 929  */
 930
 931 typedef struct _q80_set_port_cfg {
 932         uint16_t        opcode;
 933         uint16_t        count_version;
 934
 935         uint32_t        cfg_bits;
 936
 937 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK     (0x7 << 1)
 938 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE     (0x0 << 1)
 939 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS      (0x2 << 1)
 940 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY      (0x3 << 1)
 941 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT      (0x4 << 1)
 942
 943 #define Q8_VALID_LOOPBACK_MODE(mode) \
 944              (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
 945                 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
 946                  ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
 947
 948 #define Q8_PORT_CFG_BITS_DCBX_ENABLE            BIT_4
 949
 950 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK         (0x3 << 5)
 951 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED         (0x0 << 5)
 952 #define Q8_PORT_CFG_BITS_PAUSE_STD              (0x1 << 5)
 953 #define Q8_PORT_CFG_BITS_PAUSE_PPM              (0x2 << 5)
 954
 955 #define Q8_PORT_CFG_BITS_LNKCAP_10MB            BIT_8
 956 #define Q8_PORT_CFG_BITS_LNKCAP_100MB           BIT_9
 957 #define Q8_PORT_CFG_BITS_LNKCAP_1GB             BIT_10
 958 #define Q8_PORT_CFG_BITS_LNKCAP_10GB            BIT_11
 959
 960 #define Q8_PORT_CFG_BITS_AUTONEG                BIT_15
 961 #define Q8_PORT_CFG_BITS_XMT_DISABLE            BIT_17
 962 #define Q8_PORT_CFG_BITS_FEC_RQSTD              BIT_18
 963 #define Q8_PORT_CFG_BITS_EEE_RQSTD              BIT_19
 964
 965 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK      (0x3 << 20)
 966 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV       (0x0 << 20)
 967 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT           (0x1 << 20)
 968 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV           (0x2 << 20)
 969
 970 } __packed q80_set_port_cfg_t;
 971
 972 typedef struct _q80_set_port_cfg_rsp {
 973         uint16_t        opcode;
 974         uint16_t        regcnt_status;
 975 } __packed q80_set_port_cfg_rsp_t;
 976
 977 /*
 978  * Get Port Configuration Command
 979  */
 980
 981 typedef struct _q80_get_port_cfg {
 982         uint16_t        opcode;
 983         uint16_t        count_version;
 984 } __packed q80_get_port_cfg_t;
 985
 986 typedef struct _q80_get_port_cfg_rsp {
 987         uint16_t        opcode;
 988         uint16_t        regcnt_status;
 989
 990         uint32_t        cfg_bits; /* same as in q80_set_port_cfg_t */
 991
 992         uint8_t         phys_port_type;
 993         uint8_t         rsvd[3];
 994 } __packed q80_get_port_cfg_rsp_t;
 995
 996 /*
 997  * Get Link Status Command
 998  * Used to get current PAUSE values for the port
 999  */
1000
1001 typedef struct _q80_get_link_status {
1002         uint16_t        opcode;
1003         uint16_t        count_version;
1004 } __packed q80_get_link_status_t;
1005
1006 typedef struct _q80_get_link_status_rsp {
1007         uint16_t        opcode;
1008         uint16_t        regcnt_status;
1009
1010         uint32_t        cfg_bits;
1011 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP               BIT_0
1012
1013 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK       (0x7 << 3)
1014 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN    (0x0 << 3)
1015 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB       (0x1 << 3)
1016 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB      (0x2 << 3)
1017 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB        (0x3 << 3)
1018 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB       (0x4 << 3)
1019
1020 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK        (0x3 << 6)
1021 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE     (0x0 << 6)
1022 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD         (0x1 << 6)
1023 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM         (0x2 << 6)
1024
1025 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK         (0x7 << 8)
1026 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE         (0x0 << 6)
1027 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS          (0x2 << 6)
1028 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY          (0x3 << 6)
1029
1030 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED           BIT_12
1031 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED           BIT_13
1032
1033 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK     (0x3 << 20)
1034 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE         (0x0 << 20)
1035 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT          (0x1 << 20)
1036 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV          (0x2 << 20)
1037 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV      (0x3 << 20)
1038
1039         uint32_t        link_state;
1040 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL                 BIT_0
1041 #define Q8_GET_LINK_STAT_PORT_RST_DONE                  BIT_3
1042 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN                  BIT_4
1043 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN                  BIT_5
1044 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT                BIT_6
1045 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT               BIT_7
1046 #define Q8_GET_LINK_STAT_XMT_DISABLED                   BIT_9
1047 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
1048
1049         uint32_t        sfp_info;
1050 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK                0x3
1051 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED        0x0
1052 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE                0x1
1053 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID             0x2
1054 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID               0x3
1055
1056 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK            (0x3 << 2)
1057 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR     (0x0 << 2)
1058 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC      (0x1 << 2)
1059 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED    (0x2 << 2)
1060 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR    (0x3 << 2)
1061
1062 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK              (0x1F << 4)
1063 #define Q8_GET_LINK_STAT_SFP_MOD_NONE                   (0x00 << 4)
1064 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM                (0x01 << 4)
1065 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR                 (0x02 << 4)
1066 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR                 (0x03 << 4)
1067 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P                (0x04 << 4)
1068 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL               (0x05 << 4)
1069 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL               (0x06 << 4)
1070 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX                  (0x07 << 4)
1071 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX                  (0x08 << 4)
1072 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX                  (0x09 << 4)
1073 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT                   (0x0A << 4)
1074 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL                (0x0B << 4)
1075 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN                (0x0F << 4)
1076
1077 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD             BIT_9
1078 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
1079 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK     (0xFF << 16)
1080
1081 } __packed q80_get_link_status_rsp_t;
1082
1083
1084 /*
1085  * Transmit Related Definitions
1086  */
1087 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
1088 #define MAX_TCNTXT_RINGS           8
1089
1090 /*
1091  * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
1092  */
1093
1094 typedef struct _q80_rq_tx_ring {
1095         uint64_t        paddr;
1096         uint64_t        tx_consumer;
1097         uint16_t        nentries;
1098         uint16_t        intr_id;
1099         uint8_t         intr_src_bit;
1100         uint8_t         rsrvd[3];
1101 } __packed q80_rq_tx_ring_t;
1102
1103 typedef struct _q80_rq_tx_cntxt {
1104         uint16_t                opcode;
1105         uint16_t                count_version;
1106
1107         uint32_t                cap0;
1108 #define Q8_TX_CNTXT_CAP0_BASEFW         (1 << 0)
1109 #define Q8_TX_CNTXT_CAP0_LSO            (1 << 6)
1110 #define Q8_TX_CNTXT_CAP0_TC             (1 << 25)
1111
1112         uint32_t                cap1;
1113         uint32_t                cap2;
1114         uint32_t                cap3;
1115         uint8_t                 ntx_rings;
1116         uint8_t                 traffic_class; /* bits 8-10; others reserved */
1117         uint16_t                tx_vpid;
1118         q80_rq_tx_ring_t        tx_ring[MAX_TCNTXT_RINGS];
1119 } __packed q80_rq_tx_cntxt_t;
1120
1121 typedef struct _q80_rsp_tx_ring {
1122         uint32_t                prod_index;
1123         uint16_t                cntxt_id;
1124         uint8_t                 state;
1125         uint8_t                 rsrvd;
1126 } q80_rsp_tx_ring_t;
1127
1128 typedef struct _q80_rsp_tx_cntxt {
1129         uint16_t                opcode;
1130         uint16_t                regcnt_status;
1131         uint8_t                 ntx_rings;
1132         uint8_t                 phy_port;
1133         uint8_t                 virt_port;
1134         uint8_t                 rsrvd;
1135         q80_rsp_tx_ring_t       tx_ring[MAX_TCNTXT_RINGS];
1136 } __packed q80_rsp_tx_cntxt_t;
1137
1138 typedef struct _q80_tx_cntxt_destroy {
1139         uint16_t        opcode;
1140         uint16_t        count_version;
1141         uint32_t        cntxt_id;
1142 } __packed q80_tx_cntxt_destroy_t;
1143
1144 typedef struct _q80_tx_cntxt_destroy_rsp {
1145         uint16_t        opcode;
1146         uint16_t        regcnt_status;
1147 } __packed q80_tx_cntxt_destroy_rsp_t;
1148
1149 /*
1150  * Transmit Command Descriptor
1151  * These commands are issued on the Transmit Ring associated with a Transmit
1152  * context
1153  */
1154 typedef struct _q80_tx_cmd {
1155         uint8_t         tcp_hdr_off;    /* TCP Header Offset */
1156         uint8_t         ip_hdr_off;     /* IP Header Offset */
1157         uint16_t        flags_opcode;   /* Bits 0-6: flags; 7-12: opcode */
1158
1159         /* flags field */
1160 #define Q8_TX_CMD_FLAGS_MULTICAST       0x01
1161 #define Q8_TX_CMD_FLAGS_LSO_TSO         0x02
1162 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED     0x10
1163 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID      0x40
1164
1165         /* opcode field */
1166 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6        (0xC << 7)
1167 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6        (0xB << 7)
1168 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6           (0x6 << 7)
1169 #define Q8_TX_CMD_OP_XMT_TCP_LSO                (0x5 << 7)
1170 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM             (0x3 << 7)
1171 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM             (0x2 << 7)
1172 #define Q8_TX_CMD_OP_XMT_ETHER                  (0x1 << 7)
1173
1174         uint8_t         n_bufs;         /* # of data segs in data buffer */
1175         uint8_t         data_len_lo;    /* data length lower 8 bits */
1176         uint16_t        data_len_hi;    /* data length upper 16 bits */
1177
1178         uint64_t        buf2_addr;      /* buffer 2 address */
1179
1180         uint16_t        rsrvd0;
1181         uint16_t        mss;            /* MSS for this packet */
1182         uint8_t         cntxtid;        /* Bits 7-4: ContextId; 3-0: reserved */
1183
1184 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1185
1186         uint8_t         total_hdr_len;  /* MAC+IP+TCP Header Length for LSO */
1187         uint16_t        rsrvd1;
1188
1189         uint64_t        buf3_addr;      /* buffer 3 address */
1190         uint64_t        buf1_addr;      /* buffer 1 address */
1191
1192         uint16_t        buf1_len;       /* length of buffer 1 */
1193         uint16_t        buf2_len;       /* length of buffer 2 */
1194         uint16_t        buf3_len;       /* length of buffer 3 */
1195         uint16_t        buf4_len;       /* length of buffer 4 */
1196
1197         uint64_t        buf4_addr;      /* buffer 4 address */
1198
1199         uint32_t        rsrvd2;
1200         uint16_t        rsrvd3;
1201         uint16_t        vlan_tci;       /* VLAN TCI when hw tagging is enabled*/
1202
1203 } __packed q80_tx_cmd_t; /* 64 bytes */
1204
1205 #define Q8_TX_CMD_MAX_SEGMENTS          4
1206 #define Q8_TX_CMD_TSO_ALIGN             2
1207 #define Q8_TX_MAX_NON_TSO_SEGS          62
1208
1209
1210 /*
1211  * Receive Related Definitions
1212  */
1213 #define MAX_RDS_RING_SETS       8 /* Max# of Receive Descriptor Rings */
1214
1215 #ifdef QL_ENABLE_ISCSI_TLV
1216 #define MAX_SDS_RINGS           32 /* Max# of Status Descriptor Rings */
1217 #define NUM_TX_RINGS            (MAX_SDS_RINGS * 2)
1218 #else
1219 #define MAX_SDS_RINGS           4 /* Max# of Status Descriptor Rings */
1220 #define NUM_TX_RINGS            MAX_SDS_RINGS
1221 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */
1222 #define MAX_RDS_RINGS           MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1223
1224
1225 typedef struct _q80_rq_sds_ring {
1226         uint64_t paddr; /* physical addr of status ring in system memory */
1227         uint64_t hdr_split1;
1228         uint64_t hdr_split2;
1229         uint16_t size; /* number of entries in status ring */
1230         uint16_t hdr_split1_size;
1231         uint16_t hdr_split2_size;
1232         uint16_t hdr_split_count;
1233         uint16_t intr_id;
1234         uint8_t  intr_src_bit;
1235         uint8_t  rsrvd[5];
1236 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1237
1238 typedef struct _q80_rq_rds_ring {
1239         uint64_t paddr_std;     /* physical addr of rcv ring in system memory */
1240         uint64_t paddr_jumbo;   /* physical addr of rcv ring in system memory */
1241         uint16_t std_bsize;
1242         uint16_t std_nentries;
1243         uint16_t jumbo_bsize;
1244         uint16_t jumbo_nentries;
1245 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1246
1247 #define MAX_RCNTXT_SDS_RINGS    8
1248
1249 typedef struct _q80_rq_rcv_cntxt {
1250         uint16_t                opcode;
1251         uint16_t                count_version;
1252         uint32_t                cap0;
1253 #define Q8_RCV_CNTXT_CAP0_BASEFW        (1 << 0)
1254 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS     (1 << 1)
1255 #define Q8_RCV_CNTXT_CAP0_LRO           (1 << 5)
1256 #define Q8_RCV_CNTXT_CAP0_HW_LRO        (1 << 10)
1257 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN    (1 << 14)
1258 #define Q8_RCV_CNTXT_CAP0_RSS           (1 << 15)
1259 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS      (1 << 16)
1260 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO     (1 << 18)
1261 #define Q8_RCV_CNTXT_CAP0_SGL_LRO       (1 << 19)
1262 #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO  (1 << 26)
1263
1264         uint32_t                cap1;
1265         uint32_t                cap2;
1266         uint32_t                cap3;
1267         uint8_t                 nrds_sets_rings;
1268         uint8_t                 nsds_rings;
1269         uint16_t                rds_producer_mode;
1270 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE       0
1271 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED       1
1272
1273         uint16_t                rcv_vpid;
1274         uint16_t                rsrvd0;
1275         uint32_t                rsrvd1;
1276         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1277         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1278 } __packed q80_rq_rcv_cntxt_t;
1279
1280 typedef struct _q80_rsp_rds_ring {
1281         uint32_t prod_std;
1282         uint32_t prod_jumbo;
1283 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1284
1285 typedef struct _q80_rsp_rcv_cntxt {
1286         uint16_t                opcode;
1287         uint16_t                regcnt_status;
1288         uint8_t                 nrds_sets_rings;
1289         uint8_t                 nsds_rings;
1290         uint16_t                cntxt_id;
1291         uint8_t                 state;
1292         uint8_t                 num_funcs;
1293         uint8_t                 phy_port;
1294         uint8_t                 virt_port;
1295         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1296         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1297 } __packed q80_rsp_rcv_cntxt_t;
1298
1299 typedef struct _q80_rcv_cntxt_destroy {
1300         uint16_t        opcode;
1301         uint16_t        count_version;
1302         uint32_t        cntxt_id;
1303 } __packed q80_rcv_cntxt_destroy_t;
1304
1305 typedef struct _q80_rcv_cntxt_destroy_rsp {
1306         uint16_t        opcode;
1307         uint16_t        regcnt_status;
1308 } __packed q80_rcv_cntxt_destroy_rsp_t;
1309
1310
1311 /*
1312  * Add Receive Rings
1313  */
1314 typedef struct _q80_rq_add_rcv_rings {
1315         uint16_t                opcode;
1316         uint16_t                count_version;
1317         uint8_t                 nrds_sets_rings;
1318         uint8_t                 nsds_rings;
1319         uint16_t                cntxt_id;
1320         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1321         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1322 } __packed q80_rq_add_rcv_rings_t;
1323
1324 typedef struct _q80_rsp_add_rcv_rings {
1325         uint16_t                opcode;
1326         uint16_t                regcnt_status;
1327         uint8_t                 nrds_sets_rings;
1328         uint8_t                 nsds_rings;
1329         uint16_t                cntxt_id;
1330         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1331         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1332 } __packed q80_rsp_add_rcv_rings_t;
1333
1334 /*
1335  * Map Status Ring to Receive Descriptor Set
1336  */
1337
1338 #define MAX_SDS_TO_RDS_MAP      16
1339
1340 typedef struct _q80_sds_rds_map_e {
1341         uint8_t sds_ring;
1342         uint8_t rsrvd0;
1343         uint8_t rds_ring;
1344         uint8_t rsrvd1;
1345 } __packed q80_sds_rds_map_e_t;
1346
1347 typedef struct _q80_rq_map_sds_to_rds {
1348         uint16_t                opcode;
1349         uint16_t                count_version;
1350         uint16_t                cntxt_id;
1351         uint16_t                num_rings;
1352         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1353 } __packed q80_rq_map_sds_to_rds_t;
1354
1355
1356 typedef struct _q80_rsp_map_sds_to_rds {
1357         uint16_t                opcode;
1358         uint16_t                regcnt_status;
1359         uint16_t                cntxt_id;
1360         uint16_t                num_rings;
1361         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1362 } __packed q80_rsp_map_sds_to_rds_t;
1363
1364
1365 /*
1366  * Receive Descriptor corresponding to each entry in the receive ring
1367  */
1368 typedef struct _q80_rcv_desc {
1369         uint16_t handle;
1370         uint16_t rsrvd;
1371         uint32_t buf_size; /* buffer size in bytes */
1372         uint64_t buf_addr; /* physical address of buffer */
1373 } __packed q80_recv_desc_t;
1374
1375 /*
1376  * Status Descriptor corresponding to each entry in the Status ring
1377  */
1378 typedef struct _q80_stat_desc {
1379         uint64_t data[2];
1380 } __packed q80_stat_desc_t;
1381
1382 /*
1383  * definitions for data[0] field of Status Descriptor
1384  */
1385 #define Q8_STAT_DESC_RSS_HASH(data)             (data & 0xFFFFFFFF)
1386 #define Q8_STAT_DESC_TOTAL_LENGTH(data)         ((data >> 32) & 0x3FFF)
1387 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF)
1388 #define Q8_STAT_DESC_HANDLE(data)               ((data >> 48) & 0xFFFF)
1389 /*
1390  * definitions for data[1] field of Status Descriptor
1391  */
1392
1393 #define Q8_STAT_DESC_OPCODE(data)               ((data >> 42) & 0xF)
1394 #define         Q8_STAT_DESC_OPCODE_RCV_PKT             0x01
1395 #define         Q8_STAT_DESC_OPCODE_LRO_PKT             0x02
1396 #define         Q8_STAT_DESC_OPCODE_SGL_LRO             0x04
1397 #define         Q8_STAT_DESC_OPCODE_SGL_RCV             0x05
1398 #define         Q8_STAT_DESC_OPCODE_CONT                0x06
1399
1400 /*
1401  * definitions for data[1] field of Status Descriptor for standard frames
1402  * status descriptor opcode equals 0x04
1403  */
1404 #define Q8_STAT_DESC_STATUS(data)               ((data >> 39) & 0x0007)
1405 #define         Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE     0x00
1406 #define         Q8_STAT_DESC_STATUS_NO_CHKSUM           0x01
1407 #define         Q8_STAT_DESC_STATUS_CHKSUM_OK           0x02
1408 #define         Q8_STAT_DESC_STATUS_CHKSUM_ERR          0x03
1409
1410 #define Q8_STAT_DESC_VLAN(data)                 ((data >> 47) & 1)
1411 #define Q8_STAT_DESC_VLAN_ID(data)              ((data >> 48) & 0xFFFF)
1412
1413 #define Q8_STAT_DESC_PROTOCOL(data)             ((data >> 44) & 0x000F)
1414 #define Q8_STAT_DESC_L2_OFFSET(data)            ((data >> 48) & 0x001F)
1415 #define Q8_STAT_DESC_COUNT(data)                ((data >> 37) & 0x0007)
1416
1417 /*
1418  * definitions for data[0-1] fields of Status Descriptor for LRO
1419  * status descriptor opcode equals 0x04
1420  */
1421
1422 /* definitions for data[1] field */
1423 #define Q8_LRO_STAT_DESC_SEQ_NUM(data)          (uint32_t)(data)
1424
1425 /*
1426  * definitions specific to opcode 0x04 data[1]
1427  */
1428 #define Q8_STAT_DESC_COUNT_SGL_LRO(data)        ((data >> 13) & 0x0007)
1429 #define Q8_SGL_LRO_STAT_L2_OFFSET(data)         ((data >> 16) & 0xFF)
1430 #define Q8_SGL_LRO_STAT_L4_OFFSET(data)         ((data >> 24) & 0xFF)
1431 #define Q8_SGL_LRO_STAT_TS(data)                ((data >> 40) & 0x1)
1432 #define Q8_SGL_LRO_STAT_PUSH_BIT(data)          ((data >> 41) & 0x1)
1433
1434
1435 /*
1436  * definitions specific to opcode 0x05 data[1]
1437  */
1438 #define Q8_STAT_DESC_COUNT_SGL_RCV(data)        ((data >> 37) & 0x0003)
1439
1440 /*
1441  * definitions for opcode 0x06
1442  */
1443 /* definitions for data[0] field */
1444 #define Q8_SGL_STAT_DESC_HANDLE1(data)          (data & 0xFFFF)
1445 #define Q8_SGL_STAT_DESC_HANDLE2(data)          ((data >> 16) & 0xFFFF)
1446 #define Q8_SGL_STAT_DESC_HANDLE3(data)          ((data >> 32) & 0xFFFF)
1447 #define Q8_SGL_STAT_DESC_HANDLE4(data)          ((data >> 48) & 0xFFFF)
1448
1449 /* definitions for data[1] field */
1450 #define Q8_SGL_STAT_DESC_HANDLE5(data)          (data & 0xFFFF)
1451 #define Q8_SGL_STAT_DESC_HANDLE6(data)          ((data >> 16) & 0xFFFF)
1452 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data)      ((data >> 32) & 0x7)
1453 #define Q8_SGL_STAT_DESC_HANDLE7(data)          ((data >> 48) & 0xFFFF)
1454
1455 /** Driver Related Definitions Begin **/
1456
1457 #define TX_SMALL_PKT_SIZE       128 /* size in bytes of small packets */
1458
1459 /* The number of descriptors should be a power of 2 */
1460 #define NUM_TX_DESCRIPTORS              1024
1461 #define NUM_STATUS_DESCRIPTORS          1024
1462
1463
1464 #define NUM_RX_DESCRIPTORS      2048
1465
1466 /*
1467  * structure describing various dma buffers
1468  */
1469
1470 typedef struct qla_dmabuf {
1471         volatile struct {
1472                 uint32_t        tx_ring         :1,
1473                                 rds_ring        :1,
1474                                 sds_ring        :1,
1475                                 minidump        :1;
1476         } flags;
1477
1478         qla_dma_t               tx_ring;
1479         qla_dma_t               rds_ring[MAX_RDS_RINGS];
1480         qla_dma_t               sds_ring[MAX_SDS_RINGS];
1481         qla_dma_t               minidump;
1482 } qla_dmabuf_t;
1483
1484 typedef struct _qla_sds {
1485         q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1486         uint32_t        sdsr_next; /* next entry in SDS ring to process */
1487         struct lro_ctrl lro;
1488         void            *rxb_free;
1489         uint32_t        rx_free;
1490         volatile uint32_t rcv_active;
1491         uint32_t        sds_consumer;
1492         uint64_t        intr_count;
1493         uint64_t        spurious_intr_count;
1494 } qla_sds_t;
1495
1496 #define Q8_MAX_LRO_CONT_DESC    7
1497 #define Q8_MAX_HANDLES_LRO      (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1498 #define Q8_MAX_HANDLES_NON_LRO  8
1499
1500 typedef struct _qla_sgl_rcv {
1501         uint16_t        pkt_length;
1502         uint16_t        num_handles;
1503         uint16_t        chksum_status;
1504         uint32_t        rss_hash;
1505         uint16_t        rss_hash_flags;
1506         uint16_t        vlan_tag;
1507         uint16_t        handle[Q8_MAX_HANDLES_NON_LRO];
1508 } qla_sgl_rcv_t;
1509
1510 typedef struct _qla_sgl_lro {
1511         uint16_t        flags;
1512 #define Q8_LRO_COMP_TS          0x1
1513 #define Q8_LRO_COMP_PUSH_BIT    0x2
1514         uint16_t        l2_offset;
1515         uint16_t        l4_offset;
1516
1517         uint16_t        payload_length;
1518         uint16_t        num_handles;
1519         uint32_t        rss_hash;
1520         uint16_t        rss_hash_flags;
1521         uint16_t        vlan_tag;
1522         uint16_t        handle[Q8_MAX_HANDLES_LRO];
1523 } qla_sgl_lro_t;
1524
1525 typedef union {
1526         qla_sgl_rcv_t   rcv;
1527         qla_sgl_lro_t   lro;
1528 } qla_sgl_comp_t;
1529
1530 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1531                 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1532
1533 typedef struct _qla_hw_tx_cntxt {
1534         q80_tx_cmd_t    *tx_ring_base;
1535         bus_addr_t      tx_ring_paddr;
1536
1537         volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1538         bus_addr_t      tx_cons_paddr;
1539
1540         volatile uint32_t txr_free; /* # of free entries in tx ring */
1541         volatile uint32_t txr_next; /* # next available tx ring entry */
1542         volatile uint32_t txr_comp; /* index of last tx entry completed */
1543
1544         uint32_t        tx_prod_reg;
1545         uint16_t        tx_cntxt_id;
1546
1547 } qla_hw_tx_cntxt_t;
1548
1549 typedef struct _qla_mcast {
1550         uint16_t        rsrvd;
1551         uint8_t         addr[ETHER_ADDR_LEN];
1552 } __packed qla_mcast_t;
1553
1554 typedef struct _qla_rdesc {
1555         volatile uint32_t prod_std;
1556         volatile uint32_t prod_jumbo;
1557         volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1558         volatile int32_t  rx_in; /* next standard rcv ring to add mbufs */
1559         volatile uint64_t count;
1560 } qla_rdesc_t;
1561
1562 typedef struct _qla_flash_desc_table {
1563         uint32_t        flash_valid;
1564         uint16_t        flash_ver;
1565         uint16_t        flash_len;
1566         uint16_t        flash_cksum;
1567         uint16_t        flash_unused;
1568         uint8_t         flash_model[16];
1569         uint16_t        flash_manuf;
1570         uint16_t        flash_id;
1571         uint8_t         flash_flag;
1572         uint8_t         erase_cmd;
1573         uint8_t         alt_erase_cmd;
1574         uint8_t         write_enable_cmd;
1575         uint8_t         write_enable_bits;
1576         uint8_t         write_statusreg_cmd;
1577         uint8_t         unprotected_sec_cmd;
1578         uint8_t         read_manuf_cmd;
1579         uint32_t        block_size;
1580         uint32_t        alt_block_size;
1581         uint32_t        flash_size;
1582         uint32_t        write_enable_data;
1583         uint8_t         readid_addr_len;
1584         uint8_t         write_disable_bits;
1585         uint8_t         read_dev_id_len;
1586         uint8_t         chip_erase_cmd;
1587         uint16_t        read_timeo;
1588         uint8_t         protected_sec_cmd;
1589         uint8_t         resvd[65];
1590 } __packed qla_flash_desc_table_t;
1591
1592 /*
1593  * struct for storing hardware specific information for a given interface
1594  */
1595 typedef struct _qla_hw {
1596         struct {
1597                 uint32_t
1598                         unicast_mac     :1,
1599                         bcast_mac       :1,
1600                         loopback_mode   :2,
1601                         init_tx_cnxt    :1,
1602                         init_rx_cnxt    :1,
1603                         init_intr_cnxt  :1,
1604                         fduplex         :1,
1605                         autoneg         :1,
1606                         fdt_valid       :1;
1607         } flags;
1608
1609
1610         uint16_t        link_speed;
1611         uint16_t        cable_length;
1612         uint32_t        cable_oui;
1613         uint8_t         link_up;
1614         uint8_t         module_type;
1615         uint8_t         link_faults;
1616
1617         uint8_t         mac_rcv_mode;
1618
1619         uint32_t        max_mtu;
1620
1621         uint8_t         mac_addr[ETHER_ADDR_LEN];
1622
1623         uint32_t        num_sds_rings;
1624         uint32_t        num_rds_rings;
1625         uint32_t        num_tx_rings;
1626
1627         qla_dmabuf_t    dma_buf;
1628
1629         /* Transmit Side */
1630
1631         qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1632
1633         /* Receive Side */
1634
1635         uint16_t        rcv_cntxt_id;
1636
1637         uint32_t        mbx_intr_mask_offset;
1638
1639         uint16_t        intr_id[MAX_SDS_RINGS];
1640         uint32_t        intr_src[MAX_SDS_RINGS];
1641
1642         qla_sds_t       sds[MAX_SDS_RINGS];
1643         uint32_t        mbox[Q8_NUM_MBOX];
1644         qla_rdesc_t     rds[MAX_RDS_RINGS];
1645
1646         uint32_t        rds_pidx_thres;
1647         uint32_t        sds_cidx_thres;
1648
1649         uint32_t        rcv_intr_coalesce;
1650         uint32_t        xmt_intr_coalesce;
1651
1652         /* Immediate Completion */
1653         volatile uint32_t imd_compl;
1654         volatile uint32_t aen_mb0;
1655         volatile uint32_t aen_mb1;
1656         volatile uint32_t aen_mb2;
1657         volatile uint32_t aen_mb3;
1658         volatile uint32_t aen_mb4;
1659
1660         /* multicast address list */
1661         uint32_t        nmcast;
1662         qla_mcast_t     mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1663         uint8_t         mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)];
1664
1665         /* reset sequence */
1666 #define Q8_MAX_RESET_SEQ_IDX    16
1667         uint32_t        rst_seq[Q8_MAX_RESET_SEQ_IDX];
1668         uint32_t        rst_seq_idx;
1669
1670         /* heart beat register value */
1671         uint32_t        hbeat_value;
1672         uint32_t        health_count;
1673
1674         uint32_t        max_tx_segs;
1675         uint32_t        min_lro_pkt_size;
1676
1677         uint32_t        enable_9kb;
1678
1679         uint32_t        user_pri_nic;
1680         uint32_t        user_pri_iscsi;
1681         uint64_t        iscsi_pkt_count;
1682
1683         /* Flash Descriptor Table */
1684         qla_flash_desc_table_t fdt;
1685
1686         /* Minidump Related */
1687         uint32_t        mdump_init;
1688         uint32_t        mdump_done;
1689         uint32_t        mdump_active;
1690         uint32_t        mdump_capture_mask;
1691         uint32_t        mdump_start_seq_index;
1692         void            *mdump_buffer;
1693         uint32_t        mdump_buffer_size;
1694         void            *mdump_template;
1695         uint32_t        mdump_template_size;
1696 } qla_hw_t;
1697
1698 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1699                 bus_write_4((ha->pci_reg), prod_reg, val);
1700
1701 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1702                 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1703
1704 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1705         bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1706
1707 #define QL_ENABLE_INTERRUPTS(ha, i) \
1708                 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1709
1710 #define QL_BUFFER_ALIGN                16
1711
1712
1713 /*
1714  * Flash Configuration
1715  */
1716 #define Q8_BOARD_CONFIG_OFFSET          0x370000
1717 #define Q8_BOARD_CONFIG_LENGTH          0x2000
1718
1719 #define Q8_BOARD_CONFIG_MAC0_LO         0x400
1720
1721 #define Q8_FDT_LOCK_MAGIC_ID            0x00FD00FD
1722 #define Q8_FDT_FLASH_ADDR_VAL           0xFD009F
1723 #define Q8_FDT_FLASH_CTRL_VAL           0x3F
1724 #define Q8_FDT_MASK_VAL                 0xFF
1725
1726 #define Q8_WR_ENABLE_FL_ADDR            0xFD0100
1727 #define Q8_WR_ENABLE_FL_CTRL            0x5
1728
1729 #define Q8_ERASE_LOCK_MAGIC_ID          0x00EF00EF
1730 #define Q8_ERASE_FL_ADDR_MASK           0xFD0300
1731 #define Q8_ERASE_FL_CTRL_MASK           0x3D
1732
1733 #define Q8_WR_FL_LOCK_MAGIC_ID          0xABCDABCD
1734 #define Q8_WR_FL_ADDR_MASK              0x800000
1735 #define Q8_WR_FL_CTRL_MASK              0x3D
1736
1737 #define QL_FDT_OFFSET                   0x3F0000
1738 #define Q8_FLASH_SECTOR_SIZE            0x10000
1739
1740 /*
1741  * Off Chip Memory Access
1742  */
1743
1744 typedef struct _q80_offchip_mem_val {
1745         uint32_t data_lo;
1746         uint32_t data_hi;
1747         uint32_t data_ulo;
1748         uint32_t data_uhi;
1749 } q80_offchip_mem_val_t;
1750
1751 #endif /* #ifndef _QL_HW_H_ */