sys/dev/qlxgbe/ql_isr.c

   1 /*
   2  * Copyright (c) 2013-2016 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File: ql_isr.c
  30  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36
  37 #include "ql_os.h"
  38 #include "ql_hw.h"
  39 #include "ql_def.h"
  40 #include "ql_inline.h"
  41 #include "ql_ver.h"
  42 #include "ql_glbl.h"
  43 #include "ql_dbg.h"
  44
  45 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp,
  46                 uint32_t r_idx);
  47
  48 static void
  49 qla_rcv_error(qla_host_t *ha)
  50 {
  51         ha->flags.stop_rcv = 1;
  52         ha->qla_initiate_recovery = 1;
  53 }
  54
  55
  56 /*
  57  * Name: qla_rx_intr
  58  * Function: Handles normal ethernet frames received
  59  */
  60 static void
  61 qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx)
  62 {
  63         qla_rx_buf_t            *rxb;
  64         struct mbuf             *mp = NULL, *mpf = NULL, *mpl = NULL;
  65         struct ifnet            *ifp = ha->ifp;
  66         qla_sds_t               *sdsp;
  67         struct ether_vlan_header *eh;
  68         uint32_t                i, rem_len = 0;
  69         uint32_t                r_idx = 0;
  70         qla_rx_ring_t           *rx_ring;
  71
  72         if (ha->hw.num_rds_rings > 1)
  73                 r_idx = sds_idx;
  74
  75         ha->hw.rds[r_idx].count++;
  76
  77         sdsp = &ha->hw.sds[sds_idx];
  78         rx_ring = &ha->rx_ring[r_idx];
  79
  80         for (i = 0; i < sgc->num_handles; i++) {
  81                 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
  82
  83                 QL_ASSERT(ha, (rxb != NULL),
  84                         ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
  85                         sds_idx));
  86
  87                 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) {
  88                         /* log the error */
  89                         device_printf(ha->pci_dev,
  90                                 "%s invalid rxb[%d, %d, 0x%04x]\n",
  91                                 __func__, sds_idx, i, sgc->handle[i]);
  92                         qla_rcv_error(ha);
  93                         return;
  94                 }
  95
  96                 mp = rxb->m_head;
  97                 if (i == 0)
  98                         mpf = mp;
  99
 100                 QL_ASSERT(ha, (mp != NULL),
 101                         ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
 102                         sds_idx));
 103
 104                 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
 105
 106                 rxb->m_head = NULL;
 107                 rxb->next = sdsp->rxb_free;
 108                 sdsp->rxb_free = rxb;
 109                 sdsp->rx_free++;
 110
 111                 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) {
 112                         /* log the error */
 113                         device_printf(ha->pci_dev,
 114                                 "%s mp  == NULL [%d, %d, 0x%04x]\n",
 115                                 __func__, sds_idx, i, sgc->handle[i]);
 116                         qla_rcv_error(ha);
 117                         return;
 118                 }
 119
 120                 if (i == 0) {
 121                         mpl = mpf = mp;
 122                         mp->m_flags |= M_PKTHDR;
 123                         mp->m_pkthdr.len = sgc->pkt_length;
 124                         mp->m_pkthdr.rcvif = ifp;
 125                         rem_len = mp->m_pkthdr.len;
 126                 } else {
 127                         mp->m_flags &= ~M_PKTHDR;
 128                         mpl->m_next = mp;
 129                         mpl = mp;
 130                         rem_len = rem_len - mp->m_len;
 131                 }
 132         }
 133
 134         mpl->m_len = rem_len;
 135
 136         eh = mtod(mpf, struct ether_vlan_header *);
 137
 138         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 139                 uint32_t *data = (uint32_t *)eh;
 140
 141                 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
 142                 mpf->m_flags |= M_VLANTAG;
 143
 144                 *(data + 3) = *(data + 2);
 145                 *(data + 2) = *(data + 1);
 146                 *(data + 1) = *data;
 147
 148                 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
 149         }
 150
 151         if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
 152                 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
 153                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 154                 mpf->m_pkthdr.csum_data = 0xFFFF;
 155         } else {
 156                 mpf->m_pkthdr.csum_flags = 0;
 157         }
 158
 159         ifp->if_ipackets++;
 160
 161         mpf->m_pkthdr.flowid = sgc->rss_hash;
 162         mpf->m_flags |= M_FLOWID;
 163
 164         (*ifp->if_input)(ifp, mpf);
 165
 166         if (sdsp->rx_free > ha->std_replenish)
 167                 qla_replenish_normal_rx(ha, sdsp, r_idx);
 168
 169         return;
 170 }
 171
 172 #define QLA_TCP_HDR_SIZE        20
 173 #define QLA_TCP_TS_OPTION_SIZE  12
 174
 175 /*
 176  * Name: qla_lro_intr
 177  * Function: Handles normal ethernet frames received
 178  */
 179 static int
 180 qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx)
 181 {
 182         qla_rx_buf_t *rxb;
 183         struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
 184         struct ifnet *ifp = ha->ifp;
 185         qla_sds_t *sdsp;
 186         struct ether_vlan_header *eh;
 187         uint32_t i, rem_len = 0, pkt_length, iplen;
 188         struct tcphdr *th;
 189         struct ip *ip = NULL;
 190         struct ip6_hdr *ip6 = NULL;
 191         uint16_t etype;
 192         uint32_t r_idx = 0;
 193         qla_rx_ring_t *rx_ring;
 194
 195         if (ha->hw.num_rds_rings > 1)
 196                 r_idx = sds_idx;
 197
 198         ha->hw.rds[r_idx].count++;
 199
 200         rx_ring = &ha->rx_ring[r_idx];
 201
 202         ha->lro_pkt_count++;
 203
 204         sdsp = &ha->hw.sds[sds_idx];
 205
 206         pkt_length = sgc->payload_length + sgc->l4_offset;
 207
 208         if (sgc->flags & Q8_LRO_COMP_TS) {
 209                 pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE;
 210         } else {
 211                 pkt_length += QLA_TCP_HDR_SIZE;
 212         }
 213         ha->lro_bytes += pkt_length;
 214
 215         for (i = 0; i < sgc->num_handles; i++) {
 216                 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
 217
 218                 QL_ASSERT(ha, (rxb != NULL),
 219                         ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
 220                         sds_idx));
 221
 222                 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) {
 223                         /* log the error */
 224                         device_printf(ha->pci_dev,
 225                                 "%s invalid rxb[%d, %d, 0x%04x]\n",
 226                                 __func__, sds_idx, i, sgc->handle[i]);
 227                         qla_rcv_error(ha);
 228                         return (0);
 229                 }
 230
 231                 mp = rxb->m_head;
 232                 if (i == 0)
 233                         mpf = mp;
 234
 235                 QL_ASSERT(ha, (mp != NULL),
 236                         ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
 237                         sds_idx));
 238
 239                 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
 240
 241                 rxb->m_head = NULL;
 242                 rxb->next = sdsp->rxb_free;
 243                 sdsp->rxb_free = rxb;
 244                 sdsp->rx_free++;
 245
 246                 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) {
 247                         /* log the error */
 248                         device_printf(ha->pci_dev,
 249                                 "%s mp  == NULL [%d, %d, 0x%04x]\n",
 250                                 __func__, sds_idx, i, sgc->handle[i]);
 251                         qla_rcv_error(ha);
 252                         return (0);
 253                 }
 254
 255                 if (i == 0) {
 256                         mpl = mpf = mp;
 257                         mp->m_flags |= M_PKTHDR;
 258                         mp->m_pkthdr.len = pkt_length;
 259                         mp->m_pkthdr.rcvif = ifp;
 260                         rem_len = mp->m_pkthdr.len;
 261                 } else {
 262                         mp->m_flags &= ~M_PKTHDR;
 263                         mpl->m_next = mp;
 264                         mpl = mp;
 265                         rem_len = rem_len - mp->m_len;
 266                 }
 267         }
 268
 269         mpl->m_len = rem_len;
 270
 271         th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset);
 272
 273         if (sgc->flags & Q8_LRO_COMP_PUSH_BIT)
 274                 th->th_flags |= TH_PUSH;
 275
 276         m_adj(mpf, sgc->l2_offset);
 277
 278         eh = mtod(mpf, struct ether_vlan_header *);
 279
 280         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 281                 uint32_t *data = (uint32_t *)eh;
 282
 283                 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
 284                 mpf->m_flags |= M_VLANTAG;
 285
 286                 *(data + 3) = *(data + 2);
 287                 *(data + 2) = *(data + 1);
 288                 *(data + 1) = *data;
 289
 290                 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
 291
 292                 etype = ntohs(eh->evl_proto);
 293         } else {
 294                 etype = ntohs(eh->evl_encap_proto);
 295         }
 296
 297         if (etype == ETHERTYPE_IP) {
 298                 ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN);
 299
 300                 iplen = (ip->ip_hl << 2) + (th->th_off << 2) +
 301                                 sgc->payload_length;
 302
 303                 ip->ip_len = htons(iplen);
 304
 305                 ha->ipv4_lro++;
 306
 307                 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV4);
 308
 309         } else if (etype == ETHERTYPE_IPV6) {
 310                 ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN);
 311
 312                 iplen = (th->th_off << 2) + sgc->payload_length;
 313
 314                 ip6->ip6_plen = htons(iplen);
 315
 316                 ha->ipv6_lro++;
 317
 318                 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV6);
 319
 320         } else {
 321                 m_freem(mpf);
 322
 323                 if (sdsp->rx_free > ha->std_replenish)
 324                         qla_replenish_normal_rx(ha, sdsp, r_idx);
 325                 return 0;
 326         }
 327
 328         mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
 329                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 330         mpf->m_pkthdr.csum_data = 0xFFFF;
 331
 332         mpf->m_pkthdr.flowid = sgc->rss_hash;
 333         mpf->m_flags |= M_FLOWID;
 334
 335         ifp->if_ipackets++;
 336
 337         (*ifp->if_input)(ifp, mpf);
 338
 339         if (sdsp->rx_free > ha->std_replenish)
 340                 qla_replenish_normal_rx(ha, sdsp, r_idx);
 341
 342         return (0);
 343 }
 344
 345 static int
 346 qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx,
 347         uint32_t dcount, uint16_t *handle, uint16_t *nhandles)
 348 {
 349         uint32_t i;
 350         uint16_t num_handles;
 351         q80_stat_desc_t *sdesc;
 352         uint32_t opcode;
 353
 354         *nhandles = 0;
 355         dcount--;
 356
 357         for (i = 0; i < dcount; i++) {
 358                 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
 359                 sdesc = (q80_stat_desc_t *)
 360                                 &ha->hw.sds[sds_idx].sds_ring_base[comp_idx];
 361
 362                 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 363
 364                 if (!opcode) {
 365                         device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
 366                                 __func__, (void *)sdesc->data[0],
 367                                 (void *)sdesc->data[1]);
 368                         return -1;
 369                 }
 370
 371                 num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1]));
 372                 if (!num_handles) {
 373                         device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
 374                                 __func__, (void *)sdesc->data[0],
 375                                 (void *)sdesc->data[1]);
 376                         return -1;
 377                 }
 378
 379                 if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID))
 380                         num_handles = -1;
 381
 382                 switch (num_handles) {
 383
 384                 case 1:
 385                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 386                         break;
 387
 388                 case 2:
 389                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 390                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 391                         break;
 392
 393                 case 3:
 394                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 395                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 396                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 397                         break;
 398
 399                 case 4:
 400                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 401                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 402                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 403                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 404                         break;
 405
 406                 case 5:
 407                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 408                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 409                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 410                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 411                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 412                         break;
 413
 414                 case 6:
 415                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 416                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 417                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 418                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 419                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 420                         *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
 421                         break;
 422
 423                 case 7:
 424                         *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
 425                         *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
 426                         *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
 427                         *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
 428                         *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
 429                         *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
 430                         *handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1]));
 431                         break;
 432
 433                 default:
 434                         device_printf(ha->pci_dev,
 435                                 "%s: invalid num handles %p %p\n",
 436                                 __func__, (void *)sdesc->data[0],
 437                                 (void *)sdesc->data[1]);
 438
 439                         QL_ASSERT(ha, (0),\
 440                         ("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n",
 441                         __func__, "invalid num handles", sds_idx, num_handles,
 442                         (void *)sdesc->data[0],(void *)sdesc->data[1]));
 443
 444                         qla_rcv_error(ha);
 445                         return 0;
 446                 }
 447                 *nhandles = *nhandles + num_handles;
 448         }
 449         return 0;
 450 }
 451
 452 /*
 453  * Name: ql_rcv_isr
 454  * Function: Main Interrupt Service Routine
 455  */
 456 uint32_t
 457 ql_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
 458 {
 459         device_t dev;
 460         qla_hw_t *hw;
 461         uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode;
 462         volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL;
 463         uint32_t ret = 0;
 464         qla_sgl_comp_t sgc;
 465         uint16_t nhandles;
 466         uint32_t sds_replenish_threshold = 0;
 467         uint32_t r_idx = 0;
 468         qla_sds_t *sdsp;
 469
 470         dev = ha->pci_dev;
 471         hw = &ha->hw;
 472
 473         hw->sds[sds_idx].rcv_active = 1;
 474         if (ha->flags.stop_rcv) {
 475                 hw->sds[sds_idx].rcv_active = 0;
 476                 return 0;
 477         }
 478
 479         QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx));
 480
 481         /*
 482          * receive interrupts
 483          */
 484         comp_idx = hw->sds[sds_idx].sdsr_next;
 485
 486         while (count-- && !ha->flags.stop_rcv) {
 487
 488                 sdesc = (q80_stat_desc_t *)
 489                                 &hw->sds[sds_idx].sds_ring_base[comp_idx];
 490
 491                 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 492
 493                 if (!opcode)
 494                         break;
 495
 496                 hw->sds[sds_idx].intr_count++;
 497                 switch (opcode) {
 498
 499                 case Q8_STAT_DESC_OPCODE_RCV_PKT:
 500
 501                         desc_count = 1;
 502
 503                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 504
 505                         sgc.rcv.pkt_length =
 506                                 Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0]));
 507                         sgc.rcv.num_handles = 1;
 508                         sgc.rcv.handle[0] =
 509                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 510                         sgc.rcv.chksum_status =
 511                                 Q8_STAT_DESC_STATUS((sdesc->data[1]));
 512
 513                         sgc.rcv.rss_hash =
 514                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 515
 516                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 517                                 sgc.rcv.vlan_tag =
 518                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 519                         }
 520                         qla_rx_intr(ha, &sgc.rcv, sds_idx);
 521                         break;
 522
 523                 case Q8_STAT_DESC_OPCODE_SGL_RCV:
 524
 525                         desc_count =
 526                                 Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1]));
 527
 528                         if (desc_count > 1) {
 529                                 c_idx = (comp_idx + desc_count -1) &
 530                                                 (NUM_STATUS_DESCRIPTORS-1);
 531                                 sdesc0 = (q80_stat_desc_t *)
 532                                         &hw->sds[sds_idx].sds_ring_base[c_idx];
 533
 534                                 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
 535                                                 Q8_STAT_DESC_OPCODE_CONT) {
 536                                         desc_count = 0;
 537                                         break;
 538                                 }
 539                         }
 540
 541                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 542
 543                         sgc.rcv.pkt_length =
 544                                 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\
 545                                         (sdesc->data[0]));
 546                         sgc.rcv.chksum_status =
 547                                 Q8_STAT_DESC_STATUS((sdesc->data[1]));
 548
 549                         sgc.rcv.rss_hash =
 550                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 551
 552                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 553                                 sgc.rcv.vlan_tag =
 554                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 555                         }
 556
 557                         QL_ASSERT(ha, (desc_count <= 2) ,\
 558                                 ("%s: [sds_idx, data0, data1]="\
 559                                 "%d, %p, %p]\n", __func__, sds_idx,\
 560                                 (void *)sdesc->data[0],\
 561                                 (void *)sdesc->data[1]));
 562
 563                         sgc.rcv.num_handles = 1;
 564                         sgc.rcv.handle[0] =
 565                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 566
 567                         if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count,
 568                                 &sgc.rcv.handle[1], &nhandles)) {
 569                                 device_printf(dev,
 570                                         "%s: [sds_idx, dcount, data0, data1]="
 571                                          "[%d, %d, 0x%llx, 0x%llx]\n",
 572                                         __func__, sds_idx, desc_count,
 573                                         (long long unsigned int)sdesc->data[0],
 574                                         (long long unsigned int)sdesc->data[1]);
 575                                 desc_count = 0;
 576                                 break;
 577                         }
 578
 579                         sgc.rcv.num_handles += nhandles;
 580
 581                         qla_rx_intr(ha, &sgc.rcv, sds_idx);
 582
 583                         break;
 584
 585                 case Q8_STAT_DESC_OPCODE_SGL_LRO:
 586
 587                         desc_count =
 588                                 Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1]));
 589
 590                         if (desc_count > 1) {
 591                                 c_idx = (comp_idx + desc_count -1) &
 592                                                 (NUM_STATUS_DESCRIPTORS-1);
 593                                 sdesc0 = (q80_stat_desc_t *)
 594                                         &hw->sds[sds_idx].sds_ring_base[c_idx];
 595
 596                                 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
 597                                                 Q8_STAT_DESC_OPCODE_CONT) {
 598                                         desc_count = 0;
 599                                         break;
 600                                 }
 601                         }
 602                         bzero(&sgc, sizeof(qla_sgl_comp_t));
 603
 604                         sgc.lro.payload_length =
 605                         Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0]));
 606
 607                         sgc.lro.rss_hash =
 608                                 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
 609
 610                         sgc.lro.num_handles = 1;
 611                         sgc.lro.handle[0] =
 612                                 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
 613
 614                         if (Q8_SGL_LRO_STAT_TS((sdesc->data[1])))
 615                                 sgc.lro.flags |= Q8_LRO_COMP_TS;
 616
 617                         if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1])))
 618                                 sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT;
 619
 620                         sgc.lro.l2_offset =
 621                                 Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1]));
 622                         sgc.lro.l4_offset =
 623                                 Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1]));
 624
 625                         if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
 626                                 sgc.lro.vlan_tag =
 627                                         Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
 628                         }
 629
 630                         QL_ASSERT(ha, (desc_count <= 7) ,\
 631                                 ("%s: [sds_idx, data0, data1]="\
 632                                  "[%d, 0x%llx, 0x%llx]\n",\
 633                                 __func__, sds_idx,\
 634                                 (long long unsigned int)sdesc->data[0],\
 635                                 (long long unsigned int)sdesc->data[1]));
 636
 637                         if (qla_rcv_cont_sds(ha, sds_idx, comp_idx,
 638                                 desc_count, &sgc.lro.handle[1], &nhandles)) {
 639                                 device_printf(dev,
 640                                 "%s: [sds_idx, data0, data1]="\
 641                                  "[%d, 0x%llx, 0x%llx]\n",\
 642                                 __func__, sds_idx,\
 643                                 (long long unsigned int)sdesc->data[0],\
 644                                 (long long unsigned int)sdesc->data[1]);
 645
 646                                 desc_count = 0;
 647                                 break;
 648                         }
 649
 650                         sgc.lro.num_handles += nhandles;
 651
 652                         if (qla_lro_intr(ha, &sgc.lro, sds_idx)) {
 653                                 device_printf(dev,
 654                                 "%s: [sds_idx, data0, data1]="\
 655                                  "[%d, 0x%llx, 0x%llx]\n",\
 656                                 __func__, sds_idx,\
 657                                 (long long unsigned int)sdesc->data[0],\
 658                                 (long long unsigned int)sdesc->data[1]);
 659                                 device_printf(dev,
 660                                 "%s: [comp_idx, c_idx, dcount, nhndls]="\
 661                                  "[%d, %d, %d, %d]\n",\
 662                                 __func__, comp_idx, c_idx, desc_count,
 663                                 sgc.lro.num_handles);
 664                                 if (desc_count > 1) {
 665                                 device_printf(dev,
 666                                 "%s: [sds_idx, data0, data1]="\
 667                                  "[%d, 0x%llx, 0x%llx]\n",\
 668                                 __func__, sds_idx,\
 669                                 (long long unsigned int)sdesc0->data[0],\
 670                                 (long long unsigned int)sdesc0->data[1]);
 671                                 }
 672                         }
 673
 674                         break;
 675
 676                 default:
 677                         device_printf(dev, "%s: default 0x%llx!\n", __func__,
 678                                         (long long unsigned int)sdesc->data[0]);
 679                         break;
 680                 }
 681
 682                 if (desc_count == 0)
 683                         break;
 684
 685                 sds_replenish_threshold += desc_count;
 686
 687
 688                 while (desc_count--) {
 689                         sdesc->data[0] = 0ULL;
 690                         sdesc->data[1] = 0ULL;
 691                         comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
 692                         sdesc = (q80_stat_desc_t *)
 693                                 &hw->sds[sds_idx].sds_ring_base[comp_idx];
 694                 }
 695
 696                 if (sds_replenish_threshold > ha->hw.sds_cidx_thres) {
 697                         sds_replenish_threshold = 0;
 698                         if (hw->sds[sds_idx].sdsr_next != comp_idx) {
 699                                 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\
 700                                         comp_idx);
 701                         }
 702                         hw->sds[sds_idx].sdsr_next = comp_idx;
 703                 }
 704         }
 705
 706         if (ha->flags.stop_rcv)
 707                 goto ql_rcv_isr_exit;
 708
 709         if (hw->sds[sds_idx].sdsr_next != comp_idx) {
 710                 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
 711                 hw->sds[sds_idx].sdsr_next = comp_idx;
 712         } else {
 713                 hw->sds[sds_idx].spurious_intr_count++;
 714
 715                 if (ha->hw.num_rds_rings > 1)
 716                         r_idx = sds_idx;
 717
 718                 sdsp = &ha->hw.sds[sds_idx];
 719
 720                 if (sdsp->rx_free > ha->std_replenish)
 721                         qla_replenish_normal_rx(ha, sdsp, r_idx);
 722         }
 723
 724         sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
 725         opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
 726
 727         if (opcode)
 728                 ret = -1;
 729
 730 ql_rcv_isr_exit:
 731         hw->sds[sds_idx].rcv_active = 0;
 732
 733         return (ret);
 734 }
 735
 736 void
 737 ql_mbx_isr(void *arg)
 738 {
 739         qla_host_t *ha;
 740         uint32_t data;
 741         uint32_t prev_link_state;
 742
 743         ha = arg;
 744
 745         if (ha == NULL) {
 746                 device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__);
 747                 return;
 748         }
 749
 750         data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
 751         if ((data & 0x3) != 0x1) {
 752                 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
 753                 return;
 754         }
 755
 756         data = READ_REG32(ha, Q8_FW_MBOX0);
 757
 758         if ((data & 0xF000) != 0x8000)
 759                 return;
 760
 761         data = data & 0xFFFF;
 762
 763         switch (data) {
 764
 765         case 0x8001:  /* It's an AEN */
 766
 767                 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 768
 769                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 770                 ha->hw.cable_length = data & 0xFFFF;
 771
 772                 data = data >> 16;
 773                 ha->hw.link_speed = data & 0xFFF;
 774
 775                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 776
 777                 prev_link_state =  ha->hw.link_up;
 778                 ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1);
 779
 780                 if (prev_link_state !=  ha->hw.link_up) {
 781                         if (ha->hw.link_up)
 782                                 if_link_state_change(ha->ifp, LINK_STATE_UP);
 783                         else
 784                                 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
 785                 }
 786
 787
 788                 ha->hw.module_type = ((data >> 8) & 0xFF);
 789                 ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1);
 790                 ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1);
 791
 792                 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 793                 ha->hw.flags.loopback_mode = data & 0x03;
 794
 795                 ha->hw.link_faults = (data >> 3) & 0xFF;
 796
 797                 break;
 798
 799         case 0x8100:
 800                 ha->hw.imd_compl=1;
 801                 break;
 802
 803         case 0x8101:
 804                 ha->async_event = 1;
 805                 ha->hw.aen_mb0 = 0x8101;
 806                 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 807                 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 808                 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 809                 ha->hw.aen_mb4 = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 810                 break;
 811
 812         case 0x8110:
 813                 /* for now just dump the registers */
 814                 {
 815                         uint32_t ombx[5];
 816
 817                         ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 818                         ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 819                         ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 820                         ombx[3] = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
 821                         ombx[4] = READ_REG32(ha, (Q8_FW_MBOX0 + 20));
 822
 823                         device_printf(ha->pci_dev, "%s: "
 824                                 "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 825                                 __func__, data, ombx[0], ombx[1], ombx[2],
 826                                 ombx[3], ombx[4]);
 827                 }
 828
 829                 break;
 830
 831         case 0x8130:
 832                 /* sfp insertion aen */
 833                 device_printf(ha->pci_dev, "%s: sfp inserted [0x%08x]\n",
 834                         __func__, READ_REG32(ha, (Q8_FW_MBOX0 + 4)));
 835                 break;
 836
 837         case 0x8131:
 838                 /* sfp removal aen */
 839                 device_printf(ha->pci_dev, "%s: sfp removed]\n", __func__);
 840                 break;
 841
 842         case 0x8140:
 843                 {
 844                         uint32_t ombx[3];
 845
 846                         ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
 847                         ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
 848                         ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
 849
 850                         device_printf(ha->pci_dev, "%s: "
 851                                 "0x%08x 0x%08x 0x%08x 0x%08x \n",
 852                                 __func__, data, ombx[0], ombx[1], ombx[2]);
 853                 }
 854                 break;
 855
 856         default:
 857                 device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data);
 858                 break;
 859         }
 860         WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
 861         WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
 862         return;
 863 }
 864
 865
 866 static void
 867 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx)
 868 {
 869         qla_rx_buf_t *rxb;
 870         int count = sdsp->rx_free;
 871         uint32_t rx_next;
 872         qla_rdesc_t *rdesc;
 873
 874         /* we can play with this value via a sysctl */
 875         uint32_t replenish_thresh = ha->hw.rds_pidx_thres;
 876
 877         rdesc = &ha->hw.rds[r_idx];
 878
 879         rx_next = rdesc->rx_next;
 880
 881         while (count--) {
 882                 rxb = sdsp->rxb_free;
 883
 884                 if (rxb == NULL)
 885                         break;
 886
 887                 sdsp->rxb_free = rxb->next;
 888                 sdsp->rx_free--;
 889
 890                 if (ql_get_mbuf(ha, rxb, NULL) == 0) {
 891                         qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in,
 892                                 rxb->handle,
 893                                 rxb->paddr, (rxb->m_head)->m_pkthdr.len);
 894                         rdesc->rx_in++;
 895                         if (rdesc->rx_in == NUM_RX_DESCRIPTORS)
 896                                 rdesc->rx_in = 0;
 897                         rdesc->rx_next++;
 898                         if (rdesc->rx_next == NUM_RX_DESCRIPTORS)
 899                                 rdesc->rx_next = 0;
 900                 } else {
 901                         device_printf(ha->pci_dev,
 902                                 "%s: qla_get_mbuf [(%d),(%d),(%d)] failed\n",
 903                                 __func__, r_idx, rdesc->rx_in, rxb->handle);
 904
 905                         rxb->m_head = NULL;
 906                         rxb->next = sdsp->rxb_free;
 907                         sdsp->rxb_free = rxb;
 908                         sdsp->rx_free++;
 909
 910                         break;
 911                 }
 912                 if (replenish_thresh-- == 0) {
 913                         QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
 914                                 rdesc->rx_next);
 915                         rx_next = rdesc->rx_next;
 916                         replenish_thresh = ha->hw.rds_pidx_thres;
 917                 }
 918         }
 919
 920         if (rx_next != rdesc->rx_next) {
 921                 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
 922                         rdesc->rx_next);
 923         }
 924 }
 925
 926 void
 927 ql_isr(void *arg)
 928 {
 929         qla_ivec_t *ivec = arg;
 930         qla_host_t *ha ;
 931         int idx;
 932         qla_hw_t *hw;
 933         struct ifnet *ifp;
 934         qla_tx_fp_t *fp;
 935
 936         ha = ivec->ha;
 937         hw = &ha->hw;
 938         ifp = ha->ifp;
 939
 940         if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings)
 941                 return;
 942
 943
 944         fp = &ha->tx_fp[idx];
 945
 946         if (fp->fp_taskqueue != NULL)
 947                 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);
 948
 949         return;
 950 }
 951