2 * Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
3 * Copyright (c) 1997, 1998, 1999
4 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
39 * available from http://www.sis.com.tw.
41 * This driver also supports the NatSemi DP83815. Datasheets are
42 * available from http://www.national.com.
44 * Written by Bill Paul <wpaul@ee.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
49 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
50 * simple TX and RX descriptors of 3 longwords in size. The receiver
51 * has a single perfect filter entry for the station address and a
52 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
53 * transceiver while the 7016 requires an external transceiver chip.
54 * Both chips offer the standard bit-bang MII interface as well as
55 * an enchanced PHY interface which simplifies accessing MII registers.
57 * The only downside to this chipset is that RX descriptors must be
61 #ifdef HAVE_KERNEL_OPTION_HEADERS
62 #include "opt_device_polling.h"
65 #include <sys/param.h>
66 #include <sys/systm.h>
68 #include <sys/endian.h>
69 #include <sys/kernel.h>
71 #include <sys/malloc.h>
73 #include <sys/module.h>
74 #include <sys/socket.h>
75 #include <sys/sockio.h>
76 #include <sys/sysctl.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_dl.h>
82 #include <net/if_media.h>
83 #include <net/if_types.h>
84 #include <net/if_vlan_var.h>
88 #include <machine/bus.h>
89 #include <machine/resource.h>
92 #include <dev/mii/mii.h>
93 #include <dev/mii/miivar.h>
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
98 #define SIS_USEIOSPACE
100 #include <dev/sis/if_sisreg.h>
102 MODULE_DEPEND(sis, pci, 1, 1, 1);
103 MODULE_DEPEND(sis, ether, 1, 1, 1);
104 MODULE_DEPEND(sis, miibus, 1, 1, 1);
106 /* "device miibus" required. See GENERIC if you get errors here. */
107 #include "miibus_if.h"
109 #define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
110 #define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
111 #define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
114 * register space access macros
116 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
118 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
120 #define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
123 * Various supported device vendors/types and their names.
125 static struct sis_type sis_devs[] = {
126 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
127 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
128 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
132 static int sis_detach(device_t);
133 static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
134 static int sis_dma_alloc(struct sis_softc *);
135 static void sis_dma_free(struct sis_softc *);
136 static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
137 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
138 static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
139 #ifndef __NO_STRICT_ALIGNMENT
140 static __inline void sis_fixup_rx(struct mbuf *);
142 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
143 static int sis_ifmedia_upd(struct ifnet *);
144 static void sis_init(void *);
145 static void sis_initl(struct sis_softc *);
146 static void sis_intr(void *);
147 static int sis_ioctl(struct ifnet *, u_long, caddr_t);
148 static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
149 static int sis_resume(device_t);
150 static int sis_rxeof(struct sis_softc *);
151 static void sis_rxfilter(struct sis_softc *);
152 static void sis_rxfilter_ns(struct sis_softc *);
153 static void sis_rxfilter_sis(struct sis_softc *);
154 static void sis_start(struct ifnet *);
155 static void sis_startl(struct ifnet *);
156 static void sis_stop(struct sis_softc *);
157 static int sis_suspend(device_t);
158 static void sis_add_sysctls(struct sis_softc *);
159 static void sis_watchdog(struct sis_softc *);
160 static void sis_wol(struct sis_softc *);
163 static struct resource_spec sis_res_spec[] = {
164 #ifdef SIS_USEIOSPACE
165 { SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
167 { SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
169 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
173 #define SIS_SETBIT(sc, reg, x) \
174 CSR_WRITE_4(sc, reg, \
175 CSR_READ_4(sc, reg) | (x))
177 #define SIS_CLRBIT(sc, reg, x) \
178 CSR_WRITE_4(sc, reg, \
179 CSR_READ_4(sc, reg) & ~(x))
182 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
185 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
188 * Routine to reverse the bits in a word. Stolen almost
189 * verbatim from /usr/games/fortune.
192 sis_reverse(uint16_t n)
194 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
195 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
196 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
197 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
203 sis_delay(struct sis_softc *sc)
207 for (idx = (300 / 33) + 1; idx > 0; idx--)
208 CSR_READ_4(sc, SIS_CSR);
212 sis_eeprom_idle(struct sis_softc *sc)
216 SIO_SET(SIS_EECTL_CSEL);
218 SIO_SET(SIS_EECTL_CLK);
221 for (i = 0; i < 25; i++) {
222 SIO_CLR(SIS_EECTL_CLK);
224 SIO_SET(SIS_EECTL_CLK);
228 SIO_CLR(SIS_EECTL_CLK);
230 SIO_CLR(SIS_EECTL_CSEL);
232 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
236 * Send a read command and address to the EEPROM, check for ACK.
239 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
243 d = addr | SIS_EECMD_READ;
246 * Feed in each bit and stobe the clock.
248 for (i = 0x400; i; i >>= 1) {
250 SIO_SET(SIS_EECTL_DIN);
252 SIO_CLR(SIS_EECTL_DIN);
255 SIO_SET(SIS_EECTL_CLK);
257 SIO_CLR(SIS_EECTL_CLK);
263 * Read a word of data stored in the EEPROM at address 'addr.'
266 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
271 /* Force EEPROM to idle state. */
274 /* Enter EEPROM access mode. */
276 SIO_CLR(SIS_EECTL_CLK);
278 SIO_SET(SIS_EECTL_CSEL);
282 * Send address of word we want to read.
284 sis_eeprom_putbyte(sc, addr);
287 * Start reading bits from EEPROM.
289 for (i = 0x8000; i; i >>= 1) {
290 SIO_SET(SIS_EECTL_CLK);
292 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
295 SIO_CLR(SIS_EECTL_CLK);
299 /* Turn off EEPROM access mode. */
306 * Read a sequence of words from the EEPROM.
309 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
312 uint16_t word = 0, *ptr;
314 for (i = 0; i < cnt; i++) {
315 sis_eeprom_getword(sc, off + i, &word);
316 ptr = (uint16_t *)(dest + (i * 2));
324 #if defined(__i386__) || defined(__amd64__)
326 sis_find_bridge(device_t dev)
328 devclass_t pci_devclass;
329 device_t *pci_devices;
331 device_t *pci_children;
332 int pci_childcount = 0;
333 device_t *busp, *childp;
334 device_t child = NULL;
337 if ((pci_devclass = devclass_find("pci")) == NULL)
340 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
342 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
343 if (device_get_children(*busp, &pci_children, &pci_childcount))
345 for (j = 0, childp = pci_children;
346 j < pci_childcount; j++, childp++) {
347 if (pci_get_vendor(*childp) == SIS_VENDORID &&
348 pci_get_device(*childp) == 0x0008) {
350 free(pci_children, M_TEMP);
354 free(pci_children, M_TEMP);
358 free(pci_devices, M_TEMP);
363 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
368 bus_space_tag_t btag;
370 bridge = sis_find_bridge(dev);
373 reg = pci_read_config(bridge, 0x48, 1);
374 pci_write_config(bridge, 0x48, reg|0x40, 1);
377 #if defined(__amd64__) || defined(__i386__)
378 btag = X86_BUS_SPACE_IO;
381 for (i = 0; i < cnt; i++) {
382 bus_space_write_1(btag, 0x0, 0x70, i + off);
383 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
386 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
390 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
392 uint32_t filtsave, csrsave;
394 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
395 csrsave = CSR_READ_4(sc, SIS_CSR);
397 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
398 CSR_WRITE_4(sc, SIS_CSR, 0);
400 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
402 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
403 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
404 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
405 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
406 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
407 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
409 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
410 CSR_WRITE_4(sc, SIS_CSR, csrsave);
415 * Sync the PHYs by setting data bit and strobing the clock 32 times.
418 sis_mii_sync(struct sis_softc *sc)
422 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
424 for (i = 0; i < 32; i++) {
425 SIO_SET(SIS_MII_CLK);
427 SIO_CLR(SIS_MII_CLK);
433 * Clock a series of bits through the MII.
436 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
440 SIO_CLR(SIS_MII_CLK);
442 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
444 SIO_SET(SIS_MII_DATA);
446 SIO_CLR(SIS_MII_DATA);
449 SIO_CLR(SIS_MII_CLK);
451 SIO_SET(SIS_MII_CLK);
456 * Read an PHY register through the MII.
459 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
464 * Set up frame for RX.
466 frame->mii_stdelim = SIS_MII_STARTDELIM;
467 frame->mii_opcode = SIS_MII_READOP;
468 frame->mii_turnaround = 0;
474 SIO_SET(SIS_MII_DIR);
479 * Send command/address info.
481 sis_mii_send(sc, frame->mii_stdelim, 2);
482 sis_mii_send(sc, frame->mii_opcode, 2);
483 sis_mii_send(sc, frame->mii_phyaddr, 5);
484 sis_mii_send(sc, frame->mii_regaddr, 5);
487 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
489 SIO_SET(SIS_MII_CLK);
493 SIO_CLR(SIS_MII_DIR);
496 SIO_CLR(SIS_MII_CLK);
498 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
499 SIO_SET(SIS_MII_CLK);
503 * Now try reading data bits. If the ack failed, we still
504 * need to clock through 16 cycles to keep the PHY(s) in sync.
507 for (i = 0; i < 16; i++) {
508 SIO_CLR(SIS_MII_CLK);
510 SIO_SET(SIS_MII_CLK);
516 for (i = 0x8000; i; i >>= 1) {
517 SIO_CLR(SIS_MII_CLK);
520 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
521 frame->mii_data |= i;
524 SIO_SET(SIS_MII_CLK);
530 SIO_CLR(SIS_MII_CLK);
532 SIO_SET(SIS_MII_CLK);
541 * Write to a PHY register through the MII.
544 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
548 * Set up frame for TX.
551 frame->mii_stdelim = SIS_MII_STARTDELIM;
552 frame->mii_opcode = SIS_MII_WRITEOP;
553 frame->mii_turnaround = SIS_MII_TURNAROUND;
556 * Turn on data output.
558 SIO_SET(SIS_MII_DIR);
562 sis_mii_send(sc, frame->mii_stdelim, 2);
563 sis_mii_send(sc, frame->mii_opcode, 2);
564 sis_mii_send(sc, frame->mii_phyaddr, 5);
565 sis_mii_send(sc, frame->mii_regaddr, 5);
566 sis_mii_send(sc, frame->mii_turnaround, 2);
567 sis_mii_send(sc, frame->mii_data, 16);
570 SIO_SET(SIS_MII_CLK);
572 SIO_CLR(SIS_MII_CLK);
578 SIO_CLR(SIS_MII_DIR);
584 sis_miibus_readreg(device_t dev, int phy, int reg)
586 struct sis_softc *sc;
587 struct sis_mii_frame frame;
589 sc = device_get_softc(dev);
591 if (sc->sis_type == SIS_TYPE_83815) {
595 * The NatSemi chip can take a while after
596 * a reset to come ready, during which the BMSR
597 * returns a value of 0. This is *never* supposed
598 * to happen: some of the BMSR bits are meant to
599 * be hardwired in the on position, and this can
600 * confuse the miibus code a bit during the probe
601 * and attach phase. So we make an effort to check
602 * for this condition and wait for it to clear.
604 if (!CSR_READ_4(sc, NS_BMSR))
606 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
610 * Chipsets < SIS_635 seem not to be able to read/write
611 * through mdio. Use the enhanced PHY access register
614 if (sc->sis_type == SIS_TYPE_900 &&
615 sc->sis_rev < SIS_REV_635) {
621 CSR_WRITE_4(sc, SIS_PHYCTL,
622 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
623 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
625 for (i = 0; i < SIS_TIMEOUT; i++) {
626 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
630 if (i == SIS_TIMEOUT) {
631 device_printf(sc->sis_dev, "PHY failed to come ready\n");
635 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
642 bzero((char *)&frame, sizeof(frame));
644 frame.mii_phyaddr = phy;
645 frame.mii_regaddr = reg;
646 sis_mii_readreg(sc, &frame);
648 return (frame.mii_data);
653 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
655 struct sis_softc *sc;
656 struct sis_mii_frame frame;
658 sc = device_get_softc(dev);
660 if (sc->sis_type == SIS_TYPE_83815) {
663 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
668 * Chipsets < SIS_635 seem not to be able to read/write
669 * through mdio. Use the enhanced PHY access register
672 if (sc->sis_type == SIS_TYPE_900 &&
673 sc->sis_rev < SIS_REV_635) {
679 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
680 (reg << 6) | SIS_PHYOP_WRITE);
681 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
683 for (i = 0; i < SIS_TIMEOUT; i++) {
684 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
688 if (i == SIS_TIMEOUT)
689 device_printf(sc->sis_dev, "PHY failed to come ready\n");
691 bzero((char *)&frame, sizeof(frame));
693 frame.mii_phyaddr = phy;
694 frame.mii_regaddr = reg;
695 frame.mii_data = data;
696 sis_mii_writereg(sc, &frame);
702 sis_miibus_statchg(device_t dev)
704 struct sis_softc *sc;
705 struct mii_data *mii;
709 sc = device_get_softc(dev);
712 mii = device_get_softc(sc->sis_miibus);
714 if (mii == NULL || ifp == NULL ||
715 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
718 sc->sis_flags &= ~SIS_FLAG_LINK;
719 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
720 (IFM_ACTIVE | IFM_AVALID)) {
721 switch (IFM_SUBTYPE(mii->mii_media_active)) {
723 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
724 sc->sis_flags |= SIS_FLAG_LINK;
727 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
728 sc->sis_flags |= SIS_FLAG_LINK;
735 if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
737 * Stopping MACs seem to reset SIS_TX_LISTPTR and
738 * SIS_RX_LISTPTR which in turn requires resetting
739 * TX/RX buffers. So just don't do anything for
745 /* Set full/half duplex mode. */
746 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
747 SIS_SETBIT(sc, SIS_TX_CFG,
748 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
749 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
751 SIS_CLRBIT(sc, SIS_TX_CFG,
752 (SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
753 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
756 if (sc->sis_type == SIS_TYPE_83816) {
758 * MPII03.D: Half Duplex Excessive Collisions.
759 * Also page 49 in 83816 manual
761 SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
764 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
765 IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
767 * Short Cable Receive Errors (MP21.E)
769 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
770 reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
771 CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
773 reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
774 if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
775 device_printf(sc->sis_dev,
776 "Applying short cable fix (reg=%x)\n", reg);
777 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
778 SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
780 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
782 /* Enable TX/RX MACs. */
783 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
784 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
788 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
792 /* Compute CRC for the address value. */
793 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
796 * return the filter bit position
798 * The NatSemi chip has a 512-bit filter, which is
799 * different than the SiS, so we special-case it.
801 if (sc->sis_type == SIS_TYPE_83815)
803 else if (sc->sis_rev >= SIS_REV_635 ||
804 sc->sis_rev == SIS_REV_900B)
811 sis_rxfilter(struct sis_softc *sc)
816 if (sc->sis_type == SIS_TYPE_83815)
819 sis_rxfilter_sis(sc);
823 sis_rxfilter_ns(struct sis_softc *sc)
826 struct ifmultiaddr *ifma;
827 uint32_t h, i, filter;
831 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
832 if (filter & SIS_RXFILTCTL_ENABLE) {
834 * Filter should be disabled to program other bits.
836 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
837 CSR_READ_4(sc, SIS_RXFILT_CTL);
839 filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
840 NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
841 SIS_RXFILTCTL_ALLMULTI);
843 if (ifp->if_flags & IFF_BROADCAST)
844 filter |= SIS_RXFILTCTL_BROAD;
846 * For the NatSemi chip, we have to explicitly enable the
847 * reception of ARP frames, as well as turn on the 'perfect
848 * match' filter where we store the station address, otherwise
849 * we won't receive unicasts meant for this host.
851 filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
853 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
854 filter |= SIS_RXFILTCTL_ALLMULTI;
855 if (ifp->if_flags & IFF_PROMISC)
856 filter |= SIS_RXFILTCTL_ALLPHYS;
859 * We have to explicitly enable the multicast hash table
860 * on the NatSemi chip if we want to use it, which we do.
862 filter |= NS_RXFILTCTL_MCHASH;
864 /* first, zot all the existing hash bits */
865 for (i = 0; i < 32; i++) {
866 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
868 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
872 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
873 if (ifma->ifma_addr->sa_family != AF_LINK)
876 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
879 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
883 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
885 if_maddr_runlock(ifp);
888 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
889 CSR_READ_4(sc, SIS_RXFILT_CTL);
893 sis_rxfilter_sis(struct sis_softc *sc)
896 struct ifmultiaddr *ifma;
897 uint32_t filter, h, i, n;
902 /* hash table size */
903 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
908 filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
909 if (filter & SIS_RXFILTCTL_ENABLE) {
910 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILT_CTL);
911 CSR_READ_4(sc, SIS_RXFILT_CTL);
913 filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
914 SIS_RXFILTCTL_ALLMULTI);
915 if (ifp->if_flags & IFF_BROADCAST)
916 filter |= SIS_RXFILTCTL_BROAD;
918 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
919 filter |= SIS_RXFILTCTL_ALLMULTI;
920 if (ifp->if_flags & IFF_PROMISC)
921 filter |= SIS_RXFILTCTL_ALLPHYS;
922 for (i = 0; i < n; i++)
925 for (i = 0; i < n; i++)
929 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
930 if (ifma->ifma_addr->sa_family != AF_LINK)
933 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
934 hashes[h >> 4] |= 1 << (h & 0xf);
937 if_maddr_runlock(ifp);
939 filter |= SIS_RXFILTCTL_ALLMULTI;
940 for (i = 0; i < n; i++)
945 for (i = 0; i < n; i++) {
946 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
947 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
950 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter);
951 CSR_READ_4(sc, SIS_RXFILT_CTL);
955 sis_reset(struct sis_softc *sc)
959 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
961 for (i = 0; i < SIS_TIMEOUT; i++) {
962 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
966 if (i == SIS_TIMEOUT)
967 device_printf(sc->sis_dev, "reset never completed\n");
969 /* Wait a little while for the chip to get its brains in order. */
973 * If this is a NetSemi chip, make sure to clear
976 if (sc->sis_type == SIS_TYPE_83815) {
977 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
978 CSR_WRITE_4(sc, NS_CLKRUN, 0);
980 /* Disable WOL functions. */
981 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
986 * Probe for an SiS chip. Check the PCI vendor and device
987 * IDs against our list and return a device name if we find a match.
990 sis_probe(device_t dev)
996 while (t->sis_name != NULL) {
997 if ((pci_get_vendor(dev) == t->sis_vid) &&
998 (pci_get_device(dev) == t->sis_did)) {
999 device_set_desc(dev, t->sis_name);
1000 return (BUS_PROBE_DEFAULT);
1009 * Attach the interface. Allocate softc structures, do ifmedia
1010 * setup and ethernet/BPF attach.
1013 sis_attach(device_t dev)
1015 u_char eaddr[ETHER_ADDR_LEN];
1016 struct sis_softc *sc;
1018 int error = 0, pmc, waittime = 0;
1021 sc = device_get_softc(dev);
1025 mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1027 callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
1029 if (pci_get_device(dev) == SIS_DEVICEID_900)
1030 sc->sis_type = SIS_TYPE_900;
1031 if (pci_get_device(dev) == SIS_DEVICEID_7016)
1032 sc->sis_type = SIS_TYPE_7016;
1033 if (pci_get_vendor(dev) == NS_VENDORID)
1034 sc->sis_type = SIS_TYPE_83815;
1036 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
1038 * Map control/status registers.
1040 pci_enable_busmaster(dev);
1042 error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
1044 device_printf(dev, "couldn't allocate resources\n");
1048 /* Reset the adapter. */
1051 if (sc->sis_type == SIS_TYPE_900 &&
1052 (sc->sis_rev == SIS_REV_635 ||
1053 sc->sis_rev == SIS_REV_900B)) {
1054 SIO_SET(SIS_CFG_RND_CNT);
1055 SIO_SET(SIS_CFG_PERR_DETECT);
1059 * Get station address from the EEPROM.
1061 switch (pci_get_vendor(dev)) {
1063 sc->sis_srr = CSR_READ_4(sc, NS_SRR);
1065 /* We can't update the device description, so spew */
1066 if (sc->sis_srr == NS_SRR_15C)
1067 device_printf(dev, "Silicon Revision: DP83815C\n");
1068 else if (sc->sis_srr == NS_SRR_15D)
1069 device_printf(dev, "Silicon Revision: DP83815D\n");
1070 else if (sc->sis_srr == NS_SRR_16A)
1071 device_printf(dev, "Silicon Revision: DP83816A\n");
1073 device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
1076 * Reading the MAC address out of the EEPROM on
1077 * the NatSemi chip takes a bit more work than
1078 * you'd expect. The address spans 4 16-bit words,
1079 * with the first word containing only a single bit.
1080 * You have to shift everything over one bit to
1081 * get it aligned properly. Also, the bits are
1082 * stored backwards (the LSB is really the MSB,
1083 * and so on) so you have to reverse them in order
1084 * to get the MAC address into the form we want.
1085 * Why? Who the hell knows.
1090 sis_read_eeprom(sc, (caddr_t)&tmp,
1091 NS_EE_NODEADDR, 4, 0);
1093 /* Shift everything over one bit. */
1094 tmp[3] = tmp[3] >> 1;
1095 tmp[3] |= tmp[2] << 15;
1096 tmp[2] = tmp[2] >> 1;
1097 tmp[2] |= tmp[1] << 15;
1098 tmp[1] = tmp[1] >> 1;
1099 tmp[1] |= tmp[0] << 15;
1101 /* Now reverse all the bits. */
1102 tmp[3] = sis_reverse(tmp[3]);
1103 tmp[2] = sis_reverse(tmp[2]);
1104 tmp[1] = sis_reverse(tmp[1]);
1106 eaddr[0] = (tmp[1] >> 0) & 0xFF;
1107 eaddr[1] = (tmp[1] >> 8) & 0xFF;
1108 eaddr[2] = (tmp[2] >> 0) & 0xFF;
1109 eaddr[3] = (tmp[2] >> 8) & 0xFF;
1110 eaddr[4] = (tmp[3] >> 0) & 0xFF;
1111 eaddr[5] = (tmp[3] >> 8) & 0xFF;
1116 #if defined(__i386__) || defined(__amd64__)
1118 * If this is a SiS 630E chipset with an embedded
1119 * SiS 900 controller, we have to read the MAC address
1120 * from the APC CMOS RAM. Our method for doing this
1121 * is very ugly since we have to reach out and grab
1122 * ahold of hardware for which we cannot properly
1123 * allocate resources. This code is only compiled on
1124 * the i386 architecture since the SiS 630E chipset
1125 * is for x86 motherboards only. Note that there are
1126 * a lot of magic numbers in this hack. These are
1127 * taken from SiS's Linux driver. I'd like to replace
1128 * them with proper symbolic definitions, but that
1129 * requires some datasheets that I don't have access
1132 if (sc->sis_rev == SIS_REV_630S ||
1133 sc->sis_rev == SIS_REV_630E ||
1134 sc->sis_rev == SIS_REV_630EA1)
1135 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1137 else if (sc->sis_rev == SIS_REV_635 ||
1138 sc->sis_rev == SIS_REV_630ET)
1139 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1140 else if (sc->sis_rev == SIS_REV_96x) {
1141 /* Allow to read EEPROM from LAN. It is shared
1142 * between a 1394 controller and the NIC and each
1143 * time we access it, we need to set SIS_EECMD_REQ.
1145 SIO_SET(SIS_EECMD_REQ);
1146 for (waittime = 0; waittime < SIS_TIMEOUT;
1148 /* Force EEPROM to idle state. */
1149 sis_eeprom_idle(sc);
1150 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1151 sis_read_eeprom(sc, (caddr_t)&eaddr,
1152 SIS_EE_NODEADDR, 3, 0);
1158 * Set SIS_EECTL_CLK to high, so a other master
1159 * can operate on the i2c bus.
1161 SIO_SET(SIS_EECTL_CLK);
1162 /* Refuse EEPROM access by LAN */
1163 SIO_SET(SIS_EECMD_DONE);
1166 sis_read_eeprom(sc, (caddr_t)&eaddr,
1167 SIS_EE_NODEADDR, 3, 0);
1171 sis_add_sysctls(sc);
1173 /* Allocate DMA'able memory. */
1174 if ((error = sis_dma_alloc(sc)) != 0)
1177 ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
1179 device_printf(dev, "can not if_alloc()\n");
1184 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1185 ifp->if_mtu = ETHERMTU;
1186 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1187 ifp->if_ioctl = sis_ioctl;
1188 ifp->if_start = sis_start;
1189 ifp->if_init = sis_init;
1190 IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1191 ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
1192 IFQ_SET_READY(&ifp->if_snd);
1194 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
1195 if (sc->sis_type == SIS_TYPE_83815)
1196 ifp->if_capabilities |= IFCAP_WOL;
1198 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1199 ifp->if_capenable = ifp->if_capabilities;
1205 error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
1206 sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1208 device_printf(dev, "attaching PHYs failed\n");
1213 * Call MI attach routine.
1215 ether_ifattach(ifp, eaddr);
1218 * Tell the upper layer(s) we support long frames.
1220 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1221 ifp->if_capabilities |= IFCAP_VLAN_MTU;
1222 ifp->if_capenable = ifp->if_capabilities;
1223 #ifdef DEVICE_POLLING
1224 ifp->if_capabilities |= IFCAP_POLLING;
1227 /* Hook interrupt last to avoid having to lock softc */
1228 error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
1229 NULL, sis_intr, sc, &sc->sis_intrhand);
1232 device_printf(dev, "couldn't set up irq\n");
1233 ether_ifdetach(ifp);
1245 * Shutdown hardware and free up resources. This can be called any
1246 * time after the mutex has been initialized. It is called in both
1247 * the error case in attach and the normal detach case so it needs
1248 * to be careful about only freeing resources that have actually been
1252 sis_detach(device_t dev)
1254 struct sis_softc *sc;
1257 sc = device_get_softc(dev);
1258 KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
1261 #ifdef DEVICE_POLLING
1262 if (ifp->if_capenable & IFCAP_POLLING)
1263 ether_poll_deregister(ifp);
1266 /* These should only be active if attach succeeded. */
1267 if (device_is_attached(dev)) {
1271 callout_drain(&sc->sis_stat_ch);
1272 ether_ifdetach(ifp);
1275 device_delete_child(dev, sc->sis_miibus);
1276 bus_generic_detach(dev);
1278 if (sc->sis_intrhand)
1279 bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
1280 bus_release_resources(dev, sis_res_spec, sc->sis_res);
1287 mtx_destroy(&sc->sis_mtx);
1292 struct sis_dmamap_arg {
1293 bus_addr_t sis_busaddr;
1297 sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1299 struct sis_dmamap_arg *ctx;
1304 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1306 ctx = (struct sis_dmamap_arg *)arg;
1307 ctx->sis_busaddr = segs[0].ds_addr;
1311 sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
1312 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
1313 bus_addr_t *paddr, const char *msg)
1315 struct sis_dmamap_arg ctx;
1318 error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
1319 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
1320 maxsize, 0, NULL, NULL, tag);
1322 device_printf(sc->sis_dev,
1323 "could not create %s dma tag\n", msg);
1326 /* Allocate DMA'able memory for ring. */
1327 error = bus_dmamem_alloc(*tag, (void **)ring,
1328 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
1330 device_printf(sc->sis_dev,
1331 "could not allocate DMA'able memory for %s\n", msg);
1334 /* Load the address of the ring. */
1335 ctx.sis_busaddr = 0;
1336 error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
1337 &ctx, BUS_DMA_NOWAIT);
1339 device_printf(sc->sis_dev,
1340 "could not load DMA'able memory for %s\n", msg);
1343 *paddr = ctx.sis_busaddr;
1348 sis_dma_alloc(struct sis_softc *sc)
1350 struct sis_rxdesc *rxd;
1351 struct sis_txdesc *txd;
1354 /* Allocate the parent bus DMA tag appropriate for PCI. */
1355 error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1356 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1357 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
1358 0, NULL, NULL, &sc->sis_parent_tag);
1360 device_printf(sc->sis_dev,
1361 "could not allocate parent dma tag\n");
1365 /* Create RX ring. */
1366 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
1367 &sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
1368 &sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
1372 /* Create TX ring. */
1373 error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
1374 &sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
1375 &sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
1379 /* Create tag for RX mbufs. */
1380 error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
1381 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
1382 MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
1384 device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
1388 /* Create tag for TX mbufs. */
1389 error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
1390 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1391 MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
1394 device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
1398 /* Create DMA maps for RX buffers. */
1399 error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
1401 device_printf(sc->sis_dev,
1402 "can't create spare DMA map for RX\n");
1405 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1406 rxd = &sc->sis_rxdesc[i];
1408 error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
1410 device_printf(sc->sis_dev,
1411 "can't create DMA map for RX\n");
1416 /* Create DMA maps for TX buffers. */
1417 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1418 txd = &sc->sis_txdesc[i];
1420 error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
1422 device_printf(sc->sis_dev,
1423 "can't create DMA map for TX\n");
1432 sis_dma_free(struct sis_softc *sc)
1434 struct sis_rxdesc *rxd;
1435 struct sis_txdesc *txd;
1438 /* Destroy DMA maps for RX buffers. */
1439 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1440 rxd = &sc->sis_rxdesc[i];
1442 bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
1444 if (sc->sis_rx_sparemap)
1445 bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
1447 /* Destroy DMA maps for TX buffers. */
1448 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1449 txd = &sc->sis_txdesc[i];
1451 bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
1455 bus_dma_tag_destroy(sc->sis_rx_tag);
1457 bus_dma_tag_destroy(sc->sis_tx_tag);
1459 /* Destroy RX ring. */
1460 if (sc->sis_rx_list_map)
1461 bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
1462 if (sc->sis_rx_list_map && sc->sis_rx_list)
1463 bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
1464 sc->sis_rx_list_map);
1466 if (sc->sis_rx_list_tag)
1467 bus_dma_tag_destroy(sc->sis_rx_list_tag);
1469 /* Destroy TX ring. */
1470 if (sc->sis_tx_list_map)
1471 bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
1473 if (sc->sis_tx_list_map && sc->sis_tx_list)
1474 bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
1475 sc->sis_tx_list_map);
1477 if (sc->sis_tx_list_tag)
1478 bus_dma_tag_destroy(sc->sis_tx_list_tag);
1480 /* Destroy the parent tag. */
1481 if (sc->sis_parent_tag)
1482 bus_dma_tag_destroy(sc->sis_parent_tag);
1486 * Initialize the TX and RX descriptors and allocate mbufs for them. Note that
1487 * we arrange the descriptors in a closed ring, so that the last descriptor
1488 * points back to the first.
1491 sis_ring_init(struct sis_softc *sc)
1493 struct sis_rxdesc *rxd;
1494 struct sis_txdesc *txd;
1498 bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
1499 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1500 txd = &sc->sis_txdesc[i];
1502 if (i == SIS_TX_LIST_CNT - 1)
1503 next = SIS_TX_RING_ADDR(sc, 0);
1505 next = SIS_TX_RING_ADDR(sc, i + 1);
1506 sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
1508 sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
1509 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1510 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1512 sc->sis_rx_cons = 0;
1513 bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
1514 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1515 rxd = &sc->sis_rxdesc[i];
1516 rxd->rx_desc = &sc->sis_rx_list[i];
1517 if (i == SIS_RX_LIST_CNT - 1)
1518 next = SIS_RX_RING_ADDR(sc, 0);
1520 next = SIS_RX_RING_ADDR(sc, i + 1);
1521 rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
1522 error = sis_newbuf(sc, rxd);
1526 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1533 * Initialize an RX descriptor and attach an MBUF cluster.
1536 sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
1539 bus_dma_segment_t segs[1];
1543 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1546 m->m_len = m->m_pkthdr.len = SIS_RXLEN;
1547 #ifndef __NO_STRICT_ALIGNMENT
1548 m_adj(m, SIS_RX_BUF_ALIGN);
1551 if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
1552 segs, &nsegs, 0) != 0) {
1556 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
1558 if (rxd->rx_m != NULL) {
1559 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
1560 BUS_DMASYNC_POSTREAD);
1561 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
1563 map = rxd->rx_dmamap;
1564 rxd->rx_dmamap = sc->sis_rx_sparemap;
1565 sc->sis_rx_sparemap = map;
1566 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
1568 rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
1569 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1573 static __inline void
1574 sis_discard_rxbuf(struct sis_rxdesc *rxd)
1577 rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
1580 #ifndef __NO_STRICT_ALIGNMENT
1581 static __inline void
1582 sis_fixup_rx(struct mbuf *m)
1584 uint16_t *src, *dst;
1587 src = mtod(m, uint16_t *);
1588 dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
1590 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1593 m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
1598 * A frame has been uploaded: pass the resulting mbuf chain up to
1599 * the higher level protocols.
1602 sis_rxeof(struct sis_softc *sc)
1606 struct sis_rxdesc *rxd;
1607 struct sis_desc *cur_rx;
1608 int prog, rx_cons, rx_npkts = 0, total_len;
1611 SIS_LOCK_ASSERT(sc);
1613 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1616 rx_cons = sc->sis_rx_cons;
1619 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
1620 SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
1621 #ifdef DEVICE_POLLING
1622 if (ifp->if_capenable & IFCAP_POLLING) {
1623 if (sc->rxcycles <= 0)
1628 cur_rx = &sc->sis_rx_list[rx_cons];
1629 rxstat = le32toh(cur_rx->sis_cmdsts);
1630 if ((rxstat & SIS_CMDSTS_OWN) == 0)
1632 rxd = &sc->sis_rxdesc[rx_cons];
1634 total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
1635 if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
1636 total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
1638 rxstat &= ~SIS_RXSTAT_GIANT;
1639 if (SIS_RXSTAT_ERROR(rxstat) != 0) {
1641 if (rxstat & SIS_RXSTAT_COLL)
1642 ifp->if_collisions++;
1643 sis_discard_rxbuf(rxd);
1647 /* Add a new receive buffer to the ring. */
1649 if (sis_newbuf(sc, rxd) != 0) {
1651 sis_discard_rxbuf(rxd);
1655 /* No errors; receive the packet. */
1656 m->m_pkthdr.len = m->m_len = total_len;
1657 #ifndef __NO_STRICT_ALIGNMENT
1659 * On architectures without alignment problems we try to
1660 * allocate a new buffer for the receive ring, and pass up
1661 * the one where the packet is already, saving the expensive
1667 m->m_pkthdr.rcvif = ifp;
1670 (*ifp->if_input)(ifp, m);
1676 sc->sis_rx_cons = rx_cons;
1677 bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
1678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1685 * A frame was downloaded to the chip. It's safe for us to clean up
1690 sis_txeof(struct sis_softc *sc)
1693 struct sis_desc *cur_tx;
1694 struct sis_txdesc *txd;
1695 uint32_t cons, txstat;
1697 SIS_LOCK_ASSERT(sc);
1699 cons = sc->sis_tx_cons;
1700 if (cons == sc->sis_tx_prod)
1704 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
1705 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1708 * Go through our tx list and free mbufs for those
1709 * frames that have been transmitted.
1711 for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
1712 cur_tx = &sc->sis_tx_list[cons];
1713 txstat = le32toh(cur_tx->sis_cmdsts);
1714 if ((txstat & SIS_CMDSTS_OWN) != 0)
1716 txd = &sc->sis_txdesc[cons];
1717 if (txd->tx_m != NULL) {
1718 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
1719 BUS_DMASYNC_POSTWRITE);
1720 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1723 if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
1725 ifp->if_collisions +=
1726 (txstat & SIS_TXSTAT_COLLCNT) >> 16;
1729 if (txstat & SIS_TXSTAT_EXCESSCOLLS)
1730 ifp->if_collisions++;
1731 if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
1732 ifp->if_collisions++;
1736 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1738 sc->sis_tx_cons = cons;
1739 if (sc->sis_tx_cnt == 0)
1740 sc->sis_watchdog_timer = 0;
1746 struct sis_softc *sc;
1747 struct mii_data *mii;
1751 SIS_LOCK_ASSERT(sc);
1754 mii = device_get_softc(sc->sis_miibus);
1757 if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
1758 sis_miibus_statchg(sc->sis_dev);
1759 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
1762 #ifdef DEVICE_POLLING
1763 static poll_handler_t sis_poll;
1766 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1768 struct sis_softc *sc = ifp->if_softc;
1772 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1778 * On the sis, reading the status register also clears it.
1779 * So before returning to intr mode we must make sure that all
1780 * possible pending sources of interrupts have been served.
1781 * In practice this means run to completion the *eof routines,
1782 * and then call the interrupt routine
1784 sc->rxcycles = count;
1785 rx_npkts = sis_rxeof(sc);
1787 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1790 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1793 /* Reading the ISR register clears all interrupts. */
1794 status = CSR_READ_4(sc, SIS_ISR);
1796 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1799 if (status & (SIS_ISR_RX_IDLE))
1800 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1802 if (status & SIS_ISR_SYSERR) {
1803 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1811 #endif /* DEVICE_POLLING */
1816 struct sis_softc *sc;
1824 #ifdef DEVICE_POLLING
1825 if (ifp->if_capenable & IFCAP_POLLING) {
1831 /* Reading the ISR register clears all interrupts. */
1832 status = CSR_READ_4(sc, SIS_ISR);
1833 if ((status & SIS_INTRS) == 0) {
1839 /* Disable interrupts. */
1840 CSR_WRITE_4(sc, SIS_IER, 0);
1842 for (;(status & SIS_INTRS) != 0;) {
1843 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1846 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
1847 SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
1850 if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
1851 SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
1854 if (status & SIS_ISR_RX_OFLOW)
1857 if (status & (SIS_ISR_RX_IDLE))
1858 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1860 if (status & SIS_ISR_SYSERR) {
1861 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1866 status = CSR_READ_4(sc, SIS_ISR);
1869 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1870 /* Re-enable interrupts. */
1871 CSR_WRITE_4(sc, SIS_IER, 1);
1873 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1881 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1882 * pointers to the fragment pointers.
1885 sis_encap(struct sis_softc *sc, struct mbuf **m_head)
1888 struct sis_txdesc *txd;
1890 bus_dma_segment_t segs[SIS_MAXTXSEGS];
1892 int error, i, frag, nsegs, prod;
1895 prod = sc->sis_tx_prod;
1896 txd = &sc->sis_txdesc[prod];
1897 if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
1898 (*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
1900 padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
1901 if (M_WRITABLE(m) == 0) {
1902 /* Get a writable copy. */
1903 m = m_dup(*m_head, M_DONTWAIT);
1911 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
1912 m = m_defrag(m, M_DONTWAIT);
1920 * Manually pad short frames, and zero the pad space
1921 * to avoid leaking data.
1923 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1924 m->m_pkthdr.len += padlen;
1925 m->m_len = m->m_pkthdr.len;
1928 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1929 *m_head, segs, &nsegs, 0);
1930 if (error == EFBIG) {
1931 m = m_collapse(*m_head, M_DONTWAIT, SIS_MAXTXSEGS);
1938 error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
1939 *m_head, segs, &nsegs, 0);
1945 } else if (error != 0)
1948 /* Check for descriptor overruns. */
1949 if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
1950 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
1954 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
1957 for (i = 0; i < nsegs; i++) {
1958 f = &sc->sis_tx_list[prod];
1960 f->sis_cmdsts = htole32(segs[i].ds_len |
1963 f->sis_cmdsts = htole32(segs[i].ds_len |
1964 SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
1965 f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
1966 SIS_INC(prod, SIS_TX_LIST_CNT);
1970 /* Update producer index. */
1971 sc->sis_tx_prod = prod;
1973 /* Remove MORE flag on the last descriptor. */
1974 prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
1975 f = &sc->sis_tx_list[prod];
1976 f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
1978 /* Lastly transfer ownership of packet to the controller. */
1979 f = &sc->sis_tx_list[frag];
1980 f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
1982 /* Swap the last and the first dmamaps. */
1983 map = txd->tx_dmamap;
1984 txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
1985 sc->sis_txdesc[prod].tx_dmamap = map;
1986 sc->sis_txdesc[prod].tx_m = *m_head;
1992 sis_start(struct ifnet *ifp)
1994 struct sis_softc *sc;
2003 sis_startl(struct ifnet *ifp)
2005 struct sis_softc *sc;
2006 struct mbuf *m_head;
2011 SIS_LOCK_ASSERT(sc);
2013 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2014 IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
2017 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2018 sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
2019 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2023 if (sis_encap(sc, &m_head) != 0) {
2026 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2027 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2034 * If there's a BPF listener, bounce a copy of this frame
2037 BPF_MTAP(ifp, m_head);
2042 bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
2043 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2044 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
2047 * Set a timeout in case the chip goes out to lunch.
2049 sc->sis_watchdog_timer = 5;
2056 struct sis_softc *sc = xsc;
2064 sis_initl(struct sis_softc *sc)
2066 struct ifnet *ifp = sc->sis_ifp;
2067 struct mii_data *mii;
2070 SIS_LOCK_ASSERT(sc);
2072 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2076 * Cancel pending I/O and free all RX/TX buffers.
2080 * Reset the chip to a known state.
2084 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
2086 * Configure 400usec of interrupt holdoff. This is based
2087 * on emperical tests on a Soekris 4801.
2089 CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
2093 mii = device_get_softc(sc->sis_miibus);
2095 /* Set MAC address */
2096 eaddr = IF_LLADDR(sc->sis_ifp);
2097 if (sc->sis_type == SIS_TYPE_83815) {
2098 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
2099 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
2100 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
2101 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
2102 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
2103 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
2105 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
2106 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
2107 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
2108 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
2109 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
2110 CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
2113 /* Init circular TX/RX lists. */
2114 if (sis_ring_init(sc) != 0) {
2115 device_printf(sc->sis_dev,
2116 "initialization failed: no memory for rx buffers\n");
2121 if (sc->sis_type == SIS_TYPE_83815 || sc->sis_type == SIS_TYPE_83816) {
2122 if (sc->sis_manual_pad != 0)
2123 sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
2125 sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
2129 * Short Cable Receive Errors (MP21.E)
2130 * also: Page 78 of the DP83815 data sheet (september 2002 version)
2131 * recommends the following register settings "for optimum
2132 * performance." for rev 15C. Set this also for 15D parts as
2133 * they require it in practice.
2135 if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
2136 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
2137 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
2138 /* set val for c2 */
2139 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
2141 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
2142 /* rais SD off, from 4 to c */
2143 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
2144 CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
2148 /* Turn the receive filter on */
2149 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
2152 * Load the address of the RX and TX lists.
2154 CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
2155 CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
2157 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
2158 * the PCI bus. When this bit is set, the Max DMA Burst Size
2159 * for TX/RX DMA should be no larger than 16 double words.
2161 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
2162 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
2164 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
2167 /* Accept Long Packets for VLAN support */
2168 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
2171 * Assume 100Mbps link, actual MAC configuration is done
2172 * after getting a valid link.
2174 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
2177 * Enable interrupts.
2179 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
2180 #ifdef DEVICE_POLLING
2182 * ... only enable interrupts if we are not polling, make sure
2183 * they are off otherwise.
2185 if (ifp->if_capenable & IFCAP_POLLING)
2186 CSR_WRITE_4(sc, SIS_IER, 0);
2189 CSR_WRITE_4(sc, SIS_IER, 1);
2191 /* Clear MAC disable. */
2192 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
2194 sc->sis_flags &= ~SIS_FLAG_LINK;
2197 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2198 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2200 callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
2204 * Set media options.
2207 sis_ifmedia_upd(struct ifnet *ifp)
2209 struct sis_softc *sc;
2210 struct mii_data *mii;
2211 struct mii_softc *miisc;
2217 mii = device_get_softc(sc->sis_miibus);
2218 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2220 error = mii_mediachg(mii);
2227 * Report current media status.
2230 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2232 struct sis_softc *sc;
2233 struct mii_data *mii;
2238 mii = device_get_softc(sc->sis_miibus);
2241 ifmr->ifm_active = mii->mii_media_active;
2242 ifmr->ifm_status = mii->mii_media_status;
2246 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2248 struct sis_softc *sc = ifp->if_softc;
2249 struct ifreq *ifr = (struct ifreq *) data;
2250 struct mii_data *mii;
2251 int error = 0, mask;
2256 if (ifp->if_flags & IFF_UP) {
2257 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2258 ((ifp->if_flags ^ sc->sis_if_flags) &
2259 (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2263 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2265 sc->sis_if_flags = ifp->if_flags;
2276 mii = device_get_softc(sc->sis_miibus);
2277 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2281 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2282 #ifdef DEVICE_POLLING
2283 if ((mask & IFCAP_POLLING) != 0 &&
2284 (IFCAP_POLLING & ifp->if_capabilities) != 0) {
2285 ifp->if_capenable ^= IFCAP_POLLING;
2286 if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
2287 error = ether_poll_register(sis_poll, ifp);
2292 /* Disable interrupts. */
2293 CSR_WRITE_4(sc, SIS_IER, 0);
2295 error = ether_poll_deregister(ifp);
2296 /* Enable interrupts. */
2297 CSR_WRITE_4(sc, SIS_IER, 1);
2300 #endif /* DEVICE_POLLING */
2301 if ((mask & IFCAP_WOL) != 0 &&
2302 (ifp->if_capabilities & IFCAP_WOL) != 0) {
2303 if ((mask & IFCAP_WOL_UCAST) != 0)
2304 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2305 if ((mask & IFCAP_WOL_MCAST) != 0)
2306 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2307 if ((mask & IFCAP_WOL_MAGIC) != 0)
2308 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2313 error = ether_ioctl(ifp, command, data);
2321 sis_watchdog(struct sis_softc *sc)
2324 SIS_LOCK_ASSERT(sc);
2326 if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
2329 device_printf(sc->sis_dev, "watchdog timeout\n");
2330 sc->sis_ifp->if_oerrors++;
2332 sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2335 if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
2336 sis_startl(sc->sis_ifp);
2340 * Stop the adapter and free any mbufs allocated to the
2344 sis_stop(struct sis_softc *sc)
2347 struct sis_rxdesc *rxd;
2348 struct sis_txdesc *txd;
2351 SIS_LOCK_ASSERT(sc);
2354 sc->sis_watchdog_timer = 0;
2356 callout_stop(&sc->sis_stat_ch);
2358 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2359 CSR_WRITE_4(sc, SIS_IER, 0);
2360 CSR_WRITE_4(sc, SIS_IMR, 0);
2361 CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
2362 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2364 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2365 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2367 sc->sis_flags &= ~SIS_FLAG_LINK;
2370 * Free data in the RX lists.
2372 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2373 rxd = &sc->sis_rxdesc[i];
2374 if (rxd->rx_m != NULL) {
2375 bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
2376 BUS_DMASYNC_POSTREAD);
2377 bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
2384 * Free the TX list buffers.
2386 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2387 txd = &sc->sis_txdesc[i];
2388 if (txd->tx_m != NULL) {
2389 bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
2390 BUS_DMASYNC_POSTWRITE);
2391 bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
2399 * Stop all chip I/O so that the kernel's probe routines don't
2400 * get confused by errant DMAs when rebooting.
2403 sis_shutdown(device_t dev)
2406 return (sis_suspend(dev));
2410 sis_suspend(device_t dev)
2412 struct sis_softc *sc;
2414 sc = device_get_softc(dev);
2423 sis_resume(device_t dev)
2425 struct sis_softc *sc;
2428 sc = device_get_softc(dev);
2431 if ((ifp->if_flags & IFF_UP) != 0) {
2432 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2440 sis_wol(struct sis_softc *sc)
2448 if ((ifp->if_capenable & IFCAP_WOL) == 0)
2451 if (sc->sis_type == SIS_TYPE_83815) {
2453 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2455 /* Configure WOL events. */
2456 CSR_READ_4(sc, NS_WCSR);
2458 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2459 val |= NS_WCSR_WAKE_UCAST;
2460 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2461 val |= NS_WCSR_WAKE_MCAST;
2462 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2463 val |= NS_WCSR_WAKE_MAGIC;
2464 CSR_WRITE_4(sc, NS_WCSR, val);
2465 /* Enable PME and clear PMESTS. */
2466 val = CSR_READ_4(sc, NS_CLKRUN);
2467 val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
2468 CSR_WRITE_4(sc, NS_CLKRUN, val);
2469 /* Enable silent RX mode. */
2470 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
2472 if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
2475 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2476 val |= SIS_PWRMAN_WOL_MAGIC;
2477 CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
2479 pmstat = pci_read_config(sc->sis_dev,
2480 pmc + PCIR_POWER_STATUS, 2);
2481 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2482 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2483 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2484 pci_write_config(sc->sis_dev,
2485 pmc + PCIR_POWER_STATUS, pmstat, 2);
2490 sis_add_sysctls(struct sis_softc *sc)
2492 struct sysctl_ctx_list *ctx;
2493 struct sysctl_oid_list *children;
2497 ctx = device_get_sysctl_ctx(sc->sis_dev);
2498 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
2500 unit = device_get_unit(sc->sis_dev);
2502 * Unlike most other controllers, NS DP83815/DP83816 controllers
2503 * seem to pad with 0xFF when it encounter short frames. According
2504 * to RFC 1042 the pad bytes should be 0x00. Turning this tunable
2505 * on will have driver pad manully but it's disabled by default
2506 * because it will consume extra CPU cycles for short frames.
2508 sc->sis_manual_pad = 0;
2509 snprintf(tn, sizeof(tn), "dev.sis.%d.manual_pad", unit);
2510 TUNABLE_INT_FETCH(tn, &sc->sis_manual_pad);
2511 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
2512 CTLFLAG_RW, &sc->sis_manual_pad, 0, "Manually pad short frames");
2515 static device_method_t sis_methods[] = {
2516 /* Device interface */
2517 DEVMETHOD(device_probe, sis_probe),
2518 DEVMETHOD(device_attach, sis_attach),
2519 DEVMETHOD(device_detach, sis_detach),
2520 DEVMETHOD(device_shutdown, sis_shutdown),
2521 DEVMETHOD(device_suspend, sis_suspend),
2522 DEVMETHOD(device_resume, sis_resume),
2525 DEVMETHOD(bus_print_child, bus_generic_print_child),
2526 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2529 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
2530 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
2531 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
2536 static driver_t sis_driver = {
2539 sizeof(struct sis_softc)
2542 static devclass_t sis_devclass;
2544 DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
2545 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);