2 * Copyright (c) 1999 Seigo Tanimura
5 * Portions of this source are based on cwcealdr.cpp and dhwiface.cpp in
6 * cwcealdr1.zip, the sample sources by Crystal Semiconductor.
7 * Copyright (c) 1996-1998 Crystal Semiconductor Corp.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <machine/resource.h>
38 #include <machine/bus.h>
41 #ifdef HAVE_KERNEL_OPTION_HEADERS
45 #include <dev/sound/pcm/sound.h>
46 #include <dev/sound/chip.h>
47 #include <dev/sound/pci/csareg.h>
48 #include <dev/sound/pci/csavar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
53 #include <dev/sound/pci/cs461x_dsp.h>
55 SND_DECLARE_FILE("$FreeBSD$");
57 /* This is the pci device id. */
58 #define CS4610_PCI_ID 0x60011013
59 #define CS4614_PCI_ID 0x60031013
60 #define CS4615_PCI_ID 0x60041013
62 /* Here is the parameter structure per a device. */
64 device_t dev; /* device */
65 csa_res res; /* resources */
67 device_t pcm; /* pcm device */
68 driver_intr_t* pcmintr; /* pcm intr */
69 void *pcmintr_arg; /* pcm intr arg */
70 device_t midi; /* midi device */
71 driver_intr_t* midiintr; /* midi intr */
72 void *midiintr_arg; /* midi intr arg */
73 void *ih; /* cookie */
75 struct csa_card *card;
76 struct csa_bridgeinfo binfo; /* The state of this bridge. */
79 typedef struct csa_softc *sc_p;
81 static int csa_probe(device_t dev);
82 static int csa_attach(device_t dev);
83 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
84 u_long start, u_long end, u_long count, u_int flags);
85 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
87 static int csa_setup_intr(device_t bus, device_t child,
88 struct resource *irq, int flags,
89 #if __FreeBSD_version >= 700031
90 driver_filter_t *filter,
92 driver_intr_t *intr, void *arg, void **cookiep);
93 static int csa_teardown_intr(device_t bus, device_t child,
94 struct resource *irq, void *cookie);
95 static driver_intr_t csa_intr;
96 static int csa_initialize(sc_p scp);
97 static int csa_downloadimage(csa_res *resp);
98 static int csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len);
100 static devclass_t csa_devclass;
116 devclass_t pci_devclass;
117 device_t *pci_devices, *pci_children, *busp, *childp;
118 int pci_count = 0, pci_childcount = 0;
121 bus_space_tag_t btag;
123 if ((pci_devclass = devclass_find("pci")) == NULL) {
127 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
129 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
131 if (device_get_children(*busp, &pci_children, &pci_childcount))
133 for (j = 0, childp = pci_children; j < pci_childcount; j++, childp++) {
134 if (pci_get_vendor(*childp) == 0x8086 && pci_get_device(*childp) == 0x7113) {
135 port = (pci_read_config(*childp, 0x41, 1) << 8) + 0x10;
137 btag = X86_BUS_SPACE_IO;
139 control = bus_space_read_2(btag, 0x0, port);
141 control |= run? 0 : 0x2000;
142 bus_space_write_2(btag, 0x0, port, control);
143 free(pci_devices, M_TEMP);
144 free(pci_children, M_TEMP);
148 free(pci_children, M_TEMP);
151 free(pci_devices, M_TEMP);
158 static struct csa_card cards_4610[] = {
159 {0, 0, "Unknown/invalid SSID (CS4610)", NULL, NULL, NULL, 0},
162 static struct csa_card cards_4614[] = {
163 {0x1489, 0x7001, "Genius Soundmaker 128 value", amp_none, NULL, NULL, 0},
164 {0x5053, 0x3357, "Turtle Beach Santa Cruz", amp_voyetra, NULL, NULL, 1},
165 {0x1071, 0x6003, "Mitac MI6020/21", amp_voyetra, NULL, NULL, 0},
166 {0x14AF, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
167 {0x1681, 0x0050, "Hercules Game Theatre XP", NULL, NULL, NULL, 0},
168 {0x1014, 0x0132, "Thinkpad 570", amp_none, NULL, NULL, 0},
169 {0x1014, 0x0153, "Thinkpad 600X/A20/T20", amp_none, NULL, clkrun_hack, 0},
170 {0x1014, 0x1010, "Thinkpad 600E (unsupported)", NULL, NULL, NULL, 0},
171 {0, 0, "Unknown/invalid SSID (CS4614)", NULL, NULL, NULL, 0},
174 static struct csa_card cards_4615[] = {
175 {0, 0, "Unknown/invalid SSID (CS4615)", NULL, NULL, NULL, 0},
178 static struct csa_card nocard = {0, 0, "unknown", NULL, NULL, NULL, 0};
183 struct csa_card *cards;
186 static struct card_type cards[] = {
187 {CS4610_PCI_ID, "CS4610/CS4611", cards_4610},
188 {CS4614_PCI_ID, "CS4280/CS4614/CS4622/CS4624/CS4630", cards_4614},
189 {CS4615_PCI_ID, "CS4615", cards_4615},
193 static struct card_type *
194 csa_findcard(device_t dev)
199 while (cards[i].devid != 0) {
200 if (pci_get_devid(dev) == cards[i].devid)
208 csa_findsubcard(device_t dev)
211 struct card_type *card;
212 struct csa_card *subcard;
214 card = csa_findcard(dev);
217 subcard = card->cards;
219 while (subcard[i].subvendor != 0) {
220 if (pci_get_subvendor(dev) == subcard[i].subvendor
221 && pci_get_subdevice(dev) == subcard[i].subdevice) {
230 csa_probe(device_t dev)
232 struct card_type *card;
234 card = csa_findcard(dev);
236 device_set_desc(dev, card->name);
237 return BUS_PROBE_DEFAULT;
243 csa_attach(device_t dev)
247 struct sndcard_func *func;
250 scp = device_get_softc(dev);
252 /* Fill in the softc. */
253 bzero(scp, sizeof(*scp));
256 pci_enable_busmaster(dev);
258 /* Allocate the resources. */
260 scp->card = csa_findsubcard(dev);
261 scp->binfo.card = scp->card;
262 printf("csa: card is %s\n", scp->card->name);
263 resp->io_rid = PCIR_BAR(0);
264 resp->io = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
265 &resp->io_rid, RF_ACTIVE);
266 if (resp->io == NULL)
268 resp->mem_rid = PCIR_BAR(1);
269 resp->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
270 &resp->mem_rid, RF_ACTIVE);
271 if (resp->mem == NULL)
274 resp->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
275 &resp->irq_rid, RF_ACTIVE | RF_SHAREABLE);
276 if (resp->irq == NULL)
279 /* Enable interrupt. */
280 if (snd_setup_intr(dev, resp->irq, 0, csa_intr, scp, &scp->ih))
283 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
284 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
287 /* Initialize the chip. */
288 if (csa_initialize(scp))
291 /* Reset the Processor. */
294 /* Download the Processor Image to the processor. */
295 if (csa_downloadimage(resp))
298 /* Attach the children. */
301 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
306 func->varinfo = &scp->binfo;
307 func->func = SCF_PCM;
308 scp->pcm = device_add_child(dev, "pcm", -1);
309 device_set_ivars(scp->pcm, func);
312 func = malloc(sizeof(struct sndcard_func), M_DEVBUF, M_NOWAIT | M_ZERO);
317 func->varinfo = &scp->binfo;
318 func->func = SCF_MIDI;
319 scp->midi = device_add_child(dev, "midi", -1);
320 device_set_ivars(scp->midi, func);
322 bus_generic_attach(dev);
327 bus_teardown_intr(dev, resp->irq, scp->ih);
329 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
331 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
333 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
338 csa_detach(device_t dev)
342 struct sndcard_func *func;
345 scp = device_get_softc(dev);
348 if (scp->midi != NULL) {
349 func = device_get_ivars(scp->midi);
350 err = device_delete_child(dev, scp->midi);
354 free(func, M_DEVBUF);
358 if (scp->pcm != NULL) {
359 func = device_get_ivars(scp->pcm);
360 err = device_delete_child(dev, scp->pcm);
364 free(func, M_DEVBUF);
368 bus_teardown_intr(dev, resp->irq, scp->ih);
369 bus_release_resource(dev, SYS_RES_IRQ, resp->irq_rid, resp->irq);
370 bus_release_resource(dev, SYS_RES_MEMORY, resp->mem_rid, resp->mem);
371 bus_release_resource(dev, SYS_RES_MEMORY, resp->io_rid, resp->io);
373 return bus_generic_detach(dev);
377 csa_resume(device_t dev)
382 scp = device_get_softc(dev);
385 /* Initialize the chip. */
386 if (csa_initialize(scp))
389 /* Reset the Processor. */
392 /* Download the Processor Image to the processor. */
393 if (csa_downloadimage(resp))
396 return (bus_generic_resume(dev));
399 static struct resource *
400 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
401 u_long start, u_long end, u_long count, u_int flags)
405 struct resource *res;
407 scp = device_get_softc(bus);
435 csa_release_resource(device_t bus, device_t child, int type, int rid,
442 * The following three functions deal with interrupt handling.
443 * An interrupt is primarily handled by the bridge driver.
444 * The bridge driver then determines the child devices to pass
445 * the interrupt. Certain information of the device can be read
446 * only once(eg the value of HISR). The bridge driver is responsible
447 * to pass such the information to the children.
451 csa_setup_intr(device_t bus, device_t child,
452 struct resource *irq, int flags,
453 #if __FreeBSD_version >= 700031
454 driver_filter_t *filter,
456 driver_intr_t *intr, void *arg, void **cookiep)
460 struct sndcard_func *func;
462 #if __FreeBSD_version >= 700031
463 if (filter != NULL) {
464 printf("ata-csa.c: we cannot use a filter here\n");
468 scp = device_get_softc(bus);
472 * Look at the function code of the child to determine
473 * the appropriate hander for it.
475 func = device_get_ivars(child);
476 if (func == NULL || irq != resp->irq)
479 switch (func->func) {
482 scp->pcmintr_arg = arg;
486 scp->midiintr = intr;
487 scp->midiintr_arg = arg;
494 if ((csa_readio(resp, BA0_HISR) & HISR_INTENA) == 0)
495 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
501 csa_teardown_intr(device_t bus, device_t child,
502 struct resource *irq, void *cookie)
506 struct sndcard_func *func;
508 scp = device_get_softc(bus);
512 * Look at the function code of the child to determine
513 * the appropriate hander for it.
515 func = device_get_ivars(child);
516 if (func == NULL || irq != resp->irq || cookie != scp)
519 switch (func->func) {
522 scp->pcmintr_arg = NULL;
526 scp->midiintr = NULL;
527 scp->midiintr_arg = NULL;
537 /* The interrupt handler */
547 /* Is this interrupt for us? */
548 hisr = csa_readio(resp, BA0_HISR);
549 if ((hisr & 0x7fffffff) == 0) {
551 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
556 * Pass the value of HISR via struct csa_bridgeinfo.
557 * The children get access through their ivars.
559 scp->binfo.hisr = hisr;
561 /* Invoke the handlers of the children. */
562 if ((hisr & (HISR_VC0 | HISR_VC1)) != 0 && scp->pcmintr != NULL) {
563 scp->pcmintr(scp->pcmintr_arg);
564 hisr &= ~(HISR_VC0 | HISR_VC1);
566 if ((hisr & HISR_MIDI) != 0 && scp->midiintr != NULL) {
567 scp->midiintr(scp->midiintr_arg);
572 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
576 csa_initialize(sc_p scp)
579 u_int32_t acsts, acisv;
585 * First, blast the clock control register to zero so that the PLL starts
586 * out in a known state, and blast the master serial port control register
587 * to zero so that the serial ports also start out in a known state.
589 csa_writeio(resp, BA0_CLKCR1, 0);
590 csa_writeio(resp, BA0_SERMC1, 0);
593 * If we are in AC97 mode, then we must set the part to a host controlled
594 * AC-link. Otherwise, we won't be able to bring up the link.
597 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_1_03); /* 1.03 codec */
599 csa_writeio(resp, BA0_SERACC, SERACC_HSP | SERACC_CODEC_TYPE_2_0); /* 2.0 codec */
603 * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
604 * spec) and then drive it high. This is done for non AC97 modes since
605 * there might be logic external to the CS461x that uses the ARST# line
608 csa_writeio(resp, BA0_ACCTL, 1);
610 csa_writeio(resp, BA0_ACCTL, 0);
612 csa_writeio(resp, BA0_ACCTL, ACCTL_RSTN);
615 * The first thing we do here is to enable sync generation. As soon
616 * as we start receiving bit clock, we'll start producing the SYNC
619 csa_writeio(resp, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
622 * Now wait for a short while to allow the AC97 part to start
623 * generating bit clock (so we don't try to start the PLL without an
629 * Set the serial port timing configuration, so that
630 * the clock control circuit gets its clock from the correct place.
632 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97);
636 * Write the selected clock control setup to the hardware. Do not turn on
637 * SWCE yet (if requested), so that the devices clocked by the output of
638 * PLL are not clocked until the PLL is stable.
640 csa_writeio(resp, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
641 csa_writeio(resp, BA0_PLLM, 0x3a);
642 csa_writeio(resp, BA0_CLKCR2, CLKCR2_PDIVS_8);
647 csa_writeio(resp, BA0_CLKCR1, CLKCR1_PLLP);
650 * Wait until the PLL has stabilized.
655 * Turn on clocking of the core so that we can setup the serial ports.
657 csa_writeio(resp, BA0_CLKCR1, csa_readio(resp, BA0_CLKCR1) | CLKCR1_SWCE);
660 * Fill the serial port FIFOs with silence.
662 csa_clearserialfifos(resp);
665 * Set the serial port FIFO pointer to the first sample in the FIFO.
668 csa_writeio(resp, BA0_SERBSP, 0);
672 * Write the serial port configuration to the part. The master
673 * enable bit is not set until all other values have been written.
675 csa_writeio(resp, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
676 csa_writeio(resp, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
677 csa_writeio(resp, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
680 * Wait for the codec ready signal from the AC97 codec.
683 for (i = 0 ; i < 1000 ; i++) {
685 * First, lets wait a short while to let things settle out a bit,
686 * and to prevent retrying the read too quickly.
691 * Read the AC97 status register to see if we've seen a CODEC READY
692 * signal from the AC97 codec.
694 acsts = csa_readio(resp, BA0_ACSTS);
695 if ((acsts & ACSTS_CRDY) != 0)
700 * Make sure we sampled CODEC READY.
702 if ((acsts & ACSTS_CRDY) == 0)
706 * Assert the vaid frame signal so that we can start sending commands
709 csa_writeio(resp, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
712 * Wait until we've sampled input slots 3 and 4 as valid, meaning that
713 * the codec is pumping ADC data across the AC-link.
716 for (i = 0 ; i < 2000 ; i++) {
718 * First, lets wait a short while to let things settle out a bit,
719 * and to prevent retrying the read too quickly.
722 DELAY(10000000L); /* clw */
727 * Read the input slot valid register and see if input slots 3 and
730 acisv = csa_readio(resp, BA0_ACISV);
731 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
735 * Make sure we sampled valid input slots 3 and 4. If not, then return
738 if ((acisv & (ACISV_ISV3 | ACISV_ISV4)) != (ACISV_ISV3 | ACISV_ISV4))
742 * Now, assert valid frame and the slot 3 and 4 valid bits. This will
743 * commense the transfer of digital audio data to the AC97 codec.
745 csa_writeio(resp, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
748 * Power down the DAC and ADC. We will power them up (if) when we need
752 csa_writeio(resp, BA0_AC97_POWERDOWN, 0x300);
756 * Turn off the Processor by turning off the software clock enable flag in
757 * the clock control register.
760 clkcr1 = csa_readio(resp, BA0_CLKCR1) & ~CLKCR1_SWCE;
761 csa_writeio(resp, BA0_CLKCR1, clkcr1);
765 * Enable interrupts on the part.
768 csa_writeio(resp, BA0_HICR, HICR_IEV | HICR_CHGM);
775 csa_clearserialfifos(csa_res *resp)
778 u_int8_t clkcr1, serbst;
781 * See if the devices are powered down. If so, we must power them up first
782 * or they will not respond.
785 clkcr1 = csa_readio(resp, BA0_CLKCR1);
786 if ((clkcr1 & CLKCR1_SWCE) == 0) {
787 csa_writeio(resp, BA0_CLKCR1, clkcr1 | CLKCR1_SWCE);
792 * We want to clear out the serial port FIFOs so we don't end up playing
793 * whatever random garbage happens to be in them. We fill the sample FIFOs
794 * with zero (silence).
796 csa_writeio(resp, BA0_SERBWP, 0);
798 /* Fill all 256 sample FIFO locations. */
800 for (i = 0 ; i < 256 ; i++) {
801 /* Make sure the previous FIFO write operation has completed. */
802 for (j = 0 ; j < 5 ; j++) {
804 serbst = csa_readio(resp, BA0_SERBST);
805 if ((serbst & SERBST_WBSY) == 0)
808 if ((serbst & SERBST_WBSY) != 0) {
810 csa_writeio(resp, BA0_CLKCR1, clkcr1);
812 /* Write the serial port FIFO index. */
813 csa_writeio(resp, BA0_SERBAD, i);
814 /* Tell the serial port to load the new value into the FIFO location. */
815 csa_writeio(resp, BA0_SERBCM, SERBCM_WRC);
818 * Now, if we powered up the devices, then power them back down again.
819 * This is kinda ugly, but should never happen.
822 csa_writeio(resp, BA0_CLKCR1, clkcr1);
826 csa_resetdsp(csa_res *resp)
831 * Write the reset bit of the SP control register.
833 csa_writemem(resp, BA1_SPCR, SPCR_RSTSP);
836 * Write the control register.
838 csa_writemem(resp, BA1_SPCR, SPCR_DRQEN);
841 * Clear the trap registers.
843 for (i = 0 ; i < 8 ; i++) {
844 csa_writemem(resp, BA1_DREG, DREG_REGID_TRAP_SELECT + i);
845 csa_writemem(resp, BA1_TWPR, 0xffff);
847 csa_writemem(resp, BA1_DREG, 0);
850 * Set the frame timer to reflect the number of cycles per frame.
852 csa_writemem(resp, BA1_FRMT, 0xadf);
856 csa_downloadimage(csa_res *resp)
861 for (ul = 0, offset = 0 ; ul < INKY_MEMORY_COUNT ; ul++) {
863 * DMA this block from host memory to the appropriate
864 * memory on the CSDevice.
866 ret = csa_transferimage(resp,
867 cs461x_firmware.BA1Array + offset,
868 cs461x_firmware.MemoryStat[ul].ulDestAddr,
869 cs461x_firmware.MemoryStat[ul].ulSourceSize);
872 offset += cs461x_firmware.MemoryStat[ul].ulSourceSize >> 2;
878 csa_transferimage(csa_res *resp, u_int32_t *src, u_long dest, u_long len)
883 * We do not allow DMAs from host memory to host memory (although the DMA
884 * can do it) and we do not allow DMAs which are not a multiple of 4 bytes
885 * in size (because that DMA can not do that). Return an error if either
886 * of these conditions exist.
888 if ((len & 0x3) != 0)
891 /* Check the destination address that it is a multiple of 4 */
892 if ((dest & 0x3) != 0)
895 /* Write the buffer out. */
896 for (ul = 0 ; ul < len ; ul += 4)
897 csa_writemem(resp, dest + ul, src[ul >> 2]);
902 csa_readcodec(csa_res *resp, u_long offset, u_int32_t *data)
905 u_int32_t acctl, acsts;
908 * Make sure that there is not data sitting around from a previous
909 * uncompleted access. ACSDA = Status Data Register = 47Ch
911 csa_readio(resp, BA0_ACSDA);
914 * Setup the AC97 control registers on the CS461x to send the
915 * appropriate command to the AC97 to perform the read.
916 * ACCAD = Command Address Register = 46Ch
917 * ACCDA = Command Data Register = 470h
918 * ACCTL = Control Register = 460h
919 * set DCV - will clear when process completed
920 * set CRW - Read command
921 * set VFRM - valid frame enabled
922 * set ESYN - ASYNC generation enabled
923 * set RSTN - ARST# inactive, AC97 codec not reset
927 * Get the actual AC97 register from the offset
929 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
930 csa_writeio(resp, BA0_ACCDA, 0);
931 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
934 * Wait for the read to occur.
937 for (i = 0 ; i < 10 ; i++) {
939 * First, we want to wait for a short time.
944 * Now, check to see if the read has completed.
945 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
947 acctl = csa_readio(resp, BA0_ACCTL);
948 if ((acctl & ACCTL_DCV) == 0)
953 * Make sure the read completed.
955 if ((acctl & ACCTL_DCV) != 0)
959 * Wait for the valid status bit to go active.
962 for (i = 0 ; i < 10 ; i++) {
964 * Read the AC97 status register.
965 * ACSTS = Status Register = 464h
967 acsts = csa_readio(resp, BA0_ACSTS);
969 * See if we have valid status.
970 * VSTS - Valid Status
972 if ((acsts & ACSTS_VSTS) != 0)
975 * Wait for a short while.
981 * Make sure we got valid status.
983 if ((acsts & ACSTS_VSTS) == 0)
987 * Read the data returned from the AC97 register.
988 * ACSDA = Status Data Register = 474h
990 *data = csa_readio(resp, BA0_ACSDA);
996 csa_writecodec(csa_res *resp, u_long offset, u_int32_t data)
1002 * Setup the AC97 control registers on the CS461x to send the
1003 * appropriate command to the AC97 to perform the write.
1004 * ACCAD = Command Address Register = 46Ch
1005 * ACCDA = Command Data Register = 470h
1006 * ACCTL = Control Register = 460h
1007 * set DCV - will clear when process completed
1008 * set VFRM - valid frame enabled
1009 * set ESYN - ASYNC generation enabled
1010 * set RSTN - ARST# inactive, AC97 codec not reset
1014 * Get the actual AC97 register from the offset
1016 csa_writeio(resp, BA0_ACCAD, offset - BA0_AC97_RESET);
1017 csa_writeio(resp, BA0_ACCDA, data);
1018 csa_writeio(resp, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1021 * Wait for the write to occur.
1024 for (i = 0 ; i < 10 ; i++) {
1026 * First, we want to wait for a short time.
1031 * Now, check to see if the read has completed.
1032 * ACCTL = 460h, DCV should be reset by now and 460h = 17h
1034 acctl = csa_readio(resp, BA0_ACCTL);
1035 if ((acctl & ACCTL_DCV) == 0)
1040 * Make sure the write completed.
1042 if ((acctl & ACCTL_DCV) != 0)
1049 csa_readio(csa_res *resp, u_long offset)
1053 if (offset < BA0_AC97_RESET)
1054 return bus_space_read_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset) & 0xffffffff;
1056 if (csa_readcodec(resp, offset, &ul))
1063 csa_writeio(csa_res *resp, u_long offset, u_int32_t data)
1065 if (offset < BA0_AC97_RESET)
1066 bus_space_write_4(rman_get_bustag(resp->io), rman_get_bushandle(resp->io), offset, data);
1068 csa_writecodec(resp, offset, data);
1072 csa_readmem(csa_res *resp, u_long offset)
1074 return bus_space_read_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset);
1078 csa_writemem(csa_res *resp, u_long offset, u_int32_t data)
1080 bus_space_write_4(rman_get_bustag(resp->mem), rman_get_bushandle(resp->mem), offset, data);
1083 static device_method_t csa_methods[] = {
1084 /* Device interface */
1085 DEVMETHOD(device_probe, csa_probe),
1086 DEVMETHOD(device_attach, csa_attach),
1087 DEVMETHOD(device_detach, csa_detach),
1088 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1089 DEVMETHOD(device_suspend, bus_generic_suspend),
1090 DEVMETHOD(device_resume, csa_resume),
1093 DEVMETHOD(bus_alloc_resource, csa_alloc_resource),
1094 DEVMETHOD(bus_release_resource, csa_release_resource),
1095 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1096 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1097 DEVMETHOD(bus_setup_intr, csa_setup_intr),
1098 DEVMETHOD(bus_teardown_intr, csa_teardown_intr),
1103 static driver_t csa_driver = {
1106 sizeof(struct csa_softc),
1110 * csa can be attached to a pci bus.
1112 DRIVER_MODULE(snd_csa, pci, csa_driver, csa_devclass, 0, 0);
1113 MODULE_DEPEND(snd_csa, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1114 MODULE_VERSION(snd_csa, 1);