2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised
31 * that this driver still in its early stage, and possible of rewrite are
32 * pretty much guaranteed. There are supposedly several distinct parent/child
33 * busses to make this "perfect", but as for now and for the sake of
34 * simplicity, everything is gobble up within single source.
37 * 1) HDA Controller support
38 * 2) HDA Codecs support, which may include
41 * 3) Widget parser - the real magic of why this driver works on so
42 * many hardwares with minimal vendor specific quirk. The original
43 * parser was written using Ruby and can be found at
44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude
45 * ruby parser take the verbose dmesg dump as its input. Refer to
46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various
47 * interesting documents, especially UAA (Universal Audio Architecture).
48 * 4) Possible vendor specific support.
49 * (snd_hda_intel, snd_hda_ati, etc..)
51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the
52 * Compaq V3000 with Conexant HDA.
54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
56 * * This driver is a collaborative effort made by: *
58 * * Stephane E. Potvin <sepotvin@videotron.ca> *
59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> *
60 * * Wesley Morgan <morganw@chemikals.org> *
61 * * Daniel Eischen <deischen@FreeBSD.org> *
62 * * Maxime Guillaud <bsd-ports@mguillaud.net> *
63 * * Ariff Abdullah <ariff@FreeBSD.org> *
64 * * Alexander Motin <mav@FreeBSD.org> *
66 * * ....and various people from freebsd-multimedia@FreeBSD.org *
68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
75 #include <dev/sound/pcm/sound.h>
76 #include <dev/pci/pcireg.h>
77 #include <dev/pci/pcivar.h>
79 #include <sys/ctype.h>
80 #include <sys/taskqueue.h>
82 #include <dev/sound/pci/hda/hdac_private.h>
83 #include <dev/sound/pci/hda/hdac_reg.h>
84 #include <dev/sound/pci/hda/hda_reg.h>
85 #include <dev/sound/pci/hda/hdac.h>
89 #define HDA_DRV_TEST_REV "20100226_0142"
91 SND_DECLARE_FILE("$FreeBSD$");
93 #define HDA_BOOTVERBOSE(stmt) do { \
94 if (bootverbose != 0 || snd_verbose > 3) { \
99 #define HDA_BOOTHVERBOSE(stmt) do { \
100 if (snd_verbose > 3) { \
106 #undef HDAC_INTR_EXTRA
107 #define HDAC_INTR_EXTRA 1
110 #define hdac_lock(sc) snd_mtxlock((sc)->lock)
111 #define hdac_unlock(sc) snd_mtxunlock((sc)->lock)
112 #define hdac_lockassert(sc) snd_mtxassert((sc)->lock)
113 #define hdac_lockowned(sc) mtx_owned((sc)->lock)
115 #define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v))
116 #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \
117 (fl) == 0xffffffff || \
118 (((fl) & 0xffff0000) == 0xffff0000 && \
119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \
120 (((fl) & 0x0000ffff) == 0x0000ffff && \
121 ((fl) & 0xffff0000) == ((v) & 0xffff0000)))
122 #define HDA_MATCH_ALL 0xffffffff
123 #define HDAC_INVALID 0xffffffff
125 /* Default controller / jack sense poll: 250ms */
126 #define HDAC_POLL_INTERVAL max(hz >> 2, 1)
129 * Make room for possible 4096 playback/record channels, in 100 years to come.
131 #define HDAC_TRIGGER_NONE 0x00000000
132 #define HDAC_TRIGGER_PLAY 0x00000fff
133 #define HDAC_TRIGGER_REC 0x00fff000
134 #define HDAC_TRIGGER_UNSOL 0x80000000
136 #define HDA_MODEL_CONSTRUCT(vendor, model) \
137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))
139 /* Controller models */
142 #define INTEL_VENDORID 0x8086
143 #define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)
144 #define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)
145 #define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20)
146 #define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668)
147 #define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a)
148 #define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)
149 #define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b)
150 #define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e)
151 #define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)
152 #define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)
153 #define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)
154 #define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)
155 #define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b)
156 #define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff)
159 #define NVIDIA_VENDORID 0x10de
160 #define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)
161 #define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)
162 #define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)
163 #define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)
164 #define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)
165 #define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)
166 #define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)
167 #define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)
168 #define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)
169 #define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)
170 #define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)
171 #define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)
172 #define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)
173 #define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)
174 #define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)
175 #define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)
176 #define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)
177 #define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)
178 #define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)
179 #define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95)
180 #define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)
181 #define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)
182 #define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)
185 #define ATI_VENDORID 0x1002
186 #define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b)
187 #define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383)
188 #define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b)
189 #define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919)
190 #define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f)
191 #define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00)
192 #define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08)
193 #define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10)
194 #define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18)
195 #define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20)
196 #define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28)
197 #define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30)
198 #define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38)
199 #define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40)
200 #define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48)
201 #define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff)
204 #define RDC_VENDORID 0x17f3
205 #define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010)
208 #define VIA_VENDORID 0x1106
209 #define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288)
210 #define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff)
213 #define SIS_VENDORID 0x1039
214 #define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502)
215 #define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff)
218 #define ULI_VENDORID 0x10b9
219 #define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461)
220 #define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff)
225 #define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600)
228 #define HP_VENDORID 0x103c
229 #define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5)
230 #define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2)
231 #define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa)
232 #define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0)
233 #define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013)
234 #define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010)
235 #define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5)
236 #define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801)
237 #define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802)
238 #define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff)
239 /* What is wrong with XN 2563 anyway? (Got the picture ?) */
240 #define HP_NX6325_SUBVENDORX 0x103c30b0
243 #define DELL_VENDORID 0x1028
244 #define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9)
245 #define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc)
246 #define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227)
247 #define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228)
248 #define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9)
249 #define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7)
250 #define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da)
251 #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff)
254 #define CLEVO_VENDORID 0x1558
255 #define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)
256 #define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)
259 #define ACER_VENDORID 0x1025
260 #define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f)
261 #define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127)
262 #define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f)
263 #define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133)
264 #define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110)
265 #define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b)
266 #define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f)
267 #define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff)
270 #define ASUS_VENDORID 0x1043
271 #define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153)
272 #define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
273 #define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263)
274 #define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323)
275 #define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338)
276 #define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339)
277 #define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)
278 #define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971)
279 #define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993)
280 #define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f)
281 #define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
282 #define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)
283 #define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)
284 #define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)
285 #define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234)
286 #define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)
287 #define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff)
290 #define IBM_VENDORID 0x1014
291 #define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6)
292 #define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff)
295 #define LENOVO_VENDORID 0x17aa
296 #define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)
297 #define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)
298 #define LENOVO_B450_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x3a0d)
299 #define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)
300 #define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)
303 #define SAMSUNG_VENDORID 0x144d
304 #define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)
305 #define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)
308 #define MEDION_VENDORID 0x161f
309 #define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d)
310 #define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff)
312 /* Apple Computer Inc. */
313 #define APPLE_VENDORID 0x106b
314 #define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)
317 #define SONY_VENDORID 0x104d
318 #define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc)
319 #define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff)
322 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id
323 * instead of their own, which is beyond my comprehension
324 * (see HDA_CODEC_STAC9221 below).
326 #define APPLE_INTEL_MAC 0x76808384
327 #define APPLE_MACBOOKPRO55 0xcb7910de
330 #define LG_VENDORID 0x1854
331 #define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018)
332 #define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff)
334 /* Fujitsu Siemens */
335 #define FS_VENDORID 0x1734
336 #define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8)
337 #define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd)
338 #define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff)
340 /* Fujitsu Limited */
341 #define FL_VENDORID 0x10cf
342 #define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326)
343 #define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d)
344 #define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff)
347 #define TOSHIBA_VENDORID 0x1179
348 #define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)
349 #define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)
350 #define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)
352 /* Micro-Star International (MSI) */
353 #define MSI_VENDORID 0x1462
354 #define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349)
355 #define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a)
356 #define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff)
358 /* Giga-Byte Technology */
359 #define GB_VENDORID 0x1458
360 #define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022)
361 #define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff)
364 #define UNIWILL_VENDORID 0x1584
365 #define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)
366 #define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)
369 /* Misc constants.. */
370 #define HDA_AMP_VOL_DEFAULT (-1)
371 #define HDA_AMP_MUTE_DEFAULT (0xffffffff)
372 #define HDA_AMP_MUTE_NONE (0)
373 #define HDA_AMP_MUTE_LEFT (1 << 0)
374 #define HDA_AMP_MUTE_RIGHT (1 << 1)
375 #define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT)
377 #define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT))
378 #define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1)
380 #define HDA_ADC_MONITOR (1 << 0)
382 #define HDA_CTL_OUT 1
385 #define HDA_GPIO_MAX 8
386 /* 0 - 7 = GPIO , 8 = Flush */
387 #define HDA_QUIRK_GPIO0 (1 << 0)
388 #define HDA_QUIRK_GPIO1 (1 << 1)
389 #define HDA_QUIRK_GPIO2 (1 << 2)
390 #define HDA_QUIRK_GPIO3 (1 << 3)
391 #define HDA_QUIRK_GPIO4 (1 << 4)
392 #define HDA_QUIRK_GPIO5 (1 << 5)
393 #define HDA_QUIRK_GPIO6 (1 << 6)
394 #define HDA_QUIRK_GPIO7 (1 << 7)
395 #define HDA_QUIRK_GPIOFLUSH (1 << 8)
397 /* 9 - 25 = anything else */
398 #define HDA_QUIRK_SOFTPCMVOL (1 << 9)
399 #define HDA_QUIRK_FIXEDRATE (1 << 10)
400 #define HDA_QUIRK_FORCESTEREO (1 << 11)
401 #define HDA_QUIRK_EAPDINV (1 << 12)
402 #define HDA_QUIRK_DMAPOS (1 << 13)
403 #define HDA_QUIRK_SENSEINV (1 << 14)
405 /* 26 - 31 = vrefs */
406 #define HDA_QUIRK_IVREF50 (1 << 26)
407 #define HDA_QUIRK_IVREF80 (1 << 27)
408 #define HDA_QUIRK_IVREF100 (1 << 28)
409 #define HDA_QUIRK_OVREF50 (1 << 29)
410 #define HDA_QUIRK_OVREF80 (1 << 30)
411 #define HDA_QUIRK_OVREF100 (1 << 31)
413 #define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \
415 #define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \
417 #define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF)
419 #if __FreeBSD_version < 600000
420 #define taskqueue_drain(...)
423 static const struct {
426 } hdac_quirks_tab[] = {
427 { "gpio0", HDA_QUIRK_GPIO0 },
428 { "gpio1", HDA_QUIRK_GPIO1 },
429 { "gpio2", HDA_QUIRK_GPIO2 },
430 { "gpio3", HDA_QUIRK_GPIO3 },
431 { "gpio4", HDA_QUIRK_GPIO4 },
432 { "gpio5", HDA_QUIRK_GPIO5 },
433 { "gpio6", HDA_QUIRK_GPIO6 },
434 { "gpio7", HDA_QUIRK_GPIO7 },
435 { "gpioflush", HDA_QUIRK_GPIOFLUSH },
436 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL },
437 { "fixedrate", HDA_QUIRK_FIXEDRATE },
438 { "forcestereo", HDA_QUIRK_FORCESTEREO },
439 { "eapdinv", HDA_QUIRK_EAPDINV },
440 { "dmapos", HDA_QUIRK_DMAPOS },
441 { "senseinv", HDA_QUIRK_SENSEINV },
442 { "ivref50", HDA_QUIRK_IVREF50 },
443 { "ivref80", HDA_QUIRK_IVREF80 },
444 { "ivref100", HDA_QUIRK_IVREF100 },
445 { "ovref50", HDA_QUIRK_OVREF50 },
446 { "ovref80", HDA_QUIRK_OVREF80 },
447 { "ovref100", HDA_QUIRK_OVREF100 },
448 { "ivref", HDA_QUIRK_IVREF },
449 { "ovref", HDA_QUIRK_OVREF },
450 { "vref", HDA_QUIRK_VREF },
452 #define HDAC_QUIRKS_TAB_LEN \
453 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0]))
455 #define HDA_BDL_MIN 2
456 #define HDA_BDL_MAX 256
457 #define HDA_BDL_DEFAULT HDA_BDL_MIN
459 #define HDA_BLK_MIN HDAC_DMA_ALIGNMENT
460 #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))
462 #define HDA_BUFSZ_MIN 4096
463 #define HDA_BUFSZ_MAX 65536
464 #define HDA_BUFSZ_DEFAULT 16384
466 #define HDA_PARSE_MAXDEPTH 10
468 #define HDAC_UNSOLTAG_EVENT_HP 0x00
470 MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller");
472 const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red",
473 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D",
476 const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD",
477 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in",
478 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"};
480 const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"};
483 static uint32_t hdac_fmt[] = {
484 SND_FORMAT(AFMT_S16_LE, 2, 0),
488 static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0};
490 #define HDAC_NO_MSI 1
491 #define HDAC_NO_64BIT 2
493 static const struct {
498 { HDA_INTEL_CPT, "Intel Cougar Point", 0 },
499 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0 },
500 { HDA_INTEL_PPT1, "Intel Panther Point", 0 },
501 { HDA_INTEL_82801F, "Intel 82801F", 0 },
502 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 },
503 { HDA_INTEL_82801G, "Intel 82801G", 0 },
504 { HDA_INTEL_82801H, "Intel 82801H", 0 },
505 { HDA_INTEL_82801I, "Intel 82801I", 0 },
506 { HDA_INTEL_82801JI, "Intel 82801JI", 0 },
507 { HDA_INTEL_82801JD, "Intel 82801JD", 0 },
508 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0 },
509 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0 },
510 { HDA_INTEL_SCH, "Intel SCH", 0 },
511 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI },
512 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI },
513 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 },
514 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 },
515 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 },
516 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 },
517 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 },
518 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 },
519 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 },
520 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 },
521 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT },
522 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT },
523 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT },
524 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT },
525 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 },
526 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 },
527 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 },
528 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 },
529 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 },
530 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 },
531 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 },
532 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 },
533 { HDA_ATI_SB450, "ATI SB450", 0 },
534 { HDA_ATI_SB600, "ATI SB600", 0 },
535 { HDA_ATI_RS600, "ATI RS600", 0 },
536 { HDA_ATI_RS690, "ATI RS690", 0 },
537 { HDA_ATI_RS780, "ATI RS780", 0 },
538 { HDA_ATI_R600, "ATI R600", 0 },
539 { HDA_ATI_RV610, "ATI RV610", 0 },
540 { HDA_ATI_RV620, "ATI RV620", 0 },
541 { HDA_ATI_RV630, "ATI RV630", 0 },
542 { HDA_ATI_RV635, "ATI RV635", 0 },
543 { HDA_ATI_RV710, "ATI RV710", 0 },
544 { HDA_ATI_RV730, "ATI RV730", 0 },
545 { HDA_ATI_RV740, "ATI RV740", 0 },
546 { HDA_ATI_RV770, "ATI RV770", 0 },
547 { HDA_RDC_M3010, "RDC M3010", 0 },
548 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 },
549 { HDA_SIS_966, "SiS 966", 0 },
550 { HDA_ULI_M5461, "ULI M5461", 0 },
552 { HDA_INTEL_ALL, "Intel (Unknown)" },
553 { HDA_NVIDIA_ALL, "NVidia (Unknown)" },
554 { HDA_ATI_ALL, "ATI (Unknown)" },
555 { HDA_VIA_ALL, "VIA (Unknown)" },
556 { HDA_SIS_ALL, "SiS (Unknown)" },
557 { HDA_ULI_ALL, "ULI (Unknown)" },
559 #define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0]))
561 static const struct {
566 } hdac_pcie_snoop[] = {
567 { INTEL_VENDORID, 0x00, 0x00, 0x00 },
568 { ATI_VENDORID, 0x42, 0xf8, 0x02 },
569 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
571 #define HDAC_PCIESNOOP_LEN \
572 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0]))
574 static const struct {
581 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */
582 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */
583 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */
584 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */
585 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */
586 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */
587 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */
588 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */
589 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */
590 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */
591 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */
592 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */
593 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */
594 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */
595 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */
596 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */
597 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */
598 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */
599 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */
600 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */
601 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */
602 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */
603 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */
604 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */
605 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */
606 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */
607 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */
608 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */
609 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */
610 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */
611 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */
612 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */
613 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */
614 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */
615 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */
617 #define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0]))
619 /* All codecs you can eat... */
620 #define HDA_CODEC_CONSTRUCT(vendor, id) \
621 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))
624 #define CIRRUSLOGIC_VENDORID 0x1013
625 #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206)
626 #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207)
627 #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff)
630 #define REALTEK_VENDORID 0x10ec
631 #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)
632 #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)
633 #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)
634 #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)
635 #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)
636 #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270)
637 #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)
638 #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273)
639 #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275)
640 #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)
641 #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)
642 #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)
643 #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665)
644 #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)
645 #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)
646 #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)
647 #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)
648 #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)
649 #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)
650 #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887)
651 #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)
652 #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)
653 #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892)
654 #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)
657 #define ANALOGDEVICES_VENDORID 0x11d4
658 #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)
659 #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)
660 #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)
661 #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)
662 #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)
663 #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)
664 #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)
665 #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)
666 #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)
667 #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)
668 #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)
669 #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)
670 #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)
671 #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)
672 #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)
673 #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)
676 #define CMEDIA_VENDORID 0x434d
677 #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980)
678 #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)
681 #define SIGMATEL_VENDORID 0x8384
682 #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)
683 #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)
684 #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)
685 #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)
686 #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)
687 #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)
688 #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)
689 #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)
690 #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)
691 #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)
692 #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)
693 #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)
694 #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)
695 #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)
696 #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)
697 #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)
698 #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)
699 #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)
700 #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)
701 #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)
702 #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)
703 #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)
704 #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)
705 #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)
706 #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661)
707 #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)
708 #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664)
709 #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)
710 #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)
711 #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)
712 #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)
713 #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)
714 #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)
715 #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)
716 #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)
717 #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)
718 #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)
719 #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)
720 #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)
721 #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)
722 #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)
723 #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)
726 #define IDT_VENDORID 0x111d
727 #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)
728 #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)
729 #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)
730 #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)
731 #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)
732 #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)
733 #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)
734 #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)
735 #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)
736 #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)
737 #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)
738 #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)
739 #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)
742 #define SII_VENDORID 0x1095
743 #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)
744 #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)
745 #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)
748 #define AGERE_VENDORID 0x11c1
749 #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)
752 #define CONEXANT_VENDORID 0x14f1
753 #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)
754 #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)
755 #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)
756 #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066)
757 #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067)
758 #define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068)
759 #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069)
760 #define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e)
761 #define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097)
762 #define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098)
763 #define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1)
764 #define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2)
765 #define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab)
766 #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac)
767 #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8)
768 #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)
769 #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)
772 #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)
773 #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)
774 #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)
775 #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)
776 #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)
777 #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)
778 #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)
779 #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)
780 #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)
781 #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)
782 #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)
783 #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)
784 #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)
785 #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)
786 #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)
787 #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)
788 #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)
789 #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)
790 #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)
791 #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)
792 #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)
793 #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)
794 #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)
795 #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)
796 #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)
797 #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)
798 #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)
799 #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)
800 #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)
801 #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)
802 #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)
803 #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)
804 #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)
805 #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)
806 #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)
807 #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)
808 #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433)
809 #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721)
810 #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428)
811 #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428)
812 #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448)
813 #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440)
814 #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441)
815 #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438)
816 #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438)
817 #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441)
818 #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)
821 #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)
822 #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)
823 #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)
824 #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)
825 #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)
828 #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)
829 #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)
830 #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)
831 #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a)
832 #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b)
833 #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c)
834 #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d)
835 #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)
836 #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)
837 #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)
840 #define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054)
841 #define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801)
842 #define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802)
843 #define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803)
844 #define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804)
845 #define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805)
846 #define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)
847 #define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff)
850 static const struct {
854 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" },
855 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" },
856 { HDA_CODEC_ALC260, "Realtek ALC260" },
857 { HDA_CODEC_ALC262, "Realtek ALC262" },
858 { HDA_CODEC_ALC267, "Realtek ALC267" },
859 { HDA_CODEC_ALC268, "Realtek ALC268" },
860 { HDA_CODEC_ALC269, "Realtek ALC269" },
861 { HDA_CODEC_ALC270, "Realtek ALC270" },
862 { HDA_CODEC_ALC272, "Realtek ALC272" },
863 { HDA_CODEC_ALC273, "Realtek ALC273" },
864 { HDA_CODEC_ALC275, "Realtek ALC275" },
865 { HDA_CODEC_ALC660, "Realtek ALC660" },
866 { HDA_CODEC_ALC662, "Realtek ALC662" },
867 { HDA_CODEC_ALC663, "Realtek ALC663" },
868 { HDA_CODEC_ALC665, "Realtek ALC665" },
869 { HDA_CODEC_ALC861, "Realtek ALC861" },
870 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" },
871 { HDA_CODEC_ALC880, "Realtek ALC880" },
872 { HDA_CODEC_ALC882, "Realtek ALC882" },
873 { HDA_CODEC_ALC883, "Realtek ALC883" },
874 { HDA_CODEC_ALC885, "Realtek ALC885" },
875 { HDA_CODEC_ALC887, "Realtek ALC887" },
876 { HDA_CODEC_ALC888, "Realtek ALC888" },
877 { HDA_CODEC_ALC889, "Realtek ALC889" },
878 { HDA_CODEC_ALC892, "Realtek ALC892" },
879 { HDA_CODEC_AD1882, "Analog Devices AD1882" },
880 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" },
881 { HDA_CODEC_AD1883, "Analog Devices AD1883" },
882 { HDA_CODEC_AD1884, "Analog Devices AD1884" },
883 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" },
884 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" },
885 { HDA_CODEC_AD1983, "Analog Devices AD1983" },
886 { HDA_CODEC_AD1984, "Analog Devices AD1984" },
887 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" },
888 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" },
889 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" },
890 { HDA_CODEC_AD1987, "Analog Devices AD1987" },
891 { HDA_CODEC_AD1988, "Analog Devices AD1988A" },
892 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" },
893 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" },
894 { HDA_CODEC_CMI9880, "CMedia CMI9880" },
895 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" },
896 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" },
897 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" },
898 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" },
899 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" },
900 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" },
901 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" },
902 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" },
903 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" },
904 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" },
905 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" },
906 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" },
907 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" },
908 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" },
909 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" },
910 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" },
911 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" },
912 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" },
913 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" },
914 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" },
915 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" },
916 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" },
917 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" },
918 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" },
919 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" },
920 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" },
921 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" },
922 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" },
923 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" },
924 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" },
925 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" },
926 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" },
927 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" },
928 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" },
929 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" },
930 { HDA_CODEC_IDT92HD005, "IDT 92HD005" },
931 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" },
932 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" },
933 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" },
934 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" },
935 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" },
936 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" },
937 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" },
938 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" },
939 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" },
940 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" },
941 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" },
942 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" },
943 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" },
944 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" },
945 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" },
946 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" },
947 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" },
948 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" },
949 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" },
950 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" },
951 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" },
952 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" },
953 { HDA_CODEC_CX20584, "Conexant CX20584" },
954 { HDA_CODEC_CX20585, "Conexant CX20585" },
955 { HDA_CODEC_CX20590, "Conexant CX20590" },
956 { HDA_CODEC_CX20631, "Conexant CX20631" },
957 { HDA_CODEC_CX20632, "Conexant CX20632" },
958 { HDA_CODEC_CX20641, "Conexant CX20641" },
959 { HDA_CODEC_CX20642, "Conexant CX20642" },
960 { HDA_CODEC_CX20651, "Conexant CX20651" },
961 { HDA_CODEC_CX20652, "Conexant CX20652" },
962 { HDA_CODEC_CX20664, "Conexant CX20664" },
963 { HDA_CODEC_CX20665, "Conexant CX20665" },
964 { HDA_CODEC_VT1708_8, "VIA VT1708_8" },
965 { HDA_CODEC_VT1708_9, "VIA VT1708_9" },
966 { HDA_CODEC_VT1708_A, "VIA VT1708_A" },
967 { HDA_CODEC_VT1708_B, "VIA VT1708_B" },
968 { HDA_CODEC_VT1709_0, "VIA VT1709_0" },
969 { HDA_CODEC_VT1709_1, "VIA VT1709_1" },
970 { HDA_CODEC_VT1709_2, "VIA VT1709_2" },
971 { HDA_CODEC_VT1709_3, "VIA VT1709_3" },
972 { HDA_CODEC_VT1709_4, "VIA VT1709_4" },
973 { HDA_CODEC_VT1709_5, "VIA VT1709_5" },
974 { HDA_CODEC_VT1709_6, "VIA VT1709_6" },
975 { HDA_CODEC_VT1709_7, "VIA VT1709_7" },
976 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" },
977 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" },
978 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" },
979 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" },
980 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" },
981 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" },
982 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" },
983 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" },
984 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" },
985 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" },
986 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" },
987 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" },
988 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" },
989 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" },
990 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" },
991 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" },
992 { HDA_CODEC_VT1702_0, "VIA VT1702_0" },
993 { HDA_CODEC_VT1702_1, "VIA VT1702_1" },
994 { HDA_CODEC_VT1702_2, "VIA VT1702_2" },
995 { HDA_CODEC_VT1702_3, "VIA VT1702_3" },
996 { HDA_CODEC_VT1702_4, "VIA VT1702_4" },
997 { HDA_CODEC_VT1702_5, "VIA VT1702_5" },
998 { HDA_CODEC_VT1702_6, "VIA VT1702_6" },
999 { HDA_CODEC_VT1702_7, "VIA VT1702_7" },
1000 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" },
1001 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" },
1002 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" },
1003 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" },
1004 { HDA_CODEC_VT1812, "VIA VT1812" },
1005 { HDA_CODEC_VT1818S, "VIA VT1818S" },
1006 { HDA_CODEC_VT1828S, "VIA VT1828S" },
1007 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" },
1008 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" },
1009 { HDA_CODEC_VT2020, "VIA VT2020" },
1010 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" },
1011 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" },
1012 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" },
1013 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" },
1014 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" },
1015 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" },
1016 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" },
1017 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" },
1018 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" },
1019 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" },
1020 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" },
1021 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" },
1022 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" },
1023 { HDA_CODEC_INTELIP, "Intel Ibex Peak HDMI" },
1024 { HDA_CODEC_INTELBL, "Intel Bearlake HDMI" },
1025 { HDA_CODEC_INTELCA, "Intel Cantiga HDMI" },
1026 { HDA_CODEC_INTELEL, "Intel Eaglelake HDMI" },
1027 { HDA_CODEC_INTELIP2, "Intel Ibex Peak HDMI" },
1028 { HDA_CODEC_INTELCPT, "Intel Cougar Point HDMI" },
1029 { HDA_CODEC_INTELCL, "Intel Crestline HDMI" },
1030 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" },
1031 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" },
1033 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" },
1034 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" },
1035 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" },
1036 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" },
1037 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" },
1038 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" },
1039 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" },
1040 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" },
1041 { HDA_CODEC_VTXXXX, "VIA (Unknown)" },
1042 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" },
1043 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" },
1044 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" },
1045 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" },
1047 #define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0]))
1050 /****************************************************************************
1051 * Function prototypes
1052 ****************************************************************************/
1053 static void hdac_intr_handler(void *);
1054 static int hdac_reset(struct hdac_softc *, int);
1055 static int hdac_get_capabilities(struct hdac_softc *);
1056 static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
1057 static int hdac_dma_alloc(struct hdac_softc *,
1058 struct hdac_dma *, bus_size_t);
1059 static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
1060 static int hdac_mem_alloc(struct hdac_softc *);
1061 static void hdac_mem_free(struct hdac_softc *);
1062 static int hdac_irq_alloc(struct hdac_softc *);
1063 static void hdac_irq_free(struct hdac_softc *);
1064 static void hdac_corb_init(struct hdac_softc *);
1065 static void hdac_rirb_init(struct hdac_softc *);
1066 static void hdac_corb_start(struct hdac_softc *);
1067 static void hdac_rirb_start(struct hdac_softc *);
1068 static void hdac_scan_codecs(struct hdac_softc *);
1069 static void hdac_probe_codec(struct hdac_codec *);
1070 static void hdac_probe_function(struct hdac_codec *, nid_t);
1071 static int hdac_pcmchannel_setup(struct hdac_chan *);
1073 static void hdac_attach2(void *);
1075 static uint32_t hdac_command_sendone_internal(struct hdac_softc *,
1077 static void hdac_command_send_internal(struct hdac_softc *,
1078 struct hdac_command_list *, int);
1080 static int hdac_probe(device_t);
1081 static int hdac_attach(device_t);
1082 static int hdac_detach(device_t);
1083 static int hdac_suspend(device_t);
1084 static int hdac_resume(device_t);
1085 static void hdac_widget_connection_select(struct hdac_widget *, uint8_t);
1086 static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *,
1087 uint32_t, int, int);
1088 static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *,
1089 nid_t, int, int, int);
1090 static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *,
1091 nid_t, nid_t, int, int, int, int, int, int);
1092 static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t);
1094 static int hdac_rirb_flush(struct hdac_softc *sc);
1095 static int hdac_unsolq_flush(struct hdac_softc *sc);
1097 static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf);
1099 #define hdac_command(a1, a2, a3) \
1100 hdac_command_sendone_internal(a1, a2, a3)
1102 #define hdac_codec_id(c) \
1103 ((uint32_t)((c == NULL) ? 0x00000000 : \
1104 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \
1105 ((uint32_t)(c)->device_id & 0x0000ffff))))
1108 hdac_codec_name(struct hdac_codec *codec)
1113 id = hdac_codec_id(codec);
1115 for (i = 0; i < HDAC_CODECS_LEN; i++) {
1116 if (HDA_DEV_MATCH(hdac_codecs[i].id, id))
1117 return (hdac_codecs[i].name);
1120 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec");
1124 hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len)
1126 static char *ossname[] = SOUND_DEVICE_NAMES;
1130 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1131 if (mask & (1 << i)) {
1133 strlcat(buf, ", ", len);
1134 strlcat(buf, ossname[i], len);
1141 static struct hdac_audio_ctl *
1142 hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index)
1144 if (devinfo == NULL ||
1145 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO ||
1146 index == NULL || devinfo->function.audio.ctl == NULL ||
1147 devinfo->function.audio.ctlcnt < 1 ||
1148 *index < 0 || *index >= devinfo->function.audio.ctlcnt)
1150 return (&devinfo->function.audio.ctl[(*index)++]);
1153 static struct hdac_audio_ctl *
1154 hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir,
1157 struct hdac_audio_ctl *ctl;
1160 if (devinfo == NULL || devinfo->function.audio.ctl == NULL)
1164 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
1165 if (ctl->enable == 0)
1167 if (ctl->widget->nid != nid)
1169 if (dir && ctl->ndir != dir)
1171 if (index >= 0 && ctl->ndir == HDA_CTL_IN &&
1172 ctl->dir == ctl->ndir && ctl->index != index)
1175 if (found == cnt || cnt <= 0)
1183 * Jack detection (Speaker/HP redirection) event handler.
1186 hdac_hp_switch_handler(struct hdac_devinfo *devinfo)
1188 struct hdac_audio_as *as;
1189 struct hdac_softc *sc;
1190 struct hdac_widget *w;
1191 struct hdac_audio_ctl *ctl;
1196 if (devinfo == NULL || devinfo->codec == NULL ||
1197 devinfo->codec->sc == NULL)
1200 sc = devinfo->codec->sc;
1201 cad = devinfo->codec->cad;
1202 as = devinfo->function.audio.as;
1203 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1204 if (as[i].hpredir < 0)
1207 w = hdac_widget_get(devinfo, as[i].pins[15]);
1208 if (w == NULL || w->enable == 0 || w->type !=
1209 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1212 res = hdac_command(sc,
1213 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad);
1216 device_printf(sc->dev,
1217 "Pin sense: nid=%d res=0x%08x\n",
1218 as[i].pins[15], res);
1221 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res);
1222 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV)
1225 /* (Un)Mute headphone pin. */
1226 ctl = hdac_audio_ctl_amp_get(devinfo,
1227 as[i].pins[15], HDA_CTL_IN, -1, 1);
1228 if (ctl != NULL && ctl->mute) {
1229 /* If pin has muter - use it. */
1230 val = (res != 0) ? 0 : 1;
1231 if (val != ctl->forcemute) {
1232 ctl->forcemute = val;
1233 hdac_audio_ctl_amp_set(ctl,
1234 HDA_AMP_MUTE_DEFAULT,
1235 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1238 /* If there is no muter - disable pin output. */
1239 w = hdac_widget_get(devinfo, as[i].pins[15]);
1240 if (w != NULL && w->type ==
1241 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1243 val = w->wclass.pin.ctrl |
1244 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1246 val = w->wclass.pin.ctrl &
1247 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1248 if (val != w->wclass.pin.ctrl) {
1249 w->wclass.pin.ctrl = val;
1251 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1252 w->nid, w->wclass.pin.ctrl), cad);
1256 /* (Un)Mute other pins. */
1257 for (j = 0; j < 15; j++) {
1258 if (as[i].pins[j] <= 0)
1260 ctl = hdac_audio_ctl_amp_get(devinfo,
1261 as[i].pins[j], HDA_CTL_IN, -1, 1);
1262 if (ctl != NULL && ctl->mute) {
1263 /* If pin has muter - use it. */
1264 val = (res != 0) ? 1 : 0;
1265 if (val == ctl->forcemute)
1267 ctl->forcemute = val;
1268 hdac_audio_ctl_amp_set(ctl,
1269 HDA_AMP_MUTE_DEFAULT,
1270 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
1273 /* If there is no muter - disable pin output. */
1274 w = hdac_widget_get(devinfo, as[i].pins[j]);
1275 if (w != NULL && w->type ==
1276 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
1278 val = w->wclass.pin.ctrl &
1279 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1281 val = w->wclass.pin.ctrl |
1282 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
1283 if (val != w->wclass.pin.ctrl) {
1284 w->wclass.pin.ctrl = val;
1286 HDA_CMD_SET_PIN_WIDGET_CTRL(cad,
1287 w->nid, w->wclass.pin.ctrl), cad);
1295 * Callback for poll based jack detection.
1298 hdac_jack_poll_callback(void *arg)
1300 struct hdac_devinfo *devinfo = arg;
1301 struct hdac_softc *sc;
1303 if (devinfo == NULL || devinfo->codec == NULL ||
1304 devinfo->codec->sc == NULL)
1306 sc = devinfo->codec->sc;
1308 if (sc->poll_ival == 0) {
1312 hdac_hp_switch_handler(devinfo);
1313 callout_reset(&sc->poll_jack, sc->poll_ival,
1314 hdac_jack_poll_callback, devinfo);
1319 * Jack detection initializer.
1322 hdac_hp_switch_init(struct hdac_devinfo *devinfo)
1324 struct hdac_softc *sc = devinfo->codec->sc;
1325 struct hdac_audio_as *as = devinfo->function.audio.as;
1326 struct hdac_widget *w;
1328 int i, enable = 0, poll = 0;
1331 id = hdac_codec_id(devinfo->codec);
1332 cad = devinfo->codec->cad;
1333 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
1334 if (as[i].hpredir < 0)
1337 w = hdac_widget_get(devinfo, as[i].pins[15]);
1338 if (w == NULL || w->enable == 0 || w->type !=
1339 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
1341 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 ||
1342 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) {
1343 device_printf(sc->dev,
1344 "No jack detection support at pin %d\n",
1349 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) {
1351 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid,
1352 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE |
1353 HDAC_UNSOLTAG_EVENT_HP), cad);
1357 device_printf(sc->dev,
1358 "Enabling headphone/speaker "
1359 "audio routing switching:\n");
1360 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n",
1361 i, w->nid, (poll != 0) ? "POLL" : "UNSOL");
1365 hdac_hp_switch_handler(devinfo);
1367 callout_reset(&sc->poll_jack, 1,
1368 hdac_jack_poll_callback, devinfo);
1374 * Unsolicited messages handler.
1377 hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag)
1379 struct hdac_softc *sc;
1380 struct hdac_devinfo *devinfo = NULL;
1383 if (codec == NULL || codec->sc == NULL)
1389 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag);
1392 for (i = 0; i < codec->num_fgs; i++) {
1393 if (codec->fgs[i].node_type ==
1394 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
1395 devinfo = &codec->fgs[i];
1400 if (devinfo == NULL)
1404 case HDAC_UNSOLTAG_EVENT_HP:
1405 hdac_hp_switch_handler(devinfo);
1408 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag);
1414 hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch)
1416 /* XXX to be removed */
1417 #ifdef HDAC_INTR_EXTRA
1421 if (!(ch->flags & HDAC_CHN_RUNNING))
1424 /* XXX to be removed */
1425 #ifdef HDAC_INTR_EXTRA
1426 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS);
1429 /* XXX to be removed */
1430 #ifdef HDAC_INTR_EXTRA
1432 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE))
1433 device_printf(ch->pdevinfo->dev,
1434 "PCMDIR_%s intr triggered beyond stream boundary:"
1436 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res);
1440 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS,
1441 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
1443 /* XXX to be removed */
1444 #ifdef HDAC_INTR_EXTRA
1445 if (res & HDAC_SDSTS_BCIS) {
1448 /* XXX to be removed */
1449 #ifdef HDAC_INTR_EXTRA
1456 /****************************************************************************
1457 * void hdac_intr_handler(void *)
1459 * Interrupt handler. Processes interrupts received from the hdac.
1460 ****************************************************************************/
1462 hdac_intr_handler(void *context)
1464 struct hdac_softc *sc;
1467 struct hdac_rirb *rirb_base;
1471 sc = (struct hdac_softc *)context;
1474 if (sc->polling != 0) {
1479 /* Do we have anything to do? */
1480 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
1481 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) {
1488 /* Was this a controller interrupt? */
1489 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) {
1490 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
1491 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1492 /* Get as many responses that we can */
1493 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) {
1494 HDAC_WRITE_1(&sc->mem,
1495 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
1496 if (hdac_rirb_flush(sc) != 0)
1497 trigger |= HDAC_TRIGGER_UNSOL;
1498 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
1500 /* XXX to be removed */
1501 /* Clear interrupt and exit */
1502 #ifdef HDAC_INTR_EXTRA
1503 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS);
1507 if (intsts & HDAC_INTSTS_SIS_MASK) {
1508 for (i = 0; i < sc->num_chans; i++) {
1509 if ((intsts & (1 << (sc->chans[i].off >> 5))) &&
1510 hdac_stream_intr(sc, &sc->chans[i]) != 0)
1511 trigger |= (1 << i);
1513 /* XXX to be removed */
1514 #ifdef HDAC_INTR_EXTRA
1515 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts &
1516 HDAC_INTSTS_SIS_MASK);
1522 for (i = 0; i < sc->num_chans; i++) {
1523 if (trigger & (1 << i))
1524 chn_intr(sc->chans[i].c);
1526 if (trigger & HDAC_TRIGGER_UNSOL)
1527 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1530 /****************************************************************************
1531 * int hdac_reset(hdac_softc *, int)
1533 * Reset the hdac to a quiescent and known state.
1534 ****************************************************************************/
1536 hdac_reset(struct hdac_softc *sc, int wakeup)
1542 * Stop all Streams DMA engine
1544 for (i = 0; i < sc->num_iss; i++)
1545 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
1546 for (i = 0; i < sc->num_oss; i++)
1547 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
1548 for (i = 0; i < sc->num_bss; i++)
1549 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
1552 * Stop Control DMA engines.
1554 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
1555 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
1558 * Reset DMA position buffer.
1560 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
1561 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
1564 * Reset the controller. The reset must remain asserted for
1565 * a minimum of 100us.
1567 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1568 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
1571 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1572 if (!(gctl & HDAC_GCTL_CRST))
1576 if (gctl & HDAC_GCTL_CRST) {
1577 device_printf(sc->dev, "Unable to put hdac in reset\n");
1581 /* If wakeup is not requested - leave the controller in reset state. */
1586 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1587 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
1590 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
1591 if (gctl & HDAC_GCTL_CRST)
1595 if (!(gctl & HDAC_GCTL_CRST)) {
1596 device_printf(sc->dev, "Device stuck in reset\n");
1601 * Wait for codecs to finish their own reset sequence. The delay here
1602 * should be of 250us but for some reasons, on it's not enough on my
1603 * computer. Let's use twice as much as necessary to make sure that
1604 * it's reset properly.
1612 /****************************************************************************
1613 * int hdac_get_capabilities(struct hdac_softc *);
1615 * Retreive the general capabilities of the hdac;
1616 * Number of Input Streams
1617 * Number of Output Streams
1618 * Number of bidirectional Streams
1620 * CORB and RIRB sizes
1621 ****************************************************************************/
1623 hdac_get_capabilities(struct hdac_softc *sc)
1626 uint8_t corbsize, rirbsize;
1628 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
1629 sc->num_iss = HDAC_GCAP_ISS(gcap);
1630 sc->num_oss = HDAC_GCAP_OSS(gcap);
1631 sc->num_bss = HDAC_GCAP_BSS(gcap);
1632 sc->num_sdo = HDAC_GCAP_NSDO(gcap);
1633 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK);
1635 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
1636 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
1637 HDAC_CORBSIZE_CORBSZCAP_256)
1638 sc->corb_size = 256;
1639 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
1640 HDAC_CORBSIZE_CORBSZCAP_16)
1642 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
1643 HDAC_CORBSIZE_CORBSZCAP_2)
1646 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
1647 __func__, corbsize);
1651 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
1652 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
1653 HDAC_RIRBSIZE_RIRBSZCAP_256)
1654 sc->rirb_size = 256;
1655 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
1656 HDAC_RIRBSIZE_RIRBSZCAP_16)
1658 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
1659 HDAC_RIRBSIZE_RIRBSZCAP_2)
1662 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
1663 __func__, rirbsize);
1668 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
1669 "NSDO %d%s, CORB %d, RIRB %d\n",
1670 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
1671 sc->support_64bit ? ", 64bit" : "",
1672 sc->corb_size, sc->rirb_size);
1679 /****************************************************************************
1682 * This function is called by bus_dmamap_load when the mapping has been
1683 * established. We just record the physical address of the mapping into
1684 * the struct hdac_dma passed in.
1685 ****************************************************************************/
1687 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
1689 struct hdac_dma *dma;
1692 dma = (struct hdac_dma *)callback_arg;
1693 dma->dma_paddr = segs[0].ds_addr;
1698 /****************************************************************************
1699 * int hdac_dma_alloc
1701 * This function allocate and setup a dma region (struct hdac_dma).
1702 * It must be freed by a corresponding hdac_dma_free.
1703 ****************************************************************************/
1705 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
1710 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT);
1711 bzero(dma, sizeof(*dma));
1716 result = bus_dma_tag_create(
1717 bus_get_dma_tag(sc->dev), /* parent */
1718 HDAC_DMA_ALIGNMENT, /* alignment */
1720 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1721 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1722 BUS_SPACE_MAXADDR, /* highaddr */
1723 NULL, /* filtfunc */
1724 NULL, /* fistfuncarg */
1725 roundsz, /* maxsize */
1727 roundsz, /* maxsegsz */
1729 NULL, /* lockfunc */
1730 NULL, /* lockfuncarg */
1731 &dma->dma_tag); /* dmat */
1733 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
1735 goto hdac_dma_alloc_fail;
1739 * Allocate DMA memory
1741 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
1742 BUS_DMA_NOWAIT | BUS_DMA_ZERO |
1743 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
1746 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
1748 goto hdac_dma_alloc_fail;
1751 dma->dma_size = roundsz;
1756 result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
1757 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
1758 if (result != 0 || dma->dma_paddr == 0) {
1761 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
1763 goto hdac_dma_alloc_fail;
1767 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
1768 __func__, (uintmax_t)size, (uintmax_t)roundsz);
1773 hdac_dma_alloc_fail:
1774 hdac_dma_free(sc, dma);
1780 /****************************************************************************
1781 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
1783 * Free a struct dhac_dma that has been previously allocated via the
1784 * hdac_dma_alloc function.
1785 ****************************************************************************/
1787 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
1789 if (dma->dma_map != NULL) {
1792 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
1793 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1795 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1797 if (dma->dma_vaddr != NULL) {
1798 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1799 dma->dma_vaddr = NULL;
1801 dma->dma_map = NULL;
1802 if (dma->dma_tag != NULL) {
1803 bus_dma_tag_destroy(dma->dma_tag);
1804 dma->dma_tag = NULL;
1809 /****************************************************************************
1810 * int hdac_mem_alloc(struct hdac_softc *)
1812 * Allocate all the bus resources necessary to speak with the physical
1814 ****************************************************************************/
1816 hdac_mem_alloc(struct hdac_softc *sc)
1818 struct hdac_mem *mem;
1821 mem->mem_rid = PCIR_BAR(0);
1822 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1823 &mem->mem_rid, RF_ACTIVE);
1824 if (mem->mem_res == NULL) {
1825 device_printf(sc->dev,
1826 "%s: Unable to allocate memory resource\n", __func__);
1829 mem->mem_tag = rman_get_bustag(mem->mem_res);
1830 mem->mem_handle = rman_get_bushandle(mem->mem_res);
1835 /****************************************************************************
1836 * void hdac_mem_free(struct hdac_softc *)
1838 * Free up resources previously allocated by hdac_mem_alloc.
1839 ****************************************************************************/
1841 hdac_mem_free(struct hdac_softc *sc)
1843 struct hdac_mem *mem;
1846 if (mem->mem_res != NULL)
1847 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
1849 mem->mem_res = NULL;
1852 /****************************************************************************
1853 * int hdac_irq_alloc(struct hdac_softc *)
1855 * Allocate and setup the resources necessary for interrupt handling.
1856 ****************************************************************************/
1858 hdac_irq_alloc(struct hdac_softc *sc)
1860 struct hdac_irq *irq;
1866 if ((sc->flags & HDAC_F_MSI) &&
1867 (result = pci_msi_count(sc->dev)) == 1 &&
1868 pci_alloc_msi(sc->dev, &result) == 0)
1871 sc->flags &= ~HDAC_F_MSI;
1873 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
1874 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
1875 if (irq->irq_res == NULL) {
1876 device_printf(sc->dev, "%s: Unable to allocate irq\n",
1878 goto hdac_irq_alloc_fail;
1880 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
1881 NULL, hdac_intr_handler, sc, &irq->irq_handle);
1883 device_printf(sc->dev,
1884 "%s: Unable to setup interrupt handler (%x)\n",
1886 goto hdac_irq_alloc_fail;
1891 hdac_irq_alloc_fail:
1897 /****************************************************************************
1898 * void hdac_irq_free(struct hdac_softc *)
1900 * Free up resources previously allocated by hdac_irq_alloc.
1901 ****************************************************************************/
1903 hdac_irq_free(struct hdac_softc *sc)
1905 struct hdac_irq *irq;
1908 if (irq->irq_res != NULL && irq->irq_handle != NULL)
1909 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
1910 if (irq->irq_res != NULL)
1911 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
1913 if (irq->irq_rid == 0x1)
1914 pci_release_msi(sc->dev);
1915 irq->irq_handle = NULL;
1916 irq->irq_res = NULL;
1920 /****************************************************************************
1921 * void hdac_corb_init(struct hdac_softc *)
1923 * Initialize the corb registers for operations but do not start it up yet.
1924 * The CORB engine must not be running when this function is called.
1925 ****************************************************************************/
1927 hdac_corb_init(struct hdac_softc *sc)
1932 /* Setup the CORB size. */
1933 switch (sc->corb_size) {
1935 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
1938 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
1941 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
1944 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
1946 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
1948 /* Setup the CORB Address in the hdac */
1949 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
1950 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
1951 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
1953 /* Set the WP and RP */
1955 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
1956 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
1958 * The HDA specification indicates that the CORBRPRST bit will always
1959 * read as zero. Unfortunately, it seems that at least the 82801G
1960 * doesn't reset the bit to zero, which stalls the corb engine.
1961 * manually reset the bit to zero before continuing.
1963 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
1965 /* Enable CORB error reporting */
1967 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
1971 /****************************************************************************
1972 * void hdac_rirb_init(struct hdac_softc *)
1974 * Initialize the rirb registers for operations but do not start it up yet.
1975 * The RIRB engine must not be running when this function is called.
1976 ****************************************************************************/
1978 hdac_rirb_init(struct hdac_softc *sc)
1983 /* Setup the RIRB size. */
1984 switch (sc->rirb_size) {
1986 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
1989 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
1992 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
1995 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
1997 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
1999 /* Setup the RIRB Address in the hdac */
2000 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
2001 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
2002 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
2004 /* Setup the WP and RP */
2006 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
2008 /* Setup the interrupt threshold */
2009 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
2011 /* Enable Overrun and response received reporting */
2013 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
2014 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
2016 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
2021 * Make sure that the Host CPU cache doesn't contain any dirty
2022 * cache lines that falls in the rirb. If I understood correctly, it
2023 * should be sufficient to do this only once as the rirb is purely
2024 * read-only from now on.
2026 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2027 BUS_DMASYNC_PREREAD);
2031 /****************************************************************************
2032 * void hdac_corb_start(hdac_softc *)
2034 * Startup the corb DMA engine
2035 ****************************************************************************/
2037 hdac_corb_start(struct hdac_softc *sc)
2041 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
2042 corbctl |= HDAC_CORBCTL_CORBRUN;
2043 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
2046 /****************************************************************************
2047 * void hdac_rirb_start(hdac_softc *)
2049 * Startup the rirb DMA engine
2050 ****************************************************************************/
2052 hdac_rirb_start(struct hdac_softc *sc)
2056 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
2057 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
2058 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
2062 /****************************************************************************
2063 * void hdac_scan_codecs(struct hdac_softc *, int)
2065 * Scan the bus for available codecs, starting with num.
2066 ****************************************************************************/
2068 hdac_scan_codecs(struct hdac_softc *sc)
2070 struct hdac_codec *codec;
2074 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
2075 for (i = 0; i < HDAC_CODEC_MAX; i++) {
2076 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
2077 /* We have found a codec. */
2078 codec = (struct hdac_codec *)malloc(sizeof(*codec),
2079 M_HDAC, M_ZERO | M_NOWAIT);
2080 if (codec == NULL) {
2081 device_printf(sc->dev,
2082 "Unable to allocate memory for codec\n");
2085 codec->commands = NULL;
2086 codec->responses_received = 0;
2087 codec->verbs_sent = 0;
2090 sc->codecs[i] = codec;
2091 hdac_probe_codec(codec);
2094 /* All codecs have been probed, now try to attach drivers to them */
2095 /* bus_generic_attach(sc->dev); */
2098 /****************************************************************************
2099 * void hdac_probe_codec(struct hdac_softc *, int)
2101 * Probe a the given codec_id for available function groups.
2102 ****************************************************************************/
2104 hdac_probe_codec(struct hdac_codec *codec)
2106 struct hdac_softc *sc = codec->sc;
2107 uint32_t vendorid, revisionid, subnode;
2111 nid_t cad = codec->cad;
2114 device_printf(sc->dev, "Probing codec #%d...\n", cad);
2116 vendorid = hdac_command(sc,
2117 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID),
2119 revisionid = hdac_command(sc,
2120 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID),
2122 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
2123 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
2124 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
2125 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
2127 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) {
2128 device_printf(sc->dev, "Codec #%d is not responding!"
2129 " Probing aborted.\n", cad);
2133 device_printf(sc->dev, "HDA Codec #%d: %s\n",
2134 cad, hdac_codec_name(codec));
2136 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n",
2137 hdac_codec_id(codec));
2138 device_printf(sc->dev, " Vendor: 0x%04x\n",
2140 device_printf(sc->dev, " Device: 0x%04x\n",
2142 device_printf(sc->dev, " Revision: 0x%02x\n",
2143 codec->revision_id);
2144 device_printf(sc->dev, " Stepping: 0x%02x\n",
2145 codec->stepping_id);
2146 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n",
2149 subnode = hdac_command(sc,
2150 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT),
2152 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode);
2153 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode);
2156 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n",
2157 startnode, endnode);
2160 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) *
2161 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO);
2162 if (codec->fgs == NULL) {
2163 device_printf(sc->dev, "%s: Unable to allocate function groups\n",
2168 for (i = startnode; i < endnode; i++)
2169 hdac_probe_function(codec, i);
2174 * Probe codec function and add it to the list.
2177 hdac_probe_function(struct hdac_codec *codec, nid_t nid)
2179 struct hdac_softc *sc = codec->sc;
2180 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs];
2181 uint32_t fctgrptype;
2183 nid_t cad = codec->cad;
2185 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc,
2186 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad));
2189 devinfo->node_type = fctgrptype;
2190 devinfo->codec = codec;
2192 res = hdac_command(sc,
2193 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad);
2195 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res);
2196 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res);
2197 devinfo->endnode = devinfo->startnode + devinfo->nodecnt;
2200 device_printf(sc->dev,
2201 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n",
2202 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
2203 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
2204 "unknown", nid, devinfo->startnode, devinfo->endnode,
2208 if (devinfo->nodecnt > 0)
2209 devinfo->widget = (struct hdac_widget *)malloc(
2210 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC,
2213 devinfo->widget = NULL;
2215 if (devinfo->widget == NULL) {
2216 device_printf(sc->dev, "unable to allocate widgets!\n");
2217 devinfo->endnode = devinfo->startnode;
2218 devinfo->nodecnt = 0;
2226 hdac_widget_connection_parse(struct hdac_widget *w)
2228 struct hdac_softc *sc = w->devinfo->codec->sc;
2230 int i, j, max, ents, entnum;
2231 nid_t cad = w->devinfo->codec->cad;
2233 nid_t cnid, addcnid, prevcnid;
2237 res = hdac_command(sc,
2238 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad);
2240 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res);
2245 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4;
2246 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1;
2249 #define CONN_RMASK(e) (1 << ((32 / (e)) - 1))
2250 #define CONN_NMASK(e) (CONN_RMASK(e) - 1)
2251 #define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n)))
2252 #define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e))
2253 #define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e))
2255 for (i = 0; i < ents; i += entnum) {
2256 res = hdac_command(sc,
2257 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad);
2258 for (j = 0; j < entnum; j++) {
2259 cnid = CONN_CNID(res, entnum, j);
2261 if (w->nconns < ents)
2262 device_printf(sc->dev,
2263 "%s: nid=%d WARNING: zero cnid "
2264 "entnum=%d j=%d index=%d "
2265 "entries=%d found=%d res=0x%08x\n",
2266 __func__, nid, entnum, j, i,
2267 ents, w->nconns, res);
2271 if (cnid < w->devinfo->startnode ||
2272 cnid >= w->devinfo->endnode) {
2274 device_printf(sc->dev,
2275 "GHOST: nid=%d j=%d "
2276 "entnum=%d index=%d res=0x%08x\n",
2277 nid, j, entnum, i, res);
2280 if (CONN_RANGE(res, entnum, j) == 0)
2282 else if (prevcnid == 0 || prevcnid >= cnid) {
2283 device_printf(sc->dev,
2284 "%s: WARNING: Invalid child range "
2285 "nid=%d index=%d j=%d entnum=%d "
2286 "prevcnid=%d cnid=%d res=0x%08x\n",
2287 __func__, nid, i, j, entnum, prevcnid,
2291 addcnid = prevcnid + 1;
2292 while (addcnid <= cnid) {
2293 if (w->nconns > max) {
2294 device_printf(sc->dev,
2295 "Adding %d (nid=%d): "
2296 "Max connection reached! max=%d\n",
2297 addcnid, nid, max + 1);
2300 w->connsenable[w->nconns] = 1;
2301 w->conns[w->nconns++] = addcnid++;
2312 hdac_widget_pin_patch(uint32_t config, const char *str)
2315 char *key, *value, *rest, *bad;
2318 strlcpy(buf, str, sizeof(buf));
2320 while ((key = strsep(&rest, "=")) != NULL) {
2321 value = strsep(&rest, " \t");
2324 ival = strtol(value, &bad, 10);
2325 if (strcmp(key, "seq") == 0) {
2326 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK;
2327 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) &
2328 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK);
2329 } else if (strcmp(key, "as") == 0) {
2330 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK;
2331 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) &
2332 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK);
2333 } else if (strcmp(key, "misc") == 0) {
2334 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK;
2335 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) &
2336 HDA_CONFIG_DEFAULTCONF_MISC_MASK);
2337 } else if (strcmp(key, "color") == 0) {
2338 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK;
2340 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) &
2341 HDA_CONFIG_DEFAULTCONF_COLOR_MASK);
2343 for (i = 0; i < 16; i++) {
2344 if (strcasecmp(HDA_COLORS[i], value) == 0) {
2345 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT);
2349 } else if (strcmp(key, "ctype") == 0) {
2350 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK;
2351 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) &
2352 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK);
2353 } else if (strcmp(key, "device") == 0) {
2354 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2356 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) &
2357 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK);
2360 for (i = 0; i < 16; i++) {
2361 if (strcasecmp(HDA_DEVS[i], value) == 0) {
2362 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT);
2366 } else if (strcmp(key, "loc") == 0) {
2367 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK;
2368 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) &
2369 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK);
2370 } else if (strcmp(key, "conn") == 0) {
2371 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2373 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) &
2374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2377 for (i = 0; i < 4; i++) {
2378 if (strcasecmp(HDA_CONNS[i], value) == 0) {
2379 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT);
2389 hdac_widget_pin_getconfig(struct hdac_widget *w)
2391 struct hdac_softc *sc;
2392 uint32_t config, orig, id;
2395 const char *res = NULL, *patch = NULL;
2397 sc = w->devinfo->codec->sc;
2398 cad = w->devinfo->codec->cad;
2400 id = hdac_codec_id(w->devinfo->codec);
2402 config = hdac_command(sc,
2403 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid),
2408 hdac_dump_pin_config(w, orig);
2411 /* XXX: Old patches require complete review.
2412 * Now they may create more problem then solve due to
2413 * incorrect associations.
2415 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) {
2418 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2419 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2422 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2423 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT;
2428 } else if (id == HDA_CODEC_ALC880 &&
2429 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR ||
2430 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) {
2436 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2437 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2439 case 25: /* XXX MIC2 */
2440 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2441 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN;
2443 case 26: /* LINE1 */
2444 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2445 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2447 case 27: /* XXX LINE2 */
2448 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2449 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN;
2452 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
2453 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD;
2456 } else if (id == HDA_CODEC_ALC883 &&
2457 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR ||
2458 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) {
2461 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2462 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2463 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2464 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2467 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2468 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2469 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2470 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2473 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor ==
2474 HP_V3000_SUBVENDOR) {
2477 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2478 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2481 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2482 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2483 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2484 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2487 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2488 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2489 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD |
2490 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2493 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor ==
2494 HP_DV5000_SUBVENDOR) {
2498 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK;
2499 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE;
2502 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2503 ASUS_W6F_SUBVENDOR) {
2506 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2507 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2508 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT |
2509 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2516 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2517 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2518 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN |
2519 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED);
2522 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2523 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2524 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2525 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2528 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor ==
2529 UNIWILL_9075_SUBVENDOR) {
2532 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK |
2533 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK);
2534 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT |
2535 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK);
2541 if (id == HDA_CODEC_AD1986A &&
2542 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR ||
2543 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR ||
2544 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) {
2546 case 26: /* Headphones with redirection */
2547 patch = "as=1 seq=15";
2549 case 28: /* 5.1 out => 2.0 out + 1 input */
2550 patch = "device=Line-in as=8 seq=1";
2552 case 29: /* Can't use this as input, as the only available mic
2553 * preamplifier is busy by front panel mic (nid 31).
2554 * If you want to use this rear connector as mic input,
2555 * you have to disable the front panel one. */
2558 case 31: /* Lot of inputs configured with as=15 and unusable */
2559 patch = "as=8 seq=3";
2562 patch = "as=8 seq=4";
2565 patch = "as=8 seq=5";
2568 patch = "as=8 seq=6";
2571 } else if (id == HDA_CODEC_ALC260 &&
2572 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) {
2575 patch = "seq=15 device=Headphones";
2578 } else if (id == HDA_CODEC_ALC268) {
2579 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) {
2581 case 20: /* Headphones Jack */
2582 patch = "as=1 seq=15";
2586 } else if (id == HDA_CODEC_CX20561 &&
2587 sc->pci_subvendor == LENOVO_B450_SUBVENDOR) {
2590 patch = "as=1 seq=15";
2596 config = hdac_widget_pin_patch(config, patch);
2598 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid);
2599 if (resource_string_value(device_get_name(sc->dev),
2600 device_get_unit(sc->dev), buf, &res) == 0) {
2601 if (strncmp(res, "0x", 2) == 0) {
2602 config = strtol(res + 2, NULL, 16);
2604 config = hdac_widget_pin_patch(config, res);
2610 device_printf(sc->dev,
2611 "Patching pin config nid=%u 0x%08x -> 0x%08x\n",
2619 hdac_widget_pin_getcaps(struct hdac_widget *w)
2621 struct hdac_softc *sc;
2622 uint32_t caps, orig, id;
2625 sc = w->devinfo->codec->sc;
2626 cad = w->devinfo->codec->cad;
2628 id = hdac_codec_id(w->devinfo->codec);
2630 caps = hdac_command(sc,
2631 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad);
2636 device_printf(sc->dev,
2637 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n",
2645 hdac_widget_pin_parse(struct hdac_widget *w)
2647 struct hdac_softc *sc = w->devinfo->codec->sc;
2648 uint32_t config, pincap;
2650 nid_t cad = w->devinfo->codec->cad;
2654 config = hdac_widget_pin_getconfig(w);
2655 w->wclass.pin.config = config;
2657 pincap = hdac_widget_pin_getcaps(w);
2658 w->wclass.pin.cap = pincap;
2660 w->wclass.pin.ctrl = hdac_command(sc,
2661 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad);
2663 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) {
2664 w->param.eapdbtl = hdac_command(sc,
2665 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad);
2666 w->param.eapdbtl &= 0x7;
2667 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
2669 w->param.eapdbtl = HDAC_INVALID;
2671 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >>
2672 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT];
2674 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >>
2675 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT;
2676 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >>
2677 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT;
2679 strlcat(w->name, ": ", sizeof(w->name));
2680 strlcat(w->name, devstr, sizeof(w->name));
2681 strlcat(w->name, " (", sizeof(w->name));
2682 if (conn == 0 && color != 0 && color != 15) {
2683 strlcat(w->name, HDA_COLORS[color], sizeof(w->name));
2684 strlcat(w->name, " ", sizeof(w->name));
2686 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name));
2687 strlcat(w->name, ")", sizeof(w->name));
2691 hdac_widget_getcaps(struct hdac_widget *w, int *waspin)
2693 struct hdac_softc *sc;
2694 uint32_t caps, orig, id;
2695 nid_t cad, nid, beeper = -1;
2697 sc = w->devinfo->codec->sc;
2698 cad = w->devinfo->codec->cad;
2700 id = hdac_codec_id(w->devinfo->codec);
2702 caps = hdac_command(sc,
2703 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP),
2707 /* On some codecs beeper is an input pin, but it is not recordable
2708 alone. Also most of BIOSes does not declare beeper pin.
2709 Change beeper pin node type to beeper to help parser. */
2712 case HDA_CODEC_AD1882:
2713 case HDA_CODEC_AD1883:
2714 case HDA_CODEC_AD1984:
2715 case HDA_CODEC_AD1984A:
2716 case HDA_CODEC_AD1984B:
2717 case HDA_CODEC_AD1987:
2718 case HDA_CODEC_AD1988:
2719 case HDA_CODEC_AD1988B:
2720 case HDA_CODEC_AD1989B:
2723 case HDA_CODEC_ALC260:
2726 case HDA_CODEC_ALC262:
2727 case HDA_CODEC_ALC268:
2728 case HDA_CODEC_ALC880:
2729 case HDA_CODEC_ALC882:
2730 case HDA_CODEC_ALC883:
2731 case HDA_CODEC_ALC885:
2732 case HDA_CODEC_ALC888:
2733 case HDA_CODEC_ALC889:
2737 if (nid == beeper) {
2738 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK;
2739 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET <<
2740 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT;
2746 device_printf(sc->dev,
2747 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n",
2756 hdac_widget_parse(struct hdac_widget *w)
2758 struct hdac_softc *sc = w->devinfo->codec->sc;
2761 nid_t cad = w->devinfo->codec->cad;
2764 wcap = hdac_widget_getcaps(w, &w->waspin);
2766 w->param.widget_cap = wcap;
2767 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap);
2770 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
2771 typestr = "audio output";
2773 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
2774 typestr = "audio input";
2776 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
2777 typestr = "audio mixer";
2779 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
2780 typestr = "audio selector";
2782 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
2785 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET:
2786 typestr = "power widget";
2788 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET:
2789 typestr = "volume widget";
2791 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
2792 typestr = "beep widget";
2794 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET:
2795 typestr = "vendor widget";
2798 typestr = "unknown type";
2802 strlcpy(w->name, typestr, sizeof(w->name));
2804 hdac_widget_connection_parse(w);
2806 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) {
2807 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2808 w->param.outamp_cap =
2810 HDA_CMD_GET_PARAMETER(cad, nid,
2811 HDA_PARAM_OUTPUT_AMP_CAP), cad);
2813 w->param.outamp_cap =
2814 w->devinfo->function.audio.outamp_cap;
2816 w->param.outamp_cap = 0;
2818 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) {
2819 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap))
2820 w->param.inamp_cap =
2822 HDA_CMD_GET_PARAMETER(cad, nid,
2823 HDA_PARAM_INPUT_AMP_CAP), cad);
2825 w->param.inamp_cap =
2826 w->devinfo->function.audio.inamp_cap;
2828 w->param.inamp_cap = 0;
2830 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
2831 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
2832 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) {
2833 cap = hdac_command(sc,
2834 HDA_CMD_GET_PARAMETER(cad, nid,
2835 HDA_PARAM_SUPP_STREAM_FORMATS), cad);
2836 w->param.supp_stream_formats = (cap != 0) ? cap :
2837 w->devinfo->function.audio.supp_stream_formats;
2838 cap = hdac_command(sc,
2839 HDA_CMD_GET_PARAMETER(cad, nid,
2840 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad);
2841 w->param.supp_pcm_size_rate = (cap != 0) ? cap :
2842 w->devinfo->function.audio.supp_pcm_size_rate;
2844 w->param.supp_stream_formats =
2845 w->devinfo->function.audio.supp_stream_formats;
2846 w->param.supp_pcm_size_rate =
2847 w->devinfo->function.audio.supp_pcm_size_rate;
2850 w->param.supp_stream_formats = 0;
2851 w->param.supp_pcm_size_rate = 0;
2854 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
2855 hdac_widget_pin_parse(w);
2858 static struct hdac_widget *
2859 hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid)
2861 if (devinfo == NULL || devinfo->widget == NULL ||
2862 nid < devinfo->startnode || nid >= devinfo->endnode)
2864 return (&devinfo->widget[nid - devinfo->startnode]);
2868 hda_poll_channel(struct hdac_chan *ch)
2871 volatile uint32_t ptr;
2873 if (!(ch->flags & HDAC_CHN_RUNNING))
2876 sz = ch->blksz * ch->blkcnt;
2877 if (ch->dmapos != NULL)
2878 ptr = *(ch->dmapos);
2880 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem,
2881 ch->off + HDAC_SDLPIB);
2884 ptr &= ~(ch->blksz - 1);
2885 delta = (sz + ptr - ch->prevptr) % sz;
2887 if (delta < ch->blksz)
2896 hda_poll_callback(void *arg)
2898 struct hdac_softc *sc = arg;
2906 if (sc->polling == 0) {
2912 for (i = 0; i < sc->num_chans; i++) {
2913 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
2916 if (hda_poll_channel(&sc->chans[i]))
2917 trigger |= (1 << i);
2922 callout_reset(&sc->poll_hda, sc->poll_ticks,
2923 hda_poll_callback, sc);
2927 for (i = 0; i < sc->num_chans; i++) {
2928 if (trigger & (1 << i))
2929 chn_intr(sc->chans[i].c);
2934 hdac_rirb_flush(struct hdac_softc *sc)
2936 struct hdac_rirb *rirb_base, *rirb;
2937 struct hdac_codec *codec;
2938 struct hdac_command_list *commands;
2944 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
2945 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
2947 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
2948 BUS_DMASYNC_POSTREAD);
2953 while (sc->rirb_rp != rirbwp) {
2955 sc->rirb_rp %= sc->rirb_size;
2956 rirb = &rirb_base[sc->rirb_rp];
2957 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
2958 if (cad < 0 || cad >= HDAC_CODEC_MAX ||
2959 sc->codecs[cad] == NULL)
2961 resp = rirb->response;
2962 codec = sc->codecs[cad];
2963 commands = codec->commands;
2964 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
2965 sc->unsolq[sc->unsolq_wp++] = (cad << 16) |
2966 ((resp >> 26) & 0xffff);
2967 sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
2968 } else if (commands != NULL && commands->num_commands > 0 &&
2969 codec->responses_received < commands->num_commands)
2970 commands->responses[codec->responses_received++] =
2979 hdac_unsolq_flush(struct hdac_softc *sc)
2985 if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
2986 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
2987 while (sc->unsolq_rp != sc->unsolq_wp) {
2988 cad = sc->unsolq[sc->unsolq_rp] >> 16;
2989 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff;
2990 sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
2991 hdac_unsolicited_handler(sc->codecs[cad], tag);
2994 sc->unsolq_st = HDAC_UNSOLQ_READY;
3001 hdac_poll_callback(void *arg)
3003 struct hdac_softc *sc = arg;
3008 if (sc->polling == 0 || sc->poll_ival == 0) {
3012 if (hdac_rirb_flush(sc) != 0)
3013 hdac_unsolq_flush(sc);
3014 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc);
3019 hdac_poll_reinit(struct hdac_softc *sc)
3021 int i, pollticks, min = 1000000;
3022 struct hdac_chan *ch;
3024 for (i = 0; i < sc->num_chans; i++) {
3025 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0)
3028 pollticks = ((uint64_t)hz * ch->blksz) /
3029 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b));
3033 if (pollticks < 1) {
3035 device_printf(sc->dev,
3036 "%s: pollticks=%d < 1 !\n",
3037 __func__, pollticks);
3041 if (min > pollticks)
3045 device_printf(sc->dev,
3046 "%s: pollticks %d -> %d\n",
3047 __func__, sc->poll_ticks, min);
3049 sc->poll_ticks = min;
3051 callout_stop(&sc->poll_hda);
3053 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc);
3057 hdac_stream_stop(struct hdac_chan *ch)
3059 struct hdac_softc *sc = ch->devinfo->codec->sc;
3062 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3063 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
3065 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3067 ch->flags &= ~HDAC_CHN_RUNNING;
3069 if (sc->polling != 0)
3070 hdac_poll_reinit(sc);
3072 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
3073 ctl &= ~(1 << (ch->off >> 5));
3074 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
3078 hdac_stream_start(struct hdac_chan *ch)
3080 struct hdac_softc *sc = ch->devinfo->codec->sc;
3083 ch->flags |= HDAC_CHN_RUNNING;
3085 if (sc->polling != 0)
3086 hdac_poll_reinit(sc);
3088 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
3089 ctl |= 1 << (ch->off >> 5);
3090 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
3092 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3093 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
3095 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3099 hdac_stream_reset(struct hdac_chan *ch)
3101 struct hdac_softc *sc = ch->devinfo->codec->sc;
3106 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3107 ctl |= HDAC_SDCTL_SRST;
3108 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3110 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3111 if (ctl & HDAC_SDCTL_SRST)
3115 if (!(ctl & HDAC_SDCTL_SRST)) {
3116 device_printf(sc->dev, "timeout in reset\n");
3118 ctl &= ~HDAC_SDCTL_SRST;
3119 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl);
3122 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0);
3123 if (!(ctl & HDAC_SDCTL_SRST))
3127 if (ctl & HDAC_SDCTL_SRST)
3128 device_printf(sc->dev, "can't reset!\n");
3132 hdac_stream_setid(struct hdac_chan *ch)
3134 struct hdac_softc *sc = ch->devinfo->codec->sc;
3137 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2);
3138 ctl &= ~HDAC_SDCTL2_STRM_MASK;
3139 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT;
3140 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl);
3144 hdac_bdl_setup(struct hdac_chan *ch)
3146 struct hdac_softc *sc = ch->devinfo->codec->sc;
3147 struct hdac_bdle *bdle;
3149 uint32_t blksz, blkcnt;
3152 addr = (uint64_t)sndbuf_getbufaddr(ch->b);
3153 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr;
3156 blkcnt = ch->blkcnt;
3158 for (i = 0; i < blkcnt; i++, bdle++) {
3159 bdle->addrl = (uint32_t)addr;
3160 bdle->addrh = (uint32_t)(addr >> 32);
3166 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt);
3167 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1);
3168 addr = ch->bdl_dma.dma_paddr;
3169 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr);
3170 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
3171 if (ch->dmapos != NULL &&
3172 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) {
3173 addr = sc->pos_dma.dma_paddr;
3174 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
3175 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001);
3176 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32));
3181 hdac_bdl_alloc(struct hdac_chan *ch)
3183 struct hdac_softc *sc = ch->devinfo->codec->sc;
3186 rc = hdac_dma_alloc(sc, &ch->bdl_dma,
3187 sizeof(struct hdac_bdle) * HDA_BDL_MAX);
3189 device_printf(sc->dev, "can't alloc bdl\n");
3197 hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid,
3198 int index, int lmute, int rmute,
3199 int left, int right, int dir)
3206 if (left != right || lmute != rmute) {
3207 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) |
3208 (lmute << 7) | left;
3210 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3211 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) |
3212 (rmute << 7) | right;
3214 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) |
3215 (lmute << 7) | left;
3218 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad);
3222 hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute,
3223 int left, int right)
3225 struct hdac_softc *sc;
3229 sc = ctl->widget->devinfo->codec->sc;
3230 cad = ctl->widget->devinfo->codec->cad;
3231 nid = ctl->widget->nid;
3233 /* Save new values if valid. */
3234 if (mute != HDA_AMP_MUTE_DEFAULT)
3236 if (left != HDA_AMP_VOL_DEFAULT)
3238 if (right != HDA_AMP_VOL_DEFAULT)
3240 /* Prepare effective values */
3241 if (ctl->forcemute) {
3247 lmute = HDA_AMP_LEFT_MUTED(ctl->muted);
3248 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted);
3252 /* Apply effective values */
3253 if (ctl->dir & HDA_CTL_OUT)
3254 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3255 lmute, rmute, left, right, 0);
3256 if (ctl->dir & HDA_CTL_IN)
3257 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index,
3258 lmute, rmute, left, right, 1);
3262 hdac_widget_connection_select(struct hdac_widget *w, uint8_t index)
3264 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1))
3266 hdac_command(w->devinfo->codec->sc,
3267 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad,
3268 w->nid, index), w->devinfo->codec->cad);
3273 /****************************************************************************
3274 * uint32_t hdac_command_sendone_internal
3276 * Wrapper function that sends only one command to a given codec
3277 ****************************************************************************/
3279 hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad)
3281 struct hdac_command_list cl;
3282 uint32_t response = HDAC_INVALID;
3284 if (!hdac_lockowned(sc))
3285 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
3286 cl.num_commands = 1;
3288 cl.responses = &response;
3290 hdac_command_send_internal(sc, &cl, cad);
3295 /****************************************************************************
3296 * hdac_command_send_internal
3298 * Send a command list to the codec via the corb. We queue as much verbs as
3299 * we can and msleep on the codec. When the interrupt get the responses
3300 * back from the rirb, it will wake us up so we can queue the remaining verbs
3302 ****************************************************************************/
3304 hdac_command_send_internal(struct hdac_softc *sc,
3305 struct hdac_command_list *commands, nid_t cad)
3307 struct hdac_codec *codec;
3312 struct hdac_rirb *rirb_base;
3314 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL ||
3315 commands->num_commands < 1)
3318 codec = sc->codecs[cad];
3319 codec->commands = commands;
3320 codec->responses_received = 0;
3321 codec->verbs_sent = 0;
3322 corb = (uint32_t *)sc->corb_dma.dma_vaddr;
3323 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
3326 if (codec->verbs_sent != commands->num_commands) {
3327 /* Queue as many verbs as possible */
3328 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP);
3330 bus_dmamap_sync(sc->corb_dma.dma_tag,
3331 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
3333 while (codec->verbs_sent != commands->num_commands &&
3334 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) {
3336 sc->corb_wp %= sc->corb_size;
3338 commands->verbs[codec->verbs_sent++];
3341 /* Send the verbs to the codecs */
3343 bus_dmamap_sync(sc->corb_dma.dma_tag,
3344 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
3346 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
3350 while (hdac_rirb_flush(sc) == 0 && --timeout)
3352 } while ((codec->verbs_sent != commands->num_commands ||
3353 codec->responses_received != commands->num_commands) && --retry);
3356 device_printf(sc->dev,
3357 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n",
3358 __func__, commands->num_commands, codec->verbs_sent,
3359 codec->responses_received);
3361 codec->commands = NULL;
3362 codec->responses_received = 0;
3363 codec->verbs_sent = 0;
3365 hdac_unsolq_flush(sc);
3369 /****************************************************************************
3371 ****************************************************************************/
3373 /****************************************************************************
3374 * int hdac_probe(device_t)
3376 * Probe for the presence of an hdac. If none is found, check for a generic
3377 * match using the subclass of the device.
3378 ****************************************************************************/
3380 hdac_probe(device_t dev)
3384 uint16_t class, subclass;
3387 model = (uint32_t)pci_get_device(dev) << 16;
3388 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
3389 class = pci_get_class(dev);
3390 subclass = pci_get_subclass(dev);
3392 bzero(desc, sizeof(desc));
3394 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
3395 if (hdac_devices[i].model == model) {
3396 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3397 result = BUS_PROBE_DEFAULT;
3400 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
3401 class == PCIC_MULTIMEDIA &&
3402 subclass == PCIS_MULTIMEDIA_HDA) {
3403 strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
3404 result = BUS_PROBE_GENERIC;
3408 if (result == ENXIO && class == PCIC_MULTIMEDIA &&
3409 subclass == PCIS_MULTIMEDIA_HDA) {
3410 strlcpy(desc, "Generic", sizeof(desc));
3411 result = BUS_PROBE_GENERIC;
3413 if (result != ENXIO) {
3414 strlcat(desc, " High Definition Audio Controller",
3416 device_set_desc_copy(dev, desc);
3423 hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b,
3424 struct pcm_channel *c, int dir)
3426 struct hdac_pcm_devinfo *pdevinfo = data;
3427 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3428 struct hdac_softc *sc = devinfo->codec->sc;
3429 struct hdac_chan *ch;
3430 int i, ord = 0, chid;
3434 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec;
3435 ch = &sc->chans[chid];
3436 for (i = 0; i < sc->num_chans && i < chid; i++) {
3437 if (ch->dir == sc->chans[i].dir)
3440 if (dir == PCMDIR_PLAY) {
3441 ch->off = (sc->num_iss + ord) << 5;
3446 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) {
3447 ch->caps.minspeed = ch->caps.maxspeed = 48000;
3448 ch->pcmrates[0] = 48000;
3449 ch->pcmrates[1] = 0;
3451 if (sc->pos_dma.dma_vaddr != NULL)
3452 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr +
3453 (sc->streamcnt * 8));
3456 ch->sid = ++sc->streamcnt;
3460 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt;
3461 ch->blkcnt = pdevinfo->chan_blkcnt;
3464 if (hdac_bdl_alloc(ch) != 0) {
3469 if (sndbuf_alloc(ch->b, sc->chan_dmat,
3470 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0,
3471 pdevinfo->chan_size) != 0)
3478 hdac_channel_setformat(kobj_t obj, void *data, uint32_t format)
3480 struct hdac_chan *ch = data;
3483 for (i = 0; ch->caps.fmtlist[i] != 0; i++) {
3484 if (format == ch->caps.fmtlist[i]) {
3494 hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed)
3496 struct hdac_chan *ch = data;
3497 uint32_t spd = 0, threshold;
3500 for (i = 0; ch->pcmrates[i] != 0; i++) {
3501 spd = ch->pcmrates[i];
3502 threshold = spd + ((ch->pcmrates[i + 1] != 0) ?
3503 ((ch->pcmrates[i + 1] - spd) >> 1) : 0);
3504 if (speed < threshold)
3508 if (spd == 0) /* impossible */
3517 hdac_stream_setup(struct hdac_chan *ch)
3519 struct hdac_softc *sc = ch->devinfo->codec->sc;
3520 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as];
3521 struct hdac_widget *w;
3522 int i, chn, totalchn, c;
3523 nid_t cad = ch->devinfo->codec->cad;
3525 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */
3526 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */
3529 totalchn = AFMT_CHANNEL(ch->fmt);
3531 device_printf(ch->pdevinfo->dev,
3532 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n",
3533 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3537 if (ch->fmt & AFMT_S16_LE)
3538 fmt |= ch->bit16 << 4;
3539 else if (ch->fmt & AFMT_S32_LE)
3540 fmt |= ch->bit32 << 4;
3543 for (i = 0; i < HDA_RATE_TAB_LEN; i++) {
3544 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) {
3545 fmt |= hda_rate_tab[i].base;
3546 fmt |= hda_rate_tab[i].mul;
3547 fmt |= hda_rate_tab[i].div;
3551 fmt |= (totalchn - 1);
3553 /* Set channel mapping for known speaker setups. */
3554 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */
3556 else if (as->pinset == 0x0017) /* Standard 7.1 */
3559 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt);
3561 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN;
3562 if (ch->fmt & AFMT_AC3)
3563 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO;
3566 for (i = 0; ch->io[i] != -1; i++) {
3567 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3571 /* If HP redirection is enabled, but failed to use same
3572 DAC, make last DAC to duplicate first one. */
3573 if (as->fakeredir && i == (as->pincnt - 1)) {
3576 if (map >= 0) /* Map known speaker setups. */
3577 chn = (((chmap[map][totalchn / 2] >> i * 4) &
3579 if (chn < 0 || chn >= totalchn) {
3582 c = (ch->sid << 4) | chn;
3586 device_printf(ch->pdevinfo->dev,
3587 "PCMDIR_%s: Stream setup nid=%d: "
3588 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n",
3589 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC",
3590 ch->io[i], fmt, dfmt, c);
3593 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad);
3594 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3596 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt),
3600 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad);
3603 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad);
3605 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad);
3607 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad);
3609 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1;
3614 * Greatest Common Divisor.
3617 gcd(unsigned a, unsigned b)
3630 * Least Common Multiple.
3633 lcm(unsigned a, unsigned b)
3636 return ((a * b) / gcd(a, b));
3640 hdac_channel_setfragments(kobj_t obj, void *data,
3641 uint32_t blksz, uint32_t blkcnt)
3643 struct hdac_chan *ch = data;
3644 struct hdac_softc *sc = ch->devinfo->codec->sc;
3646 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b));
3648 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN))
3649 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN;
3650 if (blksz < HDA_BLK_MIN)
3651 blksz = HDA_BLK_MIN;
3652 if (blkcnt > HDA_BDL_MAX)
3653 blkcnt = HDA_BDL_MAX;
3654 if (blkcnt < HDA_BDL_MIN)
3655 blkcnt = HDA_BDL_MIN;
3657 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) {
3658 if ((blkcnt >> 1) >= HDA_BDL_MIN)
3660 else if ((blksz >> 1) >= HDA_BLK_MIN)
3666 if ((sndbuf_getblksz(ch->b) != blksz ||
3667 sndbuf_getblkcnt(ch->b) != blkcnt) &&
3668 sndbuf_resize(ch->b, blkcnt, blksz) != 0)
3669 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n",
3670 __func__, blksz, blkcnt);
3672 ch->blksz = sndbuf_getblksz(ch->b);
3673 ch->blkcnt = sndbuf_getblkcnt(ch->b);
3679 hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz)
3681 struct hdac_chan *ch = data;
3683 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt);
3689 hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch)
3691 struct hdac_devinfo *devinfo = ch->devinfo;
3692 struct hdac_widget *w;
3693 nid_t cad = devinfo->codec->cad;
3696 hdac_stream_stop(ch);
3698 for (i = 0; ch->io[i] != -1; i++) {
3699 w = hdac_widget_get(ch->devinfo, ch->io[i]);
3702 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
3704 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0),
3708 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i],
3714 hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch)
3718 hdac_stream_stop(ch);
3719 hdac_stream_reset(ch);
3721 hdac_stream_setid(ch);
3722 hdac_stream_setup(ch);
3723 hdac_stream_start(ch);
3727 hdac_channel_trigger(kobj_t obj, void *data, int go)
3729 struct hdac_chan *ch = data;
3730 struct hdac_softc *sc = ch->devinfo->codec->sc;
3732 if (!PCMTRIG_COMMON(go))
3738 hdac_channel_start(sc, ch);
3742 hdac_channel_stop(sc, ch);
3753 hdac_channel_getptr(kobj_t obj, void *data)
3755 struct hdac_chan *ch = data;
3756 struct hdac_softc *sc = ch->devinfo->codec->sc;
3760 if (sc->polling != 0)
3762 else if (ch->dmapos != NULL)
3763 ptr = *(ch->dmapos);
3765 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB);
3769 * Round to available space and force 128 bytes aligment.
3771 ptr %= ch->blksz * ch->blkcnt;
3772 ptr &= HDA_BLK_ALIGN;
3777 static struct pcmchan_caps *
3778 hdac_channel_getcaps(kobj_t obj, void *data)
3780 return (&((struct hdac_chan *)data)->caps);
3783 static kobj_method_t hdac_channel_methods[] = {
3784 KOBJMETHOD(channel_init, hdac_channel_init),
3785 KOBJMETHOD(channel_setformat, hdac_channel_setformat),
3786 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed),
3787 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize),
3788 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments),
3789 KOBJMETHOD(channel_trigger, hdac_channel_trigger),
3790 KOBJMETHOD(channel_getptr, hdac_channel_getptr),
3791 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps),
3794 CHANNEL_DECLARE(hdac_channel);
3797 hdac_audio_ctl_ossmixer_init(struct snd_mixer *m)
3799 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3800 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3801 struct hdac_softc *sc = devinfo->codec->sc;
3802 struct hdac_widget *w, *cw;
3803 struct hdac_audio_ctl *ctl;
3804 uint32_t mask, recmask, id;
3805 int i, j, softpcmvol;
3809 /* Make sure that in case of soft volume it won't stay muted. */
3810 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
3811 pdevinfo->left[i] = 100;
3812 pdevinfo->right[i] = 100;
3817 id = hdac_codec_id(devinfo->codec);
3819 /* Declate EAPD as ogain control. */
3820 if (pdevinfo->play >= 0) {
3821 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3822 w = hdac_widget_get(devinfo, i);
3823 if (w == NULL || w->enable == 0)
3825 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3826 w->param.eapdbtl == HDAC_INVALID ||
3827 w->bindas != sc->chans[pdevinfo->play].as)
3829 mask |= SOUND_MASK_OGAIN;
3834 /* Declare volume controls assigned to this association. */
3837 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3838 if (ctl->enable == 0)
3840 if ((pdevinfo->play >= 0 &&
3841 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3842 (pdevinfo->rec >= 0 &&
3843 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3844 (ctl->widget->bindas == -2 && pdevinfo->index == 0))
3845 mask |= ctl->ossmask;
3848 /* Declare record sources available to this association. */
3849 if (pdevinfo->rec >= 0) {
3850 struct hdac_chan *ch = &sc->chans[pdevinfo->rec];
3851 for (i = 0; ch->io[i] != -1; i++) {
3852 w = hdac_widget_get(devinfo, ch->io[i]);
3853 if (w == NULL || w->enable == 0)
3855 for (j = 0; j < w->nconns; j++) {
3856 if (w->connsenable[j] == 0)
3858 cw = hdac_widget_get(devinfo, w->conns[j]);
3859 if (cw == NULL || cw->enable == 0)
3861 if (cw->bindas != sc->chans[pdevinfo->rec].as &&
3864 recmask |= cw->ossmask;
3869 /* Declare soft PCM volume if needed. */
3870 if (pdevinfo->play >= 0) {
3872 if ((mask & SOUND_MASK_PCM) == 0 ||
3873 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) {
3875 mask |= SOUND_MASK_PCM;
3879 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3880 if (ctl->enable == 0)
3882 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as &&
3883 (ctl->widget->bindas != -2 || pdevinfo->index != 0))
3885 if (!(ctl->ossmask & SOUND_MASK_PCM))
3892 if (softpcmvol == 1 || ctl == NULL) {
3893 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL);
3895 device_printf(pdevinfo->dev,
3896 "%s Soft PCM volume\n",
3897 (softpcmvol == 1) ? "Forcing" : "Enabling");
3902 /* Declare master volume if needed. */
3903 if (pdevinfo->play >= 0) {
3904 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) ==
3906 mask |= SOUND_MASK_VOLUME;
3907 mix_setparentchild(m, SOUND_MIXER_VOLUME,
3909 mix_setrealdev(m, SOUND_MIXER_VOLUME,
3912 device_printf(pdevinfo->dev,
3913 "Forcing master volume with PCM\n");
3918 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3919 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1;
3921 mix_setrecdevs(m, recmask);
3922 mix_setdevs(m, mask);
3930 hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev,
3931 unsigned left, unsigned right)
3933 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
3934 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
3935 struct hdac_softc *sc = devinfo->codec->sc;
3936 struct hdac_widget *w;
3937 struct hdac_audio_ctl *ctl;
3943 /* Save new values. */
3944 pdevinfo->left[dev] = left;
3945 pdevinfo->right[dev] = right;
3947 /* 'ogain' is the special case implemented with EAPD. */
3948 if (dev == SOUND_MIXER_OGAIN) {
3951 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
3952 w = hdac_widget_get(devinfo, i);
3953 if (w == NULL || w->enable == 0)
3955 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
3956 w->param.eapdbtl == HDAC_INVALID)
3960 if (i >= devinfo->endnode) {
3964 orig = w->param.eapdbtl;
3966 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3968 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3969 if (orig != w->param.eapdbtl) {
3972 val = w->param.eapdbtl;
3973 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV)
3974 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
3976 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad,
3977 w->nid, val), devinfo->codec->cad);
3980 return (left | (left << 8));
3983 /* Recalculate all controls related to this OSS device. */
3985 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
3986 if (ctl->enable == 0 ||
3987 !(ctl->ossmask & (1 << dev)))
3989 if (!((pdevinfo->play >= 0 &&
3990 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
3991 (pdevinfo->rec >= 0 &&
3992 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
3993 ctl->widget->bindas == -2))
3998 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
3999 if (ctl->ossmask & (1 << j)) {
4000 lvol = lvol * pdevinfo->left[j] / 100;
4001 rvol = rvol * pdevinfo->right[j] / 100;
4004 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0;
4005 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0;
4006 lvol = (lvol * ctl->step + 50) / 100;
4007 rvol = (rvol * ctl->step + 50) / 100;
4008 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol);
4012 return (left | (right << 8));
4016 * Commutate specified record source.
4019 hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth)
4021 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
4022 struct hdac_widget *w, *cw;
4023 struct hdac_audio_ctl *ctl;
4028 if (depth > HDA_PARSE_MAXDEPTH)
4031 w = hdac_widget_get(devinfo, nid);
4032 if (w == NULL || w->enable == 0)
4035 for (i = 0; i < w->nconns; i++) {
4036 if (w->connsenable[i] == 0)
4038 cw = hdac_widget_get(devinfo, w->conns[i]);
4039 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
4041 /* Call recursively to trace signal to it's source if needed. */
4042 if ((src & cw->ossmask) != 0) {
4043 if (cw->ossdev < 0) {
4044 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src,
4045 w->conns[i], depth + 1);
4050 /* We have two special cases: mixers and others (selectors). */
4051 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) {
4052 ctl = hdac_audio_ctl_amp_get(devinfo,
4053 w->nid, HDA_CTL_IN, i, 1);
4056 /* If we have input control on this node mute them
4057 * according to requested sources. */
4058 muted = (src & cw->ossmask) ? 0 : 1;
4059 if (muted != ctl->forcemute) {
4060 ctl->forcemute = muted;
4061 hdac_audio_ctl_amp_set(ctl,
4062 HDA_AMP_MUTE_DEFAULT,
4063 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT);
4066 device_printf(pdevinfo->dev,
4067 "Recsel (%s): nid %d source %d %s\n",
4068 hdac_audio_ctl_ossmixer_mask2allname(
4069 src, buf, sizeof(buf)),
4070 nid, i, muted?"mute":"unmute");
4075 if ((src & cw->ossmask) == 0)
4077 /* If we found requested source - select it and exit. */
4078 hdac_widget_connection_select(w, i);
4080 device_printf(pdevinfo->dev,
4081 "Recsel (%s): nid %d source %d select\n",
4082 hdac_audio_ctl_ossmixer_mask2allname(
4083 src, buf, sizeof(buf)),
4093 hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src)
4095 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m);
4096 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
4097 struct hdac_widget *w;
4098 struct hdac_softc *sc = devinfo->codec->sc;
4099 struct hdac_chan *ch;
4101 uint32_t ret = 0xffffffff;
4105 /* Commutate requested recsrc for each ADC. */
4106 ch = &sc->chans[pdevinfo->rec];
4107 for (i = 0; ch->io[i] != -1; i++) {
4108 w = hdac_widget_get(devinfo, ch->io[i]);
4109 if (w == NULL || w->enable == 0)
4111 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0);
4116 return ((ret == 0xffffffff)? 0 : ret);
4119 static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = {
4120 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init),
4121 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set),
4122 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc),
4125 MIXER_DECLARE(hdac_audio_ctl_ossmixer);
4128 hdac_unsolq_task(void *context, int pending)
4130 struct hdac_softc *sc;
4132 sc = (struct hdac_softc *)context;
4135 hdac_unsolq_flush(sc);
4139 /****************************************************************************
4140 * int hdac_attach(device_t)
4142 * Attach the device into the kernel. Interrupts usually won't be enabled
4143 * when this function is called. Setup everything that doesn't require
4144 * interrupts and defer probing of codecs until interrupts are enabled.
4145 ****************************************************************************/
4147 hdac_attach(device_t dev)
4149 struct hdac_softc *sc;
4153 uint16_t class, subclass;
4158 device_printf(dev, "HDA Driver Revision: %s\n",
4162 model = (uint32_t)pci_get_device(dev) << 16;
4163 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
4164 class = pci_get_class(dev);
4165 subclass = pci_get_subclass(dev);
4167 for (i = 0; i < HDAC_DEVICES_LEN; i++) {
4168 if (hdac_devices[i].model == model) {
4172 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
4173 class == PCIC_MULTIMEDIA &&
4174 subclass == PCIS_MULTIMEDIA_HDA) {
4180 sc = device_get_softc(dev);
4181 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME);
4183 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16;
4184 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff;
4185 vendor = pci_get_vendor(dev);
4187 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) {
4188 /* Screw nx6325 - subdevice/subvendor swapped */
4189 sc->pci_subvendor = HP_NX6325_SUBVENDOR;
4192 callout_init(&sc->poll_hda, CALLOUT_MPSAFE);
4193 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE);
4194 callout_init(&sc->poll_jack, CALLOUT_MPSAFE);
4196 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
4198 sc->poll_ticks = 1000000;
4199 sc->poll_ival = HDAC_POLL_INTERVAL;
4200 if (resource_int_value(device_get_name(dev),
4201 device_get_unit(dev), "polling", &i) == 0 && i != 0)
4207 for (i = 0; i < HDAC_CODEC_MAX; i++)
4208 sc->codecs[i] = NULL;
4210 pci_enable_busmaster(dev);
4212 if (vendor == INTEL_VENDORID) {
4214 v = pci_read_config(dev, 0x44, 1);
4215 pci_write_config(dev, 0x44, v & 0xf8, 1);
4217 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
4218 pci_read_config(dev, 0x44, 1));
4222 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI))
4223 sc->flags &= ~HDAC_F_MSI;
4225 sc->flags |= HDAC_F_MSI;
4226 if (resource_int_value(device_get_name(dev),
4227 device_get_unit(dev), "msi", &i) == 0) {
4229 sc->flags &= ~HDAC_F_MSI;
4231 sc->flags |= HDAC_F_MSI;
4234 #if defined(__i386__) || defined(__amd64__)
4235 sc->flags |= HDAC_F_DMA_NOCACHE;
4237 if (resource_int_value(device_get_name(dev),
4238 device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
4240 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4243 * Try to enable PCIe snoop to avoid messing around with
4244 * uncacheable DMA attribute. Since PCIe snoop register
4245 * config is pretty much vendor specific, there are no
4246 * general solutions on how to enable it, forcing us (even
4247 * Microsoft) to enable uncacheable or write combined DMA
4250 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
4252 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) {
4253 if (hdac_pcie_snoop[i].vendor != vendor)
4255 sc->flags &= ~HDAC_F_DMA_NOCACHE;
4256 if (hdac_pcie_snoop[i].reg == 0x00)
4258 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4259 if ((v & hdac_pcie_snoop[i].enable) ==
4260 hdac_pcie_snoop[i].enable)
4262 v &= hdac_pcie_snoop[i].mask;
4263 v |= hdac_pcie_snoop[i].enable;
4264 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
4265 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
4266 if ((v & hdac_pcie_snoop[i].enable) !=
4267 hdac_pcie_snoop[i].enable) {
4270 "WARNING: Failed to enable PCIe "
4273 #if defined(__i386__) || defined(__amd64__)
4274 sc->flags |= HDAC_F_DMA_NOCACHE;
4279 #if defined(__i386__) || defined(__amd64__)
4284 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
4285 (sc->flags & HDAC_F_DMA_NOCACHE) ?
4286 "Uncacheable" : "PCIe snoop", vendor);
4289 /* Allocate resources */
4290 result = hdac_mem_alloc(sc);
4292 goto hdac_attach_fail;
4293 result = hdac_irq_alloc(sc);
4295 goto hdac_attach_fail;
4297 /* Get Capabilities */
4298 result = hdac_get_capabilities(sc);
4300 goto hdac_attach_fail;
4302 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT))
4303 sc->support_64bit = 0;
4305 /* Allocate CORB and RIRB dma memory */
4306 result = hdac_dma_alloc(sc, &sc->corb_dma,
4307 sc->corb_size * sizeof(uint32_t));
4309 goto hdac_attach_fail;
4310 result = hdac_dma_alloc(sc, &sc->rirb_dma,
4311 sc->rirb_size * sizeof(struct hdac_rirb));
4313 goto hdac_attach_fail;
4315 result = bus_dma_tag_create(
4316 bus_get_dma_tag(sc->dev), /* parent */
4317 HDAC_DMA_ALIGNMENT, /* alignment */
4319 (sc->support_64bit) ? BUS_SPACE_MAXADDR :
4320 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
4321 BUS_SPACE_MAXADDR, /* highaddr */
4322 NULL, /* filtfunc */
4323 NULL, /* fistfuncarg */
4324 HDA_BUFSZ_MAX, /* maxsize */
4326 HDA_BUFSZ_MAX, /* maxsegsz */
4328 NULL, /* lockfunc */
4329 NULL, /* lockfuncarg */
4330 &sc->chan_dmat); /* dmat */
4332 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
4334 goto hdac_attach_fail;
4337 /* Quiesce everything */
4339 device_printf(dev, "Reset controller...\n");
4343 /* Initialize the CORB and RIRB */
4347 /* Defer remaining of initialization until interrupts are enabled */
4348 sc->intrhook.ich_func = hdac_attach2;
4349 sc->intrhook.ich_arg = (void *)sc;
4350 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
4351 sc->intrhook.ich_func = NULL;
4352 hdac_attach2((void *)sc);
4359 hdac_dma_free(sc, &sc->rirb_dma);
4360 hdac_dma_free(sc, &sc->corb_dma);
4362 snd_mtxfree(sc->lock);
4368 hdac_audio_parse(struct hdac_devinfo *devinfo)
4370 struct hdac_codec *codec = devinfo->codec;
4371 struct hdac_softc *sc = codec->sc;
4372 struct hdac_widget *w;
4377 cad = devinfo->codec->cad;
4380 res = hdac_command(sc,
4381 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad);
4382 devinfo->function.audio.gpio = res;
4385 device_printf(sc->dev, "GPIO: 0x%08x "
4386 "NumGPIO=%d NumGPO=%d "
4387 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
4388 devinfo->function.audio.gpio,
4389 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
4390 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
4391 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
4392 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
4393 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
4396 res = hdac_command(sc,
4397 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS),
4399 devinfo->function.audio.supp_stream_formats = res;
4401 res = hdac_command(sc,
4402 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE),
4404 devinfo->function.audio.supp_pcm_size_rate = res;
4406 res = hdac_command(sc,
4407 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP),
4409 devinfo->function.audio.outamp_cap = res;
4411 res = hdac_command(sc,
4412 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP),
4414 devinfo->function.audio.inamp_cap = res;
4416 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4417 w = hdac_widget_get(devinfo, i);
4419 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i);
4421 w->devinfo = devinfo;
4428 w->param.eapdbtl = HDAC_INVALID;
4429 hdac_widget_parse(w);
4435 hdac_audio_ctl_parse(struct hdac_devinfo *devinfo)
4437 struct hdac_softc *sc = devinfo->codec->sc;
4438 struct hdac_audio_ctl *ctls;
4439 struct hdac_widget *w, *cw;
4440 int i, j, cnt, max, ocap, icap;
4441 int mute, offset, step, size;
4443 /* XXX This is redundant */
4445 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4446 w = hdac_widget_get(devinfo, i);
4447 if (w == NULL || w->enable == 0)
4449 if (w->param.outamp_cap != 0)
4451 if (w->param.inamp_cap != 0) {
4453 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4454 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4455 for (j = 0; j < w->nconns; j++) {
4456 cw = hdac_widget_get(devinfo,
4458 if (cw == NULL || cw->enable == 0)
4470 devinfo->function.audio.ctlcnt = max;
4475 ctls = (struct hdac_audio_ctl *)malloc(
4476 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT);
4480 device_printf(sc->dev, "unable to allocate ctls!\n");
4481 devinfo->function.audio.ctlcnt = 0;
4486 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) {
4488 device_printf(sc->dev, "%s: Ctl overflow!\n",
4492 w = hdac_widget_get(devinfo, i);
4493 if (w == NULL || w->enable == 0)
4495 ocap = w->param.outamp_cap;
4496 icap = w->param.inamp_cap;
4498 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap);
4499 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap);
4500 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap);
4501 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap);
4502 /*if (offset > step) {
4504 device_printf(sc->dev,
4505 "BUGGY outamp: nid=%d "
4506 "[offset=%d > step=%d]\n",
4507 w->nid, offset, step);
4511 ctls[cnt].enable = 1;
4512 ctls[cnt].widget = w;
4513 ctls[cnt].mute = mute;
4514 ctls[cnt].step = step;
4515 ctls[cnt].size = size;
4516 ctls[cnt].offset = offset;
4517 ctls[cnt].left = offset;
4518 ctls[cnt].right = offset;
4519 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX ||
4521 ctls[cnt].ndir = HDA_CTL_IN;
4523 ctls[cnt].ndir = HDA_CTL_OUT;
4524 ctls[cnt++].dir = HDA_CTL_OUT;
4528 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap);
4529 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap);
4530 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap);
4531 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap);
4532 /*if (offset > step) {
4534 device_printf(sc->dev,
4535 "BUGGY inamp: nid=%d "
4536 "[offset=%d > step=%d]\n",
4537 w->nid, offset, step);
4542 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR:
4543 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER:
4544 for (j = 0; j < w->nconns; j++) {
4546 device_printf(sc->dev,
4547 "%s: Ctl overflow!\n",
4551 cw = hdac_widget_get(devinfo,
4553 if (cw == NULL || cw->enable == 0)
4555 ctls[cnt].enable = 1;
4556 ctls[cnt].widget = w;
4557 ctls[cnt].childwidget = cw;
4558 ctls[cnt].index = j;
4559 ctls[cnt].mute = mute;
4560 ctls[cnt].step = step;
4561 ctls[cnt].size = size;
4562 ctls[cnt].offset = offset;
4563 ctls[cnt].left = offset;
4564 ctls[cnt].right = offset;
4565 ctls[cnt].ndir = HDA_CTL_IN;
4566 ctls[cnt++].dir = HDA_CTL_IN;
4571 device_printf(sc->dev,
4572 "%s: Ctl overflow!\n",
4576 ctls[cnt].enable = 1;
4577 ctls[cnt].widget = w;
4578 ctls[cnt].mute = mute;
4579 ctls[cnt].step = step;
4580 ctls[cnt].size = size;
4581 ctls[cnt].offset = offset;
4582 ctls[cnt].left = offset;
4583 ctls[cnt].right = offset;
4585 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4586 ctls[cnt].ndir = HDA_CTL_OUT;
4588 ctls[cnt].ndir = HDA_CTL_IN;
4589 ctls[cnt++].dir = HDA_CTL_IN;
4595 devinfo->function.audio.ctl = ctls;
4599 hdac_audio_as_parse(struct hdac_devinfo *devinfo)
4601 struct hdac_softc *sc = devinfo->codec->sc;
4602 struct hdac_audio_as *as;
4603 struct hdac_widget *w;
4604 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir;
4606 /* Count present associations */
4608 for (j = 1; j < 16; j++) {
4609 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4610 w = hdac_widget_get(devinfo, i);
4611 if (w == NULL || w->enable == 0)
4613 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4615 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config)
4619 if (j != 15) /* There could be many 1-pin assocs #15 */
4624 devinfo->function.audio.ascnt = max;
4629 as = (struct hdac_audio_as *)malloc(
4630 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT);
4634 device_printf(sc->dev, "unable to allocate assocs!\n");
4635 devinfo->function.audio.ascnt = 0;
4639 for (i = 0; i < max; i++) {
4645 /* Scan associations skipping as=0. */
4647 for (j = 1; j < 16; j++) {
4650 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
4651 w = hdac_widget_get(devinfo, i);
4652 if (w == NULL || w->enable == 0)
4654 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
4656 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config);
4657 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config);
4662 ("%s: Associations owerflow (%d of %d)",
4663 __func__, cnt, max));
4664 type = w->wclass.pin.config &
4665 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK;
4666 /* Get pin direction. */
4667 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT ||
4668 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER ||
4669 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT ||
4670 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT ||
4671 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT)
4675 /* If this is a first pin - create new association. */
4676 if (as[cnt].pincnt == 0) {
4683 /* Check association correctness. */
4684 if (as[cnt].pins[seq] != 0) {
4685 device_printf(sc->dev, "%s: Duplicate pin %d (%d) "
4686 "in association %d! Disabling association.\n",
4687 __func__, seq, w->nid, j);
4690 if (dir != as[cnt].dir) {
4691 device_printf(sc->dev, "%s: Pin %d has wrong "
4692 "direction for association %d! Disabling "
4694 __func__, w->nid, j);
4697 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) {
4698 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap))
4699 as[cnt].digital = 3;
4700 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap))
4701 as[cnt].digital = 2;
4703 as[cnt].digital = 1;
4705 /* Headphones with seq=15 may mean redirection. */
4706 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT &&
4709 as[cnt].pins[seq] = w->nid;
4711 /* Association 15 is a multiple unassociated pins. */
4715 if (j != 15 && as[cnt].pincnt > 0) {
4716 if (hpredir && as[cnt].pincnt > 1)
4717 as[cnt].hpredir = first;
4722 device_printf(sc->dev,
4723 "%d associations found:\n", max);
4724 for (i = 0; i < max; i++) {
4725 device_printf(sc->dev,
4726 "Association %d (%d) %s%s:\n",
4727 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out",
4728 as[i].enable?"":" (disabled)");
4729 for (j = 0; j < 16; j++) {
4730 if (as[i].pins[j] == 0)
4732 device_printf(sc->dev,
4733 " Pin nid=%d seq=%d\n",
4739 devinfo->function.audio.as = as;
4742 static const struct {
4745 uint32_t set, unset;
4748 * XXX Force stereo quirk. Monoural recording / playback
4749 * on few codecs (especially ALC880) seems broken or
4750 * perhaps unsupported.
4752 { HDA_MATCH_ALL, HDA_MATCH_ALL,
4753 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 },
4754 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL,
4755 HDA_QUIRK_GPIO0, 0 },
4756 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660,
4757 HDA_QUIRK_GPIO0, 0 },
4758 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880,
4759 HDA_QUIRK_GPIO0, 0 },
4760 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880,
4761 HDA_QUIRK_GPIO0, 0 },
4762 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882,
4763 HDA_QUIRK_GPIO0, 0 },
4764 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882,
4765 HDA_QUIRK_GPIO0, 0 },
4766 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A,
4767 HDA_QUIRK_EAPDINV, 0 },
4768 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A,
4769 HDA_QUIRK_EAPDINV, 0 },
4770 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861,
4771 HDA_QUIRK_OVREF, 0 },
4772 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861,
4773 HDA_QUIRK_OVREF, 0 },
4774 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988,
4775 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/
4776 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880,
4777 HDA_QUIRK_GPIO1, 0 },
4778 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A,
4779 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 },
4780 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A,
4781 HDA_QUIRK_EAPDINV, 0 },
4782 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885,
4783 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0},
4784 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221,
4785 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 },
4786 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206,
4787 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 },
4788 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X,
4789 HDA_QUIRK_GPIO0, 0 },
4790 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X,
4791 HDA_QUIRK_GPIO2, 0 },
4792 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X,
4793 HDA_QUIRK_GPIO0, 0 },
4794 { HDA_MATCH_ALL, HDA_CODEC_AD1988,
4795 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4796 { HDA_MATCH_ALL, HDA_CODEC_AD1988B,
4797 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },
4798 { HDA_MATCH_ALL, HDA_CODEC_CX20549,
4799 0, HDA_QUIRK_FORCESTEREO }
4801 #define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0]))
4804 hdac_vendor_patch_parse(struct hdac_devinfo *devinfo)
4806 struct hdac_widget *w;
4807 uint32_t id, subvendor;
4810 id = hdac_codec_id(devinfo->codec);
4811 subvendor = devinfo->codec->sc->pci_subvendor;
4816 for (i = 0; i < HDAC_QUIRKS_LEN; i++) {
4817 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) &&
4818 HDA_DEV_MATCH(hdac_quirks[i].id, id)))
4820 if (hdac_quirks[i].set != 0)
4821 devinfo->function.audio.quirks |=
4823 if (hdac_quirks[i].unset != 0)
4824 devinfo->function.audio.quirks &=
4825 ~(hdac_quirks[i].unset);
4829 case HDA_CODEC_AD1983:
4831 * This codec has several possible usages, but none
4832 * fit the parser best. Help parser to choose better.
4834 /* Disable direct unmixed playback to get pcm volume. */
4835 w = hdac_widget_get(devinfo, 5);
4837 w->connsenable[0] = 0;
4838 w = hdac_widget_get(devinfo, 6);
4840 w->connsenable[0] = 0;
4841 w = hdac_widget_get(devinfo, 11);
4843 w->connsenable[0] = 0;
4844 /* Disable mic and line selectors. */
4845 w = hdac_widget_get(devinfo, 12);
4847 w->connsenable[1] = 0;
4848 w = hdac_widget_get(devinfo, 13);
4850 w->connsenable[1] = 0;
4851 /* Disable recording from mono playback mix. */
4852 w = hdac_widget_get(devinfo, 20);
4854 w->connsenable[3] = 0;
4856 case HDA_CODEC_AD1986A:
4858 * This codec has overcomplicated input mixing.
4859 * Make some cleaning there.
4861 /* Disable input mono mixer. Not needed and not supported. */
4862 w = hdac_widget_get(devinfo, 43);
4865 /* Disable any with any input mixing mesh. Use separately. */
4866 w = hdac_widget_get(devinfo, 39);
4869 w = hdac_widget_get(devinfo, 40);
4872 w = hdac_widget_get(devinfo, 41);
4875 w = hdac_widget_get(devinfo, 42);
4878 /* Disable duplicate mixer node connector. */
4879 w = hdac_widget_get(devinfo, 15);
4881 w->connsenable[3] = 0;
4882 /* There is only one mic preamplifier, use it effectively. */
4883 w = hdac_widget_get(devinfo, 31);
4885 if ((w->wclass.pin.config &
4886 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4887 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4888 w = hdac_widget_get(devinfo, 16);
4890 w->connsenable[2] = 0;
4892 w = hdac_widget_get(devinfo, 15);
4894 w->connsenable[0] = 0;
4897 w = hdac_widget_get(devinfo, 32);
4899 if ((w->wclass.pin.config &
4900 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
4901 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) {
4902 w = hdac_widget_get(devinfo, 16);
4904 w->connsenable[0] = 0;
4906 w = hdac_widget_get(devinfo, 15);
4908 w->connsenable[1] = 0;
4912 if (subvendor == ASUS_A8X_SUBVENDOR) {
4914 * This is just plain ridiculous.. There
4915 * are several A8 series that share the same
4916 * pci id but works differently (EAPD).
4918 w = hdac_widget_get(devinfo, 26);
4919 if (w != NULL && w->type ==
4920 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
4921 (w->wclass.pin.config &
4922 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) !=
4923 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE)
4924 devinfo->function.audio.quirks &=
4928 case HDA_CODEC_AD1981HD:
4930 * This codec has very unusual design with several
4931 * points inappropriate for the present parser.
4933 /* Disable recording from mono playback mix. */
4934 w = hdac_widget_get(devinfo, 21);
4936 w->connsenable[3] = 0;
4937 /* Disable rear to front mic mixer, use separately. */
4938 w = hdac_widget_get(devinfo, 31);
4941 /* Disable direct playback, use mixer. */
4942 w = hdac_widget_get(devinfo, 5);
4944 w->connsenable[0] = 0;
4945 w = hdac_widget_get(devinfo, 6);
4947 w->connsenable[0] = 0;
4948 w = hdac_widget_get(devinfo, 9);
4950 w->connsenable[0] = 0;
4951 w = hdac_widget_get(devinfo, 24);
4953 w->connsenable[0] = 0;
4955 case HDA_CODEC_CX20582:
4956 case HDA_CODEC_CX20583:
4957 case HDA_CODEC_CX20584:
4958 case HDA_CODEC_CX20585:
4959 case HDA_CODEC_CX20590:
4961 * These codecs have extra connectivity on record side
4962 * too reach for the present parser.
4964 w = hdac_widget_get(devinfo, 20);
4966 w->connsenable[1] = 0;
4967 w = hdac_widget_get(devinfo, 21);
4969 w->connsenable[1] = 0;
4970 w = hdac_widget_get(devinfo, 22);
4972 w->connsenable[0] = 0;
4978 * Trace path from DAC to pin.
4981 hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
4982 int dupseq, int min, int only, int depth)
4984 struct hdac_widget *w;
4988 if (depth > HDA_PARSE_MAXDEPTH)
4990 w = hdac_widget_get(devinfo, nid);
4991 if (w == NULL || w->enable == 0)
4995 device_printf(devinfo->codec->sc->dev,
4996 " %*stracing via nid %d\n",
4997 depth + 1, "", w->nid);
5000 /* Use only unused widgets */
5001 if (w->bindas >= 0 && w->bindas != as) {
5004 device_printf(devinfo->codec->sc->dev,
5005 " %*snid %d busy by association %d\n",
5006 depth + 1, "", w->nid, w->bindas);
5012 if (w->bindseqmask != 0) {
5015 device_printf(devinfo->codec->sc->dev,
5016 " %*snid %d busy by seqmask %x\n",
5017 depth + 1, "", w->nid, w->bindseqmask);
5023 /* If this is headphones - allow duplicate first pin. */
5024 if (w->bindseqmask != 0 &&
5025 (w->bindseqmask & (1 << dupseq)) == 0) {
5027 device_printf(devinfo->codec->sc->dev,
5028 " %*snid %d busy by seqmask %x\n",
5029 depth + 1, "", w->nid, w->bindseqmask);
5036 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5037 /* Do not traverse input. AD1988 has digital monitor
5038 for which we are not ready. */
5040 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
5041 /* If we are tracing HP take only dac of first pin. */
5042 if ((only == 0 || only == w->nid) &&
5043 (w->nid >= min) && (dupseq < 0 || w->nid ==
5044 devinfo->function.audio.as[as].dacs[dupseq]))
5047 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5052 /* Find reachable DACs with smallest nid respecting constraints. */
5053 for (i = 0; i < w->nconns; i++) {
5054 if (w->connsenable[i] == 0)
5056 if (w->selconn != -1 && w->selconn != i)
5058 if ((ret = hdac_audio_trace_dac(devinfo, as, seq,
5059 w->conns[i], dupseq, min, only, depth + 1)) != 0) {
5060 if (m == 0 || ret < m) {
5064 if (only || dupseq >= 0)
5068 if (m && only && ((w->nconns > 1 &&
5069 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
5070 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR))
5076 w->bindseqmask |= (1 << seq);
5080 device_printf(devinfo->codec->sc->dev,
5081 " %*snid %d returned %d\n",
5082 depth + 1, "", w->nid, m);
5089 * Trace path from widget to ADC.
5092 hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid,
5093 int only, int depth)
5095 struct hdac_widget *w, *wc;
5099 if (depth > HDA_PARSE_MAXDEPTH)
5101 w = hdac_widget_get(devinfo, nid);
5102 if (w == NULL || w->enable == 0)
5105 device_printf(devinfo->codec->sc->dev,
5106 " %*stracing via nid %d\n",
5107 depth + 1, "", w->nid);
5109 /* Use only unused widgets */
5110 if (w->bindas >= 0 && w->bindas != as) {
5112 device_printf(devinfo->codec->sc->dev,
5113 " %*snid %d busy by association %d\n",
5114 depth + 1, "", w->nid, w->bindas);
5120 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5121 /* If we are tracing HP take only dac of first pin. */
5125 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5130 /* Try to find reachable ADCs with specified nid. */
5131 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5132 wc = hdac_widget_get(devinfo, j);
5133 if (wc == NULL || wc->enable == 0)
5135 for (i = 0; i < wc->nconns; i++) {
5136 if (wc->connsenable[i] == 0)
5138 if (wc->conns[i] != nid)
5140 if (hdac_audio_trace_adc(devinfo, as, seq,
5141 j, only, depth + 1) != 0) {
5143 if (((wc->nconns > 1 &&
5144 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) ||
5145 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) &&
5155 w->bindseqmask |= (1 << seq);
5158 device_printf(devinfo->codec->sc->dev,
5159 " %*snid %d returned %d\n",
5160 depth + 1, "", w->nid, res);
5166 * Erase trace path of the specified association.
5169 hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq)
5171 struct hdac_widget *w;
5174 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5175 w = hdac_widget_get(devinfo, i);
5176 if (w == NULL || w->enable == 0)
5178 if (w->bindas == as) {
5180 w->bindseqmask &= ~(1 << seq);
5181 if (w->bindseqmask == 0) {
5195 * Trace association path from DAC to output
5198 hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq)
5200 struct hdac_audio_as *ases = devinfo->function.audio.as;
5205 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++)
5207 /* Check if there is no any left. If so - we succeeded. */
5211 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1;
5216 device_printf(devinfo->codec->sc->dev,
5217 " Tracing pin %d with min nid %d",
5218 ases[as].pins[i], min);
5220 printf(" and hpredir %d", hpredir);
5223 /* Trace this pin taking min nid into account. */
5224 res = hdac_audio_trace_dac(devinfo, as, i,
5225 ases[as].pins[i], hpredir, min, 0, 0);
5227 /* If we failed - return to previous and redo it. */
5229 device_printf(devinfo->codec->sc->dev,
5230 " Unable to trace pin %d seq %d with min "
5232 ases[as].pins[i], i, min);
5234 printf(" and hpredir %d", hpredir);
5240 device_printf(devinfo->codec->sc->dev,
5241 " Pin %d traced to DAC %d",
5242 ases[as].pins[i], res);
5244 printf(" and hpredir %d", hpredir);
5245 if (ases[as].fakeredir)
5246 printf(" with fake redirection");
5249 /* Trace again to mark the path */
5250 hdac_audio_trace_dac(devinfo, as, i,
5251 ases[as].pins[i], hpredir, min, res, 0);
5252 ases[as].dacs[i] = res;
5253 /* We succeeded, so call next. */
5254 if (hdac_audio_trace_as_out(devinfo, as, i + 1))
5256 /* If next failed, we should retry with next min */
5257 hdac_audio_undo_trace(devinfo, as, i);
5258 ases[as].dacs[i] = 0;
5264 * Trace association path from input to ADC
5267 hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as)
5269 struct hdac_audio_as *ases = devinfo->function.audio.as;
5270 struct hdac_widget *w;
5273 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5274 w = hdac_widget_get(devinfo, j);
5275 if (w == NULL || w->enable == 0)
5277 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
5279 if (w->bindas >= 0 && w->bindas != as)
5283 for (i = 0; i < 16; i++) {
5284 if (ases[as].pins[i] == 0)
5288 device_printf(devinfo->codec->sc->dev,
5289 " Tracing pin %d to ADC %d\n",
5290 ases[as].pins[i], j);
5292 /* Trace this pin taking goal into account. */
5293 if (hdac_audio_trace_adc(devinfo, as, i,
5294 ases[as].pins[i], j, 0) == 0) {
5295 /* If we failed - return to previous and redo it. */
5297 device_printf(devinfo->codec->sc->dev,
5298 " Unable to trace pin %d to ADC %d, undo traces\n",
5299 ases[as].pins[i], j);
5301 hdac_audio_undo_trace(devinfo, as, -1);
5302 for (k = 0; k < 16; k++)
5303 ases[as].dacs[k] = 0;
5307 device_printf(devinfo->codec->sc->dev,
5308 " Pin %d traced to ADC %d\n",
5309 ases[as].pins[i], j);
5311 ases[as].dacs[i] = j;
5320 * Trace input monitor path from mixer to output association.
5323 hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth)
5325 struct hdac_audio_as *ases = devinfo->function.audio.as;
5326 struct hdac_widget *w, *wc;
5330 if (depth > HDA_PARSE_MAXDEPTH)
5332 w = hdac_widget_get(devinfo, nid);
5333 if (w == NULL || w->enable == 0)
5336 device_printf(devinfo->codec->sc->dev,
5337 " %*stracing via nid %d\n",
5338 depth + 1, "", w->nid);
5340 /* Use only unused widgets */
5341 if (depth > 0 && w->bindas != -1) {
5342 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) {
5344 device_printf(devinfo->codec->sc->dev,
5345 " %*snid %d found output association %d\n",
5346 depth + 1, "", w->nid, w->bindas);
5349 w->pflags |= HDA_ADC_MONITOR;
5353 device_printf(devinfo->codec->sc->dev,
5354 " %*snid %d busy by input association %d\n",
5355 depth + 1, "", w->nid, w->bindas);
5362 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT:
5363 /* Do not traverse input. AD1988 has digital monitor
5364 for which we are not ready. */
5366 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
5371 /* Try to find reachable ADCs with specified nid. */
5372 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5373 wc = hdac_widget_get(devinfo, j);
5374 if (wc == NULL || wc->enable == 0)
5376 for (i = 0; i < wc->nconns; i++) {
5377 if (wc->connsenable[i] == 0)
5379 if (wc->conns[i] != nid)
5381 if (hdac_audio_trace_to_out(devinfo,
5382 j, depth + 1) != 0) {
5384 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5392 if (res && w->bindas == -1)
5396 device_printf(devinfo->codec->sc->dev,
5397 " %*snid %d returned %d\n",
5398 depth + 1, "", w->nid, res);
5404 * Trace extra associations (beeper, monitor)
5407 hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo)
5409 struct hdac_audio_as *as = devinfo->function.audio.as;
5410 struct hdac_widget *w;
5414 /* Find mixer associated with input, but supplying signal
5415 for output associations. Hope it will be input monitor. */
5417 device_printf(devinfo->codec->sc->dev,
5418 "Tracing input monitor\n");
5420 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5421 w = hdac_widget_get(devinfo, j);
5422 if (w == NULL || w->enable == 0)
5424 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5426 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN)
5429 device_printf(devinfo->codec->sc->dev,
5430 " Tracing nid %d to out\n",
5433 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5435 device_printf(devinfo->codec->sc->dev,
5436 " nid %d is input monitor\n",
5439 w->ossdev = SOUND_MIXER_IMIX;
5443 /* Other inputs monitor */
5444 /* Find input pins supplying signal for output associations.
5445 Hope it will be input monitoring. */
5447 device_printf(devinfo->codec->sc->dev,
5448 "Tracing other input monitors\n");
5450 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5451 w = hdac_widget_get(devinfo, j);
5452 if (w == NULL || w->enable == 0)
5454 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5456 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN)
5459 device_printf(devinfo->codec->sc->dev,
5460 " Tracing nid %d to out\n",
5463 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5465 device_printf(devinfo->codec->sc->dev,
5466 " nid %d is input monitor\n",
5474 device_printf(devinfo->codec->sc->dev,
5475 "Tracing beeper\n");
5477 for (j = devinfo->startnode; j < devinfo->endnode; j++) {
5478 w = hdac_widget_get(devinfo, j);
5479 if (w == NULL || w->enable == 0)
5481 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET)
5484 device_printf(devinfo->codec->sc->dev,
5485 " Tracing nid %d to out\n",
5488 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) {
5490 device_printf(devinfo->codec->sc->dev,
5491 " nid %d traced to out\n",
5500 * Bind assotiations to PCM channels
5503 hdac_audio_bind_as(struct hdac_devinfo *devinfo)
5505 struct hdac_softc *sc = devinfo->codec->sc;
5506 struct hdac_audio_as *as = devinfo->function.audio.as;
5507 int j, cnt = 0, free;
5509 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5513 if (sc->num_chans == 0) {
5514 sc->chans = (struct hdac_chan *)malloc(
5515 sizeof(struct hdac_chan) * cnt,
5516 M_HDAC, M_ZERO | M_NOWAIT);
5517 if (sc->chans == NULL) {
5518 device_printf(sc->dev,
5519 "Channels memory allocation failed!\n");
5523 sc->chans = (struct hdac_chan *)realloc(sc->chans,
5524 sizeof(struct hdac_chan) * (sc->num_chans + cnt),
5525 M_HDAC, M_ZERO | M_NOWAIT);
5526 if (sc->chans == NULL) {
5528 device_printf(sc->dev,
5529 "Channels memory allocation failed!\n");
5532 /* Fixup relative pointers after realloc */
5533 for (j = 0; j < sc->num_chans; j++)
5534 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist;
5536 free = sc->num_chans;
5537 sc->num_chans += cnt;
5539 for (j = free; j < free + cnt; j++) {
5540 sc->chans[j].devinfo = devinfo;
5541 sc->chans[j].as = -1;
5544 /* Assign associations in order of their numbers, */
5545 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
5546 if (as[j].enable == 0)
5550 sc->chans[free].as = j;
5551 sc->chans[free].dir =
5552 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY;
5553 hdac_pcmchannel_setup(&sc->chans[free]);
5559 hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo)
5561 struct hdac_widget *w;
5564 /* Disable power and volume widgets. */
5565 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5566 w = hdac_widget_get(devinfo, i);
5567 if (w == NULL || w->enable == 0)
5569 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET ||
5570 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) {
5573 device_printf(devinfo->codec->sc->dev,
5574 " Disabling nid %d due to it's"
5575 " non-audio type.\n",
5583 hdac_audio_disable_useless(struct hdac_devinfo *devinfo)
5585 struct hdac_widget *w, *cw;
5586 struct hdac_audio_ctl *ctl;
5587 int done, found, i, j, k;
5589 /* Disable useless pins. */
5590 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5591 w = hdac_widget_get(devinfo, i);
5592 if (w == NULL || w->enable == 0)
5594 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
5595 if ((w->wclass.pin.config &
5596 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) ==
5597 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) {
5600 device_printf(devinfo->codec->sc->dev,
5601 " Disabling pin nid %d due"
5602 " to None connectivity.\n",
5605 } else if ((w->wclass.pin.config &
5606 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) {
5609 device_printf(devinfo->codec->sc->dev,
5610 " Disabling unassociated"
5619 /* Disable and mute controls for disabled widgets. */
5621 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5622 if (ctl->enable == 0)
5624 if (ctl->widget->enable == 0 ||
5625 (ctl->childwidget != NULL &&
5626 ctl->childwidget->enable == 0)) {
5628 ctl->muted = HDA_AMP_MUTE_ALL;
5632 if (ctl->ndir == HDA_CTL_IN)
5633 ctl->widget->connsenable[ctl->index] = 0;
5636 device_printf(devinfo->codec->sc->dev,
5637 " Disabling ctl %d nid %d cnid %d due"
5638 " to disabled widget.\n", i,
5640 (ctl->childwidget != NULL)?
5641 ctl->childwidget->nid:-1);
5645 /* Disable useless widgets. */
5646 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5647 w = hdac_widget_get(devinfo, i);
5648 if (w == NULL || w->enable == 0)
5650 /* Disable inputs with disabled child widgets. */
5651 for (j = 0; j < w->nconns; j++) {
5652 if (w->connsenable[j]) {
5653 cw = hdac_widget_get(devinfo, w->conns[j]);
5654 if (cw == NULL || cw->enable == 0) {
5655 w->connsenable[j] = 0;
5657 device_printf(devinfo->codec->sc->dev,
5658 " Disabling nid %d connection %d due"
5659 " to disabled child widget.\n",
5665 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5666 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5668 /* Disable mixers and selectors without inputs. */
5670 for (j = 0; j < w->nconns; j++) {
5671 if (w->connsenable[j]) {
5680 device_printf(devinfo->codec->sc->dev,
5681 " Disabling nid %d due to all it's"
5682 " inputs disabled.\n", w->nid);
5685 /* Disable nodes without consumers. */
5686 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR &&
5687 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5690 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5691 cw = hdac_widget_get(devinfo, k);
5692 if (cw == NULL || cw->enable == 0)
5694 for (j = 0; j < cw->nconns; j++) {
5695 if (cw->connsenable[j] && cw->conns[j] == i) {
5705 device_printf(devinfo->codec->sc->dev,
5706 " Disabling nid %d due to all it's"
5707 " consumers disabled.\n", w->nid);
5711 } while (done == 0);
5716 hdac_audio_disable_unas(struct hdac_devinfo *devinfo)
5718 struct hdac_audio_as *as = devinfo->function.audio.as;
5719 struct hdac_widget *w, *cw;
5720 struct hdac_audio_ctl *ctl;
5723 /* Disable unassosiated widgets. */
5724 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5725 w = hdac_widget_get(devinfo, i);
5726 if (w == NULL || w->enable == 0)
5728 if (w->bindas == -1) {
5731 device_printf(devinfo->codec->sc->dev,
5732 " Disabling unassociated nid %d.\n",
5737 /* Disable input connections on input pin and
5738 * output on output. */
5739 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5740 w = hdac_widget_get(devinfo, i);
5741 if (w == NULL || w->enable == 0)
5743 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
5747 if (as[w->bindas].dir == HDA_CTL_IN) {
5748 for (j = 0; j < w->nconns; j++) {
5749 if (w->connsenable[j] == 0)
5751 w->connsenable[j] = 0;
5753 device_printf(devinfo->codec->sc->dev,
5754 " Disabling connection to input pin "
5755 "nid %d conn %d.\n",
5759 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5761 if (ctl && ctl->enable) {
5763 ctl->muted = HDA_AMP_MUTE_ALL;
5769 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
5770 HDA_CTL_OUT, -1, 1);
5771 if (ctl && ctl->enable) {
5773 ctl->muted = HDA_AMP_MUTE_ALL;
5778 for (k = devinfo->startnode; k < devinfo->endnode; k++) {
5779 cw = hdac_widget_get(devinfo, k);
5780 if (cw == NULL || cw->enable == 0)
5782 for (j = 0; j < cw->nconns; j++) {
5783 if (cw->connsenable[j] && cw->conns[j] == i) {
5784 cw->connsenable[j] = 0;
5786 device_printf(devinfo->codec->sc->dev,
5787 " Disabling connection from output pin "
5788 "nid %d conn %d cnid %d.\n",
5791 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
5794 ctl = hdac_audio_ctl_amp_get(devinfo, k,
5796 if (ctl && ctl->enable) {
5798 ctl->muted = HDA_AMP_MUTE_ALL;
5811 hdac_audio_disable_notselected(struct hdac_devinfo *devinfo)
5813 struct hdac_audio_as *as = devinfo->function.audio.as;
5814 struct hdac_widget *w;
5817 /* On playback path we can safely disable all unseleted inputs. */
5818 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5819 w = hdac_widget_get(devinfo, i);
5820 if (w == NULL || w->enable == 0)
5824 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5826 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN)
5828 for (j = 0; j < w->nconns; j++) {
5829 if (w->connsenable[j] == 0)
5831 if (w->selconn < 0 || w->selconn == j)
5833 w->connsenable[j] = 0;
5835 device_printf(devinfo->codec->sc->dev,
5836 " Disabling unselected connection "
5837 "nid %d conn %d.\n",
5845 hdac_audio_disable_crossas(struct hdac_devinfo *devinfo)
5847 struct hdac_audio_as *ases = devinfo->function.audio.as;
5848 struct hdac_widget *w, *cw;
5849 struct hdac_audio_ctl *ctl;
5852 /* Disable crossassociatement and unwanted crosschannel connections. */
5853 /* ... using selectors */
5854 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5855 w = hdac_widget_get(devinfo, i);
5856 if (w == NULL || w->enable == 0)
5860 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
5862 if (w->bindas == -2)
5864 for (j = 0; j < w->nconns; j++) {
5865 if (w->connsenable[j] == 0)
5867 cw = hdac_widget_get(devinfo, w->conns[j]);
5868 if (cw == NULL || w->enable == 0)
5870 if (cw->bindas == -2 ||
5871 ((w->pflags & HDA_ADC_MONITOR) &&
5873 ases[cw->bindas].dir == HDA_CTL_IN))
5875 if (w->bindas == cw->bindas &&
5876 (w->bindseqmask & cw->bindseqmask) != 0)
5878 w->connsenable[j] = 0;
5880 device_printf(devinfo->codec->sc->dev,
5881 " Disabling crossassociatement connection "
5882 "nid %d conn %d cnid %d.\n",
5887 /* ... using controls */
5889 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
5890 if (ctl->enable == 0 || ctl->childwidget == NULL)
5892 if (ctl->widget->bindas == -2)
5894 if (ctl->childwidget->bindas == -2 ||
5895 ((ctl->widget->pflags & HDA_ADC_MONITOR) &&
5896 ctl->childwidget->bindas >= 0 &&
5897 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN))
5899 if (ctl->widget->bindas != ctl->childwidget->bindas ||
5900 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) {
5902 ctl->muted = HDA_AMP_MUTE_ALL;
5906 if (ctl->ndir == HDA_CTL_IN)
5907 ctl->widget->connsenable[ctl->index] = 0;
5909 device_printf(devinfo->codec->sc->dev,
5910 " Disabling crossassociatement connection "
5911 "ctl %d nid %d cnid %d.\n", i,
5913 ctl->childwidget->nid);
5920 #define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0)
5923 * Find controls to control amplification for source.
5926 hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index,
5927 int ossdev, int ctlable, int depth, int need)
5929 struct hdac_widget *w, *wc;
5930 struct hdac_audio_ctl *ctl;
5931 int i, j, conns = 0, rneed;
5933 if (depth > HDA_PARSE_MAXDEPTH)
5936 w = hdac_widget_get(devinfo, nid);
5937 if (w == NULL || w->enable == 0)
5940 /* Count number of active inputs. */
5942 for (j = 0; j < w->nconns; j++) {
5943 if (w->connsenable[j])
5948 /* If this is not a first step - use input mixer.
5949 Pins have common input ctl so care must be taken. */
5950 if (depth > 0 && ctlable && (conns == 1 ||
5951 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) {
5952 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN,
5955 if (HDA_CTL_GIVE(ctl) & need)
5956 ctl->ossmask |= (1 << ossdev);
5958 ctl->possmask |= (1 << ossdev);
5959 need &= ~HDA_CTL_GIVE(ctl);
5963 /* If widget has own ossdev - not traverse it.
5964 It will be traversed on it's own. */
5965 if (w->ossdev >= 0 && depth > 0)
5968 /* We must not traverse pin */
5969 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT ||
5970 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) &&
5974 /* record that this widget exports such signal, */
5975 w->ossmask |= (1 << ossdev);
5977 /* If signals mixed, we can't assign controls farther.
5978 * Ignore this on depth zero. Caller must knows why.
5979 * Ignore this for static selectors if this input selected.
5985 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1);
5987 if (HDA_CTL_GIVE(ctl) & need)
5988 ctl->ossmask |= (1 << ossdev);
5990 ctl->possmask |= (1 << ossdev);
5991 need &= ~HDA_CTL_GIVE(ctl);
5996 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
5997 wc = hdac_widget_get(devinfo, i);
5998 if (wc == NULL || wc->enable == 0)
6000 for (j = 0; j < wc->nconns; j++) {
6001 if (wc->connsenable[j] && wc->conns[j] == nid) {
6002 rneed |= hdac_audio_ctl_source_amp(devinfo,
6003 wc->nid, j, ossdev, ctlable, depth + 1, need);
6013 * Find controls to control amplification for destination.
6016 hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index,
6017 int ossdev, int depth, int need)
6019 struct hdac_audio_as *as = devinfo->function.audio.as;
6020 struct hdac_widget *w, *wc;
6021 struct hdac_audio_ctl *ctl;
6022 int i, j, consumers;
6024 if (depth > HDA_PARSE_MAXDEPTH)
6027 w = hdac_widget_get(devinfo, nid);
6028 if (w == NULL || w->enable == 0)
6032 /* If this node produce output for several consumers,
6033 we can't touch it. */
6035 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6036 wc = hdac_widget_get(devinfo, i);
6037 if (wc == NULL || wc->enable == 0)
6039 for (j = 0; j < wc->nconns; j++) {
6040 if (wc->connsenable[j] && wc->conns[j] == nid)
6044 /* The only exception is if real HP redirection is configured
6045 and this is a duplication point.
6046 XXX: Actually exception is not completely correct.
6047 XXX: Duplication point check is not perfect. */
6048 if ((consumers == 2 && (w->bindas < 0 ||
6049 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir ||
6050 (w->bindseqmask & (1 << 15)) == 0)) ||
6054 /* Else use it's output mixer. */
6055 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
6056 HDA_CTL_OUT, -1, 1);
6058 if (HDA_CTL_GIVE(ctl) & need)
6059 ctl->ossmask |= (1 << ossdev);
6061 ctl->possmask |= (1 << ossdev);
6062 need &= ~HDA_CTL_GIVE(ctl);
6066 /* We must not traverse pin */
6067 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6071 for (i = 0; i < w->nconns; i++) {
6073 if (w->connsenable[i] == 0)
6075 if (index >= 0 && i != index)
6077 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid,
6080 if (HDA_CTL_GIVE(ctl) & tneed)
6081 ctl->ossmask |= (1 << ossdev);
6083 ctl->possmask |= (1 << ossdev);
6084 tneed &= ~HDA_CTL_GIVE(ctl);
6086 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev,
6092 * Assign OSS names to sound sources
6095 hdac_audio_assign_names(struct hdac_devinfo *devinfo)
6097 struct hdac_audio_as *as = devinfo->function.audio.as;
6098 struct hdac_widget *w;
6100 int type = -1, use, used = 0;
6101 static const int types[7][13] = {
6102 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
6103 SOUND_MIXER_LINE3, -1 }, /* line */
6104 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */
6105 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */
6106 { SOUND_MIXER_CD, -1 }, /* cd */
6107 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */
6108 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3,
6110 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2,
6111 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT,
6112 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1,
6113 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR,
6117 /* Surely known names */
6118 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6119 w = hdac_widget_get(devinfo, i);
6120 if (w == NULL || w->enable == 0)
6122 if (w->bindas == -1)
6126 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX:
6127 if (as[w->bindas].dir == HDA_CTL_OUT)
6130 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
6131 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN:
6134 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
6135 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK)
6136 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK)
6140 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD:
6143 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
6146 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN:
6147 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN:
6154 while (types[type][j] >= 0 &&
6155 (used & (1 << types[type][j])) != 0) {
6158 if (types[type][j] >= 0)
6159 use = types[type][j];
6161 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT:
6162 use = SOUND_MIXER_PCM;
6164 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET:
6165 use = SOUND_MIXER_SPEAKER;
6175 /* Semi-known names */
6176 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6177 w = hdac_widget_get(devinfo, i);
6178 if (w == NULL || w->enable == 0)
6182 if (w->bindas == -1)
6184 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6186 if (as[w->bindas].dir == HDA_CTL_OUT)
6189 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) {
6190 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT:
6191 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER:
6192 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT:
6193 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX:
6196 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN:
6199 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT:
6200 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT:
6207 while (types[type][j] >= 0 &&
6208 (used & (1 << types[type][j])) != 0) {
6211 if (types[type][j] >= 0) {
6212 w->ossdev = types[type][j];
6213 used |= (1 << types[type][j]);
6217 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6218 w = hdac_widget_get(devinfo, i);
6219 if (w == NULL || w->enable == 0)
6223 if (w->bindas == -1)
6225 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6227 if (as[w->bindas].dir == HDA_CTL_OUT)
6230 while (types[6][j] >= 0 &&
6231 (used & (1 << types[6][j])) != 0) {
6234 if (types[6][j] >= 0) {
6235 w->ossdev = types[6][j];
6236 used |= (1 << types[6][j]);
6242 hdac_audio_build_tree(struct hdac_devinfo *devinfo)
6244 struct hdac_audio_as *as = devinfo->function.audio.as;
6247 /* Trace all associations in order of their numbers, */
6248 for (j = 0; j < devinfo->function.audio.ascnt; j++) {
6249 if (as[j].enable == 0)
6252 device_printf(devinfo->codec->sc->dev,
6253 "Tracing association %d (%d)\n", j, as[j].index);
6255 if (as[j].dir == HDA_CTL_OUT) {
6257 res = hdac_audio_trace_as_out(devinfo, j, 0);
6258 if (res == 0 && as[j].hpredir >= 0 &&
6259 as[j].fakeredir == 0) {
6260 /* If codec can't do analog HP redirection
6261 try to make it using one more DAC. */
6262 as[j].fakeredir = 1;
6266 res = hdac_audio_trace_as_in(devinfo, j);
6270 device_printf(devinfo->codec->sc->dev,
6271 "Association %d (%d) trace succeeded\n",
6276 device_printf(devinfo->codec->sc->dev,
6277 "Association %d (%d) trace failed\n",
6284 /* Trace mixer and beeper pseudo associations. */
6285 hdac_audio_trace_as_extra(devinfo);
6289 hdac_audio_assign_mixers(struct hdac_devinfo *devinfo)
6291 struct hdac_audio_as *as = devinfo->function.audio.as;
6292 struct hdac_audio_ctl *ctl;
6293 struct hdac_widget *w, *cw;
6296 /* Assign mixers to the tree. */
6297 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6298 w = hdac_widget_get(devinfo, i);
6299 if (w == NULL || w->enable == 0)
6301 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
6302 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET ||
6303 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6304 as[w->bindas].dir == HDA_CTL_IN)) {
6307 hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6308 w->ossdev, 1, 0, 1);
6309 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
6310 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6311 SOUND_MIXER_RECLEV, 0, 1);
6312 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX &&
6313 as[w->bindas].dir == HDA_CTL_OUT) {
6314 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6315 SOUND_MIXER_VOLUME, 0, 1);
6317 if (w->ossdev == SOUND_MIXER_IMIX) {
6318 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1,
6319 w->ossdev, 1, 0, 1)) {
6320 /* If we are unable to control input monitor
6321 as source - try to control it as destination. */
6322 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1,
6326 if (w->pflags & HDA_ADC_MONITOR) {
6327 for (j = 0; j < w->nconns; j++) {
6328 if (!w->connsenable[j])
6330 cw = hdac_widget_get(devinfo, w->conns[j]);
6331 if (cw == NULL || cw->enable == 0)
6333 if (cw->bindas == -1)
6335 if (cw->bindas >= 0 &&
6336 as[cw->bindas].dir != HDA_CTL_IN)
6338 hdac_audio_ctl_dest_amp(devinfo,
6339 w->nid, j, SOUND_MIXER_IGAIN, 0, 1);
6343 /* Treat unrequired as possible. */
6345 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6346 if (ctl->ossmask == 0)
6347 ctl->ossmask = ctl->possmask;
6352 hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo)
6354 struct hdac_audio_as *as = devinfo->function.audio.as;
6355 struct hdac_widget *w;
6359 for (i = 0; i < devinfo->nodecnt; i++) {
6360 w = &devinfo->widget[i];
6363 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
6366 pincap = w->wclass.pin.cap;
6368 /* Disable everything. */
6369 w->wclass.pin.ctrl &= ~(
6370 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE |
6371 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE |
6372 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE |
6373 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK);
6375 if (w->enable == 0 ||
6376 w->bindas < 0 || as[w->bindas].enable == 0) {
6377 /* Pin is unused so left it disabled. */
6379 } else if (as[w->bindas].dir == HDA_CTL_IN) {
6380 /* Input pin, configure for input. */
6381 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6382 w->wclass.pin.ctrl |=
6383 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE;
6385 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) &&
6386 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6387 w->wclass.pin.ctrl |=
6388 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6389 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6390 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) &&
6391 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6392 w->wclass.pin.ctrl |=
6393 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6394 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6395 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) &&
6396 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6397 w->wclass.pin.ctrl |=
6398 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6399 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6401 /* Output pin, configure for output. */
6402 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6403 w->wclass.pin.ctrl |=
6404 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE;
6406 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) &&
6407 (w->wclass.pin.config &
6408 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) ==
6409 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT)
6410 w->wclass.pin.ctrl |=
6411 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE;
6413 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) &&
6414 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6415 w->wclass.pin.ctrl |=
6416 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6417 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100);
6418 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) &&
6419 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6420 w->wclass.pin.ctrl |=
6421 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6422 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80);
6423 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) &&
6424 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6425 w->wclass.pin.ctrl |=
6426 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE(
6427 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50);
6433 hdac_audio_ctl_commit(struct hdac_devinfo *devinfo)
6435 struct hdac_audio_ctl *ctl;
6439 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6440 if (ctl->enable == 0 || ctl->ossmask != 0) {
6441 /* Mute disabled and mixer controllable controls.
6442 * Last will be initialized by mixer_init().
6443 * This expected to reduce click on startup. */
6444 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0);
6447 /* Init fixed controls to 0dB amplification. */
6451 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z);
6456 hdac_audio_commit(struct hdac_devinfo *devinfo)
6458 struct hdac_softc *sc = devinfo->codec->sc;
6459 struct hdac_widget *w;
6461 uint32_t gdata, gmask, gdir;
6462 int commitgpio, numgpio;
6465 cad = devinfo->codec->cad;
6467 if (sc->pci_subvendor == APPLE_INTEL_MAC)
6468 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid,
6471 /* Commit controls. */
6472 hdac_audio_ctl_commit(devinfo);
6474 /* Commit selectors, pins and EAPD. */
6475 for (i = 0; i < devinfo->nodecnt; i++) {
6476 w = &devinfo->widget[i];
6479 if (w->selconn == -1)
6482 hdac_widget_connection_select(w, w->selconn);
6483 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) {
6485 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid,
6486 w->wclass.pin.ctrl), cad);
6488 if (w->param.eapdbtl != HDAC_INVALID) {
6491 val = w->param.eapdbtl;
6492 if (devinfo->function.audio.quirks &
6494 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD;
6496 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid,
6506 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO(
6507 devinfo->function.audio.gpio);
6509 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH)
6510 commitgpio = (numgpio > 0) ? 1 : 0;
6512 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) {
6513 if (!(devinfo->function.audio.quirks &
6516 if (commitgpio == 0) {
6519 gdata = hdac_command(sc,
6520 HDA_CMD_GET_GPIO_DATA(cad,
6521 devinfo->nid), cad);
6522 gmask = hdac_command(sc,
6523 HDA_CMD_GET_GPIO_ENABLE_MASK(cad,
6524 devinfo->nid), cad);
6525 gdir = hdac_command(sc,
6526 HDA_CMD_GET_GPIO_DIRECTION(cad,
6527 devinfo->nid), cad);
6528 device_printf(sc->dev,
6529 "GPIO init: data=0x%08x "
6530 "mask=0x%08x dir=0x%08x\n",
6531 gdata, gmask, gdir);
6543 if (commitgpio != 0) {
6545 device_printf(sc->dev,
6546 "GPIO commit: data=0x%08x mask=0x%08x "
6548 gdata, gmask, gdir);
6551 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid,
6554 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid,
6557 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid,
6563 hdac_powerup(struct hdac_devinfo *devinfo)
6565 struct hdac_softc *sc = devinfo->codec->sc;
6566 nid_t cad = devinfo->codec->cad;
6570 HDA_CMD_SET_POWER_STATE(cad,
6571 devinfo->nid, HDA_CMD_POWER_STATE_D0),
6575 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
6577 HDA_CMD_SET_POWER_STATE(cad,
6578 i, HDA_CMD_POWER_STATE_D0),
6585 hdac_pcmchannel_setup(struct hdac_chan *ch)
6587 struct hdac_devinfo *devinfo = ch->devinfo;
6588 struct hdac_audio_as *as = devinfo->function.audio.as;
6589 struct hdac_widget *w;
6590 uint32_t cap, fmtcap, pcmcap;
6591 int i, j, ret, channels, onlystereo;
6594 ch->caps = hdac_caps;
6595 ch->caps.fmtlist = ch->fmtlist;
6598 ch->pcmrates[0] = 48000;
6599 ch->pcmrates[1] = 0;
6605 fmtcap = devinfo->function.audio.supp_stream_formats;
6606 pcmcap = devinfo->function.audio.supp_pcm_size_rate;
6608 for (i = 0; i < 16; i++) {
6609 /* Check as is correct */
6612 /* Cound only present DACs */
6613 if (as[ch->as].dacs[i] <= 0)
6615 /* Ignore duplicates */
6616 for (j = 0; j < ret; j++) {
6617 if (ch->io[j] == as[ch->as].dacs[i])
6623 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]);
6624 if (w == NULL || w->enable == 0)
6626 cap = w->param.supp_stream_formats;
6627 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) &&
6628 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6630 /* Many CODECs does not declare AC3 support on SPDIF.
6631 I don't beleave that they doesn't support it! */
6632 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
6633 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK;
6636 pcmcap = w->param.supp_pcm_size_rate;
6639 pcmcap &= w->param.supp_pcm_size_rate;
6641 ch->io[ret++] = as[ch->as].dacs[i];
6642 /* Do not count redirection pin/dac channels. */
6643 if (i == 15 && as[ch->as].hpredir >= 0)
6645 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1;
6646 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1)
6652 if (as[ch->as].fakeredir)
6654 /* Standard speaks only about stereo pins and playback, ... */
6655 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT)
6657 /* ..., but there it gives us info about speakers layout. */
6658 as[ch->as].pinset = pinset;
6660 ch->supp_stream_formats = fmtcap;
6661 ch->supp_pcm_size_rate = pcmcap;
6672 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) {
6673 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap))
6675 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap))
6677 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap))
6679 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap))
6681 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap))
6683 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) {
6684 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0);
6686 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0);
6688 if (channels >= 2) {
6689 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0);
6691 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0);
6693 if (channels == 4 || /* Any 4-channel */
6694 pinset == 0x0007 || /* 5.1 */
6695 pinset == 0x0013 || /* 5.1 */
6696 pinset == 0x0017) { /* 7.1 */
6697 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0);
6699 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0);
6701 if (channels == 6 || /* Any 6-channel */
6702 pinset == 0x0017) { /* 7.1 */
6703 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1);
6705 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1);
6707 if (channels == 8) { /* Any 8-channel */
6708 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1);
6710 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1);
6713 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) {
6714 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0);
6718 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap))
6719 ch->pcmrates[i++] = 8000;
6720 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap))
6721 ch->pcmrates[i++] = 11025;
6722 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap))
6723 ch->pcmrates[i++] = 16000;
6724 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap))
6725 ch->pcmrates[i++] = 22050;
6726 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap))
6727 ch->pcmrates[i++] = 32000;
6728 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap))
6729 ch->pcmrates[i++] = 44100;
6730 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */
6731 ch->pcmrates[i++] = 48000;
6732 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap))
6733 ch->pcmrates[i++] = 88200;
6734 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap))
6735 ch->pcmrates[i++] = 96000;
6736 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap))
6737 ch->pcmrates[i++] = 176400;
6738 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap))
6739 ch->pcmrates[i++] = 192000;
6740 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */
6741 ch->pcmrates[i] = 0;
6743 ch->caps.minspeed = ch->pcmrates[0];
6744 ch->caps.maxspeed = ch->pcmrates[i - 1];
6752 hdac_create_pcms(struct hdac_devinfo *devinfo)
6754 struct hdac_softc *sc = devinfo->codec->sc;
6755 struct hdac_audio_as *as = devinfo->function.audio.as;
6756 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0;
6758 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6759 if (as[i].enable == 0)
6761 if (as[i].dir == HDA_CTL_IN) {
6773 devinfo->function.audio.num_devs =
6774 max(ardev, apdev) + max(drdev, dpdev);
6775 devinfo->function.audio.devs =
6776 (struct hdac_pcm_devinfo *)malloc(
6777 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo),
6778 M_HDAC, M_ZERO | M_NOWAIT);
6779 if (devinfo->function.audio.devs == NULL) {
6780 device_printf(sc->dev,
6781 "Unable to allocate memory for devices\n");
6784 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6785 devinfo->function.audio.devs[i].index = i;
6786 devinfo->function.audio.devs[i].devinfo = devinfo;
6787 devinfo->function.audio.devs[i].play = -1;
6788 devinfo->function.audio.devs[i].rec = -1;
6789 devinfo->function.audio.devs[i].digital = 255;
6791 for (i = 0; i < devinfo->function.audio.ascnt; i++) {
6792 if (as[i].enable == 0)
6794 for (j = 0; j < devinfo->function.audio.num_devs; j++) {
6795 if (devinfo->function.audio.devs[j].digital != 255 &&
6796 (!devinfo->function.audio.devs[j].digital) !=
6799 if (as[i].dir == HDA_CTL_IN) {
6800 if (devinfo->function.audio.devs[j].rec >= 0)
6802 devinfo->function.audio.devs[j].rec
6805 if (devinfo->function.audio.devs[j].play >= 0)
6807 devinfo->function.audio.devs[j].play
6810 sc->chans[as[i].chan].pdevinfo =
6811 &devinfo->function.audio.devs[j];
6812 devinfo->function.audio.devs[j].digital =
6817 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
6818 struct hdac_pcm_devinfo *pdevinfo =
6819 &devinfo->function.audio.devs[i];
6821 device_add_child(sc->dev, "pcm", -1);
6822 device_set_ivars(pdevinfo->dev,
6828 hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag)
6830 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
6831 struct hdac_audio_ctl *ctl;
6832 struct hdac_softc *sc = devinfo->codec->sc;
6837 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM |
6838 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV |
6839 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN |
6840 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR);
6843 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) {
6844 if ((flag & (1 << j)) == 0)
6848 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
6849 if (ctl->enable == 0 ||
6850 ctl->widget->enable == 0)
6852 if (!((pdevinfo->play >= 0 &&
6853 ctl->widget->bindas == sc->chans[pdevinfo->play].as) ||
6854 (pdevinfo->rec >= 0 &&
6855 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) ||
6856 (ctl->widget->bindas == -2 && pdevinfo->index == 0)))
6858 if ((ctl->ossmask & (1 << j)) == 0)
6862 device_printf(pdevinfo->dev, "\n");
6863 if (banner != NULL) {
6864 device_printf(pdevinfo->dev, "%s", banner);
6866 device_printf(pdevinfo->dev, "Unknown Ctl");
6868 printf(" (OSS: %s)\n",
6869 hdac_audio_ctl_ossmixer_mask2allname(1 << j,
6871 device_printf(pdevinfo->dev, " |\n");
6874 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i,
6876 (ctl->ndir == HDA_CTL_IN)?"in ":"out");
6877 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir)
6878 printf(" %2d): ", ctl->index);
6881 if (ctl->step > 0) {
6882 printf("%+d/%+ddB (%d steps)%s\n",
6883 (0 - ctl->offset) * (ctl->size + 1) / 4,
6884 (ctl->step - ctl->offset) * (ctl->size + 1) / 4,
6886 ctl->mute?" + mute":"");
6888 printf("%s\n", ctl->mute?"mute":"");
6894 hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap)
6900 device_printf(dev, " Stream cap: 0x%08x\n", cap);
6901 device_printf(dev, " ");
6902 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap))
6904 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap))
6906 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap))
6912 device_printf(dev, " PCM cap: 0x%08x\n", cap);
6913 device_printf(dev, " ");
6914 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap))
6916 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap))
6918 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap))
6920 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap))
6922 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap))
6925 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap))
6927 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap))
6929 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap))
6931 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap))
6933 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap))
6935 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap))
6938 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap))
6940 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap))
6942 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap))
6944 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap))
6951 hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w)
6955 pincap = w->wclass.pin.cap;
6957 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap);
6958 device_printf(sc->dev, " ");
6959 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap))
6961 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap))
6963 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap))
6965 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap))
6967 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap))
6969 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap))
6971 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap))
6973 if (HDA_PARAM_PIN_CAP_HDMI(pincap))
6975 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) {
6977 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap))
6979 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap))
6981 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap))
6983 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap))
6985 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap))
6989 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap))
6991 if (HDA_PARAM_PIN_CAP_DP(pincap))
6993 if (HDA_PARAM_PIN_CAP_HBR(pincap))
6996 device_printf(sc->dev, " Pin config: 0x%08x\n",
6997 w->wclass.pin.config);
6998 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl);
6999 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE)
7001 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE)
7003 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE)
7005 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK)
7011 hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf)
7013 struct hdac_softc *sc = w->devinfo->codec->sc;
7015 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s "
7016 "jack %2d loc %2d color %7s misc %d%s\n",
7018 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf),
7019 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf),
7020 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)],
7021 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)],
7022 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf),
7023 HDA_CONFIG_DEFAULTCONF_LOCATION(conf),
7024 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)],
7025 HDA_CONFIG_DEFAULTCONF_MISC(conf),
7026 (w->enable == 0)?" [DISABLED]":"");
7030 hdac_dump_pin_configs(struct hdac_devinfo *devinfo)
7032 struct hdac_widget *w;
7035 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7036 w = hdac_widget_get(devinfo, i);
7039 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7041 hdac_dump_pin_config(w, w->wclass.pin.config);
7046 hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner)
7048 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap);
7049 device_printf(sc->dev, " "
7050 "mute=%d step=%d size=%d offset=%d\n",
7051 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap),
7052 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap),
7053 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap),
7054 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap));
7058 hdac_dump_nodes(struct hdac_devinfo *devinfo)
7060 struct hdac_softc *sc = devinfo->codec->sc;
7061 static char *ossname[] = SOUND_DEVICE_NAMES;
7062 struct hdac_widget *w, *cw;
7066 device_printf(sc->dev, "\n");
7067 device_printf(sc->dev, "Default Parameter\n");
7068 device_printf(sc->dev, "-----------------\n");
7069 hdac_dump_audio_formats(sc->dev,
7070 devinfo->function.audio.supp_stream_formats,
7071 devinfo->function.audio.supp_pcm_size_rate);
7072 device_printf(sc->dev, " IN amp: 0x%08x\n",
7073 devinfo->function.audio.inamp_cap);
7074 device_printf(sc->dev, " OUT amp: 0x%08x\n",
7075 devinfo->function.audio.outamp_cap);
7076 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7077 w = hdac_widget_get(devinfo, i);
7079 device_printf(sc->dev, "Ghost widget nid=%d\n", i);
7082 device_printf(sc->dev, "\n");
7083 device_printf(sc->dev, " nid: %d%s\n", w->nid,
7084 (w->enable == 0) ? " [DISABLED]" : "");
7085 device_printf(sc->dev, " Name: %s\n", w->name);
7086 device_printf(sc->dev, " Widget cap: 0x%08x\n",
7087 w->param.widget_cap);
7088 if (w->param.widget_cap & 0x0ee1) {
7089 device_printf(sc->dev, " ");
7090 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap))
7092 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap))
7094 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap))
7096 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap))
7098 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap))
7100 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap))
7102 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap);
7106 printf(" %dCH", j + 1);
7109 if (w->bindas != -1) {
7110 device_printf(sc->dev, " Association: %d (0x%08x)\n",
7111 w->bindas, w->bindseqmask);
7113 if (w->ossmask != 0 || w->ossdev >= 0) {
7114 device_printf(sc->dev, " OSS: %s",
7115 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf)));
7117 printf(" (%s)", ossname[w->ossdev]);
7120 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT ||
7121 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) {
7122 hdac_dump_audio_formats(sc->dev,
7123 w->param.supp_stream_formats,
7124 w->param.supp_pcm_size_rate);
7125 } else if (w->type ==
7126 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7127 hdac_dump_pin(sc, w);
7128 if (w->param.eapdbtl != HDAC_INVALID)
7129 device_printf(sc->dev, " EAPD: 0x%08x\n",
7131 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) &&
7132 w->param.outamp_cap != 0)
7133 hdac_dump_amp(sc, w->param.outamp_cap, "Output");
7134 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) &&
7135 w->param.inamp_cap != 0)
7136 hdac_dump_amp(sc, w->param.inamp_cap, " Input");
7137 if (w->nconns > 0) {
7138 device_printf(sc->dev, " connections: %d\n", w->nconns);
7139 device_printf(sc->dev, " |\n");
7141 for (j = 0; j < w->nconns; j++) {
7142 cw = hdac_widget_get(devinfo, w->conns[j]);
7143 device_printf(sc->dev, " + %s<- nid=%d [%s]",
7144 (w->connsenable[j] == 0)?"[DISABLED] ":"",
7145 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name);
7147 printf(" [UNKNOWN]");
7148 else if (cw->enable == 0)
7149 printf(" [DISABLED]");
7150 if (w->nconns > 1 && w->selconn == j && w->type !=
7151 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER)
7152 printf(" (selected)");
7160 hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth)
7162 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7163 struct hdac_widget *w, *cw;
7167 if (depth > HDA_PARSE_MAXDEPTH)
7170 w = hdac_widget_get(devinfo, nid);
7171 if (w == NULL || w->enable == 0)
7175 device_printf(pdevinfo->dev, "%*s", 4, "");
7177 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, "");
7178 printf("nid=%d [%s]", w->nid, w->name);
7181 if (w->ossmask == 0) {
7185 printf(" [src: %s]",
7186 hdac_audio_ctl_ossmixer_mask2allname(
7187 w->ossmask, buf, sizeof(buf)));
7188 if (w->ossdev >= 0) {
7195 for (i = 0; i < w->nconns; i++) {
7196 if (w->connsenable[i] == 0)
7198 cw = hdac_widget_get(devinfo, w->conns[i]);
7199 if (cw == NULL || cw->enable == 0 || cw->bindas == -1)
7202 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, "");
7205 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1);
7211 hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo)
7213 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7214 struct hdac_softc *sc = devinfo->codec->sc;
7215 struct hdac_audio_as *as;
7216 struct hdac_widget *w;
7219 if (pdevinfo->play < 0)
7222 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as];
7223 for (i = 0; i < 16; i++) {
7224 if (as->pins[i] <= 0)
7226 w = hdac_widget_get(devinfo, as->pins[i]);
7227 if (w == NULL || w->enable == 0)
7231 device_printf(pdevinfo->dev, "\n");
7232 device_printf(pdevinfo->dev, "Playback:\n");
7234 device_printf(pdevinfo->dev, "\n");
7235 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0);
7240 hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo)
7242 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7243 struct hdac_softc *sc = devinfo->codec->sc;
7244 struct hdac_widget *w;
7248 if (pdevinfo->rec < 0)
7251 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7252 w = hdac_widget_get(devinfo, i);
7253 if (w == NULL || w->enable == 0)
7255 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT)
7257 if (w->bindas != sc->chans[pdevinfo->rec].as)
7261 device_printf(pdevinfo->dev, "\n");
7262 device_printf(pdevinfo->dev, "Record:\n");
7264 device_printf(pdevinfo->dev, "\n");
7265 hdac_dump_dst_nid(pdevinfo, i, 0);
7270 hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo)
7272 struct hdac_devinfo *devinfo = pdevinfo->devinfo;
7273 struct hdac_widget *w;
7277 if (pdevinfo->index != 0)
7280 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7281 w = hdac_widget_get(devinfo, i);
7282 if (w == NULL || w->enable == 0)
7284 if (w->ossdev != SOUND_MIXER_IMIX)
7288 device_printf(pdevinfo->dev, "\n");
7289 device_printf(pdevinfo->dev, "Input Mix:\n");
7291 device_printf(pdevinfo->dev, "\n");
7292 hdac_dump_dst_nid(pdevinfo, i, 0);
7297 hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo)
7299 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
7303 if (pdevinfo->play >= 0) {
7305 device_printf(pdevinfo->dev, "\n");
7306 device_printf(pdevinfo->dev, "Playback:\n");
7307 device_printf(pdevinfo->dev, "\n");
7308 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7309 sc->chans[i].supp_pcm_size_rate);
7310 device_printf(pdevinfo->dev, " DAC:");
7311 for (nids = sc->chans[i].io; *nids != -1; nids++)
7312 printf(" %d", *nids);
7315 if (pdevinfo->rec >= 0) {
7317 device_printf(pdevinfo->dev, "\n");
7318 device_printf(pdevinfo->dev, "Record:\n");
7319 device_printf(pdevinfo->dev, "\n");
7320 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats,
7321 sc->chans[i].supp_pcm_size_rate);
7322 device_printf(pdevinfo->dev, " ADC:");
7323 for (nids = sc->chans[i].io; *nids != -1; nids++)
7324 printf(" %d", *nids);
7330 hdac_release_resources(struct hdac_softc *sc)
7340 callout_stop(&sc->poll_hda);
7341 callout_stop(&sc->poll_hdac);
7342 callout_stop(&sc->poll_jack);
7345 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7346 callout_drain(&sc->poll_hda);
7347 callout_drain(&sc->poll_hdac);
7348 callout_drain(&sc->poll_jack);
7352 for (i = 0; i < HDAC_CODEC_MAX; i++) {
7353 if (sc->codecs[i] == NULL)
7355 for (j = 0; j < sc->codecs[i]->num_fgs; j++) {
7356 free(sc->codecs[i]->fgs[j].widget, M_HDAC);
7357 if (sc->codecs[i]->fgs[j].node_type ==
7358 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7359 free(sc->codecs[i]->fgs[j].function.audio.ctl,
7361 free(sc->codecs[i]->fgs[j].function.audio.as,
7363 free(sc->codecs[i]->fgs[j].function.audio.devs,
7367 free(sc->codecs[i]->fgs, M_HDAC);
7368 free(sc->codecs[i], M_HDAC);
7369 sc->codecs[i] = NULL;
7372 hdac_dma_free(sc, &sc->pos_dma);
7373 hdac_dma_free(sc, &sc->rirb_dma);
7374 hdac_dma_free(sc, &sc->corb_dma);
7375 for (i = 0; i < sc->num_chans; i++) {
7376 if (sc->chans[i].blkcnt > 0)
7377 hdac_dma_free(sc, &sc->chans[i].bdl_dma);
7379 free(sc->chans, M_HDAC);
7380 if (sc->chan_dmat != NULL) {
7381 bus_dma_tag_destroy(sc->chan_dmat);
7382 sc->chan_dmat = NULL;
7385 snd_mtxfree(sc->lock);
7388 /* This function surely going to make its way into upper level someday. */
7390 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
7392 const char *res = NULL;
7393 int i = 0, j, k, len, inv;
7401 if (resource_string_value(device_get_name(sc->dev),
7402 device_get_unit(sc->dev), "config", &res) != 0)
7404 if (!(res != NULL && strlen(res) > 0))
7407 device_printf(sc->dev, "HDA Config:");
7410 while (res[i] != '\0' &&
7411 (res[i] == ',' || isspace(res[i]) != 0))
7413 if (res[i] == '\0') {
7420 while (res[j] != '\0' &&
7421 !(res[j] == ',' || isspace(res[j]) != 0))
7424 if (len > 2 && strncmp(res + i, "no", 2) == 0)
7428 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) {
7429 if (strncmp(res + i + inv,
7430 hdac_quirks_tab[k].key, len - inv) != 0)
7432 if (len - inv != strlen(hdac_quirks_tab[k].key))
7435 printf(" %s%s", (inv != 0) ? "no" : "",
7436 hdac_quirks_tab[k].key);
7438 if (inv == 0 && on != NULL)
7439 *on |= hdac_quirks_tab[k].value;
7440 else if (inv != 0 && off != NULL)
7441 *off |= hdac_quirks_tab[k].value;
7449 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
7451 struct hdac_softc *sc;
7456 dev = oidp->oid_arg1;
7457 sc = device_get_softc(dev);
7463 err = sysctl_handle_int(oidp, &val, 0, req);
7465 if (err != 0 || req->newptr == NULL)
7467 if (val < 0 || val > 1)
7471 if (val != sc->polling) {
7473 callout_stop(&sc->poll_hda);
7474 callout_stop(&sc->poll_hdac);
7476 callout_drain(&sc->poll_hda);
7477 callout_drain(&sc->poll_hdac);
7480 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7481 ctl |= HDAC_INTCTL_GIE;
7482 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7484 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
7485 ctl &= ~HDAC_INTCTL_GIE;
7486 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
7488 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7491 hdac_poll_reinit(sc);
7492 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7501 sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS)
7503 struct hdac_softc *sc;
7507 dev = oidp->oid_arg1;
7508 sc = device_get_softc(dev);
7512 val = ((uint64_t)sc->poll_ival * 1000) / hz;
7514 err = sysctl_handle_int(oidp, &val, 0, req);
7516 if (err != 0 || req->newptr == NULL)
7523 val = ((uint64_t)val * hz) / 1000;
7530 sc->poll_ival = val;
7537 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
7539 struct hdac_softc *sc;
7540 struct hdac_codec *codec;
7541 struct hdac_devinfo *devinfo;
7542 struct hdac_widget *w;
7544 uint32_t res, pincap, delay;
7545 int codec_index, fg_index;
7549 dev = oidp->oid_arg1;
7550 sc = device_get_softc(dev);
7554 err = sysctl_handle_int(oidp, &val, 0, req);
7555 if (err != 0 || req->newptr == NULL || val == 0)
7558 /* XXX: Temporary. For debugging. */
7562 } else if (val == 101) {
7568 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7569 codec = sc->codecs[codec_index];
7573 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7574 devinfo = &codec->fgs[fg_index];
7575 if (devinfo->node_type !=
7576 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO)
7579 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n",
7580 codec_index, devinfo->nid);
7581 for (i = devinfo->startnode; i < devinfo->endnode; i++) {
7582 w = hdac_widget_get(devinfo, i);
7583 if (w == NULL || w->type !=
7584 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)
7586 hdac_dump_pin_config(w, w->wclass.pin.config);
7587 pincap = w->wclass.pin.cap;
7588 device_printf(dev, " Caps: %2s %3s %2s %4s %4s",
7589 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"",
7590 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"",
7591 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"",
7592 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"",
7593 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":"");
7594 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) ||
7595 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) {
7596 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) {
7599 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad);
7601 res = hdac_command(sc,
7602 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad);
7603 if (res != 0x7fffffff && res != 0xffffffff)
7606 } while (++delay < 10000);
7609 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad,
7612 printf(" Sense: 0x%08x", res);
7614 printf(" delay %dus", delay * 10);
7619 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n",
7620 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio),
7621 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio),
7622 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio),
7623 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio),
7624 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio));
7625 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) {
7626 device_printf(dev, " GPI:");
7627 res = hdac_command(sc,
7628 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad);
7629 printf(" data=0x%08x", res);
7630 res = hdac_command(sc,
7631 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid),
7633 printf(" wake=0x%08x", res);
7634 res = hdac_command(sc,
7635 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7637 printf(" unsol=0x%08x", res);
7638 res = hdac_command(sc,
7639 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad);
7640 printf(" sticky=0x%08x\n", res);
7642 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) {
7643 device_printf(dev, " GPO:");
7644 res = hdac_command(sc,
7645 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad);
7646 printf(" data=0x%08x\n", res);
7648 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) {
7649 device_printf(dev, "GPIO:");
7650 res = hdac_command(sc,
7651 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad);
7652 printf(" data=0x%08x", res);
7653 res = hdac_command(sc,
7654 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad);
7655 printf(" enable=0x%08x", res);
7656 res = hdac_command(sc,
7657 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad);
7658 printf(" direction=0x%08x\n", res);
7659 res = hdac_command(sc,
7660 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad);
7661 device_printf(dev, " wake=0x%08x", res);
7662 res = hdac_command(sc,
7663 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid),
7665 printf(" unsol=0x%08x", res);
7666 res = hdac_command(sc,
7667 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad);
7668 printf(" sticky=0x%08x\n", res);
7677 hdac_attach2(void *arg)
7679 struct hdac_codec *codec;
7680 struct hdac_softc *sc;
7681 struct hdac_audio_ctl *ctl;
7682 uint32_t quirks_on, quirks_off;
7683 int codec_index, fg_index;
7684 int i, dmaalloc = 0;
7685 struct hdac_devinfo *devinfo;
7687 sc = (struct hdac_softc *)arg;
7689 hdac_config_fetch(sc, &quirks_on, &quirks_off);
7692 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n",
7693 quirks_on, quirks_off);
7698 /* Remove ourselves from the config hooks */
7699 if (sc->intrhook.ich_func != NULL) {
7700 config_intrhook_disestablish(&sc->intrhook);
7701 sc->intrhook.ich_func = NULL;
7704 /* Start the corb and rirb engines */
7706 device_printf(sc->dev, "Starting CORB Engine...\n");
7708 hdac_corb_start(sc);
7710 device_printf(sc->dev, "Starting RIRB Engine...\n");
7712 hdac_rirb_start(sc);
7715 device_printf(sc->dev,
7716 "Enabling controller interrupt...\n");
7718 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
7720 if (sc->polling == 0) {
7721 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
7722 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
7724 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
7729 device_printf(sc->dev,
7730 "Scanning HDA codecs ...\n");
7732 hdac_scan_codecs(sc);
7734 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7735 codec = sc->codecs[codec_index];
7738 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7739 devinfo = &codec->fgs[fg_index];
7741 device_printf(sc->dev, "\n");
7742 device_printf(sc->dev,
7743 "Processing %s FG cad=%d nid=%d...\n",
7744 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio":
7745 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem":
7747 devinfo->codec->cad, devinfo->nid);
7749 if (devinfo->node_type !=
7750 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
7752 device_printf(sc->dev,
7753 "Powering down...\n");
7756 HDA_CMD_SET_POWER_STATE(codec->cad,
7757 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7763 device_printf(sc->dev, "Powering up...\n");
7765 hdac_powerup(devinfo);
7767 device_printf(sc->dev, "Parsing audio FG...\n");
7769 hdac_audio_parse(devinfo);
7771 device_printf(sc->dev, "Parsing Ctls...\n");
7773 hdac_audio_ctl_parse(devinfo);
7775 device_printf(sc->dev, "Parsing vendor patch...\n");
7777 hdac_vendor_patch_parse(devinfo);
7778 devinfo->function.audio.quirks |= quirks_on;
7779 devinfo->function.audio.quirks &= ~quirks_off;
7782 device_printf(sc->dev, "Disabling nonaudio...\n");
7784 hdac_audio_disable_nonaudio(devinfo);
7786 device_printf(sc->dev, "Disabling useless...\n");
7788 hdac_audio_disable_useless(devinfo);
7790 device_printf(sc->dev, "Patched pins configuration:\n");
7791 hdac_dump_pin_configs(devinfo);
7794 device_printf(sc->dev, "Parsing pin associations...\n");
7796 hdac_audio_as_parse(devinfo);
7798 device_printf(sc->dev, "Building AFG tree...\n");
7800 hdac_audio_build_tree(devinfo);
7802 device_printf(sc->dev, "Disabling unassociated "
7805 hdac_audio_disable_unas(devinfo);
7807 device_printf(sc->dev, "Disabling nonselected "
7810 hdac_audio_disable_notselected(devinfo);
7812 device_printf(sc->dev, "Disabling useless...\n");
7814 hdac_audio_disable_useless(devinfo);
7816 device_printf(sc->dev, "Disabling "
7817 "crossassociatement connections...\n");
7819 hdac_audio_disable_crossas(devinfo);
7821 device_printf(sc->dev, "Disabling useless...\n");
7823 hdac_audio_disable_useless(devinfo);
7825 device_printf(sc->dev, "Binding associations to channels...\n");
7827 hdac_audio_bind_as(devinfo);
7829 device_printf(sc->dev, "Assigning names to signal sources...\n");
7831 hdac_audio_assign_names(devinfo);
7833 device_printf(sc->dev, "Assigning mixers to the tree...\n");
7835 hdac_audio_assign_mixers(devinfo);
7837 device_printf(sc->dev, "Preparing pin controls...\n");
7839 hdac_audio_prepare_pin_ctrl(devinfo);
7841 device_printf(sc->dev, "AFG commit...\n");
7843 hdac_audio_commit(devinfo);
7845 device_printf(sc->dev, "HP switch init...\n");
7847 hdac_hp_switch_init(devinfo);
7849 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) &&
7851 if (hdac_dma_alloc(sc, &sc->pos_dma,
7852 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) {
7854 device_printf(sc->dev, "Failed to "
7855 "allocate DMA pos buffer "
7863 device_printf(sc->dev, "Creating PCM devices...\n");
7865 hdac_create_pcms(devinfo);
7868 if (devinfo->function.audio.quirks != 0) {
7869 device_printf(sc->dev, "FG config/quirks:");
7870 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) {
7871 if ((devinfo->function.audio.quirks &
7872 hdac_quirks_tab[i].value) ==
7873 hdac_quirks_tab[i].value)
7874 printf(" %s", hdac_quirks_tab[i].key);
7879 device_printf(sc->dev, "\n");
7880 device_printf(sc->dev, "+-------------------+\n");
7881 device_printf(sc->dev, "| DUMPING HDA NODES |\n");
7882 device_printf(sc->dev, "+-------------------+\n");
7883 hdac_dump_nodes(devinfo);
7887 device_printf(sc->dev, "\n");
7888 device_printf(sc->dev, "+------------------------+\n");
7889 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n");
7890 device_printf(sc->dev, "+------------------------+\n");
7891 device_printf(sc->dev, "\n");
7893 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) {
7894 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i,
7895 (ctl->widget != NULL) ? ctl->widget->nid : -1,
7896 (ctl->ndir == HDA_CTL_IN)?"in ":"out",
7897 (ctl->dir == HDA_CTL_IN)?"in ":"out",
7899 if (ctl->childwidget != NULL)
7900 printf(" cnid %3d", ctl->childwidget->nid);
7903 printf(" ossmask=0x%08x\n",
7905 device_printf(sc->dev,
7906 " mute: %d step: %3d size: %3d off: %3d%s\n",
7907 ctl->mute, ctl->step, ctl->size, ctl->offset,
7908 (ctl->enable == 0) ? " [DISABLED]" :
7909 ((ctl->ossmask == 0) ? " [UNUSED]" : ""));
7917 device_printf(sc->dev, "\n");
7920 bus_generic_attach(sc->dev);
7922 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7923 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7924 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7925 sysctl_hdac_polling, "I", "Enable polling mode");
7926 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7927 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7928 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev,
7929 sizeof(sc->dev), sysctl_hdac_polling_interval, "I",
7930 "Controller/Jack Sense polling interval (1-1000 ms)");
7931 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
7932 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
7933 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
7934 sysctl_hdac_pindump, "I", "Dump pin states/data");
7937 /****************************************************************************
7938 * int hdac_suspend(device_t)
7940 * Suspend and power down HDA bus and codecs.
7941 ****************************************************************************/
7943 hdac_suspend(device_t dev)
7945 struct hdac_softc *sc;
7946 struct hdac_codec *codec;
7947 struct hdac_devinfo *devinfo;
7948 int codec_index, fg_index, i;
7951 device_printf(dev, "Suspend...\n");
7954 sc = device_get_softc(dev);
7958 device_printf(dev, "Stop streams...\n");
7960 for (i = 0; i < sc->num_chans; i++) {
7961 if (sc->chans[i].flags & HDAC_CHN_RUNNING) {
7962 sc->chans[i].flags |= HDAC_CHN_SUSPEND;
7963 hdac_channel_stop(sc, &sc->chans[i]);
7967 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
7968 codec = sc->codecs[codec_index];
7971 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
7972 devinfo = &codec->fgs[fg_index];
7976 " cad=%d nid=%d to the D3 state...\n",
7977 codec->cad, devinfo->nid);
7980 HDA_CMD_SET_POWER_STATE(codec->cad,
7981 devinfo->nid, HDA_CMD_POWER_STATE_D3),
7987 device_printf(dev, "Reset controller...\n");
7989 callout_stop(&sc->poll_hda);
7990 callout_stop(&sc->poll_hdac);
7991 callout_stop(&sc->poll_jack);
7994 taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
7995 callout_drain(&sc->poll_hda);
7996 callout_drain(&sc->poll_hdac);
7997 callout_drain(&sc->poll_jack);
8000 device_printf(dev, "Suspend done\n");
8006 /****************************************************************************
8007 * int hdac_resume(device_t)
8009 * Powerup and restore HDA bus and codecs state.
8010 ****************************************************************************/
8012 hdac_resume(device_t dev)
8014 struct hdac_softc *sc;
8015 struct hdac_codec *codec;
8016 struct hdac_devinfo *devinfo;
8017 int codec_index, fg_index, i;
8020 device_printf(dev, "Resume...\n");
8023 sc = device_get_softc(dev);
8026 /* Quiesce everything */
8028 device_printf(dev, "Reset controller...\n");
8032 /* Initialize the CORB and RIRB */
8036 /* Start the corb and rirb engines */
8038 device_printf(dev, "Starting CORB Engine...\n");
8040 hdac_corb_start(sc);
8042 device_printf(dev, "Starting RIRB Engine...\n");
8044 hdac_rirb_start(sc);
8048 "Enabling controller interrupt...\n");
8050 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
8052 if (sc->polling == 0) {
8053 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
8054 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
8056 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc);
8060 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) {
8061 codec = sc->codecs[codec_index];
8064 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) {
8065 devinfo = &codec->fgs[fg_index];
8066 if (devinfo->node_type !=
8067 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) {
8070 "Power down unsupported non-audio FG"
8071 " cad=%d nid=%d to the D3 state...\n",
8072 codec->cad, devinfo->nid);
8075 HDA_CMD_SET_POWER_STATE(codec->cad,
8076 devinfo->nid, HDA_CMD_POWER_STATE_D3),
8083 "Power up audio FG cad=%d nid=%d...\n",
8084 devinfo->codec->cad, devinfo->nid);
8086 hdac_powerup(devinfo);
8088 device_printf(dev, "AFG commit...\n");
8090 hdac_audio_commit(devinfo);
8092 device_printf(dev, "HP switch init...\n");
8094 hdac_hp_switch_init(devinfo);
8097 for (i = 0; i < devinfo->function.audio.num_devs; i++) {
8098 struct hdac_pcm_devinfo *pdevinfo =
8099 &devinfo->function.audio.devs[i];
8101 device_printf(pdevinfo->dev,
8102 "OSS mixer reinitialization...\n");
8104 if (mixer_reinit(pdevinfo->dev) == -1)
8105 device_printf(pdevinfo->dev,
8106 "unable to reinitialize the mixer\n");
8113 device_printf(dev, "Start streams...\n");
8115 for (i = 0; i < sc->num_chans; i++) {
8116 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) {
8117 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND;
8118 hdac_channel_start(sc, &sc->chans[i]);
8125 device_printf(dev, "Resume done\n");
8130 /****************************************************************************
8131 * int hdac_detach(device_t)
8133 * Detach and free up resources utilized by the hdac device.
8134 ****************************************************************************/
8136 hdac_detach(device_t dev)
8138 struct hdac_softc *sc;
8140 int i, devcount, error;
8142 if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
8144 for (i = 0; i < devcount; i++) {
8145 if ((error = device_delete_child(dev, devlist[i])) != 0) {
8146 free(devlist, M_TEMP);
8150 free(devlist, M_TEMP);
8152 sc = device_get_softc(dev);
8153 hdac_release_resources(sc);
8159 hdac_print_child(device_t dev, device_t child)
8161 struct hdac_pcm_devinfo *pdevinfo =
8162 (struct hdac_pcm_devinfo *)device_get_ivars(child);
8165 retval = bus_print_child_header(dev, child);
8166 retval += printf(" at cad %d nid %d",
8167 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid);
8168 retval += bus_print_child_footer(dev, child);
8173 static device_method_t hdac_methods[] = {
8174 /* device interface */
8175 DEVMETHOD(device_probe, hdac_probe),
8176 DEVMETHOD(device_attach, hdac_attach),
8177 DEVMETHOD(device_detach, hdac_detach),
8178 DEVMETHOD(device_suspend, hdac_suspend),
8179 DEVMETHOD(device_resume, hdac_resume),
8181 DEVMETHOD(bus_print_child, hdac_print_child),
8185 static driver_t hdac_driver = {
8188 sizeof(struct hdac_softc),
8191 static devclass_t hdac_devclass;
8193 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0);
8194 MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
8195 MODULE_VERSION(snd_hda, 1);
8198 hdac_pcm_probe(device_t dev)
8200 struct hdac_pcm_devinfo *pdevinfo =
8201 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8204 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s",
8205 hdac_codec_name(pdevinfo->devinfo->codec),
8207 (pdevinfo->digital == 3)?"DisplayPort":
8208 ((pdevinfo->digital == 2)?"HDMI":
8209 ((pdevinfo->digital)?"Digital":"Analog")));
8210 device_set_desc_copy(dev, buf);
8215 hdac_pcm_attach(device_t dev)
8217 struct hdac_pcm_devinfo *pdevinfo =
8218 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8219 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc;
8220 char status[SND_STATUSLEN];
8223 pdevinfo->chan_size = pcm_getbuffersize(dev,
8224 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX);
8227 device_printf(dev, "+--------------------------------------+\n");
8228 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n");
8229 device_printf(dev, "+--------------------------------------+\n");
8230 hdac_dump_pcmchannels(pdevinfo);
8231 device_printf(dev, "\n");
8232 device_printf(dev, "+-------------------------------+\n");
8233 device_printf(dev, "| DUMPING Playback/Record Paths |\n");
8234 device_printf(dev, "+-------------------------------+\n");
8235 hdac_dump_dac(pdevinfo);
8236 hdac_dump_adc(pdevinfo);
8237 hdac_dump_mix(pdevinfo);
8238 device_printf(dev, "\n");
8239 device_printf(dev, "+-------------------------+\n");
8240 device_printf(dev, "| DUMPING Volume Controls |\n");
8241 device_printf(dev, "+-------------------------+\n");
8242 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME);
8243 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM);
8244 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD);
8245 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC);
8246 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR);
8247 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE);
8248 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER);
8249 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV);
8250 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX);
8251 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN);
8252 hdac_dump_ctls(pdevinfo, NULL, 0);
8253 device_printf(dev, "\n");
8256 if (resource_int_value(device_get_name(dev),
8257 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) {
8259 if (i < HDA_BLK_MIN)
8261 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i;
8263 while (pdevinfo->chan_blkcnt >> i)
8265 pdevinfo->chan_blkcnt = 1 << (i - 1);
8266 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN)
8267 pdevinfo->chan_blkcnt = HDA_BDL_MIN;
8268 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX)
8269 pdevinfo->chan_blkcnt = HDA_BDL_MAX;
8271 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT;
8274 * We don't register interrupt handler with snd_setup_intr
8275 * in pcm device. Mark pcm device as MPSAFE manually.
8277 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
8280 device_printf(dev, "OSS mixer initialization...\n");
8282 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0)
8283 device_printf(dev, "Can't register mixer\n");
8286 device_printf(dev, "Registering PCM channels...\n");
8288 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0,
8289 (pdevinfo->rec >= 0)?1:0) != 0)
8290 device_printf(dev, "Can't register PCM\n");
8292 pdevinfo->registered++;
8294 if (pdevinfo->play >= 0)
8295 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo);
8296 if (pdevinfo->rec >= 0)
8297 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo);
8299 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s",
8300 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid,
8301 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda));
8302 pcm_setstatus(dev, status);
8308 hdac_pcm_detach(device_t dev)
8310 struct hdac_pcm_devinfo *pdevinfo =
8311 (struct hdac_pcm_devinfo *)device_get_ivars(dev);
8314 if (pdevinfo->registered > 0) {
8315 err = pcm_unregister(dev);
8323 static device_method_t hdac_pcm_methods[] = {
8324 /* device interface */
8325 DEVMETHOD(device_probe, hdac_pcm_probe),
8326 DEVMETHOD(device_attach, hdac_pcm_attach),
8327 DEVMETHOD(device_detach, hdac_pcm_detach),
8331 static driver_t hdac_pcm_driver = {
8337 DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0);