sys/dev/usb/controller/xhci.c

   1 /*-
   2  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  28  *
  29  * The XHCI 1.0 spec can be found at
  30  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  31  * and the USB 3.0 spec at
  32  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  33  */
  34
  35 /*
  36  * A few words about the design implementation: This driver emulates
  37  * the concept about TDs which is found in EHCI specification. This
  38  * way we avoid too much diveration among USB drivers.
  39  */
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/stdint.h>
  45 #include <sys/stddef.h>
  46 #include <sys/param.h>
  47 #include <sys/queue.h>
  48 #include <sys/types.h>
  49 #include <sys/systm.h>
  50 #include <sys/kernel.h>
  51 #include <sys/bus.h>
  52 #include <sys/module.h>
  53 #include <sys/lock.h>
  54 #include <sys/mutex.h>
  55 #include <sys/condvar.h>
  56 #include <sys/sysctl.h>
  57 #include <sys/sx.h>
  58 #include <sys/unistd.h>
  59 #include <sys/callout.h>
  60 #include <sys/malloc.h>
  61 #include <sys/priv.h>
  62
  63 #include <dev/usb/usb.h>
  64 #include <dev/usb/usbdi.h>
  65
  66 #define USB_DEBUG_VAR xhcidebug
  67
  68 #include <dev/usb/usb_core.h>
  69 #include <dev/usb/usb_debug.h>
  70 #include <dev/usb/usb_busdma.h>
  71 #include <dev/usb/usb_process.h>
  72 #include <dev/usb/usb_transfer.h>
  73 #include <dev/usb/usb_device.h>
  74 #include <dev/usb/usb_hub.h>
  75 #include <dev/usb/usb_util.h>
  76
  77 #include <dev/usb/usb_controller.h>
  78 #include <dev/usb/usb_bus.h>
  79 #include <dev/usb/controller/xhci.h>
  80 #include <dev/usb/controller/xhcireg.h>
  81
  82 #define XHCI_BUS2SC(bus) \
  83    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  84     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  85
  86 #ifdef USB_DEBUG
  87 static int xhcidebug;
  88 static int xhciroute;
  89 static int xhcipolling;
  90 static int xhcidma32;
  91
  92 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcidebug, 0, "Debug level");
  95 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  96 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
  97     &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
  98 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
  99 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 100     &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
 101 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
 103     &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
 104 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
 105 #else
 106 #define xhciroute 0
 107 #define xhcidma32 0
 108 #endif
 109
 110 #define XHCI_INTR_ENDPT 1
 111
 112 struct xhci_std_temp {
 113         struct xhci_softc       *sc;
 114         struct usb_page_cache   *pc;
 115         struct xhci_td          *td;
 116         struct xhci_td          *td_next;
 117         uint32_t                len;
 118         uint32_t                offset;
 119         uint32_t                max_packet_size;
 120         uint32_t                average;
 121         uint16_t                isoc_delta;
 122         uint16_t                isoc_frame;
 123         uint8_t                 shortpkt;
 124         uint8_t                 multishort;
 125         uint8_t                 last_frame;
 126         uint8_t                 trb_type;
 127         uint8_t                 direction;
 128         uint8_t                 tbc;
 129         uint8_t                 tlbpc;
 130         uint8_t                 step_td;
 131         uint8_t                 do_isoc_sync;
 132 };
 133
 134 static void     xhci_do_poll(struct usb_bus *);
 135 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 136 static void     xhci_root_intr(struct xhci_softc *);
 137 static void     xhci_free_device_ext(struct usb_device *);
 138 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 139                     struct usb_endpoint_descriptor *);
 140 static usb_proc_callback_t xhci_configure_msg;
 141 static usb_error_t xhci_configure_device(struct usb_device *);
 142 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 143     struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 144     uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t);
 145 static usb_error_t xhci_configure_mask(struct usb_device *,
 146                     uint32_t, uint8_t);
 147 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 148                     uint64_t, uint8_t);
 149 static void xhci_endpoint_doorbell(struct usb_xfer *);
 150 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 151 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 152 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 153 #ifdef USB_DEBUG
 154 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 155 #endif
 156
 157 extern struct usb_bus_methods xhci_bus_methods;
 158
 159 #ifdef USB_DEBUG
 160 static void
 161 xhci_dump_trb(struct xhci_trb *trb)
 162 {
 163         DPRINTFN(5, "trb = %p\n", trb);
 164         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 165         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 166         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 167 }
 168
 169 static void
 170 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 171 {
 172         DPRINTFN(5, "pep = %p\n", pep);
 173         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 174         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 175         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 176         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 177         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 178         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 179         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 180 }
 181
 182 static void
 183 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 184 {
 185         DPRINTFN(5, "psl = %p\n", psl);
 186         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 187         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 188         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 189         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 190 }
 191 #endif
 192
 193 uint8_t
 194 xhci_use_polling(void)
 195 {
 196 #ifdef USB_DEBUG
 197         return (xhcipolling != 0);
 198 #else
 199         return (0);
 200 #endif
 201 }
 202
 203 static void
 204 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 205 {
 206         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 207         uint16_t i;
 208
 209         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 210            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 211
 212         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 213            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 214
 215         for (i = 0; i != sc->sc_noscratch; i++) {
 216                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 217                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 218         }
 219 }
 220
 221 static void
 222 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 223 {
 224         if (sc->sc_ctx_is_64_byte) {
 225                 uint32_t offset;
 226                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 227                 /* all contexts are initially 32-bytes */
 228                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 229                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 230         }
 231         *ptr = htole32(val);
 232 }
 233
 234 static uint32_t
 235 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 236 {
 237         if (sc->sc_ctx_is_64_byte) {
 238                 uint32_t offset;
 239                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 240                 /* all contexts are initially 32-bytes */
 241                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 242                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 243         }
 244         return (le32toh(*ptr));
 245 }
 246
 247 static void
 248 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 249 {
 250         if (sc->sc_ctx_is_64_byte) {
 251                 uint32_t offset;
 252                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 253                 /* all contexts are initially 32-bytes */
 254                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 255                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 256         }
 257         *ptr = htole64(val);
 258 }
 259
 260 #ifdef USB_DEBUG
 261 static uint64_t
 262 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 263 {
 264         if (sc->sc_ctx_is_64_byte) {
 265                 uint32_t offset;
 266                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 267                 /* all contexts are initially 32-bytes */
 268                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 269                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 270         }
 271         return (le64toh(*ptr));
 272 }
 273 #endif
 274
 275 static int
 276 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 277 {
 278         struct usb_page_search buf_res;
 279         struct xhci_hw_root *phwr;
 280         uint64_t addr;
 281         uint32_t temp;
 282
 283         DPRINTF("\n");
 284
 285         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 286         if (temp & XHCI_CRCR_LO_CRR) {
 287                 DPRINTF("Command ring running\n");
 288                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 289
 290                 /*
 291                  * Try to abort the last command as per section
 292                  * 4.6.1.2 "Aborting a Command" of the XHCI
 293                  * specification:
 294                  */
 295
 296                 /* stop and cancel */
 297                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 298                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 299
 300                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 301                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 302
 303                 /* wait 250ms */
 304                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 305
 306                 /* check if command ring is still running */
 307                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 308                 if (temp & XHCI_CRCR_LO_CRR) {
 309                         DPRINTF("Comand ring still running\n");
 310                         return (USB_ERR_IOERROR);
 311                 }
 312         }
 313
 314         /* reset command ring */
 315         sc->sc_command_ccs = 1;
 316         sc->sc_command_idx = 0;
 317
 318         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 319
 320         /* set up command ring control base address */
 321         addr = buf_res.physaddr;
 322         phwr = buf_res.buffer;
 323         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 324
 325         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 326
 327         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 328         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 329
 330         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 331
 332         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 333         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 334
 335         return (0);
 336 }
 337
 338 usb_error_t
 339 xhci_start_controller(struct xhci_softc *sc)
 340 {
 341         struct usb_page_search buf_res;
 342         struct xhci_hw_root *phwr;
 343         struct xhci_dev_ctx_addr *pdctxa;
 344         usb_error_t err;
 345         uint64_t addr;
 346         uint32_t temp;
 347         uint16_t i;
 348
 349         DPRINTF("\n");
 350
 351         sc->sc_event_ccs = 1;
 352         sc->sc_event_idx = 0;
 353         sc->sc_command_ccs = 1;
 354         sc->sc_command_idx = 0;
 355
 356         err = xhci_reset_controller(sc);
 357         if (err)
 358                 return (err);
 359
 360         /* set up number of device slots */
 361         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 362             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 363
 364         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 365
 366         temp = XREAD4(sc, oper, XHCI_USBSTS);
 367
 368         /* clear interrupts */
 369         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 370         /* disable all device notifications */
 371         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 372
 373         /* set up device context base address */
 374         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 375         pdctxa = buf_res.buffer;
 376         memset(pdctxa, 0, sizeof(*pdctxa));
 377
 378         addr = buf_res.physaddr;
 379         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 380
 381         /* slot 0 points to the table of scratchpad pointers */
 382         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 383
 384         for (i = 0; i != sc->sc_noscratch; i++) {
 385                 struct usb_page_search buf_scp;
 386                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 387                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 388         }
 389
 390         addr = buf_res.physaddr;
 391
 392         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 393         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 394         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 395         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 396
 397         /* set up event table size */
 398         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 399             XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
 400
 401         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
 402
 403         /* set up interrupt rate */
 404         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 405
 406         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 407
 408         phwr = buf_res.buffer;
 409         addr = buf_res.physaddr;
 410         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 411
 412         /* reset hardware root structure */
 413         memset(phwr, 0, sizeof(*phwr));
 414
 415         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 416         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 417
 418         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 419
 420         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 421         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 422
 423         addr = buf_res.physaddr;
 424
 425         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 426
 427         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 428         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 429
 430         /* set up interrupter registers */
 431         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 432         temp |= XHCI_IMAN_INTR_ENA;
 433         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 434
 435         /* set up command ring control base address */
 436         addr = buf_res.physaddr;
 437         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 438
 439         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 440
 441         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 442         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 443
 444         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 445
 446         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 447
 448         /* Go! */
 449         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 450             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 451
 452         for (i = 0; i != 100; i++) {
 453                 usb_pause_mtx(NULL, hz / 100);
 454                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 455                 if (!temp)
 456                         break;
 457         }
 458         if (temp) {
 459                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 460                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 461                 return (USB_ERR_IOERROR);
 462         }
 463
 464         /* catch any lost interrupts */
 465         xhci_do_poll(&sc->sc_bus);
 466
 467         if (sc->sc_port_route != NULL) {
 468                 /* Route all ports to the XHCI by default */
 469                 sc->sc_port_route(sc->sc_bus.parent,
 470                     ~xhciroute, xhciroute);
 471         }
 472         return (0);
 473 }
 474
 475 usb_error_t
 476 xhci_halt_controller(struct xhci_softc *sc)
 477 {
 478         uint32_t temp;
 479         uint16_t i;
 480
 481         DPRINTF("\n");
 482
 483         sc->sc_capa_off = 0;
 484         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 485         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 486         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 487
 488         /* Halt controller */
 489         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 490
 491         for (i = 0; i != 100; i++) {
 492                 usb_pause_mtx(NULL, hz / 100);
 493                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 494                 if (temp)
 495                         break;
 496         }
 497
 498         if (!temp) {
 499                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 500                 return (USB_ERR_IOERROR);
 501         }
 502         return (0);
 503 }
 504
 505 usb_error_t
 506 xhci_reset_controller(struct xhci_softc *sc)
 507 {
 508         uint32_t temp = 0;
 509         uint16_t i;
 510
 511         DPRINTF("\n");
 512
 513         /* Reset controller */
 514         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 515
 516         for (i = 0; i != 100; i++) {
 517                 usb_pause_mtx(NULL, hz / 100);
 518                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 519                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 520                 if (!temp)
 521                         break;
 522         }
 523
 524         if (temp) {
 525                 device_printf(sc->sc_bus.parent, "Controller "
 526                     "reset timeout.\n");
 527                 return (USB_ERR_IOERROR);
 528         }
 529         return (0);
 530 }
 531
 532 usb_error_t
 533 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
 534 {
 535         uint32_t temp;
 536
 537         DPRINTF("\n");
 538
 539         /* initialize some bus fields */
 540         sc->sc_bus.parent = self;
 541
 542         /* set the bus revision */
 543         sc->sc_bus.usbrev = USB_REV_3_0;
 544
 545         /* set up the bus struct */
 546         sc->sc_bus.methods = &xhci_bus_methods;
 547
 548         /* set up devices array */
 549         sc->sc_bus.devices = sc->sc_devices;
 550         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 551
 552         /* set default cycle state in case of early interrupts */
 553         sc->sc_event_ccs = 1;
 554         sc->sc_command_ccs = 1;
 555
 556         /* set up bus space offsets */
 557         sc->sc_capa_off = 0;
 558         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 559         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 560         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 561
 562         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 563         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 564         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 565
 566         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 567
 568         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 569                 device_printf(sc->sc_bus.parent, "Controller does "
 570                     "not support 4K page size.\n");
 571                 return (ENXIO);
 572         }
 573
 574         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 575
 576         DPRINTF("HCS0 = 0x%08x\n", temp);
 577
 578         /* set up context size */
 579         if (XHCI_HCS0_CSZ(temp)) {
 580                 sc->sc_ctx_is_64_byte = 1;
 581         } else {
 582                 sc->sc_ctx_is_64_byte = 0;
 583         }
 584
 585         /* get DMA bits */
 586         sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
 587             xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
 588
 589         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 590             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 591
 592         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 593
 594         /* get number of device slots */
 595         sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
 596
 597         if (sc->sc_noport == 0) {
 598                 device_printf(sc->sc_bus.parent, "Invalid number "
 599                     "of ports: %u\n", sc->sc_noport);
 600                 return (ENXIO);
 601         }
 602
 603         sc->sc_noport = sc->sc_noport;
 604         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 605
 606         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 607
 608         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 609                 sc->sc_noslot = XHCI_MAX_DEVICES;
 610
 611         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 612
 613         DPRINTF("HCS2=0x%08x\n", temp);
 614
 615         /* get number of scratchpads */
 616         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 617
 618         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 619                 device_printf(sc->sc_bus.parent, "XHCI request "
 620                     "too many scratchpads\n");
 621                 return (ENOMEM);
 622         }
 623
 624         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 625
 626         /* get event table size */
 627         sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
 628         if (sc->sc_erst_max > XHCI_MAX_RSEG)
 629                 sc->sc_erst_max = XHCI_MAX_RSEG;
 630
 631         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 632
 633         /* get maximum exit latency */
 634         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 635             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 636
 637         /* Check if we should use the default IMOD value. */
 638         if (sc->sc_imod_default == 0)
 639                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 640
 641         /* get all DMA memory */
 642         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 643             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 644                 return (ENOMEM);
 645         }
 646
 647         /* set up command queue mutex and condition varible */
 648         cv_init(&sc->sc_cmd_cv, "CMDQ");
 649         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 650
 651         if (usb_proc_create(&sc->sc_config_proc,
 652             &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) {
 653                 printf("WARNING: Creation of XHCI configure "
 654                     "callback process failed.\n");
 655         }
 656         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 657         sc->sc_config_msg[0].bus = &sc->sc_bus;
 658         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 659         sc->sc_config_msg[1].bus = &sc->sc_bus;
 660
 661         return (0);
 662 }
 663
 664 void
 665 xhci_uninit(struct xhci_softc *sc)
 666 {
 667         usb_proc_free(&sc->sc_config_proc);
 668
 669         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 670
 671         cv_destroy(&sc->sc_cmd_cv);
 672         sx_destroy(&sc->sc_cmd_sx);
 673 }
 674
 675 static void
 676 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 677 {
 678         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 679
 680         switch (state) {
 681         case USB_HW_POWER_SUSPEND:
 682                 DPRINTF("Stopping the XHCI\n");
 683                 xhci_halt_controller(sc);
 684                 xhci_reset_controller(sc);
 685                 break;
 686         case USB_HW_POWER_SHUTDOWN:
 687                 DPRINTF("Stopping the XHCI\n");
 688                 xhci_halt_controller(sc);
 689                 xhci_reset_controller(sc);
 690                 break;
 691         case USB_HW_POWER_RESUME:
 692                 DPRINTF("Starting the XHCI\n");
 693                 xhci_start_controller(sc);
 694                 break;
 695         default:
 696                 break;
 697         }
 698 }
 699
 700 static usb_error_t
 701 xhci_generic_done_sub(struct usb_xfer *xfer)
 702 {
 703         struct xhci_td *td;
 704         struct xhci_td *td_alt_next;
 705         uint32_t len;
 706         uint8_t status;
 707
 708         td = xfer->td_transfer_cache;
 709         td_alt_next = td->alt_next;
 710
 711         if (xfer->aframes != xfer->nframes)
 712                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 713
 714         while (1) {
 715
 716                 usb_pc_cpu_invalidate(td->page_cache);
 717
 718                 status = td->status;
 719                 len = td->remainder;
 720
 721                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 722                     xfer, (unsigned int)xfer->aframes,
 723                     (unsigned int)xfer->nframes,
 724                     (unsigned int)len, (unsigned int)td->len,
 725                     (unsigned int)status);
 726
 727                 /*
 728                  * Verify the status length and
 729                  * add the length to "frlengths[]":
 730                  */
 731                 if (len > td->len) {
 732                         /* should not happen */
 733                         DPRINTF("Invalid status length, "
 734                             "0x%04x/0x%04x bytes\n", len, td->len);
 735                         status = XHCI_TRB_ERROR_LENGTH;
 736                 } else if (xfer->aframes != xfer->nframes) {
 737                         xfer->frlengths[xfer->aframes] += td->len - len;
 738                 }
 739                 /* Check for last transfer */
 740                 if (((void *)td) == xfer->td_transfer_last) {
 741                         td = NULL;
 742                         break;
 743                 }
 744                 /* Check for transfer error */
 745                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 746                     status != XHCI_TRB_ERROR_SUCCESS) {
 747                         /* the transfer is finished */
 748                         td = NULL;
 749                         break;
 750                 }
 751                 /* Check for short transfer */
 752                 if (len > 0) {
 753                         if (xfer->flags_int.short_frames_ok ||
 754                             xfer->flags_int.isochronous_xfr ||
 755                             xfer->flags_int.control_xfr) {
 756                                 /* follow alt next */
 757                                 td = td->alt_next;
 758                         } else {
 759                                 /* the transfer is finished */
 760                                 td = NULL;
 761                         }
 762                         break;
 763                 }
 764                 td = td->obj_next;
 765
 766                 if (td->alt_next != td_alt_next) {
 767                         /* this USB frame is complete */
 768                         break;
 769                 }
 770         }
 771
 772         /* update transfer cache */
 773
 774         xfer->td_transfer_cache = td;
 775
 776         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 777             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 778             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 779             USB_ERR_NORMAL_COMPLETION);
 780 }
 781
 782 static void
 783 xhci_generic_done(struct usb_xfer *xfer)
 784 {
 785         usb_error_t err = 0;
 786
 787         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 788             xfer, xfer->endpoint);
 789
 790         /* reset scanner */
 791
 792         xfer->td_transfer_cache = xfer->td_transfer_first;
 793
 794         if (xfer->flags_int.control_xfr) {
 795
 796                 if (xfer->flags_int.control_hdr)
 797                         err = xhci_generic_done_sub(xfer);
 798
 799                 xfer->aframes = 1;
 800
 801                 if (xfer->td_transfer_cache == NULL)
 802                         goto done;
 803         }
 804
 805         while (xfer->aframes != xfer->nframes) {
 806
 807                 err = xhci_generic_done_sub(xfer);
 808                 xfer->aframes++;
 809
 810                 if (xfer->td_transfer_cache == NULL)
 811                         goto done;
 812         }
 813
 814         if (xfer->flags_int.control_xfr &&
 815             !xfer->flags_int.control_act)
 816                 err = xhci_generic_done_sub(xfer);
 817 done:
 818         /* transfer is complete */
 819         xhci_device_done(xfer, err);
 820 }
 821
 822 static void
 823 xhci_activate_transfer(struct usb_xfer *xfer)
 824 {
 825         struct xhci_td *td;
 826
 827         td = xfer->td_transfer_cache;
 828
 829         usb_pc_cpu_invalidate(td->page_cache);
 830
 831         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 832
 833                 /* activate the transfer */
 834
 835                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 836                 usb_pc_cpu_flush(td->page_cache);
 837
 838                 xhci_endpoint_doorbell(xfer);
 839         }
 840 }
 841
 842 static void
 843 xhci_skip_transfer(struct usb_xfer *xfer)
 844 {
 845         struct xhci_td *td;
 846         struct xhci_td *td_last;
 847
 848         td = xfer->td_transfer_cache;
 849         td_last = xfer->td_transfer_last;
 850
 851         td = td->alt_next;
 852
 853         usb_pc_cpu_invalidate(td->page_cache);
 854
 855         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 856
 857                 usb_pc_cpu_invalidate(td_last->page_cache);
 858
 859                 /* copy LINK TRB to current waiting location */
 860
 861                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 862                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 863                 usb_pc_cpu_flush(td->page_cache);
 864
 865                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 866                 usb_pc_cpu_flush(td->page_cache);
 867
 868                 xhci_endpoint_doorbell(xfer);
 869         }
 870 }
 871
 872 /*------------------------------------------------------------------------*
 873  *      xhci_check_transfer
 874  *------------------------------------------------------------------------*/
 875 static void
 876 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 877 {
 878         int64_t offset;
 879         uint64_t td_event;
 880         uint32_t temp;
 881         uint32_t remainder;
 882         uint8_t status;
 883         uint8_t halted;
 884         uint8_t epno;
 885         uint8_t index;
 886         uint8_t i;
 887
 888         /* decode TRB */
 889         td_event = le64toh(trb->qwTrb0);
 890         temp = le32toh(trb->dwTrb2);
 891
 892         remainder = XHCI_TRB_2_REM_GET(temp);
 893         status = XHCI_TRB_2_ERROR_GET(temp);
 894
 895         temp = le32toh(trb->dwTrb3);
 896         epno = XHCI_TRB_3_EP_GET(temp);
 897         index = XHCI_TRB_3_SLOT_GET(temp);
 898
 899         /* check if error means halted */
 900         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 901             status != XHCI_TRB_ERROR_SUCCESS);
 902
 903         DPRINTF("slot=%u epno=%u remainder=%u status=%u\n",
 904             index, epno, remainder, status);
 905
 906         if (index > sc->sc_noslot) {
 907                 DPRINTF("Invalid slot.\n");
 908                 return;
 909         }
 910
 911         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 912                 DPRINTF("Invalid endpoint.\n");
 913                 return;
 914         }
 915
 916         /* try to find the USB transfer that generated the event */
 917         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 918                 struct usb_xfer *xfer;
 919                 struct xhci_td *td;
 920                 struct xhci_endpoint_ext *pepext;
 921
 922                 pepext = &sc->sc_hw.devs[index].endp[epno];
 923
 924                 xfer = pepext->xfer[i];
 925                 if (xfer == NULL)
 926                         continue;
 927
 928                 td = xfer->td_transfer_cache;
 929
 930                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 931                         (long long)td_event,
 932                         (long long)td->td_self,
 933                         (long long)td->td_self + sizeof(td->td_trb));
 934
 935                 /*
 936                  * NOTE: Some XHCI implementations might not trigger
 937                  * an event on the last LINK TRB so we need to
 938                  * consider both the last and second last event
 939                  * address as conditions for a successful transfer.
 940                  *
 941                  * NOTE: We assume that the XHCI will only trigger one
 942                  * event per chain of TRBs.
 943                  */
 944
 945                 offset = td_event - td->td_self;
 946
 947                 if (offset >= 0 &&
 948                     offset < (int64_t)sizeof(td->td_trb)) {
 949
 950                         usb_pc_cpu_invalidate(td->page_cache);
 951
 952                         /* compute rest of remainder, if any */
 953                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 954                                 temp = le32toh(td->td_trb[i].dwTrb2);
 955                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 956                         }
 957
 958                         DPRINTFN(5, "New remainder: %u\n", remainder);
 959
 960                         /* clear isochronous transfer errors */
 961                         if (xfer->flags_int.isochronous_xfr) {
 962                                 if (halted) {
 963                                         halted = 0;
 964                                         status = XHCI_TRB_ERROR_SUCCESS;
 965                                         remainder = td->len;
 966                                 }
 967                         }
 968
 969                         /* "td->remainder" is verified later */
 970                         td->remainder = remainder;
 971                         td->status = status;
 972
 973                         usb_pc_cpu_flush(td->page_cache);
 974
 975                         /*
 976                          * 1) Last transfer descriptor makes the
 977                          * transfer done
 978                          */
 979                         if (((void *)td) == xfer->td_transfer_last) {
 980                                 DPRINTF("TD is last\n");
 981                                 xhci_generic_done(xfer);
 982                                 break;
 983                         }
 984
 985                         /*
 986                          * 2) Any kind of error makes the transfer
 987                          * done
 988                          */
 989                         if (halted) {
 990                                 DPRINTF("TD has I/O error\n");
 991                                 xhci_generic_done(xfer);
 992                                 break;
 993                         }
 994
 995                         /*
 996                          * 3) If there is no alternate next transfer,
 997                          * a short packet also makes the transfer done
 998                          */
 999                         if (td->remainder > 0) {
1000                                 if (td->alt_next == NULL) {
1001                                         DPRINTF(
1002                                             "short TD has no alternate next\n");
1003                                         xhci_generic_done(xfer);
1004                                         break;
1005                                 }
1006                                 DPRINTF("TD has short pkt\n");
1007                                 if (xfer->flags_int.short_frames_ok ||
1008                                     xfer->flags_int.isochronous_xfr ||
1009                                     xfer->flags_int.control_xfr) {
1010                                         /* follow the alt next */
1011                                         xfer->td_transfer_cache = td->alt_next;
1012                                         xhci_activate_transfer(xfer);
1013                                         break;
1014                                 }
1015                                 xhci_skip_transfer(xfer);
1016                                 xhci_generic_done(xfer);
1017                                 break;
1018                         }
1019
1020                         /*
1021                          * 4) Transfer complete - go to next TD
1022                          */
1023                         DPRINTF("Following next TD\n");
1024                         xfer->td_transfer_cache = td->obj_next;
1025                         xhci_activate_transfer(xfer);
1026                         break;          /* there should only be one match */
1027                 }
1028         }
1029 }
1030
1031 static int
1032 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1033 {
1034         if (sc->sc_cmd_addr == trb->qwTrb0) {
1035                 DPRINTF("Received command event\n");
1036                 sc->sc_cmd_result[0] = trb->dwTrb2;
1037                 sc->sc_cmd_result[1] = trb->dwTrb3;
1038                 cv_signal(&sc->sc_cmd_cv);
1039                 return (1);     /* command match */
1040         }
1041         return (0);
1042 }
1043
1044 static int
1045 xhci_interrupt_poll(struct xhci_softc *sc)
1046 {
1047         struct usb_page_search buf_res;
1048         struct xhci_hw_root *phwr;
1049         uint64_t addr;
1050         uint32_t temp;
1051         int retval = 0;
1052         uint16_t i;
1053         uint8_t event;
1054         uint8_t j;
1055         uint8_t k;
1056         uint8_t t;
1057
1058         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1059
1060         phwr = buf_res.buffer;
1061
1062         /* Receive any events */
1063
1064         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1065
1066         i = sc->sc_event_idx;
1067         j = sc->sc_event_ccs;
1068         t = 2;
1069
1070         while (1) {
1071
1072                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1073
1074                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1075
1076                 if (j != k)
1077                         break;
1078
1079                 event = XHCI_TRB_3_TYPE_GET(temp);
1080
1081                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1082                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1083                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1084                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1085
1086                 switch (event) {
1087                 case XHCI_TRB_EVENT_TRANSFER:
1088                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1089                         break;
1090                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1091                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1092                         break;
1093                 default:
1094                         DPRINTF("Unhandled event = %u\n", event);
1095                         break;
1096                 }
1097
1098                 i++;
1099
1100                 if (i == XHCI_MAX_EVENTS) {
1101                         i = 0;
1102                         j ^= 1;
1103
1104                         /* check for timeout */
1105                         if (!--t)
1106                                 break;
1107                 }
1108         }
1109
1110         sc->sc_event_idx = i;
1111         sc->sc_event_ccs = j;
1112
1113         /*
1114          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1115          * latched. That means to activate the register we need to
1116          * write both the low and high double word of the 64-bit
1117          * register.
1118          */
1119
1120         addr = buf_res.physaddr;
1121         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1122
1123         /* try to clear busy bit */
1124         addr |= XHCI_ERDP_LO_BUSY;
1125
1126         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1127         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1128
1129         return (retval);
1130 }
1131
1132 static usb_error_t
1133 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1134     uint16_t timeout_ms)
1135 {
1136         struct usb_page_search buf_res;
1137         struct xhci_hw_root *phwr;
1138         uint64_t addr;
1139         uint32_t temp;
1140         uint8_t i;
1141         uint8_t j;
1142         uint8_t timeout = 0;
1143         int err;
1144
1145         XHCI_CMD_ASSERT_LOCKED(sc);
1146
1147         /* get hardware root structure */
1148
1149         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1150
1151         phwr = buf_res.buffer;
1152
1153         /* Queue command */
1154
1155         USB_BUS_LOCK(&sc->sc_bus);
1156 retry:
1157         i = sc->sc_command_idx;
1158         j = sc->sc_command_ccs;
1159
1160         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1161             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1162             (long long)le64toh(trb->qwTrb0),
1163             (long)le32toh(trb->dwTrb2),
1164             (long)le32toh(trb->dwTrb3));
1165
1166         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1167         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1168
1169         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1170
1171         temp = trb->dwTrb3;
1172
1173         if (j)
1174                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1175         else
1176                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1177
1178         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1179
1180         phwr->hwr_commands[i].dwTrb3 = temp;
1181
1182         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1183
1184         addr = buf_res.physaddr;
1185         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1186
1187         sc->sc_cmd_addr = htole64(addr);
1188
1189         i++;
1190
1191         if (i == (XHCI_MAX_COMMANDS - 1)) {
1192
1193                 if (j) {
1194                         temp = htole32(XHCI_TRB_3_TC_BIT |
1195                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1196                             XHCI_TRB_3_CYCLE_BIT);
1197                 } else {
1198                         temp = htole32(XHCI_TRB_3_TC_BIT |
1199                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1200                 }
1201
1202                 phwr->hwr_commands[i].dwTrb3 = temp;
1203
1204                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1205
1206                 i = 0;
1207                 j ^= 1;
1208         }
1209
1210         sc->sc_command_idx = i;
1211         sc->sc_command_ccs = j;
1212
1213         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1214
1215         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1216             USB_MS_TO_TICKS(timeout_ms));
1217
1218         /*
1219          * In some error cases event interrupts are not generated.
1220          * Poll one time to see if the command has completed.
1221          */
1222         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1223                 DPRINTF("Command was completed when polling\n");
1224                 err = 0;
1225         }
1226         if (err != 0) {
1227                 DPRINTF("Command timeout!\n");
1228                 /*
1229                  * After some weeks of continuous operation, it has
1230                  * been observed that the ASMedia Technology, ASM1042
1231                  * SuperSpeed USB Host Controller can suddenly stop
1232                  * accepting commands via the command queue. Try to
1233                  * first reset the command queue. If that fails do a
1234                  * host controller reset.
1235                  */
1236                 if (timeout == 0 &&
1237                     xhci_reset_command_queue_locked(sc) == 0) {
1238                         temp = le32toh(trb->dwTrb3);
1239
1240                         /*
1241                          * Avoid infinite XHCI reset loops if the set
1242                          * address command fails to respond due to a
1243                          * non-enumerating device:
1244                          */
1245                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1246                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1247                                 DPRINTF("Set address timeout\n");
1248                         } else {
1249                                 timeout = 1;
1250                                 goto retry;
1251                         }
1252                 } else {
1253                         DPRINTF("Controller reset!\n");
1254                         usb_bus_reset_async_locked(&sc->sc_bus);
1255                 }
1256                 err = USB_ERR_TIMEOUT;
1257                 trb->dwTrb2 = 0;
1258                 trb->dwTrb3 = 0;
1259         } else {
1260                 temp = le32toh(sc->sc_cmd_result[0]);
1261                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1262                         err = USB_ERR_IOERROR;
1263
1264                 trb->dwTrb2 = sc->sc_cmd_result[0];
1265                 trb->dwTrb3 = sc->sc_cmd_result[1];
1266         }
1267
1268         USB_BUS_UNLOCK(&sc->sc_bus);
1269
1270         return (err);
1271 }
1272
1273 #if 0
1274 static usb_error_t
1275 xhci_cmd_nop(struct xhci_softc *sc)
1276 {
1277         struct xhci_trb trb;
1278         uint32_t temp;
1279
1280         DPRINTF("\n");
1281
1282         trb.qwTrb0 = 0;
1283         trb.dwTrb2 = 0;
1284         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1285
1286         trb.dwTrb3 = htole32(temp);
1287
1288         return (xhci_do_command(sc, &trb, 100 /* ms */));
1289 }
1290 #endif
1291
1292 static usb_error_t
1293 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1294 {
1295         struct xhci_trb trb;
1296         uint32_t temp;
1297         usb_error_t err;
1298
1299         DPRINTF("\n");
1300
1301         trb.qwTrb0 = 0;
1302         trb.dwTrb2 = 0;
1303         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1304
1305         err = xhci_do_command(sc, &trb, 100 /* ms */);
1306         if (err)
1307                 goto done;
1308
1309         temp = le32toh(trb.dwTrb3);
1310
1311         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1312
1313 done:
1314         return (err);
1315 }
1316
1317 static usb_error_t
1318 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1319 {
1320         struct xhci_trb trb;
1321         uint32_t temp;
1322
1323         DPRINTF("\n");
1324
1325         trb.qwTrb0 = 0;
1326         trb.dwTrb2 = 0;
1327         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1328             XHCI_TRB_3_SLOT_SET(slot_id);
1329
1330         trb.dwTrb3 = htole32(temp);
1331
1332         return (xhci_do_command(sc, &trb, 100 /* ms */));
1333 }
1334
1335 static usb_error_t
1336 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1337     uint8_t bsr, uint8_t slot_id)
1338 {
1339         struct xhci_trb trb;
1340         uint32_t temp;
1341
1342         DPRINTF("\n");
1343
1344         trb.qwTrb0 = htole64(input_ctx);
1345         trb.dwTrb2 = 0;
1346         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1347             XHCI_TRB_3_SLOT_SET(slot_id);
1348
1349         if (bsr)
1350                 temp |= XHCI_TRB_3_BSR_BIT;
1351
1352         trb.dwTrb3 = htole32(temp);
1353
1354         return (xhci_do_command(sc, &trb, 500 /* ms */));
1355 }
1356
1357 static usb_error_t
1358 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1359 {
1360         struct usb_page_search buf_inp;
1361         struct usb_page_search buf_dev;
1362         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1363         struct xhci_hw_dev *hdev;
1364         struct xhci_dev_ctx *pdev;
1365         struct xhci_endpoint_ext *pepext;
1366         uint32_t temp;
1367         uint16_t mps;
1368         usb_error_t err;
1369         uint8_t index;
1370
1371         /* the root HUB case is not handled here */
1372         if (udev->parent_hub == NULL)
1373                 return (USB_ERR_INVAL);
1374
1375         index = udev->controller_slot_id;
1376
1377         hdev =  &sc->sc_hw.devs[index];
1378
1379         if (mtx != NULL)
1380                 mtx_unlock(mtx);
1381
1382         XHCI_CMD_LOCK(sc);
1383
1384         switch (hdev->state) {
1385         case XHCI_ST_DEFAULT:
1386         case XHCI_ST_ENABLED:
1387
1388                 hdev->state = XHCI_ST_ENABLED;
1389
1390                 /* set configure mask to slot and EP0 */
1391                 xhci_configure_mask(udev, 3, 0);
1392
1393                 /* configure input slot context structure */
1394                 err = xhci_configure_device(udev);
1395
1396                 if (err != 0) {
1397                         DPRINTF("Could not configure device\n");
1398                         break;
1399                 }
1400
1401                 /* configure input endpoint context structure */
1402                 switch (udev->speed) {
1403                 case USB_SPEED_LOW:
1404                 case USB_SPEED_FULL:
1405                         mps = 8;
1406                         break;
1407                 case USB_SPEED_HIGH:
1408                         mps = 64;
1409                         break;
1410                 default:
1411                         mps = 512;
1412                         break;
1413                 }
1414
1415                 pepext = xhci_get_endpoint_ext(udev,
1416                     &udev->ctrl_ep_desc);
1417
1418                 /* ensure the control endpoint is setup again */
1419                 USB_BUS_LOCK(udev->bus);
1420                 pepext->trb_halted = 1;
1421                 pepext->trb_running = 0;
1422                 USB_BUS_UNLOCK(udev->bus);
1423
1424                 err = xhci_configure_endpoint(udev,
1425                     &udev->ctrl_ep_desc, pepext,
1426                     0, 1, 1, 0, mps, mps);
1427
1428                 if (err != 0) {
1429                         DPRINTF("Could not configure default endpoint\n");
1430                         break;
1431                 }
1432
1433                 /* execute set address command */
1434                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1435
1436                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1437                     (address == 0), index);
1438
1439                 if (err != 0) {
1440                         temp = le32toh(sc->sc_cmd_result[0]);
1441                         if (address == 0 && sc->sc_port_route != NULL &&
1442                             XHCI_TRB_2_ERROR_GET(temp) ==
1443                             XHCI_TRB_ERROR_PARAMETER) {
1444                                 /* LynxPoint XHCI - ports are not switchable */
1445                                 /* Un-route all ports from the XHCI */
1446                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1447                         }
1448                         DPRINTF("Could not set address "
1449                             "for slot %u.\n", index);
1450                         if (address != 0)
1451                                 break;
1452                 }
1453
1454                 /* update device address to new value */
1455
1456                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1457                 pdev = buf_dev.buffer;
1458                 usb_pc_cpu_invalidate(&hdev->device_pc);
1459
1460                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1461                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1462
1463                 /* update device state to new value */
1464
1465                 if (address != 0)
1466                         hdev->state = XHCI_ST_ADDRESSED;
1467                 else
1468                         hdev->state = XHCI_ST_DEFAULT;
1469                 break;
1470
1471         default:
1472                 DPRINTF("Wrong state for set address.\n");
1473                 err = USB_ERR_IOERROR;
1474                 break;
1475         }
1476         XHCI_CMD_UNLOCK(sc);
1477
1478         if (mtx != NULL)
1479                 mtx_lock(mtx);
1480
1481         return (err);
1482 }
1483
1484 static usb_error_t
1485 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1486     uint8_t deconfigure, uint8_t slot_id)
1487 {
1488         struct xhci_trb trb;
1489         uint32_t temp;
1490
1491         DPRINTF("\n");
1492
1493         trb.qwTrb0 = htole64(input_ctx);
1494         trb.dwTrb2 = 0;
1495         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1496             XHCI_TRB_3_SLOT_SET(slot_id);
1497
1498         if (deconfigure)
1499                 temp |= XHCI_TRB_3_DCEP_BIT;
1500
1501         trb.dwTrb3 = htole32(temp);
1502
1503         return (xhci_do_command(sc, &trb, 100 /* ms */));
1504 }
1505
1506 static usb_error_t
1507 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1508     uint8_t slot_id)
1509 {
1510         struct xhci_trb trb;
1511         uint32_t temp;
1512
1513         DPRINTF("\n");
1514
1515         trb.qwTrb0 = htole64(input_ctx);
1516         trb.dwTrb2 = 0;
1517         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1518             XHCI_TRB_3_SLOT_SET(slot_id);
1519         trb.dwTrb3 = htole32(temp);
1520
1521         return (xhci_do_command(sc, &trb, 100 /* ms */));
1522 }
1523
1524 static usb_error_t
1525 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1526     uint8_t ep_id, uint8_t slot_id)
1527 {
1528         struct xhci_trb trb;
1529         uint32_t temp;
1530
1531         DPRINTF("\n");
1532
1533         trb.qwTrb0 = 0;
1534         trb.dwTrb2 = 0;
1535         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1536             XHCI_TRB_3_SLOT_SET(slot_id) |
1537             XHCI_TRB_3_EP_SET(ep_id);
1538
1539         if (preserve)
1540                 temp |= XHCI_TRB_3_PRSV_BIT;
1541
1542         trb.dwTrb3 = htole32(temp);
1543
1544         return (xhci_do_command(sc, &trb, 100 /* ms */));
1545 }
1546
1547 static usb_error_t
1548 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1549     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1550 {
1551         struct xhci_trb trb;
1552         uint32_t temp;
1553
1554         DPRINTF("\n");
1555
1556         trb.qwTrb0 = htole64(dequeue_ptr);
1557
1558         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1559         trb.dwTrb2 = htole32(temp);
1560
1561         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1562             XHCI_TRB_3_SLOT_SET(slot_id) |
1563             XHCI_TRB_3_EP_SET(ep_id);
1564         trb.dwTrb3 = htole32(temp);
1565
1566         return (xhci_do_command(sc, &trb, 100 /* ms */));
1567 }
1568
1569 static usb_error_t
1570 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1571     uint8_t ep_id, uint8_t slot_id)
1572 {
1573         struct xhci_trb trb;
1574         uint32_t temp;
1575
1576         DPRINTF("\n");
1577
1578         trb.qwTrb0 = 0;
1579         trb.dwTrb2 = 0;
1580         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1581             XHCI_TRB_3_SLOT_SET(slot_id) |
1582             XHCI_TRB_3_EP_SET(ep_id);
1583
1584         if (suspend)
1585                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1586
1587         trb.dwTrb3 = htole32(temp);
1588
1589         return (xhci_do_command(sc, &trb, 100 /* ms */));
1590 }
1591
1592 static usb_error_t
1593 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1594 {
1595         struct xhci_trb trb;
1596         uint32_t temp;
1597
1598         DPRINTF("\n");
1599
1600         trb.qwTrb0 = 0;
1601         trb.dwTrb2 = 0;
1602         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1603             XHCI_TRB_3_SLOT_SET(slot_id);
1604
1605         trb.dwTrb3 = htole32(temp);
1606
1607         return (xhci_do_command(sc, &trb, 100 /* ms */));
1608 }
1609
1610 /*------------------------------------------------------------------------*
1611  *      xhci_interrupt - XHCI interrupt handler
1612  *------------------------------------------------------------------------*/
1613 void
1614 xhci_interrupt(struct xhci_softc *sc)
1615 {
1616         uint32_t status;
1617         uint32_t temp;
1618
1619         USB_BUS_LOCK(&sc->sc_bus);
1620
1621         status = XREAD4(sc, oper, XHCI_USBSTS);
1622
1623         /* acknowledge interrupts, if any */
1624         if (status != 0) {
1625                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1626                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1627         }
1628
1629         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1630
1631         /* force clearing of pending interrupts */
1632         if (temp & XHCI_IMAN_INTR_PEND)
1633                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1634
1635         /* check for event(s) */
1636         xhci_interrupt_poll(sc);
1637
1638         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1639             XHCI_STS_HSE | XHCI_STS_HCE)) {
1640
1641                 if (status & XHCI_STS_PCD) {
1642                         xhci_root_intr(sc);
1643                 }
1644
1645                 if (status & XHCI_STS_HCH) {
1646                         printf("%s: host controller halted\n",
1647                             __FUNCTION__);
1648                 }
1649
1650                 if (status & XHCI_STS_HSE) {
1651                         printf("%s: host system error\n",
1652                             __FUNCTION__);
1653                 }
1654
1655                 if (status & XHCI_STS_HCE) {
1656                         printf("%s: host controller error\n",
1657                            __FUNCTION__);
1658                 }
1659         }
1660         USB_BUS_UNLOCK(&sc->sc_bus);
1661 }
1662
1663 /*------------------------------------------------------------------------*
1664  *      xhci_timeout - XHCI timeout handler
1665  *------------------------------------------------------------------------*/
1666 static void
1667 xhci_timeout(void *arg)
1668 {
1669         struct usb_xfer *xfer = arg;
1670
1671         DPRINTF("xfer=%p\n", xfer);
1672
1673         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1674
1675         /* transfer is transferred */
1676         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1677 }
1678
1679 static void
1680 xhci_do_poll(struct usb_bus *bus)
1681 {
1682         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1683
1684         USB_BUS_LOCK(&sc->sc_bus);
1685         xhci_interrupt_poll(sc);
1686         USB_BUS_UNLOCK(&sc->sc_bus);
1687 }
1688
1689 static void
1690 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1691 {
1692         struct usb_page_search buf_res;
1693         struct xhci_td *td;
1694         struct xhci_td *td_next;
1695         struct xhci_td *td_alt_next;
1696         struct xhci_td *td_first;
1697         uint32_t buf_offset;
1698         uint32_t average;
1699         uint32_t len_old;
1700         uint32_t npkt_off;
1701         uint32_t dword;
1702         uint8_t shortpkt_old;
1703         uint8_t precompute;
1704         uint8_t x;
1705
1706         td_alt_next = NULL;
1707         buf_offset = 0;
1708         shortpkt_old = temp->shortpkt;
1709         len_old = temp->len;
1710         npkt_off = 0;
1711         precompute = 1;
1712
1713 restart:
1714
1715         td = temp->td;
1716         td_next = td_first = temp->td_next;
1717
1718         while (1) {
1719
1720                 if (temp->len == 0) {
1721
1722                         if (temp->shortpkt)
1723                                 break;
1724
1725                         /* send a Zero Length Packet, ZLP, last */
1726
1727                         temp->shortpkt = 1;
1728                         average = 0;
1729
1730                 } else {
1731
1732                         average = temp->average;
1733
1734                         if (temp->len < average) {
1735                                 if (temp->len % temp->max_packet_size) {
1736                                         temp->shortpkt = 1;
1737                                 }
1738                                 average = temp->len;
1739                         }
1740                 }
1741
1742                 if (td_next == NULL)
1743                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1744
1745                 /* get next TD */
1746
1747                 td = td_next;
1748                 td_next = td->obj_next;
1749
1750                 /* check if we are pre-computing */
1751
1752                 if (precompute) {
1753
1754                         /* update remaining length */
1755
1756                         temp->len -= average;
1757
1758                         continue;
1759                 }
1760                 /* fill out current TD */
1761
1762                 td->len = average;
1763                 td->remainder = 0;
1764                 td->status = 0;
1765
1766                 /* update remaining length */
1767
1768                 temp->len -= average;
1769
1770                 /* reset TRB index */
1771
1772                 x = 0;
1773
1774                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1775                         /* immediate data */
1776
1777                         if (average > 8)
1778                                 average = 8;
1779
1780                         td->td_trb[0].qwTrb0 = 0;
1781
1782                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1783                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1784                            average);
1785
1786                         dword = XHCI_TRB_2_BYTES_SET(8) |
1787                             XHCI_TRB_2_TDSZ_SET(0) |
1788                             XHCI_TRB_2_IRQ_SET(0);
1789
1790                         td->td_trb[0].dwTrb2 = htole32(dword);
1791
1792                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1793                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1794
1795                         /* check wLength */
1796                         if (td->td_trb[0].qwTrb0 &
1797                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1798                                 if (td->td_trb[0].qwTrb0 &
1799                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1800                                         dword |= XHCI_TRB_3_TRT_IN;
1801                                 else
1802                                         dword |= XHCI_TRB_3_TRT_OUT;
1803                         }
1804
1805                         td->td_trb[0].dwTrb3 = htole32(dword);
1806 #ifdef USB_DEBUG
1807                         xhci_dump_trb(&td->td_trb[x]);
1808 #endif
1809                         x++;
1810
1811                 } else do {
1812
1813                         uint32_t npkt;
1814
1815                         /* fill out buffer pointers */
1816
1817                         if (average == 0) {
1818                                 memset(&buf_res, 0, sizeof(buf_res));
1819                         } else {
1820                                 usbd_get_page(temp->pc, temp->offset +
1821                                     buf_offset, &buf_res);
1822
1823                                 /* get length to end of page */
1824                                 if (buf_res.length > average)
1825                                         buf_res.length = average;
1826
1827                                 /* check for maximum length */
1828                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1829                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1830
1831                                 npkt_off += buf_res.length;
1832                         }
1833
1834                         /* set up npkt */
1835                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1836                             temp->max_packet_size;
1837
1838                         if (npkt == 0)
1839                                 npkt = 1;
1840                         else if (npkt > 31)
1841                                 npkt = 31;
1842
1843                         /* fill out TRB's */
1844                         td->td_trb[x].qwTrb0 =
1845                             htole64((uint64_t)buf_res.physaddr);
1846
1847                         dword =
1848                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1849                           XHCI_TRB_2_TDSZ_SET(npkt) |
1850                           XHCI_TRB_2_IRQ_SET(0);
1851
1852                         td->td_trb[x].dwTrb2 = htole32(dword);
1853
1854                         switch (temp->trb_type) {
1855                         case XHCI_TRB_TYPE_ISOCH:
1856                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1857                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1858                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1859                                 if (td != td_first) {
1860                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1861                                 } else if (temp->do_isoc_sync != 0) {
1862                                         temp->do_isoc_sync = 0;
1863                                         /* wait until "isoc_frame" */
1864                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1865                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1866                                 } else {
1867                                         /* start data transfer at next interval */
1868                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1869                                             XHCI_TRB_3_ISO_SIA_BIT;
1870                                 }
1871                                 if (temp->direction == UE_DIR_IN)
1872                                         dword |= XHCI_TRB_3_ISP_BIT;
1873                                 break;
1874                         case XHCI_TRB_TYPE_DATA_STAGE:
1875                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1876                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1877                                 if (temp->direction == UE_DIR_IN)
1878                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1879                                 /*
1880                                  * Section 3.2.9 in the XHCI
1881                                  * specification about control
1882                                  * transfers says that we should use a
1883                                  * normal-TRB if there are more TRBs
1884                                  * extending the data-stage
1885                                  * TRB. Update the "trb_type".
1886                                  */
1887                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1888                                 break;
1889                         case XHCI_TRB_TYPE_STATUS_STAGE:
1890                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1891                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1892                                 if (temp->direction == UE_DIR_IN)
1893                                         dword |= XHCI_TRB_3_DIR_IN;
1894                                 break;
1895                         default:        /* XHCI_TRB_TYPE_NORMAL */
1896                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1897                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1898                                 if (temp->direction == UE_DIR_IN)
1899                                         dword |= XHCI_TRB_3_ISP_BIT;
1900                                 break;
1901                         }
1902                         td->td_trb[x].dwTrb3 = htole32(dword);
1903
1904                         average -= buf_res.length;
1905                         buf_offset += buf_res.length;
1906 #ifdef USB_DEBUG
1907                         xhci_dump_trb(&td->td_trb[x]);
1908 #endif
1909                         x++;
1910
1911                 } while (average != 0);
1912
1913                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1914
1915                 /* store number of data TRB's */
1916
1917                 td->ntrb = x;
1918
1919                 DPRINTF("NTRB=%u\n", x);
1920
1921                 /* fill out link TRB */
1922
1923                 if (td_next != NULL) {
1924                         /* link the current TD with the next one */
1925                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1926                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1927                 } else {
1928                         /* this field will get updated later */
1929                         DPRINTF("NOLINK\n");
1930                 }
1931
1932                 dword = XHCI_TRB_2_IRQ_SET(0);
1933
1934                 td->td_trb[x].dwTrb2 = htole32(dword);
1935
1936                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1937                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1938                     /*
1939                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1940                      * frame only receives a single short packet event
1941                      * by setting the CHAIN bit in the LINK field. In
1942                      * addition some XHCI controllers have problems
1943                      * sending a ZLP unless the CHAIN-BIT is set in
1944                      * the LINK TRB.
1945                      */
1946                     XHCI_TRB_3_CHAIN_BIT;
1947
1948                 td->td_trb[x].dwTrb3 = htole32(dword);
1949
1950                 td->alt_next = td_alt_next;
1951 #ifdef USB_DEBUG
1952                 xhci_dump_trb(&td->td_trb[x]);
1953 #endif
1954                 usb_pc_cpu_flush(td->page_cache);
1955         }
1956
1957         if (precompute) {
1958                 precompute = 0;
1959
1960                 /* set up alt next pointer, if any */
1961                 if (temp->last_frame) {
1962                         td_alt_next = NULL;
1963                 } else {
1964                         /* we use this field internally */
1965                         td_alt_next = td_next;
1966                 }
1967
1968                 /* restore */
1969                 temp->shortpkt = shortpkt_old;
1970                 temp->len = len_old;
1971                 goto restart;
1972         }
1973
1974         /*
1975          * Remove cycle bit from the first TRB if we are
1976          * stepping them:
1977          */
1978         if (temp->step_td != 0) {
1979                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1980                 usb_pc_cpu_flush(td_first->page_cache);
1981         }
1982
1983         /* clear TD SIZE to zero, hence this is the last TRB */
1984         /* remove chain bit because this is the last data TRB in the chain */
1985         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1986         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1987         /* remove CHAIN-BIT from last LINK TRB */
1988         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1989
1990         usb_pc_cpu_flush(td->page_cache);
1991
1992         temp->td = td;
1993         temp->td_next = td_next;
1994 }
1995
1996 static void
1997 xhci_setup_generic_chain(struct usb_xfer *xfer)
1998 {
1999         struct xhci_std_temp temp;
2000         struct xhci_td *td;
2001         uint32_t x;
2002         uint32_t y;
2003         uint8_t mult;
2004
2005         temp.do_isoc_sync = 0;
2006         temp.step_td = 0;
2007         temp.tbc = 0;
2008         temp.tlbpc = 0;
2009         temp.average = xfer->max_hc_frame_size;
2010         temp.max_packet_size = xfer->max_packet_size;
2011         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2012         temp.pc = NULL;
2013         temp.last_frame = 0;
2014         temp.offset = 0;
2015         temp.multishort = xfer->flags_int.isochronous_xfr ||
2016             xfer->flags_int.control_xfr ||
2017             xfer->flags_int.short_frames_ok;
2018
2019         /* toggle the DMA set we are using */
2020         xfer->flags_int.curr_dma_set ^= 1;
2021
2022         /* get next DMA set */
2023         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2024
2025         temp.td = NULL;
2026         temp.td_next = td;
2027
2028         xfer->td_transfer_first = td;
2029         xfer->td_transfer_cache = td;
2030
2031         if (xfer->flags_int.isochronous_xfr) {
2032                 uint8_t shift;
2033
2034                 /* compute multiplier for ISOCHRONOUS transfers */
2035                 mult = xfer->endpoint->ecomp ?
2036                     (xfer->endpoint->ecomp->bmAttributes & 3) : 0;
2037                 /* check for USB 2.0 multiplier */
2038                 if (mult == 0) {
2039                         mult = (xfer->endpoint->edesc->
2040                             wMaxPacketSize[1] >> 3) & 3;
2041                 }
2042                 /* range check */
2043                 if (mult > 2)
2044                         mult = 3;
2045                 else
2046                         mult++;
2047
2048                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2049
2050                 DPRINTF("MFINDEX=0x%08x\n", x);
2051
2052                 switch (usbd_get_speed(xfer->xroot->udev)) {
2053                 case USB_SPEED_FULL:
2054                         shift = 3;
2055                         temp.isoc_delta = 8;    /* 1ms */
2056                         x += temp.isoc_delta - 1;
2057                         x &= ~(temp.isoc_delta - 1);
2058                         break;
2059                 default:
2060                         shift = usbd_xfer_get_fps_shift(xfer);
2061                         temp.isoc_delta = 1U << shift;
2062                         x += temp.isoc_delta - 1;
2063                         x &= ~(temp.isoc_delta - 1);
2064                         /* simple frame load balancing */
2065                         x += xfer->endpoint->usb_uframe;
2066                         break;
2067                 }
2068
2069                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2070
2071                 if ((xfer->endpoint->is_synced == 0) ||
2072                     (y < (xfer->nframes << shift)) ||
2073                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2074                         /*
2075                          * If there is data underflow or the pipe
2076                          * queue is empty we schedule the transfer a
2077                          * few frames ahead of the current frame
2078                          * position. Else two isochronous transfers
2079                          * might overlap.
2080                          */
2081                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2082                         xfer->endpoint->is_synced = 1;
2083                         temp.do_isoc_sync = 1;
2084
2085                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2086                 }
2087
2088                 /* compute isochronous completion time */
2089
2090                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2091
2092                 xfer->isoc_time_complete =
2093                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2094                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2095
2096                 x = 0;
2097                 temp.isoc_frame = xfer->endpoint->isoc_next;
2098                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2099
2100                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2101
2102         } else if (xfer->flags_int.control_xfr) {
2103
2104                 /* check if we should prepend a setup message */
2105
2106                 if (xfer->flags_int.control_hdr) {
2107
2108                         temp.len = xfer->frlengths[0];
2109                         temp.pc = xfer->frbuffers + 0;
2110                         temp.shortpkt = temp.len ? 1 : 0;
2111                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2112                         temp.direction = 0;
2113
2114                         /* check for last frame */
2115                         if (xfer->nframes == 1) {
2116                                 /* no STATUS stage yet, SETUP is last */
2117                                 if (xfer->flags_int.control_act)
2118                                         temp.last_frame = 1;
2119                         }
2120
2121                         xhci_setup_generic_chain_sub(&temp);
2122                 }
2123                 x = 1;
2124                 mult = 1;
2125                 temp.isoc_delta = 0;
2126                 temp.isoc_frame = 0;
2127                 temp.trb_type = xfer->flags_int.control_did_data ?
2128                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2129         } else {
2130                 x = 0;
2131                 mult = 1;
2132                 temp.isoc_delta = 0;
2133                 temp.isoc_frame = 0;
2134                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2135         }
2136
2137         if (x != xfer->nframes) {
2138                 /* set up page_cache pointer */
2139                 temp.pc = xfer->frbuffers + x;
2140                 /* set endpoint direction */
2141                 temp.direction = UE_GET_DIR(xfer->endpointno);
2142         }
2143
2144         while (x != xfer->nframes) {
2145
2146                 /* DATA0 / DATA1 message */
2147
2148                 temp.len = xfer->frlengths[x];
2149                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2150                     x != 0 && temp.multishort == 0);
2151
2152                 x++;
2153
2154                 if (x == xfer->nframes) {
2155                         if (xfer->flags_int.control_xfr) {
2156                                 /* no STATUS stage yet, DATA is last */
2157                                 if (xfer->flags_int.control_act)
2158                                         temp.last_frame = 1;
2159                         } else {
2160                                 temp.last_frame = 1;
2161                         }
2162                 }
2163                 if (temp.len == 0) {
2164
2165                         /* make sure that we send an USB packet */
2166
2167                         temp.shortpkt = 0;
2168
2169                         temp.tbc = 0;
2170                         temp.tlbpc = mult - 1;
2171
2172                 } else if (xfer->flags_int.isochronous_xfr) {
2173
2174                         uint8_t tdpc;
2175
2176                         /*
2177                          * Isochronous transfers don't have short
2178                          * packet termination:
2179                          */
2180
2181                         temp.shortpkt = 1;
2182
2183                         /* isochronous transfers have a transfer limit */
2184
2185                         if (temp.len > xfer->max_frame_size)
2186                                 temp.len = xfer->max_frame_size;
2187
2188                         /* compute TD packet count */
2189                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2190                             xfer->max_packet_size;
2191
2192                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2193                         temp.tlbpc = (tdpc % mult);
2194
2195                         if (temp.tlbpc == 0)
2196                                 temp.tlbpc = mult - 1;
2197                         else
2198                                 temp.tlbpc--;
2199                 } else {
2200
2201                         /* regular data transfer */
2202
2203                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2204                 }
2205
2206                 xhci_setup_generic_chain_sub(&temp);
2207
2208                 if (xfer->flags_int.isochronous_xfr) {
2209                         temp.offset += xfer->frlengths[x - 1];
2210                         temp.isoc_frame += temp.isoc_delta;
2211                 } else {
2212                         /* get next Page Cache pointer */
2213                         temp.pc = xfer->frbuffers + x;
2214                 }
2215         }
2216
2217         /* check if we should append a status stage */
2218
2219         if (xfer->flags_int.control_xfr &&
2220             !xfer->flags_int.control_act) {
2221
2222                 /*
2223                  * Send a DATA1 message and invert the current
2224                  * endpoint direction.
2225                  */
2226 #ifdef XHCI_STEP_STATUS_STAGE
2227                 temp.step_td = (xfer->nframes != 0);
2228 #else
2229                 temp.step_td = 0;
2230 #endif
2231                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2232                 temp.len = 0;
2233                 temp.pc = NULL;
2234                 temp.shortpkt = 0;
2235                 temp.last_frame = 1;
2236                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2237
2238                 xhci_setup_generic_chain_sub(&temp);
2239         }
2240
2241         td = temp.td;
2242
2243         /* must have at least one frame! */
2244
2245         xfer->td_transfer_last = td;
2246
2247         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2248 }
2249
2250 static void
2251 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2252 {
2253         struct usb_page_search buf_res;
2254         struct xhci_dev_ctx_addr *pdctxa;
2255
2256         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2257
2258         pdctxa = buf_res.buffer;
2259
2260         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2261
2262         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2263
2264         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2265 }
2266
2267 static usb_error_t
2268 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2269 {
2270         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2271         struct usb_page_search buf_inp;
2272         struct xhci_input_dev_ctx *pinp;
2273         uint32_t temp;
2274         uint8_t index;
2275         uint8_t x;
2276
2277         index = udev->controller_slot_id;
2278
2279         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2280
2281         pinp = buf_inp.buffer;
2282
2283         if (drop) {
2284                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2285                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2286                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2287         } else {
2288                 /*
2289                  * Some hardware requires that we drop the endpoint
2290                  * context before adding it again:
2291                  */
2292                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2293                     mask & XHCI_INCTX_NON_CTRL_MASK);
2294
2295                 /* Add new endpoint context */
2296                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2297
2298                 /* find most significant set bit */
2299                 for (x = 31; x != 1; x--) {
2300                         if (mask & (1 << x))
2301                                 break;
2302                 }
2303
2304                 /* adjust */
2305                 x--;
2306
2307                 /* figure out the maximum number of contexts */
2308                 if (x > sc->sc_hw.devs[index].context_num)
2309                         sc->sc_hw.devs[index].context_num = x;
2310                 else
2311                         x = sc->sc_hw.devs[index].context_num;
2312
2313                 /* update number of contexts */
2314                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2315                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2316                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2317                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2318         }
2319         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2320         return (0);
2321 }
2322
2323 static usb_error_t
2324 xhci_configure_endpoint(struct usb_device *udev,
2325     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2326     uint16_t interval, uint8_t max_packet_count,
2327     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2328     uint16_t max_frame_size)
2329 {
2330         struct usb_page_search buf_inp;
2331         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2332         struct xhci_input_dev_ctx *pinp;
2333         uint64_t ring_addr = pepext->physaddr;
2334         uint32_t temp;
2335         uint8_t index;
2336         uint8_t epno;
2337         uint8_t type;
2338
2339         index = udev->controller_slot_id;
2340
2341         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2342
2343         pinp = buf_inp.buffer;
2344
2345         epno = edesc->bEndpointAddress;
2346         type = edesc->bmAttributes & UE_XFERTYPE;
2347
2348         if (type == UE_CONTROL)
2349                 epno |= UE_DIR_IN;
2350
2351         epno = XHCI_EPNO2EPID(epno);
2352
2353         if (epno == 0)
2354                 return (USB_ERR_NO_PIPE);               /* invalid */
2355
2356         if (max_packet_count == 0)
2357                 return (USB_ERR_BAD_BUFSIZE);
2358
2359         max_packet_count--;
2360
2361         if (mult == 0)
2362                 return (USB_ERR_BAD_BUFSIZE);
2363
2364         /* store bMaxPacketSize for control endpoints */
2365         pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2366         usb_pc_cpu_flush(pepext->page_cache);
2367
2368         temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2369             XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2370             XHCI_EPCTX_0_LSA_SET(0);
2371
2372         switch (udev->speed) {
2373         case USB_SPEED_FULL:
2374         case USB_SPEED_LOW:
2375                 /* 1ms -> 125us */
2376                 fps_shift += 3;
2377                 break;
2378         default:
2379                 break;
2380         }
2381
2382         switch (type) {
2383         case UE_INTERRUPT:
2384                 if (fps_shift > 3)
2385                         fps_shift--;
2386                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2387                 break;
2388         case UE_ISOCHRONOUS:
2389                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2390
2391                 switch (udev->speed) {
2392                 case USB_SPEED_SUPER:
2393                         if (mult > 3)
2394                                 mult = 3;
2395                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2396                         max_packet_count /= mult;
2397                         break;
2398                 default:
2399                         break;
2400                 }
2401                 break;
2402         default:
2403                 break;
2404         }
2405
2406         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2407
2408         temp =
2409             XHCI_EPCTX_1_HID_SET(0) |
2410             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2411             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2412
2413         /*
2414          * Always enable the "three strikes and you are gone" feature
2415          * except for ISOCHRONOUS endpoints. This is suggested by
2416          * section 4.3.3 in the XHCI specification about device slot
2417          * initialisation.
2418          */
2419         if (type != UE_ISOCHRONOUS)
2420                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2421
2422         switch (type) {
2423         case UE_CONTROL:
2424                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2425                 break;
2426         case UE_ISOCHRONOUS:
2427                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2428                 break;
2429         case UE_BULK:
2430                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2431                 break;
2432         default:
2433                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2434                 break;
2435         }
2436
2437         /* check for IN direction */
2438         if (epno & 1)
2439                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2440
2441         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2442
2443         ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2444
2445         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2446
2447         switch (edesc->bmAttributes & UE_XFERTYPE) {
2448         case UE_INTERRUPT:
2449         case UE_ISOCHRONOUS:
2450                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2451                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2452                     max_frame_size));
2453                 break;
2454         case UE_CONTROL:
2455                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2456                 break;
2457         default:
2458                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2459                 break;
2460         }
2461
2462         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2463
2464 #ifdef USB_DEBUG
2465         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2466 #endif
2467         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2468
2469         return (0);             /* success */
2470 }
2471
2472 static usb_error_t
2473 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2474 {
2475         struct xhci_endpoint_ext *pepext;
2476         struct usb_endpoint_ss_comp_descriptor *ecomp;
2477
2478         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2479             xfer->endpoint->edesc);
2480
2481         ecomp = xfer->endpoint->ecomp;
2482
2483         pepext->trb[0].dwTrb3 = 0;      /* halt any transfers */
2484         usb_pc_cpu_flush(pepext->page_cache);
2485
2486         return (xhci_configure_endpoint(xfer->xroot->udev,
2487             xfer->endpoint->edesc, pepext,
2488             xfer->interval, xfer->max_packet_count,
2489             (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1,
2490             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2491             xfer->max_frame_size));
2492 }
2493
2494 static usb_error_t
2495 xhci_configure_device(struct usb_device *udev)
2496 {
2497         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2498         struct usb_page_search buf_inp;
2499         struct usb_page_cache *pcinp;
2500         struct xhci_input_dev_ctx *pinp;
2501         struct usb_device *hubdev;
2502         uint32_t temp;
2503         uint32_t route;
2504         uint32_t rh_port;
2505         uint8_t is_hub;
2506         uint8_t index;
2507         uint8_t depth;
2508
2509         index = udev->controller_slot_id;
2510
2511         DPRINTF("index=%u\n", index);
2512
2513         pcinp = &sc->sc_hw.devs[index].input_pc;
2514
2515         usbd_get_page(pcinp, 0, &buf_inp);
2516
2517         pinp = buf_inp.buffer;
2518
2519         rh_port = 0;
2520         route = 0;
2521
2522         /* figure out route string and root HUB port number */
2523
2524         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2525
2526                 if (hubdev->parent_hub == NULL)
2527                         break;
2528
2529                 depth = hubdev->parent_hub->depth;
2530
2531                 /*
2532                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2533                  * more than 15 ports
2534                  */
2535
2536                 rh_port = hubdev->port_no;
2537
2538                 if (depth == 0)
2539                         break;
2540
2541                 if (rh_port > 15)
2542                         rh_port = 15;
2543
2544                 if (depth < 6)
2545                         route |= rh_port << (4 * (depth - 1));
2546         }
2547
2548         DPRINTF("Route=0x%08x\n", route);
2549
2550         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2551             XHCI_SCTX_0_CTX_NUM_SET(
2552             sc->sc_hw.devs[index].context_num + 1);
2553
2554         switch (udev->speed) {
2555         case USB_SPEED_LOW:
2556                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2557                 if (udev->parent_hs_hub != NULL &&
2558                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2559                     UDPROTO_HSHUBMTT) {
2560                         DPRINTF("Device inherits MTT\n");
2561                         temp |= XHCI_SCTX_0_MTT_SET(1);
2562                 }
2563                 break;
2564         case USB_SPEED_HIGH:
2565                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2566                 if (sc->sc_hw.devs[index].nports != 0 &&
2567                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2568                         DPRINTF("HUB supports MTT\n");
2569                         temp |= XHCI_SCTX_0_MTT_SET(1);
2570                 }
2571                 break;
2572         case USB_SPEED_FULL:
2573                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2574                 if (udev->parent_hs_hub != NULL &&
2575                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2576                     UDPROTO_HSHUBMTT) {
2577                         DPRINTF("Device inherits MTT\n");
2578                         temp |= XHCI_SCTX_0_MTT_SET(1);
2579                 }
2580                 break;
2581         default:
2582                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2583                 break;
2584         }
2585
2586         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2587             (udev->speed == USB_SPEED_SUPER ||
2588             udev->speed == USB_SPEED_HIGH);
2589
2590         if (is_hub)
2591                 temp |= XHCI_SCTX_0_HUB_SET(1);
2592
2593         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2594
2595         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2596
2597         if (is_hub) {
2598                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2599                     sc->sc_hw.devs[index].nports);
2600         }
2601
2602         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2603
2604         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2605
2606         if (is_hub) {
2607                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2608                     sc->sc_hw.devs[index].tt);
2609         }
2610
2611         hubdev = udev->parent_hs_hub;
2612
2613         /* check if we should activate the transaction translator */
2614         switch (udev->speed) {
2615         case USB_SPEED_FULL:
2616         case USB_SPEED_LOW:
2617                 if (hubdev != NULL) {
2618                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2619                             hubdev->controller_slot_id);
2620                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2621                             udev->hs_port_no);
2622                 }
2623                 break;
2624         default:
2625                 break;
2626         }
2627
2628         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2629
2630         /*
2631          * These fields should be initialized to zero, according to
2632          * XHCI section 6.2.2 - slot context:
2633          */
2634         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2635             XHCI_SCTX_3_SLOT_STATE_SET(0);
2636
2637         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2638
2639 #ifdef USB_DEBUG
2640         xhci_dump_device(sc, &pinp->ctx_slot);
2641 #endif
2642         usb_pc_cpu_flush(pcinp);
2643
2644         return (0);             /* success */
2645 }
2646
2647 static usb_error_t
2648 xhci_alloc_device_ext(struct usb_device *udev)
2649 {
2650         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2651         struct usb_page_search buf_dev;
2652         struct usb_page_search buf_ep;
2653         struct xhci_trb *trb;
2654         struct usb_page_cache *pc;
2655         struct usb_page *pg;
2656         uint64_t addr;
2657         uint8_t index;
2658         uint8_t i;
2659
2660         index = udev->controller_slot_id;
2661
2662         pc = &sc->sc_hw.devs[index].device_pc;
2663         pg = &sc->sc_hw.devs[index].device_pg;
2664
2665         /* need to initialize the page cache */
2666         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2667
2668         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2669             (2 * sizeof(struct xhci_dev_ctx)) :
2670             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2671                 goto error;
2672
2673         usbd_get_page(pc, 0, &buf_dev);
2674
2675         pc = &sc->sc_hw.devs[index].input_pc;
2676         pg = &sc->sc_hw.devs[index].input_pg;
2677
2678         /* need to initialize the page cache */
2679         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2680
2681         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2682             (2 * sizeof(struct xhci_input_dev_ctx)) :
2683             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2684                 goto error;
2685         }
2686
2687         pc = &sc->sc_hw.devs[index].endpoint_pc;
2688         pg = &sc->sc_hw.devs[index].endpoint_pg;
2689
2690         /* need to initialize the page cache */
2691         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2692
2693         if (usb_pc_alloc_mem(pc, pg,
2694             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2695                 goto error;
2696         }
2697
2698         /* initialise all endpoint LINK TRBs */
2699
2700         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2701
2702                 /* lookup endpoint TRB ring */
2703                 usbd_get_page(pc, (uintptr_t)&
2704                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2705
2706                 /* get TRB pointer */
2707                 trb = buf_ep.buffer;
2708                 trb += XHCI_MAX_TRANSFERS - 1;
2709
2710                 /* get TRB start address */
2711                 addr = buf_ep.physaddr;
2712
2713                 /* create LINK TRB */
2714                 trb->qwTrb0 = htole64(addr);
2715                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2716                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2717                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2718         }
2719
2720         usb_pc_cpu_flush(pc);
2721
2722         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2723
2724         return (0);
2725
2726 error:
2727         xhci_free_device_ext(udev);
2728
2729         return (USB_ERR_NOMEM);
2730 }
2731
2732 static void
2733 xhci_free_device_ext(struct usb_device *udev)
2734 {
2735         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2736         uint8_t index;
2737
2738         index = udev->controller_slot_id;
2739         xhci_set_slot_pointer(sc, index, 0);
2740
2741         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2742         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2743         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2744 }
2745
2746 static struct xhci_endpoint_ext *
2747 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2748 {
2749         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2750         struct xhci_endpoint_ext *pepext;
2751         struct usb_page_cache *pc;
2752         struct usb_page_search buf_ep;
2753         uint8_t epno;
2754         uint8_t index;
2755
2756         epno = edesc->bEndpointAddress;
2757         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2758                 epno |= UE_DIR_IN;
2759
2760         epno = XHCI_EPNO2EPID(epno);
2761
2762         index = udev->controller_slot_id;
2763
2764         pc = &sc->sc_hw.devs[index].endpoint_pc;
2765
2766         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep);
2767
2768         pepext = &sc->sc_hw.devs[index].endp[epno];
2769         pepext->page_cache = pc;
2770         pepext->trb = buf_ep.buffer;
2771         pepext->physaddr = buf_ep.physaddr;
2772
2773         return (pepext);
2774 }
2775
2776 static void
2777 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2778 {
2779         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2780         uint8_t epno;
2781         uint8_t index;
2782
2783         epno = xfer->endpointno;
2784         if (xfer->flags_int.control_xfr)
2785                 epno |= UE_DIR_IN;
2786
2787         epno = XHCI_EPNO2EPID(epno);
2788         index = xfer->xroot->udev->controller_slot_id;
2789
2790         if (xfer->xroot->udev->flags.self_suspended == 0) {
2791                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2792                     epno | XHCI_DB_SID_SET(/*xfer->stream_id*/ 0));
2793         }
2794 }
2795
2796 static void
2797 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2798 {
2799         struct xhci_endpoint_ext *pepext;
2800
2801         if (xfer->flags_int.bandwidth_reclaimed) {
2802                 xfer->flags_int.bandwidth_reclaimed = 0;
2803
2804                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2805                     xfer->endpoint->edesc);
2806
2807                 pepext->trb_used--;
2808
2809                 pepext->xfer[xfer->qh_pos] = NULL;
2810
2811                 if (error && pepext->trb_running != 0) {
2812                         pepext->trb_halted = 1;
2813                         pepext->trb_running = 0;
2814                 }
2815         }
2816 }
2817
2818 static usb_error_t
2819 xhci_transfer_insert(struct usb_xfer *xfer)
2820 {
2821         struct xhci_td *td_first;
2822         struct xhci_td *td_last;
2823         struct xhci_trb *trb_link;
2824         struct xhci_endpoint_ext *pepext;
2825         uint64_t addr;
2826         uint8_t i;
2827         uint8_t inext;
2828         uint8_t trb_limit;
2829
2830         DPRINTFN(8, "\n");
2831
2832         /* check if already inserted */
2833         if (xfer->flags_int.bandwidth_reclaimed) {
2834                 DPRINTFN(8, "Already in schedule\n");
2835                 return (0);
2836         }
2837
2838         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2839             xfer->endpoint->edesc);
2840
2841         td_first = xfer->td_transfer_first;
2842         td_last = xfer->td_transfer_last;
2843         addr = pepext->physaddr;
2844
2845         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2846         case UE_CONTROL:
2847         case UE_INTERRUPT:
2848                 /* single buffered */
2849                 trb_limit = 1;
2850                 break;
2851         default:
2852                 /* multi buffered */
2853                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2854                 break;
2855         }
2856
2857         if (pepext->trb_used >= trb_limit) {
2858                 DPRINTFN(8, "Too many TDs queued.\n");
2859                 return (USB_ERR_NOMEM);
2860         }
2861
2862         /* check if bMaxPacketSize changed */
2863         if (xfer->flags_int.control_xfr != 0 &&
2864             pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2865
2866                 DPRINTFN(8, "Reconfigure control endpoint\n");
2867
2868                 /* force driver to reconfigure endpoint */
2869                 pepext->trb_halted = 1;
2870                 pepext->trb_running = 0;
2871         }
2872
2873         /* check for stopped condition, after putting transfer on interrupt queue */
2874         if (pepext->trb_running == 0) {
2875                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2876
2877                 DPRINTFN(8, "Not running\n");
2878
2879                 /* start configuration */
2880                 (void)usb_proc_msignal(&sc->sc_config_proc,
2881                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2882                 return (0);
2883         }
2884
2885         pepext->trb_used++;
2886
2887         /* get current TRB index */
2888         i = pepext->trb_index;
2889
2890         /* get next TRB index */
2891         inext = (i + 1);
2892
2893         /* the last entry of the ring is a hardcoded link TRB */
2894         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2895                 inext = 0;
2896
2897         /* compute terminating return address */
2898         addr += inext * sizeof(struct xhci_trb);
2899
2900         /* compute link TRB pointer */
2901         trb_link = td_last->td_trb + td_last->ntrb;
2902
2903         /* update next pointer of last link TRB */
2904         trb_link->qwTrb0 = htole64(addr);
2905         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2906         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2907             XHCI_TRB_3_CYCLE_BIT |
2908             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2909
2910 #ifdef USB_DEBUG
2911         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2912 #endif
2913         usb_pc_cpu_flush(td_last->page_cache);
2914
2915         /* write ahead chain end marker */
2916
2917         pepext->trb[inext].qwTrb0 = 0;
2918         pepext->trb[inext].dwTrb2 = 0;
2919         pepext->trb[inext].dwTrb3 = 0;
2920
2921         /* update next pointer of link TRB */
2922
2923         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2924         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2925
2926 #ifdef USB_DEBUG
2927         xhci_dump_trb(&pepext->trb[i]);
2928 #endif
2929         usb_pc_cpu_flush(pepext->page_cache);
2930
2931         /* toggle cycle bit which activates the transfer chain */
2932
2933         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2934             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2935
2936         usb_pc_cpu_flush(pepext->page_cache);
2937
2938         DPRINTF("qh_pos = %u\n", i);
2939
2940         pepext->xfer[i] = xfer;
2941
2942         xfer->qh_pos = i;
2943
2944         xfer->flags_int.bandwidth_reclaimed = 1;
2945
2946         pepext->trb_index = inext;
2947
2948         xhci_endpoint_doorbell(xfer);
2949
2950         return (0);
2951 }
2952
2953 static void
2954 xhci_root_intr(struct xhci_softc *sc)
2955 {
2956         uint16_t i;
2957
2958         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2959
2960         /* clear any old interrupt data */
2961         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2962
2963         for (i = 1; i <= sc->sc_noport; i++) {
2964                 /* pick out CHANGE bits from the status register */
2965                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2966                     XHCI_PS_CSC | XHCI_PS_PEC |
2967                     XHCI_PS_OCC | XHCI_PS_WRC |
2968                     XHCI_PS_PRC | XHCI_PS_PLC |
2969                     XHCI_PS_CEC)) {
2970                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2971                         DPRINTF("port %d changed\n", i);
2972                 }
2973         }
2974         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2975             sizeof(sc->sc_hub_idata));
2976 }
2977
2978 /*------------------------------------------------------------------------*
2979  *      xhci_device_done - XHCI done handler
2980  *
2981  * NOTE: This function can be called two times in a row on
2982  * the same USB transfer. From close and from interrupt.
2983  *------------------------------------------------------------------------*/
2984 static void
2985 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2986 {
2987         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2988             xfer, xfer->endpoint, error);
2989
2990         /* remove transfer from HW queue */
2991         xhci_transfer_remove(xfer, error);
2992
2993         /* dequeue transfer and start next transfer */
2994         usbd_transfer_done(xfer, error);
2995 }
2996
2997 /*------------------------------------------------------------------------*
2998  * XHCI data transfer support (generic type)
2999  *------------------------------------------------------------------------*/
3000 static void
3001 xhci_device_generic_open(struct usb_xfer *xfer)
3002 {
3003         if (xfer->flags_int.isochronous_xfr) {
3004                 switch (xfer->xroot->udev->speed) {
3005                 case USB_SPEED_FULL:
3006                         break;
3007                 default:
3008                         usb_hs_bandwidth_alloc(xfer);
3009                         break;
3010                 }
3011         }
3012 }
3013
3014 static void
3015 xhci_device_generic_close(struct usb_xfer *xfer)
3016 {
3017         DPRINTF("\n");
3018
3019         xhci_device_done(xfer, USB_ERR_CANCELLED);
3020
3021         if (xfer->flags_int.isochronous_xfr) {
3022                 switch (xfer->xroot->udev->speed) {
3023                 case USB_SPEED_FULL:
3024                         break;
3025                 default:
3026                         usb_hs_bandwidth_free(xfer);
3027                         break;
3028                 }
3029         }
3030 }
3031
3032 static void
3033 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3034     struct usb_xfer *enter_xfer)
3035 {
3036         struct usb_xfer *xfer;
3037
3038         /* check if there is a current transfer */
3039         xfer = ep->endpoint_q.curr;
3040         if (xfer == NULL)
3041                 return;
3042
3043         /*
3044          * Check if the current transfer is started and then pickup
3045          * the next one, if any. Else wait for next start event due to
3046          * block on failure feature.
3047          */
3048         if (!xfer->flags_int.bandwidth_reclaimed)
3049                 return;
3050
3051         xfer = TAILQ_FIRST(&ep->endpoint_q.head);
3052         if (xfer == NULL) {
3053                 /*
3054                  * In case of enter we have to consider that the
3055                  * transfer is queued by the USB core after the enter
3056                  * method is called.
3057                  */
3058                 xfer = enter_xfer;
3059
3060                 if (xfer == NULL)
3061                         return;
3062         }
3063
3064         /* try to multi buffer */
3065         xhci_transfer_insert(xfer);
3066 }
3067
3068 static void
3069 xhci_device_generic_enter(struct usb_xfer *xfer)
3070 {
3071         DPRINTF("\n");
3072
3073         /* set up TD's and QH */
3074         xhci_setup_generic_chain(xfer);
3075
3076         xhci_device_generic_multi_enter(xfer->endpoint, xfer);
3077 }
3078
3079 static void
3080 xhci_device_generic_start(struct usb_xfer *xfer)
3081 {
3082         DPRINTF("\n");
3083
3084         /* try to insert xfer on HW queue */
3085         xhci_transfer_insert(xfer);
3086
3087         /* try to multi buffer */
3088         xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3089
3090         /* add transfer last on interrupt queue */
3091         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3092
3093         /* start timeout, if any */
3094         if (xfer->timeout != 0)
3095                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3096 }
3097
3098 struct usb_pipe_methods xhci_device_generic_methods =
3099 {
3100         .open = xhci_device_generic_open,
3101         .close = xhci_device_generic_close,
3102         .enter = xhci_device_generic_enter,
3103         .start = xhci_device_generic_start,
3104 };
3105
3106 /*------------------------------------------------------------------------*
3107  * xhci root HUB support
3108  *------------------------------------------------------------------------*
3109  * Simulate a hardware HUB by handling all the necessary requests.
3110  *------------------------------------------------------------------------*/
3111
3112 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3113
3114 static const
3115 struct usb_device_descriptor xhci_devd =
3116 {
3117         .bLength = sizeof(xhci_devd),
3118         .bDescriptorType = UDESC_DEVICE,        /* type */
3119         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3120         .bDeviceClass = UDCLASS_HUB,            /* class */
3121         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3122         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3123         .bMaxPacketSize = 9,                    /* max packet size */
3124         HSETW(.idVendor, 0x0000),               /* vendor */
3125         HSETW(.idProduct, 0x0000),              /* product */
3126         HSETW(.bcdDevice, 0x0100),              /* device version */
3127         .iManufacturer = 1,
3128         .iProduct = 2,
3129         .iSerialNumber = 0,
3130         .bNumConfigurations = 1,                /* # of configurations */
3131 };
3132
3133 static const
3134 struct xhci_bos_desc xhci_bosd = {
3135         .bosd = {
3136                 .bLength = sizeof(xhci_bosd.bosd),
3137                 .bDescriptorType = UDESC_BOS,
3138                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3139                 .bNumDeviceCaps = 3,
3140         },
3141         .usb2extd = {
3142                 .bLength = sizeof(xhci_bosd.usb2extd),
3143                 .bDescriptorType = 1,
3144                 .bDevCapabilityType = 2,
3145                 .bmAttributes[0] = 2,
3146         },
3147         .usbdcd = {
3148                 .bLength = sizeof(xhci_bosd.usbdcd),
3149                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3150                 .bDevCapabilityType = 3,
3151                 .bmAttributes = 0, /* XXX */
3152                 HSETW(.wSpeedsSupported, 0x000C),
3153                 .bFunctionalitySupport = 8,
3154                 .bU1DevExitLat = 255,   /* dummy - not used */
3155                 .wU2DevExitLat = { 0x00, 0x08 },
3156         },
3157         .cidd = {
3158                 .bLength = sizeof(xhci_bosd.cidd),
3159                 .bDescriptorType = 1,
3160                 .bDevCapabilityType = 4,
3161                 .bReserved = 0,
3162                 .bContainerID = 0, /* XXX */
3163         },
3164 };
3165
3166 static const
3167 struct xhci_config_desc xhci_confd = {
3168         .confd = {
3169                 .bLength = sizeof(xhci_confd.confd),
3170                 .bDescriptorType = UDESC_CONFIG,
3171                 .wTotalLength[0] = sizeof(xhci_confd),
3172                 .bNumInterface = 1,
3173                 .bConfigurationValue = 1,
3174                 .iConfiguration = 0,
3175                 .bmAttributes = UC_SELF_POWERED,
3176                 .bMaxPower = 0          /* max power */
3177         },
3178         .ifcd = {
3179                 .bLength = sizeof(xhci_confd.ifcd),
3180                 .bDescriptorType = UDESC_INTERFACE,
3181                 .bNumEndpoints = 1,
3182                 .bInterfaceClass = UICLASS_HUB,
3183                 .bInterfaceSubClass = UISUBCLASS_HUB,
3184                 .bInterfaceProtocol = 0,
3185         },
3186         .endpd = {
3187                 .bLength = sizeof(xhci_confd.endpd),
3188                 .bDescriptorType = UDESC_ENDPOINT,
3189                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3190                 .bmAttributes = UE_INTERRUPT,
3191                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3192                 .bInterval = 255,
3193         },
3194         .endpcd = {
3195                 .bLength = sizeof(xhci_confd.endpcd),
3196                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3197                 .bMaxBurst = 0,
3198                 .bmAttributes = 0,
3199         },
3200 };
3201
3202 static const
3203 struct usb_hub_ss_descriptor xhci_hubd = {
3204         .bLength = sizeof(xhci_hubd),
3205         .bDescriptorType = UDESC_SS_HUB,
3206 };
3207
3208 static usb_error_t
3209 xhci_roothub_exec(struct usb_device *udev,
3210     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3211 {
3212         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3213         const char *str_ptr;
3214         const void *ptr;
3215         uint32_t port;
3216         uint32_t v;
3217         uint16_t len;
3218         uint16_t i;
3219         uint16_t value;
3220         uint16_t index;
3221         uint8_t j;
3222         usb_error_t err;
3223
3224         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3225
3226         /* buffer reset */
3227         ptr = (const void *)&sc->sc_hub_desc;
3228         len = 0;
3229         err = 0;
3230
3231         value = UGETW(req->wValue);
3232         index = UGETW(req->wIndex);
3233
3234         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3235             "wValue=0x%04x wIndex=0x%04x\n",
3236             req->bmRequestType, req->bRequest,
3237             UGETW(req->wLength), value, index);
3238
3239 #define C(x,y) ((x) | ((y) << 8))
3240         switch (C(req->bRequest, req->bmRequestType)) {
3241         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3242         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3243         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3244                 /*
3245                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3246                  * for the integrated root hub.
3247                  */
3248                 break;
3249         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3250                 len = 1;
3251                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3252                 break;
3253         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3254                 switch (value >> 8) {
3255                 case UDESC_DEVICE:
3256                         if ((value & 0xff) != 0) {
3257                                 err = USB_ERR_IOERROR;
3258                                 goto done;
3259                         }
3260                         len = sizeof(xhci_devd);
3261                         ptr = (const void *)&xhci_devd;
3262                         break;
3263
3264                 case UDESC_BOS:
3265                         if ((value & 0xff) != 0) {
3266                                 err = USB_ERR_IOERROR;
3267                                 goto done;
3268                         }
3269                         len = sizeof(xhci_bosd);
3270                         ptr = (const void *)&xhci_bosd;
3271                         break;
3272
3273                 case UDESC_CONFIG:
3274                         if ((value & 0xff) != 0) {
3275                                 err = USB_ERR_IOERROR;
3276                                 goto done;
3277                         }
3278                         len = sizeof(xhci_confd);
3279                         ptr = (const void *)&xhci_confd;
3280                         break;
3281
3282                 case UDESC_STRING:
3283                         switch (value & 0xff) {
3284                         case 0: /* Language table */
3285                                 str_ptr = "\001";
3286                                 break;
3287
3288                         case 1: /* Vendor */
3289                                 str_ptr = sc->sc_vendor;
3290                                 break;
3291
3292                         case 2: /* Product */
3293                                 str_ptr = "XHCI root HUB";
3294                                 break;
3295
3296                         default:
3297                                 str_ptr = "";
3298                                 break;
3299                         }
3300
3301                         len = usb_make_str_desc(
3302                             sc->sc_hub_desc.temp,
3303                             sizeof(sc->sc_hub_desc.temp),
3304                             str_ptr);
3305                         break;
3306
3307                 default:
3308                         err = USB_ERR_IOERROR;
3309                         goto done;
3310                 }
3311                 break;
3312         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3313                 len = 1;
3314                 sc->sc_hub_desc.temp[0] = 0;
3315                 break;
3316         case C(UR_GET_STATUS, UT_READ_DEVICE):
3317                 len = 2;
3318                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3319                 break;
3320         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3321         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3322                 len = 2;
3323                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3324                 break;
3325         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3326                 if (value >= XHCI_MAX_DEVICES) {
3327                         err = USB_ERR_IOERROR;
3328                         goto done;
3329                 }
3330                 break;
3331         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3332                 if (value != 0 && value != 1) {
3333                         err = USB_ERR_IOERROR;
3334                         goto done;
3335                 }
3336                 sc->sc_conf = value;
3337                 break;
3338         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3339                 break;
3340         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3341         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3342         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3343                 err = USB_ERR_IOERROR;
3344                 goto done;
3345         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3346                 break;
3347         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3348                 break;
3349                 /* Hub requests */
3350         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3351                 break;
3352         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3353                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3354
3355                 if ((index < 1) ||
3356                     (index > sc->sc_noport)) {
3357                         err = USB_ERR_IOERROR;
3358                         goto done;
3359                 }
3360                 port = XHCI_PORTSC(index);
3361
3362                 v = XREAD4(sc, oper, port);
3363                 i = XHCI_PS_PLS_GET(v);
3364                 v &= ~XHCI_PS_CLEAR;
3365
3366                 switch (value) {
3367                 case UHF_C_BH_PORT_RESET:
3368                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3369                         break;
3370                 case UHF_C_PORT_CONFIG_ERROR:
3371                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3372                         break;
3373                 case UHF_C_PORT_SUSPEND:
3374                 case UHF_C_PORT_LINK_STATE:
3375                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3376                         break;
3377                 case UHF_C_PORT_CONNECTION:
3378                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3379                         break;
3380                 case UHF_C_PORT_ENABLE:
3381                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3382                         break;
3383                 case UHF_C_PORT_OVER_CURRENT:
3384                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3385                         break;
3386                 case UHF_C_PORT_RESET:
3387                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3388                         break;
3389                 case UHF_PORT_ENABLE:
3390                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3391                         break;
3392                 case UHF_PORT_POWER:
3393                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3394                         break;
3395                 case UHF_PORT_INDICATOR:
3396                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3397                         break;
3398                 case UHF_PORT_SUSPEND:
3399
3400                         /* U3 -> U15 */
3401                         if (i == 3) {
3402                                 XWRITE4(sc, oper, port, v |
3403                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3404                         }
3405
3406                         /* wait 20ms for resume sequence to complete */
3407                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3408
3409                         /* U0 */
3410                         XWRITE4(sc, oper, port, v |
3411                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3412                         break;
3413                 default:
3414                         err = USB_ERR_IOERROR;
3415                         goto done;
3416                 }
3417                 break;
3418
3419         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3420                 if ((value & 0xff) != 0) {
3421                         err = USB_ERR_IOERROR;
3422                         goto done;
3423                 }
3424
3425                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3426
3427                 sc->sc_hub_desc.hubd = xhci_hubd;
3428
3429                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3430
3431                 if (XHCI_HCS0_PPC(v))
3432                         i = UHD_PWR_INDIVIDUAL;
3433                 else
3434                         i = UHD_PWR_GANGED;
3435
3436                 if (XHCI_HCS0_PIND(v))
3437                         i |= UHD_PORT_IND;
3438
3439                 i |= UHD_OC_INDIVIDUAL;
3440
3441                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3442
3443                 /* see XHCI section 5.4.9: */
3444                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3445
3446                 for (j = 1; j <= sc->sc_noport; j++) {
3447
3448                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3449                         if (v & XHCI_PS_DR) {
3450                                 sc->sc_hub_desc.hubd.
3451                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3452                         }
3453                 }
3454                 len = sc->sc_hub_desc.hubd.bLength;
3455                 break;
3456
3457         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3458                 len = 16;
3459                 memset(sc->sc_hub_desc.temp, 0, 16);
3460                 break;
3461
3462         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3463                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3464
3465                 if ((index < 1) ||
3466                     (index > sc->sc_noport)) {
3467                         err = USB_ERR_IOERROR;
3468                         goto done;
3469                 }
3470
3471                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3472
3473                 DPRINTFN(9, "port status=0x%08x\n", v);
3474
3475                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3476
3477                 switch (XHCI_PS_SPEED_GET(v)) {
3478                 case 3:
3479                         i |= UPS_HIGH_SPEED;
3480                         break;
3481                 case 2:
3482                         i |= UPS_LOW_SPEED;
3483                         break;
3484                 case 1:
3485                         /* FULL speed */
3486                         break;
3487                 default:
3488                         i |= UPS_OTHER_SPEED;
3489                         break;
3490                 }
3491
3492                 if (v & XHCI_PS_CCS)
3493                         i |= UPS_CURRENT_CONNECT_STATUS;
3494                 if (v & XHCI_PS_PED)
3495                         i |= UPS_PORT_ENABLED;
3496                 if (v & XHCI_PS_OCA)
3497                         i |= UPS_OVERCURRENT_INDICATOR;
3498                 if (v & XHCI_PS_PR)
3499                         i |= UPS_RESET;
3500 #if 0
3501                 if (v & XHCI_PS_PP)
3502                         /* XXX undefined */
3503 #endif
3504                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3505
3506                 i = 0;
3507                 if (v & XHCI_PS_CSC)
3508                         i |= UPS_C_CONNECT_STATUS;
3509                 if (v & XHCI_PS_PEC)
3510                         i |= UPS_C_PORT_ENABLED;
3511                 if (v & XHCI_PS_OCC)
3512                         i |= UPS_C_OVERCURRENT_INDICATOR;
3513                 if (v & XHCI_PS_WRC)
3514                         i |= UPS_C_BH_PORT_RESET;
3515                 if (v & XHCI_PS_PRC)
3516                         i |= UPS_C_PORT_RESET;
3517                 if (v & XHCI_PS_PLC)
3518                         i |= UPS_C_PORT_LINK_STATE;
3519                 if (v & XHCI_PS_CEC)
3520                         i |= UPS_C_PORT_CONFIG_ERROR;
3521
3522                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3523                 len = sizeof(sc->sc_hub_desc.ps);
3524                 break;
3525
3526         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3527                 err = USB_ERR_IOERROR;
3528                 goto done;
3529
3530         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3531                 break;
3532
3533         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3534
3535                 i = index >> 8;
3536                 index &= 0x00FF;
3537
3538                 if ((index < 1) ||
3539                     (index > sc->sc_noport)) {
3540                         err = USB_ERR_IOERROR;
3541                         goto done;
3542                 }
3543
3544                 port = XHCI_PORTSC(index);
3545                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3546
3547                 switch (value) {
3548                 case UHF_PORT_U1_TIMEOUT:
3549                         if (XHCI_PS_SPEED_GET(v) != 4) {
3550                                 err = USB_ERR_IOERROR;
3551                                 goto done;
3552                         }
3553                         port = XHCI_PORTPMSC(index);
3554                         v = XREAD4(sc, oper, port);
3555                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3556                         v |= XHCI_PM3_U1TO_SET(i);
3557                         XWRITE4(sc, oper, port, v);
3558                         break;
3559                 case UHF_PORT_U2_TIMEOUT:
3560                         if (XHCI_PS_SPEED_GET(v) != 4) {
3561                                 err = USB_ERR_IOERROR;
3562                                 goto done;
3563                         }
3564                         port = XHCI_PORTPMSC(index);
3565                         v = XREAD4(sc, oper, port);
3566                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3567                         v |= XHCI_PM3_U2TO_SET(i);
3568                         XWRITE4(sc, oper, port, v);
3569                         break;
3570                 case UHF_BH_PORT_RESET:
3571                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3572                         break;
3573                 case UHF_PORT_LINK_STATE:
3574                         XWRITE4(sc, oper, port, v |
3575                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3576                         /* 4ms settle time */
3577                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3578                         break;
3579                 case UHF_PORT_ENABLE:
3580                         DPRINTFN(3, "set port enable %d\n", index);
3581                         break;
3582                 case UHF_PORT_SUSPEND:
3583                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3584                         j = XHCI_PS_SPEED_GET(v);
3585                         if ((j < 1) || (j > 3)) {
3586                                 /* non-supported speed */
3587                                 err = USB_ERR_IOERROR;
3588                                 goto done;
3589                         }
3590                         XWRITE4(sc, oper, port, v |
3591                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3592                         break;
3593                 case UHF_PORT_RESET:
3594                         DPRINTFN(6, "reset port %d\n", index);
3595                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3596                         break;
3597                 case UHF_PORT_POWER:
3598                         DPRINTFN(3, "set port power %d\n", index);
3599                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3600                         break;
3601                 case UHF_PORT_TEST:
3602                         DPRINTFN(3, "set port test %d\n", index);
3603                         break;
3604                 case UHF_PORT_INDICATOR:
3605                         DPRINTFN(3, "set port indicator %d\n", index);
3606
3607                         v &= ~XHCI_PS_PIC_SET(3);
3608                         v |= XHCI_PS_PIC_SET(1);
3609
3610                         XWRITE4(sc, oper, port, v);
3611                         break;
3612                 default:
3613                         err = USB_ERR_IOERROR;
3614                         goto done;
3615                 }
3616                 break;
3617
3618         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3619         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3620         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3621         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3622                 break;
3623         default:
3624                 err = USB_ERR_IOERROR;
3625                 goto done;
3626         }
3627 done:
3628         *plength = len;
3629         *pptr = ptr;
3630         return (err);
3631 }
3632
3633 static void
3634 xhci_xfer_setup(struct usb_setup_params *parm)
3635 {
3636         struct usb_page_search page_info;
3637         struct usb_page_cache *pc;
3638         struct xhci_softc *sc;
3639         struct usb_xfer *xfer;
3640         void *last_obj;
3641         uint32_t ntd;
3642         uint32_t n;
3643
3644         sc = XHCI_BUS2SC(parm->udev->bus);
3645         xfer = parm->curr_xfer;
3646
3647         /*
3648          * The proof for the "ntd" formula is illustrated like this:
3649          *
3650          * +------------------------------------+
3651          * |                                    |
3652          * |         |remainder ->              |
3653          * |   +-----+---+                      |
3654          * |   | xxx | x | frm 0                |
3655          * |   +-----+---++                     |
3656          * |   | xxx | xx | frm 1               |
3657          * |   +-----+----+                     |
3658          * |            ...                     |
3659          * +------------------------------------+
3660          *
3661          * "xxx" means a completely full USB transfer descriptor
3662          *
3663          * "x" and "xx" means a short USB packet
3664          *
3665          * For the remainder of an USB transfer modulo
3666          * "max_data_length" we need two USB transfer descriptors.
3667          * One to transfer the remaining data and one to finalise with
3668          * a zero length packet in case the "force_short_xfer" flag is
3669          * set. We only need two USB transfer descriptors in the case
3670          * where the transfer length of the first one is a factor of
3671          * "max_frame_size". The rest of the needed USB transfer
3672          * descriptors is given by the buffer size divided by the
3673          * maximum data payload.
3674          */
3675         parm->hc_max_packet_size = 0x400;
3676         parm->hc_max_packet_count = 16 * 3;
3677         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3678
3679         xfer->flags_int.bdma_enable = 1;
3680
3681         usbd_transfer_setup_sub(parm);
3682
3683         if (xfer->flags_int.isochronous_xfr) {
3684                 ntd = ((1 * xfer->nframes)
3685                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3686         } else if (xfer->flags_int.control_xfr) {
3687                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3688                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3689         } else {
3690                 ntd = ((2 * xfer->nframes)
3691                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3692         }
3693
3694 alloc_dma_set:
3695
3696         if (parm->err)
3697                 return;
3698
3699         /*
3700          * Allocate queue heads and transfer descriptors
3701          */
3702         last_obj = NULL;
3703
3704         if (usbd_transfer_setup_sub_malloc(
3705             parm, &pc, sizeof(struct xhci_td),
3706             XHCI_TD_ALIGN, ntd)) {
3707                 parm->err = USB_ERR_NOMEM;
3708                 return;
3709         }
3710         if (parm->buf) {
3711                 for (n = 0; n != ntd; n++) {
3712                         struct xhci_td *td;
3713
3714                         usbd_get_page(pc + n, 0, &page_info);
3715
3716                         td = page_info.buffer;
3717
3718                         /* init TD */
3719                         td->td_self = page_info.physaddr;
3720                         td->obj_next = last_obj;
3721                         td->page_cache = pc + n;
3722
3723                         last_obj = td;
3724
3725                         usb_pc_cpu_flush(pc + n);
3726                 }
3727         }
3728         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3729
3730         if (!xfer->flags_int.curr_dma_set) {
3731                 xfer->flags_int.curr_dma_set = 1;
3732                 goto alloc_dma_set;
3733         }
3734 }
3735
3736 static usb_error_t
3737 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3738 {
3739         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3740         struct usb_page_search buf_inp;
3741         struct usb_device *udev;
3742         struct xhci_endpoint_ext *pepext;
3743         struct usb_endpoint_descriptor *edesc;
3744         struct usb_page_cache *pcinp;
3745         usb_error_t err;
3746         uint8_t index;
3747         uint8_t epno;
3748
3749         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3750             xfer->endpoint->edesc);
3751
3752         udev = xfer->xroot->udev;
3753         index = udev->controller_slot_id;
3754
3755         pcinp = &sc->sc_hw.devs[index].input_pc;
3756
3757         usbd_get_page(pcinp, 0, &buf_inp);
3758
3759         edesc = xfer->endpoint->edesc;
3760
3761         epno = edesc->bEndpointAddress;
3762
3763         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3764                 epno |= UE_DIR_IN;
3765
3766         epno = XHCI_EPNO2EPID(epno);
3767
3768         if (epno == 0)
3769                 return (USB_ERR_NO_PIPE);               /* invalid */
3770
3771         XHCI_CMD_LOCK(sc);
3772
3773         /* configure endpoint */
3774
3775         err = xhci_configure_endpoint_by_xfer(xfer);
3776
3777         if (err != 0) {
3778                 XHCI_CMD_UNLOCK(sc);
3779                 return (err);
3780         }
3781
3782         /*
3783          * Get the endpoint into the stopped state according to the
3784          * endpoint context state diagram in the XHCI specification:
3785          */
3786
3787         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3788
3789         if (err != 0)
3790                 DPRINTF("Could not stop endpoint %u\n", epno);
3791
3792         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3793
3794         if (err != 0)
3795                 DPRINTF("Could not reset endpoint %u\n", epno);
3796
3797         err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr |
3798             XHCI_EPCTX_2_DCS_SET(1), 0, epno, index);
3799
3800         if (err != 0)
3801                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3802
3803         /*
3804          * Get the endpoint into the running state according to the
3805          * endpoint context state diagram in the XHCI specification:
3806          */
3807
3808         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3809
3810         if (epno > 1)
3811                 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3812         else
3813                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3814
3815         if (err != 0)
3816                 DPRINTF("Could not configure endpoint %u\n", epno);
3817
3818         XHCI_CMD_UNLOCK(sc);
3819
3820         return (0);
3821 }
3822
3823 static void
3824 xhci_xfer_unsetup(struct usb_xfer *xfer)
3825 {
3826         return;
3827 }
3828
3829 static void
3830 xhci_start_dma_delay(struct usb_xfer *xfer)
3831 {
3832         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3833
3834         /* put transfer on interrupt queue (again) */
3835         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3836
3837         (void)usb_proc_msignal(&sc->sc_config_proc,
3838             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3839 }
3840
3841 static void
3842 xhci_configure_msg(struct usb_proc_msg *pm)
3843 {
3844         struct xhci_softc *sc;
3845         struct xhci_endpoint_ext *pepext;
3846         struct usb_xfer *xfer;
3847
3848         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3849
3850 restart:
3851         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3852
3853                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3854                     xfer->endpoint->edesc);
3855
3856                 if ((pepext->trb_halted != 0) ||
3857                     (pepext->trb_running == 0)) {
3858
3859                         uint8_t i;
3860
3861                         /* clear halted and running */
3862                         pepext->trb_halted = 0;
3863                         pepext->trb_running = 0;
3864
3865                         /* nuke remaining buffered transfers */
3866
3867                         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
3868                                 /*
3869                                  * NOTE: We need to use the timeout
3870                                  * error code here else existing
3871                                  * isochronous clients can get
3872                                  * confused:
3873                                  */
3874                                 if (pepext->xfer[i] != NULL) {
3875                                         xhci_device_done(pepext->xfer[i],
3876                                             USB_ERR_TIMEOUT);
3877                                 }
3878                         }
3879
3880                         /*
3881                          * NOTE: The USB transfer cannot vanish in
3882                          * this state!
3883                          */
3884
3885                         USB_BUS_UNLOCK(&sc->sc_bus);
3886
3887                         xhci_configure_reset_endpoint(xfer);
3888
3889                         USB_BUS_LOCK(&sc->sc_bus);
3890
3891                         /* check if halted is still cleared */
3892                         if (pepext->trb_halted == 0) {
3893                                 pepext->trb_running = 1;
3894                                 pepext->trb_index = 0;
3895                         }
3896                         goto restart;
3897                 }
3898
3899                 if (xfer->flags_int.did_dma_delay) {
3900
3901                         /* remove transfer from interrupt queue (again) */
3902                         usbd_transfer_dequeue(xfer);
3903
3904                         /* we are finally done */
3905                         usb_dma_delay_done_cb(xfer);
3906
3907                         /* queue changed - restart */
3908                         goto restart;
3909                 }
3910         }
3911
3912         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3913
3914                 /* try to insert xfer on HW queue */
3915                 xhci_transfer_insert(xfer);
3916
3917                 /* try to multi buffer */
3918                 xhci_device_generic_multi_enter(xfer->endpoint, NULL);
3919         }
3920 }
3921
3922 static void
3923 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3924     struct usb_endpoint *ep)
3925 {
3926         struct xhci_endpoint_ext *pepext;
3927
3928         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3929             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3930
3931         if (udev->parent_hub == NULL) {
3932                 /* root HUB has special endpoint handling */
3933                 return;
3934         }
3935
3936         ep->methods = &xhci_device_generic_methods;
3937
3938         pepext = xhci_get_endpoint_ext(udev, edesc);
3939
3940         USB_BUS_LOCK(udev->bus);
3941         pepext->trb_halted = 1;
3942         pepext->trb_running = 0;
3943         USB_BUS_UNLOCK(udev->bus);
3944 }
3945
3946 static void
3947 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3948 {
3949
3950 }
3951
3952 static void
3953 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3954 {
3955         struct xhci_endpoint_ext *pepext;
3956
3957         DPRINTF("\n");
3958
3959         if (udev->flags.usb_mode != USB_MODE_HOST) {
3960                 /* not supported */
3961                 return;
3962         }
3963         if (udev->parent_hub == NULL) {
3964                 /* root HUB has special endpoint handling */
3965                 return;
3966         }
3967
3968         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3969
3970         USB_BUS_LOCK(udev->bus);
3971         pepext->trb_halted = 1;
3972         pepext->trb_running = 0;
3973         USB_BUS_UNLOCK(udev->bus);
3974 }
3975
3976 static usb_error_t
3977 xhci_device_init(struct usb_device *udev)
3978 {
3979         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3980         usb_error_t err;
3981         uint8_t temp;
3982
3983         /* no init for root HUB */
3984         if (udev->parent_hub == NULL)
3985                 return (0);
3986
3987         XHCI_CMD_LOCK(sc);
3988
3989         /* set invalid default */
3990
3991         udev->controller_slot_id = sc->sc_noslot + 1;
3992
3993         /* try to get a new slot ID from the XHCI */
3994
3995         err = xhci_cmd_enable_slot(sc, &temp);
3996
3997         if (err) {
3998                 XHCI_CMD_UNLOCK(sc);
3999                 return (err);
4000         }
4001
4002         if (temp > sc->sc_noslot) {
4003                 XHCI_CMD_UNLOCK(sc);
4004                 return (USB_ERR_BAD_ADDRESS);
4005         }
4006
4007         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4008                 DPRINTF("slot %u already allocated.\n", temp);
4009                 XHCI_CMD_UNLOCK(sc);
4010                 return (USB_ERR_BAD_ADDRESS);
4011         }
4012
4013         /* store slot ID for later reference */
4014
4015         udev->controller_slot_id = temp;
4016
4017         /* reset data structure */
4018
4019         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4020
4021         /* set mark slot allocated */
4022
4023         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4024
4025         err = xhci_alloc_device_ext(udev);
4026
4027         XHCI_CMD_UNLOCK(sc);
4028
4029         /* get device into default state */
4030
4031         if (err == 0)
4032                 err = xhci_set_address(udev, NULL, 0);
4033
4034         return (err);
4035 }
4036
4037 static void
4038 xhci_device_uninit(struct usb_device *udev)
4039 {
4040         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4041         uint8_t index;
4042
4043         /* no init for root HUB */
4044         if (udev->parent_hub == NULL)
4045                 return;
4046
4047         XHCI_CMD_LOCK(sc);
4048
4049         index = udev->controller_slot_id;
4050
4051         if (index <= sc->sc_noslot) {
4052                 xhci_cmd_disable_slot(sc, index);
4053                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4054
4055                 /* free device extension */
4056                 xhci_free_device_ext(udev);
4057         }
4058
4059         XHCI_CMD_UNLOCK(sc);
4060 }
4061
4062 static void
4063 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4064 {
4065         /*
4066          * Wait until the hardware has finished any possible use of
4067          * the transfer descriptor(s)
4068          */
4069         *pus = 2048;                    /* microseconds */
4070 }
4071
4072 static void
4073 xhci_device_resume(struct usb_device *udev)
4074 {
4075         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4076         uint8_t index;
4077         uint8_t n;
4078         uint8_t p;
4079
4080         DPRINTF("\n");
4081
4082         /* check for root HUB */
4083         if (udev->parent_hub == NULL)
4084                 return;
4085
4086         index = udev->controller_slot_id;
4087
4088         XHCI_CMD_LOCK(sc);
4089
4090         /* blindly resume all endpoints */
4091
4092         USB_BUS_LOCK(udev->bus);
4093
4094         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4095                 for (p = 0; p != 1 /*XHCI_MAX_STREAMS*/; p++) {
4096                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4097                             n | XHCI_DB_SID_SET(p));
4098                 }
4099         }
4100
4101         USB_BUS_UNLOCK(udev->bus);
4102
4103         XHCI_CMD_UNLOCK(sc);
4104 }
4105
4106 static void
4107 xhci_device_suspend(struct usb_device *udev)
4108 {
4109         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4110         uint8_t index;
4111         uint8_t n;
4112         usb_error_t err;
4113
4114         DPRINTF("\n");
4115
4116         /* check for root HUB */
4117         if (udev->parent_hub == NULL)
4118                 return;
4119
4120         index = udev->controller_slot_id;
4121
4122         XHCI_CMD_LOCK(sc);
4123
4124         /* blindly suspend all endpoints */
4125
4126         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4127                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4128                 if (err != 0) {
4129                         DPRINTF("Failed to suspend endpoint "
4130                             "%u on slot %u (ignored).\n", n, index);
4131                 }
4132         }
4133
4134         XHCI_CMD_UNLOCK(sc);
4135 }
4136
4137 static void
4138 xhci_set_hw_power(struct usb_bus *bus)
4139 {
4140         DPRINTF("\n");
4141 }
4142
4143 static void
4144 xhci_device_state_change(struct usb_device *udev)
4145 {
4146         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4147         struct usb_page_search buf_inp;
4148         usb_error_t err;
4149         uint8_t index;
4150
4151         /* check for root HUB */
4152         if (udev->parent_hub == NULL)
4153                 return;
4154
4155         index = udev->controller_slot_id;
4156
4157         DPRINTF("\n");
4158
4159         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4160                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4161                     &sc->sc_hw.devs[index].tt);
4162                 if (err != 0)
4163                         sc->sc_hw.devs[index].nports = 0;
4164         }
4165
4166         XHCI_CMD_LOCK(sc);
4167
4168         switch (usb_get_device_state(udev)) {
4169         case USB_STATE_POWERED:
4170                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4171                         break;
4172
4173                 /* set default state */
4174                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4175
4176                 /* reset number of contexts */
4177                 sc->sc_hw.devs[index].context_num = 0;
4178
4179                 err = xhci_cmd_reset_dev(sc, index);
4180
4181                 if (err != 0) {
4182                         DPRINTF("Device reset failed "
4183                             "for slot %u.\n", index);
4184                 }
4185                 break;
4186
4187         case USB_STATE_ADDRESSED:
4188                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4189                         break;
4190
4191                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4192
4193                 /* set configure mask to slot only */
4194                 xhci_configure_mask(udev, 1, 0);
4195
4196                 /* deconfigure all endpoints, except EP0 */
4197                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4198
4199                 if (err) {
4200                         DPRINTF("Failed to deconfigure "
4201                             "slot %u.\n", index);
4202                 }
4203                 break;
4204
4205         case USB_STATE_CONFIGURED:
4206                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4207                         break;
4208
4209                 /* set configured state */
4210                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4211
4212                 /* reset number of contexts */
4213                 sc->sc_hw.devs[index].context_num = 0;
4214
4215                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4216
4217                 xhci_configure_mask(udev, 3, 0);
4218
4219                 err = xhci_configure_device(udev);
4220                 if (err != 0) {
4221                         DPRINTF("Could not configure device "
4222                             "at slot %u.\n", index);
4223                 }
4224
4225                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4226                 if (err != 0) {
4227                         DPRINTF("Could not evaluate device "
4228                             "context at slot %u.\n", index);
4229                 }
4230                 break;
4231
4232         default:
4233                 break;
4234         }
4235         XHCI_CMD_UNLOCK(sc);
4236 }
4237
4238 struct usb_bus_methods xhci_bus_methods = {
4239         .endpoint_init = xhci_ep_init,
4240         .endpoint_uninit = xhci_ep_uninit,
4241         .xfer_setup = xhci_xfer_setup,
4242         .xfer_unsetup = xhci_xfer_unsetup,
4243         .get_dma_delay = xhci_get_dma_delay,
4244         .device_init = xhci_device_init,
4245         .device_uninit = xhci_device_uninit,
4246         .device_resume = xhci_device_resume,
4247         .device_suspend = xhci_device_suspend,
4248         .set_hw_power = xhci_set_hw_power,
4249         .roothub_exec = xhci_roothub_exec,
4250         .xfer_poll = xhci_do_poll,
4251         .start_dma_delay = xhci_start_dma_delay,
4252         .set_address = xhci_set_address,
4253         .clear_stall = xhci_ep_clear_stall,
4254         .device_state_change = xhci_device_state_change,
4255         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4256 };