2 * Copyright(c) 2002-2011 Exar Corp.
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29 * POSSIBILITY OF SUCH DAMAGE.
33 #include <dev/vxge/vxgehal/vxgehal.h>
36 * vxge_hal_driver_config_check - Check driver configuration.
37 * @config: Driver configuration information
39 * Check the driver configuration
41 * Returns: VXGE_HAL_OK - success,
42 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
46 vxge_hal_driver_config_check(vxge_hal_driver_config_t *config)
48 if (config->level > VXGE_TRACE)
49 return (VXGE_HAL_BADCFG_LOG_LEVEL);
54 * __hal_device_wire_port_config_check - Check wire port configuration.
55 * @port_config: Port configuration information
57 * Check wire port configuration
59 * Returns: VXGE_HAL_OK - success,
60 * otherwise one of the vxge_hal_status_e enumerated error codes.
64 __hal_device_wire_port_config_check(vxge_hal_wire_port_config_t *port_config)
66 if (port_config->port_id > VXGE_HAL_WIRE_PORT_MAX_PORTS)
67 return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_ID);
69 if ((port_config->media > VXGE_HAL_WIRE_PORT_MAX_MEDIA) &&
70 (port_config->media != VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT))
71 return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_MEDIA);
73 if (((port_config->mtu < VXGE_HAL_WIRE_PORT_MIN_INITIAL_MTU) ||
74 (port_config->mtu > VXGE_HAL_WIRE_PORT_MAX_INITIAL_MTU)) &&
75 (port_config->mtu != VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU))
76 return (VXGE_HAL_BADCFG_WIRE_PORT_MAX_INITIAL_MTU);
78 if ((port_config->autoneg_mode >
79 VXGE_HAL_WIRE_PORT_AUTONEG_MODE_RESERVED) &&
80 (port_config->autoneg_mode !=
81 VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT))
82 return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_MODE);
84 if ((port_config->autoneg_rate >
85 VXGE_HAL_WIRE_PORT_AUTONEG_RATE_10G) &&
86 (port_config->autoneg_rate !=
87 VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT))
88 return (VXGE_HAL_BADCFG_WIRE_PORT_AUTONEG_RATE);
90 if ((port_config->fixed_use_fsm !=
91 VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_PROCESSOR) &&
92 (port_config->fixed_use_fsm !=
93 VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_HW) &&
94 (port_config->fixed_use_fsm !=
95 VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT))
96 return (VXGE_HAL_BADCFG_WIRE_PORT_FIXED_USE_FSM);
98 if ((port_config->antp_use_fsm !=
99 VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_PROCESSOR) &&
100 (port_config->antp_use_fsm !=
101 VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_HW) &&
102 (port_config->antp_use_fsm !=
103 VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT))
104 return (VXGE_HAL_BADCFG_WIRE_PORT_ANTP_USE_FSM);
106 if ((port_config->anbe_use_fsm !=
107 VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_PROCESSOR) &&
108 (port_config->anbe_use_fsm !=
109 VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_HW) &&
110 (port_config->anbe_use_fsm !=
111 VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT))
112 return (VXGE_HAL_BADCFG_WIRE_PORT_ANBE_USE_FSM);
114 if ((port_config->link_stability_period >
115 VXGE_HAL_WIRE_PORT_MAX_LINK_STABILITY_PERIOD) &&
116 (port_config->link_stability_period !=
117 VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD))
118 return (VXGE_HAL_BADCFG_WIRE_PORT_LINK_STABILITY_PERIOD);
120 if ((port_config->port_stability_period >
121 VXGE_HAL_WIRE_PORT_MAX_PORT_STABILITY_PERIOD) &&
122 (port_config->port_stability_period !=
123 VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD))
124 return (VXGE_HAL_BADCFG_WIRE_PORT_PORT_STABILITY_PERIOD);
126 if ((port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_ENABLE) &&
127 (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DISABLE) &&
128 (port_config->tmac_en != VXGE_HAL_WIRE_PORT_TMAC_DEFAULT))
129 return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_EN);
131 if ((port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_ENABLE) &&
132 (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DISABLE) &&
133 (port_config->rmac_en != VXGE_HAL_WIRE_PORT_RMAC_DEFAULT))
134 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_EN);
136 if ((port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_NO_PAD) &&
137 (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_64B_PAD) &&
138 (port_config->tmac_pad != VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT))
139 return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD);
141 if ((port_config->tmac_pad_byte >
142 VXGE_HAL_WIRE_PORT_MAX_TMAC_PAD_BYTE) &&
143 (port_config->tmac_pad_byte !=
144 VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE))
145 return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_PAD_BYTE);
147 if ((port_config->tmac_util_period >
148 VXGE_HAL_WIRE_PORT_MAX_TMAC_UTIL_PERIOD) &&
149 (port_config->tmac_util_period !=
150 VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD))
151 return (VXGE_HAL_BADCFG_WIRE_PORT_TMAC_UTIL_PERIOD);
153 if ((port_config->rmac_strip_fcs !=
154 VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS) &&
155 (port_config->rmac_strip_fcs !=
156 VXGE_HAL_WIRE_PORT_RMAC_SEND_FCS_TO_HOST) &&
157 (port_config->rmac_strip_fcs !=
158 VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT))
159 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_STRIP_FCS);
161 if ((port_config->rmac_prom_en !=
162 VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_ENABLE) &&
163 (port_config->rmac_prom_en !=
164 VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DISABLE) &&
165 (port_config->rmac_prom_en !=
166 VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT))
167 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PROM_EN);
169 if ((port_config->rmac_discard_pfrm !=
170 VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM) &&
171 (port_config->rmac_discard_pfrm !=
172 VXGE_HAL_WIRE_PORT_RMAC_SEND_PFRM_TO_HOST) &&
173 (port_config->rmac_discard_pfrm !=
174 VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT))
175 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_DISCARD_PFRM);
177 if ((port_config->rmac_util_period >
178 VXGE_HAL_WIRE_PORT_MAX_RMAC_UTIL_PERIOD) &&
179 (port_config->rmac_util_period !=
180 VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD))
181 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_UTIL_PERIOD);
183 if ((port_config->rmac_pause_gen_en !=
184 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_ENABLE) &&
185 (port_config->rmac_pause_gen_en !=
186 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DISABLE) &&
187 (port_config->rmac_pause_gen_en !=
188 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT))
189 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_GEN_EN);
191 if ((port_config->rmac_pause_rcv_en !=
192 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_ENABLE) &&
193 (port_config->rmac_pause_rcv_en !=
194 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DISABLE) &&
195 (port_config->rmac_pause_rcv_en !=
196 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT))
197 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_RCV_EN);
199 if (((port_config->rmac_pause_time <
200 VXGE_HAL_WIRE_PORT_MIN_RMAC_HIGH_PTIME) ||
201 (port_config->rmac_pause_time >
202 VXGE_HAL_WIRE_PORT_MAX_RMAC_HIGH_PTIME)) &&
203 (port_config->rmac_pause_time !=
204 VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME))
205 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_HIGH_PTIME);
207 if ((port_config->limiter_en !=
208 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_ENABLE) &&
209 (port_config->limiter_en !=
210 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DISABLE) &&
211 (port_config->limiter_en !=
212 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT))
213 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_PAUSE_LIMITER_EN);
215 if ((port_config->max_limit > VXGE_HAL_WIRE_PORT_MAX_RMAC_MAX_LIMIT) &&
216 (port_config->max_limit != VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT))
217 return (VXGE_HAL_BADCFG_WIRE_PORT_RMAC_MAX_LIMIT);
219 return (VXGE_HAL_OK);
224 * __hal_device_switch_port_config_check - Check switch port configuration.
225 * @port_config: Port configuration information
227 * Check switch port configuration
229 * Returns: VXGE_HAL_OK - success,
230 * otherwise one of the vxge_hal_status_e enumerated error codes.
234 __hal_device_switch_port_config_check(
235 vxge_hal_switch_port_config_t *port_config)
237 if (((port_config->mtu < VXGE_HAL_SWITCH_PORT_MIN_INITIAL_MTU) ||
238 (port_config->mtu > VXGE_HAL_SWITCH_PORT_MAX_INITIAL_MTU)) &&
239 (port_config->mtu != VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU))
240 return (VXGE_HAL_BADCFG_SWITCH_PORT_MAX_INITIAL_MTU);
242 if ((port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_ENABLE) &&
243 (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DISABLE) &&
244 (port_config->tmac_en != VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT))
245 return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_EN);
247 if ((port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_ENABLE) &&
248 (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DISABLE) &&
249 (port_config->rmac_en != VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT))
250 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_EN);
252 if ((port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_NO_PAD) &&
253 (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_64B_PAD) &&
254 (port_config->tmac_pad != VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT))
255 return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD);
257 if ((port_config->tmac_pad_byte >
258 VXGE_HAL_SWITCH_PORT_MAX_TMAC_PAD_BYTE) &&
259 (port_config->tmac_pad_byte !=
260 VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE))
261 return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_PAD_BYTE);
263 if ((port_config->tmac_util_period >
264 VXGE_HAL_SWITCH_PORT_MAX_TMAC_UTIL_PERIOD) &&
265 (port_config->tmac_util_period !=
266 VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD))
267 return (VXGE_HAL_BADCFG_SWITCH_PORT_TMAC_UTIL_PERIOD);
269 if ((port_config->rmac_strip_fcs !=
270 VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS) &&
271 (port_config->rmac_strip_fcs !=
272 VXGE_HAL_SWITCH_PORT_RMAC_SEND_FCS_TO_HOST) &&
273 (port_config->rmac_strip_fcs !=
274 VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT))
275 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_STRIP_FCS);
277 if ((port_config->rmac_prom_en !=
278 VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_ENABLE) &&
279 (port_config->rmac_prom_en !=
280 VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DISABLE) &&
281 (port_config->rmac_prom_en !=
282 VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT))
283 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PROM_EN);
285 if ((port_config->rmac_discard_pfrm !=
286 VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM) &&
287 (port_config->rmac_discard_pfrm !=
288 VXGE_HAL_SWITCH_PORT_RMAC_SEND_PFRM_TO_HOST) &&
289 (port_config->rmac_discard_pfrm !=
290 VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT))
291 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_DISCARD_PFRM);
293 if ((port_config->rmac_util_period >
294 VXGE_HAL_SWITCH_PORT_MAX_RMAC_UTIL_PERIOD) &&
295 (port_config->rmac_util_period !=
296 VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD))
297 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_UTIL_PERIOD);
299 if ((port_config->rmac_pause_gen_en !=
300 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_ENABLE) &&
301 (port_config->rmac_pause_gen_en !=
302 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DISABLE) &&
303 (port_config->rmac_pause_gen_en !=
304 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT))
305 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_GEN_EN);
307 if ((port_config->rmac_pause_rcv_en !=
308 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_ENABLE) &&
309 (port_config->rmac_pause_rcv_en !=
310 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DISABLE) &&
311 (port_config->rmac_pause_rcv_en !=
312 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT))
313 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_RCV_EN);
315 if (((port_config->rmac_pause_time <
316 VXGE_HAL_SWITCH_PORT_MIN_RMAC_HIGH_PTIME) ||
317 (port_config->rmac_pause_time >
318 VXGE_HAL_SWITCH_PORT_MAX_RMAC_HIGH_PTIME)) &&
319 (port_config->rmac_pause_time !=
320 VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME))
321 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_HIGH_PTIME);
323 if ((port_config->limiter_en !=
324 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_ENABLE) &&
325 (port_config->limiter_en !=
326 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DISABLE) &&
327 (port_config->limiter_en !=
328 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT))
329 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_PAUSE_LIMITER_EN);
331 if ((port_config->max_limit >
332 VXGE_HAL_SWITCH_PORT_MAX_RMAC_MAX_LIMIT) &&
333 (port_config->max_limit !=
334 VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT))
335 return (VXGE_HAL_BADCFG_SWITCH_PORT_RMAC_MAX_LIMIT);
337 return (VXGE_HAL_OK);
341 * __hal_device_mac_config_check - Check mac port configuration.
342 * @mac_config: MAC configuration information
344 * Check mac port configuration
346 * Returns: VXGE_HAL_OK - success,
347 * otherwise one of the vxge_hal_status_e enumerated error codes.
351 __hal_device_mac_config_check(vxge_hal_mac_config_t *mac_config)
354 vxge_hal_status_e status;
356 status = __hal_device_wire_port_config_check(
357 &mac_config->wire_port_config[0]);
359 if (status != VXGE_HAL_OK)
362 status = __hal_device_wire_port_config_check(
363 &mac_config->wire_port_config[1]);
365 if (status != VXGE_HAL_OK)
368 status = __hal_device_switch_port_config_check(
369 &mac_config->switch_port_config);
371 if (status != VXGE_HAL_OK)
374 if ((mac_config->network_stability_period >
375 VXGE_HAL_MAC_MAX_NETWORK_STABILITY_PERIOD) &&
376 (mac_config->network_stability_period !=
377 VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD))
378 return (VXGE_HAL_BADCFG_MAC_NETWORK_STABILITY_PERIOD);
380 for (i = 0; i < 16; i++) {
382 if ((mac_config->mc_pause_threshold[i] >
383 VXGE_HAL_MAC_MAX_MC_PAUSE_THRESHOLD) &&
384 (mac_config->mc_pause_threshold[i] !=
385 VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD))
386 return (VXGE_HAL_BADCFG_MAC_MC_PAUSE_THRESHOLD);
390 if ((mac_config->tmac_perma_stop_en !=
391 VXGE_HAL_MAC_TMAC_PERMA_STOP_ENABLE) &&
392 (mac_config->tmac_perma_stop_en !=
393 VXGE_HAL_MAC_TMAC_PERMA_STOP_DISABLE) &&
394 (mac_config->tmac_perma_stop_en !=
395 VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT))
396 return (VXGE_HAL_BADCFG_MAC_PERMA_STOP_EN);
398 if ((mac_config->tmac_tx_switch_dis !=
399 VXGE_HAL_MAC_TMAC_TX_SWITCH_ENABLE) &&
400 (mac_config->tmac_tx_switch_dis !=
401 VXGE_HAL_MAC_TMAC_TX_SWITCH_DISABLE) &&
402 (mac_config->tmac_tx_switch_dis !=
403 VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT))
404 return (VXGE_HAL_BADCFG_MAC_TMAC_TX_SWITCH_DIS);
406 if ((mac_config->tmac_lossy_switch_en !=
407 VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_ENABLE) &&
408 (mac_config->tmac_lossy_switch_en !=
409 VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DISABLE) &&
410 (mac_config->tmac_lossy_switch_en !=
411 VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT))
412 return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_SWITCH_EN);
414 if ((mac_config->tmac_lossy_wire_en !=
415 VXGE_HAL_MAC_TMAC_LOSSY_WIRE_ENABLE) &&
416 (mac_config->tmac_lossy_wire_en !=
417 VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DISABLE) &&
418 (mac_config->tmac_lossy_wire_en !=
419 VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT))
420 return (VXGE_HAL_BADCFG_MAC_TMAC_LOSSY_WIRE_EN);
422 if ((mac_config->tmac_bcast_to_wire_dis !=
423 VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DISABLE) &&
424 (mac_config->tmac_bcast_to_wire_dis !=
425 VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_ENABLE) &&
426 (mac_config->tmac_bcast_to_wire_dis !=
427 VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT))
428 return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_WIRE_DIS);
430 if ((mac_config->tmac_bcast_to_switch_dis !=
431 VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DISABLE) &&
432 (mac_config->tmac_bcast_to_switch_dis !=
433 VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_ENABLE) &&
434 (mac_config->tmac_bcast_to_switch_dis !=
435 VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT))
436 return (VXGE_HAL_BADCFG_MAC_TMAC_BCAST_TO_SWITCH_DIS);
438 if ((mac_config->tmac_host_append_fcs_en !=
439 VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_ENABLE) &&
440 (mac_config->tmac_host_append_fcs_en !=
441 VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DISABLE) &&
442 (mac_config->tmac_host_append_fcs_en !=
443 VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT))
444 return (VXGE_HAL_BADCFG_MAC_TMAC_HOST_APPEND_FCS_EN);
446 if ((mac_config->tpa_support_snap_ab_n !=
447 VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AB) &&
448 (mac_config->tpa_support_snap_ab_n !=
449 VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_LLC_SAP_AA) &&
450 (mac_config->tpa_support_snap_ab_n !=
451 VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT))
452 return (VXGE_HAL_BADCFG_MAC_TPA_SUPPORT_SNAP_AB_N);
454 if ((mac_config->tpa_ecc_enable_n !=
455 VXGE_HAL_MAC_TPA_ECC_ENABLE_N_ENABLE) &&
456 (mac_config->tpa_ecc_enable_n !=
457 VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DISABLE) &&
458 (mac_config->tpa_ecc_enable_n !=
459 VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT))
460 return (VXGE_HAL_BADCFG_MAC_TPA_ECC_ENABLE_N);
462 if ((mac_config->rpa_ignore_frame_err !=
463 VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_ENABLE) &&
464 (mac_config->rpa_ignore_frame_err !=
465 VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DISABLE) &&
466 (mac_config->rpa_ignore_frame_err !=
467 VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT))
468 return (VXGE_HAL_BADCFG_MAC_RPA_IGNORE_FRAME_ERR);
470 if ((mac_config->rpa_support_snap_ab_n !=
471 VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_ENABLE) &&
472 (mac_config->rpa_support_snap_ab_n !=
473 VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DISABLE) &&
474 (mac_config->rpa_support_snap_ab_n !=
475 VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT))
476 return (VXGE_HAL_BADCFG_MAC_RPA_SNAP_AB_N);
478 if ((mac_config->rpa_search_for_hao !=
479 VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_ENABLE) &&
480 (mac_config->rpa_search_for_hao !=
481 VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DISABLE) &&
482 (mac_config->rpa_search_for_hao !=
483 VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT))
484 return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_HAO);
486 if ((mac_config->rpa_support_ipv6_mobile_hdrs !=
487 VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_ENABLE) &&
488 (mac_config->rpa_support_ipv6_mobile_hdrs !=
489 VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DISABLE) &&
490 (mac_config->rpa_support_ipv6_mobile_hdrs !=
491 VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT))
492 return (VXGE_HAL_BADCFG_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS);
494 if ((mac_config->rpa_ipv6_stop_searching !=
495 VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING) &&
496 (mac_config->rpa_ipv6_stop_searching !=
497 VXGE_HAL_MAC_RPA_IPV6_DONT_STOP_SEARCHING) &&
498 (mac_config->rpa_ipv6_stop_searching !=
499 VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT))
500 return (VXGE_HAL_BADCFG_MAC_RPA_IPV6_STOP_SEARCHING);
502 if ((mac_config->rpa_no_ps_if_unknown !=
503 VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_ENABLE) &&
504 (mac_config->rpa_no_ps_if_unknown !=
505 VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DISABLE) &&
506 (mac_config->rpa_no_ps_if_unknown !=
507 VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT))
508 return (VXGE_HAL_BADCFG_MAC_RPA_NO_PS_IF_UNKNOWN);
510 if ((mac_config->rpa_search_for_etype !=
511 VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_ENABLE) &&
512 (mac_config->rpa_search_for_etype !=
513 VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DISABLE) &&
514 (mac_config->rpa_search_for_etype !=
515 VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT))
516 return (VXGE_HAL_BADCFG_MAC_RPA_SEARCH_FOR_ETYPE);
518 if ((mac_config->rpa_repl_l4_comp_csum !=
519 VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_ENABLE) &&
520 (mac_config->rpa_repl_l4_comp_csum !=
521 VXGE_HAL_MAC_RPA_REPL_L4_COMP_CSUM_DISABLE) &&
522 (mac_config->rpa_repl_l4_comp_csum !=
523 VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT))
524 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_COMP_CSUM);
526 if ((mac_config->rpa_repl_l3_incl_cf !=
527 VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_ENABLE) &&
528 (mac_config->rpa_repl_l3_incl_cf !=
529 VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DISABLE) &&
530 (mac_config->rpa_repl_l3_incl_cf !=
531 VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT))
532 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_INCL_CF);
534 if ((mac_config->rpa_repl_l3_comp_csum !=
535 VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_ENABLE) &&
536 (mac_config->rpa_repl_l3_comp_csum !=
537 VXGE_HAL_MAC_RPA_REPL_L3_COMP_CSUM_DISABLE) &&
538 (mac_config->rpa_repl_l3_comp_csum !=
539 VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT))
540 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L3_COMP_CSUM);
542 if ((mac_config->rpa_repl_ipv4_tcp_incl_ph !=
543 VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_ENABLE) &&
544 (mac_config->rpa_repl_ipv4_tcp_incl_ph !=
545 VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DISABLE) &&
546 (mac_config->rpa_repl_ipv4_tcp_incl_ph !=
547 VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT))
548 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_TCP_INCL_PH);
550 if ((mac_config->rpa_repl_ipv6_tcp_incl_ph !=
551 VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_ENABLE) &&
552 (mac_config->rpa_repl_ipv6_tcp_incl_ph !=
553 VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DISABLE) &&
554 (mac_config->rpa_repl_ipv6_tcp_incl_ph !=
555 VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT))
556 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_TCP_INCL_PH);
558 if ((mac_config->rpa_repl_ipv4_udp_incl_ph !=
559 VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_ENABLE) &&
560 (mac_config->rpa_repl_ipv4_udp_incl_ph !=
561 VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DISABLE) &&
562 (mac_config->rpa_repl_ipv4_udp_incl_ph !=
563 VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT))
564 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV4_UDP_INCL_PH);
566 if ((mac_config->rpa_repl_ipv6_udp_incl_ph !=
567 VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_ENABLE) &&
568 (mac_config->rpa_repl_ipv6_udp_incl_ph !=
569 VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DISABLE) &&
570 (mac_config->rpa_repl_ipv6_udp_incl_ph !=
571 VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT))
572 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_IPV6_UDP_INCL_PH);
574 if ((mac_config->rpa_repl_l4_incl_cf !=
575 VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_ENABLE) &&
576 (mac_config->rpa_repl_l4_incl_cf !=
577 VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DISABLE) &&
578 (mac_config->rpa_repl_l4_incl_cf !=
579 VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT))
580 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_L4_INCL_CF);
582 if ((mac_config->rpa_repl_strip_vlan_tag !=
583 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_ENABLE) &&
584 (mac_config->rpa_repl_strip_vlan_tag !=
585 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DISABLE) &&
586 (mac_config->rpa_repl_strip_vlan_tag !=
587 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT))
588 return (VXGE_HAL_BADCFG_MAC_RPA_REPL_STRIP_VLAN_TAG);
590 return (VXGE_HAL_OK);
594 * __hal_device_lag_port_config_check - Check LAG port configuration.
595 * @aggr_config: LAG port configuration information
597 * Check LAG port configuration
599 * Returns: VXGE_HAL_OK - success,
600 * otherwise one of the vxge_hal_status_e enumerated error codes.
604 __hal_device_lag_port_config_check(vxge_hal_lag_port_config_t *port_config)
606 if ((port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_0) &&
607 (port_config->port_id != VXGE_HAL_LAG_PORT_PORT_ID_1))
608 return (VXGE_HAL_BADCFG_LAG_PORT_PORT_ID);
610 if ((port_config->lag_en !=
611 VXGE_HAL_LAG_PORT_LAG_EN_DISABLE) &&
612 (port_config->lag_en !=
613 VXGE_HAL_LAG_PORT_LAG_EN_ENABLE) &&
614 (port_config->lag_en !=
615 VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT))
616 return (VXGE_HAL_BADCFG_LAG_PORT_LAG_EN);
618 if ((port_config->discard_slow_proto !=
619 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DISABLE) &&
620 (port_config->discard_slow_proto !=
621 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_ENABLE) &&
622 (port_config->discard_slow_proto !=
623 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT))
624 return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_SLOW_PROTO);
626 if ((port_config->host_chosen_aggr !=
627 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_0) &&
628 (port_config->host_chosen_aggr !=
629 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_1) &&
630 (port_config->host_chosen_aggr !=
631 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT))
632 return (VXGE_HAL_BADCFG_LAG_PORT_HOST_CHOSEN_AGGR);
634 if ((port_config->discard_unknown_slow_proto !=
635 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DISABLE) &&
636 (port_config->discard_unknown_slow_proto !=
637 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_ENABLE) &&
638 (port_config->discard_unknown_slow_proto !=
639 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT))
640 return (VXGE_HAL_BADCFG_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO);
642 if ((port_config->actor_port_num >
643 VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_NUM) &&
644 (port_config->actor_port_num !=
645 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM))
646 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_NUM);
648 if ((port_config->actor_port_priority >
649 VXGE_HAL_LAG_PORT_MAX_ACTOR_PORT_PRIORITY) &&
650 (port_config->actor_port_priority !=
651 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY))
652 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_PORT_PRIORITY);
654 if ((port_config->actor_key_10g >
655 VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_10G) &&
656 (port_config->actor_key_10g !=
657 VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G))
658 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_10G);
660 if ((port_config->actor_key_1g > VXGE_HAL_LAG_PORT_MAX_ACTOR_KEY_1G) &&
661 (port_config->actor_key_1g != VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G))
662 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_KEY_1G);
664 if ((port_config->actor_lacp_activity !=
665 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_PASSIVE) &&
666 (port_config->actor_lacp_activity !=
667 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_ACTIVE) &&
668 (port_config->actor_lacp_activity !=
669 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT))
670 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_ACTIVITY);
672 if ((port_config->actor_lacp_timeout !=
673 VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_LONG) &&
674 (port_config->actor_lacp_timeout !=
675 VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_SHORT) &&
676 (port_config->actor_lacp_timeout !=
677 VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT))
678 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_LACP_TIMEOUT);
680 if ((port_config->actor_aggregation !=
681 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_INDIVIDUAL) &&
682 (port_config->actor_aggregation !=
683 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_AGGREGATEABLE) &&
684 (port_config->actor_aggregation !=
685 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT))
686 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_AGGREGATION);
688 if ((port_config->actor_synchronization !=
689 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_OUT_OF_SYNC) &&
690 (port_config->actor_synchronization !=
691 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_IN_SYNC) &&
692 (port_config->actor_synchronization !=
693 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT))
694 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_SYNCHRONIZATION);
696 if ((port_config->actor_collecting !=
697 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DISABLE) &&
698 (port_config->actor_collecting !=
699 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_ENABLE) &&
700 (port_config->actor_collecting !=
701 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT))
702 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_COLLECTING);
704 if ((port_config->actor_distributing !=
705 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) &&
706 (port_config->actor_distributing !=
707 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) &&
708 (port_config->actor_distributing !=
709 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT))
710 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING);
712 if ((port_config->actor_distributing !=
713 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DISABLE) &&
714 (port_config->actor_distributing !=
715 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_ENABLE) &&
716 (port_config->actor_distributing !=
717 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT))
718 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DISTRIBUTING);
720 if ((port_config->actor_defaulted !=
721 VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED) &&
722 (port_config->actor_defaulted !=
723 VXGE_HAL_LAG_PORT_ACTOR_NOT_DEFAULTED) &&
724 (port_config->actor_defaulted !=
725 VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT))
726 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_DEFAULTED);
728 if ((port_config->actor_expired !=
729 VXGE_HAL_LAG_PORT_ACTOR_EXPIRED) &&
730 (port_config->actor_expired !=
731 VXGE_HAL_LAG_PORT_ACTOR_NOT_EXPIRED) &&
732 (port_config->actor_expired !=
733 VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT))
734 return (VXGE_HAL_BADCFG_LAG_PORT_ACTOR_EXPIRED);
736 if ((port_config->partner_sys_pri >
737 VXGE_HAL_LAG_PORT_MAX_PARTNER_SYS_PRI) &&
738 (port_config->partner_sys_pri !=
739 VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI))
740 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYS_PRI);
742 if ((port_config->partner_key > VXGE_HAL_LAG_PORT_MAX_PARTNER_KEY) &&
743 (port_config->partner_key != VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY))
744 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_KEY);
746 if ((port_config->partner_port_num >
747 VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_NUM) &&
748 (port_config->partner_port_num !=
749 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM))
750 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_NUM);
752 if ((port_config->partner_port_priority >
753 VXGE_HAL_LAG_PORT_MAX_PARTNER_PORT_PRIORITY) &&
754 (port_config->partner_port_priority !=
755 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY))
756 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_PORT_PRIORITY);
758 if ((port_config->partner_lacp_activity !=
759 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_PASSIVE) &&
760 (port_config->partner_lacp_activity !=
761 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_ACTIVE) &&
762 (port_config->partner_lacp_activity !=
763 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT))
764 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_ACTIVITY);
766 if ((port_config->partner_lacp_timeout !=
767 VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_LONG) &&
768 (port_config->partner_lacp_timeout !=
769 VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_SHORT) &&
770 (port_config->partner_lacp_timeout !=
771 VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT))
772 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_LACP_TIMEOUT);
774 if ((port_config->partner_aggregation !=
775 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_INDIVIDUAL) &&
776 (port_config->partner_aggregation !=
777 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_AGGREGATEABLE) &&
778 (port_config->partner_aggregation !=
779 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT))
780 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_AGGREGATION);
782 if ((port_config->partner_synchronization !=
783 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_OUT_OF_SYNC) &&
784 (port_config->partner_synchronization !=
785 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_IN_SYNC) &&
786 (port_config->partner_synchronization !=
787 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT))
788 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_SYNCHRONIZATION);
790 if ((port_config->partner_collecting !=
791 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DISABLE) &&
792 (port_config->partner_collecting !=
793 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_ENABLE) &&
794 (port_config->partner_collecting !=
795 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT))
796 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_COLLECTING);
798 if ((port_config->partner_distributing !=
799 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) &&
800 (port_config->partner_distributing !=
801 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) &&
802 (port_config->partner_distributing !=
803 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT))
804 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING);
806 if ((port_config->partner_distributing !=
807 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DISABLE) &&
808 (port_config->partner_distributing !=
809 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_ENABLE) &&
810 (port_config->partner_distributing !=
811 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT))
812 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DISTRIBUTING);
814 if ((port_config->partner_defaulted !=
815 VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED) &&
816 (port_config->partner_defaulted !=
817 VXGE_HAL_LAG_PORT_PARTNER_NOT_DEFAULTED) &&
818 (port_config->partner_defaulted !=
819 VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT))
820 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_DEFAULTED);
822 if ((port_config->partner_expired !=
823 VXGE_HAL_LAG_PORT_PARTNER_EXPIRED) &&
824 (port_config->partner_expired !=
825 VXGE_HAL_LAG_PORT_PARTNER_NOT_EXPIRED) &&
826 (port_config->partner_expired !=
827 VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT))
828 return (VXGE_HAL_BADCFG_LAG_PORT_PARTNER_EXPIRED);
830 return (VXGE_HAL_OK);
834 * __hal_device_lag_aggr_config_check - Check aggregator configuration.
835 * @aggr_config: Aggregator configuration information
837 * Check aggregator configuration
839 * Returns: VXGE_HAL_OK - success,
840 * otherwise one of the vxge_hal_status_e enumerated error codes.
844 __hal_device_lag_aggr_config_check(vxge_hal_lag_aggr_config_t *aggr_config)
846 if ((aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_1) &&
847 (aggr_config->aggr_id != VXGE_HAL_LAG_AGGR_AGGR_ID_2))
848 return (VXGE_HAL_BADCFG_LAG_AGGR_AGGR_ID);
850 if ((aggr_config->use_port_mac_addr !=
851 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DISBALE) &&
852 (aggr_config->use_port_mac_addr !=
853 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_ENABLE) &&
854 (aggr_config->use_port_mac_addr !=
855 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT))
856 return (VXGE_HAL_BADCFG_LAG_AGGR_USE_PORT_MAC_ADDR);
858 if ((aggr_config->mac_addr_sel !=
859 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_0) &&
860 (aggr_config->mac_addr_sel !=
861 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_PORT_1) &&
862 (aggr_config->mac_addr_sel !=
863 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT))
864 return (VXGE_HAL_BADCFG_LAG_AGGR_MAC_ADDR_SEL);
866 if ((aggr_config->admin_key > VXGE_HAL_LAG_AGGR_MAX_ADMIN_KEY) &&
867 (aggr_config->admin_key != VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY))
868 return (VXGE_HAL_BADCFG_LAG_AGGR_ADMIN_KEY);
870 return (VXGE_HAL_OK);
874 * __hal_device_lag_la_config_check
875 * Check LAG link aggregation mode configuration.
876 * @la_config: LAG configuration information
878 * Check LAG link aggregation mode configuration
880 * Returns: VXGE_HAL_OK - success,
881 * otherwise one of the vxge_hal_status_e enumerated error codes.
885 __hal_device_lag_la_config_check(vxge_hal_lag_la_config_t *la_config)
887 if ((la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DISBALE) &&
888 (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_ENABLE) &&
889 (la_config->tx_discard != VXGE_HAL_LAG_TX_DISCARD_DEFAULT))
890 return (VXGE_HAL_BADCFG_LAG_TX_DISCARD);
892 if ((la_config->distrib_alg_sel !=
893 VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_VPATH) &&
894 (la_config->distrib_alg_sel !=
895 VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEST_MAC_ADDR) &&
896 (la_config->distrib_alg_sel !=
897 VXGE_HAL_LAG_DISTRIB_ALG_SEL_SRC_MAC_ADDR) &&
898 (la_config->distrib_alg_sel !=
899 VXGE_HAL_LAG_DISTRIB_ALG_SEL_BOTH_MAC_ADDR) &&
900 (la_config->distrib_alg_sel !=
901 VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT))
902 return (VXGE_HAL_BADCFG_LAG_DISTRIB_ALG_SEL);
904 if ((la_config->distrib_remap_if_fail !=
905 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DISBALE) &&
906 (la_config->distrib_remap_if_fail !=
907 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_ENABLE) &&
908 (la_config->distrib_remap_if_fail !=
909 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT))
910 return (VXGE_HAL_BADCFG_LAG_DISTRIB_REMAP_IF_FAIL);
912 if ((la_config->coll_max_delay > VXGE_HAL_LAG_MAX_COLL_MAX_DELAY) &&
913 (la_config->coll_max_delay != VXGE_HAL_LAG_DEF_COLL_MAX_DELAY))
914 return (VXGE_HAL_BADCFG_LAG_COLL_MAX_DELAY);
916 if ((la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DISBALE) &&
917 (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_ENABLE) &&
918 (la_config->rx_discard != VXGE_HAL_LAG_RX_DISCARD_DEFAULT))
919 return (VXGE_HAL_BADCFG_LAG_RX_DISCARD);
921 return (VXGE_HAL_OK);
925 * __hal_device_lag_ap_config_check - Check LAG a/p mode configuration.
926 * @ap_config: LAG configuration information
928 * Check LAG a/p mode configuration
930 * Returns: VXGE_HAL_OK - success,
931 * otherwise one of the vxge_hal_status_e enumerated error codes.
935 __hal_device_lag_ap_config_check(vxge_hal_lag_ap_config_t *ap_config)
937 if ((ap_config->hot_standby !=
938 VXGE_HAL_LAG_HOT_STANDBY_DISBALE_PORT) &&
939 (ap_config->hot_standby !=
940 VXGE_HAL_LAG_HOT_STANDBY_KEEP_UP_PORT) &&
941 (ap_config->hot_standby !=
942 VXGE_HAL_LAG_HOT_STANDBY_DEFAULT))
943 return (VXGE_HAL_BADCFG_LAG_HOT_STANDBY);
945 if ((ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DISBALE) &&
946 (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_ENBALE) &&
947 (ap_config->lacp_decides != VXGE_HAL_LAG_LACP_DECIDES_DEFAULT))
948 return (VXGE_HAL_BADCFG_LAG_LACP_DECIDES);
950 if ((ap_config->pref_active_port !=
951 VXGE_HAL_LAG_PREF_ACTIVE_PORT_0) &&
952 (ap_config->pref_active_port !=
953 VXGE_HAL_LAG_PREF_ACTIVE_PORT_1) &&
954 (ap_config->pref_active_port !=
955 VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT))
956 return (VXGE_HAL_BADCFG_LAG_PREF_ACTIVE_PORT);
958 if ((ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DISBALE) &&
959 (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_ENBALE) &&
960 (ap_config->auto_failback != VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT))
961 return (VXGE_HAL_BADCFG_LAG_AUTO_FAILBACK);
963 if ((ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DISBALE) &&
964 (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_ENBALE) &&
965 (ap_config->failback_en != VXGE_HAL_LAG_FAILBACK_EN_DEFAULT))
966 return (VXGE_HAL_BADCFG_LAG_FAILBACK_EN);
968 if ((ap_config->cold_failover_timeout !=
969 VXGE_HAL_LAG_MIN_COLD_FAILOVER_TIMEOUT) &&
970 (ap_config->cold_failover_timeout !=
971 VXGE_HAL_LAG_MAX_COLD_FAILOVER_TIMEOUT) &&
972 (ap_config->cold_failover_timeout !=
973 VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT))
974 return (VXGE_HAL_BADCFG_LAG_COLD_FAILOVER_TIMEOUT);
976 if ((ap_config->alt_admin_key !=
977 VXGE_HAL_LAG_MIN_ALT_ADMIN_KEY) &&
978 (ap_config->alt_admin_key !=
979 VXGE_HAL_LAG_MAX_ALT_ADMIN_KEY) &&
980 (ap_config->alt_admin_key !=
981 VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY))
982 return (VXGE_HAL_BADCFG_LAG_ALT_ADMIN_KEY);
984 if ((ap_config->alt_aggr !=
985 VXGE_HAL_LAG_ALT_AGGR_0) &&
986 (ap_config->alt_aggr !=
987 VXGE_HAL_LAG_ALT_AGGR_1) &&
988 (ap_config->alt_aggr !=
989 VXGE_HAL_LAG_ALT_AGGR_DEFAULT))
990 return (VXGE_HAL_BADCFG_LAG_ALT_AGGR);
992 return (VXGE_HAL_OK);
996 * __hal_device_lag_sl_config_check - Check LAG Single Link mode configuration.
997 * @sl_config: LAG configuration information
999 * Check LAG Single link mode configuration
1001 * Returns: VXGE_HAL_OK - success,
1002 * otherwise one of the vxge_hal_status_e enumerated error codes.
1006 __hal_device_lag_sl_config_check(vxge_hal_lag_sl_config_t *sl_config)
1008 if ((sl_config->pref_indiv_port !=
1009 VXGE_HAL_LAG_PREF_INDIV_PORT_0) &&
1010 (sl_config->pref_indiv_port !=
1011 VXGE_HAL_LAG_PREF_INDIV_PORT_1) &&
1012 (sl_config->pref_indiv_port !=
1013 VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT))
1014 return (VXGE_HAL_BADCFG_LAG_PREF_INDIV_PORT);
1016 return (VXGE_HAL_OK);
1020 * __hal_device_lag_lacp_config_check - Check LACP configuration.
1021 * @lacp_config: LAG configuration information
1023 * Check LACP configuration
1025 * Returns: VXGE_HAL_OK - success,
1026 * otherwise one of the vxge_hal_status_e enumerated error codes.
1030 __hal_device_lag_lacp_config_check(vxge_hal_lag_lacp_config_t *lacp_config)
1032 if ((lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DISBALE) &&
1033 (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_ENABLE) &&
1034 (lacp_config->lacp_en != VXGE_HAL_LAG_LACP_EN_DEFAULT))
1035 return (VXGE_HAL_BADCFG_LAG_LACP_EN);
1037 if ((lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_NORMAL) &&
1038 (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_RESET) &&
1039 (lacp_config->lacp_begin != VXGE_HAL_LAG_LACP_BEGIN_DEFAULT))
1040 return (VXGE_HAL_BADCFG_LAG_LACP_BEGIN);
1042 if ((lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DISBALE) &&
1043 (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_ENABLE) &&
1044 (lacp_config->discard_lacp != VXGE_HAL_LAG_DISCARD_LACP_DEFAULT))
1045 return (VXGE_HAL_BADCFG_LAG_DISCARD_LACP);
1047 if ((lacp_config->liberal_len_chk !=
1048 VXGE_HAL_LAG_LIBERAL_LEN_CHK_DISBALE) &&
1049 (lacp_config->liberal_len_chk !=
1050 VXGE_HAL_LAG_LIBERAL_LEN_CHK_ENABLE) &&
1051 (lacp_config->liberal_len_chk !=
1052 VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT))
1053 return (VXGE_HAL_BADCFG_LAG_LIBERAL_LEN_CHK);
1055 if ((lacp_config->marker_gen_recv_en !=
1056 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DISBALE) &&
1057 (lacp_config->marker_gen_recv_en !=
1058 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_ENABLE) &&
1059 (lacp_config->marker_gen_recv_en !=
1060 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT))
1061 return (VXGE_HAL_BADCFG_LAG_MARKER_GEN_RECV_EN);
1063 if ((lacp_config->marker_resp_en !=
1064 VXGE_HAL_LAG_MARKER_RESP_EN_DISBALE) &&
1065 (lacp_config->marker_resp_en !=
1066 VXGE_HAL_LAG_MARKER_RESP_EN_ENABLE) &&
1067 (lacp_config->marker_resp_en !=
1068 VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT))
1069 return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_EN);
1071 if ((lacp_config->marker_resp_timeout !=
1072 VXGE_HAL_LAG_MIN_MARKER_RESP_TIMEOUT) &&
1073 (lacp_config->marker_resp_timeout !=
1074 VXGE_HAL_LAG_MAX_MARKER_RESP_TIMEOUT) &&
1075 (lacp_config->marker_resp_timeout !=
1076 VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT))
1077 return (VXGE_HAL_BADCFG_LAG_MARKER_RESP_TIMEOUT);
1079 if ((lacp_config->slow_proto_mrkr_min_interval !=
1080 VXGE_HAL_LAG_MIN_SLOW_PROTO_MRKR_MIN_INTERVAL) &&
1081 (lacp_config->slow_proto_mrkr_min_interval !=
1082 VXGE_HAL_LAG_MAX_SLOW_PROTO_MRKR_MIN_INTERVAL) &&
1083 (lacp_config->slow_proto_mrkr_min_interval !=
1084 VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL))
1085 return (VXGE_HAL_BADCFG_LAG_SLOW_PROTO_MRKR_MIN_INTERVAL);
1087 if ((lacp_config->throttle_mrkr_resp !=
1088 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DISBALE) &&
1089 (lacp_config->throttle_mrkr_resp !=
1090 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_ENABLE) &&
1091 (lacp_config->throttle_mrkr_resp !=
1092 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT))
1093 return (VXGE_HAL_BADCFG_LAG_THROTTLE_MRKR_RESP);
1095 return (VXGE_HAL_OK);
1099 * __hal_device_lag_config_check - Check link aggregation configuration.
1100 * @lag_config: LAG configuration information
1102 * Check link aggregation configuration
1104 * Returns: VXGE_HAL_OK - success,
1105 * otherwise one of the vxge_hal_status_e enumerated error codes.
1109 __hal_device_lag_config_check(vxge_hal_lag_config_t *lag_config)
1112 vxge_hal_status_e status;
1114 if ((lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DISABLE) &&
1115 (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_ENABLE) &&
1116 (lag_config->lag_en != VXGE_HAL_LAG_LAG_EN_DEFAULT))
1117 return (VXGE_HAL_BADCFG_LAG_LAG_EN);
1119 if ((lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_LAG) &&
1120 (lag_config->lag_mode !=
1121 VXGE_HAL_LAG_LAG_MODE_ACTIVE_PASSIVE_FAILOVER) &&
1122 (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_SINGLE_LINK) &&
1123 (lag_config->lag_mode != VXGE_HAL_LAG_LAG_MODE_DEFAULT))
1124 return (VXGE_HAL_BADCFG_LAG_LAG_MODE);
1126 status = __hal_device_lag_la_config_check(&lag_config->la_mode_config);
1127 if (status == VXGE_HAL_OK)
1130 status = __hal_device_lag_ap_config_check(&lag_config->ap_mode_config);
1131 if (status == VXGE_HAL_OK)
1134 status = __hal_device_lag_sl_config_check(&lag_config->sl_mode_config);
1135 if (status == VXGE_HAL_OK)
1138 status = __hal_device_lag_lacp_config_check(&lag_config->lacp_config);
1139 if (status == VXGE_HAL_OK)
1142 if ((lag_config->incr_tx_aggr_stats !=
1143 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DISBALE) &&
1144 (lag_config->incr_tx_aggr_stats !=
1145 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_ENABLE) &&
1146 (lag_config->incr_tx_aggr_stats !=
1147 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT))
1148 return (VXGE_HAL_BADCFG_LAG_TX_AGGR_STATS);
1150 for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) {
1152 if ((status = __hal_device_lag_port_config_check(
1153 &lag_config->port_config[i])) != VXGE_HAL_OK)
1158 for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) {
1160 if ((status = __hal_device_lag_aggr_config_check(
1161 &lag_config->aggr_config[i])) != VXGE_HAL_OK)
1166 if ((lag_config->sys_pri > VXGE_HAL_LAG_MAX_SYS_PRI) &&
1167 (lag_config->sys_pri != VXGE_HAL_LAG_DEF_SYS_PRI))
1168 return (VXGE_HAL_BADCFG_LAG_SYS_PRI);
1170 if ((lag_config->use_port_mac_addr !=
1171 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DISBALE) &&
1172 (lag_config->use_port_mac_addr !=
1173 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_ENABLE) &&
1174 (lag_config->use_port_mac_addr !=
1175 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT))
1176 return (VXGE_HAL_BADCFG_LAG_USE_PORT_MAC_ADDR);
1178 if ((lag_config->mac_addr_sel !=
1179 VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_0) &&
1180 (lag_config->mac_addr_sel !=
1181 VXGE_HAL_LAG_MAC_ADDR_SEL_PORT_1) &&
1182 (lag_config->mac_addr_sel !=
1183 VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT))
1184 return (VXGE_HAL_BADCFG_LAG_MAC_ADDR_SEL);
1186 if ((lag_config->fast_per_time > VXGE_HAL_LAG_MAX_FAST_PER_TIME) &&
1187 (lag_config->fast_per_time != VXGE_HAL_LAG_DEF_FAST_PER_TIME))
1188 return (VXGE_HAL_BADCFG_LAG_FAST_PER_TIME);
1190 if ((lag_config->slow_per_time > VXGE_HAL_LAG_MAX_SLOW_PER_TIME) &&
1191 (lag_config->slow_per_time != VXGE_HAL_LAG_DEF_SLOW_PER_TIME))
1192 return (VXGE_HAL_BADCFG_LAG_SLOW_PER_TIME);
1194 if ((lag_config->short_timeout > VXGE_HAL_LAG_MAX_SHORT_TIMEOUT) &&
1195 (lag_config->short_timeout != VXGE_HAL_LAG_DEF_SHORT_TIMEOUT))
1196 return (VXGE_HAL_BADCFG_LAG_SHORT_TIMEOUT);
1198 if ((lag_config->long_timeout > VXGE_HAL_LAG_MAX_LONG_TIMEOUT) &&
1199 (lag_config->long_timeout != VXGE_HAL_LAG_DEF_LONG_TIMEOUT))
1200 return (VXGE_HAL_BADCFG_LAG_LONG_TIMEOUT);
1202 if ((lag_config->churn_det_time > VXGE_HAL_LAG_MAX_CHURN_DET_TIME) &&
1203 (lag_config->churn_det_time != VXGE_HAL_LAG_DEF_CHURN_DET_TIME))
1204 return (VXGE_HAL_BADCFG_LAG_CHURN_DET_TIME);
1206 if ((lag_config->aggr_wait_time > VXGE_HAL_LAG_MAX_AGGR_WAIT_TIME) &&
1207 (lag_config->aggr_wait_time != VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME))
1208 return (VXGE_HAL_BADCFG_LAG_AGGR_WAIT_TIME);
1210 if ((lag_config->short_timer_scale !=
1211 VXGE_HAL_LAG_SHORT_TIMER_SCALE_1X) &&
1212 (lag_config->short_timer_scale !=
1213 VXGE_HAL_LAG_SHORT_TIMER_SCALE_10X) &&
1214 (lag_config->short_timer_scale !=
1215 VXGE_HAL_LAG_SHORT_TIMER_SCALE_100X) &&
1216 (lag_config->short_timer_scale !=
1217 VXGE_HAL_LAG_SHORT_TIMER_SCALE_1000X) &&
1218 (lag_config->short_timer_scale !=
1219 VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT))
1220 return (VXGE_HAL_BADCFG_LAG_SHORT_TIMER_SCALE);
1222 if ((lag_config->long_timer_scale !=
1223 VXGE_HAL_LAG_LONG_TIMER_SCALE_1X) &&
1224 (lag_config->long_timer_scale !=
1225 VXGE_HAL_LAG_LONG_TIMER_SCALE_10X) &&
1226 (lag_config->long_timer_scale !=
1227 VXGE_HAL_LAG_LONG_TIMER_SCALE_100X) &&
1228 (lag_config->long_timer_scale !=
1229 VXGE_HAL_LAG_LONG_TIMER_SCALE_1000X) &&
1230 (lag_config->long_timer_scale !=
1231 VXGE_HAL_LAG_LONG_TIMER_SCALE_10000X) &&
1232 (lag_config->long_timer_scale !=
1233 VXGE_HAL_LAG_LONG_TIMER_SCALE_100000X) &&
1234 (lag_config->long_timer_scale !=
1235 VXGE_HAL_LAG_LONG_TIMER_SCALE_1000000X) &&
1236 (lag_config->long_timer_scale !=
1237 VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT))
1238 return (VXGE_HAL_BADCFG_LAG_LONG_TIMER_SCALE);
1240 return (VXGE_HAL_OK);
1244 * __hal_vpath_qos_config_check - Check vpath QOS configuration.
1245 * @config: Vpath QOS configuration information
1247 * Check the vpath QOS configuration
1249 * Returns: VXGE_HAL_OK - success,
1250 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1254 __hal_vpath_qos_config_check(vxge_hal_vpath_qos_config_t *config)
1256 if ((config->priority > VXGE_HAL_VPATH_QOS_PRIORITY_MAX) &&
1257 (config->priority != VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT))
1258 return (VXGE_HAL_BADCFG_VPATH_QOS_PRIORITY);
1260 if ((config->min_bandwidth >
1261 VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_MAX) &&
1262 (config->min_bandwidth !=
1263 VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT))
1264 return (VXGE_HAL_BADCFG_VPATH_QOS_MIN_BANDWIDTH);
1266 if ((config->max_bandwidth >
1267 VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_MAX) &&
1268 (config->max_bandwidth !=
1269 VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT))
1270 return (VXGE_HAL_BADCFG_VPATH_QOS_MAX_BANDWIDTH);
1272 return (VXGE_HAL_OK);
1276 * __hal_mrpcim_config_check - Check mrpcim configuration.
1277 * @config: mrpcim configuration information
1279 * Check the mrpcim configuration
1281 * Returns: VXGE_HAL_OK - success,
1282 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1286 __hal_mrpcim_config_check(vxge_hal_mrpcim_config_t *config)
1289 vxge_hal_status_e status = VXGE_HAL_OK;
1291 if ((status = __hal_device_mac_config_check(&config->mac_config)) !=
1295 if ((status = __hal_device_lag_config_check(&config->lag_config)) !=
1299 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
1301 if ((status = __hal_vpath_qos_config_check(
1302 &config->vp_qos[i])) != VXGE_HAL_OK)
1307 return (VXGE_HAL_OK);
1311 * __hal_device_ring_config_check - Check ring configuration.
1312 * @ring_config: Device configuration information
1314 * Check the ring configuration
1316 * Returns: VXGE_HAL_OK - success,
1317 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1321 __hal_device_ring_config_check(vxge_hal_ring_config_t *ring_config)
1323 if ((ring_config->enable != VXGE_HAL_RING_ENABLE) &&
1324 (ring_config->enable != VXGE_HAL_RING_DISABLE))
1325 return (VXGE_HAL_BADCFG_RING_ENABLE);
1327 if ((ring_config->ring_length < VXGE_HAL_MIN_RING_LENGTH) ||
1328 (ring_config->ring_length > VXGE_HAL_MAX_RING_LENGTH))
1329 return (VXGE_HAL_BADCFG_RING_LENGTH);
1331 if ((ring_config->buffer_mode < VXGE_HAL_RING_RXD_BUFFER_MODE_1) ||
1332 (ring_config->buffer_mode > VXGE_HAL_RING_RXD_BUFFER_MODE_5))
1333 return (VXGE_HAL_BADCFG_RING_RXD_BUFFER_MODE);
1335 if ((ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_A) &&
1336 (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_B) &&
1337 (ring_config->scatter_mode != VXGE_HAL_RING_SCATTER_MODE_C) &&
1338 (ring_config->scatter_mode !=
1339 VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT))
1340 return (VXGE_HAL_BADCFG_RING_SCATTER_MODE);
1342 if ((ring_config->post_mode != VXGE_HAL_RING_POST_MODE_LEGACY) &&
1343 (ring_config->post_mode != VXGE_HAL_RING_POST_MODE_DOORBELL) &&
1344 (ring_config->post_mode !=
1345 VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT))
1346 return (VXGE_HAL_BADCFG_RING_POST_MODE);
1348 if ((ring_config->max_frm_len > VXGE_HAL_MAX_RING_MAX_FRM_LEN) &&
1349 (ring_config->max_frm_len != VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU))
1350 return (VXGE_HAL_BADCFG_RING_MAX_FRM_LEN);
1352 if ((ring_config->no_snoop_bits > VXGE_HAL_RING_NO_SNOOP_ALL) &&
1353 (ring_config->no_snoop_bits !=
1354 VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT))
1355 return (VXGE_HAL_BADCFG_RING_NO_SNOOP_ALL);
1357 if ((ring_config->rx_timer_val > VXGE_HAL_RING_MAX_RX_TIMER_VAL) &&
1358 (ring_config->rx_timer_val !=
1359 VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL))
1360 return (VXGE_HAL_BADCFG_RING_TIMER_VAL);
1362 if ((ring_config->greedy_return !=
1363 VXGE_HAL_RING_GREEDY_RETURN_ENABLE) &&
1364 (ring_config->greedy_return !=
1365 VXGE_HAL_RING_GREEDY_RETURN_DISABLE) &&
1366 (ring_config->greedy_return !=
1367 VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT))
1368 return (VXGE_HAL_BADCFG_RING_GREEDY_RETURN);
1370 if ((ring_config->rx_timer_ci !=
1371 VXGE_HAL_RING_RX_TIMER_CI_ENABLE) &&
1372 (ring_config->rx_timer_ci !=
1373 VXGE_HAL_RING_RX_TIMER_CI_DISABLE) &&
1374 (ring_config->rx_timer_ci !=
1375 VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT))
1376 return (VXGE_HAL_BADCFG_RING_TIMER_CI);
1378 if (((ring_config->backoff_interval_us <
1379 VXGE_HAL_MIN_BACKOFF_INTERVAL_US) ||
1380 (ring_config->backoff_interval_us >
1381 VXGE_HAL_MAX_BACKOFF_INTERVAL_US)) &&
1382 (ring_config->backoff_interval_us !=
1383 VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US))
1384 return (VXGE_HAL_BADCFG_RING_BACKOFF_INTERVAL_US);
1386 if ((ring_config->indicate_max_pkts <
1387 VXGE_HAL_MIN_RING_INDICATE_MAX_PKTS) ||
1388 (ring_config->indicate_max_pkts >
1389 VXGE_HAL_MAX_RING_INDICATE_MAX_PKTS))
1390 return (VXGE_HAL_BADCFG_RING_INDICATE_MAX_PKTS);
1392 return (VXGE_HAL_OK);
1396 * __hal_device_fifo_config_check - Check fifo configuration.
1397 * @fifo_config: Fifo configuration information
1399 * Check the fifo configuration
1401 * Returns: VXGE_HAL_OK - success,
1402 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1406 __hal_device_fifo_config_check(vxge_hal_fifo_config_t *fifo_config)
1408 if ((fifo_config->enable != VXGE_HAL_FIFO_ENABLE) &&
1409 (fifo_config->enable != VXGE_HAL_FIFO_DISABLE))
1410 return (VXGE_HAL_BADCFG_FIFO_ENABLE);
1412 if ((fifo_config->fifo_length < VXGE_HAL_MIN_FIFO_LENGTH) ||
1413 (fifo_config->fifo_length > VXGE_HAL_MAX_FIFO_LENGTH))
1414 return (VXGE_HAL_BADCFG_FIFO_LENGTH);
1416 if ((fifo_config->max_frags < VXGE_HAL_MIN_FIFO_FRAGS) ||
1417 (fifo_config->max_frags > VXGE_HAL_MAX_FIFO_FRAGS))
1418 return (VXGE_HAL_BADCFG_FIFO_FRAGS);
1420 if (fifo_config->alignment_size > VXGE_HAL_MAX_FIFO_ALIGNMENT_SIZE)
1421 return (VXGE_HAL_BADCFG_FIFO_ALIGNMENT_SIZE);
1423 if (fifo_config->max_aligned_frags > fifo_config->max_frags)
1424 return (VXGE_HAL_BADCFG_FIFO_MAX_FRAGS);
1426 if ((fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_ENABLE) &&
1427 (fifo_config->intr != VXGE_HAL_FIFO_QUEUE_INTR_DISABLE))
1428 return (VXGE_HAL_BADCFG_FIFO_QUEUE_INTR);
1430 if (fifo_config->no_snoop_bits > VXGE_HAL_FIFO_NO_SNOOP_ALL)
1431 return (VXGE_HAL_BADCFG_FIFO_NO_SNOOP_ALL);
1433 return (VXGE_HAL_OK);
1438 * __hal_device_tim_intr_config_check - Check tim intr configuration.
1439 * @tim_intr_config: tim intr configuration information
1441 * Check the tim intr configuration
1443 * Returns: VXGE_HAL_OK - success,
1444 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1448 __hal_device_tim_intr_config_check(vxge_hal_tim_intr_config_t *tim_intr_config)
1450 if ((tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_ENABLE) &&
1451 (tim_intr_config->intr_enable != VXGE_HAL_TIM_INTR_DISABLE))
1452 return (VXGE_HAL_BADCFG_TIM_INTR_ENABLE);
1454 if ((tim_intr_config->btimer_val >
1455 VXGE_HAL_MAX_TIM_BTIMER_VAL) &&
1456 (tim_intr_config->btimer_val !=
1457 VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL))
1458 return (VXGE_HAL_BADCFG_TIM_BTIMER_VAL);
1460 if ((tim_intr_config->timer_ac_en !=
1461 VXGE_HAL_TIM_TIMER_AC_ENABLE) &&
1462 (tim_intr_config->timer_ac_en !=
1463 VXGE_HAL_TIM_TIMER_AC_DISABLE) &&
1464 (tim_intr_config->timer_ac_en !=
1465 VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT))
1466 return (VXGE_HAL_BADCFG_TIM_TIMER_AC_EN);
1468 if ((tim_intr_config->timer_ci_en !=
1469 VXGE_HAL_TIM_TIMER_CI_ENABLE) &&
1470 (tim_intr_config->timer_ci_en !=
1471 VXGE_HAL_TIM_TIMER_CI_DISABLE) &&
1472 (tim_intr_config->timer_ci_en !=
1473 VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT))
1474 return (VXGE_HAL_BADCFG_TIM_TIMER_CI_EN);
1476 if ((tim_intr_config->timer_ri_en !=
1477 VXGE_HAL_TIM_TIMER_RI_ENABLE) &&
1478 (tim_intr_config->timer_ri_en !=
1479 VXGE_HAL_TIM_TIMER_RI_DISABLE) &&
1480 (tim_intr_config->timer_ri_en !=
1481 VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT))
1482 return (VXGE_HAL_BADCFG_TIM_TIMER_RI_EN);
1484 if ((tim_intr_config->rtimer_event_sf >
1485 VXGE_HAL_MAX_TIM_RTIMER_EVENT_SF) &&
1486 (tim_intr_config->rtimer_event_sf !=
1487 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF))
1488 return (VXGE_HAL_BADCFG_TIM_BTIMER_EVENT_SF);
1490 if ((tim_intr_config->rtimer_val >
1491 VXGE_HAL_MAX_TIM_RTIMER_VAL) &&
1492 (tim_intr_config->rtimer_val !=
1493 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL))
1494 return (VXGE_HAL_BADCFG_TIM_RTIMER_VAL);
1496 if ((((tim_intr_config->util_sel > 19) &&
1497 (tim_intr_config->util_sel < 32)) ||
1498 ((tim_intr_config->util_sel > 48) &&
1499 (tim_intr_config->util_sel < 63))) &&
1500 (tim_intr_config->util_sel !=
1501 VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT))
1502 return (VXGE_HAL_BADCFG_TIM_UTIL_SEL);
1504 if ((tim_intr_config->ltimer_val >
1505 VXGE_HAL_MAX_TIM_LTIMER_VAL) &&
1506 (tim_intr_config->ltimer_val !=
1507 VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL))
1508 return (VXGE_HAL_BADCFG_TIM_LTIMER_VAL);
1510 if ((tim_intr_config->txfrm_cnt_en !=
1511 VXGE_HAL_TXFRM_CNT_EN_ENABLE) &&
1512 (tim_intr_config->txfrm_cnt_en !=
1513 VXGE_HAL_TXFRM_CNT_EN_DISABLE) &&
1514 (tim_intr_config->txfrm_cnt_en !=
1515 VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT))
1516 return (VXGE_HAL_BADCFG_TXFRM_CNT_EN);
1518 if ((tim_intr_config->txd_cnt_en !=
1519 VXGE_HAL_TXD_CNT_EN_ENABLE) &&
1520 (tim_intr_config->txd_cnt_en !=
1521 VXGE_HAL_TXD_CNT_EN_DISABLE) &&
1522 (tim_intr_config->txd_cnt_en !=
1523 VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT))
1524 return (VXGE_HAL_BADCFG_TXD_CNT_EN);
1526 if ((tim_intr_config->urange_a >
1527 VXGE_HAL_MAX_TIM_URANGE_A) &&
1528 (tim_intr_config->urange_a !=
1529 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A))
1530 return (VXGE_HAL_BADCFG_TIM_URANGE_A);
1532 if ((tim_intr_config->uec_a >
1533 VXGE_HAL_MAX_TIM_UEC_A) &&
1534 (tim_intr_config->uec_a !=
1535 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A))
1536 return (VXGE_HAL_BADCFG_TIM_UEC_A);
1538 if ((tim_intr_config->urange_b >
1539 VXGE_HAL_MAX_TIM_URANGE_B) &&
1540 (tim_intr_config->urange_b !=
1541 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B))
1542 return (VXGE_HAL_BADCFG_TIM_URANGE_B);
1544 if ((tim_intr_config->uec_b >
1545 VXGE_HAL_MAX_TIM_UEC_B) &&
1546 (tim_intr_config->uec_b !=
1547 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B))
1548 return (VXGE_HAL_BADCFG_TIM_UEC_B);
1550 if ((tim_intr_config->urange_c >
1551 VXGE_HAL_MAX_TIM_URANGE_C) &&
1552 (tim_intr_config->urange_c !=
1553 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C))
1554 return (VXGE_HAL_BADCFG_TIM_URANGE_C);
1556 if ((tim_intr_config->uec_c >
1557 VXGE_HAL_MAX_TIM_UEC_C) &&
1558 (tim_intr_config->uec_c !=
1559 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C))
1560 return (VXGE_HAL_BADCFG_TIM_UEC_C);
1562 if ((tim_intr_config->uec_d >
1563 VXGE_HAL_MAX_TIM_UEC_D) &&
1564 (tim_intr_config->uec_d !=
1565 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D))
1566 return (VXGE_HAL_BADCFG_TIM_UEC_D);
1568 if (((tim_intr_config->ufca_intr_thres <
1569 VXGE_HAL_MIN_UFCA_INTR_THRES) ||
1570 (tim_intr_config->ufca_intr_thres >
1571 VXGE_HAL_MAX_UFCA_INTR_THRES)) &&
1572 (tim_intr_config->ufca_intr_thres !=
1573 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES))
1574 return (VXGE_HAL_BADCFG_UFCA_INTR_THRES);
1576 if (((tim_intr_config->ufca_lo_lim <
1577 VXGE_HAL_MIN_UFCA_LO_LIM) ||
1578 (tim_intr_config->ufca_lo_lim >
1579 VXGE_HAL_MAX_UFCA_LO_LIM)) &&
1580 (tim_intr_config->ufca_lo_lim !=
1581 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM))
1582 return (VXGE_HAL_BADCFG_UFCA_LO_LIM);
1584 if (((tim_intr_config->ufca_hi_lim <
1585 VXGE_HAL_MIN_UFCA_HI_LIM) ||
1586 (tim_intr_config->ufca_hi_lim >
1587 VXGE_HAL_MAX_UFCA_HI_LIM)) &&
1588 (tim_intr_config->ufca_hi_lim !=
1589 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM))
1590 return (VXGE_HAL_BADCFG_UFCA_HI_LIM);
1592 if (((tim_intr_config->ufca_lbolt_period <
1593 VXGE_HAL_MIN_UFCA_LBOLT_PERIOD) ||
1594 (tim_intr_config->ufca_lbolt_period >
1595 VXGE_HAL_MAX_UFCA_LBOLT_PERIOD)) &&
1596 (tim_intr_config->ufca_lbolt_period !=
1597 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD))
1598 return (VXGE_HAL_BADCFG_UFCA_LBOLT_PERIOD);
1600 return (VXGE_HAL_OK);
1604 * __hal_device_vpath_config_check - Check vpath configuration.
1605 * @vp_config: Vpath configuration information
1607 * Check the vpath configuration
1609 * Returns: VXGE_HAL_OK - success,
1610 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1614 __hal_device_vpath_config_check(vxge_hal_vp_config_t *vp_config)
1616 vxge_hal_status_e status;
1618 if (vp_config->vp_id > VXGE_HAL_MAX_VIRTUAL_PATHS)
1619 return (VXGE_HAL_BADCFG_VPATH_ID);
1621 if ((vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT0) &&
1622 (vp_config->wire_port != VXGE_HAL_VPATH_USE_PORT1) &&
1623 (vp_config->wire_port != VXGE_HAL_VPATH_USE_BOTH) &&
1624 (vp_config->wire_port != VXGE_HAL_VPATH_USE_DEFAULT_PORT))
1625 return (VXGE_HAL_BADCFG_VPATH_WIRE_PORT);
1627 if ((vp_config->priority != VXGE_HAL_VPATH_PRIORITY_DEFAULT) &&
1628 (((int)vp_config->priority < VXGE_HAL_VPATH_PRIORITY_MIN) ||
1629 (vp_config->priority > VXGE_HAL_VPATH_PRIORITY_MAX)))
1630 return (VXGE_HAL_BADCFG_VPATH_PRIORITY);
1632 if ((vp_config->bandwidth != VXGE_HAL_VPATH_BW_LIMIT_DEFAULT) &&
1633 ((vp_config->bandwidth < VXGE_HAL_VPATH_BW_LIMIT_MIN) ||
1634 (vp_config->bandwidth > VXGE_HAL_VPATH_BW_LIMIT_MAX)))
1635 return (VXGE_HAL_BADCFG_VPATH_BANDWIDTH_LIMIT);
1637 if ((vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_ENABLE) &&
1638 (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_DISABLE) &&
1639 (vp_config->no_snoop != VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT))
1640 return (VXGE_HAL_BADCFG_VPATH_NO_SNOOP);
1642 status = __hal_device_ring_config_check(&vp_config->ring);
1643 if (status != VXGE_HAL_OK)
1646 status = __hal_device_fifo_config_check(&vp_config->fifo);
1647 if (status != VXGE_HAL_OK)
1651 status = __hal_device_tim_intr_config_check(&vp_config->tti);
1652 if (status != VXGE_HAL_OK)
1655 status = __hal_device_tim_intr_config_check(&vp_config->rti);
1656 if (status != VXGE_HAL_OK)
1659 if ((vp_config->mtu != VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1660 ((vp_config->mtu < VXGE_HAL_VPATH_MIN_INITIAL_MTU) ||
1661 (vp_config->mtu > VXGE_HAL_VPATH_MAX_INITIAL_MTU)))
1662 return (VXGE_HAL_BADCFG_VPATH_MTU);
1664 if ((vp_config->tpa_lsov2_en !=
1665 VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT) &&
1666 (vp_config->tpa_lsov2_en !=
1667 VXGE_HAL_VPATH_TPA_LSOV2_EN_ENABLE) &&
1668 (vp_config->tpa_lsov2_en !=
1669 VXGE_HAL_VPATH_TPA_LSOV2_EN_DISABLE))
1670 return (VXGE_HAL_BADCFG_VPATH_TPA_LSOV2_EN);
1672 if ((vp_config->tpa_ignore_frame_error !=
1673 VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT) &&
1674 (vp_config->tpa_ignore_frame_error !=
1675 VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_ENABLE) &&
1676 (vp_config->tpa_ignore_frame_error !=
1677 VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_DISABLE))
1678 return (VXGE_HAL_BADCFG_VPATH_TPA_IGNORE_FRAME_ERROR);
1680 if ((vp_config->tpa_ipv6_keep_searching !=
1681 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT) &&
1682 (vp_config->tpa_ipv6_keep_searching !=
1683 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_ENABLE) &&
1684 (vp_config->tpa_ipv6_keep_searching !=
1685 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_DISABLE))
1686 return (VXGE_HAL_BADCFG_VPATH_TPA_IPV6_KEEP_SEARCHING);
1688 if ((vp_config->tpa_l4_pshdr_present !=
1689 VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT) &&
1690 (vp_config->tpa_l4_pshdr_present !=
1691 VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_ENABLE) &&
1692 (vp_config->tpa_l4_pshdr_present !=
1693 VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_DISABLE))
1694 return (VXGE_HAL_BADCFG_VPATH_TPA_L4_PSHDR_PRESENT);
1696 if ((vp_config->tpa_support_mobile_ipv6_hdrs !=
1697 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_USE_FLASH_DEFAULT) &&
1698 (vp_config->tpa_support_mobile_ipv6_hdrs !=
1699 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_ENABLE) &&
1700 (vp_config->tpa_support_mobile_ipv6_hdrs !=
1701 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DISABLE))
1702 return (VXGE_HAL_BADCFG_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS);
1704 if ((vp_config->rpa_ipv4_tcp_incl_ph !=
1705 VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT) &&
1706 (vp_config->rpa_ipv4_tcp_incl_ph !=
1707 VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_ENABLE) &&
1708 (vp_config->rpa_ipv4_tcp_incl_ph !=
1709 VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_DISABLE))
1710 return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_TCP_INCL_PH);
1712 if ((vp_config->rpa_ipv6_tcp_incl_ph !=
1713 VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT) &&
1714 (vp_config->rpa_ipv6_tcp_incl_ph !=
1715 VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_ENABLE) &&
1716 (vp_config->rpa_ipv6_tcp_incl_ph !=
1717 VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_DISABLE))
1718 return (VXGE_HAL_BADCFG_VPATH_RPA_IPV6_TCP_INCL_PH);
1720 if ((vp_config->rpa_ipv4_udp_incl_ph !=
1721 VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT) &&
1722 (vp_config->rpa_ipv4_udp_incl_ph !=
1723 VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_ENABLE) &&
1724 (vp_config->rpa_ipv4_udp_incl_ph !=
1725 VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_DISABLE))
1726 return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH);
1728 if ((vp_config->rpa_ipv6_udp_incl_ph !=
1729 VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT) &&
1730 (vp_config->rpa_ipv6_udp_incl_ph !=
1731 VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_ENABLE) &&
1732 (vp_config->rpa_ipv6_udp_incl_ph !=
1733 VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_DISABLE))
1734 return (VXGE_HAL_BADCFG_VPATH_RPA_IPV4_UDP_INCL_PH);
1736 if ((vp_config->rpa_l4_incl_cf !=
1737 VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT) &&
1738 (vp_config->rpa_l4_incl_cf !=
1739 VXGE_HAL_VPATH_RPA_L4_INCL_CF_ENABLE) &&
1740 (vp_config->rpa_l4_incl_cf !=
1741 VXGE_HAL_VPATH_RPA_L4_INCL_CF_DISABLE))
1742 return (VXGE_HAL_BADCFG_VPATH_RPA_L4_INCL_CF);
1744 if ((vp_config->rpa_strip_vlan_tag !=
1745 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1746 (vp_config->rpa_strip_vlan_tag !=
1747 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1748 (vp_config->rpa_strip_vlan_tag !=
1749 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1750 return (VXGE_HAL_BADCFG_VPATH_RPA_STRIP_VLAN_TAG);
1752 if ((vp_config->rpa_l4_comp_csum !=
1753 VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT) &&
1754 (vp_config->rpa_l4_comp_csum !=
1755 VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_ENABLE) &&
1756 (vp_config->rpa_l4_comp_csum !=
1757 VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_DISABLE))
1758 return (VXGE_HAL_BADCFG_VPATH_RPA_L4_COMP_CSUM);
1760 if ((vp_config->rpa_l3_incl_cf !=
1761 VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT) &&
1762 (vp_config->rpa_l3_incl_cf !=
1763 VXGE_HAL_VPATH_RPA_L3_INCL_CF_ENABLE) &&
1764 (vp_config->rpa_l3_incl_cf !=
1765 VXGE_HAL_VPATH_RPA_L3_INCL_CF_DISABLE))
1766 return (VXGE_HAL_BADCFG_VPATH_RPA_L3_INCL_CF);
1768 if ((vp_config->rpa_l3_comp_csum !=
1769 VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT) &&
1770 (vp_config->rpa_l3_comp_csum !=
1771 VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_ENABLE) &&
1772 (vp_config->rpa_l3_comp_csum !=
1773 VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_DISABLE))
1774 return (VXGE_HAL_BADCFG_VPATH_RPA_L3_COMP_CSUM);
1776 if ((vp_config->rpa_ucast_all_addr_en !=
1777 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT) &&
1778 (vp_config->rpa_ucast_all_addr_en !=
1779 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_ENABLE) &&
1780 (vp_config->rpa_ucast_all_addr_en !=
1781 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE))
1782 return (VXGE_HAL_BADCFG_VPATH_RPA_UCAST_ALL_ADDR_EN);
1784 if ((vp_config->rpa_mcast_all_addr_en !=
1785 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT) &&
1786 (vp_config->rpa_mcast_all_addr_en !=
1787 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_ENABLE) &&
1788 (vp_config->rpa_mcast_all_addr_en !=
1789 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_DISABLE))
1790 return (VXGE_HAL_BADCFG_VPATH_RPA_MCAST_ALL_ADDR_EN);
1792 if ((vp_config->rpa_bcast_en !=
1793 VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT) &&
1794 (vp_config->rpa_bcast_en !=
1795 VXGE_HAL_VPATH_RPA_BCAST_ENABLE) &&
1796 (vp_config->rpa_bcast_en !=
1797 VXGE_HAL_VPATH_RPA_BCAST_DISABLE))
1798 return (VXGE_HAL_BADCFG_VPATH_RPA_CAST_EN);
1800 if ((vp_config->rpa_all_vid_en !=
1801 VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT) &&
1802 (vp_config->rpa_all_vid_en !=
1803 VXGE_HAL_VPATH_RPA_ALL_VID_ENABLE) &&
1804 (vp_config->rpa_all_vid_en !=
1805 VXGE_HAL_VPATH_RPA_ALL_VID_DISABLE))
1806 return (VXGE_HAL_BADCFG_VPATH_RPA_ALL_VID_EN);
1808 if ((vp_config->vp_queue_l2_flow !=
1809 VXGE_HAL_VPATH_VP_Q_L2_FLOW_ENABLE) &&
1810 (vp_config->vp_queue_l2_flow !=
1811 VXGE_HAL_VPATH_VP_Q_L2_FLOW_DISABLE) &&
1812 (vp_config->vp_queue_l2_flow !=
1813 VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT))
1814 return (VXGE_HAL_BADCFG_VPATH_VP_Q_L2_FLOW);
1816 return (VXGE_HAL_OK);
1820 * __hal_device_config_check - Check device configuration.
1821 * @new_config: Device configuration information
1823 * Check the device configuration
1825 * Returns: VXGE_HAL_OK - success,
1826 * otherwise one of the vxge_hal_status_e {} enumerated error codes.
1830 __hal_device_config_check(vxge_hal_device_config_t *new_config)
1833 vxge_hal_status_e status;
1835 if (new_config->dma_blockpool_incr <
1836 VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE)
1837 return (VXGE_HAL_BADCFG_BLOCKPOOL_INCR);
1839 if (new_config->dma_blockpool_max <
1840 VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE)
1841 return (VXGE_HAL_BADCFG_BLOCKPOOL_MAX);
1843 if ((status = __hal_mrpcim_config_check(&new_config->mrpcim_config)) !=
1847 if (new_config->isr_polling_cnt > VXGE_HAL_MAX_ISR_POLLING_CNT)
1848 return (VXGE_HAL_BADCFG_ISR_POLLING_CNT);
1850 if ((new_config->max_payload_size >
1851 VXGE_HAL_MAX_PAYLOAD_SIZE_4096) &&
1852 (new_config->max_payload_size !=
1853 VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE))
1854 return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE);
1856 if ((new_config->mmrb_count > VXGE_HAL_MMRB_COUNT_4096) &&
1857 (new_config->mmrb_count != VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT))
1858 return (VXGE_HAL_BADCFG_MAX_PAYLOAD_SIZE);
1860 if (((new_config->stats_refresh_time_sec <
1861 VXGE_HAL_MIN_STATS_REFRESH_TIME) ||
1862 (new_config->stats_refresh_time_sec >
1863 VXGE_HAL_MAX_STATS_REFRESH_TIME)) &&
1864 (new_config->stats_refresh_time_sec !=
1865 VXGE_HAL_STATS_REFRESH_DISABLE))
1866 return (VXGE_HAL_BADCFG_STATS_REFRESH_TIME);
1868 if ((new_config->intr_mode != VXGE_HAL_INTR_MODE_IRQLINE) &&
1869 (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX) &&
1870 (new_config->intr_mode != VXGE_HAL_INTR_MODE_MSIX_ONE_SHOT) &&
1871 (new_config->intr_mode != VXGE_HAL_INTR_MODE_EMULATED_INTA) &&
1872 (new_config->intr_mode != VXGE_HAL_INTR_MODE_DEF))
1873 return (VXGE_HAL_BADCFG_INTR_MODE);
1875 if ((new_config->dump_on_unknown !=
1876 VXGE_HAL_DUMP_ON_UNKNOWN_DISABLE) &&
1877 (new_config->dump_on_unknown !=
1878 VXGE_HAL_DUMP_ON_UNKNOWN_ENABLE))
1879 return (VXGE_HAL_BADCFG_DUMP_ON_UNKNOWN);
1881 if ((new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_DISABLE) &&
1882 (new_config->dump_on_serr != VXGE_HAL_DUMP_ON_SERR_ENABLE))
1883 return (VXGE_HAL_BADCFG_DUMP_ON_SERR);
1885 if ((new_config->dump_on_critical !=
1886 VXGE_HAL_DUMP_ON_CRITICAL_DISABLE) &&
1887 (new_config->dump_on_critical !=
1888 VXGE_HAL_DUMP_ON_CRITICAL_ENABLE))
1889 return (VXGE_HAL_BADCFG_DUMP_ON_CRITICAL);
1891 if ((new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_DISABLE) &&
1892 (new_config->dump_on_eccerr != VXGE_HAL_DUMP_ON_ECCERR_ENABLE))
1893 return (VXGE_HAL_BADCFG_DUMP_ON_ECCERR);
1895 if ((new_config->rth_en != VXGE_HAL_RTH_DISABLE) &&
1896 (new_config->rth_en != VXGE_HAL_RTH_ENABLE))
1897 return (VXGE_HAL_BADCFG_RTH_EN);
1899 if ((new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_SOLO_IT) &&
1900 (new_config->rth_it_type != VXGE_HAL_RTH_IT_TYPE_MULTI_IT))
1901 return (VXGE_HAL_BADCFG_RTH_IT_TYPE);
1903 if ((new_config->rts_mac_en != VXGE_HAL_RTS_MAC_DISABLE) &&
1904 (new_config->rts_mac_en != VXGE_HAL_RTS_MAC_ENABLE))
1905 return (VXGE_HAL_BADCFG_RTS_MAC_EN);
1907 if ((new_config->rts_qos_en != VXGE_HAL_RTS_QOS_DISABLE) &&
1908 (new_config->rts_qos_en != VXGE_HAL_RTS_QOS_ENABLE))
1909 return (VXGE_HAL_BADCFG_RTS_QOS_EN);
1911 if ((new_config->rts_port_en != VXGE_HAL_RTS_PORT_DISABLE) &&
1912 (new_config->rts_port_en != VXGE_HAL_RTS_PORT_ENABLE))
1913 return (VXGE_HAL_BADCFG_RTS_PORT_EN);
1915 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
1916 if ((status = __hal_device_vpath_config_check(
1917 &new_config->vp_config[i])) != VXGE_HAL_OK)
1921 if ((new_config->max_cqe_groups < VXGE_HAL_MIN_MAX_CQE_GROUPS) ||
1922 (new_config->max_cqe_groups > VXGE_HAL_MAX_MAX_CQE_GROUPS))
1923 return (VXGE_HAL_BADCFG_MAX_CQE_GROUPS);
1925 if ((new_config->max_num_wqe_od_groups <
1926 VXGE_HAL_MIN_MAX_NUM_OD_GROUPS) ||
1927 (new_config->max_num_wqe_od_groups >
1928 VXGE_HAL_MAX_MAX_NUM_OD_GROUPS))
1929 return (VXGE_HAL_BADCFG_MAX_NUM_OD_GROUPS);
1931 if ((new_config->no_wqe_threshold < VXGE_HAL_MIN_NO_WQE_THRESHOLD) ||
1932 (new_config->no_wqe_threshold > VXGE_HAL_MAX_NO_WQE_THRESHOLD))
1933 return (VXGE_HAL_BADCFG_NO_WQE_THRESHOLD);
1935 if ((new_config->refill_threshold_high <
1936 VXGE_HAL_MIN_REFILL_THRESHOLD_HIGH) ||
1937 (new_config->refill_threshold_high >
1938 VXGE_HAL_MAX_REFILL_THRESHOLD_HIGH))
1939 return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_HIGH);
1941 if ((new_config->refill_threshold_low <
1942 VXGE_HAL_MIN_REFILL_THRESHOLD_LOW) ||
1943 (new_config->refill_threshold_low >
1944 VXGE_HAL_MAX_REFILL_THRESHOLD_LOW))
1945 return (VXGE_HAL_BADCFG_REFILL_THRESHOLD_LOW);
1947 if ((new_config->ack_blk_limit < VXGE_HAL_MIN_ACK_BLOCK_LIMIT) ||
1948 (new_config->ack_blk_limit > VXGE_HAL_MAX_ACK_BLOCK_LIMIT))
1949 return (VXGE_HAL_BADCFG_ACK_BLOCK_LIMIT);
1951 if ((new_config->stats_read_method !=
1952 VXGE_HAL_STATS_READ_METHOD_DMA) &&
1953 (new_config->stats_read_method !=
1954 VXGE_HAL_STATS_READ_METHOD_PIO))
1955 return (VXGE_HAL_BADCFG_STATS_READ_METHOD);
1957 if ((new_config->poll_or_doorbell !=
1958 VXGE_HAL_POLL_OR_DOORBELL_POLL) &&
1959 (new_config->poll_or_doorbell !=
1960 VXGE_HAL_POLL_OR_DOORBELL_DOORBELL))
1961 return (VXGE_HAL_BADCFG_POLL_OR_DOOR_BELL);
1963 if ((new_config->device_poll_millis <
1964 VXGE_HAL_MIN_DEVICE_POLL_MILLIS) ||
1965 (new_config->device_poll_millis >
1966 VXGE_HAL_MAX_DEVICE_POLL_MILLIS))
1967 return (VXGE_HAL_BADCFG_DEVICE_POLL_MILLIS);
1970 return (VXGE_HAL_OK);
1974 * vxge_hal_device_config_default_get - Initialize device config with defaults.
1975 * @device_config: Configuration structure to be initialized,
1976 * For the X3100 configuration "knobs" please
1977 * refer to vxge_hal_device_config_t and X3100
1980 * Initialize X3100 device config with default values.
1982 * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(),
1983 * vxge_hal_status_e {} vxge_hal_device_attr_t {}.
1986 vxge_hal_device_config_default_get(
1987 vxge_hal_device_config_t *device_config)
1990 vxge_hal_mac_config_t *mac_config;
1991 vxge_hal_wire_port_config_t *wire_port_config;
1992 vxge_hal_switch_port_config_t *switch_port_config;
1994 vxge_hal_trace_log_driver("==> %s:%s:%d",
1995 __FILE__, __func__, __LINE__);
1997 vxge_hal_trace_log_driver("device_config = 0x"VXGE_OS_STXFMT,
1998 (ptr_t) device_config);
2000 device_config->dma_blockpool_min = VXGE_HAL_MIN_DMA_BLOCK_POOL_SIZE;
2001 device_config->dma_blockpool_initial =
2002 VXGE_HAL_INITIAL_DMA_BLOCK_POOL_SIZE;
2003 device_config->dma_blockpool_incr = VXGE_HAL_INCR_DMA_BLOCK_POOL_SIZE;
2004 device_config->dma_blockpool_max = VXGE_HAL_MAX_DMA_BLOCK_POOL_SIZE;
2006 mac_config = &device_config->mrpcim_config.mac_config;
2008 for (i = 0; i < VXGE_HAL_MAC_MAX_WIRE_PORTS; i++) {
2010 wire_port_config = &mac_config->wire_port_config[i];
2012 wire_port_config->port_id = i;
2014 wire_port_config->media = VXGE_HAL_WIRE_PORT_MEDIA_DEFAULT;
2016 wire_port_config->mtu = VXGE_HAL_WIRE_PORT_DEF_INITIAL_MTU;
2018 wire_port_config->autoneg_mode =
2019 VXGE_HAL_WIRE_PORT_AUTONEG_MODE_DEFAULT;
2021 wire_port_config->autoneg_rate =
2022 VXGE_HAL_WIRE_PORT_AUTONEG_RATE_DEFAULT;
2024 wire_port_config->fixed_use_fsm =
2025 VXGE_HAL_WIRE_PORT_FIXED_USE_FSM_DEFAULT;
2027 wire_port_config->antp_use_fsm =
2028 VXGE_HAL_WIRE_PORT_ANTP_USE_FSM_DEFAULT;
2030 wire_port_config->anbe_use_fsm =
2031 VXGE_HAL_WIRE_PORT_ANBE_USE_FSM_DEFAULT;
2033 wire_port_config->link_stability_period =
2034 VXGE_HAL_WIRE_PORT_DEF_LINK_STABILITY_PERIOD;
2036 wire_port_config->port_stability_period =
2037 VXGE_HAL_WIRE_PORT_DEF_PORT_STABILITY_PERIOD;
2039 wire_port_config->tmac_en =
2040 VXGE_HAL_WIRE_PORT_TMAC_DEFAULT;
2042 wire_port_config->rmac_en =
2043 VXGE_HAL_WIRE_PORT_RMAC_DEFAULT;
2045 wire_port_config->tmac_pad =
2046 VXGE_HAL_WIRE_PORT_TMAC_PAD_DEFAULT;
2048 wire_port_config->tmac_pad_byte =
2049 VXGE_HAL_WIRE_PORT_DEF_TMAC_PAD_BYTE;
2051 wire_port_config->tmac_util_period =
2052 VXGE_HAL_WIRE_PORT_DEF_TMAC_UTIL_PERIOD;
2054 wire_port_config->rmac_strip_fcs =
2055 VXGE_HAL_WIRE_PORT_RMAC_STRIP_FCS_DEFAULT;
2057 wire_port_config->rmac_prom_en =
2058 VXGE_HAL_WIRE_PORT_RMAC_PROM_EN_DEFAULT;
2060 wire_port_config->rmac_discard_pfrm =
2061 VXGE_HAL_WIRE_PORT_RMAC_DISCARD_PFRM_DEFAULT;
2063 wire_port_config->rmac_util_period =
2064 VXGE_HAL_WIRE_PORT_DEF_RMAC_UTIL_PERIOD;
2066 wire_port_config->rmac_pause_gen_en =
2067 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_GEN_EN_DEFAULT;
2069 wire_port_config->rmac_pause_rcv_en =
2070 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_RCV_EN_DEFAULT;
2072 wire_port_config->rmac_pause_time =
2073 VXGE_HAL_WIRE_PORT_DEF_RMAC_HIGH_PTIME;
2075 wire_port_config->limiter_en =
2076 VXGE_HAL_WIRE_PORT_RMAC_PAUSE_LIMITER_DEFAULT;
2078 wire_port_config->max_limit =
2079 VXGE_HAL_WIRE_PORT_DEF_RMAC_MAX_LIMIT;
2082 switch_port_config = &mac_config->switch_port_config;
2084 switch_port_config->mtu =
2085 VXGE_HAL_SWITCH_PORT_DEF_INITIAL_MTU;
2087 switch_port_config->tmac_en =
2088 VXGE_HAL_SWITCH_PORT_TMAC_DEFAULT;
2090 switch_port_config->rmac_en =
2091 VXGE_HAL_SWITCH_PORT_RMAC_DEFAULT;
2093 switch_port_config->tmac_pad =
2094 VXGE_HAL_SWITCH_PORT_TMAC_PAD_DEFAULT;
2096 switch_port_config->tmac_pad_byte =
2097 VXGE_HAL_SWITCH_PORT_DEF_TMAC_PAD_BYTE;
2099 switch_port_config->tmac_util_period =
2100 VXGE_HAL_SWITCH_PORT_DEF_TMAC_UTIL_PERIOD;
2102 switch_port_config->rmac_strip_fcs =
2103 VXGE_HAL_SWITCH_PORT_RMAC_STRIP_FCS_DEFAULT;
2105 switch_port_config->rmac_prom_en =
2106 VXGE_HAL_SWITCH_PORT_RMAC_PROM_EN_DEFAULT;
2108 switch_port_config->rmac_discard_pfrm =
2109 VXGE_HAL_SWITCH_PORT_RMAC_DISCARD_PFRM_DEFAULT;
2111 switch_port_config->rmac_util_period =
2112 VXGE_HAL_SWITCH_PORT_DEF_RMAC_UTIL_PERIOD;
2114 switch_port_config->rmac_pause_gen_en =
2115 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_GEN_EN_DEFAULT;
2117 switch_port_config->rmac_pause_rcv_en =
2118 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_RCV_EN_DEFAULT;
2120 switch_port_config->rmac_pause_time =
2121 VXGE_HAL_SWITCH_PORT_DEF_RMAC_HIGH_PTIME;
2123 switch_port_config->limiter_en =
2124 VXGE_HAL_SWITCH_PORT_RMAC_PAUSE_LIMITER_DEFAULT;
2126 switch_port_config->max_limit =
2127 VXGE_HAL_SWITCH_PORT_DEF_RMAC_MAX_LIMIT;
2129 mac_config->network_stability_period =
2130 VXGE_HAL_MAC_DEF_NETWORK_STABILITY_PERIOD;
2132 for (i = 0; i < 16; i++) {
2134 mac_config->mc_pause_threshold[i] =
2135 VXGE_HAL_MAC_DEF_MC_PAUSE_THRESHOLD;
2139 mac_config->tmac_perma_stop_en =
2140 VXGE_HAL_MAC_TMAC_PERMA_STOP_DEFAULT;
2142 mac_config->tmac_tx_switch_dis =
2143 VXGE_HAL_MAC_TMAC_TX_SWITCH_DEFAULT;
2145 mac_config->tmac_lossy_switch_en =
2146 VXGE_HAL_MAC_TMAC_LOSSY_SWITCH_DEFAULT;
2148 mac_config->tmac_lossy_wire_en =
2149 VXGE_HAL_MAC_TMAC_LOSSY_WIRE_DEFAULT;
2151 mac_config->tmac_bcast_to_wire_dis =
2152 VXGE_HAL_MAC_TMAC_BCAST_TO_WIRE_DEFAULT;
2154 mac_config->tmac_bcast_to_switch_dis =
2155 VXGE_HAL_MAC_TMAC_BCAST_TO_SWITCH_DEFAULT;
2157 mac_config->tmac_host_append_fcs_en =
2158 VXGE_HAL_MAC_TMAC_HOST_APPEND_FCS_DEFAULT;
2160 mac_config->tpa_support_snap_ab_n =
2161 VXGE_HAL_MAC_TPA_SUPPORT_SNAP_AB_N_DEFAULT;
2163 mac_config->tpa_ecc_enable_n =
2164 VXGE_HAL_MAC_TPA_ECC_ENABLE_N_DEFAULT;
2166 mac_config->rpa_ignore_frame_err =
2167 VXGE_HAL_MAC_RPA_IGNORE_FRAME_ERR_DEFAULT;
2169 mac_config->rpa_support_snap_ab_n =
2170 VXGE_HAL_MAC_RPA_SUPPORT_SNAP_AB_N_DEFAULT;
2172 mac_config->rpa_search_for_hao =
2173 VXGE_HAL_MAC_RPA_SEARCH_FOR_HAO_DEFAULT;
2175 mac_config->rpa_support_ipv6_mobile_hdrs =
2176 VXGE_HAL_MAC_RPA_SUPPORT_IPV6_MOBILE_HDRS_DEFAULT;
2178 mac_config->rpa_ipv6_stop_searching =
2179 VXGE_HAL_MAC_RPA_IPV6_STOP_SEARCHING_DEFAULT;
2181 mac_config->rpa_no_ps_if_unknown =
2182 VXGE_HAL_MAC_RPA_NO_PS_IF_UNKNOWN_DEFAULT;
2184 mac_config->rpa_search_for_etype =
2185 VXGE_HAL_MAC_RPA_SEARCH_FOR_ETYPE_DEFAULT;
2187 mac_config->rpa_repl_l4_comp_csum =
2188 VXGE_HAL_MAC_RPA_REPL_l4_COMP_CSUM_DEFAULT;
2190 mac_config->rpa_repl_l3_incl_cf =
2191 VXGE_HAL_MAC_RPA_REPL_L3_INCL_CF_DEFAULT;
2193 mac_config->rpa_repl_l3_comp_csum =
2194 VXGE_HAL_MAC_RPA_REPL_l3_COMP_CSUM_DEFAULT;
2196 mac_config->rpa_repl_ipv4_tcp_incl_ph =
2197 VXGE_HAL_MAC_RPA_REPL_IPV4_TCP_INCL_PH_DEFAULT;
2199 mac_config->rpa_repl_ipv6_tcp_incl_ph =
2200 VXGE_HAL_MAC_RPA_REPL_IPV6_TCP_INCL_PH_DEFAULT;
2202 mac_config->rpa_repl_ipv4_udp_incl_ph =
2203 VXGE_HAL_MAC_RPA_REPL_IPV4_UDP_INCL_PH_DEFAULT;
2205 mac_config->rpa_repl_ipv6_udp_incl_ph =
2206 VXGE_HAL_MAC_RPA_REPL_IPV6_UDP_INCL_PH_DEFAULT;
2208 mac_config->rpa_repl_l4_incl_cf =
2209 VXGE_HAL_MAC_RPA_REPL_L4_INCL_CF_DEFAULT;
2211 mac_config->rpa_repl_strip_vlan_tag =
2212 VXGE_HAL_MAC_RPA_REPL_STRIP_VLAN_TAG_DEFAULT;
2214 device_config->mrpcim_config.lag_config.lag_en =
2215 VXGE_HAL_LAG_LAG_EN_DEFAULT;
2217 device_config->mrpcim_config.lag_config.lag_mode =
2218 VXGE_HAL_LAG_LAG_MODE_DEFAULT;
2220 device_config->mrpcim_config.lag_config.la_mode_config.tx_discard =
2221 VXGE_HAL_LAG_TX_DISCARD_DEFAULT;
2223 device_config->mrpcim_config.lag_config.la_mode_config.distrib_alg_sel =
2224 VXGE_HAL_LAG_DISTRIB_ALG_SEL_DEFAULT;
2226 device_config->mrpcim_config.lag_config.la_mode_config.distrib_dest =
2227 VXGE_HAL_LAG_DISTRIB_DEST_DEFAULT;
2230 mrpcim_config.lag_config.la_mode_config.distrib_remap_if_fail =
2231 VXGE_HAL_LAG_DISTRIB_REMAP_IF_FAIL_DEFAULT;
2233 device_config->mrpcim_config.lag_config.la_mode_config.coll_max_delay =
2234 VXGE_HAL_LAG_DEF_COLL_MAX_DELAY;
2236 device_config->mrpcim_config.lag_config.la_mode_config.rx_discard =
2237 VXGE_HAL_LAG_RX_DISCARD_DEFAULT;
2239 device_config->mrpcim_config.lag_config.ap_mode_config.hot_standby =
2240 VXGE_HAL_LAG_HOT_STANDBY_DEFAULT;
2242 device_config->mrpcim_config.lag_config.ap_mode_config.lacp_decides =
2243 VXGE_HAL_LAG_LACP_DECIDES_DEFAULT;
2246 mrpcim_config.lag_config.ap_mode_config.pref_active_port =
2247 VXGE_HAL_LAG_PREF_ACTIVE_PORT_DEFAULT;
2249 device_config->mrpcim_config.lag_config.ap_mode_config.auto_failback =
2250 VXGE_HAL_LAG_AUTO_FAILBACK_DEFAULT;
2252 device_config->mrpcim_config.lag_config.ap_mode_config.failback_en =
2253 VXGE_HAL_LAG_FAILBACK_EN_DEFAULT;
2256 mrpcim_config.lag_config.ap_mode_config.cold_failover_timeout =
2257 VXGE_HAL_LAG_DEF_COLD_FAILOVER_TIMEOUT;
2259 device_config->mrpcim_config.lag_config.ap_mode_config.alt_admin_key =
2260 VXGE_HAL_LAG_DEF_ALT_ADMIN_KEY;
2262 device_config->mrpcim_config.lag_config.ap_mode_config.alt_aggr =
2263 VXGE_HAL_LAG_ALT_AGGR_DEFAULT;
2265 device_config->mrpcim_config.lag_config.sl_mode_config.pref_indiv_port =
2266 VXGE_HAL_LAG_PREF_INDIV_PORT_DEFAULT;
2268 device_config->mrpcim_config.lag_config.lacp_config.lacp_en =
2269 VXGE_HAL_LAG_LACP_EN_DEFAULT;
2271 device_config->mrpcim_config.lag_config.lacp_config.lacp_begin =
2272 VXGE_HAL_LAG_LACP_BEGIN_DEFAULT;
2274 device_config->mrpcim_config.lag_config.lacp_config.discard_lacp =
2275 VXGE_HAL_LAG_DISCARD_LACP_DEFAULT;
2277 device_config->mrpcim_config.lag_config.lacp_config.liberal_len_chk =
2278 VXGE_HAL_LAG_LIBERAL_LEN_CHK_DEFAULT;
2280 device_config->mrpcim_config.lag_config.lacp_config.marker_gen_recv_en =
2281 VXGE_HAL_LAG_MARKER_GEN_RECV_EN_DEFAULT;
2283 device_config->mrpcim_config.lag_config.lacp_config.marker_resp_en =
2284 VXGE_HAL_LAG_MARKER_RESP_EN_DEFAULT;
2287 mrpcim_config.lag_config.lacp_config.marker_resp_timeout =
2288 VXGE_HAL_LAG_DEF_MARKER_RESP_TIMEOUT;
2291 mrpcim_config.lag_config.lacp_config.slow_proto_mrkr_min_interval =
2292 VXGE_HAL_LAG_DEF_SLOW_PROTO_MRKR_MIN_INTERVAL;
2294 device_config->mrpcim_config.lag_config.lacp_config.throttle_mrkr_resp =
2295 VXGE_HAL_LAG_THROTTLE_MRKR_RESP_DEFAULT;
2297 device_config->mrpcim_config.lag_config.incr_tx_aggr_stats =
2298 VXGE_HAL_LAG_INCR_TX_AGGR_STATS_DEFAULT;
2300 for (i = 0; i < VXGE_HAL_LAG_PORT_MAX_PORTS; i++) {
2302 vxge_hal_lag_port_config_t *port_config =
2303 &device_config->mrpcim_config.lag_config.port_config[i];
2305 port_config->port_id = i;
2307 port_config->lag_en = VXGE_HAL_LAG_PORT_LAG_EN_DEFAULT;
2309 port_config->discard_slow_proto =
2310 VXGE_HAL_LAG_PORT_DISCARD_SLOW_PROTO_DEFAULT;
2312 port_config->host_chosen_aggr =
2313 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT;
2315 port_config->host_chosen_aggr =
2316 VXGE_HAL_LAG_PORT_HOST_CHOSEN_AGGR_DEFAULT;
2318 port_config->discard_unknown_slow_proto =
2319 VXGE_HAL_LAG_PORT_DISCARD_UNKNOWN_SLOW_PROTO_DEFAULT;
2321 port_config->actor_port_num =
2322 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_NUM;
2324 port_config->actor_port_priority =
2325 VXGE_HAL_LAG_PORT_DEF_ACTOR_PORT_PRIORITY;
2327 port_config->actor_key_10g =
2328 VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_10G;
2330 port_config->actor_key_1g =
2331 VXGE_HAL_LAG_PORT_DEF_ACTOR_KEY_1G;
2333 port_config->actor_lacp_activity =
2334 VXGE_HAL_LAG_PORT_ACTOR_LACP_ACTIVITY_DEFAULT;
2336 port_config->actor_lacp_timeout =
2337 VXGE_HAL_LAG_PORT_ACTOR_LACP_TIMEOUT_DEFAULT;
2339 port_config->actor_aggregation =
2340 VXGE_HAL_LAG_PORT_ACTOR_AGGREGATION_DEFAULT;
2342 port_config->actor_synchronization =
2343 VXGE_HAL_LAG_PORT_ACTOR_SYNCHRONIZATION_DEFAULT;
2345 port_config->actor_collecting =
2346 VXGE_HAL_LAG_PORT_ACTOR_COLLECTING_DEFAULT;
2348 port_config->actor_distributing =
2349 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT;
2351 port_config->actor_distributing =
2352 VXGE_HAL_LAG_PORT_ACTOR_DISTRIBUTING_DEFAULT;
2354 port_config->actor_defaulted =
2355 VXGE_HAL_LAG_PORT_ACTOR_DEFAULTED_DEFAULT;
2357 port_config->actor_expired =
2358 VXGE_HAL_LAG_PORT_ACTOR_EXPIRED_DEFAULT;
2360 port_config->partner_sys_pri =
2361 VXGE_HAL_LAG_PORT_DEF_PARTNER_SYS_PRI;
2363 port_config->partner_key =
2364 VXGE_HAL_LAG_PORT_DEF_PARTNER_KEY;
2366 port_config->partner_port_num =
2367 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_NUM;
2369 port_config->partner_port_priority =
2370 VXGE_HAL_LAG_PORT_DEF_PARTNER_PORT_PRIORITY;
2372 port_config->partner_lacp_activity =
2373 VXGE_HAL_LAG_PORT_PARTNER_LACP_ACTIVITY_DEFAULT;
2375 port_config->partner_lacp_timeout =
2376 VXGE_HAL_LAG_PORT_PARTNER_LACP_TIMEOUT_DEFAULT;
2378 port_config->partner_aggregation =
2379 VXGE_HAL_LAG_PORT_PARTNER_AGGREGATION_DEFAULT;
2381 port_config->partner_synchronization =
2382 VXGE_HAL_LAG_PORT_PARTNER_SYNCHRONIZATION_DEFAULT;
2384 port_config->partner_collecting =
2385 VXGE_HAL_LAG_PORT_PARTNER_COLLECTING_DEFAULT;
2387 port_config->partner_distributing =
2388 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT;
2390 port_config->partner_distributing =
2391 VXGE_HAL_LAG_PORT_PARTNER_DISTRIBUTING_DEFAULT;
2393 port_config->partner_defaulted =
2394 VXGE_HAL_LAG_PORT_PARTNER_DEFAULTED_DEFAULT;
2396 port_config->partner_expired =
2397 VXGE_HAL_LAG_PORT_PARTNER_EXPIRED_DEFAULT;
2401 for (i = 0; i < VXGE_HAL_LAG_AGGR_MAX_PORTS; i++) {
2404 mrpcim_config.lag_config.aggr_config[i].aggr_id = i + 1;
2407 mrpcim_config.lag_config.aggr_config[i].use_port_mac_addr =
2408 VXGE_HAL_LAG_AGGR_USE_PORT_MAC_ADDR_DEFAULT;
2411 mrpcim_config.lag_config.aggr_config[i].mac_addr_sel =
2412 VXGE_HAL_LAG_AGGR_MAC_ADDR_SEL_DEFAULT;
2415 mrpcim_config.lag_config.aggr_config[i].admin_key =
2416 VXGE_HAL_LAG_AGGR_DEF_ADMIN_KEY;
2420 device_config->mrpcim_config.lag_config.sys_pri =
2421 VXGE_HAL_LAG_DEF_SYS_PRI;
2423 device_config->mrpcim_config.lag_config.use_port_mac_addr =
2424 VXGE_HAL_LAG_USE_PORT_MAC_ADDR_DEFAULT;
2426 device_config->mrpcim_config.lag_config.mac_addr_sel =
2427 VXGE_HAL_LAG_MAC_ADDR_SEL_DEFAULT;
2429 device_config->mrpcim_config.lag_config.fast_per_time =
2430 VXGE_HAL_LAG_DEF_FAST_PER_TIME;
2432 device_config->mrpcim_config.lag_config.slow_per_time =
2433 VXGE_HAL_LAG_DEF_SLOW_PER_TIME;
2435 device_config->mrpcim_config.lag_config.short_timeout =
2436 VXGE_HAL_LAG_DEF_SHORT_TIMEOUT;
2438 device_config->mrpcim_config.lag_config.long_timeout =
2439 VXGE_HAL_LAG_DEF_LONG_TIMEOUT;
2441 device_config->mrpcim_config.lag_config.churn_det_time =
2442 VXGE_HAL_LAG_DEF_CHURN_DET_TIME;
2444 device_config->mrpcim_config.lag_config.aggr_wait_time =
2445 VXGE_HAL_LAG_DEF_AGGR_WAIT_TIME;
2447 device_config->mrpcim_config.lag_config.short_timer_scale =
2448 VXGE_HAL_LAG_SHORT_TIMER_SCALE_DEFAULT;
2450 device_config->mrpcim_config.lag_config.long_timer_scale =
2451 VXGE_HAL_LAG_LONG_TIMER_SCALE_DEFAULT;
2453 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
2455 device_config->mrpcim_config.vp_qos[i].priority =
2456 VXGE_HAL_VPATH_QOS_PRIORITY_DEFAULT;
2458 device_config->mrpcim_config.vp_qos[i].min_bandwidth =
2459 VXGE_HAL_VPATH_QOS_MIN_BANDWIDTH_DEFAULT;
2461 device_config->mrpcim_config.vp_qos[i].max_bandwidth =
2462 VXGE_HAL_VPATH_QOS_MAX_BANDWIDTH_DEFAULT;
2466 device_config->isr_polling_cnt = VXGE_HAL_DEF_ISR_POLLING_CNT;
2468 device_config->max_payload_size =
2469 VXGE_HAL_USE_BIOS_DEFAULT_PAYLOAD_SIZE;
2471 device_config->mmrb_count = VXGE_HAL_USE_BIOS_DEFAULT_MMRB_COUNT;
2473 device_config->stats_refresh_time_sec =
2474 VXGE_HAL_USE_FLASH_DEFAULT_STATS_REFRESH_TIME;
2476 device_config->intr_mode = VXGE_HAL_INTR_MODE_DEF;
2478 device_config->dump_on_unknown = VXGE_HAL_DUMP_ON_UNKNOWN_DEFAULT;
2480 device_config->dump_on_serr = VXGE_HAL_DUMP_ON_SERR_DEFAULT;
2482 device_config->dump_on_critical = VXGE_HAL_DUMP_ON_CRITICAL_DEFAULT;
2484 device_config->dump_on_eccerr = VXGE_HAL_DUMP_ON_ECCERR_DEFAULT;
2486 device_config->rth_en = VXGE_HAL_RTH_DEFAULT;
2488 device_config->rth_it_type = VXGE_HAL_RTH_IT_TYPE_DEFAULT;
2490 device_config->device_poll_millis = VXGE_HAL_DEF_DEVICE_POLL_MILLIS;
2492 device_config->rts_mac_en = VXGE_HAL_RTS_MAC_DEFAULT;
2494 device_config->rts_qos_en = VXGE_HAL_RTS_QOS_DEFAULT;
2496 device_config->rts_port_en = VXGE_HAL_RTS_PORT_DEFAULT;
2498 for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
2500 device_config->vp_config[i].vp_id = i;
2502 device_config->vp_config[i].wire_port =
2503 VXGE_HAL_VPATH_USE_DEFAULT_PORT;
2505 device_config->vp_config[i].priority =
2506 VXGE_HAL_VPATH_PRIORITY_DEFAULT;
2508 device_config->vp_config[i].bandwidth =
2509 VXGE_HAL_VPATH_BW_LIMIT_DEFAULT;
2511 device_config->vp_config[i].no_snoop =
2512 VXGE_HAL_VPATH_NO_SNOOP_USE_FLASH_DEFAULT;
2514 device_config->vp_config[i].ring.enable =
2515 VXGE_HAL_RING_DEFAULT;
2517 device_config->vp_config[i].ring.ring_length =
2518 VXGE_HAL_DEF_RING_LENGTH;
2520 device_config->vp_config[i].ring.buffer_mode =
2521 VXGE_HAL_RING_RXD_BUFFER_MODE_DEFAULT;
2523 device_config->vp_config[i].ring.scatter_mode =
2524 VXGE_HAL_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2526 device_config->vp_config[i].ring.post_mode =
2527 VXGE_HAL_RING_POST_MODE_USE_FLASH_DEFAULT;
2529 device_config->vp_config[i].ring.max_frm_len =
2530 VXGE_HAL_MAX_RING_FRM_LEN_USE_MTU;
2532 device_config->vp_config[i].ring.no_snoop_bits =
2533 VXGE_HAL_RING_NO_SNOOP_USE_FLASH_DEFAULT;
2535 device_config->vp_config[i].ring.rx_timer_val =
2536 VXGE_HAL_RING_USE_FLASH_DEFAULT_RX_TIMER_VAL;
2538 device_config->vp_config[i].ring.greedy_return =
2539 VXGE_HAL_RING_GREEDY_RETURN_USE_FLASH_DEFAULT;
2541 device_config->vp_config[i].ring.rx_timer_ci =
2542 VXGE_HAL_RING_RX_TIMER_CI_USE_FLASH_DEFAULT;
2544 device_config->vp_config[i].ring.backoff_interval_us =
2545 VXGE_HAL_USE_FLASH_DEFAULT_BACKOFF_INTERVAL_US;
2547 device_config->vp_config[i].ring.indicate_max_pkts =
2548 VXGE_HAL_DEF_RING_INDICATE_MAX_PKTS;
2551 device_config->vp_config[i].fifo.enable =
2552 VXGE_HAL_FIFO_DEFAULT;
2554 device_config->vp_config[i].fifo.fifo_length =
2555 VXGE_HAL_DEF_FIFO_LENGTH;
2557 device_config->vp_config[i].fifo.max_frags =
2558 VXGE_HAL_DEF_FIFO_FRAGS;
2560 device_config->vp_config[i].fifo.alignment_size =
2561 VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE;
2563 device_config->vp_config[i].fifo.max_aligned_frags = 0;
2565 device_config->vp_config[i].fifo.intr =
2566 VXGE_HAL_FIFO_QUEUE_INTR_DEFAULT;
2568 device_config->vp_config[i].fifo.no_snoop_bits =
2569 VXGE_HAL_FIFO_NO_SNOOP_DEFAULT;
2572 device_config->vp_config[i].tti.intr_enable =
2573 VXGE_HAL_TIM_INTR_DEFAULT;
2575 device_config->vp_config[i].tti.btimer_val =
2576 VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL;
2578 device_config->vp_config[i].tti.timer_ac_en =
2579 VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT;
2581 device_config->vp_config[i].tti.timer_ci_en =
2582 VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT;
2584 device_config->vp_config[i].tti.timer_ri_en =
2585 VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT;
2587 device_config->vp_config[i].tti.rtimer_event_sf =
2588 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF;
2590 device_config->vp_config[i].tti.rtimer_val =
2591 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL;
2593 device_config->vp_config[i].tti.util_sel =
2594 VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT;
2596 device_config->vp_config[i].tti.ltimer_val =
2597 VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL;
2599 device_config->vp_config[i].tti.txfrm_cnt_en =
2600 VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT;
2602 device_config->vp_config[i].tti.txd_cnt_en =
2603 VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT;
2605 device_config->vp_config[i].tti.urange_a =
2606 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A;
2608 device_config->vp_config[i].tti.uec_a =
2609 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A;
2611 device_config->vp_config[i].tti.urange_b =
2612 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B;
2614 device_config->vp_config[i].tti.uec_b =
2615 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B;
2617 device_config->vp_config[i].tti.urange_c =
2618 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C;
2620 device_config->vp_config[i].tti.uec_c =
2621 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C;
2623 device_config->vp_config[i].tti.uec_d =
2624 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D;
2626 device_config->vp_config[i].tti.ufca_intr_thres =
2627 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES;
2629 device_config->vp_config[i].tti.ufca_lo_lim =
2630 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM;
2632 device_config->vp_config[i].tti.ufca_hi_lim =
2633 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM;
2635 device_config->vp_config[i].tti.ufca_lbolt_period =
2636 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD;
2638 device_config->vp_config[i].rti.intr_enable =
2639 VXGE_HAL_TIM_INTR_DEFAULT;
2641 device_config->vp_config[i].rti.btimer_val =
2642 VXGE_HAL_USE_FLASH_DEFAULT_TIM_BTIMER_VAL;
2644 device_config->vp_config[i].rti.timer_ac_en =
2645 VXGE_HAL_TIM_TIMER_AC_USE_FLASH_DEFAULT;
2647 device_config->vp_config[i].rti.timer_ci_en =
2648 VXGE_HAL_TIM_TIMER_CI_USE_FLASH_DEFAULT;
2650 device_config->vp_config[i].rti.timer_ri_en =
2651 VXGE_HAL_TIM_TIMER_RI_USE_FLASH_DEFAULT;
2653 device_config->vp_config[i].rti.rtimer_event_sf =
2654 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_EVENT_SF;
2656 device_config->vp_config[i].rti.rtimer_val =
2657 VXGE_HAL_USE_FLASH_DEFAULT_TIM_RTIMER_VAL;
2659 device_config->vp_config[i].rti.util_sel =
2660 VXGE_HAL_TIM_UTIL_SEL_USE_FLASH_DEFAULT;
2662 device_config->vp_config[i].rti.ltimer_val =
2663 VXGE_HAL_USE_FLASH_DEFAULT_TIM_LTIMER_VAL;
2665 device_config->vp_config[i].rti.txfrm_cnt_en =
2666 VXGE_HAL_TXFRM_CNT_EN_USE_FLASH_DEFAULT;
2668 device_config->vp_config[i].rti.txd_cnt_en =
2669 VXGE_HAL_TXD_CNT_EN_USE_FLASH_DEFAULT;
2671 device_config->vp_config[i].rti.urange_a =
2672 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_A;
2674 device_config->vp_config[i].rti.uec_a =
2675 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_A;
2677 device_config->vp_config[i].rti.urange_b =
2678 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_B;
2680 device_config->vp_config[i].rti.uec_b =
2681 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_B;
2683 device_config->vp_config[i].rti.urange_c =
2684 VXGE_HAL_USE_FLASH_DEFAULT_TIM_URANGE_C;
2686 device_config->vp_config[i].rti.uec_c =
2687 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_C;
2689 device_config->vp_config[i].rti.uec_d =
2690 VXGE_HAL_USE_FLASH_DEFAULT_TIM_UEC_D;
2692 device_config->vp_config[i].rti.ufca_intr_thres =
2693 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_INTR_THRES;
2695 device_config->vp_config[i].rti.ufca_lo_lim =
2696 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LO_LIM;
2698 device_config->vp_config[i].rti.ufca_hi_lim =
2699 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_HI_LIM;
2701 device_config->vp_config[i].rti.ufca_lbolt_period =
2702 VXGE_HAL_USE_FLASH_DEFAULT_UFCA_LBOLT_PERIOD;
2704 device_config->vp_config[i].mtu =
2705 VXGE_HAL_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
2707 device_config->vp_config[i].tpa_lsov2_en =
2708 VXGE_HAL_VPATH_TPA_LSOV2_EN_USE_FLASH_DEFAULT;
2710 device_config->vp_config[i].tpa_ignore_frame_error =
2711 VXGE_HAL_VPATH_TPA_IGNORE_FRAME_ERROR_USE_FLASH_DEFAULT;
2713 device_config->vp_config[i].tpa_ipv6_keep_searching =
2714 VXGE_HAL_VPATH_TPA_IPV6_KEEP_SEARCHING_USE_FLASH_DEFAULT;
2716 device_config->vp_config[i].tpa_l4_pshdr_present =
2717 VXGE_HAL_VPATH_TPA_L4_PSHDR_PRESENT_USE_FLASH_DEFAULT;
2719 device_config->vp_config[i].tpa_support_mobile_ipv6_hdrs =
2720 VXGE_HAL_VPATH_TPA_SUPPORT_MOBILE_IPV6_HDRS_DEFAULT;
2722 device_config->vp_config[i].rpa_ipv4_tcp_incl_ph =
2723 VXGE_HAL_VPATH_RPA_IPV4_TCP_INCL_PH_USE_FLASH_DEFAULT;
2725 device_config->vp_config[i].rpa_ipv6_tcp_incl_ph =
2726 VXGE_HAL_VPATH_RPA_IPV6_TCP_INCL_PH_USE_FLASH_DEFAULT;
2728 device_config->vp_config[i].rpa_ipv4_udp_incl_ph =
2729 VXGE_HAL_VPATH_RPA_IPV4_UDP_INCL_PH_USE_FLASH_DEFAULT;
2731 device_config->vp_config[i].rpa_ipv6_udp_incl_ph =
2732 VXGE_HAL_VPATH_RPA_IPV6_UDP_INCL_PH_USE_FLASH_DEFAULT;
2734 device_config->vp_config[i].rpa_l4_incl_cf =
2735 VXGE_HAL_VPATH_RPA_L4_INCL_CF_USE_FLASH_DEFAULT;
2737 device_config->vp_config[i].rpa_strip_vlan_tag =
2738 VXGE_HAL_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
2740 device_config->vp_config[i].rpa_l4_comp_csum =
2741 VXGE_HAL_VPATH_RPA_L4_COMP_CSUM_USE_FLASH_DEFAULT;
2743 device_config->vp_config[i].rpa_l3_incl_cf =
2744 VXGE_HAL_VPATH_RPA_L3_INCL_CF_USE_FLASH_DEFAULT;
2746 device_config->vp_config[i].rpa_l3_comp_csum =
2747 VXGE_HAL_VPATH_RPA_L3_COMP_CSUM_USE_FLASH_DEFAULT;
2749 device_config->vp_config[i].rpa_ucast_all_addr_en =
2750 VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_USE_FLASH_DEFAULT;
2752 device_config->vp_config[i].rpa_mcast_all_addr_en =
2753 VXGE_HAL_VPATH_RPA_MCAST_ALL_ADDR_USE_FLASH_DEFAULT;
2755 device_config->vp_config[i].rpa_bcast_en =
2756 VXGE_HAL_VPATH_RPA_BCAST_USE_FLASH_DEFAULT;
2758 device_config->vp_config[i].rpa_all_vid_en =
2759 VXGE_HAL_VPATH_RPA_ALL_VID_USE_FLASH_DEFAULT;
2761 device_config->vp_config[i].vp_queue_l2_flow =
2762 VXGE_HAL_VPATH_VP_Q_L2_FLOW_USE_FLASH_DEFAULT;
2766 device_config->max_cqe_groups = VXGE_HAL_DEF_MAX_CQE_GROUPS;
2768 device_config->max_num_wqe_od_groups = VXGE_HAL_DEF_MAX_NUM_OD_GROUPS;
2770 device_config->no_wqe_threshold = VXGE_HAL_DEF_NO_WQE_THRESHOLD;
2772 device_config->refill_threshold_high =
2773 VXGE_HAL_DEF_REFILL_THRESHOLD_HIGH;
2775 device_config->refill_threshold_low = VXGE_HAL_DEF_REFILL_THRESHOLD_LOW;
2777 device_config->ack_blk_limit = VXGE_HAL_DEF_ACK_BLOCK_LIMIT;
2779 device_config->poll_or_doorbell = VXGE_HAL_POLL_OR_DOORBELL_DEFAULT;
2781 device_config->stats_read_method = VXGE_HAL_STATS_READ_METHOD_DEFAULT;
2783 device_config->debug_level = VXGE_DEBUG_LEVEL_DEF;
2785 device_config->debug_mask = VXGE_DEBUG_MODULE_MASK_DEF;
2787 #if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
2788 device_config->tracebuf_size = VXGE_HAL_DEF_CIRCULAR_ARR;
2790 vxge_hal_trace_log_driver("<== %s:%s:%d Result = 0",
2791 __FILE__, __func__, __LINE__);
2793 return (VXGE_HAL_OK);
2797 vxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id)
2800 __hal_device_t *hldev = (__hal_device_t *) devh;
2801 __hal_virtualpath_t *vpath;
2803 vxge_assert(devh != NULL);
2805 vpath = (__hal_virtualpath_t *) &hldev->virtual_paths[vp_id];
2807 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2808 __FILE__, __func__, __LINE__);
2810 vxge_hal_trace_log_vpath("devh = 0x"VXGE_OS_STXFMT", vp_id = %d",
2811 (ptr_t) devh, vp_id);
2813 val64 = vxge_os_pio_mem_read64(vpath->hldev->header.pdev,
2814 vpath->hldev->header.regh0,
2815 &vpath->vp_reg->rxmac_vcfg0);
2817 val64 &= ~VXGE_HAL_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
2819 vxge_os_pio_mem_write64(vpath->hldev->header.pdev,
2820 vpath->hldev->header.regh0,
2822 &vpath->vp_reg->rxmac_vcfg0);
2824 vxge_hal_trace_log_ring("<== %s:%s:%d Result: 0",
2825 __FILE__, __func__, __LINE__);
2827 vxge_os_pio_mem_read64(vpath->hldev->header.pdev,
2828 vpath->hldev->header.regh0,
2829 &vpath->vp_reg->rxmac_vcfg0);
2833 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
2835 * Bug: Receive path stuck during small frames blast test after numerous vpath
2838 * Fix: Driver work-around is to ensure that the vpath queue in the FB(frame
2839 * buffer) is empty before reset is asserted. In order to do this driver needs
2840 * to stop RxMAC from sending frames to the queue, e.g., by configuring the
2841 * max frame length for the vpath to 0 or some small value. Driver then polls
2842 * WRDMA registers to check that the ring controller for the vpath is not
2843 * processing frames for a period of time(while having enough RxDs to do so).
2845 * Poll 2 registers in the WRDMA, namely the FRM_IN_PROGRESS_CNT_VPn register
2846 * and the PRC_RXD_DOORBELL_VPn register. There is no per-vpath register in
2847 * the frame buffer that indicates if the vpath queue is empty, so determine
2848 * the empty state with 2 conditions:
2849 * 1. There are no frames currently being processed in the WRDMA for
2851 * 2. The ring controller for the vpath is not being starved of RxDs
2852 * (otherwise it will not be able to process frames even though the FB vpath
2853 * queue is not empty).
2855 * For the second condition, compare the read value of PRC_RXD_DOORBELL_VPn
2856 * register against the RXD_SPAT value for the vpath.
2857 * The ring controller will not attempt to fetch RxDs until it has at least
2858 * RXD_SPAT qwords in the doorbell. A factor of 2 is used just to be safe.
2859 * Additionally, it is also possible that the ring controller is not
2860 * processing frames because of arbitration. The chance of this is very small,
2861 * and we try to reduce it even further by checking that the 2 conditions above
2862 * hold in 3 successive polls. This bug does not occur when frames from the
2863 * reset vpath are not selected back-to-back due to arbitration.
2864 * @hldev: HW device handle.
2869 vxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id,
2870 u32 *count, u32 *total_count)
2873 u32 new_qw_count, rxd_spat;
2874 __hal_device_t *hldev = (__hal_device_t *) devh;
2875 __hal_virtualpath_t *vpath;
2877 vpath = &hldev->virtual_paths[vp_id];
2879 vxge_assert(vpath != NULL);
2881 vxge_hal_trace_log_vpath("==> %s:%s:%d",
2882 __FILE__, __func__, __LINE__);
2884 vxge_hal_trace_log_vpath("vpath_handle = 0x"VXGE_OS_STXFMT,
2887 if (vpath->vp_config->ring.enable == VXGE_HAL_RING_DISABLE) {
2888 vxge_hal_trace_log_vpath("<== %s:%s:%d ",
2889 __FILE__, __func__, __LINE__);
2896 val64 = vxge_os_pio_mem_read64(
2898 hldev->header.regh0,
2899 &vpath->vp_reg->prc_rxd_doorbell);
2902 (u32) VXGE_HAL_PRC_RXD_DOORBELL_GET_NEW_QW_CNT(val64);
2904 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2905 hldev->header.regh0,
2906 &vpath->vp_reg->prc_cfg6);
2908 rxd_spat = (u32) VXGE_HAL_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
2910 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
2911 hldev->header.regh0,
2912 &vpath->vp_reg->frm_in_progress_cnt);
2915 * Check if there is enough RxDs with HW AND
2916 * it is not processing any frames.
2919 if ((new_qw_count <= 2 * rxd_spat) || (val64 > 0))
2925 } while ((*count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
2926 (*total_count < VXGE_HW_MAX_POLLING_COUNT));
2928 vxge_hal_trace_log_vpath("<== %s:%s:%d",
2929 __FILE__, __func__, __LINE__);
2931 vxge_assert(*total_count < VXGE_HW_MAX_POLLING_COUNT);