2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * Winbond fast ethernet PCI NIC driver
39 * Supports various cheap network adapters based on the Winbond W89C840F
40 * fast ethernet controller chip. This includes adapters manufactured by
41 * Winbond itself and some made by Linksys.
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
48 * The Winbond W89C840F chip is a bus master; in some ways it resembles
49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
50 * one major difference which is that while the registers do many of
51 * the same things as a tulip adapter, the offsets are different: where
52 * tulip registers are typically spaced 8 bytes apart, the Winbond
53 * registers are spaced 4 bytes apart. The receiver filter is also
54 * programmed differently.
56 * Like the tulip, the Winbond chip uses small descriptors containing
57 * a status word, a control word and 32-bit areas that can either be used
58 * to point to two external data blocks, or to point to a single block
59 * and another descriptor in a linked list. Descriptors can be grouped
60 * together in blocks to form fixed length rings or can be chained
61 * together in linked lists. A single packet may be spread out over
62 * several descriptors if necessary.
64 * For the receive ring, this driver uses a linked list of descriptors,
65 * each pointing to a single mbuf cluster buffer, which us large enough
66 * to hold an entire packet. The link list is looped back to created a
69 * For transmission, the driver creates a linked list of 'super descriptors'
70 * which each contain several individual descriptors linked toghether.
71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
72 * abuse as fragment pointers. This allows us to use a buffer managment
73 * scheme very similar to that used in the ThunderLAN and Etherlink XL
76 * Autonegotiation is performed using the external PHY via the MII bus.
77 * The sample boards I have all use a Davicom PHY.
79 * Note: the author of the Linux driver for the Winbond chip alludes
80 * to some sort of flaw in the chip's design that seems to mandate some
81 * drastic workaround which signigicantly impairs transmit performance.
82 * I have no idea what he's on about: transmit performance with all
83 * three of my test boards seems fine.
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/sockio.h>
90 #include <sys/malloc.h>
91 #include <sys/module.h>
92 #include <sys/kernel.h>
93 #include <sys/socket.h>
94 #include <sys/queue.h>
97 #include <net/if_arp.h>
98 #include <net/ethernet.h>
99 #include <net/if_dl.h>
100 #include <net/if_media.h>
101 #include <net/if_types.h>
105 #include <vm/vm.h> /* for vtophys */
106 #include <vm/pmap.h> /* for vtophys */
107 #include <machine/bus.h>
108 #include <machine/resource.h>
110 #include <sys/rman.h>
112 #include <dev/pci/pcireg.h>
113 #include <dev/pci/pcivar.h>
115 #include <dev/mii/mii.h>
116 #include <dev/mii/miivar.h>
118 /* "device miibus" required. See GENERIC if you get errors here. */
119 #include "miibus_if.h"
121 #define WB_USEIOSPACE
123 #include <dev/wb/if_wbreg.h>
125 MODULE_DEPEND(wb, pci, 1, 1, 1);
126 MODULE_DEPEND(wb, ether, 1, 1, 1);
127 MODULE_DEPEND(wb, miibus, 1, 1, 1);
130 * Various supported device vendors/types and their names.
132 static struct wb_type wb_devs[] = {
133 { WB_VENDORID, WB_DEVICEID_840F,
134 "Winbond W89C840F 10/100BaseTX" },
135 { CP_VENDORID, CP_DEVICEID_RL100,
136 "Compex RL100-ATX 10/100baseTX" },
140 static int wb_probe(device_t);
141 static int wb_attach(device_t);
142 static int wb_detach(device_t);
144 static void wb_bfree(void *addr, void *args);
145 static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
147 static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *);
149 static void wb_rxeof(struct wb_softc *);
150 static void wb_rxeoc(struct wb_softc *);
151 static void wb_txeof(struct wb_softc *);
152 static void wb_txeoc(struct wb_softc *);
153 static void wb_intr(void *);
154 static void wb_tick(void *);
155 static void wb_start(struct ifnet *);
156 static void wb_start_locked(struct ifnet *);
157 static int wb_ioctl(struct ifnet *, u_long, caddr_t);
158 static void wb_init(void *);
159 static void wb_init_locked(struct wb_softc *);
160 static void wb_stop(struct wb_softc *);
161 static void wb_watchdog(struct wb_softc *);
162 static int wb_shutdown(device_t);
163 static int wb_ifmedia_upd(struct ifnet *);
164 static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
166 static void wb_eeprom_putbyte(struct wb_softc *, int);
167 static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
168 static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
169 static void wb_mii_sync(struct wb_softc *);
170 static void wb_mii_send(struct wb_softc *, u_int32_t, int);
171 static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
172 static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
174 static void wb_setcfg(struct wb_softc *, u_int32_t);
175 static void wb_setmulti(struct wb_softc *);
176 static void wb_reset(struct wb_softc *);
177 static void wb_fixmedia(struct wb_softc *);
178 static int wb_list_rx_init(struct wb_softc *);
179 static int wb_list_tx_init(struct wb_softc *);
181 static int wb_miibus_readreg(device_t, int, int);
182 static int wb_miibus_writereg(device_t, int, int, int);
183 static void wb_miibus_statchg(device_t);
186 #define WB_RES SYS_RES_IOPORT
187 #define WB_RID WB_PCI_LOIO
189 #define WB_RES SYS_RES_MEMORY
190 #define WB_RID WB_PCI_LOMEM
193 static device_method_t wb_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, wb_probe),
196 DEVMETHOD(device_attach, wb_attach),
197 DEVMETHOD(device_detach, wb_detach),
198 DEVMETHOD(device_shutdown, wb_shutdown),
200 /* bus interface, for miibus */
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205 DEVMETHOD(miibus_readreg, wb_miibus_readreg),
206 DEVMETHOD(miibus_writereg, wb_miibus_writereg),
207 DEVMETHOD(miibus_statchg, wb_miibus_statchg),
211 static driver_t wb_driver = {
214 sizeof(struct wb_softc)
217 static devclass_t wb_devclass;
219 DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0);
220 DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0);
222 #define WB_SETBIT(sc, reg, x) \
223 CSR_WRITE_4(sc, reg, \
224 CSR_READ_4(sc, reg) | (x))
226 #define WB_CLRBIT(sc, reg, x) \
227 CSR_WRITE_4(sc, reg, \
228 CSR_READ_4(sc, reg) & ~(x))
231 CSR_WRITE_4(sc, WB_SIO, \
232 CSR_READ_4(sc, WB_SIO) | (x))
235 CSR_WRITE_4(sc, WB_SIO, \
236 CSR_READ_4(sc, WB_SIO) & ~(x))
239 * Send a read command and address to the EEPROM, check for ACK.
242 wb_eeprom_putbyte(sc, addr)
248 d = addr | WB_EECMD_READ;
251 * Feed in each bit and stobe the clock.
253 for (i = 0x400; i; i >>= 1) {
255 SIO_SET(WB_SIO_EE_DATAIN);
257 SIO_CLR(WB_SIO_EE_DATAIN);
260 SIO_SET(WB_SIO_EE_CLK);
262 SIO_CLR(WB_SIO_EE_CLK);
270 * Read a word of data stored in the EEPROM at address 'addr.'
273 wb_eeprom_getword(sc, addr, dest)
281 /* Enter EEPROM access mode. */
282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
285 * Send address of word we want to read.
287 wb_eeprom_putbyte(sc, addr);
289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
292 * Start reading bits from EEPROM.
294 for (i = 0x8000; i; i >>= 1) {
295 SIO_SET(WB_SIO_EE_CLK);
297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
299 SIO_CLR(WB_SIO_EE_CLK);
303 /* Turn off EEPROM access mode. */
304 CSR_WRITE_4(sc, WB_SIO, 0);
312 * Read a sequence of words from the EEPROM.
315 wb_read_eeprom(sc, dest, off, cnt, swap)
323 u_int16_t word = 0, *ptr;
325 for (i = 0; i < cnt; i++) {
326 wb_eeprom_getword(sc, off + i, &word);
327 ptr = (u_int16_t *)(dest + (i * 2));
338 * Sync the PHYs by setting data bit and strobing the clock 32 times.
346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
348 for (i = 0; i < 32; i++) {
349 SIO_SET(WB_SIO_MII_CLK);
351 SIO_CLR(WB_SIO_MII_CLK);
359 * Clock a series of bits through the MII.
362 wb_mii_send(sc, bits, cnt)
369 SIO_CLR(WB_SIO_MII_CLK);
371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
373 SIO_SET(WB_SIO_MII_DATAIN);
375 SIO_CLR(WB_SIO_MII_DATAIN);
378 SIO_CLR(WB_SIO_MII_CLK);
380 SIO_SET(WB_SIO_MII_CLK);
385 * Read an PHY register through the MII.
388 wb_mii_readreg(sc, frame)
390 struct wb_mii_frame *frame;
396 * Set up frame for RX.
398 frame->mii_stdelim = WB_MII_STARTDELIM;
399 frame->mii_opcode = WB_MII_READOP;
400 frame->mii_turnaround = 0;
403 CSR_WRITE_4(sc, WB_SIO, 0);
408 SIO_SET(WB_SIO_MII_DIR);
413 * Send command/address info.
415 wb_mii_send(sc, frame->mii_stdelim, 2);
416 wb_mii_send(sc, frame->mii_opcode, 2);
417 wb_mii_send(sc, frame->mii_phyaddr, 5);
418 wb_mii_send(sc, frame->mii_regaddr, 5);
421 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
423 SIO_SET(WB_SIO_MII_CLK);
427 SIO_CLR(WB_SIO_MII_DIR);
429 SIO_CLR(WB_SIO_MII_CLK);
431 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
432 SIO_SET(WB_SIO_MII_CLK);
434 SIO_CLR(WB_SIO_MII_CLK);
436 SIO_SET(WB_SIO_MII_CLK);
440 * Now try reading data bits. If the ack failed, we still
441 * need to clock through 16 cycles to keep the PHY(s) in sync.
444 for(i = 0; i < 16; i++) {
445 SIO_CLR(WB_SIO_MII_CLK);
447 SIO_SET(WB_SIO_MII_CLK);
453 for (i = 0x8000; i; i >>= 1) {
454 SIO_CLR(WB_SIO_MII_CLK);
457 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
458 frame->mii_data |= i;
461 SIO_SET(WB_SIO_MII_CLK);
467 SIO_CLR(WB_SIO_MII_CLK);
469 SIO_SET(WB_SIO_MII_CLK);
478 * Write to a PHY register through the MII.
481 wb_mii_writereg(sc, frame)
483 struct wb_mii_frame *frame;
488 * Set up frame for TX.
491 frame->mii_stdelim = WB_MII_STARTDELIM;
492 frame->mii_opcode = WB_MII_WRITEOP;
493 frame->mii_turnaround = WB_MII_TURNAROUND;
496 * Turn on data output.
498 SIO_SET(WB_SIO_MII_DIR);
502 wb_mii_send(sc, frame->mii_stdelim, 2);
503 wb_mii_send(sc, frame->mii_opcode, 2);
504 wb_mii_send(sc, frame->mii_phyaddr, 5);
505 wb_mii_send(sc, frame->mii_regaddr, 5);
506 wb_mii_send(sc, frame->mii_turnaround, 2);
507 wb_mii_send(sc, frame->mii_data, 16);
510 SIO_SET(WB_SIO_MII_CLK);
512 SIO_CLR(WB_SIO_MII_CLK);
518 SIO_CLR(WB_SIO_MII_DIR);
524 wb_miibus_readreg(dev, phy, reg)
529 struct wb_mii_frame frame;
531 sc = device_get_softc(dev);
533 bzero((char *)&frame, sizeof(frame));
535 frame.mii_phyaddr = phy;
536 frame.mii_regaddr = reg;
537 wb_mii_readreg(sc, &frame);
539 return(frame.mii_data);
543 wb_miibus_writereg(dev, phy, reg, data)
548 struct wb_mii_frame frame;
550 sc = device_get_softc(dev);
552 bzero((char *)&frame, sizeof(frame));
554 frame.mii_phyaddr = phy;
555 frame.mii_regaddr = reg;
556 frame.mii_data = data;
558 wb_mii_writereg(sc, &frame);
564 wb_miibus_statchg(dev)
568 struct mii_data *mii;
570 sc = device_get_softc(dev);
571 mii = device_get_softc(sc->wb_miibus);
572 wb_setcfg(sc, mii->mii_media_active);
578 * Program the 64-bit multicast hash filter.
586 u_int32_t hashes[2] = { 0, 0 };
587 struct ifmultiaddr *ifma;
593 rxfilt = CSR_READ_4(sc, WB_NETCFG);
595 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
596 rxfilt |= WB_NETCFG_RX_MULTI;
597 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
598 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
599 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
603 /* first, zot all the existing hash bits */
604 CSR_WRITE_4(sc, WB_MAR0, 0);
605 CSR_WRITE_4(sc, WB_MAR1, 0);
607 /* now program new ones */
609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
610 if (ifma->ifma_addr->sa_family != AF_LINK)
612 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
613 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
615 hashes[0] |= (1 << h);
617 hashes[1] |= (1 << (h - 32));
620 if_maddr_runlock(ifp);
623 rxfilt |= WB_NETCFG_RX_MULTI;
625 rxfilt &= ~WB_NETCFG_RX_MULTI;
627 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
628 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
629 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
635 * The Winbond manual states that in order to fiddle with the
636 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
637 * first have to put the transmit and/or receive logic in the idle state.
646 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
648 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
650 for (i = 0; i < WB_TIMEOUT; i++) {
652 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
653 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
658 device_printf(sc->wb_dev,
659 "failed to force tx and rx to idle state\n");
662 if (IFM_SUBTYPE(media) == IFM_10_T)
663 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
667 if ((media & IFM_GMASK) == IFM_FDX)
668 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
670 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
683 struct mii_data *mii;
684 struct mii_softc *miisc;
686 CSR_WRITE_4(sc, WB_NETCFG, 0);
687 CSR_WRITE_4(sc, WB_BUSCTL, 0);
688 CSR_WRITE_4(sc, WB_TXADDR, 0);
689 CSR_WRITE_4(sc, WB_RXADDR, 0);
691 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
692 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
694 for (i = 0; i < WB_TIMEOUT; i++) {
696 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
700 device_printf(sc->wb_dev, "reset never completed!\n");
702 /* Wait a little while for the chip to get its brains in order. */
705 if (sc->wb_miibus == NULL)
708 mii = device_get_softc(sc->wb_miibus);
709 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
717 struct mii_data *mii = NULL;
721 mii = device_get_softc(sc->wb_miibus);
725 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
726 media = mii->mii_media_active & ~IFM_10_T;
728 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
729 media = mii->mii_media_active & ~IFM_100_TX;
734 ifmedia_set(&mii->mii_media, media);
738 * Probe for a Winbond chip. Check the PCI vendor and device
739 * IDs against our list and return a device name if we find a match.
749 while(t->wb_name != NULL) {
750 if ((pci_get_vendor(dev) == t->wb_vid) &&
751 (pci_get_device(dev) == t->wb_did)) {
752 device_set_desc(dev, t->wb_name);
753 return (BUS_PROBE_DEFAULT);
762 * Attach the interface. Allocate softc structures, do ifmedia
763 * setup and ethernet/BPF attach.
769 u_char eaddr[ETHER_ADDR_LEN];
774 sc = device_get_softc(dev);
777 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
779 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0);
782 * Map control/status registers.
784 pci_enable_busmaster(dev);
787 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE);
789 if (sc->wb_res == NULL) {
790 device_printf(dev, "couldn't map ports/memory\n");
795 /* Allocate interrupt */
797 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
798 RF_SHAREABLE | RF_ACTIVE);
800 if (sc->wb_irq == NULL) {
801 device_printf(dev, "couldn't map interrupt\n");
806 /* Save the cache line size. */
807 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF;
809 /* Reset the adapter. */
813 * Get station address from the EEPROM.
815 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0);
817 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF,
818 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
820 if (sc->wb_ldata == NULL) {
821 device_printf(dev, "no memory for list buffers!\n");
826 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
828 ifp = sc->wb_ifp = if_alloc(IFT_ETHER);
830 device_printf(dev, "can not if_alloc()\n");
835 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
836 ifp->if_mtu = ETHERMTU;
837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
838 ifp->if_ioctl = wb_ioctl;
839 ifp->if_start = wb_start;
840 ifp->if_init = wb_init;
841 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1;
846 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd,
847 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
849 device_printf(dev, "attaching PHYs failed\n");
854 * Call MI attach routine.
856 ether_ifattach(ifp, eaddr);
858 /* Hook interrupt last to avoid having to lock softc */
859 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE,
860 NULL, wb_intr, sc, &sc->wb_intrhand);
863 device_printf(dev, "couldn't set up irq\n");
876 * Shutdown hardware and free up resources. This can be called any
877 * time after the mutex has been initialized. It is called in both
878 * the error case in attach and the normal detach case so it needs
879 * to be careful about only freeing resources that have actually been
889 sc = device_get_softc(dev);
890 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized"));
894 * Delete any miibus and phy devices attached to this interface.
895 * This should only be done if attach succeeded.
897 if (device_is_attached(dev)) {
902 callout_drain(&sc->wb_stat_callout);
905 device_delete_child(dev, sc->wb_miibus);
906 bus_generic_detach(dev);
909 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand);
911 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq);
913 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res);
919 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8,
923 mtx_destroy(&sc->wb_mtx);
929 * Initialize the transmit descriptors.
935 struct wb_chain_data *cd;
936 struct wb_list_data *ld;
942 for (i = 0; i < WB_TX_LIST_CNT; i++) {
943 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
944 if (i == (WB_TX_LIST_CNT - 1)) {
945 cd->wb_tx_chain[i].wb_nextdesc =
948 cd->wb_tx_chain[i].wb_nextdesc =
949 &cd->wb_tx_chain[i + 1];
953 cd->wb_tx_free = &cd->wb_tx_chain[0];
954 cd->wb_tx_tail = cd->wb_tx_head = NULL;
961 * Initialize the RX descriptors and allocate mbufs for them. Note that
962 * we arrange the descriptors in a closed ring, so that the last descriptor
963 * points back to the first.
969 struct wb_chain_data *cd;
970 struct wb_list_data *ld;
976 for (i = 0; i < WB_RX_LIST_CNT; i++) {
977 cd->wb_rx_chain[i].wb_ptr =
978 (struct wb_desc *)&ld->wb_rx_list[i];
979 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
980 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
982 if (i == (WB_RX_LIST_CNT - 1)) {
983 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
984 ld->wb_rx_list[i].wb_next =
985 vtophys(&ld->wb_rx_list[0]);
987 cd->wb_rx_chain[i].wb_nextdesc =
988 &cd->wb_rx_chain[i + 1];
989 ld->wb_rx_list[i].wb_next =
990 vtophys(&ld->wb_rx_list[i + 1]);
994 cd->wb_rx_head = &cd->wb_rx_chain[0];
1008 * Initialize an RX descriptor and attach an MBUF cluster.
1012 struct wb_softc *sc;
1013 struct wb_chain_onefrag *c;
1016 struct mbuf *m_new = NULL;
1019 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1022 m_new->m_data = c->wb_buf;
1023 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES;
1024 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf,
1025 NULL, 0, EXT_NET_DRV);
1028 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1029 m_new->m_data = m_new->m_ext.ext_buf;
1032 m_adj(m_new, sizeof(u_int64_t));
1035 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1036 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1037 c->wb_ptr->wb_status = WB_RXSTAT;
1043 * A frame has been uploaded: pass the resulting mbuf chain up to
1044 * the higher level protocols.
1048 struct wb_softc *sc;
1050 struct mbuf *m = NULL;
1052 struct wb_chain_onefrag *cur_rx;
1060 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1062 struct mbuf *m0 = NULL;
1064 cur_rx = sc->wb_cdata.wb_rx_head;
1065 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1067 m = cur_rx->wb_mbuf;
1069 if ((rxstat & WB_RXSTAT_MIIERR) ||
1070 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1071 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1072 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1073 !(rxstat & WB_RXSTAT_RXCMP)) {
1075 wb_newbuf(sc, cur_rx, m);
1076 device_printf(sc->wb_dev,
1077 "receiver babbling: possible chip bug,"
1078 " forcing reset\n");
1085 if (rxstat & WB_RXSTAT_RXERR) {
1087 wb_newbuf(sc, cur_rx, m);
1091 /* No errors; receive the packet. */
1092 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1095 * XXX The Winbond chip includes the CRC with every
1096 * received frame, and there's no way to turn this
1097 * behavior off (at least, I can't find anything in
1098 * the manual that explains how to do it) so we have
1099 * to trim off the CRC manually.
1101 total_len -= ETHER_CRC_LEN;
1103 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp,
1105 wb_newbuf(sc, cur_rx, m);
1114 (*ifp->if_input)(ifp, m);
1121 struct wb_softc *sc;
1125 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1126 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1127 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1128 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1129 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1135 * A frame was downloaded to the chip. It's safe for us to clean up
1140 struct wb_softc *sc;
1142 struct wb_chain *cur_tx;
1147 /* Clear the timeout timer. */
1150 if (sc->wb_cdata.wb_tx_head == NULL)
1154 * Go through our tx list and free mbufs for those
1155 * frames that have been transmitted.
1157 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1160 cur_tx = sc->wb_cdata.wb_tx_head;
1161 txstat = WB_TXSTATUS(cur_tx);
1163 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1166 if (txstat & WB_TXSTAT_TXERR) {
1168 if (txstat & WB_TXSTAT_ABORT)
1169 ifp->if_collisions++;
1170 if (txstat & WB_TXSTAT_LATECOLL)
1171 ifp->if_collisions++;
1174 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1177 m_freem(cur_tx->wb_mbuf);
1178 cur_tx->wb_mbuf = NULL;
1180 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1181 sc->wb_cdata.wb_tx_head = NULL;
1182 sc->wb_cdata.wb_tx_tail = NULL;
1186 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1193 * TX 'end of channel' interrupt handler.
1197 struct wb_softc *sc;
1205 if (sc->wb_cdata.wb_tx_head == NULL) {
1206 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1207 sc->wb_cdata.wb_tx_tail = NULL;
1209 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1210 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1212 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1223 struct wb_softc *sc;
1231 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1236 /* Disable interrupts. */
1237 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1241 status = CSR_READ_4(sc, WB_ISR);
1243 CSR_WRITE_4(sc, WB_ISR, status);
1245 if ((status & WB_INTRS) == 0)
1248 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1251 if (status & WB_ISR_RX_ERR)
1257 if (status & WB_ISR_RX_OK)
1260 if (status & WB_ISR_RX_IDLE)
1263 if (status & WB_ISR_TX_OK)
1266 if (status & WB_ISR_TX_NOBUF)
1269 if (status & WB_ISR_TX_IDLE) {
1271 if (sc->wb_cdata.wb_tx_head != NULL) {
1272 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1273 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1277 if (status & WB_ISR_TX_UNDERRUN) {
1280 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1281 /* Jack up TX threshold */
1282 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1283 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1284 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1285 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1288 if (status & WB_ISR_BUS_ERR) {
1295 /* Re-enable interrupts. */
1296 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1298 if (ifp->if_snd.ifq_head != NULL) {
1299 wb_start_locked(ifp);
1311 struct wb_softc *sc;
1312 struct mii_data *mii;
1316 mii = device_get_softc(sc->wb_miibus);
1320 if (sc->wb_timer > 0 && --sc->wb_timer == 0)
1322 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1328 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1329 * pointers to the fragment pointers.
1332 wb_encap(sc, c, m_head)
1333 struct wb_softc *sc;
1335 struct mbuf *m_head;
1338 struct wb_desc *f = NULL;
1343 * Start packing the mbufs in this chain into
1344 * the fragment pointers. Stop when we run out
1345 * of fragments or hit the end of the mbuf chain.
1350 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1351 if (m->m_len != 0) {
1352 if (frag == WB_MAXFRAGS)
1354 total_len += m->m_len;
1355 f = &c->wb_ptr->wb_frag[frag];
1356 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1358 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1361 f->wb_status = WB_TXSTAT_OWN;
1362 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1363 f->wb_data = vtophys(mtod(m, vm_offset_t));
1369 * Handle special case: we used up all 16 fragments,
1370 * but we have more mbufs left in the chain. Copy the
1371 * data into an mbuf cluster. Note that we don't
1372 * bother clearing the values in the other fragment
1373 * pointers/counters; it wouldn't gain us anything,
1374 * and would waste cycles.
1377 struct mbuf *m_new = NULL;
1379 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1382 if (m_head->m_pkthdr.len > MHLEN) {
1383 MCLGET(m_new, M_DONTWAIT);
1384 if (!(m_new->m_flags & M_EXT)) {
1389 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1390 mtod(m_new, caddr_t));
1391 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1394 f = &c->wb_ptr->wb_frag[0];
1396 f->wb_data = vtophys(mtod(m_new, caddr_t));
1397 f->wb_ctl = total_len = m_new->m_len;
1398 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1402 if (total_len < WB_MIN_FRAMELEN) {
1403 f = &c->wb_ptr->wb_frag[frag];
1404 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1405 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1406 f->wb_ctl |= WB_TXCTL_TLINK;
1407 f->wb_status = WB_TXSTAT_OWN;
1411 c->wb_mbuf = m_head;
1412 c->wb_lastdesc = frag - 1;
1413 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1414 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1420 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1421 * to the mbuf data regions directly in the transmit lists. We also save a
1422 * copy of the pointers since the transmit list fragment pointers are
1423 * physical addresses.
1430 struct wb_softc *sc;
1434 wb_start_locked(ifp);
1439 wb_start_locked(ifp)
1442 struct wb_softc *sc;
1443 struct mbuf *m_head = NULL;
1444 struct wb_chain *cur_tx = NULL, *start_tx;
1450 * Check for an available queue slot. If there are none,
1453 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1454 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1458 start_tx = sc->wb_cdata.wb_tx_free;
1460 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1461 IF_DEQUEUE(&ifp->if_snd, m_head);
1465 /* Pick a descriptor off the free list. */
1466 cur_tx = sc->wb_cdata.wb_tx_free;
1467 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1469 /* Pack the data into the descriptor. */
1470 wb_encap(sc, cur_tx, m_head);
1472 if (cur_tx != start_tx)
1473 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1476 * If there's a BPF listener, bounce a copy of this frame
1479 BPF_MTAP(ifp, cur_tx->wb_mbuf);
1483 * If there are no packets queued, bail.
1489 * Place the request for the upload interrupt
1490 * in the last descriptor in the chain. This way, if
1491 * we're chaining several packets at once, we'll only
1492 * get an interrupt once for the whole chain rather than
1493 * once for each packet.
1495 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1496 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1497 sc->wb_cdata.wb_tx_tail = cur_tx;
1499 if (sc->wb_cdata.wb_tx_head == NULL) {
1500 sc->wb_cdata.wb_tx_head = start_tx;
1501 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1502 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1505 * We need to distinguish between the case where
1506 * the own bit is clear because the chip cleared it
1507 * and where the own bit is clear because we haven't
1508 * set it yet. The magic value WB_UNSET is just some
1509 * ramdomly chosen number which doesn't have the own
1510 * bit set. When we actually transmit the frame, the
1511 * status word will have _only_ the own bit set, so
1512 * the txeoc handler will be able to tell if it needs
1513 * to initiate another transmission to flush out pending
1516 WB_TXOWN(start_tx) = WB_UNSENT;
1520 * Set a timeout in case the chip goes out to lunch.
1531 struct wb_softc *sc = xsc;
1540 struct wb_softc *sc;
1542 struct ifnet *ifp = sc->wb_ifp;
1544 struct mii_data *mii;
1547 mii = device_get_softc(sc->wb_miibus);
1550 * Cancel pending I/O and free all RX/TX buffers.
1555 sc->wb_txthresh = WB_TXTHRESH_INIT;
1558 * Set cache alignment and burst length.
1561 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1562 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1563 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1566 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1567 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1568 switch(sc->wb_cachesize) {
1570 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1573 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1576 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1580 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1584 /* This doesn't tend to work too well at 100Mbps. */
1585 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1587 /* Init our MAC address */
1588 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1589 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]);
1592 /* Init circular RX list. */
1593 if (wb_list_rx_init(sc) == ENOBUFS) {
1594 device_printf(sc->wb_dev,
1595 "initialization failed: no memory for rx buffers\n");
1600 /* Init TX descriptors. */
1601 wb_list_tx_init(sc);
1603 /* If we want promiscuous mode, set the allframes bit. */
1604 if (ifp->if_flags & IFF_PROMISC) {
1605 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1607 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1611 * Set capture broadcast bit to capture broadcast frames.
1613 if (ifp->if_flags & IFF_BROADCAST) {
1614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1616 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1620 * Program the multicast filter, if necessary.
1625 * Load the address of the RX list.
1627 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1628 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1631 * Enable interrupts.
1633 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1634 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1636 /* Enable receiver and transmitter. */
1637 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1638 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1640 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1641 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1642 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1646 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1647 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1649 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc);
1655 * Set media options.
1661 struct wb_softc *sc;
1666 if (ifp->if_flags & IFF_UP)
1674 * Report current media status.
1677 wb_ifmedia_sts(ifp, ifmr)
1679 struct ifmediareq *ifmr;
1681 struct wb_softc *sc;
1682 struct mii_data *mii;
1687 mii = device_get_softc(sc->wb_miibus);
1690 ifmr->ifm_active = mii->mii_media_active;
1691 ifmr->ifm_status = mii->mii_media_status;
1698 wb_ioctl(ifp, command, data)
1703 struct wb_softc *sc = ifp->if_softc;
1704 struct mii_data *mii;
1705 struct ifreq *ifr = (struct ifreq *) data;
1711 if (ifp->if_flags & IFF_UP) {
1714 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1729 mii = device_get_softc(sc->wb_miibus);
1730 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1733 error = ether_ioctl(ifp, command, data);
1742 struct wb_softc *sc;
1749 if_printf(ifp, "watchdog timeout\n");
1751 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1752 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1758 if (ifp->if_snd.ifq_head != NULL)
1759 wb_start_locked(ifp);
1765 * Stop the adapter and free any mbufs allocated to the
1770 struct wb_softc *sc;
1779 callout_stop(&sc->wb_stat_callout);
1781 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1782 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1783 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1784 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1787 * Free data in the RX lists.
1789 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1790 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1791 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1792 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1795 bzero((char *)&sc->wb_ldata->wb_rx_list,
1796 sizeof(sc->wb_ldata->wb_rx_list));
1799 * Free the TX list buffers.
1801 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1802 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1803 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1804 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1808 bzero((char *)&sc->wb_ldata->wb_tx_list,
1809 sizeof(sc->wb_ldata->wb_tx_list));
1811 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1817 * Stop all chip I/O so that the kernel's probe routines don't
1818 * get confused by errant DMAs when rebooting.
1824 struct wb_softc *sc;
1826 sc = device_get_softc(dev);