2 * Copyright (c) KATO Takenori, 1997, 1998.
4 * All rights reserved. Unpublished rights reserved under the copyright
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer as
13 * the first lines of this file unmodified.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <machine/cputypes.h>
41 #include <machine/md_var.h>
42 #include <machine/specialreg.h>
47 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
48 #define CPU_ENABLE_SSE
51 void initializecpu(void);
52 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
53 void enable_K5_wt_alloc(void);
54 void enable_K6_wt_alloc(void);
55 void enable_K6_2_wt_alloc(void);
59 static void init_5x86(void);
60 static void init_bluelightning(void);
61 static void init_486dlc(void);
62 static void init_cy486dx(void);
63 #ifdef CPU_I486_ON_386
64 static void init_i486_on_386(void);
66 static void init_6x86(void);
70 static void init_6x86MX(void);
71 static void init_ppro(void);
72 static void init_mendocino(void);
75 static int hw_instruction_sse;
76 SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
77 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU");
79 * -1: automatic (default)
80 * 0: keep enable CLFLUSH
81 * 1: force disable CLFLUSH
83 static int hw_clflush_disable = -1;
85 /* Must *NOT* be BSS or locore will bzero these after setting them */
86 int cpu = 0; /* Are we 386, 386sx, 486, etc? */
87 u_int cpu_feature = 0; /* Feature flags */
88 u_int cpu_feature2 = 0; /* Feature flags */
89 u_int amd_feature = 0; /* AMD feature flags */
90 u_int amd_feature2 = 0; /* AMD feature flags */
91 u_int amd_pminfo = 0; /* AMD advanced power management info */
92 u_int via_feature_rng = 0; /* VIA RNG features */
93 u_int via_feature_xcrypt = 0; /* VIA ACE features */
94 u_int cpu_high = 0; /* Highest arg to CPUID */
95 u_int cpu_id = 0; /* Stepping ID */
96 u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
97 u_int cpu_procinfo2 = 0; /* Multicore info */
98 char cpu_vendor[20] = ""; /* CPU Origin code */
99 u_int cpu_vendor_id = 0; /* CPU vendor ID */
100 u_int cpu_clflush_line_size = 32;
102 SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
103 &via_feature_rng, 0, "VIA RNG feature available in CPU");
104 SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD,
105 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU");
107 #ifdef CPU_ENABLE_SSE
108 u_int cpu_fxsr; /* SSE enabled */
109 u_int cpu_mxcsr_mask; /* valid bits in mxcsr */
117 init_bluelightning(void)
121 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
122 need_post_dma_flush = 1;
125 saveintr = intr_disable();
127 load_cr0(rcr0() | CR0_CD | CR0_NW);
130 #ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE
131 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */
133 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */
135 /* Enables 13MB and 0-640KB cache. */
136 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff);
137 #ifdef CPU_BLUELIGHTNING_3X
138 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */
140 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */
143 /* Enable caching in CR0. */
144 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
146 intr_restore(saveintr);
150 * Cyrix 486SLC/DLC/SR/DR series
158 saveintr = intr_disable();
161 ccr0 = read_cyrix_reg(CCR0);
162 #ifndef CYRIX_CACHE_WORKS
163 ccr0 |= CCR0_NC1 | CCR0_BARB;
164 write_cyrix_reg(CCR0, ccr0);
168 #ifndef CYRIX_CACHE_REALLY_WORKS
169 ccr0 |= CCR0_NC1 | CCR0_BARB;
173 #ifdef CPU_DIRECT_MAPPED_CACHE
174 ccr0 |= CCR0_CO; /* Direct mapped mode. */
176 write_cyrix_reg(CCR0, ccr0);
178 /* Clear non-cacheable region. */
179 write_cyrix_reg(NCR1+2, NCR_SIZE_0K);
180 write_cyrix_reg(NCR2+2, NCR_SIZE_0K);
181 write_cyrix_reg(NCR3+2, NCR_SIZE_0K);
182 write_cyrix_reg(NCR4+2, NCR_SIZE_0K);
184 write_cyrix_reg(0, 0); /* dummy write */
186 /* Enable caching in CR0. */
187 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
189 #endif /* !CYRIX_CACHE_WORKS */
190 intr_restore(saveintr);
195 * Cyrix 486S/DX series
203 saveintr = intr_disable();
206 ccr2 = read_cyrix_reg(CCR2);
208 ccr2 |= CCR2_SUSP_HLT;
212 /* Enables WB cache interface pin and Lock NW bit in CR0. */
213 ccr2 |= CCR2_WB | CCR2_LOCK_NW;
214 /* Unlock NW bit in CR0. */
215 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
216 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
219 write_cyrix_reg(CCR2, ccr2);
220 intr_restore(saveintr);
231 u_char ccr2, ccr3, ccr4, pcr0;
233 saveintr = intr_disable();
235 load_cr0(rcr0() | CR0_CD | CR0_NW);
238 (void)read_cyrix_reg(CCR3); /* dummy */
240 /* Initialize CCR2. */
241 ccr2 = read_cyrix_reg(CCR2);
244 ccr2 |= CCR2_SUSP_HLT;
246 ccr2 &= ~CCR2_SUSP_HLT;
249 write_cyrix_reg(CCR2, ccr2);
251 /* Initialize CCR4. */
252 ccr3 = read_cyrix_reg(CCR3);
253 write_cyrix_reg(CCR3, CCR3_MAPEN0);
255 ccr4 = read_cyrix_reg(CCR4);
258 #ifdef CPU_FASTER_5X86_FPU
259 ccr4 |= CCR4_FASTFPE;
261 ccr4 &= ~CCR4_FASTFPE;
263 ccr4 &= ~CCR4_IOMASK;
264 /********************************************************************
265 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time
266 * should be 0 for errata fix.
267 ********************************************************************/
269 ccr4 |= CPU_IORT & CCR4_IOMASK;
271 write_cyrix_reg(CCR4, ccr4);
273 /* Initialize PCR0. */
274 /****************************************************************
275 * WARNING: RSTK_EN and LOOP_EN could make your system unstable.
276 * BTB_EN might make your system unstable.
277 ****************************************************************/
278 pcr0 = read_cyrix_reg(PCR0);
295 /****************************************************************
296 * WARNING: if you use a memory mapped I/O device, don't use
297 * DISABLE_5X86_LSSER option, which may reorder memory mapped
299 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER.
300 ****************************************************************/
301 #ifdef CPU_DISABLE_5X86_LSSER
306 write_cyrix_reg(PCR0, pcr0);
309 write_cyrix_reg(CCR3, ccr3);
311 (void)read_cyrix_reg(0x80); /* dummy */
313 /* Unlock NW bit in CR0. */
314 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
315 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */
316 /* Lock NW bit in CR0. */
317 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
319 intr_restore(saveintr);
322 #ifdef CPU_I486_ON_386
324 * There are i486 based upgrade products for i386 machines.
325 * In this case, BIOS doesn't enable CPU cache.
328 init_i486_on_386(void)
332 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
333 need_post_dma_flush = 1;
336 saveintr = intr_disable();
338 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */
340 intr_restore(saveintr);
347 * XXX - What should I do here? Please let me know.
355 saveintr = intr_disable();
357 load_cr0(rcr0() | CR0_CD | CR0_NW);
360 /* Initialize CCR0. */
361 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
363 /* Initialize CCR1. */
364 #ifdef CPU_CYRIX_NO_LOCK
365 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
367 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
370 /* Initialize CCR2. */
372 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
374 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
377 ccr3 = read_cyrix_reg(CCR3);
378 write_cyrix_reg(CCR3, CCR3_MAPEN0);
380 /* Initialize CCR4. */
381 ccr4 = read_cyrix_reg(CCR4);
383 ccr4 &= ~CCR4_IOMASK;
385 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
387 write_cyrix_reg(CCR4, ccr4 | 7);
390 /* Initialize CCR5. */
392 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
396 write_cyrix_reg(CCR3, ccr3);
398 /* Unlock NW bit in CR0. */
399 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
402 * Earlier revision of the 6x86 CPU could crash the system if
403 * L1 cache is in write-back mode.
405 if ((cyrix_did & 0xff00) > 0x1600)
406 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
408 /* Revision 2.6 and lower. */
409 #ifdef CYRIX_CACHE_REALLY_WORKS
410 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
412 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */
416 /* Lock NW bit in CR0. */
417 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
419 intr_restore(saveintr);
421 #endif /* I486_CPU */
425 * IDT WinChip C6/2/2A/2B/3
427 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf
438 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC.
440 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16);
441 fcr &= ~(1ULL << 11);
444 * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3.
446 if (CPUID_TO_MODEL(cpu_id) >= 8)
447 fcr |= (1 << 12) | (1 << 19) | (1 << 20);
451 cpu_feature = regs[3];
457 * Cyrix 6x86MX (code-named M2)
459 * XXX - What should I do here? Please let me know.
467 saveintr = intr_disable();
469 load_cr0(rcr0() | CR0_CD | CR0_NW);
472 /* Initialize CCR0. */
473 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
475 /* Initialize CCR1. */
476 #ifdef CPU_CYRIX_NO_LOCK
477 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK);
479 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK);
482 /* Initialize CCR2. */
484 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
486 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT);
489 ccr3 = read_cyrix_reg(CCR3);
490 write_cyrix_reg(CCR3, CCR3_MAPEN0);
492 /* Initialize CCR4. */
493 ccr4 = read_cyrix_reg(CCR4);
494 ccr4 &= ~CCR4_IOMASK;
496 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK));
498 write_cyrix_reg(CCR4, ccr4 | 7);
501 /* Initialize CCR5. */
503 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
507 write_cyrix_reg(CCR3, ccr3);
509 /* Unlock NW bit in CR0. */
510 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW);
512 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */
514 /* Lock NW bit in CR0. */
515 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW);
517 intr_restore(saveintr);
526 * Local APIC should be disabled if it is not going to be used.
528 apicbase = rdmsr(MSR_APICBASE);
529 apicbase &= ~APICBASE_ENABLED;
530 wrmsr(MSR_APICBASE, apicbase);
534 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the
540 #ifdef CPU_PPRO2CELERON
542 u_int64_t bbl_cr_ctl3;
544 saveintr = intr_disable();
546 load_cr0(rcr0() | CR0_CD | CR0_NW);
549 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
551 /* If the L2 cache is configured, do nothing. */
552 if (!(bbl_cr_ctl3 & 1)) {
553 bbl_cr_ctl3 = 0x134052bLL;
555 /* Set L2 Cache Latency (Default: 5). */
556 #ifdef CPU_CELERON_L2_LATENCY
557 #if CPU_L2_LATENCY > 15
558 #error invalid CPU_L2_LATENCY.
560 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1;
562 bbl_cr_ctl3 |= 5 << 1;
564 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
567 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
568 intr_restore(saveintr);
569 #endif /* CPU_PPRO2CELERON */
573 * Initialize special VIA features
582 * Explicitly enable CX8 and PGE on C3.
584 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf
586 if (CPUID_TO_MODEL(cpu_id) <= 9)
587 fcr = (1 << 1) | (1 << 7);
592 * Check extended CPUID for PadLock features.
594 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf
596 do_cpuid(0xc0000000, regs);
597 if (regs[0] >= 0xc0000001) {
598 do_cpuid(0xc0000001, regs);
603 /* Enable RNG if present. */
604 if ((val & VIA_CPUID_HAS_RNG) != 0) {
605 via_feature_rng = VIA_HAS_RNG;
606 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG);
609 /* Enable PadLock if present. */
610 if ((val & VIA_CPUID_HAS_ACE) != 0)
611 via_feature_xcrypt |= VIA_HAS_AES;
612 if ((val & VIA_CPUID_HAS_ACE2) != 0)
613 via_feature_xcrypt |= VIA_HAS_AESCTR;
614 if ((val & VIA_CPUID_HAS_PHE) != 0)
615 via_feature_xcrypt |= VIA_HAS_SHA;
616 if ((val & VIA_CPUID_HAS_PMM) != 0)
617 via_feature_xcrypt |= VIA_HAS_MM;
618 if (via_feature_xcrypt != 0)
621 wrmsr(0x1107, rdmsr(0x1107) | fcr);
624 #endif /* I686_CPU */
626 #if defined(I586_CPU) || defined(I686_CPU)
632 /* Expose all hidden features. */
633 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL);
635 cpu_feature = regs[3];
640 * Initialize CR4 (Control register 4) to enable SSE instructions.
645 #if defined(CPU_ENABLE_SSE)
646 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
647 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
648 cpu_fxsr = hw_instruction_sse = 1;
660 init_bluelightning();
671 #ifdef CPU_I486_ON_386
679 #endif /* I486_CPU */
682 switch (cpu_vendor_id) {
683 case CPU_VENDOR_CENTAUR:
686 case CPU_VENDOR_TRANSMETA:
697 switch (cpu_vendor_id) {
698 case CPU_VENDOR_INTEL:
699 switch (cpu_id & 0xff0) {
708 #ifdef CPU_ATHLON_SSE_HACK
711 * Sometimes the BIOS doesn't enable SSE instructions.
712 * According to AMD document 20734, the mobile
713 * Duron, the (mobile) Athlon 4 and the Athlon MP
714 * support SSE. These correspond to cpu_id 0x66X
717 if ((cpu_feature & CPUID_XMM) == 0 &&
718 ((cpu_id & ~0xf) == 0x660 ||
719 (cpu_id & ~0xf) == 0x670 ||
720 (cpu_id & ~0xf) == 0x680)) {
722 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
724 cpu_feature = regs[3];
728 case CPU_VENDOR_CENTAUR:
731 case CPU_VENDOR_TRANSMETA:
736 if ((amd_feature & AMDID_NX) != 0) {
739 msr = rdmsr(MSR_EFER) | EFER_NXE;
740 wrmsr(MSR_EFER, msr);
752 * CPUID with %eax = 1, %ebx returns
753 * Bits 15-8: CLFLUSH line size
754 * (Value * 8 = cache line size in bytes)
756 if ((cpu_feature & CPUID_CLFSH) != 0)
757 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8;
759 * XXXKIB: (temporary) hack to work around traps generated
760 * when CLFLUSHing APIC register window under virtualization
761 * environments. These environments tend to disable the
762 * CPUID_SS feature even though the native CPU supports it.
764 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable);
765 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1)
766 cpu_feature &= ~CPUID_CLFSH;
768 * Allow to disable CLFLUSH feature manually by
769 * hw.clflush_disable tunable.
771 if (hw_clflush_disable == 1)
772 cpu_feature &= ~CPUID_CLFSH;
774 #if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
776 * OS should flush L1 cache by itself because no PC-98 supports
777 * non-Intel CPUs. Use wbinvd instruction before DMA transfer
778 * when need_pre_dma_flush = 1, use invd instruction after DMA
779 * transfer when need_post_dma_flush = 1. If your CPU upgrade
780 * product supports hardware cache control, you can add the
781 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file.
782 * This option eliminates unneeded cache flush instruction(s).
784 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
788 need_post_dma_flush = 1;
791 need_pre_dma_flush = 1;
794 need_pre_dma_flush = 1;
795 #ifdef CPU_I486_ON_386
796 need_post_dma_flush = 1;
803 } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
804 switch (cpu_id & 0xFF0) {
805 case 0x470: /* Enhanced Am486DX2 WB */
806 case 0x490: /* Enhanced Am486DX4 WB */
807 case 0x4F0: /* Am5x86 WB */
808 need_pre_dma_flush = 1;
811 } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
812 need_post_dma_flush = 1;
814 #ifdef CPU_I486_ON_386
815 need_pre_dma_flush = 1;
818 #endif /* PC98 && !CPU_UPGRADE_HW_CACHE */
821 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
823 * Enable write allocate feature of AMD processors.
824 * Following two functions require the Maxmem variable being set.
827 enable_K5_wt_alloc(void)
833 * Write allocate is supported only on models 1, 2, and 3, with
834 * a stepping of 4 or greater.
836 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
837 saveintr = intr_disable();
838 msr = rdmsr(0x83); /* HWCR */
839 wrmsr(0x83, msr & !(0x10));
842 * We have to tell the chip where the top of memory is,
843 * since video cards could have frame bufferes there,
844 * memory-mapped I/O could be there, etc.
850 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE;
852 if (!(inb(0x43b) & 4)) {
853 wrmsr(0x86, 0x0ff00f0);
854 msr |= AMD_WT_ALLOC_PRE;
858 * There is no way to know wheter 15-16M hole exists or not.
859 * Therefore, we disable write allocate for this range.
861 wrmsr(0x86, 0x0ff00f0);
862 msr |= AMD_WT_ALLOC_PRE;
867 wrmsr(0x83, msr|0x10); /* enable write allocate */
868 intr_restore(saveintr);
873 enable_K6_wt_alloc(void)
879 saveintr = intr_disable();
882 #ifdef CPU_DISABLE_CACHE
884 * Certain K6-2 box becomes unstable when write allocation is
888 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
889 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
890 * All other bits in TR12 have no effect on the processer's operation.
891 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
894 wrmsr(0x0000000e, (u_int64_t)0x0008);
896 /* Don't assume that memory size is aligned with 4M. */
898 size = ((Maxmem >> 8) + 3) >> 2;
902 /* Limit is 508M bytes. */
905 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1);
907 #if defined(PC98) || defined(NO_MEMORY_HOLE)
908 if (whcr & (0x7fLL << 1)) {
911 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
914 if (!(inb(0x43b) & 4))
922 * There is no way to know wheter 15-16M hole exists or not.
923 * Therefore, we disable write allocate for this range.
927 wrmsr(0x0c0000082, whcr);
929 intr_restore(saveintr);
933 enable_K6_2_wt_alloc(void)
939 saveintr = intr_disable();
942 #ifdef CPU_DISABLE_CACHE
944 * Certain K6-2 box becomes unstable when write allocation is
948 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12),
949 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported.
950 * All other bits in TR12 have no effect on the processer's operation.
951 * The I/O Trap Restart function (bit 9 of TR12) is always enabled
954 wrmsr(0x0000000e, (u_int64_t)0x0008);
956 /* Don't assume that memory size is aligned with 4M. */
958 size = ((Maxmem >> 8) + 3) >> 2;
962 /* Limit is 4092M bytes. */
965 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22);
967 #if defined(PC98) || defined(NO_MEMORY_HOLE)
968 if (whcr & (0x3ffLL << 22)) {
971 * If bit 2 of port 0x43b is 0, disable wrte allocate for the
974 if (!(inb(0x43b) & 4))
975 whcr &= ~(1LL << 16);
982 * There is no way to know wheter 15-16M hole exists or not.
983 * Therefore, we disable write allocate for this range.
985 whcr &= ~(1LL << 16);
987 wrmsr(0x0c0000082, whcr);
989 intr_restore(saveintr);
991 #endif /* I585_CPU && CPU_WT_ALLOC */
997 DB_SHOW_COMMAND(cyrixreg, cyrixreg)
1001 u_char ccr1, ccr2, ccr3;
1002 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0;
1005 if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1006 saveintr = intr_disable();
1009 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) {
1010 ccr0 = read_cyrix_reg(CCR0);
1012 ccr1 = read_cyrix_reg(CCR1);
1013 ccr2 = read_cyrix_reg(CCR2);
1014 ccr3 = read_cyrix_reg(CCR3);
1015 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1016 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1017 ccr4 = read_cyrix_reg(CCR4);
1018 if ((cpu == CPU_M1) || (cpu == CPU_M2))
1019 ccr5 = read_cyrix_reg(CCR5);
1021 pcr0 = read_cyrix_reg(PCR0);
1022 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */
1024 intr_restore(saveintr);
1026 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX))
1027 printf("CCR0=%x, ", (u_int)ccr0);
1029 printf("CCR1=%x, CCR2=%x, CCR3=%x",
1030 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
1031 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
1032 printf(", CCR4=%x, ", (u_int)ccr4);
1033 if (cpu == CPU_M1SC)
1034 printf("PCR0=%x\n", pcr0);
1036 printf("CCR5=%x\n", ccr5);
1039 printf("CR0=%x\n", cr0);