2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 * Derived from uart_dev_ns8250.c
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
43 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
44 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
45 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
46 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
47 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
48 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
49 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
50 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
51 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 #include <sys/cdefs.h>
58 __FBSDID("$FreeBSD$");
60 #include <sys/param.h>
61 #include <sys/systm.h>
64 #include <machine/bus.h>
65 #include <machine/pcpu.h>
67 #include <dev/uart/uart.h>
68 #include <dev/uart/uart_cpu.h>
69 #include <dev/uart/uart_bus.h>
71 #include <dev/ic/ns16550.h>
73 #include <mips/cavium/octeon_pcmap_regs.h>
75 #include <contrib/octeon-sdk/cvmx.h>
76 #include <contrib/octeon-sdk/cvmx-interrupt.h>
81 * Clear pending interrupts. THRE is cleared by reading IIR. Data
82 * that may have been received gets lost here.
85 oct16550_clrint (struct uart_bas *bas)
89 iir = uart_getreg(bas, REG_IIR);
90 while ((iir & IIR_NOPEND) == 0) {
93 (void)uart_getreg(bas, REG_LSR);
94 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
95 (void)uart_getreg(bas, REG_DATA);
96 else if (iir == IIR_MLSC)
97 (void)uart_getreg(bas, REG_MSR);
98 else if (iir == IIR_BUSY)
99 (void) uart_getreg(bas, REG_USR);
101 iir = uart_getreg(bas, REG_IIR);
105 static int delay_changed = 1;
108 oct16550_delay (struct uart_bas *bas)
112 static int delay = 0;
114 if (!delay_changed) return delay;
116 lcr = uart_getreg(bas, REG_LCR);
117 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
119 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
121 uart_setreg(bas, REG_LCR, lcr);
125 return 10; /* return an approx delay value */
127 /* 1/10th the time to transmit 1 character (estimate). */
129 return (16000000 * divisor / bas->rclk);
130 return (16000 * divisor / (bas->rclk / 1000));
135 oct16550_divisor (int rclk, int baudrate)
137 int actual_baud, divisor;
143 divisor = (rclk / (baudrate << 3) + 1) >> 1;
144 if (divisor == 0 || divisor >= 65536)
146 actual_baud = rclk / (divisor << 4);
148 /* 10 times error in percent: */
149 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
151 /* 3.0% maximum error tolerance: */
152 if (error < -30 || error > 30)
159 oct16550_drain (struct uart_bas *bas, int what)
163 delay = oct16550_delay(bas);
165 if (what & UART_DRAIN_TRANSMITTER) {
167 * Pick an arbitrary high limit to avoid getting stuck in
168 * an infinite loop when the hardware is broken. Make the
169 * limit high enough to handle large FIFOs.
171 limit = 10*10*10*1024;
172 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
175 /* printf("oct16550: transmitter appears stuck... "); */
180 if (what & UART_DRAIN_RECEIVER) {
182 * Pick an arbitrary high limit to avoid getting stuck in
183 * an infinite loop when the hardware is broken. Make the
184 * limit high enough to handle large FIFOs and integrated
185 * UARTs. The HP rx2600 for example has 3 UARTs on the
186 * management board that tend to get a lot of data send
187 * to it when the UART is first activated.
190 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
191 (void)uart_getreg(bas, REG_DATA);
196 /* printf("oct16550: receiver appears broken... "); */
205 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
206 * drained. WARNING: this function clobbers the FIFO setting!
209 oct16550_flush (struct uart_bas *bas, int what)
214 if (what & UART_FLUSH_TRANSMITTER)
216 if (what & UART_FLUSH_RECEIVER)
218 uart_setreg(bas, REG_FCR, fcr);
223 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
232 else if (databits == 7)
234 else if (databits == 6)
244 divisor = oct16550_divisor(bas->rclk, baudrate);
247 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
249 uart_setreg(bas, REG_DLL, divisor & 0xff);
250 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
255 /* Set LCR and clear DLAB. */
256 uart_setreg(bas, REG_LCR, lcr);
262 * Low-level UART interface.
264 static int oct16550_probe(struct uart_bas *bas);
265 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
266 static void oct16550_term(struct uart_bas *bas);
267 static void oct16550_putc(struct uart_bas *bas, int);
268 static int oct16550_rxready(struct uart_bas *bas);
269 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
271 struct uart_ops uart_oct16550_ops = {
272 .probe = oct16550_probe,
273 .init = oct16550_init,
274 .term = oct16550_term,
275 .putc = oct16550_putc,
276 .rxready = oct16550_rxready,
277 .getc = oct16550_getc,
281 oct16550_probe (struct uart_bas *bas)
285 /* Check known 0 bits that don't depend on DLAB. */
286 val = uart_getreg(bas, REG_IIR);
289 val = uart_getreg(bas, REG_MCR);
292 val = uart_getreg(bas, REG_USR);
299 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
304 oct16550_param(bas, baudrate, databits, stopbits, parity);
306 /* Disable all interrupt sources. */
307 ier = uart_getreg(bas, REG_IER) & 0x0;
308 uart_setreg(bas, REG_IER, ier);
311 /* Disable the FIFO (if present). */
312 // uart_setreg(bas, REG_FCR, 0);
316 uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
319 oct16550_clrint(bas);
323 oct16550_term (struct uart_bas *bas)
326 /* Clear RTS & DTR. */
327 uart_setreg(bas, REG_MCR, 0);
331 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
333 while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
334 ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
339 oct16550_putc (struct uart_bas *bas, int c)
343 /* 1/10th the time to transmit 1 character (estimate). */
344 delay = oct16550_delay(bas);
345 oct16550_wait_txhr_empty(bas, 100, delay);
346 uart_setreg(bas, REG_DATA, c);
348 oct16550_wait_txhr_empty(bas, 100, delay);
352 oct16550_rxready (struct uart_bas *bas)
355 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
359 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
365 /* 1/10th the time to transmit 1 character (estimate). */
366 delay = oct16550_delay(bas);
368 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
374 c = uart_getreg(bas, REG_DATA);
382 * High-level UART interface.
384 struct oct16550_softc {
385 struct uart_softc base;
391 static int oct16550_bus_attach(struct uart_softc *);
392 static int oct16550_bus_detach(struct uart_softc *);
393 static int oct16550_bus_flush(struct uart_softc *, int);
394 static int oct16550_bus_getsig(struct uart_softc *);
395 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
396 static int oct16550_bus_ipend(struct uart_softc *);
397 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
398 static int oct16550_bus_probe(struct uart_softc *);
399 static int oct16550_bus_receive(struct uart_softc *);
400 static int oct16550_bus_setsig(struct uart_softc *, int);
401 static int oct16550_bus_transmit(struct uart_softc *);
403 static kobj_method_t oct16550_methods[] = {
404 KOBJMETHOD(uart_attach, oct16550_bus_attach),
405 KOBJMETHOD(uart_detach, oct16550_bus_detach),
406 KOBJMETHOD(uart_flush, oct16550_bus_flush),
407 KOBJMETHOD(uart_getsig, oct16550_bus_getsig),
408 KOBJMETHOD(uart_ioctl, oct16550_bus_ioctl),
409 KOBJMETHOD(uart_ipend, oct16550_bus_ipend),
410 KOBJMETHOD(uart_param, oct16550_bus_param),
411 KOBJMETHOD(uart_probe, oct16550_bus_probe),
412 KOBJMETHOD(uart_receive, oct16550_bus_receive),
413 KOBJMETHOD(uart_setsig, oct16550_bus_setsig),
414 KOBJMETHOD(uart_transmit, oct16550_bus_transmit),
418 struct uart_class uart_oct16550_class = {
421 sizeof(struct oct16550_softc),
422 .uc_ops = &uart_oct16550_ops,
427 #define SIGCHG(c, i, s, d) \
429 i |= (i & s) ? s : s | d; \
431 i = (i & s) ? (i & ~s) | d : i; \
435 oct16550_bus_attach (struct uart_softc *sc)
437 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
438 struct uart_bas *bas;
441 unit = device_get_unit(sc->sc_dev);
444 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
445 oct16550->mcr = uart_getreg(bas, REG_MCR);
446 oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
447 uart_setreg(bas, REG_FCR, oct16550->fcr);
449 oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
451 if (oct16550->mcr & MCR_DTR)
452 sc->sc_hwsig |= SER_DTR;
453 if (oct16550->mcr & MCR_RTS)
454 sc->sc_hwsig |= SER_RTS;
455 oct16550_bus_getsig(sc);
457 oct16550_clrint(bas);
458 oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
459 oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
460 uart_setreg(bas, REG_IER, oct16550->ier);
464 * Enable the interrupt in CIU. // UART-x2 @ IP2
468 cvmx_interrupt_unmask_irq(CVMX_IRQ_UART0);
471 cvmx_interrupt_unmask_irq(CVMX_IRQ_UART1);
474 panic("%s: invalid UART %d", __func__, unit);
480 oct16550_bus_detach (struct uart_softc *sc)
482 struct uart_bas *bas;
486 ier = uart_getreg(bas, REG_IER) & 0xf0;
487 uart_setreg(bas, REG_IER, ier);
489 oct16550_clrint(bas);
494 oct16550_bus_flush (struct uart_softc *sc, int what)
496 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
497 struct uart_bas *bas;
501 uart_lock(sc->sc_hwmtx);
502 if (sc->sc_rxfifosz > 1) {
503 oct16550_flush(bas, what);
504 uart_setreg(bas, REG_FCR, oct16550->fcr);
508 error = oct16550_drain(bas, what);
509 uart_unlock(sc->sc_hwmtx);
514 oct16550_bus_getsig (struct uart_softc *sc)
516 uint32_t new, old, sig;
522 uart_lock(sc->sc_hwmtx);
523 msr = uart_getreg(&sc->sc_bas, REG_MSR);
524 uart_unlock(sc->sc_hwmtx);
525 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
526 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
527 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
528 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
529 new = sig & ~SER_MASK_DELTA;
530 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
535 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
537 struct uart_bas *bas;
538 int baudrate, divisor, error;
543 uart_lock(sc->sc_hwmtx);
545 case UART_IOCTL_BREAK:
546 lcr = uart_getreg(bas, REG_LCR);
551 uart_setreg(bas, REG_LCR, lcr);
554 case UART_IOCTL_IFLOW:
555 lcr = uart_getreg(bas, REG_LCR);
557 uart_setreg(bas, REG_LCR, 0xbf);
559 efr = uart_getreg(bas, REG_EFR);
564 uart_setreg(bas, REG_EFR, efr);
566 uart_setreg(bas, REG_LCR, lcr);
569 case UART_IOCTL_OFLOW:
570 lcr = uart_getreg(bas, REG_LCR);
572 uart_setreg(bas, REG_LCR, 0xbf);
574 efr = uart_getreg(bas, REG_EFR);
579 uart_setreg(bas, REG_EFR, efr);
581 uart_setreg(bas, REG_LCR, lcr);
584 case UART_IOCTL_BAUD:
585 lcr = uart_getreg(bas, REG_LCR);
586 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
588 divisor = uart_getreg(bas, REG_DLL) |
589 (uart_getreg(bas, REG_DLH) << 8);
591 uart_setreg(bas, REG_LCR, lcr);
593 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
596 *(int*)data = baudrate;
604 uart_unlock(sc->sc_hwmtx);
610 oct16550_bus_ipend(struct uart_softc *sc)
612 struct uart_bas *bas;
617 uart_lock(sc->sc_hwmtx);
619 iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
620 if (iir != IIR_NOPEND) {
622 if (iir == IIR_RLS) {
623 lsr = uart_getreg(bas, REG_LSR);
625 ipend |= SER_INT_OVERRUN;
627 ipend |= SER_INT_BREAK;
629 ipend |= SER_INT_RXREADY;
631 } else if (iir == IIR_RXRDY) {
632 ipend |= SER_INT_RXREADY;
634 } else if (iir == IIR_RXTOUT) {
635 ipend |= SER_INT_RXREADY;
637 } else if (iir == IIR_TXRDY) {
638 ipend |= SER_INT_TXIDLE;
640 } else if (iir == IIR_MLSC) {
641 ipend |= SER_INT_SIGCHG;
643 } else if (iir == IIR_BUSY) {
644 (void) uart_getreg(bas, REG_USR);
647 uart_unlock(sc->sc_hwmtx);
649 //#define OCTEON_VISUAL_UART 1
650 #ifdef OCTEON_VISUAL_UART
651 static int where1 = 0;
653 if (ipend) octeon_led_run_wheel(&where1, 6 + device_get_unit(sc->sc_dev));
660 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
661 int stopbits, int parity)
663 struct uart_bas *bas;
667 uart_lock(sc->sc_hwmtx);
668 error = oct16550_param(bas, baudrate, databits, stopbits, parity);
669 uart_unlock(sc->sc_hwmtx);
674 oct16550_bus_probe (struct uart_softc *sc)
676 struct uart_bas *bas;
680 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_sysinfo_get()->cpu_clock_hz;
682 error = oct16550_probe(bas);
687 uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
690 * Enable FIFOs. And check that the UART has them. If not, we're
691 * done. Since this is the first time we enable the FIFOs, we reset
694 oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
695 #define ENABLE_OCTEON_FIFO 1
696 #ifdef ENABLE_OCTEON_FIFO
697 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
701 oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
703 if (device_get_unit(sc->sc_dev)) {
704 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
706 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
708 #ifdef ENABLE_OCTEON_FIFO
709 sc->sc_rxfifosz = 64;
710 sc->sc_txfifosz = 64;
719 * XXX there are some issues related to hardware flow control and
720 * it's likely that uart(4) is the cause. This basicly needs more
721 * investigation, but we avoid using for hardware flow control
724 /* 16650s or higher have automatic flow control. */
725 if (sc->sc_rxfifosz > 16) {
735 oct16550_bus_receive (struct uart_softc *sc)
737 struct uart_bas *bas;
742 uart_lock(sc->sc_hwmtx);
743 lsr = uart_getreg(bas, REG_LSR);
745 while (lsr & LSR_RXRDY) {
746 if (uart_rx_full(sc)) {
747 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
750 xc = uart_getreg(bas, REG_DATA);
752 xc |= UART_STAT_FRAMERR;
754 xc |= UART_STAT_PARERR;
756 lsr = uart_getreg(bas, REG_LSR);
758 /* Discard everything left in the Rx FIFO. */
760 * First do a dummy read/discard anyway, in case the UART was lying to us.
761 * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
762 * Results in a stuck ipend loop.
764 (void)uart_getreg(bas, REG_DATA);
765 while (lsr & LSR_RXRDY) {
766 (void)uart_getreg(bas, REG_DATA);
768 lsr = uart_getreg(bas, REG_LSR);
770 uart_unlock(sc->sc_hwmtx);
775 oct16550_bus_setsig (struct uart_softc *sc, int sig)
777 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
778 struct uart_bas *bas;
785 if (sig & SER_DDTR) {
786 SIGCHG(sig & SER_DTR, new, SER_DTR,
789 if (sig & SER_DRTS) {
790 SIGCHG(sig & SER_RTS, new, SER_RTS,
793 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
794 uart_lock(sc->sc_hwmtx);
795 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
797 oct16550->mcr |= MCR_DTR;
799 oct16550->mcr |= MCR_RTS;
800 uart_setreg(bas, REG_MCR, oct16550->mcr);
802 uart_unlock(sc->sc_hwmtx);
807 oct16550_bus_transmit (struct uart_softc *sc)
809 struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
810 struct uart_bas *bas;
814 uart_lock(sc->sc_hwmtx);
815 #ifdef NO_UART_INTERRUPTS
816 for (i = 0; i < sc->sc_txdatasz; i++) {
817 oct16550_putc(bas, sc->sc_txbuf[i]);
821 oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
822 uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
825 for (i = 0; i < sc->sc_txdatasz; i++) {
826 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
831 uart_unlock(sc->sc_hwmtx);