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32 #ifndef __NLM_FMNV2_H__
33 #define __NLM_FMNV2_H__
37 * @author Netlogic Microsystems
38 * @brief HAL for Fast message network V2
41 /* FMN configuration registers */
42 #define CMS_OUTPUTQ_CONFIG(i) ((i)*2)
43 #define CMS_MAX_OUTPUTQ 1024
44 #define CMS_OUTPUTQ_CREDIT_CFG (0x2000/4)
45 #define CMS_MSG_CONFIG (0x2008/4)
46 #define CMS_MSG_ERR (0x2010/4)
47 #define CMS_TRACE_CONFIG (0x2018/4)
48 #define CMS_TRACE_BASE_ADDR (0x2020/4)
49 #define CMS_TRACE_LIMIT_ADDR (0x2028/4)
50 #define CMS_TRACE_CURRENT_ADDR (0x2030/4)
51 #define CMS_MSG_ENDIAN_SWAP (0x2038/4)
53 #define CMS_CPU_PUSHQ(node, core, thread, vc) \
54 (((node)<<10) | ((core)<<4) | ((thread)<<2) | ((vc)<<0))
55 #define CMS_POPQ(node, queue) (((node)<<10) | (queue))
56 #define CMS_IO_PUSHQ(node, queue) (((node)<<10) | (queue))
58 #define CMS_POPQ_QID(i) (128+(i))
59 #define CMS_POPQ_MAXQID 255
60 #define CMS_PCIE0_QID(i) (256+(i))
61 #define CMS_PCIE0_MAXQID 257
62 #define CMS_PCIE1_QID(i) (258+(i))
63 #define CMS_PCIE1_MAXQID 259
64 #define CMS_PCIE2_QID(i) (260+(i))
65 #define CMS_PCIE2_MAXQID 261
66 #define CMS_PCIE3_QID(i) (262+(i))
67 #define CMS_PCIE3_MAXQID 263
68 #define CMS_DTE_QID(i) (264+(i))
69 #define CMS_DTE_MAXQID 267
70 #define CMS_RSA_ECC_QID(i) (272+(i))
71 #define CMS_RSA_ECC_MAXQID 280
72 #define CMS_CRYPTO_QID(i) (281+(i))
73 #define CMS_CRYPTO_MAXQID 296
74 /* TODO PCI header register 0x3C says CMP starts at 297(0x129) VERIFY */
75 #define CMS_CMP_QID(i) (298+(i))
76 #define CMS_CMP_MAXQID 305
77 #define CMS_POE_QID(i) (384+(i))
78 #define CMS_POE_MAXQID 391
79 #define CMS_NAE_QID(i) (476+(i))
80 #define CMS_NAE_MAXQID 1023
82 #define CMS_NAE_TX_VC_BASE 476
83 #define CMS_NAE_TX_VC_LIMIT 999
84 #define CMS_NAE_RX_VC_BASE 1000
85 #define CMS_NAE_RX_VC_LIMIT 1019
87 #define MAX_CMS_QUEUES 1024
89 /* FMN Level Interrupt Type */
90 #define CMS_LVL_INTR_DISABLE 0
91 #define CMS_LVL_LOW_WATERMARK 1
92 #define CMS_LVL_HI_WATERMARK 2
94 /* FMN Level interrupt trigger values */
95 #define CMS_QUEUE_NON_EMPTY 0
96 #define CMS_QUEUE_QUARTER_FULL 1
97 #define CMS_QUEUE_HALF_FULL 2
98 #define CMS_QUEUE_THREE_QUARTER_FULL 3
99 #define CMS_QUEUE_FULL 4
101 /* FMN Timer Interrupt Type */
102 #define CMS_TIMER_INTR_DISABLE 0
103 #define CMS_TIMER_CONSUMER 1
104 #define CMS_TIMER_PRODUCER 1
106 /* FMN timer interrupt trigger values */
107 #define CMS_TWO_POW_EIGHT_CYCLES 0
108 #define CMS_TWO_POW_TEN_CYCLES 1
109 #define CMS_TWO_POW_TWELVE_CYCLES 2
110 #define CMS_TWO_POW_FOURTEEN_CYCLES 3
111 #define CMS_TWO_POW_SIXTEEN_CYCLES 4
112 #define CMS_TWO_POW_EIGHTTEEN_CYCLES 5
113 #define CMS_TWO_POW_TWENTY_CYCLES 6
114 #define CMS_TWO_POW_TWENTYTWO_CYCLES 7
116 #define CMS_QUEUE_ENA 1ULL
117 #define CMS_QUEUE_DIS 0
118 #define CMS_SPILL_ENA 1ULL
119 #define CMS_SPILL_DIS 0
121 #define CMS_MAX_VCPU_VC 4
123 /* Each XLP chip can hold upto 32K messages on the chip itself */
124 #define CMS_ON_CHIP_MESG_SPACE (32*1024)
125 #define CMS_ON_CHIP_PER_QUEUE_SPACE \
126 ((CMS_ON_CHIP_MESG_SPACE)/(MAX_CMS_QUEUES))
127 #define CMS_MAX_ONCHIP_SEGMENTS 1024
128 #define CMS_MAX_SPILL_SEGMENTS_PER_QUEUE 64
130 /* FMN Network error */
131 #define CMS_ILLEGAL_DST_ERROR 0x100
132 #define CMS_BIU_TIMEOUT_ERROR 0x080
133 #define CMS_BIU_ERROR 0x040
134 #define CMS_SPILL_FILL_UNCORRECT_ECC_ERROR 0x020
135 #define CMS_SPILL_FILL_CORRECT_ECC_ERROR 0x010
136 #define CMS_SPILL_UNCORRECT_ECC_ERROR 0x008
137 #define CMS_SPILL_CORRECT_ECC_ERROR 0x004
138 #define CMS_OUTPUTQ_UNCORRECT_ECC_ERROR 0x002
139 #define CMS_OUTPUTQ_CORRECT_ECC_ERROR 0x001
141 /* worst case, a single entry message consists of a 4 byte header
142 * and an 8-byte entry = 12 bytes in total
144 #define CMS_SINGLE_ENTRY_MSG_SIZE 12
145 /* total spill memory needed for one FMN queue */
146 #define CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs) \
147 ((spilltotmsgs) * (CMS_SINGLE_ENTRY_MSG_SIZE))
148 /* total spill memory needed */
149 #define CMS_TOTAL_SPILL_MEM(spilltotmsgs) \
150 ((CMS_PER_QUEUE_SPILL_MEM(spilltotmsgs)) * \
152 /* total number of FMN messages possible in a queue */
153 #define CMS_TOTAL_QUEUE_SIZE(spilltotmsgs) \
154 ((spilltotmsgs) + (CMS_ON_CHIP_PER_QUEUE_SPACE))
156 /* FMN Src station id's */
157 #define CMS_CPU0_SRC_STID (0 << 4)
158 #define CMS_CPU1_SRC_STID (1 << 4)
159 #define CMS_CPU2_SRC_STID (2 << 4)
160 #define CMS_CPU3_SRC_STID (3 << 4)
161 #define CMS_CPU4_SRC_STID (4 << 4)
162 #define CMS_CPU5_SRC_STID (5 << 4)
163 #define CMS_CPU6_SRC_STID (6 << 4)
164 #define CMS_CPU7_SRC_STID (7 << 4)
165 #define CMS_PCIE0_SRC_STID 256
166 #define CMS_PCIE1_SRC_STID 258
167 #define CMS_PCIE2_SRC_STID 260
168 #define CMS_PCIE3_SRC_STID 262
169 #define CMS_DTE_SRC_STID 264
170 #define CMS_RSA_ECC_SRC_STID 272
171 #define CMS_CRYPTO_SRC_STID 281
172 #define CMS_CMP_SRC_STID 298
173 #define CMS_POE_SRC_STID 384
174 #define CMS_NAE_SRC_STID 476
176 #define CMS_DEFAULT_CREDIT(cmstotstns,spilltotmsgs) \
177 ((CMS_TOTAL_QUEUE_SIZE(spilltotmsgs)) / \
180 #define CMS_DEFAULT_CREDIT(cmstotstns,spilltotmsgs) 8
182 /* POPQ related defines */
183 #define CMS_POPQID_START 128
184 #define CMS_POPQID_END 255
186 #define CMS_INT_RCVD 0x800000000000000ULL
188 #define nlm_read_cms_reg(b, r) nlm_read_reg64_xkphys(b,r)
189 #define nlm_write_cms_reg(b, r, v) nlm_write_reg64_xkphys(b,r,v)
190 #define nlm_get_cms_pcibase(node) nlm_pcicfg_base(XLP_IO_CMS_OFFSET(node))
191 #define nlm_get_cms_regbase(node) nlm_xkphys_map_pcibar0(nlm_get_cms_pcibase(node))
239 extern uint64_t nlm_cms_spill_total_messages;
240 extern uint32_t nlm_cms_total_stations;
241 extern uint32_t cms_onchip_seg_availability[CMS_ON_CHIP_PER_QUEUE_SPACE];
243 extern uint64_t cms_base_addr(int node);
244 extern int nlm_cms_verify_credit_config (int spill_en, int tot_credit);
245 extern int nlm_cms_get_oc_space(int qsize, int max_queues, int qid, int *ocbase, int *ocstart, int *ocend);
246 extern void nlm_cms_setup_credits (uint64_t base, int destid, int srcid, int credit);
247 extern int nlm_cms_config_onchip_queue (uint64_t base, uint64_t cms_spill_base, int qid, int spill_en);
248 extern void nlm_cms_default_setup(int node, uint64_t spill_base, int spill_en, int popq_en);
249 extern uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid);
250 extern void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val);
251 extern void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type, int intr_val);
252 extern void nlm_cms_level_intr(int node, int sub_type, int intr_val);
253 extern void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type, int intr_val);
254 extern void nlm_cms_timer_intr(int node, int en, int sub_type, int intr_val);
255 extern int nlm_cms_outputq_intr_check(uint64_t base, int qid);
256 extern void nlm_cms_outputq_clr_intr(uint64_t base, int qid);
257 extern void nlm_cms_illegal_dst_error_intr(uint64_t base, int en);
258 extern void nlm_cms_timeout_error_intr(uint64_t base, int en);
259 extern void nlm_cms_biu_error_resp_intr(uint64_t base, int en);
260 extern void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en);
261 extern void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en);
262 extern void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en);
263 extern void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en);
264 extern uint64_t nlm_cms_network_error_status(uint64_t base);
265 extern int nlm_cms_get_net_error_code(uint64_t err);
266 extern int nlm_cms_get_net_error_syndrome(uint64_t err);
267 extern int nlm_cms_get_net_error_ramindex(uint64_t err);
268 extern int nlm_cms_get_net_error_outputq(uint64_t err);
269 extern void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base, uint64_t trace_limit, int match_dstid_en, int dst_id, int match_srcid_en, int src_id, int wrap);
270 extern void nlm_cms_endian_byte_swap (uint64_t base, int en);
271 extern uint8_t xlp_msg_send(uint8_t vc, uint8_t size);
272 extern int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
274 extern int nlm_cms_alloc_onchip_q(uint64_t base, int qid, int nsegs);