sys/pci/if_rl.c

   1 /*-
   2  * Copyright (c) 1997, 1998
   3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by Bill Paul.
  16  * 4. Neither the name of the author nor the names of any co-contributors
  17  *    may be used to endorse or promote products derived from this software
  18  *    without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  30  * THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 /*
  37  * RealTek 8129/8139 PCI NIC driver
  38  *
  39  * Supports several extremely cheap PCI 10/100 adapters based on
  40  * the RealTek chipset. Datasheets can be obtained from
  41  * www.realtek.com.tw.
  42  *
  43  * Written by Bill Paul <wpaul@ctr.columbia.edu>
  44  * Electrical Engineering Department
  45  * Columbia University, New York City
  46  */
  47 /*
  48  * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
  49  * probably the worst PCI ethernet controller ever made, with the possible
  50  * exception of the FEAST chip made by SMC. The 8139 supports bus-master
  51  * DMA, but it has a terrible interface that nullifies any performance
  52  * gains that bus-master DMA usually offers.
  53  *
  54  * For transmission, the chip offers a series of four TX descriptor
  55  * registers. Each transmit frame must be in a contiguous buffer, aligned
  56  * on a longword (32-bit) boundary. This means we almost always have to
  57  * do mbuf copies in order to transmit a frame, except in the unlikely
  58  * case where a) the packet fits into a single mbuf, and b) the packet
  59  * is 32-bit aligned within the mbuf's data area. The presence of only
  60  * four descriptor registers means that we can never have more than four
  61  * packets queued for transmission at any one time.
  62  *
  63  * Reception is not much better. The driver has to allocate a single large
  64  * buffer area (up to 64K in size) into which the chip will DMA received
  65  * frames. Because we don't know where within this region received packets
  66  * will begin or end, we have no choice but to copy data from the buffer
  67  * area into mbufs in order to pass the packets up to the higher protocol
  68  * levels.
  69  *
  70  * It's impossible given this rotten design to really achieve decent
  71  * performance at 100Mbps, unless you happen to have a 400Mhz PII or
  72  * some equally overmuscled CPU to drive it.
  73  *
  74  * On the bright side, the 8139 does have a built-in PHY, although
  75  * rather than using an MDIO serial interface like most other NICs, the
  76  * PHY registers are directly accessible through the 8139's register
  77  * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
  78  * filter.
  79  *
  80  * The 8129 chip is an older version of the 8139 that uses an external PHY
  81  * chip. The 8129 has a serial MDIO interface for accessing the MII where
  82  * the 8139 lets you directly access the on-board PHY registers. We need
  83  * to select which interface to use depending on the chip type.
  84  */
  85
  86 #ifdef HAVE_KERNEL_OPTION_HEADERS
  87 #include "opt_device_polling.h"
  88 #endif
  89
  90 #include <sys/param.h>
  91 #include <sys/endian.h>
  92 #include <sys/systm.h>
  93 #include <sys/sockio.h>
  94 #include <sys/mbuf.h>
  95 #include <sys/malloc.h>
  96 #include <sys/kernel.h>
  97 #include <sys/module.h>
  98 #include <sys/socket.h>
  99 #include <sys/sysctl.h>
 100
 101 #include <net/if.h>
 102 #include <net/if_arp.h>
 103 #include <net/ethernet.h>
 104 #include <net/if_dl.h>
 105 #include <net/if_media.h>
 106 #include <net/if_types.h>
 107
 108 #include <net/bpf.h>
 109
 110 #include <machine/bus.h>
 111 #include <machine/resource.h>
 112 #include <sys/bus.h>
 113 #include <sys/rman.h>
 114
 115 #include <dev/mii/mii.h>
 116 #include <dev/mii/miivar.h>
 117
 118 #include <dev/pci/pcireg.h>
 119 #include <dev/pci/pcivar.h>
 120
 121 MODULE_DEPEND(rl, pci, 1, 1, 1);
 122 MODULE_DEPEND(rl, ether, 1, 1, 1);
 123 MODULE_DEPEND(rl, miibus, 1, 1, 1);
 124
 125 /* "device miibus" required.  See GENERIC if you get errors here. */
 126 #include "miibus_if.h"
 127
 128 #include <pci/if_rlreg.h>
 129
 130 /*
 131  * Various supported device vendors/types and their names.
 132  */
 133 static struct rl_type rl_devs[] = {
 134         { RT_VENDORID, RT_DEVICEID_8129, RL_8129,
 135                 "RealTek 8129 10/100BaseTX" },
 136         { RT_VENDORID, RT_DEVICEID_8139, RL_8139,
 137                 "RealTek 8139 10/100BaseTX" },
 138         { RT_VENDORID, RT_DEVICEID_8139D, RL_8139,
 139                 "RealTek 8139 10/100BaseTX" },
 140         { RT_VENDORID, RT_DEVICEID_8138, RL_8139,
 141                 "RealTek 8139 10/100BaseTX CardBus" },
 142         { RT_VENDORID, RT_DEVICEID_8100, RL_8139,
 143                 "RealTek 8100 10/100BaseTX" },
 144         { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 145                 "Accton MPX 5030/5038 10/100BaseTX" },
 146         { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139,
 147                 "Delta Electronics 8139 10/100BaseTX" },
 148         { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139,
 149                 "Addtron Technology 8139 10/100BaseTX" },
 150         { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139,
 151                 "D-Link DFE-530TX+ 10/100BaseTX" },
 152         { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139,
 153                 "D-Link DFE-690TXD 10/100BaseTX" },
 154         { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139,
 155                 "Nortel Networks 10/100BaseTX" },
 156         { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139,
 157                 "Corega FEther CB-TXD" },
 158         { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139,
 159                 "Corega FEtherII CB-TXD" },
 160         { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139,
 161                 "Peppercon AG ROL-F" },
 162         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139,
 163                 "Planex FNW-3603-TX" },
 164         { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139,
 165                 "Planex FNW-3800-TX" },
 166         { CP_VENDORID, RT_DEVICEID_8139, RL_8139,
 167                 "Compaq HNE-300" },
 168         { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139,
 169                 "LevelOne FPC-0106TX" },
 170         { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139,
 171                 "Edimax EP-4103DL CardBus" }
 172 };
 173
 174 static int rl_attach(device_t);
 175 static int rl_detach(device_t);
 176 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 177 static int rl_dma_alloc(struct rl_softc *);
 178 static void rl_dma_free(struct rl_softc *);
 179 static void rl_eeprom_putbyte(struct rl_softc *, int);
 180 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
 181 static int rl_encap(struct rl_softc *, struct mbuf **);
 182 static int rl_list_tx_init(struct rl_softc *);
 183 static int rl_list_rx_init(struct rl_softc *);
 184 static int rl_ifmedia_upd(struct ifnet *);
 185 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 186 static int rl_ioctl(struct ifnet *, u_long, caddr_t);
 187 static void rl_intr(void *);
 188 static void rl_init(void *);
 189 static void rl_init_locked(struct rl_softc *sc);
 190 static void rl_mii_send(struct rl_softc *, uint32_t, int);
 191 static void rl_mii_sync(struct rl_softc *);
 192 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
 193 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
 194 static int rl_miibus_readreg(device_t, int, int);
 195 static void rl_miibus_statchg(device_t);
 196 static int rl_miibus_writereg(device_t, int, int, int);
 197 #ifdef DEVICE_POLLING
 198 static int rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 199 static int rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
 200 #endif
 201 static int rl_probe(device_t);
 202 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int);
 203 static void rl_reset(struct rl_softc *);
 204 static int rl_resume(device_t);
 205 static int rl_rxeof(struct rl_softc *);
 206 static void rl_rxfilter(struct rl_softc *);
 207 static int rl_shutdown(device_t);
 208 static void rl_start(struct ifnet *);
 209 static void rl_start_locked(struct ifnet *);
 210 static void rl_stop(struct rl_softc *);
 211 static int rl_suspend(device_t);
 212 static void rl_tick(void *);
 213 static void rl_txeof(struct rl_softc *);
 214 static void rl_watchdog(struct rl_softc *);
 215 static void rl_setwol(struct rl_softc *);
 216 static void rl_clrwol(struct rl_softc *);
 217
 218 static device_method_t rl_methods[] = {
 219         /* Device interface */
 220         DEVMETHOD(device_probe,         rl_probe),
 221         DEVMETHOD(device_attach,        rl_attach),
 222         DEVMETHOD(device_detach,        rl_detach),
 223         DEVMETHOD(device_suspend,       rl_suspend),
 224         DEVMETHOD(device_resume,        rl_resume),
 225         DEVMETHOD(device_shutdown,      rl_shutdown),
 226
 227         /* bus interface */
 228         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 229         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 230
 231         /* MII interface */
 232         DEVMETHOD(miibus_readreg,       rl_miibus_readreg),
 233         DEVMETHOD(miibus_writereg,      rl_miibus_writereg),
 234         DEVMETHOD(miibus_statchg,       rl_miibus_statchg),
 235
 236         { 0, 0 }
 237 };
 238
 239 static driver_t rl_driver = {
 240         "rl",
 241         rl_methods,
 242         sizeof(struct rl_softc)
 243 };
 244
 245 static devclass_t rl_devclass;
 246
 247 DRIVER_MODULE(rl, pci, rl_driver, rl_devclass, 0, 0);
 248 DRIVER_MODULE(rl, cardbus, rl_driver, rl_devclass, 0, 0);
 249 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
 250
 251 #define EE_SET(x)                                       \
 252         CSR_WRITE_1(sc, RL_EECMD,                       \
 253                 CSR_READ_1(sc, RL_EECMD) | x)
 254
 255 #define EE_CLR(x)                                       \
 256         CSR_WRITE_1(sc, RL_EECMD,                       \
 257                 CSR_READ_1(sc, RL_EECMD) & ~x)
 258
 259 /*
 260  * Send a read command and address to the EEPROM, check for ACK.
 261  */
 262 static void
 263 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
 264 {
 265         register int            d, i;
 266
 267         d = addr | sc->rl_eecmd_read;
 268
 269         /*
 270          * Feed in each bit and strobe the clock.
 271          */
 272         for (i = 0x400; i; i >>= 1) {
 273                 if (d & i) {
 274                         EE_SET(RL_EE_DATAIN);
 275                 } else {
 276                         EE_CLR(RL_EE_DATAIN);
 277                 }
 278                 DELAY(100);
 279                 EE_SET(RL_EE_CLK);
 280                 DELAY(150);
 281                 EE_CLR(RL_EE_CLK);
 282                 DELAY(100);
 283         }
 284 }
 285
 286 /*
 287  * Read a word of data stored in the EEPROM at address 'addr.'
 288  */
 289 static void
 290 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
 291 {
 292         register int            i;
 293         uint16_t                word = 0;
 294
 295         /* Enter EEPROM access mode. */
 296         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 297
 298         /*
 299          * Send address of word we want to read.
 300          */
 301         rl_eeprom_putbyte(sc, addr);
 302
 303         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
 304
 305         /*
 306          * Start reading bits from EEPROM.
 307          */
 308         for (i = 0x8000; i; i >>= 1) {
 309                 EE_SET(RL_EE_CLK);
 310                 DELAY(100);
 311                 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
 312                         word |= i;
 313                 EE_CLR(RL_EE_CLK);
 314                 DELAY(100);
 315         }
 316
 317         /* Turn off EEPROM access mode. */
 318         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 319
 320         *dest = word;
 321 }
 322
 323 /*
 324  * Read a sequence of words from the EEPROM.
 325  */
 326 static void
 327 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap)
 328 {
 329         int                     i;
 330         uint16_t                word = 0, *ptr;
 331
 332         for (i = 0; i < cnt; i++) {
 333                 rl_eeprom_getword(sc, off + i, &word);
 334                 ptr = (uint16_t *)(dest + (i * 2));
 335                 if (swap)
 336                         *ptr = ntohs(word);
 337                 else
 338                         *ptr = word;
 339         }
 340 }
 341
 342 /*
 343  * MII access routines are provided for the 8129, which
 344  * doesn't have a built-in PHY. For the 8139, we fake things
 345  * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
 346  * direct access PHY registers.
 347  */
 348 #define MII_SET(x)                                      \
 349         CSR_WRITE_1(sc, RL_MII,                         \
 350                 CSR_READ_1(sc, RL_MII) | (x))
 351
 352 #define MII_CLR(x)                                      \
 353         CSR_WRITE_1(sc, RL_MII,                         \
 354                 CSR_READ_1(sc, RL_MII) & ~(x))
 355
 356 /*
 357  * Sync the PHYs by setting data bit and strobing the clock 32 times.
 358  */
 359 static void
 360 rl_mii_sync(struct rl_softc *sc)
 361 {
 362         register int            i;
 363
 364         MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
 365
 366         for (i = 0; i < 32; i++) {
 367                 MII_SET(RL_MII_CLK);
 368                 DELAY(1);
 369                 MII_CLR(RL_MII_CLK);
 370                 DELAY(1);
 371         }
 372 }
 373
 374 /*
 375  * Clock a series of bits through the MII.
 376  */
 377 static void
 378 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
 379 {
 380         int                     i;
 381
 382         MII_CLR(RL_MII_CLK);
 383
 384         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
 385                 if (bits & i) {
 386                         MII_SET(RL_MII_DATAOUT);
 387                 } else {
 388                         MII_CLR(RL_MII_DATAOUT);
 389                 }
 390                 DELAY(1);
 391                 MII_CLR(RL_MII_CLK);
 392                 DELAY(1);
 393                 MII_SET(RL_MII_CLK);
 394         }
 395 }
 396
 397 /*
 398  * Read an PHY register through the MII.
 399  */
 400 static int
 401 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
 402 {
 403         int                     i, ack;
 404
 405         /* Set up frame for RX. */
 406         frame->mii_stdelim = RL_MII_STARTDELIM;
 407         frame->mii_opcode = RL_MII_READOP;
 408         frame->mii_turnaround = 0;
 409         frame->mii_data = 0;
 410
 411         CSR_WRITE_2(sc, RL_MII, 0);
 412
 413         /* Turn on data xmit. */
 414         MII_SET(RL_MII_DIR);
 415
 416         rl_mii_sync(sc);
 417
 418         /* Send command/address info. */
 419         rl_mii_send(sc, frame->mii_stdelim, 2);
 420         rl_mii_send(sc, frame->mii_opcode, 2);
 421         rl_mii_send(sc, frame->mii_phyaddr, 5);
 422         rl_mii_send(sc, frame->mii_regaddr, 5);
 423
 424         /* Idle bit */
 425         MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
 426         DELAY(1);
 427         MII_SET(RL_MII_CLK);
 428         DELAY(1);
 429
 430         /* Turn off xmit. */
 431         MII_CLR(RL_MII_DIR);
 432
 433         /* Check for ack */
 434         MII_CLR(RL_MII_CLK);
 435         DELAY(1);
 436         ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
 437         MII_SET(RL_MII_CLK);
 438         DELAY(1);
 439
 440         /*
 441          * Now try reading data bits. If the ack failed, we still
 442          * need to clock through 16 cycles to keep the PHY(s) in sync.
 443          */
 444         if (ack) {
 445                 for(i = 0; i < 16; i++) {
 446                         MII_CLR(RL_MII_CLK);
 447                         DELAY(1);
 448                         MII_SET(RL_MII_CLK);
 449                         DELAY(1);
 450                 }
 451                 goto fail;
 452         }
 453
 454         for (i = 0x8000; i; i >>= 1) {
 455                 MII_CLR(RL_MII_CLK);
 456                 DELAY(1);
 457                 if (!ack) {
 458                         if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
 459                                 frame->mii_data |= i;
 460                         DELAY(1);
 461                 }
 462                 MII_SET(RL_MII_CLK);
 463                 DELAY(1);
 464         }
 465
 466 fail:
 467         MII_CLR(RL_MII_CLK);
 468         DELAY(1);
 469         MII_SET(RL_MII_CLK);
 470         DELAY(1);
 471
 472         return (ack ? 1 : 0);
 473 }
 474
 475 /*
 476  * Write to a PHY register through the MII.
 477  */
 478 static int
 479 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
 480 {
 481
 482         /* Set up frame for TX. */
 483         frame->mii_stdelim = RL_MII_STARTDELIM;
 484         frame->mii_opcode = RL_MII_WRITEOP;
 485         frame->mii_turnaround = RL_MII_TURNAROUND;
 486
 487         /* Turn on data output. */
 488         MII_SET(RL_MII_DIR);
 489
 490         rl_mii_sync(sc);
 491
 492         rl_mii_send(sc, frame->mii_stdelim, 2);
 493         rl_mii_send(sc, frame->mii_opcode, 2);
 494         rl_mii_send(sc, frame->mii_phyaddr, 5);
 495         rl_mii_send(sc, frame->mii_regaddr, 5);
 496         rl_mii_send(sc, frame->mii_turnaround, 2);
 497         rl_mii_send(sc, frame->mii_data, 16);
 498
 499         /* Idle bit. */
 500         MII_SET(RL_MII_CLK);
 501         DELAY(1);
 502         MII_CLR(RL_MII_CLK);
 503         DELAY(1);
 504
 505         /* Turn off xmit. */
 506         MII_CLR(RL_MII_DIR);
 507
 508         return (0);
 509 }
 510
 511 static int
 512 rl_miibus_readreg(device_t dev, int phy, int reg)
 513 {
 514         struct rl_softc         *sc;
 515         struct rl_mii_frame     frame;
 516         uint16_t                rval = 0;
 517         uint16_t                rl8139_reg = 0;
 518
 519         sc = device_get_softc(dev);
 520
 521         if (sc->rl_type == RL_8139) {
 522                 switch (reg) {
 523                 case MII_BMCR:
 524                         rl8139_reg = RL_BMCR;
 525                         break;
 526                 case MII_BMSR:
 527                         rl8139_reg = RL_BMSR;
 528                         break;
 529                 case MII_ANAR:
 530                         rl8139_reg = RL_ANAR;
 531                         break;
 532                 case MII_ANER:
 533                         rl8139_reg = RL_ANER;
 534                         break;
 535                 case MII_ANLPAR:
 536                         rl8139_reg = RL_LPAR;
 537                         break;
 538                 case MII_PHYIDR1:
 539                 case MII_PHYIDR2:
 540                         return (0);
 541                 /*
 542                  * Allow the rlphy driver to read the media status
 543                  * register. If we have a link partner which does not
 544                  * support NWAY, this is the register which will tell
 545                  * us the results of parallel detection.
 546                  */
 547                 case RL_MEDIASTAT:
 548                         rval = CSR_READ_1(sc, RL_MEDIASTAT);
 549                         return (rval);
 550                 default:
 551                         device_printf(sc->rl_dev, "bad phy register\n");
 552                         return (0);
 553                 }
 554                 rval = CSR_READ_2(sc, rl8139_reg);
 555                 return (rval);
 556         }
 557
 558         bzero((char *)&frame, sizeof(frame));
 559         frame.mii_phyaddr = phy;
 560         frame.mii_regaddr = reg;
 561         rl_mii_readreg(sc, &frame);
 562
 563         return (frame.mii_data);
 564 }
 565
 566 static int
 567 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
 568 {
 569         struct rl_softc         *sc;
 570         struct rl_mii_frame     frame;
 571         uint16_t                rl8139_reg = 0;
 572
 573         sc = device_get_softc(dev);
 574
 575         if (sc->rl_type == RL_8139) {
 576                 switch (reg) {
 577                 case MII_BMCR:
 578                         rl8139_reg = RL_BMCR;
 579                         break;
 580                 case MII_BMSR:
 581                         rl8139_reg = RL_BMSR;
 582                         break;
 583                 case MII_ANAR:
 584                         rl8139_reg = RL_ANAR;
 585                         break;
 586                 case MII_ANER:
 587                         rl8139_reg = RL_ANER;
 588                         break;
 589                 case MII_ANLPAR:
 590                         rl8139_reg = RL_LPAR;
 591                         break;
 592                 case MII_PHYIDR1:
 593                 case MII_PHYIDR2:
 594                         return (0);
 595                         break;
 596                 default:
 597                         device_printf(sc->rl_dev, "bad phy register\n");
 598                         return (0);
 599                 }
 600                 CSR_WRITE_2(sc, rl8139_reg, data);
 601                 return (0);
 602         }
 603
 604         bzero((char *)&frame, sizeof(frame));
 605         frame.mii_phyaddr = phy;
 606         frame.mii_regaddr = reg;
 607         frame.mii_data = data;
 608         rl_mii_writereg(sc, &frame);
 609
 610         return (0);
 611 }
 612
 613 static void
 614 rl_miibus_statchg(device_t dev)
 615 {
 616         struct rl_softc         *sc;
 617         struct ifnet            *ifp;
 618         struct mii_data         *mii;
 619
 620         sc = device_get_softc(dev);
 621         mii = device_get_softc(sc->rl_miibus);
 622         ifp = sc->rl_ifp;
 623         if (mii == NULL || ifp == NULL ||
 624             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 625                 return;
 626
 627         sc->rl_flags &= ~RL_FLAG_LINK;
 628         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 629             (IFM_ACTIVE | IFM_AVALID)) {
 630                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 631                 case IFM_10_T:
 632                 case IFM_100_TX:
 633                         sc->rl_flags |= RL_FLAG_LINK;
 634                         break;
 635                 default:
 636                         break;
 637                 }
 638         }
 639         /*
 640          * RealTek controllers do not provide any interface to
 641          * Tx/Rx MACs for resolved speed, duplex and flow-control
 642          * parameters.
 643          */
 644 }
 645
 646 /*
 647  * Program the 64-bit multicast hash filter.
 648  */
 649 static void
 650 rl_rxfilter(struct rl_softc *sc)
 651 {
 652         struct ifnet            *ifp = sc->rl_ifp;
 653         int                     h = 0;
 654         uint32_t                hashes[2] = { 0, 0 };
 655         struct ifmultiaddr      *ifma;
 656         uint32_t                rxfilt;
 657
 658         RL_LOCK_ASSERT(sc);
 659
 660         rxfilt = CSR_READ_4(sc, RL_RXCFG);
 661         rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD |
 662             RL_RXCFG_RX_MULTI);
 663         /* Always accept frames destined for this host. */
 664         rxfilt |= RL_RXCFG_RX_INDIV;
 665         /* Set capture broadcast bit to capture broadcast frames. */
 666         if (ifp->if_flags & IFF_BROADCAST)
 667                 rxfilt |= RL_RXCFG_RX_BROAD;
 668         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 669                 rxfilt |= RL_RXCFG_RX_MULTI;
 670                 if (ifp->if_flags & IFF_PROMISC)
 671                         rxfilt |= RL_RXCFG_RX_ALLPHYS;
 672                 hashes[0] = 0xFFFFFFFF;
 673                 hashes[1] = 0xFFFFFFFF;
 674         } else {
 675                 /* Now program new ones. */
 676                 if_maddr_rlock(ifp);
 677                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 678                         if (ifma->ifma_addr->sa_family != AF_LINK)
 679                                 continue;
 680                         h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 681                             ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 682                         if (h < 32)
 683                                 hashes[0] |= (1 << h);
 684                         else
 685                                 hashes[1] |= (1 << (h - 32));
 686                 }
 687                 if_maddr_runlock(ifp);
 688                 if (hashes[0] != 0 || hashes[1] != 0)
 689                         rxfilt |= RL_RXCFG_RX_MULTI;
 690         }
 691
 692         CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
 693         CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
 694         CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
 695 }
 696
 697 static void
 698 rl_reset(struct rl_softc *sc)
 699 {
 700         register int            i;
 701
 702         RL_LOCK_ASSERT(sc);
 703
 704         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
 705
 706         for (i = 0; i < RL_TIMEOUT; i++) {
 707                 DELAY(10);
 708                 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
 709                         break;
 710         }
 711         if (i == RL_TIMEOUT)
 712                 device_printf(sc->rl_dev, "reset never completed!\n");
 713 }
 714
 715 /*
 716  * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
 717  * IDs against our list and return a device name if we find a match.
 718  */
 719 static int
 720 rl_probe(device_t dev)
 721 {
 722         struct rl_type          *t;
 723         uint16_t                devid, revid, vendor;
 724         int                     i;
 725
 726         vendor = pci_get_vendor(dev);
 727         devid = pci_get_device(dev);
 728         revid = pci_get_revid(dev);
 729
 730         if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
 731                 if (revid == 0x20) {
 732                         /* 8139C+, let re(4) take care of this device. */
 733                         return (ENXIO);
 734                 }
 735         }
 736         t = rl_devs;
 737         for (i = 0; i < sizeof(rl_devs) / sizeof(rl_devs[0]); i++, t++) {
 738                 if (vendor == t->rl_vid && devid == t->rl_did) {
 739                         device_set_desc(dev, t->rl_name);
 740                         return (BUS_PROBE_DEFAULT);
 741                 }
 742         }
 743
 744         return (ENXIO);
 745 }
 746
 747 struct rl_dmamap_arg {
 748         bus_addr_t      rl_busaddr;
 749 };
 750
 751 static void
 752 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 753 {
 754         struct rl_dmamap_arg    *ctx;
 755
 756         if (error != 0)
 757                 return;
 758
 759         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 760
 761         ctx = (struct rl_dmamap_arg *)arg;
 762         ctx->rl_busaddr = segs[0].ds_addr;
 763 }
 764
 765 /*
 766  * Attach the interface. Allocate softc structures, do ifmedia
 767  * setup and ethernet/BPF attach.
 768  */
 769 static int
 770 rl_attach(device_t dev)
 771 {
 772         uint8_t                 eaddr[ETHER_ADDR_LEN];
 773         uint16_t                as[3];
 774         struct ifnet            *ifp;
 775         struct rl_softc         *sc;
 776         struct rl_type          *t;
 777         struct sysctl_ctx_list  *ctx;
 778         struct sysctl_oid_list  *children;
 779         int                     error = 0, hwrev, i, phy, pmc, rid;
 780         int                     prefer_iomap, unit;
 781         uint16_t                rl_did = 0;
 782         char                    tn[32];
 783
 784         sc = device_get_softc(dev);
 785         unit = device_get_unit(dev);
 786         sc->rl_dev = dev;
 787
 788         sc->rl_twister_enable = 0;
 789         snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit);
 790         TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable);
 791         ctx = device_get_sysctl_ctx(sc->rl_dev);
 792         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
 793         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD,
 794            &sc->rl_twister_enable, 0, "");
 795
 796         mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
 797             MTX_DEF);
 798         callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
 799
 800         pci_enable_busmaster(dev);
 801
 802
 803         /*
 804          * Map control/status registers.
 805          * Default to using PIO access for this driver. On SMP systems,
 806          * there appear to be problems with memory mapped mode: it looks
 807          * like doing too many memory mapped access back to back in rapid
 808          * succession can hang the bus. I'm inclined to blame this on
 809          * crummy design/construction on the part of RealTek. Memory
 810          * mapped mode does appear to work on uniprocessor systems though.
 811          */
 812         prefer_iomap = 1;
 813         snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit);
 814         TUNABLE_INT_FETCH(tn, &prefer_iomap);
 815         if (prefer_iomap) {
 816                 sc->rl_res_id = PCIR_BAR(0);
 817                 sc->rl_res_type = SYS_RES_IOPORT;
 818                 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 819                     &sc->rl_res_id, RF_ACTIVE);
 820         }
 821         if (prefer_iomap == 0 || sc->rl_res == NULL) {
 822                 sc->rl_res_id = PCIR_BAR(1);
 823                 sc->rl_res_type = SYS_RES_MEMORY;
 824                 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
 825                     &sc->rl_res_id, RF_ACTIVE);
 826         }
 827         if (sc->rl_res == NULL) {
 828                 device_printf(dev, "couldn't map ports/memory\n");
 829                 error = ENXIO;
 830                 goto fail;
 831         }
 832
 833 #ifdef notdef
 834         /*
 835          * Detect the Realtek 8139B. For some reason, this chip is very
 836          * unstable when left to autoselect the media
 837          * The best workaround is to set the device to the required
 838          * media type or to set it to the 10 Meg speed.
 839          */
 840         if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF)
 841                 device_printf(dev,
 842 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n");
 843 #endif
 844
 845         sc->rl_btag = rman_get_bustag(sc->rl_res);
 846         sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
 847
 848         /* Allocate interrupt */
 849         rid = 0;
 850         sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 851             RF_SHAREABLE | RF_ACTIVE);
 852
 853         if (sc->rl_irq[0] == NULL) {
 854                 device_printf(dev, "couldn't map interrupt\n");
 855                 error = ENXIO;
 856                 goto fail;
 857         }
 858
 859         /*
 860          * Reset the adapter. Only take the lock here as it's needed in
 861          * order to call rl_reset().
 862          */
 863         RL_LOCK(sc);
 864         rl_reset(sc);
 865         RL_UNLOCK(sc);
 866
 867         sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
 868         rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
 869         if (rl_did != 0x8129)
 870                 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
 871
 872         /*
 873          * Get station address from the EEPROM.
 874          */
 875         rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0);
 876         for (i = 0; i < 3; i++) {
 877                 eaddr[(i * 2) + 0] = as[i] & 0xff;
 878                 eaddr[(i * 2) + 1] = as[i] >> 8;
 879         }
 880
 881         /*
 882          * Now read the exact device type from the EEPROM to find
 883          * out if it's an 8129 or 8139.
 884          */
 885         rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0);
 886
 887         t = rl_devs;
 888         sc->rl_type = 0;
 889         while(t->rl_name != NULL) {
 890                 if (rl_did == t->rl_did) {
 891                         sc->rl_type = t->rl_basetype;
 892                         break;
 893                 }
 894                 t++;
 895         }
 896
 897         if (sc->rl_type == 0) {
 898                 device_printf(dev, "unknown device ID: %x assuming 8139\n",
 899                     rl_did);
 900                 sc->rl_type = RL_8139;
 901                 /*
 902                  * Read RL_IDR register to get ethernet address as accessing
 903                  * EEPROM may not extract correct address.
 904                  */
 905                 for (i = 0; i < ETHER_ADDR_LEN; i++)
 906                         eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
 907         }
 908
 909         if ((error = rl_dma_alloc(sc)) != 0)
 910                 goto fail;
 911
 912         ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
 913         if (ifp == NULL) {
 914                 device_printf(dev, "can not if_alloc()\n");
 915                 error = ENOSPC;
 916                 goto fail;
 917         }
 918
 919 #define RL_PHYAD_INTERNAL       0
 920
 921         /* Do MII setup */
 922         phy = MII_PHY_ANY;
 923         if (sc->rl_type == RL_8139)
 924                 phy = RL_PHYAD_INTERNAL;
 925         error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd,
 926             rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
 927         if (error != 0) {
 928                 device_printf(dev, "attaching PHYs failed\n");
 929                 goto fail;
 930         }
 931
 932         ifp->if_softc = sc;
 933         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 934         ifp->if_mtu = ETHERMTU;
 935         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 936         ifp->if_ioctl = rl_ioctl;
 937         ifp->if_start = rl_start;
 938         ifp->if_init = rl_init;
 939         ifp->if_capabilities = IFCAP_VLAN_MTU;
 940         /* Check WOL for RTL8139B or newer controllers. */
 941         if (sc->rl_type == RL_8139 &&
 942             pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
 943                 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV;
 944                 switch (hwrev) {
 945                 case RL_HWREV_8139B:
 946                 case RL_HWREV_8130:
 947                 case RL_HWREV_8139C:
 948                 case RL_HWREV_8139D:
 949                 case RL_HWREV_8101:
 950                 case RL_HWREV_8100:
 951                         ifp->if_capabilities |= IFCAP_WOL;
 952                         /* Disable WOL. */
 953                         rl_clrwol(sc);
 954                         break;
 955                 default:
 956                         break;
 957                 }
 958         }
 959         ifp->if_capenable = ifp->if_capabilities;
 960 #ifdef DEVICE_POLLING
 961         ifp->if_capabilities |= IFCAP_POLLING;
 962 #endif
 963         IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
 964         ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
 965         IFQ_SET_READY(&ifp->if_snd);
 966
 967         /*
 968          * Call MI attach routine.
 969          */
 970         ether_ifattach(ifp, eaddr);
 971
 972         /* Hook interrupt last to avoid having to lock softc */
 973         error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE,
 974             NULL, rl_intr, sc, &sc->rl_intrhand[0]);
 975         if (error) {
 976                 device_printf(sc->rl_dev, "couldn't set up irq\n");
 977                 ether_ifdetach(ifp);
 978         }
 979
 980 fail:
 981         if (error)
 982                 rl_detach(dev);
 983
 984         return (error);
 985 }
 986
 987 /*
 988  * Shutdown hardware and free up resources. This can be called any
 989  * time after the mutex has been initialized. It is called in both
 990  * the error case in attach and the normal detach case so it needs
 991  * to be careful about only freeing resources that have actually been
 992  * allocated.
 993  */
 994 static int
 995 rl_detach(device_t dev)
 996 {
 997         struct rl_softc         *sc;
 998         struct ifnet            *ifp;
 999
1000         sc = device_get_softc(dev);
1001         ifp = sc->rl_ifp;
1002
1003         KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized"));
1004
1005 #ifdef DEVICE_POLLING
1006         if (ifp->if_capenable & IFCAP_POLLING)
1007                 ether_poll_deregister(ifp);
1008 #endif
1009         /* These should only be active if attach succeeded */
1010         if (device_is_attached(dev)) {
1011                 RL_LOCK(sc);
1012                 rl_stop(sc);
1013                 RL_UNLOCK(sc);
1014                 callout_drain(&sc->rl_stat_callout);
1015                 ether_ifdetach(ifp);
1016         }
1017 #if 0
1018         sc->suspended = 1;
1019 #endif
1020         if (sc->rl_miibus)
1021                 device_delete_child(dev, sc->rl_miibus);
1022         bus_generic_detach(dev);
1023
1024         if (sc->rl_intrhand[0])
1025                 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1026         if (sc->rl_irq[0])
1027                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]);
1028         if (sc->rl_res)
1029                 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1030                     sc->rl_res);
1031
1032         if (ifp)
1033                 if_free(ifp);
1034
1035         rl_dma_free(sc);
1036
1037         mtx_destroy(&sc->rl_mtx);
1038
1039         return (0);
1040 }
1041
1042 static int
1043 rl_dma_alloc(struct rl_softc *sc)
1044 {
1045         struct rl_dmamap_arg    ctx;
1046         int                     error, i;
1047
1048         /*
1049          * Allocate the parent bus DMA tag appropriate for PCI.
1050          */
1051         error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */
1052             1, 0,                       /* alignment, boundary */
1053             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
1054             BUS_SPACE_MAXADDR,          /* highaddr */
1055             NULL, NULL,                 /* filter, filterarg */
1056             BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */
1057             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1058             0,                          /* flags */
1059             NULL, NULL,                 /* lockfunc, lockarg */
1060             &sc->rl_parent_tag);
1061         if (error) {
1062                 device_printf(sc->rl_dev,
1063                     "failed to create parent DMA tag.\n");
1064                 goto fail;
1065         }
1066         /* Create DMA tag for Rx memory block. */
1067         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1068             RL_RX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1069             BUS_SPACE_MAXADDR,          /* lowaddr */
1070             BUS_SPACE_MAXADDR,          /* highaddr */
1071             NULL, NULL,                 /* filter, filterarg */
1072             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1,   /* maxsize,nsegments */
1073             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ,      /* maxsegsize */
1074             0,                          /* flags */
1075             NULL, NULL,                 /* lockfunc, lockarg */
1076             &sc->rl_cdata.rl_rx_tag);
1077         if (error) {
1078                 device_printf(sc->rl_dev,
1079                     "failed to create Rx memory block DMA tag.\n");
1080                 goto fail;
1081         }
1082         /* Create DMA tag for Tx buffer. */
1083         error = bus_dma_tag_create(sc->rl_parent_tag,   /* parent */
1084             RL_TX_8139_BUF_ALIGN, 0,    /* alignment, boundary */
1085             BUS_SPACE_MAXADDR,          /* lowaddr */
1086             BUS_SPACE_MAXADDR,          /* highaddr */
1087             NULL, NULL,                 /* filter, filterarg */
1088             MCLBYTES, 1,                /* maxsize, nsegments */
1089             MCLBYTES,                   /* maxsegsize */
1090             0,                          /* flags */
1091             NULL, NULL,                 /* lockfunc, lockarg */
1092             &sc->rl_cdata.rl_tx_tag);
1093         if (error) {
1094                 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n");
1095                 goto fail;
1096         }
1097
1098         /*
1099          * Allocate DMA'able memory and load DMA map for Rx memory block.
1100          */
1101         error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag,
1102             (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK |
1103             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap);
1104         if (error != 0) {
1105                 device_printf(sc->rl_dev,
1106                     "failed to allocate Rx DMA memory block.\n");
1107                 goto fail;
1108         }
1109         ctx.rl_busaddr = 0;
1110         error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag,
1111             sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf,
1112             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx,
1113             BUS_DMA_NOWAIT);
1114         if (error != 0 || ctx.rl_busaddr == 0) {
1115                 device_printf(sc->rl_dev,
1116                     "could not load Rx DMA memory block.\n");
1117                 goto fail;
1118         }
1119         sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr;
1120
1121         /* Create DMA maps for Tx buffers. */
1122         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1123                 sc->rl_cdata.rl_tx_chain[i] = NULL;
1124                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1125                 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0,
1126                     &sc->rl_cdata.rl_tx_dmamap[i]);
1127                 if (error != 0) {
1128                         device_printf(sc->rl_dev,
1129                             "could not create Tx dmamap.\n");
1130                         goto fail;
1131                 }
1132         }
1133
1134         /* Leave a few bytes before the start of the RX ring buffer. */
1135         sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
1136         sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE;
1137
1138 fail:
1139         return (error);
1140 }
1141
1142 static void
1143 rl_dma_free(struct rl_softc *sc)
1144 {
1145         int                     i;
1146
1147         /* Rx memory block. */
1148         if (sc->rl_cdata.rl_rx_tag != NULL) {
1149                 if (sc->rl_cdata.rl_rx_dmamap != NULL)
1150                         bus_dmamap_unload(sc->rl_cdata.rl_rx_tag,
1151                             sc->rl_cdata.rl_rx_dmamap);
1152                 if (sc->rl_cdata.rl_rx_dmamap != NULL &&
1153                     sc->rl_cdata.rl_rx_buf_ptr != NULL)
1154                         bus_dmamem_free(sc->rl_cdata.rl_rx_tag,
1155                             sc->rl_cdata.rl_rx_buf_ptr,
1156                             sc->rl_cdata.rl_rx_dmamap);
1157                 sc->rl_cdata.rl_rx_buf_ptr = NULL;
1158                 sc->rl_cdata.rl_rx_buf = NULL;
1159                 sc->rl_cdata.rl_rx_dmamap = NULL;
1160                 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag);
1161                 sc->rl_cdata.rl_tx_tag = NULL;
1162         }
1163
1164         /* Tx buffers. */
1165         if (sc->rl_cdata.rl_tx_tag != NULL) {
1166                 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1167                         if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) {
1168                                 bus_dmamap_destroy(
1169                                     sc->rl_cdata.rl_tx_tag,
1170                                     sc->rl_cdata.rl_tx_dmamap[i]);
1171                                 sc->rl_cdata.rl_tx_dmamap[i] = NULL;
1172                         }
1173                 }
1174                 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag);
1175                 sc->rl_cdata.rl_tx_tag = NULL;
1176         }
1177
1178         if (sc->rl_parent_tag != NULL) {
1179                 bus_dma_tag_destroy(sc->rl_parent_tag);
1180                 sc->rl_parent_tag = NULL;
1181         }
1182 }
1183
1184 /*
1185  * Initialize the transmit descriptors.
1186  */
1187 static int
1188 rl_list_tx_init(struct rl_softc *sc)
1189 {
1190         struct rl_chain_data    *cd;
1191         int                     i;
1192
1193         RL_LOCK_ASSERT(sc);
1194
1195         cd = &sc->rl_cdata;
1196         for (i = 0; i < RL_TX_LIST_CNT; i++) {
1197                 cd->rl_tx_chain[i] = NULL;
1198                 CSR_WRITE_4(sc,
1199                     RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1200         }
1201
1202         sc->rl_cdata.cur_tx = 0;
1203         sc->rl_cdata.last_tx = 0;
1204
1205         return (0);
1206 }
1207
1208 static int
1209 rl_list_rx_init(struct rl_softc *sc)
1210 {
1211
1212         RL_LOCK_ASSERT(sc);
1213
1214         bzero(sc->rl_cdata.rl_rx_buf_ptr,
1215             RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ);
1216         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap,
1217             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1218
1219         return (0);
1220 }
1221
1222 /*
1223  * A frame has been uploaded: pass the resulting mbuf chain up to
1224  * the higher level protocols.
1225  *
1226  * You know there's something wrong with a PCI bus-master chip design
1227  * when you have to use m_devget().
1228  *
1229  * The receive operation is badly documented in the datasheet, so I'll
1230  * attempt to document it here. The driver provides a buffer area and
1231  * places its base address in the RX buffer start address register.
1232  * The chip then begins copying frames into the RX buffer. Each frame
1233  * is preceded by a 32-bit RX status word which specifies the length
1234  * of the frame and certain other status bits. Each frame (starting with
1235  * the status word) is also 32-bit aligned. The frame length is in the
1236  * first 16 bits of the status word; the lower 15 bits correspond with
1237  * the 'rx status register' mentioned in the datasheet.
1238  *
1239  * Note: to make the Alpha happy, the frame payload needs to be aligned
1240  * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes)
1241  * as the offset argument to m_devget().
1242  */
1243 static int
1244 rl_rxeof(struct rl_softc *sc)
1245 {
1246         struct mbuf             *m;
1247         struct ifnet            *ifp = sc->rl_ifp;
1248         uint8_t                 *rxbufpos;
1249         int                     total_len = 0;
1250         int                     wrap = 0;
1251         int                     rx_npkts = 0;
1252         uint32_t                rxstat;
1253         uint16_t                cur_rx;
1254         uint16_t                limit;
1255         uint16_t                max_bytes, rx_bytes = 0;
1256
1257         RL_LOCK_ASSERT(sc);
1258
1259         bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap,
1260             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1261
1262         cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1263
1264         /* Do not try to read past this point. */
1265         limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1266
1267         if (limit < cur_rx)
1268                 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1269         else
1270                 max_bytes = limit - cur_rx;
1271
1272         while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1273 #ifdef DEVICE_POLLING
1274                 if (ifp->if_capenable & IFCAP_POLLING) {
1275                         if (sc->rxcycles <= 0)
1276                                 break;
1277                         sc->rxcycles--;
1278                 }
1279 #endif
1280                 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1281                 rxstat = le32toh(*(uint32_t *)rxbufpos);
1282
1283                 /*
1284                  * Here's a totally undocumented fact for you. When the
1285                  * RealTek chip is in the process of copying a packet into
1286                  * RAM for you, the length will be 0xfff0. If you spot a
1287                  * packet header with this value, you need to stop. The
1288                  * datasheet makes absolutely no mention of this and
1289                  * RealTek should be shot for this.
1290                  */
1291                 total_len = rxstat >> 16;
1292                 if (total_len == RL_RXSTAT_UNFINISHED)
1293                         break;
1294
1295                 if (!(rxstat & RL_RXSTAT_RXOK) ||
1296                     total_len < ETHER_MIN_LEN ||
1297                     total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) {
1298                         ifp->if_ierrors++;
1299                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1300                         rl_init_locked(sc);
1301                         return (rx_npkts);
1302                 }
1303
1304                 /* No errors; receive the packet. */
1305                 rx_bytes += total_len + 4;
1306
1307                 /*
1308                  * XXX The RealTek chip includes the CRC with every
1309                  * received frame, and there's no way to turn this
1310                  * behavior off (at least, I can't find anything in
1311                  * the manual that explains how to do it) so we have
1312                  * to trim off the CRC manually.
1313                  */
1314                 total_len -= ETHER_CRC_LEN;
1315
1316                 /*
1317                  * Avoid trying to read more bytes than we know
1318                  * the chip has prepared for us.
1319                  */
1320                 if (rx_bytes > max_bytes)
1321                         break;
1322
1323                 rxbufpos = sc->rl_cdata.rl_rx_buf +
1324                         ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1325                 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1326                         rxbufpos = sc->rl_cdata.rl_rx_buf;
1327
1328                 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1329                 if (total_len > wrap) {
1330                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1331                             NULL);
1332                         if (m != NULL)
1333                                 m_copyback(m, wrap, total_len - wrap,
1334                                         sc->rl_cdata.rl_rx_buf);
1335                         cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1336                 } else {
1337                         m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp,
1338                             NULL);
1339                         cur_rx += total_len + 4 + ETHER_CRC_LEN;
1340                 }
1341
1342                 /* Round up to 32-bit boundary. */
1343                 cur_rx = (cur_rx + 3) & ~3;
1344                 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1345
1346                 if (m == NULL) {
1347                         ifp->if_iqdrops++;
1348                         continue;
1349                 }
1350
1351                 ifp->if_ipackets++;
1352                 RL_UNLOCK(sc);
1353                 (*ifp->if_input)(ifp, m);
1354                 RL_LOCK(sc);
1355                 rx_npkts++;
1356         }
1357
1358         /* No need to sync Rx memory block as we didn't modify it. */
1359         return (rx_npkts);
1360 }
1361
1362 /*
1363  * A frame was downloaded to the chip. It's safe for us to clean up
1364  * the list buffers.
1365  */
1366 static void
1367 rl_txeof(struct rl_softc *sc)
1368 {
1369         struct ifnet            *ifp = sc->rl_ifp;
1370         uint32_t                txstat;
1371
1372         RL_LOCK_ASSERT(sc);
1373
1374         /*
1375          * Go through our tx list and free mbufs for those
1376          * frames that have been uploaded.
1377          */
1378         do {
1379                 if (RL_LAST_TXMBUF(sc) == NULL)
1380                         break;
1381                 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1382                 if (!(txstat & (RL_TXSTAT_TX_OK|
1383                     RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT)))
1384                         break;
1385
1386                 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1387
1388                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc),
1389                     BUS_DMASYNC_POSTWRITE);
1390                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc));
1391                 m_freem(RL_LAST_TXMBUF(sc));
1392                 RL_LAST_TXMBUF(sc) = NULL;
1393                 /*
1394                  * If there was a transmit underrun, bump the TX threshold.
1395                  * Make sure not to overflow the 63 * 32byte we can address
1396                  * with the 6 available bit.
1397                  */
1398                 if ((txstat & RL_TXSTAT_TX_UNDERRUN) &&
1399                     (sc->rl_txthresh < 2016))
1400                         sc->rl_txthresh += 32;
1401                 if (txstat & RL_TXSTAT_TX_OK)
1402                         ifp->if_opackets++;
1403                 else {
1404                         int                     oldthresh;
1405                         ifp->if_oerrors++;
1406                         if ((txstat & RL_TXSTAT_TXABRT) ||
1407                             (txstat & RL_TXSTAT_OUTOFWIN))
1408                                 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1409                         oldthresh = sc->rl_txthresh;
1410                         /* error recovery */
1411                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1412                         rl_init_locked(sc);
1413                         /* restore original threshold */
1414                         sc->rl_txthresh = oldthresh;
1415                         return;
1416                 }
1417                 RL_INC(sc->rl_cdata.last_tx);
1418                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1419         } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1420
1421         if (RL_LAST_TXMBUF(sc) == NULL)
1422                 sc->rl_watchdog_timer = 0;
1423 }
1424
1425 static void
1426 rl_twister_update(struct rl_softc *sc)
1427 {
1428         uint16_t linktest;
1429         /*
1430          * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for
1431          * Linux driver.  Values undocumented otherwise.
1432          */
1433         static const uint32_t param[4][4] = {
1434                 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1435                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1436                 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1437                 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1438         };
1439
1440         /*
1441          * Tune the so-called twister registers of the RTL8139.  These
1442          * are used to compensate for impedance mismatches.  The
1443          * method for tuning these registers is undocumented and the
1444          * following procedure is collected from public sources.
1445          */
1446         switch (sc->rl_twister)
1447         {
1448         case CHK_LINK:
1449                 /*
1450                  * If we have a sufficient link, then we can proceed in
1451                  * the state machine to the next stage.  If not, then
1452                  * disable further tuning after writing sane defaults.
1453                  */
1454                 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) {
1455                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1456                         sc->rl_twister = FIND_ROW;
1457                 } else {
1458                         CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1459                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1460                         CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1461                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1462                         sc->rl_twister = DONE;
1463                 }
1464                 break;
1465         case FIND_ROW:
1466                 /*
1467                  * Read how long it took to see the echo to find the tuning
1468                  * row to use.
1469                  */
1470                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1471                 if (linktest == RL_CSCFG_ROW3)
1472                         sc->rl_twist_row = 3;
1473                 else if (linktest == RL_CSCFG_ROW2)
1474                         sc->rl_twist_row = 2;
1475                 else if (linktest == RL_CSCFG_ROW1)
1476                         sc->rl_twist_row = 1;
1477                 else
1478                         sc->rl_twist_row = 0;
1479                 sc->rl_twist_col = 0;
1480                 sc->rl_twister = SET_PARAM;
1481                 break;
1482         case SET_PARAM:
1483                 if (sc->rl_twist_col == 0)
1484                         CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1485                 CSR_WRITE_4(sc, RL_PARA7C,
1486                     param[sc->rl_twist_row][sc->rl_twist_col]);
1487                 if (++sc->rl_twist_col == 4) {
1488                         if (sc->rl_twist_row == 3)
1489                                 sc->rl_twister = RECHK_LONG;
1490                         else
1491                                 sc->rl_twister = DONE;
1492                 }
1493                 break;
1494         case RECHK_LONG:
1495                 /*
1496                  * For long cables, we have to double check to make sure we
1497                  * don't mistune.
1498                  */
1499                 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS;
1500                 if (linktest == RL_CSCFG_ROW3)
1501                         sc->rl_twister = DONE;
1502                 else {
1503                         CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE);
1504                         sc->rl_twister = RETUNE;
1505                 }
1506                 break;
1507         case RETUNE:
1508                 /* Retune for a shorter cable (try column 2) */
1509                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST);
1510                 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF);
1511                 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF);
1512                 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET);
1513                 sc->rl_twist_row--;
1514                 sc->rl_twist_col = 0;
1515                 sc->rl_twister = SET_PARAM;
1516                 break;
1517
1518         case DONE:
1519                 break;
1520         }
1521
1522 }
1523
1524 static void
1525 rl_tick(void *xsc)
1526 {
1527         struct rl_softc         *sc = xsc;
1528         struct mii_data         *mii;
1529         int ticks;
1530
1531         RL_LOCK_ASSERT(sc);
1532         /*
1533          * If we're doing the twister cable calibration, then we need to defer
1534          * watchdog timeouts.  This is a no-op in normal operations, but
1535          * can falsely trigger when the cable calibration takes a while and
1536          * there was traffic ready to go when rl was started.
1537          *
1538          * We don't defer mii_tick since that updates the mii status, which
1539          * helps the twister process, at least according to similar patches
1540          * for the Linux driver I found online while doing the fixes.  Worst
1541          * case is a few extra mii reads during calibration.
1542          */
1543         mii = device_get_softc(sc->rl_miibus);
1544         mii_tick(mii);
1545         if ((sc->rl_flags & RL_FLAG_LINK) == 0)
1546                 rl_miibus_statchg(sc->rl_dev);
1547         if (sc->rl_twister_enable) {
1548                 if (sc->rl_twister == DONE)
1549                         rl_watchdog(sc);
1550                 else
1551                         rl_twister_update(sc);
1552                 if (sc->rl_twister == DONE)
1553                         ticks = hz;
1554                 else
1555                         ticks = hz / 10;
1556         } else {
1557                 rl_watchdog(sc);
1558                 ticks = hz;
1559         }
1560
1561         callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc);
1562 }
1563
1564 #ifdef DEVICE_POLLING
1565 static int
1566 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1567 {
1568         struct rl_softc *sc = ifp->if_softc;
1569         int rx_npkts = 0;
1570
1571         RL_LOCK(sc);
1572         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1573                 rx_npkts = rl_poll_locked(ifp, cmd, count);
1574         RL_UNLOCK(sc);
1575         return (rx_npkts);
1576 }
1577
1578 static int
1579 rl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1580 {
1581         struct rl_softc *sc = ifp->if_softc;
1582         int rx_npkts;
1583
1584         RL_LOCK_ASSERT(sc);
1585
1586         sc->rxcycles = count;
1587         rx_npkts = rl_rxeof(sc);
1588         rl_txeof(sc);
1589
1590         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1591                 rl_start_locked(ifp);
1592
1593         if (cmd == POLL_AND_CHECK_STATUS) {
1594                 uint16_t        status;
1595
1596                 /* We should also check the status register. */
1597                 status = CSR_READ_2(sc, RL_ISR);
1598                 if (status == 0xffff)
1599                         return (rx_npkts);
1600                 if (status != 0)
1601                         CSR_WRITE_2(sc, RL_ISR, status);
1602
1603                 /* XXX We should check behaviour on receiver stalls. */
1604
1605                 if (status & RL_ISR_SYSTEM_ERR) {
1606                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1607                         rl_init_locked(sc);
1608                 }
1609         }
1610         return (rx_npkts);
1611 }
1612 #endif /* DEVICE_POLLING */
1613
1614 static void
1615 rl_intr(void *arg)
1616 {
1617         struct rl_softc         *sc = arg;
1618         struct ifnet            *ifp = sc->rl_ifp;
1619         uint16_t                status;
1620         int                     count;
1621
1622         RL_LOCK(sc);
1623
1624         if (sc->suspended)
1625                 goto done_locked;
1626
1627 #ifdef DEVICE_POLLING
1628         if  (ifp->if_capenable & IFCAP_POLLING)
1629                 goto done_locked;
1630 #endif
1631
1632         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1633                 goto done_locked2;
1634         status = CSR_READ_2(sc, RL_ISR);
1635         if (status == 0xffff || (status & RL_INTRS) == 0)
1636                 goto done_locked;
1637         /*
1638          * Ours, disable further interrupts.
1639          */
1640         CSR_WRITE_2(sc, RL_IMR, 0);
1641         for (count = 16; count > 0; count--) {
1642                 CSR_WRITE_2(sc, RL_ISR, status);
1643                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1644                         if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR))
1645                                 rl_rxeof(sc);
1646                         if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR))
1647                                 rl_txeof(sc);
1648                         if (status & RL_ISR_SYSTEM_ERR) {
1649                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1650                                 rl_init_locked(sc);
1651                                 RL_UNLOCK(sc);
1652                                 return;
1653                         }
1654                 }
1655                 status = CSR_READ_2(sc, RL_ISR);
1656                 /* If the card has gone away, the read returns 0xffff. */
1657                 if (status == 0xffff || (status & RL_INTRS) == 0)
1658                         break;
1659         }
1660
1661         if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1662                 rl_start_locked(ifp);
1663
1664 done_locked2:
1665         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1666                 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1667 done_locked:
1668         RL_UNLOCK(sc);
1669 }
1670
1671 /*
1672  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1673  * pointers to the fragment pointers.
1674  */
1675 static int
1676 rl_encap(struct rl_softc *sc, struct mbuf **m_head)
1677 {
1678         struct mbuf             *m;
1679         bus_dma_segment_t       txsegs[1];
1680         int                     error, nsegs, padlen;
1681
1682         RL_LOCK_ASSERT(sc);
1683
1684         m = *m_head;
1685         padlen = 0;
1686         /*
1687          * Hardware doesn't auto-pad, so we have to make sure
1688          * pad short frames out to the minimum frame length.
1689          */
1690         if (m->m_pkthdr.len < RL_MIN_FRAMELEN)
1691                 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len;
1692         /*
1693          * The RealTek is brain damaged and wants longword-aligned
1694          * TX buffers, plus we can only have one fragment buffer
1695          * per packet. We have to copy pretty much all the time.
1696          */
1697         if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 ||
1698             (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) {
1699                 m = m_defrag(*m_head, M_DONTWAIT);
1700                 if (m == NULL) {
1701                         m_freem(*m_head);
1702                         *m_head = NULL;
1703                         return (ENOMEM);
1704                 }
1705         }
1706         *m_head = m;
1707
1708         if (padlen > 0) {
1709                 /*
1710                  * Make security-conscious people happy: zero out the
1711                  * bytes in the pad area, since we don't know what
1712                  * this mbuf cluster buffer's previous user might
1713                  * have left in it.
1714                  */
1715                 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
1716                 m->m_pkthdr.len += padlen;
1717                 m->m_len = m->m_pkthdr.len;
1718         }
1719
1720         error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag,
1721             RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0);
1722         if (error != 0)
1723                 return (error);
1724         if (nsegs == 0) {
1725                 m_freem(*m_head);
1726                 *m_head = NULL;
1727                 return (EIO);
1728         }
1729
1730         RL_CUR_TXMBUF(sc) = m;
1731         bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc),
1732             BUS_DMASYNC_PREWRITE);
1733         CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr));
1734
1735         return (0);
1736 }
1737
1738 /*
1739  * Main transmit routine.
1740  */
1741 static void
1742 rl_start(struct ifnet *ifp)
1743 {
1744         struct rl_softc         *sc = ifp->if_softc;
1745
1746         RL_LOCK(sc);
1747         rl_start_locked(ifp);
1748         RL_UNLOCK(sc);
1749 }
1750
1751 static void
1752 rl_start_locked(struct ifnet *ifp)
1753 {
1754         struct rl_softc         *sc = ifp->if_softc;
1755         struct mbuf             *m_head = NULL;
1756
1757         RL_LOCK_ASSERT(sc);
1758
1759         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1760             IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
1761                 return;
1762
1763         while (RL_CUR_TXMBUF(sc) == NULL) {
1764
1765                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1766
1767                 if (m_head == NULL)
1768                         break;
1769
1770                 if (rl_encap(sc, &m_head)) {
1771                         if (m_head == NULL)
1772                                 break;
1773                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1774                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1775                         break;
1776                 }
1777
1778                 /* Pass a copy of this mbuf chain to the bpf subsystem. */
1779                 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1780
1781                 /* Transmit the frame. */
1782                 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1783                     RL_TXTHRESH(sc->rl_txthresh) |
1784                     RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1785
1786                 RL_INC(sc->rl_cdata.cur_tx);
1787
1788                 /* Set a timeout in case the chip goes out to lunch. */
1789                 sc->rl_watchdog_timer = 5;
1790         }
1791
1792         /*
1793          * We broke out of the loop because all our TX slots are
1794          * full. Mark the NIC as busy until it drains some of the
1795          * packets from the queue.
1796          */
1797         if (RL_CUR_TXMBUF(sc) != NULL)
1798                 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1799 }
1800
1801 static void
1802 rl_init(void *xsc)
1803 {
1804         struct rl_softc         *sc = xsc;
1805
1806         RL_LOCK(sc);
1807         rl_init_locked(sc);
1808         RL_UNLOCK(sc);
1809 }
1810
1811 static void
1812 rl_init_locked(struct rl_softc *sc)
1813 {
1814         struct ifnet            *ifp = sc->rl_ifp;
1815         struct mii_data         *mii;
1816         uint32_t                eaddr[2];
1817
1818         RL_LOCK_ASSERT(sc);
1819
1820         mii = device_get_softc(sc->rl_miibus);
1821
1822         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1823                 return;
1824
1825         /*
1826          * Cancel pending I/O and free all RX/TX buffers.
1827          */
1828         rl_stop(sc);
1829
1830         rl_reset(sc);
1831         if (sc->rl_twister_enable) {
1832                 /*
1833                  * Reset twister register tuning state.  The twister
1834                  * registers and their tuning are undocumented, but
1835                  * are necessary to cope with bad links.  rl_twister =
1836                  * DONE here will disable this entirely.
1837                  */
1838                 sc->rl_twister = CHK_LINK;
1839         }
1840
1841         /*
1842          * Init our MAC address.  Even though the chipset
1843          * documentation doesn't mention it, we need to enter "Config
1844          * register write enable" mode to modify the ID registers.
1845          */
1846         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1847         bzero(eaddr, sizeof(eaddr));
1848         bcopy(IF_LLADDR(sc->rl_ifp), eaddr, ETHER_ADDR_LEN);
1849         CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]);
1850         CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]);
1851         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1852
1853         /* Init the RX memory block pointer register. */
1854         CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr +
1855             RL_RX_8139_BUF_RESERVE);
1856         /* Init TX descriptors. */
1857         rl_list_tx_init(sc);
1858         /* Init Rx memory block. */
1859         rl_list_rx_init(sc);
1860
1861         /*
1862          * Enable transmit and receive.
1863          */
1864         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1865
1866         /*
1867          * Set the initial TX and RX configuration.
1868          */
1869         CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1870         CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1871
1872         /* Set RX filter. */
1873         rl_rxfilter(sc);
1874
1875 #ifdef DEVICE_POLLING
1876         /* Disable interrupts if we are polling. */
1877         if (ifp->if_capenable & IFCAP_POLLING)
1878                 CSR_WRITE_2(sc, RL_IMR, 0);
1879         else
1880 #endif
1881         /* Enable interrupts. */
1882         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1883
1884         /* Set initial TX threshold */
1885         sc->rl_txthresh = RL_TX_THRESH_INIT;
1886
1887         /* Start RX/TX process. */
1888         CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1889
1890         /* Enable receiver and transmitter. */
1891         CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1892
1893         sc->rl_flags &= ~RL_FLAG_LINK;
1894         mii_mediachg(mii);
1895
1896         CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1897
1898         ifp->if_drv_flags |= IFF_DRV_RUNNING;
1899         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1900
1901         callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc);
1902 }
1903
1904 /*
1905  * Set media options.
1906  */
1907 static int
1908 rl_ifmedia_upd(struct ifnet *ifp)
1909 {
1910         struct rl_softc         *sc = ifp->if_softc;
1911         struct mii_data         *mii;
1912
1913         mii = device_get_softc(sc->rl_miibus);
1914
1915         RL_LOCK(sc);
1916         mii_mediachg(mii);
1917         RL_UNLOCK(sc);
1918
1919         return (0);
1920 }
1921
1922 /*
1923  * Report current media status.
1924  */
1925 static void
1926 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1927 {
1928         struct rl_softc         *sc = ifp->if_softc;
1929         struct mii_data         *mii;
1930
1931         mii = device_get_softc(sc->rl_miibus);
1932
1933         RL_LOCK(sc);
1934         mii_pollstat(mii);
1935         RL_UNLOCK(sc);
1936         ifmr->ifm_active = mii->mii_media_active;
1937         ifmr->ifm_status = mii->mii_media_status;
1938 }
1939
1940 static int
1941 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1942 {
1943         struct ifreq            *ifr = (struct ifreq *)data;
1944         struct mii_data         *mii;
1945         struct rl_softc         *sc = ifp->if_softc;
1946         int                     error = 0, mask;
1947
1948         switch (command) {
1949         case SIOCSIFFLAGS:
1950                 RL_LOCK(sc);
1951                 if (ifp->if_flags & IFF_UP) {
1952                         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1953                             ((ifp->if_flags ^ sc->rl_if_flags) &
1954                             (IFF_PROMISC | IFF_ALLMULTI)))
1955                                 rl_rxfilter(sc);
1956                         else
1957                                 rl_init_locked(sc);
1958                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1959                         rl_stop(sc);
1960                 sc->rl_if_flags = ifp->if_flags;
1961                 RL_UNLOCK(sc);
1962                 break;
1963         case SIOCADDMULTI:
1964         case SIOCDELMULTI:
1965                 RL_LOCK(sc);
1966                 rl_rxfilter(sc);
1967                 RL_UNLOCK(sc);
1968                 break;
1969         case SIOCGIFMEDIA:
1970         case SIOCSIFMEDIA:
1971                 mii = device_get_softc(sc->rl_miibus);
1972                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1973                 break;
1974         case SIOCSIFCAP:
1975                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1976 #ifdef DEVICE_POLLING
1977                 if (ifr->ifr_reqcap & IFCAP_POLLING &&
1978                     !(ifp->if_capenable & IFCAP_POLLING)) {
1979                         error = ether_poll_register(rl_poll, ifp);
1980                         if (error)
1981                                 return(error);
1982                         RL_LOCK(sc);
1983                         /* Disable interrupts */
1984                         CSR_WRITE_2(sc, RL_IMR, 0x0000);
1985                         ifp->if_capenable |= IFCAP_POLLING;
1986                         RL_UNLOCK(sc);
1987                         return (error);
1988
1989                 }
1990                 if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
1991                     ifp->if_capenable & IFCAP_POLLING) {
1992                         error = ether_poll_deregister(ifp);
1993                         /* Enable interrupts. */
1994                         RL_LOCK(sc);
1995                         CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1996                         ifp->if_capenable &= ~IFCAP_POLLING;
1997                         RL_UNLOCK(sc);
1998                         return (error);
1999                 }
2000 #endif /* DEVICE_POLLING */
2001                 if ((mask & IFCAP_WOL) != 0 &&
2002                     (ifp->if_capabilities & IFCAP_WOL) != 0) {
2003                         if ((mask & IFCAP_WOL_UCAST) != 0)
2004                                 ifp->if_capenable ^= IFCAP_WOL_UCAST;
2005                         if ((mask & IFCAP_WOL_MCAST) != 0)
2006                                 ifp->if_capenable ^= IFCAP_WOL_MCAST;
2007                         if ((mask & IFCAP_WOL_MAGIC) != 0)
2008                                 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2009                 }
2010                 break;
2011         default:
2012                 error = ether_ioctl(ifp, command, data);
2013                 break;
2014         }
2015
2016         return (error);
2017 }
2018
2019 static void
2020 rl_watchdog(struct rl_softc *sc)
2021 {
2022
2023         RL_LOCK_ASSERT(sc);
2024
2025         if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0)
2026                 return;
2027
2028         device_printf(sc->rl_dev, "watchdog timeout\n");
2029         sc->rl_ifp->if_oerrors++;
2030
2031         rl_txeof(sc);
2032         rl_rxeof(sc);
2033         sc->rl_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2034         rl_init_locked(sc);
2035 }
2036
2037 /*
2038  * Stop the adapter and free any mbufs allocated to the
2039  * RX and TX lists.
2040  */
2041 static void
2042 rl_stop(struct rl_softc *sc)
2043 {
2044         register int            i;
2045         struct ifnet            *ifp = sc->rl_ifp;
2046
2047         RL_LOCK_ASSERT(sc);
2048
2049         sc->rl_watchdog_timer = 0;
2050         callout_stop(&sc->rl_stat_callout);
2051         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2052         sc->rl_flags &= ~RL_FLAG_LINK;
2053
2054         CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2055         CSR_WRITE_2(sc, RL_IMR, 0x0000);
2056         for (i = 0; i < RL_TIMEOUT; i++) {
2057                 DELAY(10);
2058                 if ((CSR_READ_1(sc, RL_COMMAND) &
2059                     (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0)
2060                         break;
2061         }
2062         if (i == RL_TIMEOUT)
2063                 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n");
2064
2065         /*
2066          * Free the TX list buffers.
2067          */
2068         for (i = 0; i < RL_TX_LIST_CNT; i++) {
2069                 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2070                         if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
2071                                 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag,
2072                                     sc->rl_cdata.rl_tx_dmamap[i],
2073                                     BUS_DMASYNC_POSTWRITE);
2074                                 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag,
2075                                     sc->rl_cdata.rl_tx_dmamap[i]);
2076                                 m_freem(sc->rl_cdata.rl_tx_chain[i]);
2077                                 sc->rl_cdata.rl_tx_chain[i] = NULL;
2078                         }
2079                         CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
2080                             0x0000000);
2081                 }
2082         }
2083 }
2084
2085 /*
2086  * Device suspend routine.  Stop the interface and save some PCI
2087  * settings in case the BIOS doesn't restore them properly on
2088  * resume.
2089  */
2090 static int
2091 rl_suspend(device_t dev)
2092 {
2093         struct rl_softc         *sc;
2094
2095         sc = device_get_softc(dev);
2096
2097         RL_LOCK(sc);
2098         rl_stop(sc);
2099         rl_setwol(sc);
2100         sc->suspended = 1;
2101         RL_UNLOCK(sc);
2102
2103         return (0);
2104 }
2105
2106 /*
2107  * Device resume routine.  Restore some PCI settings in case the BIOS
2108  * doesn't, re-enable busmastering, and restart the interface if
2109  * appropriate.
2110  */
2111 static int
2112 rl_resume(device_t dev)
2113 {
2114         struct rl_softc         *sc;
2115         struct ifnet            *ifp;
2116         int                     pmc;
2117         uint16_t                pmstat;
2118
2119         sc = device_get_softc(dev);
2120         ifp = sc->rl_ifp;
2121
2122         RL_LOCK(sc);
2123
2124         if ((ifp->if_capabilities & IFCAP_WOL) != 0 &&
2125             pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) == 0) {
2126                 /* Disable PME and clear PME status. */
2127                 pmstat = pci_read_config(sc->rl_dev,
2128                     pmc + PCIR_POWER_STATUS, 2);
2129                 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
2130                         pmstat &= ~PCIM_PSTAT_PMEENABLE;
2131                         pci_write_config(sc->rl_dev,
2132                             pmc + PCIR_POWER_STATUS, pmstat, 2);
2133                 }
2134                 /*
2135                  * Clear WOL matching such that normal Rx filtering
2136                  * wouldn't interfere with WOL patterns.
2137                  */
2138                 rl_clrwol(sc);
2139         }
2140
2141         /* reinitialize interface if necessary */
2142         if (ifp->if_flags & IFF_UP)
2143                 rl_init_locked(sc);
2144
2145         sc->suspended = 0;
2146
2147         RL_UNLOCK(sc);
2148
2149         return (0);
2150 }
2151
2152 /*
2153  * Stop all chip I/O so that the kernel's probe routines don't
2154  * get confused by errant DMAs when rebooting.
2155  */
2156 static int
2157 rl_shutdown(device_t dev)
2158 {
2159         struct rl_softc         *sc;
2160
2161         sc = device_get_softc(dev);
2162
2163         RL_LOCK(sc);
2164         rl_stop(sc);
2165         /*
2166          * Mark interface as down since otherwise we will panic if
2167          * interrupt comes in later on, which can happen in some
2168          * cases.
2169          */
2170         sc->rl_ifp->if_flags &= ~IFF_UP;
2171         rl_setwol(sc);
2172         RL_UNLOCK(sc);
2173
2174         return (0);
2175 }
2176
2177 static void
2178 rl_setwol(struct rl_softc *sc)
2179 {
2180         struct ifnet            *ifp;
2181         int                     pmc;
2182         uint16_t                pmstat;
2183         uint8_t                 v;
2184
2185         RL_LOCK_ASSERT(sc);
2186
2187         ifp = sc->rl_ifp;
2188         if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2189                 return;
2190         if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
2191                 return;
2192
2193         /* Enable config register write. */
2194         CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2195
2196         /* Enable PME. */
2197         v = CSR_READ_1(sc, RL_CFG1);
2198         v &= ~RL_CFG1_PME;
2199         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2200                 v |= RL_CFG1_PME;
2201         CSR_WRITE_1(sc, RL_CFG1, v);
2202
2203         v = CSR_READ_1(sc, RL_CFG3);
2204         v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2205         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
2206                 v |= RL_CFG3_WOL_MAGIC;
2207         CSR_WRITE_1(sc, RL_CFG3, v);
2208
2209         /* Config register write done. */
2210         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2211
2212         v = CSR_READ_1(sc, RL_CFG5);
2213         v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2214         v &= ~RL_CFG5_WOL_LANWAKE;
2215         if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
2216                 v |= RL_CFG5_WOL_UCAST;
2217         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
2218                 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
2219         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2220                 v |= RL_CFG5_WOL_LANWAKE;
2221         CSR_WRITE_1(sc, RL_CFG5, v);
2222         /* Request PME if WOL is requested. */
2223         pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
2224         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
2225         if ((ifp->if_capenable & IFCAP_WOL) != 0)
2226                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2227         pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
2228 }
2229
2230 static void
2231 rl_clrwol(struct rl_softc *sc)
2232 {
2233         struct ifnet            *ifp;
2234         uint8_t                 v;
2235
2236         ifp = sc->rl_ifp;
2237         if ((ifp->if_capabilities & IFCAP_WOL) == 0)
2238                 return;
2239
2240         /* Enable config register write. */
2241         CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
2242
2243         v = CSR_READ_1(sc, RL_CFG3);
2244         v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
2245         CSR_WRITE_1(sc, RL_CFG3, v);
2246
2247         /* Config register write done. */
2248         CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2249
2250         v = CSR_READ_1(sc, RL_CFG5);
2251         v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
2252         v &= ~RL_CFG5_WOL_LANWAKE;
2253         CSR_WRITE_1(sc, RL_CFG5, v);
2254 }