2 * Copyright (c) 2012 The FreeBSD Foundation
3 * Copyright (c) 2013 Rui Paulo
6 * This software was developed by Semihalf under sponsorship from
7 * the FreeBSD Foundation.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Freescale i.MX535 Device Tree Source.
50 compatible = "ARM,MCIMX535";
52 d-cache-line-size = <32>;
53 i-cache-line-size = <32>;
54 d-cache-size = <0x8000>;
55 i-cache-size = <0x8000>;
56 l2-cache-line-size = <32>;
57 l2-cache-line = <0x40000>;
58 timebase-frequency = <0>;
60 clock-frequency = <0>;
65 compatible = "simple-bus";
69 /* This reflects CPU decode windows setup. */
72 tzic: tz-interrupt-controller@0fffc000 {
73 compatible = "fsl,imx53-tzic", "fsl,tzic";
75 #interrupt-cells = <1>;
76 reg = <0x0fffc000 0x00004000>;
79 * 40000000 40000FFF 4K Debug ROM
80 * 40001000 40001FFF 4K ETB
81 * 40002000 40002FFF 4K ETM
82 * 40003000 40003FFF 4K TPIU
83 * 40004000 40004FFF 4K CTI0
84 * 40005000 40005FFF 4K CTI1
85 * 40006000 40006FFF 4K CTI2
86 * 40007000 40007FFF 4K CTI3
87 * 40008000 40008FFF 4K ARM Debug Unit
89 * 0FFFC000 0FFFCFFF 0x4000 TZIC
94 compatible = "simple-bus";
97 interrupt-parent = <&tzic>;
98 ranges = <0x50000000 0x14000000>;
100 aips@50000000 { /* AIPS1 */
101 compatible = "fsl,aips-bus", "simple-bus";
102 #address-cells = <1>;
104 interrupt-parent = <&tzic>;
107 /* Required by many devices, so better to stay first */
108 /* 53FD4000 0x4000 CCM */
110 compatible = "fsl,imx53-ccm";
111 /* 63F80000 0x4000 DPLLIP1 */
112 /* 63F84000 0x4000 DPLLIP2 */
113 /* 63F88000 0x4000 DPLLIP3 */
114 reg = <0x53fd4000 0x4000
118 interrupt-parent = <&tzic>;
119 interrupts = <71 72>;
124 * GPIO modules moved up - to have it attached for
125 * drivers which rely on GPIO
127 /* 53F84000 0x4000 GPIO1 */
128 gpio1: gpio@53f84000 {
129 compatible = "fsl,imx53-gpio";
130 reg = <0x53f84000 0x4000>;
131 interrupt-parent = <&tzic>;
132 interrupts = <50 51 42 43 44 45 46 47 48 49>;
133 /* TODO: use <> also */
136 interrupt-controller;
137 #interrupt-cells = <1>;
140 /* 53F88000 0x4000 GPIO2 */
141 gpio2: gpio@53f88000 {
142 compatible = "fsl,imx53-gpio";
143 reg = <0x53f88000 0x4000>;
144 interrupt-parent = <&tzic>;
145 interrupts = <52 53>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
152 /* 53F8C000 0x4000 GPIO3 */
153 gpio3: gpio@53f8c000 {
154 compatible = "fsl,imx53-gpio";
155 reg = <0x53f8c000 0x4000>;
156 interrupt-parent = <&tzic>;
157 interrupts = <54 55>;
160 interrupt-controller;
161 #interrupt-cells = <1>;
164 /* 53F90000 0x4000 GPIO4 */
165 gpio4: gpio@53f90000 {
166 compatible = "fsl,imx53-gpio";
167 reg = <0x53f90000 0x4000>;
168 interrupt-parent = <&tzic>;
169 interrupts = <56 57>;
172 interrupt-controller;
173 #interrupt-cells = <1>;
176 /* 53FDC000 0x4000 GPIO5 */
177 gpio5: gpio@53fdc000 {
178 compatible = "fsl,imx53-gpio";
179 reg = <0x53fdc000 0x4000>;
180 interrupt-parent = <&tzic>;
181 interrupts = <103 104>;
184 interrupt-controller;
185 #interrupt-cells = <1>;
188 /* 53FE0000 0x4000 GPIO6 */
189 gpio6: gpio@53fe0000 {
190 compatible = "fsl,imx53-gpio";
191 reg = <0x53fe0000 0x4000>;
192 interrupt-parent = <&tzic>;
193 interrupts = <105 106>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
200 /* 53FE4000 0x4000 GPIO5 */
201 gpio7: gpio@53fe4000 {
202 compatible = "fsl,imx53-gpio";
203 reg = <0x53fe4000 0x4000>;
204 interrupt-parent = <&tzic>;
205 interrupts = <107 108>;
208 interrupt-controller;
209 #interrupt-cells = <1>;
213 compatible = "fsl,spba-bus", "simple-bus";
214 #address-cells = <1>;
216 interrupt-parent = <&tzic>;
219 /* 50004000 0x4000 ESDHC 1 */
221 compatible = "fsl,imx53-esdhc";
222 reg = <0x50004000 0x4000>;
223 interrupt-parent = <&tzic>; interrupts = <1>;
227 /* 50008000 0x4000 ESDHC 2 */
229 compatible = "fsl,imx53-esdhc";
230 reg = <0x50008000 0x4000>;
231 interrupt-parent = <&tzic>; interrupts = <2>;
235 /* 5000C000 0x4000 UART 3 */
236 uart3: serial@5000c000 {
237 compatible = "fsl,imx53-uart", "fsl,imx-uart";
238 reg = <0x5000c000 0x4000>;
239 interrupt-parent = <&tzic>;
244 /* 50010000 0x4000 eCSPI1 */
246 #address-cells = <1>;
248 compatible = "fsl,imx53-ecspi";
249 reg = <0x50010000 0x4000>;
250 interrupt-parent = <&tzic>;
255 /* 50014000 0x4000 SSI2 irq30 */
257 compatible = "fsl,imx53-ssi";
258 reg = <0x50014000 0x4000>;
259 interrupt-parent = <&tzic>;
264 /* 50020000 0x4000 ESDHC 3 */
266 compatible = "fsl,imx53-esdhc";
267 reg = <0x50020000 0x4000>;
268 interrupt-parent = <&tzic>;
273 /* 50024000 0x4000 ESDHC 4 */
275 compatible = "fsl,imx53-esdhc";
276 reg = <0x50024000 0x4000>;
277 interrupt-parent = <&tzic>;
282 /* 50028000 0x4000 SPDIF */
285 /* 50030000 0x4000 PATA (PORT UDMA) irq70 */
287 /* 50034000 0x4000 SLM */
288 /* 50038000 0x4000 HSI2C */
290 /* 5003C000 0x4000 SPBA */
293 /* 73F80000 0x4000 USBOH3 */
294 /* irq14 USBOH3 USB Host 1 */
295 /* irq16 USBOH3 USB Host 2 */
296 /* irq17 USBOH3 USB Host 3 */
297 /* irq18 USBOH3 USB OTG */
299 compatible = "fsl,usb-4core";
300 reg = <0x53f80000 0x4000>;
301 interrupt-parent = <&tzic>;
302 interrupts = <18 14 16 17>;
305 /* 53F98000 0x4000 WDOG1 */
307 compatible = "fsl,imx53-wdt";
308 reg = <0x53f98000 0x4000>;
309 interrupt-parent = <&tzic>;
314 /* 53F9C000 0x4000 WDOG2 (TZ) */
316 compatible = "fsl,imx53-wdt";
317 reg = <0x53f9c000 0x4000>;
318 interrupt-parent = <&tzic>;
323 /* 53F94000 0x4000 KPP */
325 compatible = "fsl,imx53-kpp";
326 reg = <0x53f94000 0x4000>;
327 interrupt-parent = <&tzic>;
332 /* 53FA0000 0x4000 GPT */
334 compatible = "fsl,imx53-gpt";
335 reg = <0x53fa0000 0x4000>;
336 interrupt-parent = <&tzic>;
341 /* 53FA4000 0x4000 SRTC */
344 compatible = "fsl,imx53-srtc";
345 reg = <0x53fa4000 0x4000>;
346 interrupt-parent = <&tzic>;
347 interrupts = <24 25>;
351 /* 53FA8000 0x4000 IOMUXC */
353 compatible = "fsl,imx53-iomux";
354 reg = <0x53fa8000 0x4000>;
355 interrupt-parent = <&tzic>;
359 /* 53FAC000 0x4000 EPIT1 */
360 epit1: timer@53fac000 {
361 compatible = "fsl,imx53-epit";
362 reg = <0x53fac000 0x4000>;
363 interrupt-parent = <&tzic>;
368 /* 53FB0000 0x4000 EPIT2 */
369 epit2: timer@53fb0000 {
370 compatible = "fsl,imx53-epit";
371 reg = <0x53fb0000 0x4000>;
372 interrupt-parent = <&tzic>;
377 /* 53FB4000 0x4000 PWM1 */
379 compatible = "fsl,imx53-pwm";
380 reg = <0x53fb4000 0x4000>;
381 interrupt-parent = <&tzic>;
386 /* 53FB8000 0x4000 PWM2 */
388 compatible = "fsl,imx53-pwm";
389 reg = <0x53fb8000 0x4000>;
390 interrupt-parent = <&tzic>;
395 /* 53FBC000 0x4000 UART 1 */
396 uart1: serial@53fbc000 {
397 compatible = "fsl,imx53-uart", "fsl,imx-uart";
398 reg = <0x53fbc000 0x4000>;
399 interrupt-parent = <&tzic>;
404 /* 53FC0000 0x4000 UART 2 */
405 uart2: serial@53fc0000 {
406 compatible = "fsl,imx53-uart", "fsl,imx-uart";
407 reg = <0x53fc0000 0x4000>;
408 interrupt-parent = <&tzic>;
413 /* 53FC0000 0x4000 UART 4 */
414 uart4: serial@53ff0000 {
415 compatible = "fsl,imx53-uart", "fsl,imx-uart";
416 reg = <0x53ff0000 0x4000>;
417 interrupt-parent = <&tzic>;
424 /* 53FC4000 0x4000 USBOH3 */
427 compatible = "fsl,imx53-otg";
428 reg = <0x53fc4000 0x4000>;
429 interrupt-parent = <&tzic>;
434 /* 53FD0000 0x4000 SRC */
436 compatible = "fsl,imx53-src";
437 reg = <0x53fd0000 0x4000>;
438 interrupt-parent = <&tzic>;
442 /* 53FD8000 0x4000 GPC */
444 compatible = "fsl,imx53-gpc";
445 reg = <0x53fd8000 0x4000>;
446 interrupt-parent = <&tzic>;
447 interrupts = <73 74>;
451 /* 53FE8000 0x4000 PATA (PORT PIO) */
452 /* 70 PATA Parallel ATA host controller interrupt */
454 compatible = "fsl,imx53-ata";
455 reg = <0x83fe0000 0x4000>;
456 interrupt-parent = <&tzic>;
463 aips@60000000 { /* AIPS2 */
464 compatible = "fsl,aips-bus", "simple-bus";
465 #address-cells = <1>;
467 interrupt-parent = <&tzic>;
470 /* 53FC0000 0x4000 UART 5 */
471 uart5: serial@63f90000 {
472 compatible = "fsl,imx53-uart", "fsl,imx-uart";
473 reg = <0x63f90000 0x4000>;
474 interrupt-parent = <&tzic>;
479 /* 63F94000 0x4000 AHBMAX */
480 /* 63F98000 0x4000 IIM */
482 * 69 IIM Interrupt request to the processor.
483 * Indicates to the processor that program or
486 /* 63F9C000 0x4000 CSU */
488 * 27 CSU Interrupt Request 1. Indicates to the
489 * processor that one or more alarm inputs were.
492 /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
493 /* irq76 Neon Monitor Interrupt */
494 /* irq77 Performance Unit Interrupt */
496 /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
497 /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
498 /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
499 /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
501 /* 63FA4000 0x4000 OWIRE irq88 */
502 /* 63FA8000 0x4000 FIRI irq93 */
503 /* 63FAC000 0x4000 eCSPI2 */
505 #address-cells = <1>;
507 compatible = "fsl,imx53-ecspi";
508 reg = <0x63fac000 0x4000>;
509 interrupt-parent = <&tzic>;
514 /* 63FB0000 0x4000 SDMA */
516 compatible = "fsl,imx53-sdma";
517 reg = <0x63fb0000 0x4000>;
518 interrupt-parent = <&tzic>;
522 /* 63FB4000 0x4000 SCC */
523 /* 21 SCC Security Monitor High Priority Interrupt. */
524 /* 22 SCC Secure (TrustZone) Interrupt. */
525 /* 23 SCC Regular (Non-Secure) Interrupt. */
527 /* 63FB8000 0x4000 ROMCP */
528 /* 63FBC000 0x4000 RTIC */
530 * 26 RTIC RTIC (Trust Zone) Interrupt Request.
531 * Indicates that the RTIC has completed hashing the
534 /* 63FC0000 0x4000 CSPI */
536 #address-cells = <1>;
538 compatible = "fsl,imx53-cspi";
539 reg = <0x63fc0000 0x4000>;
540 interrupt-parent = <&tzic>;
545 /* 63FC4000 0x4000 I2C2 */
547 #address-cells = <1>;
549 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
550 reg = <0x63fc4000 0x4000>;
551 interrupt-parent = <&tzic>;
556 /* 63FC8000 0x4000 I2C1 */
558 #address-cells = <1>;
560 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
561 reg = <0x63fc8000 0x4000>;
562 interrupt-parent = <&tzic>;
567 /* 63FCC000 0x4000 SSI1 */
568 /* 29 SSI1 SSI-1 Interrupt Request */
570 compatible = "fsl,imx53-ssi";
571 reg = <0x63fcc000 0x4000>;
572 interrupt-parent = <&tzic>;
577 /* 63FD0000 0x4000 AUDMUX */
579 compatible = "fsl,imx53-audmux";
580 reg = <0x63fd4000 0x4000>;
584 /* 63FD8000 0x4000 EXTMC */
587 /* 97 EXTMC Boot sequence completed interrupt */
589 * 101 EMI Indicates all pages have been transferred
590 * to NFC during an auto program operation.
593 /* 83FE4000 0x4000 SIM */
594 /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
595 /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
597 /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */
598 /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */
599 /* 63FE4000 0x4000 MLB */
600 /* 63FE8000 0x4000 SSI3 */
601 /* 96 SSI3 SSI-3 Interrupt Request */
603 compatible = "fsl,imx51-ssi";
604 reg = <0x63fe8000 0x4000>;
605 interrupt-parent = <&tzic>;
610 /* 63FEC000 0x4000 FEC */
612 compatible = "fsl,imx53-fec";
613 reg = <0x63fec000 0x4000>;
614 interrupt-parent = <&tzic>;
619 /* 63FF0000 0x4000 TVE */
621 /* 63FF4000 0x4000 VPU */
623 /* 100 VPU Idle interrupt from VPU */
625 /* 63FF8000 0x4000 SAHARA */
626 /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */
627 /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */
632 compatible = "simple-bus";
633 #address-cells = <1>;
639 compatible = "fsl,ipu3";
641 0x18000000 0x08000 /* CM */
642 0x18008000 0x08000 /* IDMAC */
643 0x18018000 0x08000 /* DP */
644 0x18020000 0x08000 /* IC */
645 0x18028000 0x08000 /* IRT */
646 0x18030000 0x08000 /* CSI0 */
647 0x18038000 0x08000 /* CSI1 */
648 0x18040000 0x08000 /* DI0 */
649 0x18048000 0x08000 /* DI1 */
650 0x18050000 0x08000 /* SMFC */
651 0x18058000 0x08000 /* DC */
652 0x18060000 0x08000 /* DMFC */
653 0x18068000 0x08000 /* VDI */
654 0x19000000 0x20000 /* CPMEM */
655 0x19020000 0x20000 /* LUT */
656 0x19040000 0x20000 /* SRM */
657 0x19060000 0x20000 /* TPM */
658 0x19080000 0x20000 /* DCTMPL */
660 interrupt-parent = <&tzic>;
672 TODO: Not mapped interrupts
675 84 GPU2D (OpenVG) general interrupt
676 85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
678 102 GPU3D Idle interrupt from GPU3D (for S/W power gating)