sys/boot/fdt/dts/imx53x.dtsi

   1 /*
   2  * Copyright (c) 2012 The FreeBSD Foundation
   3  * Copyright (c) 2013 Rui Paulo
   4  * All rights reserved.
   5  *
   6  * This software was developed by Semihalf under sponsorship from
   7  * the FreeBSD Foundation.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  *
  30  * Freescale i.MX535 Device Tree Source.
  31  *
  32  * $FreeBSD$
  33  */
  34
  35 / {
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38
  39         aliases {
  40                 soc = &SOC;
  41         };
  42
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "ARM,MCIMX535";
  51                         reg = <0x0>;
  52                         d-cache-line-size = <32>;
  53                         i-cache-line-size = <32>;
  54                         d-cache-size = <0x8000>;
  55                         i-cache-size = <0x8000>;
  56                         l2-cache-line-size = <32>;
  57                         l2-cache-line = <0x40000>;
  58                         timebase-frequency = <0>;
  59                         bus-frequency = <0>;
  60                         clock-frequency = <0>;
  61                 };
  62         };
  63
  64         localbus@0fffc000 {
  65                 compatible = "simple-bus";
  66                 #address-cells = <1>;
  67                 #size-cells = <1>;
  68
  69                 /* This reflects CPU decode windows setup. */
  70                 ranges;
  71
  72                 tzic: tz-interrupt-controller@0fffc000 {
  73                         compatible = "fsl,imx53-tzic", "fsl,tzic";
  74                         interrupt-controller;
  75                         #interrupt-cells = <1>;
  76                         reg = <0x0fffc000 0x00004000>;
  77                 };
  78                 /*
  79                  * 40000000 40000FFF 4K Debug ROM
  80                  * 40001000 40001FFF 4K ETB
  81                  * 40002000 40002FFF 4K ETM
  82                  * 40003000 40003FFF 4K TPIU
  83                  * 40004000 40004FFF 4K CTI0
  84                  * 40005000 40005FFF 4K CTI1
  85                  * 40006000 40006FFF 4K CTI2
  86                  * 40007000 40007FFF 4K CTI3
  87                  * 40008000 40008FFF 4K ARM Debug Unit
  88                  *
  89                  * 0FFFC000 0FFFCFFF 0x4000 TZIC
  90                  */
  91         };
  92
  93         SOC: soc@50000000 {
  94                 compatible = "simple-bus";
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 interrupt-parent = <&tzic>;
  98                 ranges = <0x50000000 0x14000000>;
  99
 100                 aips@50000000 { /* AIPS1 */
 101                         compatible = "fsl,aips-bus", "simple-bus";
 102                         #address-cells = <1>;
 103                         #size-cells = <1>;
 104                         interrupt-parent = <&tzic>;
 105                         ranges;
 106
 107                         /* Required by many devices, so better to stay first */
 108                         /* 53FD4000 0x4000 CCM */
 109                         clock@53fd4000 {
 110                                 compatible = "fsl,imx53-ccm";
 111                         /* 63F80000 0x4000 DPLLIP1 */
 112                         /* 63F84000 0x4000 DPLLIP2 */
 113                         /* 63F88000 0x4000 DPLLIP3 */
 114                                 reg = <0x53fd4000 0x4000
 115                                         0x63F80000 0x4000
 116                                         0x63F84000 0x4000
 117                                         0x63F88000 0x4000>;
 118                                 interrupt-parent = <&tzic>;
 119                                 interrupts = <71 72>;
 120                                 status = "disabled";
 121                         };
 122
 123                         /*
 124                          * GPIO modules moved up - to have it attached for
 125                          * drivers which rely on GPIO
 126                          */
 127                         /* 53F84000 0x4000 GPIO1 */
 128                         gpio1: gpio@53f84000 {
 129                                 compatible = "fsl,imx53-gpio";
 130                                 reg = <0x53f84000 0x4000>;
 131                                 interrupt-parent = <&tzic>;
 132                                 interrupts = <50 51 42 43 44 45 46 47 48 49>;
 133                                 /* TODO: use <> also */
 134                                 gpio-controller;
 135                                 #gpio-cells = <2>;
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <1>;
 138                         };
 139
 140                         /* 53F88000 0x4000 GPIO2 */
 141                         gpio2: gpio@53f88000 {
 142                                 compatible = "fsl,imx53-gpio";
 143                                 reg = <0x53f88000 0x4000>;
 144                                 interrupt-parent = <&tzic>;
 145                                 interrupts = <52 53>;
 146                                 gpio-controller;
 147                                 #gpio-cells = <2>;
 148                                 interrupt-controller;
 149                                 #interrupt-cells = <1>;
 150                         };
 151
 152                         /* 53F8C000 0x4000 GPIO3 */
 153                         gpio3: gpio@53f8c000 {
 154                                 compatible = "fsl,imx53-gpio";
 155                                 reg = <0x53f8c000 0x4000>;
 156                                 interrupt-parent = <&tzic>;
 157                                 interrupts = <54 55>;
 158                                 gpio-controller;
 159                                 #gpio-cells = <2>;
 160                                 interrupt-controller;
 161                                 #interrupt-cells = <1>;
 162                         };
 163
 164                         /* 53F90000 0x4000 GPIO4 */
 165                         gpio4: gpio@53f90000 {
 166                                 compatible = "fsl,imx53-gpio";
 167                                 reg = <0x53f90000 0x4000>;
 168                                 interrupt-parent = <&tzic>;
 169                                 interrupts = <56 57>;
 170                                 gpio-controller;
 171                                 #gpio-cells = <2>;
 172                                 interrupt-controller;
 173                                 #interrupt-cells = <1>;
 174                         };
 175
 176                         /* 53FDC000 0x4000 GPIO5 */
 177                         gpio5: gpio@53fdc000 {
 178                                 compatible = "fsl,imx53-gpio";
 179                                 reg = <0x53fdc000 0x4000>;
 180                                 interrupt-parent = <&tzic>;
 181                                 interrupts = <103 104>;
 182                                 gpio-controller;
 183                                 #gpio-cells = <2>;
 184                                 interrupt-controller;
 185                                 #interrupt-cells = <1>;
 186                         };
 187
 188                         /* 53FE0000 0x4000 GPIO6 */
 189                         gpio6: gpio@53fe0000 {
 190                                 compatible = "fsl,imx53-gpio";
 191                                 reg = <0x53fe0000 0x4000>;
 192                                 interrupt-parent = <&tzic>;
 193                                 interrupts = <105 106>;
 194                                 gpio-controller;
 195                                 #gpio-cells = <2>;
 196                                 interrupt-controller;
 197                                 #interrupt-cells = <1>;
 198                         };
 199
 200                         /* 53FE4000 0x4000 GPIO5 */
 201                         gpio7: gpio@53fe4000 {
 202                                 compatible = "fsl,imx53-gpio";
 203                                 reg = <0x53fe4000 0x4000>;
 204                                 interrupt-parent = <&tzic>;
 205                                 interrupts = <107 108>;
 206                                 gpio-controller;
 207                                 #gpio-cells = <2>;
 208                                 interrupt-controller;
 209                                 #interrupt-cells = <1>;
 210                         };
 211
 212                         spba@50000000 {
 213                                 compatible = "fsl,spba-bus", "simple-bus";
 214                                 #address-cells = <1>;
 215                                 #size-cells = <1>;
 216                                 interrupt-parent = <&tzic>;
 217                                 ranges;
 218
 219                                 /* 50004000 0x4000 ESDHC 1 */
 220                                 esdhc@50004000 {
 221                                         compatible = "fsl,imx53-esdhc";
 222                                         reg = <0x50004000 0x4000>;
 223                                         interrupt-parent = <&tzic>; interrupts = <1>;
 224                                         status = "disabled";
 225                                 };
 226
 227                                 /* 50008000 0x4000 ESDHC 2 */
 228                                 esdhc@50008000 {
 229                                         compatible = "fsl,imx53-esdhc";
 230                                         reg = <0x50008000 0x4000>;
 231                                         interrupt-parent = <&tzic>; interrupts = <2>;
 232                                         status = "disabled";
 233                                 };
 234
 235                                 /* 5000C000 0x4000 UART 3 */
 236                                 uart3: serial@5000c000 {
 237                                         compatible = "fsl,imx53-uart", "fsl,imx-uart";
 238                                         reg = <0x5000c000 0x4000>;
 239                                         interrupt-parent = <&tzic>;
 240                                         interrupts = <33>;
 241                                         status = "disabled";
 242                                 };
 243
 244                                 /* 50010000 0x4000 eCSPI1 */
 245                                 ecspi@50010000 {
 246                                         #address-cells = <1>;
 247                                         #size-cells = <0>;
 248                                         compatible = "fsl,imx53-ecspi";
 249                                         reg = <0x50010000 0x4000>;
 250                                         interrupt-parent = <&tzic>;
 251                                         interrupts = <36>;
 252                                         status = "disabled";
 253                                 };
 254
 255                                 /* 50014000 0x4000 SSI2 irq30 */
 256                                 SSI2: ssi@50014000 {
 257                                         compatible = "fsl,imx53-ssi";
 258                                         reg = <0x50014000 0x4000>;
 259                                         interrupt-parent = <&tzic>;
 260                                         interrupts = <30>;
 261                                         status = "disabled";
 262                                 };
 263
 264                                 /* 50020000 0x4000 ESDHC 3 */
 265                                 esdhc@50020000 {
 266                                         compatible = "fsl,imx53-esdhc";
 267                                         reg = <0x50020000 0x4000>;
 268                                         interrupt-parent = <&tzic>;
 269                                         interrupts = <3>;
 270                                         status = "disabled";
 271                                 };
 272
 273                                 /* 50024000 0x4000 ESDHC 4 */
 274                                 esdhc@50024000 {
 275                                         compatible = "fsl,imx53-esdhc";
 276                                         reg = <0x50024000 0x4000>;
 277                                         interrupt-parent = <&tzic>;
 278                                         interrupts = <4>;
 279                                         status = "disabled";
 280                                 };
 281
 282                                 /* 50028000 0x4000 SPDIF */
 283                                 /* 91 SPDIF */
 284
 285                                 /* 50030000 0x4000 PATA (PORT UDMA) irq70 */
 286
 287                                 /* 50034000 0x4000 SLM */
 288                                 /* 50038000 0x4000 HSI2C */
 289                                 /* 64 HS-I2C */
 290                                 /* 5003C000 0x4000 SPBA */
 291                         };
 292
 293                         /* 73F80000 0x4000 USBOH3 */
 294                         /* irq14 USBOH3 USB Host 1 */
 295                         /* irq16 USBOH3 USB Host 2 */
 296                         /* irq17 USBOH3 USB Host 3 */
 297                         /* irq18 USBOH3 USB OTG */
 298                         usb1: usb@53F80000 {
 299                                 compatible = "fsl,usb-4core";
 300                                 reg = <0x53f80000 0x4000>;
 301                                 interrupt-parent = <&tzic>;
 302                                 interrupts = <18 14 16 17>;
 303                         };
 304
 305                         /* 53F98000 0x4000 WDOG1 */
 306                         wdog@53f98000 {
 307                                 compatible = "fsl,imx53-wdt";
 308                                 reg = <0x53f98000 0x4000>;
 309                                 interrupt-parent = <&tzic>;
 310                                 interrupts = <58>;
 311                                 status = "disabled";
 312                         };
 313
 314                         /* 53F9C000 0x4000 WDOG2 (TZ) */
 315                         wdog@53f9c000 {
 316                                 compatible = "fsl,imx53-wdt";
 317                                 reg = <0x53f9c000 0x4000>;
 318                                 interrupt-parent = <&tzic>;
 319                                 interrupts = <59>;
 320                                 status = "disabled";
 321                         };
 322
 323                         /* 53F94000 0x4000 KPP */
 324                         keyboard@53f94000 {
 325                                 compatible = "fsl,imx53-kpp";
 326                                 reg = <0x53f94000 0x4000>;
 327                                 interrupt-parent = <&tzic>;
 328                                 interrupts = <60>;
 329                                 status = "disabled";
 330                         };
 331
 332                         /* 53FA0000 0x4000 GPT */
 333                         timer@53fa0000 {
 334                                 compatible = "fsl,imx53-gpt";
 335                                 reg = <0x53fa0000 0x4000>;
 336                                 interrupt-parent = <&tzic>;
 337                                 interrupts = <39>;
 338                                 status = "disabled";
 339                         };
 340
 341                         /* 53FA4000 0x4000 SRTC */
 342
 343                         rtc@53fa4000 {
 344                                 compatible = "fsl,imx53-srtc";
 345                                 reg = <0x53fa4000 0x4000>;
 346                                 interrupt-parent = <&tzic>;
 347                                 interrupts = <24 25>;
 348                                 status = "disabled";
 349                         };
 350
 351                         /* 53FA8000 0x4000 IOMUXC */
 352                         iomux@53fa8000 {
 353                                 compatible = "fsl,imx53-iomux";
 354                                 reg = <0x53fa8000 0x4000>;
 355                                 interrupt-parent = <&tzic>;
 356                                 interrupts = <7>;
 357                         };
 358
 359                         /* 53FAC000 0x4000 EPIT1 */
 360                         epit1: timer@53fac000 {
 361                                 compatible = "fsl,imx53-epit";
 362                                 reg = <0x53fac000 0x4000>;
 363                                 interrupt-parent = <&tzic>;
 364                                 interrupts = <40>;
 365                                 status = "disabled";
 366                         };
 367
 368                         /* 53FB0000 0x4000 EPIT2 */
 369                         epit2: timer@53fb0000 {
 370                                 compatible = "fsl,imx53-epit";
 371                                 reg = <0x53fb0000 0x4000>;
 372                                 interrupt-parent = <&tzic>;
 373                                 interrupts = <41>;
 374                                 status = "disabled";
 375                         };
 376
 377                         /* 53FB4000 0x4000 PWM1 */
 378                         pwm@53fb4000 {
 379                                 compatible = "fsl,imx53-pwm";
 380                                 reg = <0x53fb4000 0x4000>;
 381                                 interrupt-parent = <&tzic>;
 382                                 interrupts = <61>;
 383                                 status = "disabled";
 384                         };
 385
 386                         /* 53FB8000 0x4000 PWM2 */
 387                         pwm@53fb8000 {
 388                                 compatible = "fsl,imx53-pwm";
 389                                 reg = <0x53fb8000 0x4000>;
 390                                 interrupt-parent = <&tzic>;
 391                                 interrupts = <94>;
 392                                 status = "disabled";
 393                         };
 394
 395                         /* 53FBC000 0x4000 UART 1 */
 396                         uart1: serial@53fbc000 {
 397                                 compatible = "fsl,imx53-uart", "fsl,imx-uart";
 398                                 reg = <0x53fbc000 0x4000>;
 399                                 interrupt-parent = <&tzic>;
 400                                 interrupts = <31>;
 401                                 status = "disabled";
 402                         };
 403
 404                         /* 53FC0000 0x4000 UART 2 */
 405                         uart2: serial@53fc0000 {
 406                                 compatible = "fsl,imx53-uart", "fsl,imx-uart";
 407                                 reg = <0x53fc0000 0x4000>;
 408                                 interrupt-parent = <&tzic>;
 409                                 interrupts = <32>;
 410                                 status = "disabled";
 411                         };
 412
 413                         /* 53FC0000 0x4000 UART 4 */
 414                         uart4: serial@53ff0000 {
 415                                 compatible = "fsl,imx53-uart", "fsl,imx-uart";
 416                                 reg = <0x53ff0000 0x4000>;
 417                                 interrupt-parent = <&tzic>;
 418                                 interrupts = <13>;
 419                                 status = "disabled";
 420                         };
 421
 422
 423
 424                         /* 53FC4000 0x4000 USBOH3 */
 425                         /* NOTYET
 426                         usb@53fc4000 {
 427                                 compatible = "fsl,imx53-otg";
 428                                 reg = <0x53fc4000 0x4000>;
 429                                 interrupt-parent = <&tzic>;
 430                                 interrupts = <>;
 431                                 status = "disabled";
 432                         };
 433                         */
 434                         /* 53FD0000 0x4000 SRC */
 435                         reset@53fd0000 {
 436                                 compatible = "fsl,imx53-src";
 437                                 reg = <0x53fd0000 0x4000>;
 438                                 interrupt-parent = <&tzic>;
 439                                 interrupts = <75>;
 440                                 status = "disabled";
 441                         };
 442                         /* 53FD8000 0x4000 GPC */
 443                         power@53fd8000 {
 444                                 compatible = "fsl,imx53-gpc";
 445                                 reg = <0x53fd8000 0x4000>;
 446                                 interrupt-parent = <&tzic>;
 447                                 interrupts = <73 74>;
 448                                 status = "disabled";
 449                         };
 450
 451                         /* 53FE8000 0x4000 PATA (PORT PIO) */
 452                         /* 70 PATA Parallel ATA host controller interrupt */
 453                         ide@53fe8000 {
 454                                 compatible = "fsl,imx53-ata";
 455                                 reg = <0x83fe0000 0x4000>;
 456                                 interrupt-parent = <&tzic>;
 457                                 interrupts = <70>;
 458                                 status = "disabled";
 459                         };
 460
 461                 };
 462
 463                 aips@60000000 { /* AIPS2 */
 464                         compatible = "fsl,aips-bus", "simple-bus";
 465                         #address-cells = <1>;
 466                         #size-cells = <1>;
 467                         interrupt-parent = <&tzic>;
 468                         ranges;
 469
 470                         /* 53FC0000 0x4000 UART 5 */
 471                         uart5: serial@63f90000 {
 472                                 compatible = "fsl,imx53-uart", "fsl,imx-uart";
 473                                 reg = <0x63f90000 0x4000>;
 474                                 interrupt-parent = <&tzic>;
 475                                 interrupts = <32>;
 476                                 status = "disabled";
 477                         };
 478
 479                         /* 63F94000 0x4000 AHBMAX */
 480                         /* 63F98000 0x4000 IIM */
 481                             /*
 482                              * 69 IIM Interrupt request to the processor.
 483                              * Indicates to the processor that program or
 484                              * explicit.
 485                              */
 486                         /* 63F9C000 0x4000 CSU */
 487                             /*
 488                              * 27 CSU Interrupt Request 1. Indicates to the
 489                              * processor that one or more alarm inputs were.
 490                              */
 491
 492                         /* 63FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
 493                         /* irq76 Neon Monitor Interrupt */
 494                         /* irq77 Performance Unit Interrupt */
 495                         /* irq78 CTI IRQ */
 496                         /* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
 497                         /* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
 498                         /* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
 499                         /* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
 500
 501                         /* 63FA4000 0x4000 OWIRE irq88 */
 502                         /* 63FA8000 0x4000 FIRI irq93 */
 503                         /* 63FAC000 0x4000 eCSPI2 */
 504                         ecspi@63fac000 {
 505                                 #address-cells = <1>;
 506                                 #size-cells = <0>;
 507                                 compatible = "fsl,imx53-ecspi";
 508                                 reg = <0x63fac000 0x4000>;
 509                                 interrupt-parent = <&tzic>;
 510                                 interrupts = <37>;
 511                                 status = "disabled";
 512                         };
 513
 514                         /* 63FB0000 0x4000 SDMA */
 515                         sdma@63fb0000 {
 516                                 compatible = "fsl,imx53-sdma";
 517                                 reg = <0x63fb0000 0x4000>;
 518                                 interrupt-parent = <&tzic>;
 519                                 interrupts = <6>;
 520                         };
 521
 522                         /* 63FB4000 0x4000 SCC */
 523                         /* 21 SCC Security Monitor High Priority Interrupt. */
 524                         /* 22 SCC Secure (TrustZone) Interrupt. */
 525                         /* 23 SCC Regular (Non-Secure) Interrupt. */
 526
 527                         /* 63FB8000 0x4000 ROMCP */
 528                         /* 63FBC000 0x4000 RTIC */
 529                         /*
 530                          * 26 RTIC RTIC (Trust Zone) Interrupt Request.
 531                          * Indicates that the RTIC has completed hashing the
 532                          */
 533
 534                         /* 63FC0000 0x4000 CSPI */
 535                         cspi@63fc0000 {
 536                                 #address-cells = <1>;
 537                                 #size-cells = <0>;
 538                                 compatible = "fsl,imx53-cspi";
 539                                 reg = <0x63fc0000 0x4000>;
 540                                 interrupt-parent = <&tzic>;
 541                                 interrupts = <38>;
 542                                 status = "disabled";
 543                         };
 544
 545                         /* 63FC4000 0x4000 I2C2 */
 546                         i2c@63fc4000 {
 547                                 #address-cells = <1>;
 548                                 #size-cells = <0>;
 549                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
 550                                 reg = <0x63fc4000 0x4000>;
 551                                 interrupt-parent = <&tzic>;
 552                                 interrupts = <63>;
 553                                 status = "disabled";
 554                         };
 555
 556                         /* 63FC8000 0x4000 I2C1 */
 557                         i2c@63fc8000 {
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
 561                                 reg = <0x63fc8000 0x4000>;
 562                                 interrupt-parent = <&tzic>;
 563                                 interrupts = <62>;
 564                                 status = "disabled";
 565                         };
 566
 567                         /* 63FCC000 0x4000 SSI1 */
 568                         /* 29 SSI1 SSI-1 Interrupt Request */
 569                         SSI1: ssi@63fcc000 {
 570                                 compatible = "fsl,imx53-ssi";
 571                                 reg = <0x63fcc000 0x4000>;
 572                                 interrupt-parent = <&tzic>;
 573                                 interrupts = <29>;
 574                                 status = "disabled";
 575                         };
 576
 577                         /* 63FD0000 0x4000 AUDMUX */
 578                         audmux@63fd4000 {
 579                                 compatible = "fsl,imx53-audmux";
 580                                 reg = <0x63fd4000 0x4000>;
 581                                 status = "disabled";
 582                         };
 583
 584                         /* 63FD8000 0x4000 EXTMC */
 585                         /* 8 EXTMC (NFC) */
 586                         /* 15 EXTMC */
 587                         /* 97 EXTMC Boot sequence completed interrupt */
 588                         /*
 589                          * 101 EMI Indicates all pages have been transferred
 590                          * to NFC during an auto program operation.
 591                          */
 592
 593                         /* 83FE4000 0x4000 SIM */
 594                         /* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
 595                         /* 68 SIM intr composed of tc, etc, tfe, and rdrf */
 596
 597                         /* 63FD_C000 0x4000 apb2ip_pl301_2x2 */
 598                         /* 63FE_0000 0x4000 apb2ip_pl301_4x1 */
 599                         /* 63FE4000 0x4000 MLB */
 600                         /* 63FE8000 0x4000 SSI3 */
 601                         /* 96 SSI3 SSI-3 Interrupt Request */
 602                         SSI3: ssi@63fe8000 {
 603                                 compatible = "fsl,imx51-ssi";
 604                                 reg = <0x63fe8000 0x4000>;
 605                                 interrupt-parent = <&tzic>;
 606                                 interrupts = <96>;
 607                                 status = "disabled";
 608                         };
 609
 610                         /* 63FEC000 0x4000 FEC */
 611                         ethernet@63fec000 {
 612                                 compatible = "fsl,imx53-fec";
 613                                 reg = <0x63fec000 0x4000>;
 614                                 interrupt-parent = <&tzic>;
 615                                 interrupts = <87>;
 616                                 status = "disabled";
 617                         };
 618
 619                         /* 63FF0000 0x4000 TVE */
 620                         /* 92 TVE */
 621                         /* 63FF4000 0x4000 VPU */
 622                         /* 9 VPU */
 623                         /* 100 VPU Idle interrupt from VPU */
 624
 625                         /* 63FF8000 0x4000 SAHARA */
 626                         /* 19 SAHARA SAHARA host 0 (TrustZone) Intr */
 627                         /* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr */
 628                 };
 629         };
 630
 631         localbus@18000000 {
 632                 compatible = "simple-bus";
 633                 #address-cells = <1>;
 634                 #size-cells = <1>;
 635
 636                 ranges;
 637
 638                 vga: ipu3@18000000 {
 639                         compatible = "fsl,ipu3";
 640                         reg = <
 641                                 0x18000000 0x08000      /* CM */
 642                                 0x18008000 0x08000      /* IDMAC */
 643                                 0x18018000 0x08000      /* DP */
 644                                 0x18020000 0x08000      /* IC */
 645                                 0x18028000 0x08000      /* IRT */
 646                                 0x18030000 0x08000      /* CSI0 */
 647                                 0x18038000 0x08000      /* CSI1 */
 648                                 0x18040000 0x08000      /* DI0 */
 649                                 0x18048000 0x08000      /* DI1 */
 650                                 0x18050000 0x08000      /* SMFC */
 651                                 0x18058000 0x08000      /* DC */
 652                                 0x18060000 0x08000      /* DMFC */
 653                                 0x18068000 0x08000      /* VDI */
 654                                 0x19000000 0x20000      /* CPMEM */
 655                                 0x19020000 0x20000      /* LUT */
 656                                 0x19040000 0x20000      /* SRM */
 657                                 0x19060000 0x20000      /* TPM */
 658                                 0x19080000 0x20000      /* DCTMPL */
 659                         >;
 660                         interrupt-parent = <&tzic>;
 661                         interrupts = <
 662                                 10      /* IPUEX Error */
 663                                 11      /* IPUEX Sync */
 664                         >;
 665                         status = "disabled";
 666                 };
 667         };
 668 };
 669
 670 /*
 671
 672 TODO: Not mapped interrupts
 673
 674 5       DAP
 675 84      GPU2D (OpenVG) general interrupt
 676 85      GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
 677 12      GPU3D
 678 102     GPU3D Idle interrupt from GPU3D (for S/W power gating)
 679 90      SJC
 680 */