2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <dev/drm2/drmP.h>
37 #include <dev/drm2/drm.h>
38 #include <dev/drm2/i915/i915_drm.h>
39 #include <dev/drm2/i915/i915_drv.h>
40 #include <dev/drm2/i915/intel_drv.h>
41 #include <dev/drm2/drm_fourcc.h>
44 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
45 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
46 unsigned int crtc_w, unsigned int crtc_h,
47 uint32_t x, uint32_t y,
48 uint32_t src_w, uint32_t src_h)
50 struct drm_device *dev = plane->dev;
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 struct intel_plane *intel_plane = to_intel_plane(plane);
53 int pipe = intel_plane->pipe;
54 u32 sprctl, sprscale = 0;
57 sprctl = I915_READ(SPRCTL(pipe));
59 /* Mask out pixel format bits in case we change it */
60 sprctl &= ~SPRITE_PIXFORMAT_MASK;
61 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
62 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
64 switch (fb->pixel_format) {
65 case DRM_FORMAT_XBGR8888:
66 sprctl |= SPRITE_FORMAT_RGBX888;
69 case DRM_FORMAT_XRGB8888:
70 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
74 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
78 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
82 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
86 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
90 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
91 sprctl |= DVS_FORMAT_RGBX888;
96 if (obj->tiling_mode != I915_TILING_NONE)
97 sprctl |= SPRITE_TILED;
100 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
101 sprctl |= SPRITE_ENABLE;
103 /* Sizes are 0 based */
109 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
112 * IVB workaround: must disable low power watermarks for at least
113 * one frame before enabling scaling. LP watermarks can be re-enabled
114 * when scaling is disabled.
116 if (crtc_w != src_w || crtc_h != src_h) {
117 dev_priv->sprite_scaling_enabled = true;
118 sandybridge_update_wm(dev);
119 intel_wait_for_vblank(dev, pipe);
120 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
122 dev_priv->sprite_scaling_enabled = false;
123 /* potentially re-enable LP watermarks */
124 sandybridge_update_wm(dev);
127 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
128 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
129 if (obj->tiling_mode != I915_TILING_NONE) {
130 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
132 unsigned long offset;
134 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
135 I915_WRITE(SPRLINOFF(pipe), offset);
137 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
138 I915_WRITE(SPRSCALE(pipe), sprscale);
139 I915_WRITE(SPRCTL(pipe), sprctl);
140 I915_WRITE(SPRSURF(pipe), obj->gtt_offset);
141 POSTING_READ(SPRSURF(pipe));
145 ivb_disable_plane(struct drm_plane *plane)
147 struct drm_device *dev = plane->dev;
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 struct intel_plane *intel_plane = to_intel_plane(plane);
150 int pipe = intel_plane->pipe;
152 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
153 /* Can't leave the scaler enabled... */
154 I915_WRITE(SPRSCALE(pipe), 0);
155 /* Activate double buffered register update */
156 I915_WRITE(SPRSURF(pipe), 0);
157 POSTING_READ(SPRSURF(pipe));
161 ivb_update_colorkey(struct drm_plane *plane,
162 struct drm_intel_sprite_colorkey *key)
164 struct drm_device *dev = plane->dev;
165 struct drm_i915_private *dev_priv = dev->dev_private;
166 struct intel_plane *intel_plane;
170 intel_plane = to_intel_plane(plane);
172 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
173 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
174 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
176 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
177 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
178 if (key->flags & I915_SET_COLORKEY_DESTINATION)
179 sprctl |= SPRITE_DEST_KEY;
180 else if (key->flags & I915_SET_COLORKEY_SOURCE)
181 sprctl |= SPRITE_SOURCE_KEY;
182 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
184 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
190 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
192 struct drm_device *dev = plane->dev;
193 struct drm_i915_private *dev_priv = dev->dev_private;
194 struct intel_plane *intel_plane;
197 intel_plane = to_intel_plane(plane);
199 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
200 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
201 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
204 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
206 if (sprctl & SPRITE_DEST_KEY)
207 key->flags = I915_SET_COLORKEY_DESTINATION;
208 else if (sprctl & SPRITE_SOURCE_KEY)
209 key->flags = I915_SET_COLORKEY_SOURCE;
211 key->flags = I915_SET_COLORKEY_NONE;
215 snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
216 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
217 unsigned int crtc_w, unsigned int crtc_h,
218 uint32_t x, uint32_t y,
219 uint32_t src_w, uint32_t src_h)
221 struct drm_device *dev = plane->dev;
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 struct intel_plane *intel_plane = to_intel_plane(plane);
224 int pipe = intel_plane->pipe, pixel_size;
225 u32 dvscntr, dvsscale = 0;
227 dvscntr = I915_READ(DVSCNTR(pipe));
229 /* Mask out pixel format bits in case we change it */
230 dvscntr &= ~DVS_PIXFORMAT_MASK;
231 dvscntr &= ~DVS_RGB_ORDER_XBGR;
232 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
234 switch (fb->pixel_format) {
235 case DRM_FORMAT_XBGR8888:
236 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
239 case DRM_FORMAT_XRGB8888:
240 dvscntr |= DVS_FORMAT_RGBX888;
243 case DRM_FORMAT_YUYV:
244 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
247 case DRM_FORMAT_YVYU:
248 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
251 case DRM_FORMAT_UYVY:
252 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
255 case DRM_FORMAT_VYUY:
256 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
260 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
261 dvscntr |= DVS_FORMAT_RGBX888;
266 if (obj->tiling_mode != I915_TILING_NONE)
267 dvscntr |= DVS_TILED;
270 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
271 dvscntr |= DVS_ENABLE;
273 /* Sizes are 0 based */
279 intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
281 if (crtc_w != src_w || crtc_h != src_h)
282 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
284 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
285 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
286 if (obj->tiling_mode != I915_TILING_NONE) {
287 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
289 unsigned long offset;
291 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
292 I915_WRITE(DVSLINOFF(pipe), offset);
294 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
295 I915_WRITE(DVSSCALE(pipe), dvsscale);
296 I915_WRITE(DVSCNTR(pipe), dvscntr);
297 I915_WRITE(DVSSURF(pipe), obj->gtt_offset);
298 POSTING_READ(DVSSURF(pipe));
302 snb_disable_plane(struct drm_plane *plane)
304 struct drm_device *dev = plane->dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 struct intel_plane *intel_plane = to_intel_plane(plane);
307 int pipe = intel_plane->pipe;
309 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
310 /* Disable the scaler */
311 I915_WRITE(DVSSCALE(pipe), 0);
312 /* Flush double buffered register updates */
313 I915_WRITE(DVSSURF(pipe), 0);
314 POSTING_READ(DVSSURF(pipe));
318 intel_enable_primary(struct drm_crtc *crtc)
320 struct drm_device *dev = crtc->dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
323 int reg = DSPCNTR(intel_crtc->plane);
325 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
329 intel_disable_primary(struct drm_crtc *crtc)
331 struct drm_device *dev = crtc->dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
334 int reg = DSPCNTR(intel_crtc->plane);
336 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
340 snb_update_colorkey(struct drm_plane *plane,
341 struct drm_intel_sprite_colorkey *key)
343 struct drm_device *dev = plane->dev;
344 struct drm_i915_private *dev_priv = dev->dev_private;
345 struct intel_plane *intel_plane;
349 intel_plane = to_intel_plane(plane);
351 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
352 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
353 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
355 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
356 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
357 if (key->flags & I915_SET_COLORKEY_DESTINATION)
358 dvscntr |= DVS_DEST_KEY;
359 else if (key->flags & I915_SET_COLORKEY_SOURCE)
360 dvscntr |= DVS_SOURCE_KEY;
361 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
363 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
369 snb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
371 struct drm_device *dev = plane->dev;
372 struct drm_i915_private *dev_priv = dev->dev_private;
373 struct intel_plane *intel_plane;
376 intel_plane = to_intel_plane(plane);
378 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
379 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
380 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
383 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
385 if (dvscntr & DVS_DEST_KEY)
386 key->flags = I915_SET_COLORKEY_DESTINATION;
387 else if (dvscntr & DVS_SOURCE_KEY)
388 key->flags = I915_SET_COLORKEY_SOURCE;
390 key->flags = I915_SET_COLORKEY_NONE;
394 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
395 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
396 unsigned int crtc_w, unsigned int crtc_h,
397 uint32_t src_x, uint32_t src_y,
398 uint32_t src_w, uint32_t src_h)
400 struct drm_device *dev = plane->dev;
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
403 struct intel_plane *intel_plane = to_intel_plane(plane);
404 struct intel_framebuffer *intel_fb;
405 struct drm_i915_gem_object *obj, *old_obj;
406 int pipe = intel_plane->pipe;
408 int x = src_x >> 16, y = src_y >> 16;
409 int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
410 bool disable_primary = false;
412 intel_fb = to_intel_framebuffer(fb);
415 old_obj = intel_plane->obj;
420 /* Pipe must be running... */
421 if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
424 if (crtc_x >= primary_w || crtc_y >= primary_h)
427 /* Don't modify another pipe's plane */
428 if (intel_plane->pipe != intel_crtc->pipe)
432 * Clamp the width & height into the visible area. Note we don't
433 * try to scale the source if part of the visible region is offscreen.
434 * The caller must handle that by adjusting source offset and size.
436 if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
440 if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
442 if ((crtc_x + crtc_w) > primary_w)
443 crtc_w = primary_w - crtc_x;
445 if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
449 if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
451 if (crtc_y + crtc_h > primary_h)
452 crtc_h = primary_h - crtc_y;
454 if (!crtc_w || !crtc_h) /* Again, nothing to display */
458 * We can take a larger source and scale it down, but
459 * only so much... 16x is the max on SNB.
461 if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
465 * If the sprite is completely covering the primary plane,
466 * we can disable the primary and save power.
468 if ((crtc_x == 0) && (crtc_y == 0) &&
469 (crtc_w == primary_w) && (crtc_h == primary_h))
470 disable_primary = true;
474 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
478 intel_plane->obj = obj;
481 * Be sure to re-enable the primary before the sprite is no longer
484 if (!disable_primary && intel_plane->primary_disabled) {
485 intel_enable_primary(crtc);
486 intel_plane->primary_disabled = false;
489 intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
490 crtc_w, crtc_h, x, y, src_w, src_h);
492 if (disable_primary) {
493 intel_disable_primary(crtc);
494 intel_plane->primary_disabled = true;
497 /* Unpin old obj after new one is active to avoid ugliness */
500 * It's fairly common to simply update the position of
501 * an existing object. In that case, we don't need to
502 * wait for vblank to avoid ugliness, we only need to
503 * do the pin & ref bookkeeping.
505 if (old_obj != obj) {
507 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
510 intel_unpin_fb_obj(old_obj);
520 intel_disable_plane(struct drm_plane *plane)
522 struct drm_device *dev = plane->dev;
523 struct intel_plane *intel_plane = to_intel_plane(plane);
526 if (intel_plane->primary_disabled) {
527 intel_enable_primary(plane->crtc);
528 intel_plane->primary_disabled = false;
531 intel_plane->disable_plane(plane);
533 if (!intel_plane->obj)
537 intel_unpin_fb_obj(intel_plane->obj);
538 intel_plane->obj = NULL;
545 static void intel_destroy_plane(struct drm_plane *plane)
547 struct intel_plane *intel_plane = to_intel_plane(plane);
548 intel_disable_plane(plane);
549 drm_plane_cleanup(plane);
550 free(intel_plane, DRM_MEM_KMS);
553 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
554 struct drm_file *file_priv)
556 struct drm_intel_sprite_colorkey *set = data;
557 struct drm_i915_private *dev_priv = dev->dev_private;
558 struct drm_mode_object *obj;
559 struct drm_plane *plane;
560 struct intel_plane *intel_plane;
566 /* Make sure we don't try to enable both src & dest simultaneously */
567 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
570 sx_xlock(&dev->mode_config.mutex);
572 obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
578 plane = obj_to_plane(obj);
579 intel_plane = to_intel_plane(plane);
580 ret = intel_plane->update_colorkey(plane, set);
583 sx_xunlock(&dev->mode_config.mutex);
587 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
588 struct drm_file *file_priv)
590 struct drm_intel_sprite_colorkey *get = data;
591 struct drm_i915_private *dev_priv = dev->dev_private;
592 struct drm_mode_object *obj;
593 struct drm_plane *plane;
594 struct intel_plane *intel_plane;
600 sx_xlock(&dev->mode_config.mutex);
602 obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
608 plane = obj_to_plane(obj);
609 intel_plane = to_intel_plane(plane);
610 intel_plane->get_colorkey(plane, get);
613 sx_xunlock(&dev->mode_config.mutex);
617 static const struct drm_plane_funcs intel_plane_funcs = {
618 .update_plane = intel_update_plane,
619 .disable_plane = intel_disable_plane,
620 .destroy = intel_destroy_plane,
623 static uint32_t snb_plane_formats[] = {
633 intel_plane_init(struct drm_device *dev, enum pipe pipe)
635 struct intel_plane *intel_plane;
636 unsigned long possible_crtcs;
639 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
642 intel_plane = malloc(sizeof(struct intel_plane), DRM_MEM_KMS,
646 intel_plane->max_downscale = 16;
647 intel_plane->update_plane = snb_update_plane;
648 intel_plane->disable_plane = snb_disable_plane;
649 intel_plane->update_colorkey = snb_update_colorkey;
650 intel_plane->get_colorkey = snb_get_colorkey;
651 } else if (IS_GEN7(dev)) {
652 intel_plane->max_downscale = 2;
653 intel_plane->update_plane = ivb_update_plane;
654 intel_plane->disable_plane = ivb_disable_plane;
655 intel_plane->update_colorkey = ivb_update_colorkey;
656 intel_plane->get_colorkey = ivb_get_colorkey;
659 intel_plane->pipe = pipe;
660 possible_crtcs = (1 << pipe);
661 ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
662 &intel_plane_funcs, snb_plane_formats,
663 DRM_ARRAY_SIZE(snb_plane_formats), false);
665 free(intel_plane, DRM_MEM_KMS);