sys/dev/drm2/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include <dev/drm2/drmP.h>
  37 #include <dev/drm2/drm.h>
  38 #include <dev/drm2/i915/i915_drm.h>
  39 #include <dev/drm2/i915/i915_drv.h>
  40 #include <dev/drm2/i915/intel_drv.h>
  41 #include <dev/drm2/drm_fourcc.h>
  42
  43 static void
  44 ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
  45                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
  46                  unsigned int crtc_w, unsigned int crtc_h,
  47                  uint32_t x, uint32_t y,
  48                  uint32_t src_w, uint32_t src_h)
  49 {
  50         struct drm_device *dev = plane->dev;
  51         struct drm_i915_private *dev_priv = dev->dev_private;
  52         struct intel_plane *intel_plane = to_intel_plane(plane);
  53         int pipe = intel_plane->pipe;
  54         u32 sprctl, sprscale = 0;
  55         int pixel_size;
  56
  57         sprctl = I915_READ(SPRCTL(pipe));
  58
  59         /* Mask out pixel format bits in case we change it */
  60         sprctl &= ~SPRITE_PIXFORMAT_MASK;
  61         sprctl &= ~SPRITE_RGB_ORDER_RGBX;
  62         sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
  63
  64         switch (fb->pixel_format) {
  65         case DRM_FORMAT_XBGR8888:
  66                 sprctl |= SPRITE_FORMAT_RGBX888;
  67                 pixel_size = 4;
  68                 break;
  69         case DRM_FORMAT_XRGB8888:
  70                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
  71                 pixel_size = 4;
  72                 break;
  73         case DRM_FORMAT_YUYV:
  74                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
  75                 pixel_size = 2;
  76                 break;
  77         case DRM_FORMAT_YVYU:
  78                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
  79                 pixel_size = 2;
  80                 break;
  81         case DRM_FORMAT_UYVY:
  82                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
  83                 pixel_size = 2;
  84                 break;
  85         case DRM_FORMAT_VYUY:
  86                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
  87                 pixel_size = 2;
  88                 break;
  89         default:
  90                 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
  91                 sprctl |= DVS_FORMAT_RGBX888;
  92                 pixel_size = 4;
  93                 break;
  94         }
  95
  96         if (obj->tiling_mode != I915_TILING_NONE)
  97                 sprctl |= SPRITE_TILED;
  98
  99         /* must disable */
 100         sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 101         sprctl |= SPRITE_ENABLE;
 102
 103         /* Sizes are 0 based */
 104         src_w--;
 105         src_h--;
 106         crtc_w--;
 107         crtc_h--;
 108
 109         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 110
 111         /*
 112          * IVB workaround: must disable low power watermarks for at least
 113          * one frame before enabling scaling.  LP watermarks can be re-enabled
 114          * when scaling is disabled.
 115          */
 116         if (crtc_w != src_w || crtc_h != src_h) {
 117                 dev_priv->sprite_scaling_enabled = true;
 118                 sandybridge_update_wm(dev);
 119                 intel_wait_for_vblank(dev, pipe);
 120                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 121         } else {
 122                 dev_priv->sprite_scaling_enabled = false;
 123                 /* potentially re-enable LP watermarks */
 124                 sandybridge_update_wm(dev);
 125         }
 126
 127         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 128         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 129         if (obj->tiling_mode != I915_TILING_NONE) {
 130                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 131         } else {
 132                 unsigned long offset;
 133
 134                 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 135                 I915_WRITE(SPRLINOFF(pipe), offset);
 136         }
 137         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 138         I915_WRITE(SPRSCALE(pipe), sprscale);
 139         I915_WRITE(SPRCTL(pipe), sprctl);
 140         I915_WRITE(SPRSURF(pipe), obj->gtt_offset);
 141         POSTING_READ(SPRSURF(pipe));
 142 }
 143
 144 static void
 145 ivb_disable_plane(struct drm_plane *plane)
 146 {
 147         struct drm_device *dev = plane->dev;
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         struct intel_plane *intel_plane = to_intel_plane(plane);
 150         int pipe = intel_plane->pipe;
 151
 152         I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
 153         /* Can't leave the scaler enabled... */
 154         I915_WRITE(SPRSCALE(pipe), 0);
 155         /* Activate double buffered register update */
 156         I915_WRITE(SPRSURF(pipe), 0);
 157         POSTING_READ(SPRSURF(pipe));
 158 }
 159
 160 static int
 161 ivb_update_colorkey(struct drm_plane *plane,
 162                     struct drm_intel_sprite_colorkey *key)
 163 {
 164         struct drm_device *dev = plane->dev;
 165         struct drm_i915_private *dev_priv = dev->dev_private;
 166         struct intel_plane *intel_plane;
 167         u32 sprctl;
 168         int ret = 0;
 169
 170         intel_plane = to_intel_plane(plane);
 171
 172         I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
 173         I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
 174         I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
 175
 176         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 177         sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
 178         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 179                 sprctl |= SPRITE_DEST_KEY;
 180         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 181                 sprctl |= SPRITE_SOURCE_KEY;
 182         I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
 183
 184         POSTING_READ(SPRKEYMSK(intel_plane->pipe));
 185
 186         return ret;
 187 }
 188
 189 static void
 190 ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 191 {
 192         struct drm_device *dev = plane->dev;
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         struct intel_plane *intel_plane;
 195         u32 sprctl;
 196
 197         intel_plane = to_intel_plane(plane);
 198
 199         key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
 200         key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
 201         key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
 202         key->flags = 0;
 203
 204         sprctl = I915_READ(SPRCTL(intel_plane->pipe));
 205
 206         if (sprctl & SPRITE_DEST_KEY)
 207                 key->flags = I915_SET_COLORKEY_DESTINATION;
 208         else if (sprctl & SPRITE_SOURCE_KEY)
 209                 key->flags = I915_SET_COLORKEY_SOURCE;
 210         else
 211                 key->flags = I915_SET_COLORKEY_NONE;
 212 }
 213
 214 static void
 215 snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
 216                  struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
 217                  unsigned int crtc_w, unsigned int crtc_h,
 218                  uint32_t x, uint32_t y,
 219                  uint32_t src_w, uint32_t src_h)
 220 {
 221         struct drm_device *dev = plane->dev;
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         struct intel_plane *intel_plane = to_intel_plane(plane);
 224         int pipe = intel_plane->pipe, pixel_size;
 225         u32 dvscntr, dvsscale = 0;
 226
 227         dvscntr = I915_READ(DVSCNTR(pipe));
 228
 229         /* Mask out pixel format bits in case we change it */
 230         dvscntr &= ~DVS_PIXFORMAT_MASK;
 231         dvscntr &= ~DVS_RGB_ORDER_XBGR;
 232         dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
 233
 234         switch (fb->pixel_format) {
 235         case DRM_FORMAT_XBGR8888:
 236                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 237                 pixel_size = 4;
 238                 break;
 239         case DRM_FORMAT_XRGB8888:
 240                 dvscntr |= DVS_FORMAT_RGBX888;
 241                 pixel_size = 4;
 242                 break;
 243         case DRM_FORMAT_YUYV:
 244                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 245                 pixel_size = 2;
 246                 break;
 247         case DRM_FORMAT_YVYU:
 248                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 249                 pixel_size = 2;
 250                 break;
 251         case DRM_FORMAT_UYVY:
 252                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 253                 pixel_size = 2;
 254                 break;
 255         case DRM_FORMAT_VYUY:
 256                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 257                 pixel_size = 2;
 258                 break;
 259         default:
 260                 DRM_DEBUG_DRIVER("bad pixel format, assuming RGBX888\n");
 261                 dvscntr |= DVS_FORMAT_RGBX888;
 262                 pixel_size = 4;
 263                 break;
 264         }
 265
 266         if (obj->tiling_mode != I915_TILING_NONE)
 267                 dvscntr |= DVS_TILED;
 268
 269         /* must disable */
 270         dvscntr |= DVS_TRICKLE_FEED_DISABLE;
 271         dvscntr |= DVS_ENABLE;
 272
 273         /* Sizes are 0 based */
 274         src_w--;
 275         src_h--;
 276         crtc_w--;
 277         crtc_h--;
 278
 279         intel_update_sprite_watermarks(dev, pipe, crtc_w, pixel_size);
 280
 281         if (crtc_w != src_w || crtc_h != src_h)
 282                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 283
 284         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 285         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 286         if (obj->tiling_mode != I915_TILING_NONE) {
 287                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 288         } else {
 289                 unsigned long offset;
 290
 291                 offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
 292                 I915_WRITE(DVSLINOFF(pipe), offset);
 293         }
 294         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 295         I915_WRITE(DVSSCALE(pipe), dvsscale);
 296         I915_WRITE(DVSCNTR(pipe), dvscntr);
 297         I915_WRITE(DVSSURF(pipe), obj->gtt_offset);
 298         POSTING_READ(DVSSURF(pipe));
 299 }
 300
 301 static void
 302 snb_disable_plane(struct drm_plane *plane)
 303 {
 304         struct drm_device *dev = plane->dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         struct intel_plane *intel_plane = to_intel_plane(plane);
 307         int pipe = intel_plane->pipe;
 308
 309         I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
 310         /* Disable the scaler */
 311         I915_WRITE(DVSSCALE(pipe), 0);
 312         /* Flush double buffered register updates */
 313         I915_WRITE(DVSSURF(pipe), 0);
 314         POSTING_READ(DVSSURF(pipe));
 315 }
 316
 317 static void
 318 intel_enable_primary(struct drm_crtc *crtc)
 319 {
 320         struct drm_device *dev = crtc->dev;
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 323         int reg = DSPCNTR(intel_crtc->plane);
 324
 325         I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
 326 }
 327
 328 static void
 329 intel_disable_primary(struct drm_crtc *crtc)
 330 {
 331         struct drm_device *dev = crtc->dev;
 332         struct drm_i915_private *dev_priv = dev->dev_private;
 333         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 334         int reg = DSPCNTR(intel_crtc->plane);
 335
 336         I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
 337 }
 338
 339 static int
 340 snb_update_colorkey(struct drm_plane *plane,
 341                     struct drm_intel_sprite_colorkey *key)
 342 {
 343         struct drm_device *dev = plane->dev;
 344         struct drm_i915_private *dev_priv = dev->dev_private;
 345         struct intel_plane *intel_plane;
 346         u32 dvscntr;
 347         int ret = 0;
 348
 349         intel_plane = to_intel_plane(plane);
 350
 351         I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
 352         I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
 353         I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
 354
 355         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 356         dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
 357         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 358                 dvscntr |= DVS_DEST_KEY;
 359         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 360                 dvscntr |= DVS_SOURCE_KEY;
 361         I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
 362
 363         POSTING_READ(DVSKEYMSK(intel_plane->pipe));
 364
 365         return ret;
 366 }
 367
 368 static void
 369 snb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
 370 {
 371         struct drm_device *dev = plane->dev;
 372         struct drm_i915_private *dev_priv = dev->dev_private;
 373         struct intel_plane *intel_plane;
 374         u32 dvscntr;
 375
 376         intel_plane = to_intel_plane(plane);
 377
 378         key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
 379         key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
 380         key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
 381         key->flags = 0;
 382
 383         dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
 384
 385         if (dvscntr & DVS_DEST_KEY)
 386                 key->flags = I915_SET_COLORKEY_DESTINATION;
 387         else if (dvscntr & DVS_SOURCE_KEY)
 388                 key->flags = I915_SET_COLORKEY_SOURCE;
 389         else
 390                 key->flags = I915_SET_COLORKEY_NONE;
 391 }
 392
 393 static int
 394 intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 395                    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
 396                    unsigned int crtc_w, unsigned int crtc_h,
 397                    uint32_t src_x, uint32_t src_y,
 398                    uint32_t src_w, uint32_t src_h)
 399 {
 400         struct drm_device *dev = plane->dev;
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 403         struct intel_plane *intel_plane = to_intel_plane(plane);
 404         struct intel_framebuffer *intel_fb;
 405         struct drm_i915_gem_object *obj, *old_obj;
 406         int pipe = intel_plane->pipe;
 407         int ret = 0;
 408         int x = src_x >> 16, y = src_y >> 16;
 409         int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
 410         bool disable_primary = false;
 411
 412         intel_fb = to_intel_framebuffer(fb);
 413         obj = intel_fb->obj;
 414
 415         old_obj = intel_plane->obj;
 416
 417         src_w = src_w >> 16;
 418         src_h = src_h >> 16;
 419
 420         /* Pipe must be running... */
 421         if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE))
 422                 return -EINVAL;
 423
 424         if (crtc_x >= primary_w || crtc_y >= primary_h)
 425                 return -EINVAL;
 426
 427         /* Don't modify another pipe's plane */
 428         if (intel_plane->pipe != intel_crtc->pipe)
 429                 return -EINVAL;
 430
 431         /*
 432          * Clamp the width & height into the visible area.  Note we don't
 433          * try to scale the source if part of the visible region is offscreen.
 434          * The caller must handle that by adjusting source offset and size.
 435          */
 436         if ((crtc_x < 0) && ((crtc_x + crtc_w) > 0)) {
 437                 crtc_w += crtc_x;
 438                 crtc_x = 0;
 439         }
 440         if ((crtc_x + crtc_w) <= 0) /* Nothing to display */
 441                 goto out;
 442         if ((crtc_x + crtc_w) > primary_w)
 443                 crtc_w = primary_w - crtc_x;
 444
 445         if ((crtc_y < 0) && ((crtc_y + crtc_h) > 0)) {
 446                 crtc_h += crtc_y;
 447                 crtc_y = 0;
 448         }
 449         if ((crtc_y + crtc_h) <= 0) /* Nothing to display */
 450                 goto out;
 451         if (crtc_y + crtc_h > primary_h)
 452                 crtc_h = primary_h - crtc_y;
 453
 454         if (!crtc_w || !crtc_h) /* Again, nothing to display */
 455                 goto out;
 456
 457         /*
 458          * We can take a larger source and scale it down, but
 459          * only so much...  16x is the max on SNB.
 460          */
 461         if (((src_w * src_h) / (crtc_w * crtc_h)) > intel_plane->max_downscale)
 462                 return -EINVAL;
 463
 464         /*
 465          * If the sprite is completely covering the primary plane,
 466          * we can disable the primary and save power.
 467          */
 468         if ((crtc_x == 0) && (crtc_y == 0) &&
 469             (crtc_w == primary_w) && (crtc_h == primary_h))
 470                 disable_primary = true;
 471
 472         DRM_LOCK(dev);
 473
 474         ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
 475         if (ret)
 476                 goto out_unlock;
 477
 478         intel_plane->obj = obj;
 479
 480         /*
 481          * Be sure to re-enable the primary before the sprite is no longer
 482          * covering it fully.
 483          */
 484         if (!disable_primary && intel_plane->primary_disabled) {
 485                 intel_enable_primary(crtc);
 486                 intel_plane->primary_disabled = false;
 487         }
 488
 489         intel_plane->update_plane(plane, fb, obj, crtc_x, crtc_y,
 490                                   crtc_w, crtc_h, x, y, src_w, src_h);
 491
 492         if (disable_primary) {
 493                 intel_disable_primary(crtc);
 494                 intel_plane->primary_disabled = true;
 495         }
 496
 497         /* Unpin old obj after new one is active to avoid ugliness */
 498         if (old_obj) {
 499                 /*
 500                  * It's fairly common to simply update the position of
 501                  * an existing object.  In that case, we don't need to
 502                  * wait for vblank to avoid ugliness, we only need to
 503                  * do the pin & ref bookkeeping.
 504                  */
 505                 if (old_obj != obj) {
 506                         DRM_UNLOCK(dev);
 507                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
 508                         DRM_LOCK(dev);
 509                 }
 510                 intel_unpin_fb_obj(old_obj);
 511         }
 512
 513 out_unlock:
 514         DRM_UNLOCK(dev);
 515 out:
 516         return ret;
 517 }
 518
 519 static int
 520 intel_disable_plane(struct drm_plane *plane)
 521 {
 522         struct drm_device *dev = plane->dev;
 523         struct intel_plane *intel_plane = to_intel_plane(plane);
 524         int ret = 0;
 525
 526         if (intel_plane->primary_disabled) {
 527                 intel_enable_primary(plane->crtc);
 528                 intel_plane->primary_disabled = false;
 529         }
 530
 531         intel_plane->disable_plane(plane);
 532
 533         if (!intel_plane->obj)
 534                 goto out;
 535
 536         DRM_LOCK(dev);
 537         intel_unpin_fb_obj(intel_plane->obj);
 538         intel_plane->obj = NULL;
 539         DRM_UNLOCK(dev);
 540 out:
 541
 542         return ret;
 543 }
 544
 545 static void intel_destroy_plane(struct drm_plane *plane)
 546 {
 547         struct intel_plane *intel_plane = to_intel_plane(plane);
 548         intel_disable_plane(plane);
 549         drm_plane_cleanup(plane);
 550         free(intel_plane, DRM_MEM_KMS);
 551 }
 552
 553 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 554                               struct drm_file *file_priv)
 555 {
 556         struct drm_intel_sprite_colorkey *set = data;
 557         struct drm_i915_private *dev_priv = dev->dev_private;
 558         struct drm_mode_object *obj;
 559         struct drm_plane *plane;
 560         struct intel_plane *intel_plane;
 561         int ret = 0;
 562
 563         if (!dev_priv)
 564                 return -EINVAL;
 565
 566         /* Make sure we don't try to enable both src & dest simultaneously */
 567         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 568                 return -EINVAL;
 569
 570         sx_xlock(&dev->mode_config.mutex);
 571
 572         obj = drm_mode_object_find(dev, set->plane_id, DRM_MODE_OBJECT_PLANE);
 573         if (!obj) {
 574                 ret = -EINVAL;
 575                 goto out_unlock;
 576         }
 577
 578         plane = obj_to_plane(obj);
 579         intel_plane = to_intel_plane(plane);
 580         ret = intel_plane->update_colorkey(plane, set);
 581
 582 out_unlock:
 583         sx_xunlock(&dev->mode_config.mutex);
 584         return ret;
 585 }
 586
 587 int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
 588                               struct drm_file *file_priv)
 589 {
 590         struct drm_intel_sprite_colorkey *get = data;
 591         struct drm_i915_private *dev_priv = dev->dev_private;
 592         struct drm_mode_object *obj;
 593         struct drm_plane *plane;
 594         struct intel_plane *intel_plane;
 595         int ret = 0;
 596
 597         if (!dev_priv)
 598                 return -EINVAL;
 599
 600         sx_xlock(&dev->mode_config.mutex);
 601
 602         obj = drm_mode_object_find(dev, get->plane_id, DRM_MODE_OBJECT_PLANE);
 603         if (!obj) {
 604                 ret = -EINVAL;
 605                 goto out_unlock;
 606         }
 607
 608         plane = obj_to_plane(obj);
 609         intel_plane = to_intel_plane(plane);
 610         intel_plane->get_colorkey(plane, get);
 611
 612 out_unlock:
 613         sx_xunlock(&dev->mode_config.mutex);
 614         return ret;
 615 }
 616
 617 static const struct drm_plane_funcs intel_plane_funcs = {
 618         .update_plane = intel_update_plane,
 619         .disable_plane = intel_disable_plane,
 620         .destroy = intel_destroy_plane,
 621 };
 622
 623 static uint32_t snb_plane_formats[] = {
 624         DRM_FORMAT_XBGR8888,
 625         DRM_FORMAT_XRGB8888,
 626         DRM_FORMAT_YUYV,
 627         DRM_FORMAT_YVYU,
 628         DRM_FORMAT_UYVY,
 629         DRM_FORMAT_VYUY,
 630 };
 631
 632 int
 633 intel_plane_init(struct drm_device *dev, enum pipe pipe)
 634 {
 635         struct intel_plane *intel_plane;
 636         unsigned long possible_crtcs;
 637         int ret;
 638
 639         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
 640                 return -ENODEV;
 641
 642         intel_plane = malloc(sizeof(struct intel_plane), DRM_MEM_KMS,
 643             M_WAITOK | M_ZERO);
 644
 645         if (IS_GEN6(dev)) {
 646                 intel_plane->max_downscale = 16;
 647                 intel_plane->update_plane = snb_update_plane;
 648                 intel_plane->disable_plane = snb_disable_plane;
 649                 intel_plane->update_colorkey = snb_update_colorkey;
 650                 intel_plane->get_colorkey = snb_get_colorkey;
 651         } else if (IS_GEN7(dev)) {
 652                 intel_plane->max_downscale = 2;
 653                 intel_plane->update_plane = ivb_update_plane;
 654                 intel_plane->disable_plane = ivb_disable_plane;
 655                 intel_plane->update_colorkey = ivb_update_colorkey;
 656                 intel_plane->get_colorkey = ivb_get_colorkey;
 657         }
 658
 659         intel_plane->pipe = pipe;
 660         possible_crtcs = (1 << pipe);
 661         ret = drm_plane_init(dev, &intel_plane->base, possible_crtcs,
 662                              &intel_plane_funcs, snb_plane_formats,
 663                              DRM_ARRAY_SIZE(snb_plane_formats), false);
 664         if (ret)
 665                 free(intel_plane, DRM_MEM_KMS);
 666
 667         return ret;
 668 }
 669