1 /******************************************************************************
3 Copyright (c) 2001-2008, Intel Corporation
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7 modification, are permitted provided that the following conditions are met:
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32 ******************************************************************************/
36 * 82562G 10/100 Network Connection
37 * 82562G-2 10/100 Network Connection
38 * 82562GT 10/100 Network Connection
39 * 82562GT-2 10/100 Network Connection
40 * 82562V 10/100 Network Connection
41 * 82562V-2 10/100 Network Connection
42 * 82566DC-2 Gigabit Network Connection
43 * 82566DC Gigabit Network Connection
44 * 82566DM-2 Gigabit Network Connection
45 * 82566DM Gigabit Network Connection
46 * 82566MC Gigabit Network Connection
47 * 82566MM Gigabit Network Connection
48 * 82567LM Gigabit Network Connection
49 * 82567LF Gigabit Network Connection
50 * 82567V Gigabit Network Connection
51 * 82567LM-2 Gigabit Network Connection
52 * 82567LF-2 Gigabit Network Connection
53 * 82567V-2 Gigabit Network Connection
54 * 82567LF-3 Gigabit Network Connection
55 * 82567LM-3 Gigabit Network Connection
56 * 82567LM-4 Gigabit Network Connection
59 #include "e1000_api.h"
61 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
62 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
63 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
64 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
65 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
66 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
67 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
68 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
69 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
70 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
71 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
72 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
74 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
76 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
77 u16 words, u16 *data);
78 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
79 u16 words, u16 *data);
80 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
81 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
82 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
84 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
85 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw);
86 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw);
87 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
88 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
89 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
90 u16 *speed, u16 *duplex);
91 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
92 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
93 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
94 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
95 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
96 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
97 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
98 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
99 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
100 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
101 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
102 u32 offset, u8 *data);
103 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
105 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
106 u32 offset, u16 *data);
107 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
108 u32 offset, u8 byte);
109 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
110 u32 offset, u8 data);
111 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
113 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
114 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
116 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
117 /* Offset 04h HSFSTS */
118 union ich8_hws_flash_status {
120 u16 flcdone :1; /* bit 0 Flash Cycle Done */
121 u16 flcerr :1; /* bit 1 Flash Cycle Error */
122 u16 dael :1; /* bit 2 Direct Access error Log */
123 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
124 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
125 u16 reserved1 :2; /* bit 13:6 Reserved */
126 u16 reserved2 :6; /* bit 13:6 Reserved */
127 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
128 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
133 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
134 /* Offset 06h FLCTL */
135 union ich8_hws_flash_ctrl {
136 struct ich8_hsflctl {
137 u16 flcgo :1; /* 0 Flash Cycle Go */
138 u16 flcycle :2; /* 2:1 Flash Cycle */
139 u16 reserved :5; /* 7:3 Reserved */
140 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
141 u16 flockdn :6; /* 15:10 Reserved */
146 /* ICH Flash Region Access Permissions */
147 union ich8_hws_flash_regacc {
149 u32 grra :8; /* 0:7 GbE region Read Access */
150 u32 grwa :8; /* 8:15 GbE region Write Access */
151 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
152 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
158 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
159 * @hw: pointer to the HW structure
161 * Initialize family-specific PHY parameters and function pointers.
163 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
165 struct e1000_phy_info *phy = &hw->phy;
166 s32 ret_val = E1000_SUCCESS;
169 DEBUGFUNC("e1000_init_phy_params_ich8lan");
172 phy->reset_delay_us = 100;
174 phy->ops.acquire = e1000_acquire_swflag_ich8lan;
175 phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
176 phy->ops.check_reset_block = e1000_check_reset_block_ich8lan;
177 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ich8lan;
178 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
179 phy->ops.get_cfg_done = e1000_get_cfg_done_ich8lan;
180 phy->ops.get_info = e1000_get_phy_info_ich8lan;
181 phy->ops.read_reg = e1000_read_phy_reg_igp;
182 phy->ops.release = e1000_release_swflag_ich8lan;
183 phy->ops.reset = e1000_phy_hw_reset_ich8lan;
184 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan;
185 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan;
186 phy->ops.write_reg = e1000_write_phy_reg_igp;
187 phy->ops.power_up = e1000_power_up_phy_copper;
188 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
191 * We may need to do this twice - once for IGP and if that fails,
192 * we'll set BM func pointers and try again
194 ret_val = e1000_determine_phy_address(hw);
196 phy->ops.write_reg = e1000_write_phy_reg_bm;
197 phy->ops.read_reg = e1000_read_phy_reg_bm;
198 ret_val = e1000_determine_phy_address(hw);
200 DEBUGOUT("Cannot determine PHY address. Erroring out\n");
206 while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
209 ret_val = e1000_get_phy_id(hw);
216 case IGP03E1000_E_PHY_ID:
217 phy->type = e1000_phy_igp_3;
218 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
221 case IFE_PLUS_E_PHY_ID:
223 phy->type = e1000_phy_ife;
224 phy->autoneg_mask = E1000_ALL_NOT_GIG;
226 case BME1000_E_PHY_ID:
227 phy->type = e1000_phy_bm;
228 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
229 phy->ops.read_reg = e1000_read_phy_reg_bm;
230 phy->ops.write_reg = e1000_write_phy_reg_bm;
231 phy->ops.commit = e1000_phy_sw_reset_generic;
234 ret_val = -E1000_ERR_PHY;
243 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
244 * @hw: pointer to the HW structure
246 * Initialize family-specific NVM parameters and function
249 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
251 struct e1000_nvm_info *nvm = &hw->nvm;
252 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
253 u32 gfpreg, sector_base_addr, sector_end_addr;
254 s32 ret_val = E1000_SUCCESS;
257 DEBUGFUNC("e1000_init_nvm_params_ich8lan");
259 /* Can't read flash registers if the register set isn't mapped. */
260 if (!hw->flash_address) {
261 DEBUGOUT("ERROR: Flash registers not mapped\n");
262 ret_val = -E1000_ERR_CONFIG;
266 nvm->type = e1000_nvm_flash_sw;
268 gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
271 * sector_X_addr is a "sector"-aligned address (4096 bytes)
272 * Add 1 to sector_end_addr since this sector is included in
275 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
276 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
278 /* flash_base_addr is byte-aligned */
279 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
282 * find total size of the NVM, then cut in half since the total
283 * size represents two separate NVM banks.
285 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
286 << FLASH_SECTOR_ADDR_SHIFT;
287 nvm->flash_bank_size /= 2;
288 /* Adjust to word count */
289 nvm->flash_bank_size /= sizeof(u16);
291 nvm->word_size = E1000_SHADOW_RAM_WORDS;
293 /* Clear shadow ram */
294 for (i = 0; i < nvm->word_size; i++) {
295 dev_spec->shadow_ram[i].modified = FALSE;
296 dev_spec->shadow_ram[i].value = 0xFFFF;
299 /* Function Pointers */
300 nvm->ops.acquire = e1000_acquire_swflag_ich8lan;
301 nvm->ops.read = e1000_read_nvm_ich8lan;
302 nvm->ops.release = e1000_release_swflag_ich8lan;
303 nvm->ops.update = e1000_update_nvm_checksum_ich8lan;
304 nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
305 nvm->ops.validate = e1000_validate_nvm_checksum_ich8lan;
306 nvm->ops.write = e1000_write_nvm_ich8lan;
313 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
314 * @hw: pointer to the HW structure
316 * Initialize family-specific MAC parameters and function
319 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
321 struct e1000_mac_info *mac = &hw->mac;
323 DEBUGFUNC("e1000_init_mac_params_ich8lan");
325 /* Set media type function pointer */
326 hw->phy.media_type = e1000_media_type_copper;
328 /* Set mta register count */
329 mac->mta_reg_count = 32;
330 /* Set rar entry count */
331 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
332 if (mac->type == e1000_ich8lan)
333 mac->rar_entry_count--;
334 /* Set if part includes ASF firmware */
335 mac->asf_firmware_present = TRUE;
336 /* Set if manageability features are enabled. */
337 mac->arc_subsystem_valid = TRUE;
339 /* Function pointers */
341 /* bus type/speed/width */
342 mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
344 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
346 mac->ops.reset_hw = e1000_reset_hw_ich8lan;
347 /* hw initialization */
348 mac->ops.init_hw = e1000_init_hw_ich8lan;
350 mac->ops.setup_link = e1000_setup_link_ich8lan;
351 /* physical interface setup */
352 mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
354 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
355 /* check management mode */
356 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
358 mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
359 /* multicast address update */
360 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
362 mac->ops.mta_set = e1000_mta_set_generic;
364 mac->ops.blink_led = e1000_blink_led_generic;
366 mac->ops.setup_led = e1000_setup_led_generic;
368 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
369 /* turn on/off LED */
370 mac->ops.led_on = e1000_led_on_ich8lan;
371 mac->ops.led_off = e1000_led_off_ich8lan;
372 /* clear hardware counters */
373 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
375 /* Enable PCS Lock-loss workaround for ICH8 */
376 if (mac->type == e1000_ich8lan)
377 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
380 return E1000_SUCCESS;
384 * e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
385 * @hw: pointer to the HW structure
387 * Initialize family-specific function pointers for PHY, MAC, and NVM.
389 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
391 DEBUGFUNC("e1000_init_function_pointers_ich8lan");
393 hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
394 hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
395 hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
399 * e1000_acquire_swflag_ich8lan - Acquire software control flag
400 * @hw: pointer to the HW structure
402 * Acquires the software control flag for performing NVM and PHY
403 * operations. This is a function pointer entry point only called by
404 * read/write routines for the PHY and NVM parts.
406 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
408 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
409 s32 ret_val = E1000_SUCCESS;
411 DEBUGFUNC("e1000_acquire_swflag_ich8lan");
414 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
415 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
416 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
418 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
419 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
426 DEBUGOUT("FW or HW has locked the resource for too long.\n");
427 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
428 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
429 ret_val = -E1000_ERR_CONFIG;
438 * e1000_release_swflag_ich8lan - Release software control flag
439 * @hw: pointer to the HW structure
441 * Releases the software control flag for performing NVM and PHY operations.
442 * This is a function pointer entry point only called by read/write
443 * routines for the PHY and NVM parts.
445 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
449 DEBUGFUNC("e1000_release_swflag_ich8lan");
451 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
452 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
453 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
459 * e1000_check_mng_mode_ich8lan - Checks management mode
460 * @hw: pointer to the HW structure
462 * This checks if the adapter has manageability enabled.
463 * This is a function pointer entry point only called by read/write
464 * routines for the PHY and NVM parts.
466 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
470 DEBUGFUNC("e1000_check_mng_mode_ich8lan");
472 fwsm = E1000_READ_REG(hw, E1000_FWSM);
474 return (fwsm & E1000_FWSM_MODE_MASK) ==
475 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
479 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
480 * @hw: pointer to the HW structure
482 * Checks if firmware is blocking the reset of the PHY.
483 * This is a function pointer entry point only called by
486 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
490 DEBUGFUNC("e1000_check_reset_block_ich8lan");
492 fwsm = E1000_READ_REG(hw, E1000_FWSM);
494 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
495 : E1000_BLK_PHY_RESET;
499 * e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
500 * @hw: pointer to the HW structure
502 * Forces the speed and duplex settings of the PHY.
503 * This is a function pointer entry point only called by
504 * PHY setup routines.
506 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
508 struct e1000_phy_info *phy = &hw->phy;
513 DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
515 if (phy->type != e1000_phy_ife) {
516 ret_val = e1000_phy_force_speed_duplex_igp(hw);
520 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
524 e1000_phy_force_speed_duplex_setup(hw, &data);
526 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
530 /* Disable MDI-X support for 10/100 */
531 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
535 data &= ~IFE_PMC_AUTO_MDIX;
536 data &= ~IFE_PMC_FORCE_MDIX;
538 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
542 DEBUGOUT1("IFE PMC: %X\n", data);
546 if (phy->autoneg_wait_to_complete) {
547 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
549 ret_val = e1000_phy_has_link_generic(hw,
557 DEBUGOUT("Link taking longer than expected.\n");
560 ret_val = e1000_phy_has_link_generic(hw,
573 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
574 * @hw: pointer to the HW structure
577 * This is a function pointer entry point called by drivers
578 * or other shared routines.
580 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
582 struct e1000_phy_info *phy = &hw->phy;
583 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
585 u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
586 u16 word_addr, reg_data, reg_addr, phy_page = 0;
588 DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
590 ret_val = e1000_phy_hw_reset_generic(hw);
595 * Initialize the PHY from the NVM on ICH platforms. This
596 * is needed due to an issue where the NVM configuration is
597 * not properly autoloaded after power transitions.
598 * Therefore, after each PHY reset, we will load the
599 * configuration data out of the NVM manually.
601 if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
602 /* Check if SW needs configure the PHY */
603 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
604 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
605 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
607 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
609 data = E1000_READ_REG(hw, E1000_FEXTNVM);
610 if (!(data & sw_cfg_mask))
613 /* Wait for basic configuration completes before proceeding*/
615 data = E1000_READ_REG(hw, E1000_STATUS);
616 data &= E1000_STATUS_LAN_INIT_DONE;
618 } while ((!data) && --loop);
621 * If basic configuration is incomplete before the above loop
622 * count reaches 0, loading the configuration from NVM will
623 * leave the PHY in a bad state possibly resulting in no link.
626 DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
628 /* Clear the Init Done bit for the next init event */
629 data = E1000_READ_REG(hw, E1000_STATUS);
630 data &= ~E1000_STATUS_LAN_INIT_DONE;
631 E1000_WRITE_REG(hw, E1000_STATUS, data);
634 * Make sure HW does not configure LCD from PHY
635 * extended configuration before SW configuration
637 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
638 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
641 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
642 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
643 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
647 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
648 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
650 /* Configure LCD from extended configuration region. */
652 /* cnf_base_addr is in DWORD */
653 word_addr = (u16)(cnf_base_addr << 1);
655 for (i = 0; i < cnf_size; i++) {
656 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
661 ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
666 /* Save off the PHY page for future writes. */
667 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
672 reg_addr |= phy_page;
674 ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
685 * e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
686 * @hw: pointer to the HW structure
688 * Wrapper for calling the get_phy_info routines for the appropriate phy type.
690 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
692 s32 ret_val = -E1000_ERR_PHY_TYPE;
694 DEBUGFUNC("e1000_get_phy_info_ich8lan");
696 switch (hw->phy.type) {
698 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
700 case e1000_phy_igp_3:
702 ret_val = e1000_get_phy_info_igp(hw);
712 * e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
713 * @hw: pointer to the HW structure
715 * Populates "phy" structure with various feature states.
716 * This function is only called by other family-specific
719 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
721 struct e1000_phy_info *phy = &hw->phy;
726 DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
728 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
733 DEBUGOUT("Phy info is only valid if link is up\n");
734 ret_val = -E1000_ERR_CONFIG;
738 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
741 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
744 if (phy->polarity_correction) {
745 ret_val = e1000_check_polarity_ife_ich8lan(hw);
749 /* Polarity is forced */
750 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
751 ? e1000_rev_polarity_reversed
752 : e1000_rev_polarity_normal;
755 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
759 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
761 /* The following parameters are undefined for 10/100 operation. */
762 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
763 phy->local_rx = e1000_1000t_rx_status_undefined;
764 phy->remote_rx = e1000_1000t_rx_status_undefined;
771 * e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
772 * @hw: pointer to the HW structure
774 * Polarity is determined on the polarity reversal feature being enabled.
775 * This function is only called by other family-specific
778 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
780 struct e1000_phy_info *phy = &hw->phy;
782 u16 phy_data, offset, mask;
784 DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
787 * Polarity is determined based on the reversal feature being enabled.
789 if (phy->polarity_correction) {
790 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
791 mask = IFE_PESC_POLARITY_REVERSED;
793 offset = IFE_PHY_SPECIAL_CONTROL;
794 mask = IFE_PSC_FORCE_POLARITY;
797 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
800 phy->cable_polarity = (phy_data & mask)
801 ? e1000_rev_polarity_reversed
802 : e1000_rev_polarity_normal;
808 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
809 * @hw: pointer to the HW structure
810 * @active: TRUE to enable LPLU, FALSE to disable
812 * Sets the LPLU D0 state according to the active flag. When
813 * activating LPLU this function also disables smart speed
814 * and vice versa. LPLU will not be activated unless the
815 * device autonegotiation advertisement meets standards of
816 * either 10 or 10/100 or 10/100/1000 at all duplexes.
817 * This is a function pointer entry point only called by
818 * PHY setup routines.
820 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
822 struct e1000_phy_info *phy = &hw->phy;
824 s32 ret_val = E1000_SUCCESS;
827 DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
829 if (phy->type == e1000_phy_ife)
832 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
835 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
836 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
839 * Call gig speed drop workaround on LPLU before accessing
842 if ((hw->mac.type == e1000_ich8lan) &&
843 (hw->phy.type == e1000_phy_igp_3))
844 e1000_gig_downshift_workaround_ich8lan(hw);
846 /* When LPLU is enabled, we should disable SmartSpeed */
847 ret_val = phy->ops.read_reg(hw,
848 IGP01E1000_PHY_PORT_CONFIG,
850 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
851 ret_val = phy->ops.write_reg(hw,
852 IGP01E1000_PHY_PORT_CONFIG,
857 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
858 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
861 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
862 * during Dx states where the power conservation is most
863 * important. During driver activity we should enable
864 * SmartSpeed, so performance is maintained.
866 if (phy->smart_speed == e1000_smart_speed_on) {
867 ret_val = phy->ops.read_reg(hw,
868 IGP01E1000_PHY_PORT_CONFIG,
873 data |= IGP01E1000_PSCFR_SMART_SPEED;
874 ret_val = phy->ops.write_reg(hw,
875 IGP01E1000_PHY_PORT_CONFIG,
879 } else if (phy->smart_speed == e1000_smart_speed_off) {
880 ret_val = phy->ops.read_reg(hw,
881 IGP01E1000_PHY_PORT_CONFIG,
886 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
887 ret_val = phy->ops.write_reg(hw,
888 IGP01E1000_PHY_PORT_CONFIG,
900 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
901 * @hw: pointer to the HW structure
902 * @active: TRUE to enable LPLU, FALSE to disable
904 * Sets the LPLU D3 state according to the active flag. When
905 * activating LPLU this function also disables smart speed
906 * and vice versa. LPLU will not be activated unless the
907 * device autonegotiation advertisement meets standards of
908 * either 10 or 10/100 or 10/100/1000 at all duplexes.
909 * This is a function pointer entry point only called by
910 * PHY setup routines.
912 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
914 struct e1000_phy_info *phy = &hw->phy;
916 s32 ret_val = E1000_SUCCESS;
919 DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
921 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
924 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
925 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
927 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
928 * during Dx states where the power conservation is most
929 * important. During driver activity we should enable
930 * SmartSpeed, so performance is maintained.
932 if (phy->smart_speed == e1000_smart_speed_on) {
933 ret_val = phy->ops.read_reg(hw,
934 IGP01E1000_PHY_PORT_CONFIG,
939 data |= IGP01E1000_PSCFR_SMART_SPEED;
940 ret_val = phy->ops.write_reg(hw,
941 IGP01E1000_PHY_PORT_CONFIG,
945 } else if (phy->smart_speed == e1000_smart_speed_off) {
946 ret_val = phy->ops.read_reg(hw,
947 IGP01E1000_PHY_PORT_CONFIG,
952 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
953 ret_val = phy->ops.write_reg(hw,
954 IGP01E1000_PHY_PORT_CONFIG,
959 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
960 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
961 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
962 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
963 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
966 * Call gig speed drop workaround on LPLU before accessing
969 if ((hw->mac.type == e1000_ich8lan) &&
970 (hw->phy.type == e1000_phy_igp_3))
971 e1000_gig_downshift_workaround_ich8lan(hw);
973 /* When LPLU is enabled, we should disable SmartSpeed */
974 ret_val = phy->ops.read_reg(hw,
975 IGP01E1000_PHY_PORT_CONFIG,
980 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
981 ret_val = phy->ops.write_reg(hw,
982 IGP01E1000_PHY_PORT_CONFIG,
991 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
992 * @hw: pointer to the HW structure
993 * @bank: pointer to the variable that returns the active bank
995 * Reads signature byte from the NVM using the flash access registers.
997 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
999 s32 ret_val = E1000_SUCCESS;
1000 struct e1000_nvm_info *nvm = &hw->nvm;
1001 /* flash bank size is in words */
1002 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1003 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1004 u8 bank_high_byte = 0;
1006 if (hw->mac.type != e1000_ich10lan) {
1007 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1013 * Make sure the signature for bank 0 is valid,
1014 * if not check for bank1
1016 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
1017 if ((bank_high_byte & 0xC0) == 0x80) {
1021 * find if segment 1 is valid by verifying
1022 * bit 15:14 = 10b in word 0x13
1024 e1000_read_flash_byte_ich8lan(hw,
1025 act_offset + bank1_offset,
1028 /* bank1 has a valid signature equivalent to SEC1V */
1029 if ((bank_high_byte & 0xC0) == 0x80) {
1032 DEBUGOUT("ERROR: EEPROM not present\n");
1033 ret_val = -E1000_ERR_NVM;
1042 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1043 * @hw: pointer to the HW structure
1044 * @offset: The offset (in bytes) of the word(s) to read.
1045 * @words: Size of data to read in words
1046 * @data: Pointer to the word(s) to read at offset.
1048 * Reads a word(s) from the NVM using the flash access registers.
1050 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1053 struct e1000_nvm_info *nvm = &hw->nvm;
1054 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1056 s32 ret_val = E1000_SUCCESS;
1060 DEBUGFUNC("e1000_read_nvm_ich8lan");
1062 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1064 DEBUGOUT("nvm parameter(s) out of bounds\n");
1065 ret_val = -E1000_ERR_NVM;
1069 ret_val = nvm->ops.acquire(hw);
1073 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1074 if (ret_val != E1000_SUCCESS)
1077 act_offset = (bank) ? nvm->flash_bank_size : 0;
1078 act_offset += offset;
1080 for (i = 0; i < words; i++) {
1081 if ((dev_spec->shadow_ram) &&
1082 (dev_spec->shadow_ram[offset+i].modified)) {
1083 data[i] = dev_spec->shadow_ram[offset+i].value;
1085 ret_val = e1000_read_flash_word_ich8lan(hw,
1094 nvm->ops.release(hw);
1101 * e1000_flash_cycle_init_ich8lan - Initialize flash
1102 * @hw: pointer to the HW structure
1104 * This function does initial flash setup so that a new read/write/erase cycle
1107 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1109 union ich8_hws_flash_status hsfsts;
1110 s32 ret_val = -E1000_ERR_NVM;
1113 DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1115 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1117 /* Check if the flash descriptor is valid */
1118 if (hsfsts.hsf_status.fldesvalid == 0) {
1119 DEBUGOUT("Flash descriptor invalid. "
1120 "SW Sequencing must be used.");
1124 /* Clear FCERR and DAEL in hw status by writing 1 */
1125 hsfsts.hsf_status.flcerr = 1;
1126 hsfsts.hsf_status.dael = 1;
1128 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1131 * Either we should have a hardware SPI cycle in progress
1132 * bit to check against, in order to start a new cycle or
1133 * FDONE bit should be changed in the hardware so that it
1134 * is 1 after hardware reset, which can then be used as an
1135 * indication whether a cycle is in progress or has been
1139 if (hsfsts.hsf_status.flcinprog == 0) {
1141 * There is no cycle running at present,
1142 * so we can start a cycle.
1143 * Begin by setting Flash Cycle Done.
1145 hsfsts.hsf_status.flcdone = 1;
1146 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1147 ret_val = E1000_SUCCESS;
1150 * Otherwise poll for sometime so the current
1151 * cycle has a chance to end before giving up.
1153 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1154 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1156 if (hsfsts.hsf_status.flcinprog == 0) {
1157 ret_val = E1000_SUCCESS;
1162 if (ret_val == E1000_SUCCESS) {
1164 * Successful in waiting for previous cycle to timeout,
1165 * now set the Flash Cycle Done.
1167 hsfsts.hsf_status.flcdone = 1;
1168 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
1171 DEBUGOUT("Flash controller busy, cannot get access");
1180 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1181 * @hw: pointer to the HW structure
1182 * @timeout: maximum time to wait for completion
1184 * This function starts a flash cycle and waits for its completion.
1186 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1188 union ich8_hws_flash_ctrl hsflctl;
1189 union ich8_hws_flash_status hsfsts;
1190 s32 ret_val = -E1000_ERR_NVM;
1193 DEBUGFUNC("e1000_flash_cycle_ich8lan");
1195 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1196 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1197 hsflctl.hsf_ctrl.flcgo = 1;
1198 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1200 /* wait till FDONE bit is set to 1 */
1202 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1203 if (hsfsts.hsf_status.flcdone == 1)
1206 } while (i++ < timeout);
1208 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1209 ret_val = E1000_SUCCESS;
1215 * e1000_read_flash_word_ich8lan - Read word from flash
1216 * @hw: pointer to the HW structure
1217 * @offset: offset to data location
1218 * @data: pointer to the location for storing the data
1220 * Reads the flash word at offset into data. Offset is converted
1221 * to bytes before read.
1223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1228 DEBUGFUNC("e1000_read_flash_word_ich8lan");
1231 ret_val = -E1000_ERR_NVM;
1235 /* Must convert offset into bytes. */
1238 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1245 * e1000_read_flash_byte_ich8lan - Read byte from flash
1246 * @hw: pointer to the HW structure
1247 * @offset: The offset of the byte to read.
1248 * @data: Pointer to a byte to store the value read.
1250 * Reads a single byte from the NVM using the flash access registers.
1252 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1255 s32 ret_val = E1000_SUCCESS;
1258 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1269 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1270 * @hw: pointer to the HW structure
1271 * @offset: The offset (in bytes) of the byte or word to read.
1272 * @size: Size of data to read, 1=byte 2=word
1273 * @data: Pointer to the word to store the value read.
1275 * Reads a byte or word from the NVM using the flash access registers.
1277 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1280 union ich8_hws_flash_status hsfsts;
1281 union ich8_hws_flash_ctrl hsflctl;
1282 u32 flash_linear_addr;
1284 s32 ret_val = -E1000_ERR_NVM;
1287 DEBUGFUNC("e1000_read_flash_data_ich8lan");
1289 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1292 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1293 hw->nvm.flash_base_addr;
1298 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1299 if (ret_val != E1000_SUCCESS)
1302 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1303 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1304 hsflctl.hsf_ctrl.fldbcount = size - 1;
1305 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1306 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1308 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1310 ret_val = e1000_flash_cycle_ich8lan(hw,
1311 ICH_FLASH_READ_COMMAND_TIMEOUT);
1314 * Check if FCERR is set to 1, if set to 1, clear it
1315 * and try the whole sequence a few more times, else
1316 * read in (shift in) the Flash Data0, the order is
1317 * least significant byte first msb to lsb
1319 if (ret_val == E1000_SUCCESS) {
1320 flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1322 *data = (u8)(flash_data & 0x000000FF);
1324 *data = (u16)(flash_data & 0x0000FFFF);
1328 * If we've gotten here, then things are probably
1329 * completely hosed, but if the error condition is
1330 * detected, it won't hurt to give it another try...
1331 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1333 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1335 if (hsfsts.hsf_status.flcerr == 1) {
1336 /* Repeat for some time before giving up. */
1338 } else if (hsfsts.hsf_status.flcdone == 0) {
1339 DEBUGOUT("Timeout error - flash cycle "
1340 "did not complete.");
1344 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1351 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1352 * @hw: pointer to the HW structure
1353 * @offset: The offset (in bytes) of the word(s) to write.
1354 * @words: Size of data to write in words
1355 * @data: Pointer to the word(s) to write at offset.
1357 * Writes a byte or word to the NVM using the flash access registers.
1359 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1362 struct e1000_nvm_info *nvm = &hw->nvm;
1363 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1364 s32 ret_val = E1000_SUCCESS;
1367 DEBUGFUNC("e1000_write_nvm_ich8lan");
1369 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1371 DEBUGOUT("nvm parameter(s) out of bounds\n");
1372 ret_val = -E1000_ERR_NVM;
1376 ret_val = nvm->ops.acquire(hw);
1380 for (i = 0; i < words; i++) {
1381 dev_spec->shadow_ram[offset+i].modified = TRUE;
1382 dev_spec->shadow_ram[offset+i].value = data[i];
1385 nvm->ops.release(hw);
1392 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1393 * @hw: pointer to the HW structure
1395 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1396 * which writes the checksum to the shadow ram. The changes in the shadow
1397 * ram are then committed to the EEPROM by processing each bank at a time
1398 * checking for the modified bit and writing only the pending changes.
1399 * After a successful commit, the shadow ram is cleared and is ready for
1402 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1404 struct e1000_nvm_info *nvm = &hw->nvm;
1405 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1406 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1410 DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1412 ret_val = e1000_update_nvm_checksum_generic(hw);
1416 if (nvm->type != e1000_nvm_flash_sw)
1419 ret_val = nvm->ops.acquire(hw);
1424 * We're writing to the opposite bank so if we're on bank 1,
1425 * write to bank 0 etc. We also need to erase the segment that
1426 * is going to be written
1428 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1429 if (ret_val != E1000_SUCCESS)
1433 new_bank_offset = nvm->flash_bank_size;
1434 old_bank_offset = 0;
1435 e1000_erase_flash_bank_ich8lan(hw, 1);
1437 old_bank_offset = nvm->flash_bank_size;
1438 new_bank_offset = 0;
1439 e1000_erase_flash_bank_ich8lan(hw, 0);
1442 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1444 * Determine whether to write the value stored
1445 * in the other NVM bank or a modified value stored
1448 if (dev_spec->shadow_ram[i].modified) {
1449 data = dev_spec->shadow_ram[i].value;
1451 e1000_read_flash_word_ich8lan(hw,
1452 i + old_bank_offset,
1457 * If the word is 0x13, then make sure the signature bits
1458 * (15:14) are 11b until the commit has completed.
1459 * This will allow us to write 10b which indicates the
1460 * signature is valid. We want to do this after the write
1461 * has completed so that we don't mark the segment valid
1462 * while the write is still in progress
1464 if (i == E1000_ICH_NVM_SIG_WORD)
1465 data |= E1000_ICH_NVM_SIG_MASK;
1467 /* Convert offset to bytes. */
1468 act_offset = (i + new_bank_offset) << 1;
1471 /* Write the bytes to the new bank. */
1472 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1479 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1487 * Don't bother writing the segment valid bits if sector
1488 * programming failed.
1491 DEBUGOUT("Flash commit failed.\n");
1492 nvm->ops.release(hw);
1497 * Finally validate the new segment by setting bit 15:14
1498 * to 10b in word 0x13 , this can be done without an
1499 * erase as well since these bits are 11 to start with
1500 * and we need to change bit 14 to 0b
1502 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1503 e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1505 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1509 nvm->ops.release(hw);
1514 * And invalidate the previously valid segment by setting
1515 * its signature word (0x13) high_byte to 0b. This can be
1516 * done without an erase because flash erase sets all bits
1517 * to 1's. We can write 1's to 0's without an erase
1519 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1520 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1522 nvm->ops.release(hw);
1526 /* Great! Everything worked, we can now clear the cached entries. */
1527 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1528 dev_spec->shadow_ram[i].modified = FALSE;
1529 dev_spec->shadow_ram[i].value = 0xFFFF;
1532 nvm->ops.release(hw);
1535 * Reload the EEPROM, or else modifications will not appear
1536 * until after the next adapter reset.
1538 nvm->ops.reload(hw);
1546 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1547 * @hw: pointer to the HW structure
1549 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1550 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
1551 * calculated, in which case we need to calculate the checksum and set bit 6.
1553 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1555 s32 ret_val = E1000_SUCCESS;
1558 DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1561 * Read 0x19 and check bit 6. If this bit is 0, the checksum
1562 * needs to be fixed. This bit is an indication that the NVM
1563 * was prepared by OEM software and did not calculate the
1564 * checksum...a likely scenario.
1566 ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
1570 if ((data & 0x40) == 0) {
1572 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
1575 ret_val = hw->nvm.ops.update(hw);
1580 ret_val = e1000_validate_nvm_checksum_generic(hw);
1587 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1588 * @hw: pointer to the HW structure
1589 * @offset: The offset (in bytes) of the byte/word to read.
1590 * @size: Size of data to read, 1=byte 2=word
1591 * @data: The byte(s) to write to the NVM.
1593 * Writes one/two bytes to the NVM using the flash access registers.
1595 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1598 union ich8_hws_flash_status hsfsts;
1599 union ich8_hws_flash_ctrl hsflctl;
1600 u32 flash_linear_addr;
1602 s32 ret_val = -E1000_ERR_NVM;
1605 DEBUGFUNC("e1000_write_ich8_data");
1607 if (size < 1 || size > 2 || data > size * 0xff ||
1608 offset > ICH_FLASH_LINEAR_ADDR_MASK)
1611 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1612 hw->nvm.flash_base_addr;
1617 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1618 if (ret_val != E1000_SUCCESS)
1621 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1622 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1623 hsflctl.hsf_ctrl.fldbcount = size - 1;
1624 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1625 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1627 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1630 flash_data = (u32)data & 0x00FF;
1632 flash_data = (u32)data;
1634 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1637 * check if FCERR is set to 1 , if set to 1, clear it
1638 * and try the whole sequence a few more times else done
1640 ret_val = e1000_flash_cycle_ich8lan(hw,
1641 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1642 if (ret_val == E1000_SUCCESS)
1646 * If we're here, then things are most likely
1647 * completely hosed, but if the error condition
1648 * is detected, it won't hurt to give it another
1649 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1651 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1652 if (hsfsts.hsf_status.flcerr == 1) {
1653 /* Repeat for some time before giving up. */
1655 } else if (hsfsts.hsf_status.flcdone == 0) {
1656 DEBUGOUT("Timeout error - flash cycle "
1657 "did not complete.");
1660 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1667 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1668 * @hw: pointer to the HW structure
1669 * @offset: The index of the byte to read.
1670 * @data: The byte to write to the NVM.
1672 * Writes a single byte to the NVM using the flash access registers.
1674 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1677 u16 word = (u16)data;
1679 DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1681 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1685 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1686 * @hw: pointer to the HW structure
1687 * @offset: The offset of the byte to write.
1688 * @byte: The byte to write to the NVM.
1690 * Writes a single byte to the NVM using the flash access registers.
1691 * Goes through a retry algorithm before giving up.
1693 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1694 u32 offset, u8 byte)
1697 u16 program_retries;
1699 DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1701 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1702 if (ret_val == E1000_SUCCESS)
1705 for (program_retries = 0; program_retries < 100; program_retries++) {
1706 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1708 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1709 if (ret_val == E1000_SUCCESS)
1712 if (program_retries == 100) {
1713 ret_val = -E1000_ERR_NVM;
1722 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1723 * @hw: pointer to the HW structure
1724 * @bank: 0 for first bank, 1 for second bank, etc.
1726 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1727 * bank N is 4096 * N + flash_reg_addr.
1729 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1731 struct e1000_nvm_info *nvm = &hw->nvm;
1732 union ich8_hws_flash_status hsfsts;
1733 union ich8_hws_flash_ctrl hsflctl;
1734 u32 flash_linear_addr;
1735 /* bank size is in 16bit words - adjust to bytes */
1736 u32 flash_bank_size = nvm->flash_bank_size * 2;
1737 s32 ret_val = E1000_SUCCESS;
1739 s32 j, iteration, sector_size;
1741 DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1743 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1746 * Determine HW Sector size: Read BERASE bits of hw flash status
1748 * 00: The Hw sector is 256 bytes, hence we need to erase 16
1749 * consecutive sectors. The start index for the nth Hw sector
1750 * can be calculated as = bank * 4096 + n * 256
1751 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1752 * The start index for the nth Hw sector can be calculated
1754 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1755 * (ich9 only, otherwise error condition)
1756 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1758 switch (hsfsts.hsf_status.berasesz) {
1760 /* Hw sector size 256 */
1761 sector_size = ICH_FLASH_SEG_SIZE_256;
1762 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1765 sector_size = ICH_FLASH_SEG_SIZE_4K;
1766 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1769 if (hw->mac.type == e1000_ich9lan) {
1770 sector_size = ICH_FLASH_SEG_SIZE_8K;
1771 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1773 ret_val = -E1000_ERR_NVM;
1778 sector_size = ICH_FLASH_SEG_SIZE_64K;
1779 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1782 ret_val = -E1000_ERR_NVM;
1786 /* Start with the base address, then add the sector offset. */
1787 flash_linear_addr = hw->nvm.flash_base_addr;
1788 flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1790 for (j = 0; j < iteration ; j++) {
1793 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1798 * Write a value 11 (block Erase) in Flash
1799 * Cycle field in hw flash control
1801 hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1803 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1804 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
1808 * Write the last 24 bits of an index within the
1809 * block into Flash Linear address field in Flash
1812 flash_linear_addr += (j * sector_size);
1813 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
1816 ret_val = e1000_flash_cycle_ich8lan(hw,
1817 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1818 if (ret_val == E1000_SUCCESS)
1822 * Check if FCERR is set to 1. If 1,
1823 * clear it and try the whole sequence
1824 * a few more times else Done
1826 hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1828 if (hsfsts.hsf_status.flcerr == 1)
1829 /* repeat for some time before giving up */
1831 else if (hsfsts.hsf_status.flcdone == 0)
1833 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1841 * e1000_valid_led_default_ich8lan - Set the default LED settings
1842 * @hw: pointer to the HW structure
1843 * @data: Pointer to the LED settings
1845 * Reads the LED default settings from the NVM to data. If the NVM LED
1846 * settings is all 0's or F's, set the LED default to a valid LED default
1849 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1853 DEBUGFUNC("e1000_valid_led_default_ich8lan");
1855 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1857 DEBUGOUT("NVM Read Error\n");
1861 if (*data == ID_LED_RESERVED_0000 ||
1862 *data == ID_LED_RESERVED_FFFF)
1863 *data = ID_LED_DEFAULT_ICH8LAN;
1870 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1871 * @hw: pointer to the HW structure
1873 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1874 * register, so the the bus width is hard coded.
1876 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1878 struct e1000_bus_info *bus = &hw->bus;
1881 DEBUGFUNC("e1000_get_bus_info_ich8lan");
1883 ret_val = e1000_get_bus_info_pcie_generic(hw);
1886 * ICH devices are "PCI Express"-ish. They have
1887 * a configuration space, but do not contain
1888 * PCI Express Capability registers, so bus width
1889 * must be hardcoded.
1891 if (bus->width == e1000_bus_width_unknown)
1892 bus->width = e1000_bus_width_pcie_x1;
1898 * e1000_reset_hw_ich8lan - Reset the hardware
1899 * @hw: pointer to the HW structure
1901 * Does a full reset of the hardware which includes a reset of the PHY and
1904 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1909 DEBUGFUNC("e1000_reset_hw_ich8lan");
1912 * Prevent the PCI-E bus from sticking if there is no TLP connection
1913 * on the last TLP read/write transaction when MAC is reset.
1915 ret_val = e1000_disable_pcie_master_generic(hw);
1917 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1919 DEBUGOUT("Masking off all interrupts\n");
1920 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1923 * Disable the Transmit and Receive units. Then delay to allow
1924 * any pending transactions to complete before we hit the MAC
1925 * with the global reset.
1927 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1928 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1929 E1000_WRITE_FLUSH(hw);
1933 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1934 if (hw->mac.type == e1000_ich8lan) {
1935 /* Set Tx and Rx buffer allocation to 8k apiece. */
1936 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1937 /* Set Packet Buffer Size to 16k. */
1938 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
1941 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1943 if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
1945 * PHY HW reset requires MAC CORE reset at the same
1946 * time to make sure the interface between MAC and the
1947 * external PHY is reset.
1949 ctrl |= E1000_CTRL_PHY_RST;
1951 ret_val = e1000_acquire_swflag_ich8lan(hw);
1952 DEBUGOUT("Issuing a global reset to ich8lan\n");
1953 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
1956 ret_val = e1000_get_auto_rd_done_generic(hw);
1959 * When auto config read does not complete, do not
1960 * return with an error. This can happen in situations
1961 * where there is no eeprom and prevents getting link.
1963 DEBUGOUT("Auto Read Done did not complete\n");
1966 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1967 icr = E1000_READ_REG(hw, E1000_ICR);
1969 kab = E1000_READ_REG(hw, E1000_KABGTXD);
1970 kab |= E1000_KABGTXD_BGSQLBIAS;
1971 E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
1977 * e1000_init_hw_ich8lan - Initialize the hardware
1978 * @hw: pointer to the HW structure
1980 * Prepares the hardware for transmit and receive by doing the following:
1981 * - initialize hardware bits
1982 * - initialize LED identification
1983 * - setup receive address registers
1984 * - setup flow control
1985 * - setup transmit descriptors
1986 * - clear statistics
1988 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1990 struct e1000_mac_info *mac = &hw->mac;
1991 u32 ctrl_ext, txdctl, snoop;
1995 DEBUGFUNC("e1000_init_hw_ich8lan");
1997 e1000_initialize_hw_bits_ich8lan(hw);
1999 /* Initialize identification LED */
2000 ret_val = e1000_id_led_init_generic(hw);
2002 DEBUGOUT("Error initializing identification LED\n");
2003 /* This is not fatal and we should not stop init due to this */
2006 /* Setup the receive address. */
2007 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2009 /* Zero out the Multicast HASH table */
2010 DEBUGOUT("Zeroing the MTA\n");
2011 for (i = 0; i < mac->mta_reg_count; i++)
2012 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2014 /* Setup link and flow control */
2015 ret_val = mac->ops.setup_link(hw);
2017 /* Set the transmit descriptor write-back policy for both queues */
2018 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2019 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2020 E1000_TXDCTL_FULL_TX_DESC_WB;
2021 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2022 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2023 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2024 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
2025 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2026 E1000_TXDCTL_FULL_TX_DESC_WB;
2027 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2028 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2029 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
2032 * ICH8 has opposite polarity of no_snoop bits.
2033 * By default, we should use snoop behavior.
2035 if (mac->type == e1000_ich8lan)
2036 snoop = PCIE_ICH8_SNOOP_ALL;
2038 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2039 e1000_set_pcie_no_snoop_generic(hw, snoop);
2041 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2042 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2043 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2046 * Clear all of the statistics registers (clear on read). It is
2047 * important that we do this after we have tried to establish link
2048 * because the symbol error count will increment wildly if there
2051 e1000_clear_hw_cntrs_ich8lan(hw);
2056 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2057 * @hw: pointer to the HW structure
2059 * Sets/Clears required hardware bits necessary for correctly setting up the
2060 * hardware for transmit and receive.
2062 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2066 DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2068 /* Extended Device Control */
2069 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2071 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2073 /* Transmit Descriptor Control 0 */
2074 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2076 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2078 /* Transmit Descriptor Control 1 */
2079 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2081 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2083 /* Transmit Arbitration Control 0 */
2084 reg = E1000_READ_REG(hw, E1000_TARC(0));
2085 if (hw->mac.type == e1000_ich8lan)
2086 reg |= (1 << 28) | (1 << 29);
2087 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2088 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2090 /* Transmit Arbitration Control 1 */
2091 reg = E1000_READ_REG(hw, E1000_TARC(1));
2092 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2096 reg |= (1 << 24) | (1 << 26) | (1 << 30);
2097 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2100 if (hw->mac.type == e1000_ich8lan) {
2101 reg = E1000_READ_REG(hw, E1000_STATUS);
2103 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2110 * e1000_setup_link_ich8lan - Setup flow control and link settings
2111 * @hw: pointer to the HW structure
2113 * Determines which flow control settings to use, then configures flow
2114 * control. Calls the appropriate media-specific link configuration
2115 * function. Assuming the adapter has a valid link partner, a valid link
2116 * should be established. Assumes the hardware has previously been reset
2117 * and the transmitter and receiver are not enabled.
2119 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2121 s32 ret_val = E1000_SUCCESS;
2123 DEBUGFUNC("e1000_setup_link_ich8lan");
2125 if (hw->phy.ops.check_reset_block(hw))
2129 * ICH parts do not have a word in the NVM to determine
2130 * the default flow control setting, so we explicitly
2133 if (hw->fc.requested_mode == e1000_fc_default)
2134 hw->fc.requested_mode = e1000_fc_full;
2137 * Save off the requested flow control mode for use later. Depending
2138 * on the link partner's capabilities, we may or may not use this mode.
2140 hw->fc.current_mode = hw->fc.requested_mode;
2142 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
2143 hw->fc.current_mode);
2145 /* Continue to configure the copper link. */
2146 ret_val = hw->mac.ops.setup_physical_interface(hw);
2150 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2152 ret_val = e1000_set_fc_watermarks_generic(hw);
2159 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2160 * @hw: pointer to the HW structure
2162 * Configures the kumeran interface to the PHY to wait the appropriate time
2163 * when polling the PHY, then call the generic setup_copper_link to finish
2164 * configuring the copper link.
2166 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2172 DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2174 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2175 ctrl |= E1000_CTRL_SLU;
2176 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2177 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2180 * Set the mac to wait the maximum time between each iteration
2181 * and increase the max iterations when polling the phy;
2182 * this fixes erroneous timeouts at 10Mbps.
2184 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4),
2188 ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
2193 ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
2198 if (hw->phy.type == e1000_phy_igp_3) {
2199 ret_val = e1000_copper_link_setup_igp(hw);
2202 } else if (hw->phy.type == e1000_phy_bm) {
2203 ret_val = e1000_copper_link_setup_m88(hw);
2208 if (hw->phy.type == e1000_phy_ife) {
2209 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2214 reg_data &= ~IFE_PMC_AUTO_MDIX;
2216 switch (hw->phy.mdix) {
2218 reg_data &= ~IFE_PMC_FORCE_MDIX;
2221 reg_data |= IFE_PMC_FORCE_MDIX;
2225 reg_data |= IFE_PMC_AUTO_MDIX;
2228 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2233 ret_val = e1000_setup_copper_link_generic(hw);
2240 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2241 * @hw: pointer to the HW structure
2242 * @speed: pointer to store current link speed
2243 * @duplex: pointer to store the current link duplex
2245 * Calls the generic get_speed_and_duplex to retrieve the current link
2246 * information and then calls the Kumeran lock loss workaround for links at
2249 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2254 DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2256 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2260 if ((hw->mac.type == e1000_ich8lan) &&
2261 (hw->phy.type == e1000_phy_igp_3) &&
2262 (*speed == SPEED_1000)) {
2263 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2271 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2272 * @hw: pointer to the HW structure
2274 * Work-around for 82566 Kumeran PCS lock loss:
2275 * On link status change (i.e. PCI reset, speed change) and link is up and
2277 * 0) if workaround is optionally disabled do nothing
2278 * 1) wait 1ms for Kumeran link to come up
2279 * 2) check Kumeran Diagnostic register PCS lock loss bit
2280 * 3) if not set the link is locked (all is good), otherwise...
2282 * 5) repeat up to 10 times
2283 * Note: this is only called for IGP3 copper when speed is 1gb.
2285 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2287 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2289 s32 ret_val = E1000_SUCCESS;
2293 DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2295 if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2299 * Make sure link is up before proceeding. If not just return.
2300 * Attempting this while link is negotiating fouled up link
2303 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2305 ret_val = E1000_SUCCESS;
2309 for (i = 0; i < 10; i++) {
2310 /* read once to clear */
2311 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2314 /* and again to get new status */
2315 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2319 /* check for PCS lock */
2320 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2321 ret_val = E1000_SUCCESS;
2325 /* Issue PHY reset */
2326 hw->phy.ops.reset(hw);
2329 /* Disable GigE link negotiation */
2330 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2331 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2332 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2333 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2336 * Call gig speed drop workaround on Gig disable before accessing
2339 e1000_gig_downshift_workaround_ich8lan(hw);
2341 /* unable to acquire PCS lock */
2342 ret_val = -E1000_ERR_PHY;
2349 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2350 * @hw: pointer to the HW structure
2351 * @state: boolean value used to set the current Kumeran workaround state
2353 * If ICH8, set the current Kumeran workaround state (enabled - TRUE
2354 * /disabled - FALSE).
2356 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2359 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2361 DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2363 if (hw->mac.type != e1000_ich8lan) {
2364 DEBUGOUT("Workaround applies to ICH8 only.\n");
2368 dev_spec->kmrn_lock_loss_workaround_enabled = state;
2374 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2375 * @hw: pointer to the HW structure
2377 * Workaround for 82566 power-down on D3 entry:
2378 * 1) disable gigabit link
2379 * 2) write VR power-down enable
2381 * Continue if successful, else issue LCD reset and repeat
2383 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2389 DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2391 if (hw->phy.type != e1000_phy_igp_3)
2394 /* Try the workaround twice (if needed) */
2397 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2398 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2399 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2400 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2403 * Call gig speed drop workaround on Gig disable before
2404 * accessing any PHY registers
2406 if (hw->mac.type == e1000_ich8lan)
2407 e1000_gig_downshift_workaround_ich8lan(hw);
2409 /* Write VR power-down enable */
2410 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2411 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2412 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
2413 data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2415 /* Read it back and test */
2416 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2417 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2418 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2421 /* Issue PHY reset and repeat at most one more time */
2422 reg = E1000_READ_REG(hw, E1000_CTRL);
2423 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2432 * e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2433 * @hw: pointer to the HW structure
2435 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2436 * LPLU, Gig disable, MDIC PHY reset):
2437 * 1) Set Kumeran Near-end loopback
2438 * 2) Clear Kumeran Near-end loopback
2439 * Should only be called for ICH8[m] devices with IGP_3 Phy.
2441 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2443 s32 ret_val = E1000_SUCCESS;
2446 DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2448 if ((hw->mac.type != e1000_ich8lan) ||
2449 (hw->phy.type != e1000_phy_igp_3))
2452 ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2456 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2457 ret_val = e1000_write_kmrn_reg_generic(hw,
2458 E1000_KMRNCTRLSTA_DIAG_OFFSET,
2462 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2463 ret_val = e1000_write_kmrn_reg_generic(hw,
2464 E1000_KMRNCTRLSTA_DIAG_OFFSET,
2471 * e1000_disable_gig_wol_ich8lan - disable gig during WoL
2472 * @hw: pointer to the HW structure
2474 * During S0 to Sx transition, it is possible the link remains at gig
2475 * instead of negotiating to a lower speed. Before going to Sx, set
2476 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2479 * Should only be called for ICH9 and ICH10 devices.
2481 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2485 if ((hw->mac.type == e1000_ich10lan) ||
2486 (hw->mac.type == e1000_ich9lan)) {
2487 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2488 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2489 E1000_PHY_CTRL_GBE_DISABLE;
2490 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2497 * e1000_cleanup_led_ich8lan - Restore the default LED operation
2498 * @hw: pointer to the HW structure
2500 * Return the LED back to the default configuration.
2502 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2504 s32 ret_val = E1000_SUCCESS;
2506 DEBUGFUNC("e1000_cleanup_led_ich8lan");
2508 if (hw->phy.type == e1000_phy_ife)
2509 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2512 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2518 * e1000_led_on_ich8lan - Turn LEDs on
2519 * @hw: pointer to the HW structure
2523 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2525 s32 ret_val = E1000_SUCCESS;
2527 DEBUGFUNC("e1000_led_on_ich8lan");
2529 if (hw->phy.type == e1000_phy_ife)
2530 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2531 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2533 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2539 * e1000_led_off_ich8lan - Turn LEDs off
2540 * @hw: pointer to the HW structure
2542 * Turn off the LEDs.
2544 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2546 s32 ret_val = E1000_SUCCESS;
2548 DEBUGFUNC("e1000_led_off_ich8lan");
2550 if (hw->phy.type == e1000_phy_ife)
2551 ret_val = hw->phy.ops.write_reg(hw,
2552 IFE_PHY_SPECIAL_CONTROL_LED,
2553 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2555 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2561 * e1000_get_cfg_done_ich8lan - Read config done bit
2562 * @hw: pointer to the HW structure
2564 * Read the management control register for the config done bit for
2565 * completion status. NOTE: silicon which is EEPROM-less will fail trying
2566 * to read the config done bit, so an error is *ONLY* logged and returns
2567 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
2568 * would not be able to be reset or change link.
2570 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2572 s32 ret_val = E1000_SUCCESS;
2575 e1000_get_cfg_done_generic(hw);
2577 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2578 if (hw->mac.type != e1000_ich10lan) {
2579 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2580 (hw->phy.type == e1000_phy_igp_3)) {
2581 e1000_phy_init_script_igp3(hw);
2584 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2585 /* Maybe we should do a basic PHY config */
2586 DEBUGOUT("EEPROM not present\n");
2587 ret_val = -E1000_ERR_CONFIG;
2595 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
2596 * @hw: pointer to the HW structure
2598 * In the case of a PHY power down to save power, or to turn off link during a
2599 * driver unload, or wake on lan is not enabled, remove the link.
2601 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
2603 /* If the management interface is not enabled, then power down */
2604 if (!(hw->mac.ops.check_mng_mode(hw) ||
2605 hw->phy.ops.check_reset_block(hw)))
2606 e1000_power_down_phy_copper(hw);
2612 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2613 * @hw: pointer to the HW structure
2615 * Clears hardware counters specific to the silicon family and calls
2616 * clear_hw_cntrs_generic to clear all general purpose counters.
2618 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2620 DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2622 e1000_clear_hw_cntrs_base_generic(hw);
2624 E1000_READ_REG(hw, E1000_ALGNERRC);
2625 E1000_READ_REG(hw, E1000_RXERRC);
2626 E1000_READ_REG(hw, E1000_TNCRS);
2627 E1000_READ_REG(hw, E1000_CEXTERR);
2628 E1000_READ_REG(hw, E1000_TSCTC);
2629 E1000_READ_REG(hw, E1000_TSCTFC);
2631 E1000_READ_REG(hw, E1000_MGTPRC);
2632 E1000_READ_REG(hw, E1000_MGTPDC);
2633 E1000_READ_REG(hw, E1000_MGTPTC);
2635 E1000_READ_REG(hw, E1000_IAC);
2636 E1000_READ_REG(hw, E1000_ICRXOC);