sys/dev/e1000/e1000_ich8lan.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2008, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82562G 10/100 Network Connection
  37  * 82562G-2 10/100 Network Connection
  38  * 82562GT 10/100 Network Connection
  39  * 82562GT-2 10/100 Network Connection
  40  * 82562V 10/100 Network Connection
  41  * 82562V-2 10/100 Network Connection
  42  * 82566DC-2 Gigabit Network Connection
  43  * 82566DC Gigabit Network Connection
  44  * 82566DM-2 Gigabit Network Connection
  45  * 82566DM Gigabit Network Connection
  46  * 82566MC Gigabit Network Connection
  47  * 82566MM Gigabit Network Connection
  48  * 82567LM Gigabit Network Connection
  49  * 82567LF Gigabit Network Connection
  50  * 82567V Gigabit Network Connection
  51  * 82567LM-2 Gigabit Network Connection
  52  * 82567LF-2 Gigabit Network Connection
  53  * 82567V-2 Gigabit Network Connection
  54  * 82567LF-3 Gigabit Network Connection
  55  * 82567LM-3 Gigabit Network Connection
  56  * 82567LM-4 Gigabit Network Connection
  57  */
  58
  59 #include "e1000_api.h"
  60
  61 static s32  e1000_init_phy_params_ich8lan(struct e1000_hw *hw);
  62 static s32  e1000_init_nvm_params_ich8lan(struct e1000_hw *hw);
  63 static s32  e1000_init_mac_params_ich8lan(struct e1000_hw *hw);
  64 static s32  e1000_acquire_swflag_ich8lan(struct e1000_hw *hw);
  65 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw);
  66 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
  67 static s32  e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
  68 static s32  e1000_check_reset_block_ich8lan(struct e1000_hw *hw);
  69 static s32  e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw);
  70 static s32  e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw);
  71 static s32  e1000_get_phy_info_ich8lan(struct e1000_hw *hw);
  72 static s32  e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw,
  73                                             bool active);
  74 static s32  e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw,
  75                                             bool active);
  76 static s32  e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  77                                    u16 words, u16 *data);
  78 static s32  e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset,
  79                                     u16 words, u16 *data);
  80 static s32  e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw);
  81 static s32  e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw);
  82 static s32  e1000_valid_led_default_ich8lan(struct e1000_hw *hw,
  83                                             u16 *data);
  84 static s32  e1000_get_bus_info_ich8lan(struct e1000_hw *hw);
  85 static s32  e1000_reset_hw_ich8lan(struct e1000_hw *hw);
  86 static s32  e1000_init_hw_ich8lan(struct e1000_hw *hw);
  87 static s32  e1000_setup_link_ich8lan(struct e1000_hw *hw);
  88 static s32  e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
  89 static s32  e1000_get_link_up_info_ich8lan(struct e1000_hw *hw,
  90                                            u16 *speed, u16 *duplex);
  91 static s32  e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
  92 static s32  e1000_led_on_ich8lan(struct e1000_hw *hw);
  93 static s32  e1000_led_off_ich8lan(struct e1000_hw *hw);
  94 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
  95 static s32  e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
  96 static s32  e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout);
  97 static s32  e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw);
  98 static s32  e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw);
  99 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 100 static s32  e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 101 static s32  e1000_read_flash_byte_ich8lan(struct e1000_hw *hw,
 102                                           u32 offset, u8 *data);
 103 static s32  e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 104                                           u8 size, u16 *data);
 105 static s32  e1000_read_flash_word_ich8lan(struct e1000_hw *hw,
 106                                           u32 offset, u16 *data);
 107 static s32  e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 108                                                  u32 offset, u8 byte);
 109 static s32  e1000_write_flash_byte_ich8lan(struct e1000_hw *hw,
 110                                            u32 offset, u8 data);
 111 static s32  e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 112                                            u8 size, u16 data);
 113 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 114 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 115
 116 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 117 /* Offset 04h HSFSTS */
 118 union ich8_hws_flash_status {
 119         struct ich8_hsfsts {
 120                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 121                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 122                 u16 dael       :1; /* bit 2 Direct Access error Log */
 123                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 124                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 125                 u16 reserved1  :2; /* bit 13:6 Reserved */
 126                 u16 reserved2  :6; /* bit 13:6 Reserved */
 127                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 128                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 129         } hsf_status;
 130         u16 regval;
 131 };
 132
 133 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 134 /* Offset 06h FLCTL */
 135 union ich8_hws_flash_ctrl {
 136         struct ich8_hsflctl {
 137                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 138                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 139                 u16 reserved   :5;   /* 7:3 Reserved  */
 140                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 141                 u16 flockdn    :6;   /* 15:10 Reserved */
 142         } hsf_ctrl;
 143         u16 regval;
 144 };
 145
 146 /* ICH Flash Region Access Permissions */
 147 union ich8_hws_flash_regacc {
 148         struct ich8_flracc {
 149                 u32 grra      :8; /* 0:7 GbE region Read Access */
 150                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 151                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 152                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 153         } hsf_flregacc;
 154         u16 regval;
 155 };
 156
 157 /**
 158  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 159  *  @hw: pointer to the HW structure
 160  *
 161  *  Initialize family-specific PHY parameters and function pointers.
 162  **/
 163 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 164 {
 165         struct e1000_phy_info *phy = &hw->phy;
 166         s32 ret_val = E1000_SUCCESS;
 167         u16 i = 0;
 168
 169         DEBUGFUNC("e1000_init_phy_params_ich8lan");
 170
 171         phy->addr                     = 1;
 172         phy->reset_delay_us           = 100;
 173
 174         phy->ops.acquire              = e1000_acquire_swflag_ich8lan;
 175         phy->ops.check_polarity       = e1000_check_polarity_ife_ich8lan;
 176         phy->ops.check_reset_block    = e1000_check_reset_block_ich8lan;
 177         phy->ops.force_speed_duplex   = e1000_phy_force_speed_duplex_ich8lan;
 178         phy->ops.get_cable_length     = e1000_get_cable_length_igp_2;
 179         phy->ops.get_cfg_done         = e1000_get_cfg_done_ich8lan;
 180         phy->ops.get_info             = e1000_get_phy_info_ich8lan;
 181         phy->ops.read_reg             = e1000_read_phy_reg_igp;
 182         phy->ops.release              = e1000_release_swflag_ich8lan;
 183         phy->ops.reset                = e1000_phy_hw_reset_ich8lan;
 184         phy->ops.set_d0_lplu_state    = e1000_set_d0_lplu_state_ich8lan;
 185         phy->ops.set_d3_lplu_state    = e1000_set_d3_lplu_state_ich8lan;
 186         phy->ops.write_reg            = e1000_write_phy_reg_igp;
 187         phy->ops.power_up             = e1000_power_up_phy_copper;
 188         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 189
 190         /*
 191          * We may need to do this twice - once for IGP and if that fails,
 192          * we'll set BM func pointers and try again
 193          */
 194         ret_val = e1000_determine_phy_address(hw);
 195         if (ret_val) {
 196                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 197                 phy->ops.read_reg  = e1000_read_phy_reg_bm;
 198                 ret_val = e1000_determine_phy_address(hw);
 199                 if (ret_val) {
 200                         DEBUGOUT("Cannot determine PHY address. Erroring out\n");
 201                         goto out;
 202                 }
 203         }
 204
 205         phy->id = 0;
 206         while ((e1000_phy_unknown == e1000_get_phy_type_from_id(phy->id)) &&
 207                (i++ < 100)) {
 208                 msec_delay(1);
 209                 ret_val = e1000_get_phy_id(hw);
 210                 if (ret_val)
 211                         goto out;
 212         }
 213
 214         /* Verify phy id */
 215         switch (phy->id) {
 216         case IGP03E1000_E_PHY_ID:
 217                 phy->type = e1000_phy_igp_3;
 218                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 219                 break;
 220         case IFE_E_PHY_ID:
 221         case IFE_PLUS_E_PHY_ID:
 222         case IFE_C_E_PHY_ID:
 223                 phy->type = e1000_phy_ife;
 224                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 225                 break;
 226         case BME1000_E_PHY_ID:
 227                 phy->type = e1000_phy_bm;
 228                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 229                 phy->ops.read_reg = e1000_read_phy_reg_bm;
 230                 phy->ops.write_reg = e1000_write_phy_reg_bm;
 231                 phy->ops.commit = e1000_phy_sw_reset_generic;
 232                 break;
 233         default:
 234                 ret_val = -E1000_ERR_PHY;
 235                 goto out;
 236         }
 237
 238 out:
 239         return ret_val;
 240 }
 241
 242 /**
 243  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 244  *  @hw: pointer to the HW structure
 245  *
 246  *  Initialize family-specific NVM parameters and function
 247  *  pointers.
 248  **/
 249 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 250 {
 251         struct e1000_nvm_info *nvm = &hw->nvm;
 252         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 253         u32 gfpreg, sector_base_addr, sector_end_addr;
 254         s32 ret_val = E1000_SUCCESS;
 255         u16 i;
 256
 257         DEBUGFUNC("e1000_init_nvm_params_ich8lan");
 258
 259         /* Can't read flash registers if the register set isn't mapped. */
 260         if (!hw->flash_address) {
 261                 DEBUGOUT("ERROR: Flash registers not mapped\n");
 262                 ret_val = -E1000_ERR_CONFIG;
 263                 goto out;
 264         }
 265
 266         nvm->type = e1000_nvm_flash_sw;
 267
 268         gfpreg = E1000_READ_FLASH_REG(hw, ICH_FLASH_GFPREG);
 269
 270         /*
 271          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 272          * Add 1 to sector_end_addr since this sector is included in
 273          * the overall size.
 274          */
 275         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 276         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 277
 278         /* flash_base_addr is byte-aligned */
 279         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 280
 281         /*
 282          * find total size of the NVM, then cut in half since the total
 283          * size represents two separate NVM banks.
 284          */
 285         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 286                                   << FLASH_SECTOR_ADDR_SHIFT;
 287         nvm->flash_bank_size /= 2;
 288         /* Adjust to word count */
 289         nvm->flash_bank_size /= sizeof(u16);
 290
 291         nvm->word_size = E1000_SHADOW_RAM_WORDS;
 292
 293         /* Clear shadow ram */
 294         for (i = 0; i < nvm->word_size; i++) {
 295                 dev_spec->shadow_ram[i].modified = FALSE;
 296                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 297         }
 298
 299         /* Function Pointers */
 300         nvm->ops.acquire       = e1000_acquire_swflag_ich8lan;
 301         nvm->ops.read          = e1000_read_nvm_ich8lan;
 302         nvm->ops.release       = e1000_release_swflag_ich8lan;
 303         nvm->ops.update        = e1000_update_nvm_checksum_ich8lan;
 304         nvm->ops.valid_led_default = e1000_valid_led_default_ich8lan;
 305         nvm->ops.validate      = e1000_validate_nvm_checksum_ich8lan;
 306         nvm->ops.write         = e1000_write_nvm_ich8lan;
 307
 308 out:
 309         return ret_val;
 310 }
 311
 312 /**
 313  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 314  *  @hw: pointer to the HW structure
 315  *
 316  *  Initialize family-specific MAC parameters and function
 317  *  pointers.
 318  **/
 319 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 320 {
 321         struct e1000_mac_info *mac = &hw->mac;
 322
 323         DEBUGFUNC("e1000_init_mac_params_ich8lan");
 324
 325         /* Set media type function pointer */
 326         hw->phy.media_type = e1000_media_type_copper;
 327
 328         /* Set mta register count */
 329         mac->mta_reg_count = 32;
 330         /* Set rar entry count */
 331         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 332         if (mac->type == e1000_ich8lan)
 333                 mac->rar_entry_count--;
 334         /* Set if part includes ASF firmware */
 335         mac->asf_firmware_present = TRUE;
 336         /* Set if manageability features are enabled. */
 337         mac->arc_subsystem_valid = TRUE;
 338
 339         /* Function pointers */
 340
 341         /* bus type/speed/width */
 342         mac->ops.get_bus_info = e1000_get_bus_info_ich8lan;
 343         /* function id */
 344         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 345         /* reset */
 346         mac->ops.reset_hw = e1000_reset_hw_ich8lan;
 347         /* hw initialization */
 348         mac->ops.init_hw = e1000_init_hw_ich8lan;
 349         /* link setup */
 350         mac->ops.setup_link = e1000_setup_link_ich8lan;
 351         /* physical interface setup */
 352         mac->ops.setup_physical_interface = e1000_setup_copper_link_ich8lan;
 353         /* check for link */
 354         mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 355         /* check management mode */
 356         mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 357         /* link info */
 358         mac->ops.get_link_up_info = e1000_get_link_up_info_ich8lan;
 359         /* multicast address update */
 360         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 361         /* setting MTA */
 362         mac->ops.mta_set = e1000_mta_set_generic;
 363         /* blink LED */
 364         mac->ops.blink_led = e1000_blink_led_generic;
 365         /* setup LED */
 366         mac->ops.setup_led = e1000_setup_led_generic;
 367         /* cleanup LED */
 368         mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 369         /* turn on/off LED */
 370         mac->ops.led_on = e1000_led_on_ich8lan;
 371         mac->ops.led_off = e1000_led_off_ich8lan;
 372         /* clear hardware counters */
 373         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan;
 374
 375         /* Enable PCS Lock-loss workaround for ICH8 */
 376         if (mac->type == e1000_ich8lan)
 377                 e1000_set_kmrn_lock_loss_workaround_ich8lan(hw, TRUE);
 378
 379
 380         return E1000_SUCCESS;
 381 }
 382
 383 /**
 384  *  e1000_init_function_pointers_ich8lan - Initialize ICH8 function pointers
 385  *  @hw: pointer to the HW structure
 386  *
 387  *  Initialize family-specific function pointers for PHY, MAC, and NVM.
 388  **/
 389 void e1000_init_function_pointers_ich8lan(struct e1000_hw *hw)
 390 {
 391         DEBUGFUNC("e1000_init_function_pointers_ich8lan");
 392
 393         hw->mac.ops.init_params = e1000_init_mac_params_ich8lan;
 394         hw->nvm.ops.init_params = e1000_init_nvm_params_ich8lan;
 395         hw->phy.ops.init_params = e1000_init_phy_params_ich8lan;
 396 }
 397
 398 /**
 399  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 400  *  @hw: pointer to the HW structure
 401  *
 402  *  Acquires the software control flag for performing NVM and PHY
 403  *  operations.  This is a function pointer entry point only called by
 404  *  read/write routines for the PHY and NVM parts.
 405  **/
 406 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 407 {
 408         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 409         s32 ret_val = E1000_SUCCESS;
 410
 411         DEBUGFUNC("e1000_acquire_swflag_ich8lan");
 412
 413         while (timeout) {
 414                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 415                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 416                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 417
 418                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 419                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 420                         break;
 421                 msec_delay_irq(1);
 422                 timeout--;
 423         }
 424
 425         if (!timeout) {
 426                 DEBUGOUT("FW or HW has locked the resource for too long.\n");
 427                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 428                 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 429                 ret_val = -E1000_ERR_CONFIG;
 430                 goto out;
 431         }
 432
 433 out:
 434         return ret_val;
 435 }
 436
 437 /**
 438  *  e1000_release_swflag_ich8lan - Release software control flag
 439  *  @hw: pointer to the HW structure
 440  *
 441  *  Releases the software control flag for performing NVM and PHY operations.
 442  *  This is a function pointer entry point only called by read/write
 443  *  routines for the PHY and NVM parts.
 444  **/
 445 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 446 {
 447         u32 extcnf_ctrl;
 448
 449         DEBUGFUNC("e1000_release_swflag_ich8lan");
 450
 451         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 452         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 453         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 454
 455         return;
 456 }
 457
 458 /**
 459  *  e1000_check_mng_mode_ich8lan - Checks management mode
 460  *  @hw: pointer to the HW structure
 461  *
 462  *  This checks if the adapter has manageability enabled.
 463  *  This is a function pointer entry point only called by read/write
 464  *  routines for the PHY and NVM parts.
 465  **/
 466 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 467 {
 468         u32 fwsm;
 469
 470         DEBUGFUNC("e1000_check_mng_mode_ich8lan");
 471
 472         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 473
 474         return (fwsm & E1000_FWSM_MODE_MASK) ==
 475                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 476 }
 477
 478 /**
 479  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 480  *  @hw: pointer to the HW structure
 481  *
 482  *  Checks if firmware is blocking the reset of the PHY.
 483  *  This is a function pointer entry point only called by
 484  *  reset routines.
 485  **/
 486 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 487 {
 488         u32 fwsm;
 489
 490         DEBUGFUNC("e1000_check_reset_block_ich8lan");
 491
 492         fwsm = E1000_READ_REG(hw, E1000_FWSM);
 493
 494         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS
 495                                                 : E1000_BLK_PHY_RESET;
 496 }
 497
 498 /**
 499  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 500  *  @hw: pointer to the HW structure
 501  *
 502  *  Forces the speed and duplex settings of the PHY.
 503  *  This is a function pointer entry point only called by
 504  *  PHY setup routines.
 505  **/
 506 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 507 {
 508         struct e1000_phy_info *phy = &hw->phy;
 509         s32 ret_val;
 510         u16 data;
 511         bool link;
 512
 513         DEBUGFUNC("e1000_phy_force_speed_duplex_ich8lan");
 514
 515         if (phy->type != e1000_phy_ife) {
 516                 ret_val = e1000_phy_force_speed_duplex_igp(hw);
 517                 goto out;
 518         }
 519
 520         ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
 521         if (ret_val)
 522                 goto out;
 523
 524         e1000_phy_force_speed_duplex_setup(hw, &data);
 525
 526         ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
 527         if (ret_val)
 528                 goto out;
 529
 530         /* Disable MDI-X support for 10/100 */
 531         ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
 532         if (ret_val)
 533                 goto out;
 534
 535         data &= ~IFE_PMC_AUTO_MDIX;
 536         data &= ~IFE_PMC_FORCE_MDIX;
 537
 538         ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
 539         if (ret_val)
 540                 goto out;
 541
 542         DEBUGOUT1("IFE PMC: %X\n", data);
 543
 544         usec_delay(1);
 545
 546         if (phy->autoneg_wait_to_complete) {
 547                 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
 548
 549                 ret_val = e1000_phy_has_link_generic(hw,
 550                                                      PHY_FORCE_LIMIT,
 551                                                      100000,
 552                                                      &link);
 553                 if (ret_val)
 554                         goto out;
 555
 556                 if (!link)
 557                         DEBUGOUT("Link taking longer than expected.\n");
 558
 559                 /* Try once more */
 560                 ret_val = e1000_phy_has_link_generic(hw,
 561                                                      PHY_FORCE_LIMIT,
 562                                                      100000,
 563                                                      &link);
 564                 if (ret_val)
 565                         goto out;
 566         }
 567
 568 out:
 569         return ret_val;
 570 }
 571
 572 /**
 573  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 574  *  @hw: pointer to the HW structure
 575  *
 576  *  Resets the PHY
 577  *  This is a function pointer entry point called by drivers
 578  *  or other shared routines.
 579  **/
 580 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 581 {
 582         struct e1000_phy_info *phy = &hw->phy;
 583         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 584         s32 ret_val;
 585         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 586         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 587
 588         DEBUGFUNC("e1000_phy_hw_reset_ich8lan");
 589
 590         ret_val = e1000_phy_hw_reset_generic(hw);
 591         if (ret_val)
 592                 goto out;
 593
 594         /*
 595          * Initialize the PHY from the NVM on ICH platforms.  This
 596          * is needed due to an issue where the NVM configuration is
 597          * not properly autoloaded after power transitions.
 598          * Therefore, after each PHY reset, we will load the
 599          * configuration data out of the NVM manually.
 600          */
 601         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 602                 /* Check if SW needs configure the PHY */
 603                 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 604                     (hw->device_id == E1000_DEV_ID_ICH8_IGP_M))
 605                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 606                 else
 607                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 608
 609                 data = E1000_READ_REG(hw, E1000_FEXTNVM);
 610                 if (!(data & sw_cfg_mask))
 611                         goto out;
 612
 613                 /* Wait for basic configuration completes before proceeding*/
 614                 do {
 615                         data = E1000_READ_REG(hw, E1000_STATUS);
 616                         data &= E1000_STATUS_LAN_INIT_DONE;
 617                         usec_delay(100);
 618                 } while ((!data) && --loop);
 619
 620                 /*
 621                  * If basic configuration is incomplete before the above loop
 622                  * count reaches 0, loading the configuration from NVM will
 623                  * leave the PHY in a bad state possibly resulting in no link.
 624                  */
 625                 if (loop == 0)
 626                         DEBUGOUT("LAN_INIT_DONE not set, increase timeout\n");
 627
 628                 /* Clear the Init Done bit for the next init event */
 629                 data = E1000_READ_REG(hw, E1000_STATUS);
 630                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 631                 E1000_WRITE_REG(hw, E1000_STATUS, data);
 632
 633                 /*
 634                  * Make sure HW does not configure LCD from PHY
 635                  * extended configuration before SW configuration
 636                  */
 637                 data = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 638                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 639                         goto out;
 640
 641                 cnf_size = E1000_READ_REG(hw, E1000_EXTCNF_SIZE);
 642                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 643                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 644                 if (!cnf_size)
 645                         goto out;
 646
 647                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 648                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 649
 650                 /* Configure LCD from extended configuration region. */
 651
 652                 /* cnf_base_addr is in DWORD */
 653                 word_addr = (u16)(cnf_base_addr << 1);
 654
 655                 for (i = 0; i < cnf_size; i++) {
 656                         ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2), 1,
 657                                                    &reg_data);
 658                         if (ret_val)
 659                                 goto out;
 660
 661                         ret_val = hw->nvm.ops.read(hw, (word_addr + i * 2 + 1),
 662                                                    1, &reg_addr);
 663                         if (ret_val)
 664                                 goto out;
 665
 666                         /* Save off the PHY page for future writes. */
 667                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 668                                 phy_page = reg_data;
 669                                 continue;
 670                         }
 671
 672                         reg_addr |= phy_page;
 673
 674                         ret_val = phy->ops.write_reg(hw, (u32)reg_addr, reg_data);
 675                         if (ret_val)
 676                                 goto out;
 677                 }
 678         }
 679
 680 out:
 681         return ret_val;
 682 }
 683
 684 /**
 685  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 686  *  @hw: pointer to the HW structure
 687  *
 688  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 689  **/
 690 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 691 {
 692         s32 ret_val = -E1000_ERR_PHY_TYPE;
 693
 694         DEBUGFUNC("e1000_get_phy_info_ich8lan");
 695
 696         switch (hw->phy.type) {
 697         case e1000_phy_ife:
 698                 ret_val = e1000_get_phy_info_ife_ich8lan(hw);
 699                 break;
 700         case e1000_phy_igp_3:
 701         case e1000_phy_bm:
 702                 ret_val = e1000_get_phy_info_igp(hw);
 703                 break;
 704         default:
 705                 break;
 706         }
 707
 708         return ret_val;
 709 }
 710
 711 /**
 712  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 713  *  @hw: pointer to the HW structure
 714  *
 715  *  Populates "phy" structure with various feature states.
 716  *  This function is only called by other family-specific
 717  *  routines.
 718  **/
 719 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 720 {
 721         struct e1000_phy_info *phy = &hw->phy;
 722         s32 ret_val;
 723         u16 data;
 724         bool link;
 725
 726         DEBUGFUNC("e1000_get_phy_info_ife_ich8lan");
 727
 728         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 729         if (ret_val)
 730                 goto out;
 731
 732         if (!link) {
 733                 DEBUGOUT("Phy info is only valid if link is up\n");
 734                 ret_val = -E1000_ERR_CONFIG;
 735                 goto out;
 736         }
 737
 738         ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 739         if (ret_val)
 740                 goto out;
 741         phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
 742                                    ? FALSE : TRUE;
 743
 744         if (phy->polarity_correction) {
 745                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 746                 if (ret_val)
 747                         goto out;
 748         } else {
 749                 /* Polarity is forced */
 750                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 751                                       ? e1000_rev_polarity_reversed
 752                                       : e1000_rev_polarity_normal;
 753         }
 754
 755         ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
 756         if (ret_val)
 757                 goto out;
 758
 759         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
 760
 761         /* The following parameters are undefined for 10/100 operation. */
 762         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 763         phy->local_rx = e1000_1000t_rx_status_undefined;
 764         phy->remote_rx = e1000_1000t_rx_status_undefined;
 765
 766 out:
 767         return ret_val;
 768 }
 769
 770 /**
 771  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 772  *  @hw: pointer to the HW structure
 773  *
 774  *  Polarity is determined on the polarity reversal feature being enabled.
 775  *  This function is only called by other family-specific
 776  *  routines.
 777  **/
 778 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 779 {
 780         struct e1000_phy_info *phy = &hw->phy;
 781         s32 ret_val;
 782         u16 phy_data, offset, mask;
 783
 784         DEBUGFUNC("e1000_check_polarity_ife_ich8lan");
 785
 786         /*
 787          * Polarity is determined based on the reversal feature being enabled.
 788          */
 789         if (phy->polarity_correction) {
 790                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 791                 mask    = IFE_PESC_POLARITY_REVERSED;
 792         } else {
 793                 offset  = IFE_PHY_SPECIAL_CONTROL;
 794                 mask    = IFE_PSC_FORCE_POLARITY;
 795         }
 796
 797         ret_val = phy->ops.read_reg(hw, offset, &phy_data);
 798
 799         if (!ret_val)
 800                 phy->cable_polarity = (phy_data & mask)
 801                                       ? e1000_rev_polarity_reversed
 802                                       : e1000_rev_polarity_normal;
 803
 804         return ret_val;
 805 }
 806
 807 /**
 808  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 809  *  @hw: pointer to the HW structure
 810  *  @active: TRUE to enable LPLU, FALSE to disable
 811  *
 812  *  Sets the LPLU D0 state according to the active flag.  When
 813  *  activating LPLU this function also disables smart speed
 814  *  and vice versa.  LPLU will not be activated unless the
 815  *  device autonegotiation advertisement meets standards of
 816  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 817  *  This is a function pointer entry point only called by
 818  *  PHY setup routines.
 819  **/
 820 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 821 {
 822         struct e1000_phy_info *phy = &hw->phy;
 823         u32 phy_ctrl;
 824         s32 ret_val = E1000_SUCCESS;
 825         u16 data;
 826
 827         DEBUGFUNC("e1000_set_d0_lplu_state_ich8lan");
 828
 829         if (phy->type == e1000_phy_ife)
 830                 goto out;
 831
 832         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
 833
 834         if (active) {
 835                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 836                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 837
 838                 /*
 839                  * Call gig speed drop workaround on LPLU before accessing
 840                  * any PHY registers
 841                  */
 842                 if ((hw->mac.type == e1000_ich8lan) &&
 843                     (hw->phy.type == e1000_phy_igp_3))
 844                         e1000_gig_downshift_workaround_ich8lan(hw);
 845
 846                 /* When LPLU is enabled, we should disable SmartSpeed */
 847                 ret_val = phy->ops.read_reg(hw,
 848                                             IGP01E1000_PHY_PORT_CONFIG,
 849                                             &data);
 850                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 851                 ret_val = phy->ops.write_reg(hw,
 852                                              IGP01E1000_PHY_PORT_CONFIG,
 853                                              data);
 854                 if (ret_val)
 855                         goto out;
 856         } else {
 857                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 858                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 859
 860                 /*
 861                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 862                  * during Dx states where the power conservation is most
 863                  * important.  During driver activity we should enable
 864                  * SmartSpeed, so performance is maintained.
 865                  */
 866                 if (phy->smart_speed == e1000_smart_speed_on) {
 867                         ret_val = phy->ops.read_reg(hw,
 868                                                     IGP01E1000_PHY_PORT_CONFIG,
 869                                                     &data);
 870                         if (ret_val)
 871                                 goto out;
 872
 873                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 874                         ret_val = phy->ops.write_reg(hw,
 875                                                      IGP01E1000_PHY_PORT_CONFIG,
 876                                                      data);
 877                         if (ret_val)
 878                                 goto out;
 879                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 880                         ret_val = phy->ops.read_reg(hw,
 881                                                     IGP01E1000_PHY_PORT_CONFIG,
 882                                                     &data);
 883                         if (ret_val)
 884                                 goto out;
 885
 886                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 887                         ret_val = phy->ops.write_reg(hw,
 888                                                      IGP01E1000_PHY_PORT_CONFIG,
 889                                                      data);
 890                         if (ret_val)
 891                                 goto out;
 892                 }
 893         }
 894
 895 out:
 896         return ret_val;
 897 }
 898
 899 /**
 900  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 901  *  @hw: pointer to the HW structure
 902  *  @active: TRUE to enable LPLU, FALSE to disable
 903  *
 904  *  Sets the LPLU D3 state according to the active flag.  When
 905  *  activating LPLU this function also disables smart speed
 906  *  and vice versa.  LPLU will not be activated unless the
 907  *  device autonegotiation advertisement meets standards of
 908  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 909  *  This is a function pointer entry point only called by
 910  *  PHY setup routines.
 911  **/
 912 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 913 {
 914         struct e1000_phy_info *phy = &hw->phy;
 915         u32 phy_ctrl;
 916         s32 ret_val = E1000_SUCCESS;
 917         u16 data;
 918
 919         DEBUGFUNC("e1000_set_d3_lplu_state_ich8lan");
 920
 921         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
 922
 923         if (!active) {
 924                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 925                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 926                 /*
 927                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 928                  * during Dx states where the power conservation is most
 929                  * important.  During driver activity we should enable
 930                  * SmartSpeed, so performance is maintained.
 931                  */
 932                 if (phy->smart_speed == e1000_smart_speed_on) {
 933                         ret_val = phy->ops.read_reg(hw,
 934                                                     IGP01E1000_PHY_PORT_CONFIG,
 935                                                     &data);
 936                         if (ret_val)
 937                                 goto out;
 938
 939                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 940                         ret_val = phy->ops.write_reg(hw,
 941                                                      IGP01E1000_PHY_PORT_CONFIG,
 942                                                      data);
 943                         if (ret_val)
 944                                 goto out;
 945                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 946                         ret_val = phy->ops.read_reg(hw,
 947                                                     IGP01E1000_PHY_PORT_CONFIG,
 948                                                     &data);
 949                         if (ret_val)
 950                                 goto out;
 951
 952                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 953                         ret_val = phy->ops.write_reg(hw,
 954                                                      IGP01E1000_PHY_PORT_CONFIG,
 955                                                      data);
 956                         if (ret_val)
 957                                 goto out;
 958                 }
 959         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 960                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 961                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 962                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 963                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
 964
 965                 /*
 966                  * Call gig speed drop workaround on LPLU before accessing
 967                  * any PHY registers
 968                  */
 969                 if ((hw->mac.type == e1000_ich8lan) &&
 970                     (hw->phy.type == e1000_phy_igp_3))
 971                         e1000_gig_downshift_workaround_ich8lan(hw);
 972
 973                 /* When LPLU is enabled, we should disable SmartSpeed */
 974                 ret_val = phy->ops.read_reg(hw,
 975                                             IGP01E1000_PHY_PORT_CONFIG,
 976                                             &data);
 977                 if (ret_val)
 978                         goto out;
 979
 980                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 981                 ret_val = phy->ops.write_reg(hw,
 982                                              IGP01E1000_PHY_PORT_CONFIG,
 983                                              data);
 984         }
 985
 986 out:
 987         return ret_val;
 988 }
 989
 990 /**
 991  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 992  *  @hw: pointer to the HW structure
 993  *  @bank:  pointer to the variable that returns the active bank
 994  *
 995  *  Reads signature byte from the NVM using the flash access registers.
 996  **/
 997 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 998 {
 999         s32 ret_val = E1000_SUCCESS;
1000         struct e1000_nvm_info *nvm = &hw->nvm;
1001         /* flash bank size is in words */
1002         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1003         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1004         u8 bank_high_byte = 0;
1005
1006         if (hw->mac.type != e1000_ich10lan) {
1007                 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_SEC1VAL)
1008                         *bank = 1;
1009                 else
1010                         *bank = 0;
1011         } else {
1012                 /*
1013                  * Make sure the signature for bank 0 is valid,
1014                  * if not check for bank1
1015                  */
1016                 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
1017                 if ((bank_high_byte & 0xC0) == 0x80) {
1018                         *bank = 0;
1019                 } else {
1020                         /*
1021                          * find if segment 1 is valid by verifying
1022                          * bit 15:14 = 10b in word 0x13
1023                          */
1024                         e1000_read_flash_byte_ich8lan(hw,
1025                                                       act_offset + bank1_offset,
1026                                                       &bank_high_byte);
1027
1028                         /* bank1 has a valid signature equivalent to SEC1V */
1029                         if ((bank_high_byte & 0xC0) == 0x80) {
1030                                 *bank = 1;
1031                         } else {
1032                                 DEBUGOUT("ERROR: EEPROM not present\n");
1033                                 ret_val = -E1000_ERR_NVM;
1034                         }
1035                 }
1036         }
1037
1038         return ret_val;
1039 }
1040
1041 /**
1042  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1043  *  @hw: pointer to the HW structure
1044  *  @offset: The offset (in bytes) of the word(s) to read.
1045  *  @words: Size of data to read in words
1046  *  @data: Pointer to the word(s) to read at offset.
1047  *
1048  *  Reads a word(s) from the NVM using the flash access registers.
1049  **/
1050 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1051                                   u16 *data)
1052 {
1053         struct e1000_nvm_info *nvm = &hw->nvm;
1054         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1055         u32 act_offset;
1056         s32 ret_val = E1000_SUCCESS;
1057         u32 bank = 0;
1058         u16 i, word;
1059
1060         DEBUGFUNC("e1000_read_nvm_ich8lan");
1061
1062         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1063             (words == 0)) {
1064                 DEBUGOUT("nvm parameter(s) out of bounds\n");
1065                 ret_val = -E1000_ERR_NVM;
1066                 goto out;
1067         }
1068
1069         ret_val = nvm->ops.acquire(hw);
1070         if (ret_val)
1071                 goto out;
1072
1073         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1074         if (ret_val != E1000_SUCCESS)
1075                 goto out;
1076
1077         act_offset = (bank) ? nvm->flash_bank_size : 0;
1078         act_offset += offset;
1079
1080         for (i = 0; i < words; i++) {
1081                 if ((dev_spec->shadow_ram) &&
1082                     (dev_spec->shadow_ram[offset+i].modified)) {
1083                         data[i] = dev_spec->shadow_ram[offset+i].value;
1084                 } else {
1085                         ret_val = e1000_read_flash_word_ich8lan(hw,
1086                                                                 act_offset + i,
1087                                                                 &word);
1088                         if (ret_val)
1089                                 break;
1090                         data[i] = word;
1091                 }
1092         }
1093
1094         nvm->ops.release(hw);
1095
1096 out:
1097         return ret_val;
1098 }
1099
1100 /**
1101  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1102  *  @hw: pointer to the HW structure
1103  *
1104  *  This function does initial flash setup so that a new read/write/erase cycle
1105  *  can be started.
1106  **/
1107 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1108 {
1109         union ich8_hws_flash_status hsfsts;
1110         s32 ret_val = -E1000_ERR_NVM;
1111         s32 i = 0;
1112
1113         DEBUGFUNC("e1000_flash_cycle_init_ich8lan");
1114
1115         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1116
1117         /* Check if the flash descriptor is valid */
1118         if (hsfsts.hsf_status.fldesvalid == 0) {
1119                 DEBUGOUT("Flash descriptor invalid.  "
1120                          "SW Sequencing must be used.");
1121                 goto out;
1122         }
1123
1124         /* Clear FCERR and DAEL in hw status by writing 1 */
1125         hsfsts.hsf_status.flcerr = 1;
1126         hsfsts.hsf_status.dael = 1;
1127
1128         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1129
1130         /*
1131          * Either we should have a hardware SPI cycle in progress
1132          * bit to check against, in order to start a new cycle or
1133          * FDONE bit should be changed in the hardware so that it
1134          * is 1 after hardware reset, which can then be used as an
1135          * indication whether a cycle is in progress or has been
1136          * completed.
1137          */
1138
1139         if (hsfsts.hsf_status.flcinprog == 0) {
1140                 /*
1141                  * There is no cycle running at present,
1142                  * so we can start a cycle.
1143                  * Begin by setting Flash Cycle Done.
1144                  */
1145                 hsfsts.hsf_status.flcdone = 1;
1146                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
1147                 ret_val = E1000_SUCCESS;
1148         } else {
1149                 /*
1150                  * Otherwise poll for sometime so the current
1151                  * cycle has a chance to end before giving up.
1152                  */
1153                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1154                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1155                                                               ICH_FLASH_HSFSTS);
1156                         if (hsfsts.hsf_status.flcinprog == 0) {
1157                                 ret_val = E1000_SUCCESS;
1158                                 break;
1159                         }
1160                         usec_delay(1);
1161                 }
1162                 if (ret_val == E1000_SUCCESS) {
1163                         /*
1164                          * Successful in waiting for previous cycle to timeout,
1165                          * now set the Flash Cycle Done.
1166                          */
1167                         hsfsts.hsf_status.flcdone = 1;
1168                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFSTS,
1169                                                 hsfsts.regval);
1170                 } else {
1171                         DEBUGOUT("Flash controller busy, cannot get access");
1172                 }
1173         }
1174
1175 out:
1176         return ret_val;
1177 }
1178
1179 /**
1180  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1181  *  @hw: pointer to the HW structure
1182  *  @timeout: maximum time to wait for completion
1183  *
1184  *  This function starts a flash cycle and waits for its completion.
1185  **/
1186 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1187 {
1188         union ich8_hws_flash_ctrl hsflctl;
1189         union ich8_hws_flash_status hsfsts;
1190         s32 ret_val = -E1000_ERR_NVM;
1191         u32 i = 0;
1192
1193         DEBUGFUNC("e1000_flash_cycle_ich8lan");
1194
1195         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1196         hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1197         hsflctl.hsf_ctrl.flcgo = 1;
1198         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1199
1200         /* wait till FDONE bit is set to 1 */
1201         do {
1202                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1203                 if (hsfsts.hsf_status.flcdone == 1)
1204                         break;
1205                 usec_delay(1);
1206         } while (i++ < timeout);
1207
1208         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1209                 ret_val = E1000_SUCCESS;
1210
1211         return ret_val;
1212 }
1213
1214 /**
1215  *  e1000_read_flash_word_ich8lan - Read word from flash
1216  *  @hw: pointer to the HW structure
1217  *  @offset: offset to data location
1218  *  @data: pointer to the location for storing the data
1219  *
1220  *  Reads the flash word at offset into data.  Offset is converted
1221  *  to bytes before read.
1222  **/
1223 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1224                                          u16 *data)
1225 {
1226         s32 ret_val;
1227
1228         DEBUGFUNC("e1000_read_flash_word_ich8lan");
1229
1230         if (!data) {
1231                 ret_val = -E1000_ERR_NVM;
1232                 goto out;
1233         }
1234
1235         /* Must convert offset into bytes. */
1236         offset <<= 1;
1237
1238         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1239
1240 out:
1241         return ret_val;
1242 }
1243
1244 /**
1245  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1246  *  @hw: pointer to the HW structure
1247  *  @offset: The offset of the byte to read.
1248  *  @data: Pointer to a byte to store the value read.
1249  *
1250  *  Reads a single byte from the NVM using the flash access registers.
1251  **/
1252 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1253                                          u8 *data)
1254 {
1255         s32 ret_val = E1000_SUCCESS;
1256         u16 word = 0;
1257
1258         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1259         if (ret_val)
1260                 goto out;
1261
1262         *data = (u8)word;
1263
1264 out:
1265         return ret_val;
1266 }
1267
1268 /**
1269  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1270  *  @hw: pointer to the HW structure
1271  *  @offset: The offset (in bytes) of the byte or word to read.
1272  *  @size: Size of data to read, 1=byte 2=word
1273  *  @data: Pointer to the word to store the value read.
1274  *
1275  *  Reads a byte or word from the NVM using the flash access registers.
1276  **/
1277 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1278                                          u8 size, u16 *data)
1279 {
1280         union ich8_hws_flash_status hsfsts;
1281         union ich8_hws_flash_ctrl hsflctl;
1282         u32 flash_linear_addr;
1283         u32 flash_data = 0;
1284         s32 ret_val = -E1000_ERR_NVM;
1285         u8 count = 0;
1286
1287         DEBUGFUNC("e1000_read_flash_data_ich8lan");
1288
1289         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1290                 goto out;
1291
1292         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1293                             hw->nvm.flash_base_addr;
1294
1295         do {
1296                 usec_delay(1);
1297                 /* Steps */
1298                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1299                 if (ret_val != E1000_SUCCESS)
1300                         break;
1301
1302                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1303                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1304                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1305                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1306                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1307
1308                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1309
1310                 ret_val = e1000_flash_cycle_ich8lan(hw,
1311                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1312
1313                 /*
1314                  * Check if FCERR is set to 1, if set to 1, clear it
1315                  * and try the whole sequence a few more times, else
1316                  * read in (shift in) the Flash Data0, the order is
1317                  * least significant byte first msb to lsb
1318                  */
1319                 if (ret_val == E1000_SUCCESS) {
1320                         flash_data = E1000_READ_FLASH_REG(hw, ICH_FLASH_FDATA0);
1321                         if (size == 1)
1322                                 *data = (u8)(flash_data & 0x000000FF);
1323                         else if (size == 2)
1324                                 *data = (u16)(flash_data & 0x0000FFFF);
1325                         break;
1326                 } else {
1327                         /*
1328                          * If we've gotten here, then things are probably
1329                          * completely hosed, but if the error condition is
1330                          * detected, it won't hurt to give it another try...
1331                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1332                          */
1333                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1334                                                               ICH_FLASH_HSFSTS);
1335                         if (hsfsts.hsf_status.flcerr == 1) {
1336                                 /* Repeat for some time before giving up. */
1337                                 continue;
1338                         } else if (hsfsts.hsf_status.flcdone == 0) {
1339                                 DEBUGOUT("Timeout error - flash cycle "
1340                                          "did not complete.");
1341                                 break;
1342                         }
1343                 }
1344         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1345
1346 out:
1347         return ret_val;
1348 }
1349
1350 /**
1351  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1352  *  @hw: pointer to the HW structure
1353  *  @offset: The offset (in bytes) of the word(s) to write.
1354  *  @words: Size of data to write in words
1355  *  @data: Pointer to the word(s) to write at offset.
1356  *
1357  *  Writes a byte or word to the NVM using the flash access registers.
1358  **/
1359 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1360                                    u16 *data)
1361 {
1362         struct e1000_nvm_info *nvm = &hw->nvm;
1363         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1364         s32 ret_val = E1000_SUCCESS;
1365         u16 i;
1366
1367         DEBUGFUNC("e1000_write_nvm_ich8lan");
1368
1369         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1370             (words == 0)) {
1371                 DEBUGOUT("nvm parameter(s) out of bounds\n");
1372                 ret_val = -E1000_ERR_NVM;
1373                 goto out;
1374         }
1375
1376         ret_val = nvm->ops.acquire(hw);
1377         if (ret_val)
1378                 goto out;
1379
1380         for (i = 0; i < words; i++) {
1381                 dev_spec->shadow_ram[offset+i].modified = TRUE;
1382                 dev_spec->shadow_ram[offset+i].value = data[i];
1383         }
1384
1385         nvm->ops.release(hw);
1386
1387 out:
1388         return ret_val;
1389 }
1390
1391 /**
1392  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1393  *  @hw: pointer to the HW structure
1394  *
1395  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1396  *  which writes the checksum to the shadow ram.  The changes in the shadow
1397  *  ram are then committed to the EEPROM by processing each bank at a time
1398  *  checking for the modified bit and writing only the pending changes.
1399  *  After a successful commit, the shadow ram is cleared and is ready for
1400  *  future writes.
1401  **/
1402 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1403 {
1404         struct e1000_nvm_info *nvm = &hw->nvm;
1405         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1406         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1407         s32 ret_val;
1408         u16 data;
1409
1410         DEBUGFUNC("e1000_update_nvm_checksum_ich8lan");
1411
1412         ret_val = e1000_update_nvm_checksum_generic(hw);
1413         if (ret_val)
1414                 goto out;
1415
1416         if (nvm->type != e1000_nvm_flash_sw)
1417                 goto out;
1418
1419         ret_val = nvm->ops.acquire(hw);
1420         if (ret_val)
1421                 goto out;
1422
1423         /*
1424          * We're writing to the opposite bank so if we're on bank 1,
1425          * write to bank 0 etc.  We also need to erase the segment that
1426          * is going to be written
1427          */
1428         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1429         if (ret_val != E1000_SUCCESS)
1430                 goto out;
1431
1432         if (bank == 0) {
1433                 new_bank_offset = nvm->flash_bank_size;
1434                 old_bank_offset = 0;
1435                 e1000_erase_flash_bank_ich8lan(hw, 1);
1436         } else {
1437                 old_bank_offset = nvm->flash_bank_size;
1438                 new_bank_offset = 0;
1439                 e1000_erase_flash_bank_ich8lan(hw, 0);
1440         }
1441
1442         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1443                 /*
1444                  * Determine whether to write the value stored
1445                  * in the other NVM bank or a modified value stored
1446                  * in the shadow RAM
1447                  */
1448                 if (dev_spec->shadow_ram[i].modified) {
1449                         data = dev_spec->shadow_ram[i].value;
1450                 } else {
1451                         e1000_read_flash_word_ich8lan(hw,
1452                                                       i + old_bank_offset,
1453                                                       &data);
1454                 }
1455
1456                 /*
1457                  * If the word is 0x13, then make sure the signature bits
1458                  * (15:14) are 11b until the commit has completed.
1459                  * This will allow us to write 10b which indicates the
1460                  * signature is valid.  We want to do this after the write
1461                  * has completed so that we don't mark the segment valid
1462                  * while the write is still in progress
1463                  */
1464                 if (i == E1000_ICH_NVM_SIG_WORD)
1465                         data |= E1000_ICH_NVM_SIG_MASK;
1466
1467                 /* Convert offset to bytes. */
1468                 act_offset = (i + new_bank_offset) << 1;
1469
1470                 usec_delay(100);
1471                 /* Write the bytes to the new bank. */
1472                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1473                                                                act_offset,
1474                                                                (u8)data);
1475                 if (ret_val)
1476                         break;
1477
1478                 usec_delay(100);
1479                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1480                                                           act_offset + 1,
1481                                                           (u8)(data >> 8));
1482                 if (ret_val)
1483                         break;
1484         }
1485
1486         /*
1487          * Don't bother writing the segment valid bits if sector
1488          * programming failed.
1489          */
1490         if (ret_val) {
1491                 DEBUGOUT("Flash commit failed.\n");
1492                 nvm->ops.release(hw);
1493                 goto out;
1494         }
1495
1496         /*
1497          * Finally validate the new segment by setting bit 15:14
1498          * to 10b in word 0x13 , this can be done without an
1499          * erase as well since these bits are 11 to start with
1500          * and we need to change bit 14 to 0b
1501          */
1502         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1503         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1504         data &= 0xBFFF;
1505         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1506                                                        act_offset * 2 + 1,
1507                                                        (u8)(data >> 8));
1508         if (ret_val) {
1509                 nvm->ops.release(hw);
1510                 goto out;
1511         }
1512
1513         /*
1514          * And invalidate the previously valid segment by setting
1515          * its signature word (0x13) high_byte to 0b. This can be
1516          * done without an erase because flash erase sets all bits
1517          * to 1's. We can write 1's to 0's without an erase
1518          */
1519         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1520         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1521         if (ret_val) {
1522                 nvm->ops.release(hw);
1523                 goto out;
1524         }
1525
1526         /* Great!  Everything worked, we can now clear the cached entries. */
1527         for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
1528                 dev_spec->shadow_ram[i].modified = FALSE;
1529                 dev_spec->shadow_ram[i].value = 0xFFFF;
1530         }
1531
1532         nvm->ops.release(hw);
1533
1534         /*
1535          * Reload the EEPROM, or else modifications will not appear
1536          * until after the next adapter reset.
1537          */
1538         nvm->ops.reload(hw);
1539         msec_delay(10);
1540
1541 out:
1542         return ret_val;
1543 }
1544
1545 /**
1546  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1547  *  @hw: pointer to the HW structure
1548  *
1549  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1550  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1551  *  calculated, in which case we need to calculate the checksum and set bit 6.
1552  **/
1553 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1554 {
1555         s32 ret_val = E1000_SUCCESS;
1556         u16 data;
1557
1558         DEBUGFUNC("e1000_validate_nvm_checksum_ich8lan");
1559
1560         /*
1561          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1562          * needs to be fixed.  This bit is an indication that the NVM
1563          * was prepared by OEM software and did not calculate the
1564          * checksum...a likely scenario.
1565          */
1566         ret_val = hw->nvm.ops.read(hw, 0x19, 1, &data);
1567         if (ret_val)
1568                 goto out;
1569
1570         if ((data & 0x40) == 0) {
1571                 data |= 0x40;
1572                 ret_val = hw->nvm.ops.write(hw, 0x19, 1, &data);
1573                 if (ret_val)
1574                         goto out;
1575                 ret_val = hw->nvm.ops.update(hw);
1576                 if (ret_val)
1577                         goto out;
1578         }
1579
1580         ret_val = e1000_validate_nvm_checksum_generic(hw);
1581
1582 out:
1583         return ret_val;
1584 }
1585
1586 /**
1587  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1588  *  @hw: pointer to the HW structure
1589  *  @offset: The offset (in bytes) of the byte/word to read.
1590  *  @size: Size of data to read, 1=byte 2=word
1591  *  @data: The byte(s) to write to the NVM.
1592  *
1593  *  Writes one/two bytes to the NVM using the flash access registers.
1594  **/
1595 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1596                                           u8 size, u16 data)
1597 {
1598         union ich8_hws_flash_status hsfsts;
1599         union ich8_hws_flash_ctrl hsflctl;
1600         u32 flash_linear_addr;
1601         u32 flash_data = 0;
1602         s32 ret_val = -E1000_ERR_NVM;
1603         u8 count = 0;
1604
1605         DEBUGFUNC("e1000_write_ich8_data");
1606
1607         if (size < 1 || size > 2 || data > size * 0xff ||
1608             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1609                 goto out;
1610
1611         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1612                             hw->nvm.flash_base_addr;
1613
1614         do {
1615                 usec_delay(1);
1616                 /* Steps */
1617                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1618                 if (ret_val != E1000_SUCCESS)
1619                         break;
1620
1621                 hsflctl.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
1622                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1623                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1624                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1625                 E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
1626
1627                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_addr);
1628
1629                 if (size == 1)
1630                         flash_data = (u32)data & 0x00FF;
1631                 else
1632                         flash_data = (u32)data;
1633
1634                 E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
1635
1636                 /*
1637                  * check if FCERR is set to 1 , if set to 1, clear it
1638                  * and try the whole sequence a few more times else done
1639                  */
1640                 ret_val = e1000_flash_cycle_ich8lan(hw,
1641                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1642                 if (ret_val == E1000_SUCCESS)
1643                         break;
1644
1645                 /*
1646                  * If we're here, then things are most likely
1647                  * completely hosed, but if the error condition
1648                  * is detected, it won't hurt to give it another
1649                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1650                  */
1651                 hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1652                 if (hsfsts.hsf_status.flcerr == 1) {
1653                         /* Repeat for some time before giving up. */
1654                         continue;
1655                 } else if (hsfsts.hsf_status.flcdone == 0) {
1656                         DEBUGOUT("Timeout error - flash cycle "
1657                                  "did not complete.");
1658                         break;
1659                 }
1660         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1661
1662 out:
1663         return ret_val;
1664 }
1665
1666 /**
1667  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1668  *  @hw: pointer to the HW structure
1669  *  @offset: The index of the byte to read.
1670  *  @data: The byte to write to the NVM.
1671  *
1672  *  Writes a single byte to the NVM using the flash access registers.
1673  **/
1674 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1675                                           u8 data)
1676 {
1677         u16 word = (u16)data;
1678
1679         DEBUGFUNC("e1000_write_flash_byte_ich8lan");
1680
1681         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1682 }
1683
1684 /**
1685  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1686  *  @hw: pointer to the HW structure
1687  *  @offset: The offset of the byte to write.
1688  *  @byte: The byte to write to the NVM.
1689  *
1690  *  Writes a single byte to the NVM using the flash access registers.
1691  *  Goes through a retry algorithm before giving up.
1692  **/
1693 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1694                                                 u32 offset, u8 byte)
1695 {
1696         s32 ret_val;
1697         u16 program_retries;
1698
1699         DEBUGFUNC("e1000_retry_write_flash_byte_ich8lan");
1700
1701         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1702         if (ret_val == E1000_SUCCESS)
1703                 goto out;
1704
1705         for (program_retries = 0; program_retries < 100; program_retries++) {
1706                 DEBUGOUT2("Retrying Byte %2.2X at offset %u\n", byte, offset);
1707                 usec_delay(100);
1708                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1709                 if (ret_val == E1000_SUCCESS)
1710                         break;
1711         }
1712         if (program_retries == 100) {
1713                 ret_val = -E1000_ERR_NVM;
1714                 goto out;
1715         }
1716
1717 out:
1718         return ret_val;
1719 }
1720
1721 /**
1722  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1723  *  @hw: pointer to the HW structure
1724  *  @bank: 0 for first bank, 1 for second bank, etc.
1725  *
1726  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1727  *  bank N is 4096 * N + flash_reg_addr.
1728  **/
1729 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1730 {
1731         struct e1000_nvm_info *nvm = &hw->nvm;
1732         union ich8_hws_flash_status hsfsts;
1733         union ich8_hws_flash_ctrl hsflctl;
1734         u32 flash_linear_addr;
1735         /* bank size is in 16bit words - adjust to bytes */
1736         u32 flash_bank_size = nvm->flash_bank_size * 2;
1737         s32 ret_val = E1000_SUCCESS;
1738         s32 count = 0;
1739         s32 j, iteration, sector_size;
1740
1741         DEBUGFUNC("e1000_erase_flash_bank_ich8lan");
1742
1743         hsfsts.regval = E1000_READ_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
1744
1745         /*
1746          * Determine HW Sector size: Read BERASE bits of hw flash status
1747          * register
1748          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1749          *     consecutive sectors.  The start index for the nth Hw sector
1750          *     can be calculated as = bank * 4096 + n * 256
1751          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1752          *     The start index for the nth Hw sector can be calculated
1753          *     as = bank * 4096
1754          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1755          *     (ich9 only, otherwise error condition)
1756          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1757          */
1758         switch (hsfsts.hsf_status.berasesz) {
1759         case 0:
1760                 /* Hw sector size 256 */
1761                 sector_size = ICH_FLASH_SEG_SIZE_256;
1762                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1763                 break;
1764         case 1:
1765                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1766                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1767                 break;
1768         case 2:
1769                 if (hw->mac.type == e1000_ich9lan) {
1770                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1771                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1772                 } else {
1773                         ret_val = -E1000_ERR_NVM;
1774                         goto out;
1775                 }
1776                 break;
1777         case 3:
1778                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1779                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1780                 break;
1781         default:
1782                 ret_val = -E1000_ERR_NVM;
1783                 goto out;
1784         }
1785
1786         /* Start with the base address, then add the sector offset. */
1787         flash_linear_addr = hw->nvm.flash_base_addr;
1788         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1789
1790         for (j = 0; j < iteration ; j++) {
1791                 do {
1792                         /* Steps */
1793                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1794                         if (ret_val)
1795                                 goto out;
1796
1797                         /*
1798                          * Write a value 11 (block Erase) in Flash
1799                          * Cycle field in hw flash control
1800                          */
1801                         hsflctl.regval = E1000_READ_FLASH_REG16(hw,
1802                                                               ICH_FLASH_HSFCTL);
1803                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1804                         E1000_WRITE_FLASH_REG16(hw, ICH_FLASH_HSFCTL,
1805                                                 hsflctl.regval);
1806
1807                         /*
1808                          * Write the last 24 bits of an index within the
1809                          * block into Flash Linear address field in Flash
1810                          * Address.
1811                          */
1812                         flash_linear_addr += (j * sector_size);
1813                         E1000_WRITE_FLASH_REG(hw, ICH_FLASH_FADDR,
1814                                               flash_linear_addr);
1815
1816                         ret_val = e1000_flash_cycle_ich8lan(hw,
1817                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1818                         if (ret_val == E1000_SUCCESS)
1819                                 break;
1820
1821                         /*
1822                          * Check if FCERR is set to 1.  If 1,
1823                          * clear it and try the whole sequence
1824                          * a few more times else Done
1825                          */
1826                         hsfsts.regval = E1000_READ_FLASH_REG16(hw,
1827                                                       ICH_FLASH_HSFSTS);
1828                         if (hsfsts.hsf_status.flcerr == 1)
1829                                 /* repeat for some time before giving up */
1830                                 continue;
1831                         else if (hsfsts.hsf_status.flcdone == 0)
1832                                 goto out;
1833                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1834         }
1835
1836 out:
1837         return ret_val;
1838 }
1839
1840 /**
1841  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1842  *  @hw: pointer to the HW structure
1843  *  @data: Pointer to the LED settings
1844  *
1845  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1846  *  settings is all 0's or F's, set the LED default to a valid LED default
1847  *  setting.
1848  **/
1849 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1850 {
1851         s32 ret_val;
1852
1853         DEBUGFUNC("e1000_valid_led_default_ich8lan");
1854
1855         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1856         if (ret_val) {
1857                 DEBUGOUT("NVM Read Error\n");
1858                 goto out;
1859         }
1860
1861         if (*data == ID_LED_RESERVED_0000 ||
1862             *data == ID_LED_RESERVED_FFFF)
1863                 *data = ID_LED_DEFAULT_ICH8LAN;
1864
1865 out:
1866         return ret_val;
1867 }
1868
1869 /**
1870  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1871  *  @hw: pointer to the HW structure
1872  *
1873  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1874  *  register, so the the bus width is hard coded.
1875  **/
1876 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1877 {
1878         struct e1000_bus_info *bus = &hw->bus;
1879         s32 ret_val;
1880
1881         DEBUGFUNC("e1000_get_bus_info_ich8lan");
1882
1883         ret_val = e1000_get_bus_info_pcie_generic(hw);
1884
1885         /*
1886          * ICH devices are "PCI Express"-ish.  They have
1887          * a configuration space, but do not contain
1888          * PCI Express Capability registers, so bus width
1889          * must be hardcoded.
1890          */
1891         if (bus->width == e1000_bus_width_unknown)
1892                 bus->width = e1000_bus_width_pcie_x1;
1893
1894         return ret_val;
1895 }
1896
1897 /**
1898  *  e1000_reset_hw_ich8lan - Reset the hardware
1899  *  @hw: pointer to the HW structure
1900  *
1901  *  Does a full reset of the hardware which includes a reset of the PHY and
1902  *  MAC.
1903  **/
1904 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1905 {
1906         u32 ctrl, icr, kab;
1907         s32 ret_val;
1908
1909         DEBUGFUNC("e1000_reset_hw_ich8lan");
1910
1911         /*
1912          * Prevent the PCI-E bus from sticking if there is no TLP connection
1913          * on the last TLP read/write transaction when MAC is reset.
1914          */
1915         ret_val = e1000_disable_pcie_master_generic(hw);
1916         if (ret_val)
1917                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1918
1919         DEBUGOUT("Masking off all interrupts\n");
1920         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1921
1922         /*
1923          * Disable the Transmit and Receive units.  Then delay to allow
1924          * any pending transactions to complete before we hit the MAC
1925          * with the global reset.
1926          */
1927         E1000_WRITE_REG(hw, E1000_RCTL, 0);
1928         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1929         E1000_WRITE_FLUSH(hw);
1930
1931         msec_delay(10);
1932
1933         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1934         if (hw->mac.type == e1000_ich8lan) {
1935                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1936                 E1000_WRITE_REG(hw, E1000_PBA, E1000_PBA_8K);
1937                 /* Set Packet Buffer Size to 16k. */
1938                 E1000_WRITE_REG(hw, E1000_PBS, E1000_PBS_16K);
1939         }
1940
1941         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1942
1943         if (!hw->phy.ops.check_reset_block(hw) && !hw->phy.reset_disable) {
1944                 /*
1945                  * PHY HW reset requires MAC CORE reset at the same
1946                  * time to make sure the interface between MAC and the
1947                  * external PHY is reset.
1948                  */
1949                 ctrl |= E1000_CTRL_PHY_RST;
1950         }
1951         ret_val = e1000_acquire_swflag_ich8lan(hw);
1952         DEBUGOUT("Issuing a global reset to ich8lan\n");
1953         E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_RST));
1954         msec_delay(20);
1955
1956         ret_val = e1000_get_auto_rd_done_generic(hw);
1957         if (ret_val) {
1958                 /*
1959                  * When auto config read does not complete, do not
1960                  * return with an error. This can happen in situations
1961                  * where there is no eeprom and prevents getting link.
1962                  */
1963                 DEBUGOUT("Auto Read Done did not complete\n");
1964         }
1965
1966         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1967         icr = E1000_READ_REG(hw, E1000_ICR);
1968
1969         kab = E1000_READ_REG(hw, E1000_KABGTXD);
1970         kab |= E1000_KABGTXD_BGSQLBIAS;
1971         E1000_WRITE_REG(hw, E1000_KABGTXD, kab);
1972
1973         return ret_val;
1974 }
1975
1976 /**
1977  *  e1000_init_hw_ich8lan - Initialize the hardware
1978  *  @hw: pointer to the HW structure
1979  *
1980  *  Prepares the hardware for transmit and receive by doing the following:
1981  *   - initialize hardware bits
1982  *   - initialize LED identification
1983  *   - setup receive address registers
1984  *   - setup flow control
1985  *   - setup transmit descriptors
1986  *   - clear statistics
1987  **/
1988 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1989 {
1990         struct e1000_mac_info *mac = &hw->mac;
1991         u32 ctrl_ext, txdctl, snoop;
1992         s32 ret_val;
1993         u16 i;
1994
1995         DEBUGFUNC("e1000_init_hw_ich8lan");
1996
1997         e1000_initialize_hw_bits_ich8lan(hw);
1998
1999         /* Initialize identification LED */
2000         ret_val = e1000_id_led_init_generic(hw);
2001         if (ret_val) {
2002                 DEBUGOUT("Error initializing identification LED\n");
2003                 /* This is not fatal and we should not stop init due to this */
2004         }
2005
2006         /* Setup the receive address. */
2007         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
2008
2009         /* Zero out the Multicast HASH table */
2010         DEBUGOUT("Zeroing the MTA\n");
2011         for (i = 0; i < mac->mta_reg_count; i++)
2012                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2013
2014         /* Setup link and flow control */
2015         ret_val = mac->ops.setup_link(hw);
2016
2017         /* Set the transmit descriptor write-back policy for both queues */
2018         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
2019         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2020                  E1000_TXDCTL_FULL_TX_DESC_WB;
2021         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2022                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2023         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
2024         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1));
2025         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2026                  E1000_TXDCTL_FULL_TX_DESC_WB;
2027         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2028                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2029         E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl);
2030
2031         /*
2032          * ICH8 has opposite polarity of no_snoop bits.
2033          * By default, we should use snoop behavior.
2034          */
2035         if (mac->type == e1000_ich8lan)
2036                 snoop = PCIE_ICH8_SNOOP_ALL;
2037         else
2038                 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
2039         e1000_set_pcie_no_snoop_generic(hw, snoop);
2040
2041         ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2042         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2043         E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2044
2045         /*
2046          * Clear all of the statistics registers (clear on read).  It is
2047          * important that we do this after we have tried to establish link
2048          * because the symbol error count will increment wildly if there
2049          * is no link.
2050          */
2051         e1000_clear_hw_cntrs_ich8lan(hw);
2052
2053         return ret_val;
2054 }
2055 /**
2056  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2057  *  @hw: pointer to the HW structure
2058  *
2059  *  Sets/Clears required hardware bits necessary for correctly setting up the
2060  *  hardware for transmit and receive.
2061  **/
2062 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2063 {
2064         u32 reg;
2065
2066         DEBUGFUNC("e1000_initialize_hw_bits_ich8lan");
2067
2068         /* Extended Device Control */
2069         reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
2070         reg |= (1 << 22);
2071         E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
2072
2073         /* Transmit Descriptor Control 0 */
2074         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
2075         reg |= (1 << 22);
2076         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
2077
2078         /* Transmit Descriptor Control 1 */
2079         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
2080         reg |= (1 << 22);
2081         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
2082
2083         /* Transmit Arbitration Control 0 */
2084         reg = E1000_READ_REG(hw, E1000_TARC(0));
2085         if (hw->mac.type == e1000_ich8lan)
2086                 reg |= (1 << 28) | (1 << 29);
2087         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2088         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
2089
2090         /* Transmit Arbitration Control 1 */
2091         reg = E1000_READ_REG(hw, E1000_TARC(1));
2092         if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
2093                 reg &= ~(1 << 28);
2094         else
2095                 reg |= (1 << 28);
2096         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2097         E1000_WRITE_REG(hw, E1000_TARC(1), reg);
2098
2099         /* Device Status */
2100         if (hw->mac.type == e1000_ich8lan) {
2101                 reg = E1000_READ_REG(hw, E1000_STATUS);
2102                 reg &= ~(1 << 31);
2103                 E1000_WRITE_REG(hw, E1000_STATUS, reg);
2104         }
2105
2106         return;
2107 }
2108
2109 /**
2110  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2111  *  @hw: pointer to the HW structure
2112  *
2113  *  Determines which flow control settings to use, then configures flow
2114  *  control.  Calls the appropriate media-specific link configuration
2115  *  function.  Assuming the adapter has a valid link partner, a valid link
2116  *  should be established.  Assumes the hardware has previously been reset
2117  *  and the transmitter and receiver are not enabled.
2118  **/
2119 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2120 {
2121         s32 ret_val = E1000_SUCCESS;
2122
2123         DEBUGFUNC("e1000_setup_link_ich8lan");
2124
2125         if (hw->phy.ops.check_reset_block(hw))
2126                 goto out;
2127
2128         /*
2129          * ICH parts do not have a word in the NVM to determine
2130          * the default flow control setting, so we explicitly
2131          * set it to full.
2132          */
2133         if (hw->fc.requested_mode == e1000_fc_default)
2134                 hw->fc.requested_mode = e1000_fc_full;
2135
2136         /*
2137          * Save off the requested flow control mode for use later.  Depending
2138          * on the link partner's capabilities, we may or may not use this mode.
2139          */
2140         hw->fc.current_mode = hw->fc.requested_mode;
2141
2142         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
2143                                                     hw->fc.current_mode);
2144
2145         /* Continue to configure the copper link. */
2146         ret_val = hw->mac.ops.setup_physical_interface(hw);
2147         if (ret_val)
2148                 goto out;
2149
2150         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
2151
2152         ret_val = e1000_set_fc_watermarks_generic(hw);
2153
2154 out:
2155         return ret_val;
2156 }
2157
2158 /**
2159  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2160  *  @hw: pointer to the HW structure
2161  *
2162  *  Configures the kumeran interface to the PHY to wait the appropriate time
2163  *  when polling the PHY, then call the generic setup_copper_link to finish
2164  *  configuring the copper link.
2165  **/
2166 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2167 {
2168         u32 ctrl;
2169         s32 ret_val;
2170         u16 reg_data;
2171
2172         DEBUGFUNC("e1000_setup_copper_link_ich8lan");
2173
2174         ctrl = E1000_READ_REG(hw, E1000_CTRL);
2175         ctrl |= E1000_CTRL_SLU;
2176         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2177         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2178
2179         /*
2180          * Set the mac to wait the maximum time between each iteration
2181          * and increase the max iterations when polling the phy;
2182          * this fixes erroneous timeouts at 10Mbps.
2183          */
2184         ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 4),
2185                                                0xFFFF);
2186         if (ret_val)
2187                 goto out;
2188         ret_val = e1000_read_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
2189                                               &reg_data);
2190         if (ret_val)
2191                 goto out;
2192         reg_data |= 0x3F;
2193         ret_val = e1000_write_kmrn_reg_generic(hw, GG82563_REG(0x34, 9),
2194                                                reg_data);
2195         if (ret_val)
2196                 goto out;
2197
2198         if (hw->phy.type == e1000_phy_igp_3) {
2199                 ret_val = e1000_copper_link_setup_igp(hw);
2200                 if (ret_val)
2201                         goto out;
2202         } else if (hw->phy.type == e1000_phy_bm) {
2203                 ret_val = e1000_copper_link_setup_m88(hw);
2204                 if (ret_val)
2205                         goto out;
2206         }
2207
2208         if (hw->phy.type == e1000_phy_ife) {
2209                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2210                                                &reg_data);
2211                 if (ret_val)
2212                         goto out;
2213
2214                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2215
2216                 switch (hw->phy.mdix) {
2217                 case 1:
2218                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2219                         break;
2220                 case 2:
2221                         reg_data |= IFE_PMC_FORCE_MDIX;
2222                         break;
2223                 case 0:
2224                 default:
2225                         reg_data |= IFE_PMC_AUTO_MDIX;
2226                         break;
2227                 }
2228                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2229                                                 reg_data);
2230                 if (ret_val)
2231                         goto out;
2232         }
2233         ret_val = e1000_setup_copper_link_generic(hw);
2234
2235 out:
2236         return ret_val;
2237 }
2238
2239 /**
2240  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2241  *  @hw: pointer to the HW structure
2242  *  @speed: pointer to store current link speed
2243  *  @duplex: pointer to store the current link duplex
2244  *
2245  *  Calls the generic get_speed_and_duplex to retrieve the current link
2246  *  information and then calls the Kumeran lock loss workaround for links at
2247  *  gigabit speeds.
2248  **/
2249 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2250                                           u16 *duplex)
2251 {
2252         s32 ret_val;
2253
2254         DEBUGFUNC("e1000_get_link_up_info_ich8lan");
2255
2256         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
2257         if (ret_val)
2258                 goto out;
2259
2260         if ((hw->mac.type == e1000_ich8lan) &&
2261             (hw->phy.type == e1000_phy_igp_3) &&
2262             (*speed == SPEED_1000)) {
2263                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2264         }
2265
2266 out:
2267         return ret_val;
2268 }
2269
2270 /**
2271  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2272  *  @hw: pointer to the HW structure
2273  *
2274  *  Work-around for 82566 Kumeran PCS lock loss:
2275  *  On link status change (i.e. PCI reset, speed change) and link is up and
2276  *  speed is gigabit-
2277  *    0) if workaround is optionally disabled do nothing
2278  *    1) wait 1ms for Kumeran link to come up
2279  *    2) check Kumeran Diagnostic register PCS lock loss bit
2280  *    3) if not set the link is locked (all is good), otherwise...
2281  *    4) reset the PHY
2282  *    5) repeat up to 10 times
2283  *  Note: this is only called for IGP3 copper when speed is 1gb.
2284  **/
2285 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2286 {
2287         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2288         u32 phy_ctrl;
2289         s32 ret_val = E1000_SUCCESS;
2290         u16 i, data;
2291         bool link;
2292
2293         DEBUGFUNC("e1000_kmrn_lock_loss_workaround_ich8lan");
2294
2295         if (!(dev_spec->kmrn_lock_loss_workaround_enabled))
2296                 goto out;
2297
2298         /*
2299          * Make sure link is up before proceeding.  If not just return.
2300          * Attempting this while link is negotiating fouled up link
2301          * stability
2302          */
2303         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2304         if (!link) {
2305                 ret_val = E1000_SUCCESS;
2306                 goto out;
2307         }
2308
2309         for (i = 0; i < 10; i++) {
2310                 /* read once to clear */
2311                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2312                 if (ret_val)
2313                         goto out;
2314                 /* and again to get new status */
2315                 ret_val = hw->phy.ops.read_reg(hw, IGP3_KMRN_DIAG, &data);
2316                 if (ret_val)
2317                         goto out;
2318
2319                 /* check for PCS lock */
2320                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) {
2321                         ret_val = E1000_SUCCESS;
2322                         goto out;
2323                 }
2324
2325                 /* Issue PHY reset */
2326                 hw->phy.ops.reset(hw);
2327                 msec_delay_irq(5);
2328         }
2329         /* Disable GigE link negotiation */
2330         phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2331         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2332                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2333         E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2334
2335         /*
2336          * Call gig speed drop workaround on Gig disable before accessing
2337          * any PHY registers
2338          */
2339         e1000_gig_downshift_workaround_ich8lan(hw);
2340
2341         /* unable to acquire PCS lock */
2342         ret_val = -E1000_ERR_PHY;
2343
2344 out:
2345         return ret_val;
2346 }
2347
2348 /**
2349  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2350  *  @hw: pointer to the HW structure
2351  *  @state: boolean value used to set the current Kumeran workaround state
2352  *
2353  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2354  *  /disabled - FALSE).
2355  **/
2356 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2357                                                  bool state)
2358 {
2359         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2360
2361         DEBUGFUNC("e1000_set_kmrn_lock_loss_workaround_ich8lan");
2362
2363         if (hw->mac.type != e1000_ich8lan) {
2364                 DEBUGOUT("Workaround applies to ICH8 only.\n");
2365                 return;
2366         }
2367
2368         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2369
2370         return;
2371 }
2372
2373 /**
2374  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2375  *  @hw: pointer to the HW structure
2376  *
2377  *  Workaround for 82566 power-down on D3 entry:
2378  *    1) disable gigabit link
2379  *    2) write VR power-down enable
2380  *    3) read it back
2381  *  Continue if successful, else issue LCD reset and repeat
2382  **/
2383 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2384 {
2385         u32 reg;
2386         u16 data;
2387         u8  retry = 0;
2388
2389         DEBUGFUNC("e1000_igp3_phy_powerdown_workaround_ich8lan");
2390
2391         if (hw->phy.type != e1000_phy_igp_3)
2392                 goto out;
2393
2394         /* Try the workaround twice (if needed) */
2395         do {
2396                 /* Disable link */
2397                 reg = E1000_READ_REG(hw, E1000_PHY_CTRL);
2398                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2399                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2400                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, reg);
2401
2402                 /*
2403                  * Call gig speed drop workaround on Gig disable before
2404                  * accessing any PHY registers
2405                  */
2406                 if (hw->mac.type == e1000_ich8lan)
2407                         e1000_gig_downshift_workaround_ich8lan(hw);
2408
2409                 /* Write VR power-down enable */
2410                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2411                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2412                 hw->phy.ops.write_reg(hw, IGP3_VR_CTRL,
2413                                    data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2414
2415                 /* Read it back and test */
2416                 hw->phy.ops.read_reg(hw, IGP3_VR_CTRL, &data);
2417                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2418                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2419                         break;
2420
2421                 /* Issue PHY reset and repeat at most one more time */
2422                 reg = E1000_READ_REG(hw, E1000_CTRL);
2423                 E1000_WRITE_REG(hw, E1000_CTRL, reg | E1000_CTRL_PHY_RST);
2424                 retry++;
2425         } while (retry);
2426
2427 out:
2428         return;
2429 }
2430
2431 /**
2432  *  e1000_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2433  *  @hw: pointer to the HW structure
2434  *
2435  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2436  *  LPLU, Gig disable, MDIC PHY reset):
2437  *    1) Set Kumeran Near-end loopback
2438  *    2) Clear Kumeran Near-end loopback
2439  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2440  **/
2441 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2442 {
2443         s32 ret_val = E1000_SUCCESS;
2444         u16 reg_data;
2445
2446         DEBUGFUNC("e1000_gig_downshift_workaround_ich8lan");
2447
2448         if ((hw->mac.type != e1000_ich8lan) ||
2449             (hw->phy.type != e1000_phy_igp_3))
2450                 goto out;
2451
2452         ret_val = e1000_read_kmrn_reg_generic(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2453                                               &reg_data);
2454         if (ret_val)
2455                 goto out;
2456         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2457         ret_val = e1000_write_kmrn_reg_generic(hw,
2458                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
2459                                                reg_data);
2460         if (ret_val)
2461                 goto out;
2462         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2463         ret_val = e1000_write_kmrn_reg_generic(hw,
2464                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
2465                                                reg_data);
2466 out:
2467         return;
2468 }
2469
2470 /**
2471  *  e1000_disable_gig_wol_ich8lan - disable gig during WoL
2472  *  @hw: pointer to the HW structure
2473  *
2474  *  During S0 to Sx transition, it is possible the link remains at gig
2475  *  instead of negotiating to a lower speed.  Before going to Sx, set
2476  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2477  *  to a lower speed.
2478  *
2479  *  Should only be called for ICH9 and ICH10 devices.
2480  **/
2481 void e1000_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2482 {
2483         u32 phy_ctrl;
2484
2485         if ((hw->mac.type == e1000_ich10lan) ||
2486             (hw->mac.type == e1000_ich9lan)) {
2487                 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL);
2488                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2489                             E1000_PHY_CTRL_GBE_DISABLE;
2490                 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl);
2491         }
2492
2493         return;
2494 }
2495
2496 /**
2497  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2498  *  @hw: pointer to the HW structure
2499  *
2500  *  Return the LED back to the default configuration.
2501  **/
2502 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2503 {
2504         s32 ret_val = E1000_SUCCESS;
2505
2506         DEBUGFUNC("e1000_cleanup_led_ich8lan");
2507
2508         if (hw->phy.type == e1000_phy_ife)
2509                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2510                                               0);
2511         else
2512                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
2513
2514         return ret_val;
2515 }
2516
2517 /**
2518  *  e1000_led_on_ich8lan - Turn LEDs on
2519  *  @hw: pointer to the HW structure
2520  *
2521  *  Turn on the LEDs.
2522  **/
2523 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2524 {
2525         s32 ret_val = E1000_SUCCESS;
2526
2527         DEBUGFUNC("e1000_led_on_ich8lan");
2528
2529         if (hw->phy.type == e1000_phy_ife)
2530                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2531                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2532         else
2533                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
2534
2535         return ret_val;
2536 }
2537
2538 /**
2539  *  e1000_led_off_ich8lan - Turn LEDs off
2540  *  @hw: pointer to the HW structure
2541  *
2542  *  Turn off the LEDs.
2543  **/
2544 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2545 {
2546         s32 ret_val = E1000_SUCCESS;
2547
2548         DEBUGFUNC("e1000_led_off_ich8lan");
2549
2550         if (hw->phy.type == e1000_phy_ife)
2551                 ret_val = hw->phy.ops.write_reg(hw,
2552                                IFE_PHY_SPECIAL_CONTROL_LED,
2553                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2554         else
2555                 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2556
2557         return ret_val;
2558 }
2559
2560 /**
2561  *  e1000_get_cfg_done_ich8lan - Read config done bit
2562  *  @hw: pointer to the HW structure
2563  *
2564  *  Read the management control register for the config done bit for
2565  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2566  *  to read the config done bit, so an error is *ONLY* logged and returns
2567  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2568  *  would not be able to be reset or change link.
2569  **/
2570 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2571 {
2572         s32 ret_val = E1000_SUCCESS;
2573         u32 bank = 0;
2574
2575         e1000_get_cfg_done_generic(hw);
2576
2577         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2578         if (hw->mac.type != e1000_ich10lan) {
2579                 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
2580                     (hw->phy.type == e1000_phy_igp_3)) {
2581                         e1000_phy_init_script_igp3(hw);
2582                 }
2583         } else {
2584                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2585                         /* Maybe we should do a basic PHY config */
2586                         DEBUGOUT("EEPROM not present\n");
2587                         ret_val = -E1000_ERR_CONFIG;
2588                 }
2589         }
2590
2591         return ret_val;
2592 }
2593
2594 /**
2595  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
2596  * @hw: pointer to the HW structure
2597  *
2598  * In the case of a PHY power down to save power, or to turn off link during a
2599  * driver unload, or wake on lan is not enabled, remove the link.
2600  **/
2601 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
2602 {
2603         /* If the management interface is not enabled, then power down */
2604         if (!(hw->mac.ops.check_mng_mode(hw) ||
2605               hw->phy.ops.check_reset_block(hw)))
2606                 e1000_power_down_phy_copper(hw);
2607
2608         return;
2609 }
2610
2611 /**
2612  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2613  *  @hw: pointer to the HW structure
2614  *
2615  *  Clears hardware counters specific to the silicon family and calls
2616  *  clear_hw_cntrs_generic to clear all general purpose counters.
2617  **/
2618 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2619 {
2620         DEBUGFUNC("e1000_clear_hw_cntrs_ich8lan");
2621
2622         e1000_clear_hw_cntrs_base_generic(hw);
2623
2624         E1000_READ_REG(hw, E1000_ALGNERRC);
2625         E1000_READ_REG(hw, E1000_RXERRC);
2626         E1000_READ_REG(hw, E1000_TNCRS);
2627         E1000_READ_REG(hw, E1000_CEXTERR);
2628         E1000_READ_REG(hw, E1000_TSCTC);
2629         E1000_READ_REG(hw, E1000_TSCTFC);
2630
2631         E1000_READ_REG(hw, E1000_MGTPRC);
2632         E1000_READ_REG(hw, E1000_MGTPDC);
2633         E1000_READ_REG(hw, E1000_MGTPTC);
2634
2635         E1000_READ_REG(hw, E1000_IAC);
2636         E1000_READ_REG(hw, E1000_ICRXOC);
2637 }
2638