2 * Copyright (c) 2007 Marcel Moolenaar
3 * Copyright (c) 2000 Doug Rabson
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_IA64_CPU_H_
31 #define _MACHINE_IA64_CPU_H_
34 * Definition of DCR bits.
36 #define IA64_DCR_PP 0x0000000000000001
37 #define IA64_DCR_BE 0x0000000000000002
38 #define IA64_DCR_LC 0x0000000000000004
39 #define IA64_DCR_DM 0x0000000000000100
40 #define IA64_DCR_DP 0x0000000000000200
41 #define IA64_DCR_DK 0x0000000000000400
42 #define IA64_DCR_DX 0x0000000000000800
43 #define IA64_DCR_DR 0x0000000000001000
44 #define IA64_DCR_DA 0x0000000000002000
45 #define IA64_DCR_DD 0x0000000000004000
47 #define IA64_DCR_DEFAULT \
48 (IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
49 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
52 * Definition of PSR and IPSR bits.
54 #define IA64_PSR_BE 0x0000000000000002
55 #define IA64_PSR_UP 0x0000000000000004
56 #define IA64_PSR_AC 0x0000000000000008
57 #define IA64_PSR_MFL 0x0000000000000010
58 #define IA64_PSR_MFH 0x0000000000000020
59 #define IA64_PSR_IC 0x0000000000002000
60 #define IA64_PSR_I 0x0000000000004000
61 #define IA64_PSR_PK 0x0000000000008000
62 #define IA64_PSR_DT 0x0000000000020000
63 #define IA64_PSR_DFL 0x0000000000040000
64 #define IA64_PSR_DFH 0x0000000000080000
65 #define IA64_PSR_SP 0x0000000000100000
66 #define IA64_PSR_PP 0x0000000000200000
67 #define IA64_PSR_DI 0x0000000000400000
68 #define IA64_PSR_SI 0x0000000000800000
69 #define IA64_PSR_DB 0x0000000001000000
70 #define IA64_PSR_LP 0x0000000002000000
71 #define IA64_PSR_TB 0x0000000004000000
72 #define IA64_PSR_RT 0x0000000008000000
73 #define IA64_PSR_CPL 0x0000000300000000
74 #define IA64_PSR_CPL_KERN 0x0000000000000000
75 #define IA64_PSR_CPL_1 0x0000000100000000
76 #define IA64_PSR_CPL_2 0x0000000200000000
77 #define IA64_PSR_CPL_USER 0x0000000300000000
78 #define IA64_PSR_IS 0x0000000400000000
79 #define IA64_PSR_MC 0x0000000800000000
80 #define IA64_PSR_IT 0x0000001000000000
81 #define IA64_PSR_ID 0x0000002000000000
82 #define IA64_PSR_DA 0x0000004000000000
83 #define IA64_PSR_DD 0x0000008000000000
84 #define IA64_PSR_SS 0x0000010000000000
85 #define IA64_PSR_RI 0x0000060000000000
86 #define IA64_PSR_RI_0 0x0000000000000000
87 #define IA64_PSR_RI_1 0x0000020000000000
88 #define IA64_PSR_RI_2 0x0000040000000000
89 #define IA64_PSR_ED 0x0000080000000000
90 #define IA64_PSR_BN 0x0000100000000000
91 #define IA64_PSR_IA 0x0000200000000000
94 * Definition of ISR bits.
96 #define IA64_ISR_CODE 0x000000000000ffff
97 #define IA64_ISR_VECTOR 0x0000000000ff0000
98 #define IA64_ISR_X 0x0000000100000000
99 #define IA64_ISR_W 0x0000000200000000
100 #define IA64_ISR_R 0x0000000400000000
101 #define IA64_ISR_NA 0x0000000800000000
102 #define IA64_ISR_SP 0x0000001000000000
103 #define IA64_ISR_RS 0x0000002000000000
104 #define IA64_ISR_IR 0x0000004000000000
105 #define IA64_ISR_NI 0x0000008000000000
106 #define IA64_ISR_SO 0x0000010000000000
107 #define IA64_ISR_EI 0x0000060000000000
108 #define IA64_ISR_EI_0 0x0000000000000000
109 #define IA64_ISR_EI_1 0x0000020000000000
110 #define IA64_ISR_EI_2 0x0000040000000000
111 #define IA64_ISR_ED 0x0000080000000000
114 * Vector numbers for various ia64 interrupts.
116 #define IA64_VEC_VHPT 0
117 #define IA64_VEC_ITLB 1
118 #define IA64_VEC_DTLB 2
119 #define IA64_VEC_ALT_ITLB 3
120 #define IA64_VEC_ALT_DTLB 4
121 #define IA64_VEC_NESTED_DTLB 5
122 #define IA64_VEC_IKEY_MISS 6
123 #define IA64_VEC_DKEY_MISS 7
124 #define IA64_VEC_DIRTY_BIT 8
125 #define IA64_VEC_INST_ACCESS 9
126 #define IA64_VEC_DATA_ACCESS 10
127 #define IA64_VEC_BREAK 11
128 #define IA64_VEC_EXT_INTR 12
129 #define IA64_VEC_PAGE_NOT_PRESENT 20
130 #define IA64_VEC_KEY_PERMISSION 21
131 #define IA64_VEC_INST_ACCESS_RIGHTS 22
132 #define IA64_VEC_DATA_ACCESS_RIGHTS 23
133 #define IA64_VEC_GENERAL_EXCEPTION 24
134 #define IA64_VEC_DISABLED_FP 25
135 #define IA64_VEC_NAT_CONSUMPTION 26
136 #define IA64_VEC_SPECULATION 27
137 #define IA64_VEC_DEBUG 29
138 #define IA64_VEC_UNALIGNED_REFERENCE 30
139 #define IA64_VEC_UNSUPP_DATA_REFERENCE 31
140 #define IA64_VEC_FLOATING_POINT_FAULT 32
141 #define IA64_VEC_FLOATING_POINT_TRAP 33
142 #define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
143 #define IA64_VEC_TAKEN_BRANCH_TRAP 35
144 #define IA64_VEC_SINGLE_STEP_TRAP 36
145 #define IA64_VEC_IA32_EXCEPTION 45
146 #define IA64_VEC_IA32_INTERCEPT 46
147 #define IA64_VEC_IA32_INTERRUPT 47
152 #define IA32_EXCEPTION_DIVIDE 0
153 #define IA32_EXCEPTION_DEBUG 1
154 #define IA32_EXCEPTION_BREAK 3
155 #define IA32_EXCEPTION_OVERFLOW 4
156 #define IA32_EXCEPTION_BOUND 5
157 #define IA32_EXCEPTION_DNA 7
158 #define IA32_EXCEPTION_NOT_PRESENT 11
159 #define IA32_EXCEPTION_STACK_FAULT 12
160 #define IA32_EXCEPTION_GPFAULT 13
161 #define IA32_EXCEPTION_FPERROR 16
162 #define IA32_EXCEPTION_ALIGNMENT_CHECK 17
163 #define IA32_EXCEPTION_STREAMING_SIMD 19
165 #define IA32_INTERCEPT_INSTRUCTION 0
166 #define IA32_INTERCEPT_GATE 1
167 #define IA32_INTERCEPT_SYSTEM_FLAG 2
168 #define IA32_INTERCEPT_LOCK 4
173 * Various special ia64 instructions.
182 __asm __volatile("mf");
188 __asm __volatile("mf.a");
195 ia64_fc(u_int64_t va)
197 __asm __volatile("fc %0" :: "r"(va));
201 * Sync instruction stream.
206 __asm __volatile("sync.i");
210 * Calculate address in VHPT for va.
212 static __inline u_int64_t
213 ia64_thash(u_int64_t va)
216 __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
221 * Calculate VHPT tag for va.
223 static __inline u_int64_t
224 ia64_ttag(u_int64_t va)
227 __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
232 * Convert virtual address to physical.
234 static __inline u_int64_t
235 ia64_tpa(u_int64_t va)
238 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
243 * Generate a ptc.e instruction.
246 ia64_ptc_e(u_int64_t v)
248 __asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
252 * Generate a ptc.g instruction.
255 ia64_ptc_g(u_int64_t va, u_int64_t log2size)
257 __asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
261 * Generate a ptc.ga instruction.
264 ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
266 __asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
270 * Generate a ptc.l instruction.
273 ia64_ptc_l(u_int64_t va, u_int64_t log2size)
275 __asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
279 * Read the value of psr.
281 static __inline u_int64_t
285 __asm __volatile("mov %0=psr;;" : "=r" (result));
290 * Define accessors for application registers.
293 #define IA64_AR(name) \
295 static __inline u_int64_t \
296 ia64_get_##name(void) \
299 __asm __volatile("mov %0=ar." #name : "=r" (result)); \
303 static __inline void \
304 ia64_set_##name(u_int64_t v) \
306 __asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \
346 * Define accessors for control registers.
349 #define IA64_CR(name) \
351 static __inline u_int64_t \
352 ia64_get_##name(void) \
355 __asm __volatile("mov %0=cr." #name : "=r" (result)); \
359 static __inline void \
360 ia64_set_##name(u_int64_t v) \
362 __asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \
398 * Write a region register.
401 ia64_set_rr(u_int64_t rrbase, u_int64_t v)
403 __asm __volatile("mov rr[%0]=%1"
404 :: "r"(rrbase), "r"(v) : "memory");
408 * Read a CPUID register.
410 static __inline u_int64_t
411 ia64_get_cpuid(int i)
414 __asm __volatile("mov %0=cpuid[%1]"
415 : "=r" (result) : "r"(i));
420 ia64_disable_highfp(void)
422 __asm __volatile("ssm psr.dfh;; srlz.d");
426 ia64_enable_highfp(void)
428 __asm __volatile("rsm psr.dfh;; srlz.d");
434 __asm __volatile("srlz.d");
440 __asm __volatile("srlz.i;;");
445 #endif /* _MACHINE_IA64_CPU_H_ */