sys/ia64/include/ia64_cpu.h

   1 /*-
   2  * Copyright (c) 2007 Marcel Moolenaar
   3  * Copyright (c) 2000 Doug Rabson
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #ifndef _MACHINE_IA64_CPU_H_
  31 #define _MACHINE_IA64_CPU_H_
  32
  33 /*
  34  * Definition of DCR bits.
  35  */
  36 #define IA64_DCR_PP             0x0000000000000001
  37 #define IA64_DCR_BE             0x0000000000000002
  38 #define IA64_DCR_LC             0x0000000000000004
  39 #define IA64_DCR_DM             0x0000000000000100
  40 #define IA64_DCR_DP             0x0000000000000200
  41 #define IA64_DCR_DK             0x0000000000000400
  42 #define IA64_DCR_DX             0x0000000000000800
  43 #define IA64_DCR_DR             0x0000000000001000
  44 #define IA64_DCR_DA             0x0000000000002000
  45 #define IA64_DCR_DD             0x0000000000004000
  46
  47 #define IA64_DCR_DEFAULT                                        \
  48     (IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX |    \
  49      IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
  50
  51 /*
  52  * Definition of PSR and IPSR bits.
  53  */
  54 #define IA64_PSR_BE             0x0000000000000002
  55 #define IA64_PSR_UP             0x0000000000000004
  56 #define IA64_PSR_AC             0x0000000000000008
  57 #define IA64_PSR_MFL            0x0000000000000010
  58 #define IA64_PSR_MFH            0x0000000000000020
  59 #define IA64_PSR_IC             0x0000000000002000
  60 #define IA64_PSR_I              0x0000000000004000
  61 #define IA64_PSR_PK             0x0000000000008000
  62 #define IA64_PSR_DT             0x0000000000020000
  63 #define IA64_PSR_DFL            0x0000000000040000
  64 #define IA64_PSR_DFH            0x0000000000080000
  65 #define IA64_PSR_SP             0x0000000000100000
  66 #define IA64_PSR_PP             0x0000000000200000
  67 #define IA64_PSR_DI             0x0000000000400000
  68 #define IA64_PSR_SI             0x0000000000800000
  69 #define IA64_PSR_DB             0x0000000001000000
  70 #define IA64_PSR_LP             0x0000000002000000
  71 #define IA64_PSR_TB             0x0000000004000000
  72 #define IA64_PSR_RT             0x0000000008000000
  73 #define IA64_PSR_CPL            0x0000000300000000
  74 #define IA64_PSR_CPL_KERN       0x0000000000000000
  75 #define IA64_PSR_CPL_1          0x0000000100000000
  76 #define IA64_PSR_CPL_2          0x0000000200000000
  77 #define IA64_PSR_CPL_USER       0x0000000300000000
  78 #define IA64_PSR_IS             0x0000000400000000
  79 #define IA64_PSR_MC             0x0000000800000000
  80 #define IA64_PSR_IT             0x0000001000000000
  81 #define IA64_PSR_ID             0x0000002000000000
  82 #define IA64_PSR_DA             0x0000004000000000
  83 #define IA64_PSR_DD             0x0000008000000000
  84 #define IA64_PSR_SS             0x0000010000000000
  85 #define IA64_PSR_RI             0x0000060000000000
  86 #define IA64_PSR_RI_0           0x0000000000000000
  87 #define IA64_PSR_RI_1           0x0000020000000000
  88 #define IA64_PSR_RI_2           0x0000040000000000
  89 #define IA64_PSR_ED             0x0000080000000000
  90 #define IA64_PSR_BN             0x0000100000000000
  91 #define IA64_PSR_IA             0x0000200000000000
  92
  93 /*
  94  * Definition of ISR bits.
  95  */
  96 #define IA64_ISR_CODE           0x000000000000ffff
  97 #define IA64_ISR_VECTOR         0x0000000000ff0000
  98 #define IA64_ISR_X              0x0000000100000000
  99 #define IA64_ISR_W              0x0000000200000000
 100 #define IA64_ISR_R              0x0000000400000000
 101 #define IA64_ISR_NA             0x0000000800000000
 102 #define IA64_ISR_SP             0x0000001000000000
 103 #define IA64_ISR_RS             0x0000002000000000
 104 #define IA64_ISR_IR             0x0000004000000000
 105 #define IA64_ISR_NI             0x0000008000000000
 106 #define IA64_ISR_SO             0x0000010000000000
 107 #define IA64_ISR_EI             0x0000060000000000
 108 #define IA64_ISR_EI_0           0x0000000000000000
 109 #define IA64_ISR_EI_1           0x0000020000000000
 110 #define IA64_ISR_EI_2           0x0000040000000000
 111 #define IA64_ISR_ED             0x0000080000000000
 112
 113 /*
 114  * Vector numbers for various ia64 interrupts.
 115  */
 116 #define IA64_VEC_VHPT                   0
 117 #define IA64_VEC_ITLB                   1
 118 #define IA64_VEC_DTLB                   2
 119 #define IA64_VEC_ALT_ITLB               3
 120 #define IA64_VEC_ALT_DTLB               4
 121 #define IA64_VEC_NESTED_DTLB            5
 122 #define IA64_VEC_IKEY_MISS              6
 123 #define IA64_VEC_DKEY_MISS              7
 124 #define IA64_VEC_DIRTY_BIT              8
 125 #define IA64_VEC_INST_ACCESS            9
 126 #define IA64_VEC_DATA_ACCESS            10
 127 #define IA64_VEC_BREAK                  11
 128 #define IA64_VEC_EXT_INTR               12
 129 #define IA64_VEC_PAGE_NOT_PRESENT       20
 130 #define IA64_VEC_KEY_PERMISSION         21
 131 #define IA64_VEC_INST_ACCESS_RIGHTS     22
 132 #define IA64_VEC_DATA_ACCESS_RIGHTS     23
 133 #define IA64_VEC_GENERAL_EXCEPTION      24
 134 #define IA64_VEC_DISABLED_FP            25
 135 #define IA64_VEC_NAT_CONSUMPTION        26
 136 #define IA64_VEC_SPECULATION            27
 137 #define IA64_VEC_DEBUG                  29
 138 #define IA64_VEC_UNALIGNED_REFERENCE    30
 139 #define IA64_VEC_UNSUPP_DATA_REFERENCE  31
 140 #define IA64_VEC_FLOATING_POINT_FAULT   32
 141 #define IA64_VEC_FLOATING_POINT_TRAP    33
 142 #define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
 143 #define IA64_VEC_TAKEN_BRANCH_TRAP      35
 144 #define IA64_VEC_SINGLE_STEP_TRAP       36
 145 #define IA64_VEC_IA32_EXCEPTION         45
 146 #define IA64_VEC_IA32_INTERCEPT         46
 147 #define IA64_VEC_IA32_INTERRUPT         47
 148
 149 /*
 150  * IA-32 exceptions.
 151  */
 152 #define IA32_EXCEPTION_DIVIDE           0
 153 #define IA32_EXCEPTION_DEBUG            1
 154 #define IA32_EXCEPTION_BREAK            3
 155 #define IA32_EXCEPTION_OVERFLOW         4
 156 #define IA32_EXCEPTION_BOUND            5
 157 #define IA32_EXCEPTION_DNA              7
 158 #define IA32_EXCEPTION_NOT_PRESENT      11
 159 #define IA32_EXCEPTION_STACK_FAULT      12
 160 #define IA32_EXCEPTION_GPFAULT          13
 161 #define IA32_EXCEPTION_FPERROR          16
 162 #define IA32_EXCEPTION_ALIGNMENT_CHECK  17
 163 #define IA32_EXCEPTION_STREAMING_SIMD   19
 164
 165 #define IA32_INTERCEPT_INSTRUCTION      0
 166 #define IA32_INTERCEPT_GATE             1
 167 #define IA32_INTERCEPT_SYSTEM_FLAG      2
 168 #define IA32_INTERCEPT_LOCK             4
 169
 170 #ifndef LOCORE
 171
 172 /*
 173  * Various special ia64 instructions.
 174  */
 175
 176 /*
 177  * Memory Fence.
 178  */
 179 static __inline void
 180 ia64_mf(void)
 181 {
 182         __asm __volatile("mf");
 183 }
 184
 185 static __inline void
 186 ia64_mf_a(void)
 187 {
 188         __asm __volatile("mf.a");
 189 }
 190
 191 /*
 192  * Flush Cache.
 193  */
 194 static __inline void
 195 ia64_fc(u_int64_t va)
 196 {
 197         __asm __volatile("fc %0" :: "r"(va));
 198 }
 199
 200 /*
 201  * Sync instruction stream.
 202  */
 203 static __inline void
 204 ia64_sync_i(void)
 205 {
 206         __asm __volatile("sync.i");
 207 }
 208
 209 /*
 210  * Calculate address in VHPT for va.
 211  */
 212 static __inline u_int64_t
 213 ia64_thash(u_int64_t va)
 214 {
 215         u_int64_t result;
 216         __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
 217         return result;
 218 }
 219
 220 /*
 221  * Calculate VHPT tag for va.
 222  */
 223 static __inline u_int64_t
 224 ia64_ttag(u_int64_t va)
 225 {
 226         u_int64_t result;
 227         __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
 228         return result;
 229 }
 230
 231 /*
 232  * Convert virtual address to physical.
 233  */
 234 static __inline u_int64_t
 235 ia64_tpa(u_int64_t va)
 236 {
 237         u_int64_t result;
 238         __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
 239         return result;
 240 }
 241
 242 /*
 243  * Generate a ptc.e instruction.
 244  */
 245 static __inline void
 246 ia64_ptc_e(u_int64_t v)
 247 {
 248         __asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v));
 249 }
 250
 251 /*
 252  * Generate a ptc.g instruction.
 253  */
 254 static __inline void
 255 ia64_ptc_g(u_int64_t va, u_int64_t log2size)
 256 {
 257         __asm __volatile("ptc.g %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 258 }
 259
 260 /*
 261  * Generate a ptc.ga instruction.
 262  */
 263 static __inline void
 264 ia64_ptc_ga(u_int64_t va, u_int64_t log2size)
 265 {
 266         __asm __volatile("ptc.ga %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 267 }
 268
 269 /*
 270  * Generate a ptc.l instruction.
 271  */
 272 static __inline void
 273 ia64_ptc_l(u_int64_t va, u_int64_t log2size)
 274 {
 275         __asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size));
 276 }
 277
 278 /*
 279  * Read the value of psr.
 280  */
 281 static __inline u_int64_t
 282 ia64_get_psr(void)
 283 {
 284         u_int64_t result;
 285         __asm __volatile("mov %0=psr;;" : "=r" (result));
 286         return result;
 287 }
 288
 289 /*
 290  * Define accessors for application registers.
 291  */
 292
 293 #define IA64_AR(name)                                           \
 294                                                                 \
 295 static __inline u_int64_t                                       \
 296 ia64_get_##name(void)                                           \
 297 {                                                               \
 298         u_int64_t result;                                       \
 299         __asm __volatile("mov %0=ar." #name : "=r" (result));   \
 300         return result;                                          \
 301 }                                                               \
 302                                                                 \
 303 static __inline void                                            \
 304 ia64_set_##name(u_int64_t v)                                    \
 305 {                                                               \
 306         __asm __volatile("mov ar." #name "=%0;;" :: "r" (v));   \
 307 }
 308
 309 IA64_AR(k0)
 310 IA64_AR(k1)
 311 IA64_AR(k2)
 312 IA64_AR(k3)
 313 IA64_AR(k4)
 314 IA64_AR(k5)
 315 IA64_AR(k6)
 316 IA64_AR(k7)
 317
 318 IA64_AR(rsc)
 319 IA64_AR(bsp)
 320 IA64_AR(bspstore)
 321 IA64_AR(rnat)
 322
 323 IA64_AR(fcr)
 324
 325 IA64_AR(eflag)
 326 IA64_AR(csd)
 327 IA64_AR(ssd)
 328 IA64_AR(cflg)
 329 IA64_AR(fsr)
 330 IA64_AR(fir)
 331 IA64_AR(fdr)
 332
 333 IA64_AR(ccv)
 334
 335 IA64_AR(unat)
 336
 337 IA64_AR(fpsr)
 338
 339 IA64_AR(itc)
 340
 341 IA64_AR(pfs)
 342 IA64_AR(lc)
 343 IA64_AR(ec)
 344
 345 /*
 346  * Define accessors for control registers.
 347  */
 348
 349 #define IA64_CR(name)                                           \
 350                                                                 \
 351 static __inline u_int64_t                                       \
 352 ia64_get_##name(void)                                           \
 353 {                                                               \
 354         u_int64_t result;                                       \
 355         __asm __volatile("mov %0=cr." #name : "=r" (result));   \
 356         return result;                                          \
 357 }                                                               \
 358                                                                 \
 359 static __inline void                                            \
 360 ia64_set_##name(u_int64_t v)                                    \
 361 {                                                               \
 362         __asm __volatile("mov cr." #name "=%0;;" :: "r" (v));   \
 363 }
 364
 365 IA64_CR(dcr)
 366 IA64_CR(itm)
 367 IA64_CR(iva)
 368
 369 IA64_CR(pta)
 370
 371 IA64_CR(ipsr)
 372 IA64_CR(isr)
 373
 374 IA64_CR(iip)
 375 IA64_CR(ifa)
 376 IA64_CR(itir)
 377 IA64_CR(iipa)
 378 IA64_CR(ifs)
 379 IA64_CR(iim)
 380 IA64_CR(iha)
 381
 382 IA64_CR(lid)
 383 IA64_CR(ivr)
 384 IA64_CR(tpr)
 385 IA64_CR(eoi)
 386 IA64_CR(irr0)
 387 IA64_CR(irr1)
 388 IA64_CR(irr2)
 389 IA64_CR(irr3)
 390 IA64_CR(itv)
 391 IA64_CR(pmv)
 392 IA64_CR(cmcv)
 393
 394 IA64_CR(lrr0)
 395 IA64_CR(lrr1)
 396
 397 /*
 398  * Write a region register.
 399  */
 400 static __inline void
 401 ia64_set_rr(u_int64_t rrbase, u_int64_t v)
 402 {
 403         __asm __volatile("mov rr[%0]=%1"
 404                          :: "r"(rrbase), "r"(v) : "memory");
 405 }
 406
 407 /*
 408  * Read a CPUID register.
 409  */
 410 static __inline u_int64_t
 411 ia64_get_cpuid(int i)
 412 {
 413         u_int64_t result;
 414         __asm __volatile("mov %0=cpuid[%1]"
 415                          : "=r" (result) : "r"(i));
 416         return result;
 417 }
 418
 419 static __inline void
 420 ia64_disable_highfp(void)
 421 {
 422         __asm __volatile("ssm psr.dfh;; srlz.d");
 423 }
 424
 425 static __inline void
 426 ia64_enable_highfp(void)
 427 {
 428         __asm __volatile("rsm psr.dfh;; srlz.d");
 429 }
 430
 431 static __inline void
 432 ia64_srlz_d(void)
 433 {
 434         __asm __volatile("srlz.d");
 435 }
 436
 437 static __inline void
 438 ia64_srlz_i(void)
 439 {
 440         __asm __volatile("srlz.i;;");
 441 }
 442
 443 #endif /* !LOCORE */
 444
 445 #endif /* _MACHINE_IA64_CPU_H_ */
 446