Bindings/iommu/renesas,ipmmu-vmsa.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas VMSA-Compatible IOMMU
   8
   9 maintainers:
  10   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  11
  12 description:
  13   The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
  14   It provides address translation for bus masters outside of the CPU, each
  15   connected to the IPMMU through a port called micro-TLB.
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - items:
  21           - enum:
  22               - renesas,ipmmu-r8a73a4  # R-Mobile APE6
  23               - renesas,ipmmu-r8a7743  # RZ/G1M
  24               - renesas,ipmmu-r8a7744  # RZ/G1N
  25               - renesas,ipmmu-r8a7745  # RZ/G1E
  26               - renesas,ipmmu-r8a7790  # R-Car H2
  27               - renesas,ipmmu-r8a7791  # R-Car M2-W
  28               - renesas,ipmmu-r8a7793  # R-Car M2-N
  29               - renesas,ipmmu-r8a7794  # R-Car E2
  30           - const: renesas,ipmmu-vmsa  # R-Mobile APE6 or R-Car Gen2 or RZ/G1
  31       - items:
  32           - enum:
  33               - renesas,ipmmu-r8a774a1 # RZ/G2M
  34               - renesas,ipmmu-r8a774b1 # RZ/G2N
  35               - renesas,ipmmu-r8a774c0 # RZ/G2E
  36               - renesas,ipmmu-r8a7795  # R-Car H3
  37               - renesas,ipmmu-r8a7796  # R-Car M3-W
  38               - renesas,ipmmu-r8a77965 # R-Car M3-N
  39               - renesas,ipmmu-r8a77970 # R-Car V3M
  40               - renesas,ipmmu-r8a77980 # R-Car V3H
  41               - renesas,ipmmu-r8a77990 # R-Car E3
  42               - renesas,ipmmu-r8a77995 # R-Car D3
  43
  44   reg:
  45     maxItems: 1
  46
  47   interrupts:
  48     minItems: 1
  49     maxItems: 2
  50     description:
  51       Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
  52     items:
  53       - description: non-secure mode
  54       - description: secure mode if supported
  55
  56   '#iommu-cells':
  57     const: 1
  58     description:
  59       The number of the micro-TLB that the device is connected to.
  60
  61   power-domains:
  62     maxItems: 1
  63
  64   renesas,ipmmu-main:
  65     $ref: /schemas/types.yaml#/definitions/phandle-array
  66     description:
  67       Reference to the main IPMMU phandle plus 1 cell. The cell is
  68       the interrupt bit number associated with the particular cache IPMMU
  69       device. The interrupt bit number needs to match the main IPMMU IMSSTR
  70       register. Only used by cache IPMMU instances.
  71
  72 required:
  73   - compatible
  74   - reg
  75   - '#iommu-cells'
  76   - power-domains
  77
  78 oneOf:
  79   - required:
  80       - interrupts
  81   - required:
  82       - renesas,ipmmu-main
  83
  84 additionalProperties: false
  85
  86 examples:
  87   - |
  88     #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
  89     #include <dt-bindings/interrupt-controller/arm-gic.h>
  90     #include <dt-bindings/power/r8a7791-sysc.h>
  91
  92     ipmmu_mx: iommu@fe951000 {
  93         compatible = "renasas,ipmmu-r8a7791", "renasas,ipmmu-vmsa";
  94         reg = <0xfe951000 0x1000>;
  95         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
  96                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  97         #iommu-cells = <1>;
  98     };