1 //===- RegAllocGreedy.cpp - greedy register allocator ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the RAGreedy function pass for register allocation in
13 //===----------------------------------------------------------------------===//
15 #include "AllocationOrder.h"
16 #include "InterferenceCache.h"
17 #include "LiveDebugVariables.h"
18 #include "RegAllocBase.h"
19 #include "SpillPlacement.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/DenseMap.h"
25 #include "llvm/ADT/IndexedMap.h"
26 #include "llvm/ADT/MapVector.h"
27 #include "llvm/ADT/SetVector.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/SmallSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/ADT/StringRef.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
35 #include "llvm/CodeGen/CalcSpillWeights.h"
36 #include "llvm/CodeGen/EdgeBundles.h"
37 #include "llvm/CodeGen/LiveInterval.h"
38 #include "llvm/CodeGen/LiveIntervalUnion.h"
39 #include "llvm/CodeGen/LiveIntervals.h"
40 #include "llvm/CodeGen/LiveRangeEdit.h"
41 #include "llvm/CodeGen/LiveRegMatrix.h"
42 #include "llvm/CodeGen/LiveStacks.h"
43 #include "llvm/CodeGen/MachineBasicBlock.h"
44 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
45 #include "llvm/CodeGen/MachineDominators.h"
46 #include "llvm/CodeGen/MachineFrameInfo.h"
47 #include "llvm/CodeGen/MachineFunction.h"
48 #include "llvm/CodeGen/MachineFunctionPass.h"
49 #include "llvm/CodeGen/MachineInstr.h"
50 #include "llvm/CodeGen/MachineLoopInfo.h"
51 #include "llvm/CodeGen/MachineOperand.h"
52 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/CodeGen/RegAllocRegistry.h"
55 #include "llvm/CodeGen/RegisterClassInfo.h"
56 #include "llvm/CodeGen/SlotIndexes.h"
57 #include "llvm/CodeGen/TargetInstrInfo.h"
58 #include "llvm/CodeGen/TargetRegisterInfo.h"
59 #include "llvm/CodeGen/TargetSubtargetInfo.h"
60 #include "llvm/CodeGen/VirtRegMap.h"
61 #include "llvm/IR/Function.h"
62 #include "llvm/IR/LLVMContext.h"
63 #include "llvm/MC/MCRegisterInfo.h"
64 #include "llvm/Pass.h"
65 #include "llvm/Support/BlockFrequency.h"
66 #include "llvm/Support/BranchProbability.h"
67 #include "llvm/Support/CommandLine.h"
68 #include "llvm/Support/Debug.h"
69 #include "llvm/Support/MathExtras.h"
70 #include "llvm/Support/Timer.h"
71 #include "llvm/Support/raw_ostream.h"
72 #include "llvm/Target/TargetMachine.h"
83 #define DEBUG_TYPE "regalloc"
85 STATISTIC(NumGlobalSplits, "Number of split global live ranges");
86 STATISTIC(NumLocalSplits, "Number of split local live ranges");
87 STATISTIC(NumEvicted, "Number of interferences evicted");
89 static cl::opt<SplitEditor::ComplementSpillMode> SplitSpillMode(
90 "split-spill-mode", cl::Hidden,
91 cl::desc("Spill mode for splitting live ranges"),
92 cl::values(clEnumValN(SplitEditor::SM_Partition, "default", "Default"),
93 clEnumValN(SplitEditor::SM_Size, "size", "Optimize for size"),
94 clEnumValN(SplitEditor::SM_Speed, "speed", "Optimize for speed")),
95 cl::init(SplitEditor::SM_Speed));
97 static cl::opt<unsigned>
98 LastChanceRecoloringMaxDepth("lcr-max-depth", cl::Hidden,
99 cl::desc("Last chance recoloring max depth"),
102 static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
103 "lcr-max-interf", cl::Hidden,
104 cl::desc("Last chance recoloring maximum number of considered"
105 " interference at a time"),
108 static cl::opt<bool> ExhaustiveSearch(
109 "exhaustive-register-search", cl::NotHidden,
110 cl::desc("Exhaustive Search for registers bypassing the depth "
111 "and interference cutoffs of last chance recoloring"),
114 static cl::opt<bool> EnableLocalReassignment(
115 "enable-local-reassign", cl::Hidden,
116 cl::desc("Local reassignment can yield better allocation decisions, but "
117 "may be compile time intensive"),
120 static cl::opt<bool> EnableDeferredSpilling(
121 "enable-deferred-spilling", cl::Hidden,
122 cl::desc("Instead of spilling a variable right away, defer the actual "
123 "code insertion to the end of the allocation. That way the "
124 "allocator might still find a suitable coloring for this "
125 "variable because of other evicted variables."),
128 // FIXME: Find a good default for this flag and remove the flag.
129 static cl::opt<unsigned>
130 CSRFirstTimeCost("regalloc-csr-first-time-cost",
131 cl::desc("Cost for first time use of callee-saved register."),
132 cl::init(0), cl::Hidden);
134 static cl::opt<bool> ConsiderLocalIntervalCost(
135 "condsider-local-interval-cost", cl::Hidden,
136 cl::desc("Consider the cost of local intervals created by a split "
137 "candidate when choosing the best split candidate."),
140 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
141 createGreedyRegisterAllocator);
145 class RAGreedy : public MachineFunctionPass,
147 private LiveRangeEdit::Delegate {
148 // Convenient shortcuts.
149 using PQueue = std::priority_queue<std::pair<unsigned, unsigned>>;
150 using SmallLISet = SmallPtrSet<LiveInterval *, 4>;
151 using SmallVirtRegSet = SmallSet<unsigned, 16>;
156 // Shortcuts to some useful interface.
157 const TargetInstrInfo *TII;
158 const TargetRegisterInfo *TRI;
159 RegisterClassInfo RCI;
162 SlotIndexes *Indexes;
163 MachineBlockFrequencyInfo *MBFI;
164 MachineDominatorTree *DomTree;
165 MachineLoopInfo *Loops;
166 MachineOptimizationRemarkEmitter *ORE;
167 EdgeBundles *Bundles;
168 SpillPlacement *SpillPlacer;
169 LiveDebugVariables *DebugVars;
173 std::unique_ptr<Spiller> SpillerInstance;
175 unsigned NextCascade;
177 // Live ranges pass through a number of stages as we try to allocate them.
178 // Some of the stages may also create new live ranges:
180 // - Region splitting.
181 // - Per-block splitting.
182 // - Local splitting.
185 // Ranges produced by one of the stages skip the previous stages when they are
186 // dequeued. This improves performance because we can skip interference checks
187 // that are unlikely to give any results. It also guarantees that the live
188 // range splitting algorithm terminates, something that is otherwise hard to
190 enum LiveRangeStage {
191 /// Newly created live range that has never been queued.
194 /// Only attempt assignment and eviction. Then requeue as RS_Split.
197 /// Attempt live range splitting if assignment is impossible.
200 /// Attempt more aggressive live range splitting that is guaranteed to make
201 /// progress. This is used for split products that may not be making
205 /// Live range will be spilled. No more splitting will be attempted.
209 /// Live range is in memory. Because of other evictions, it might get moved
210 /// in a register in the end.
213 /// There is nothing more we can do to this live range. Abort compilation
214 /// if it can't be assigned.
218 // Enum CutOffStage to keep a track whether the register allocation failed
219 // because of the cutoffs encountered in last chance recoloring.
220 // Note: This is used as bitmask. New value should be next power of 2.
222 // No cutoffs encountered
225 // lcr-max-depth cutoff encountered
228 // lcr-max-interf cutoff encountered
235 static const char *const StageName[];
238 // RegInfo - Keep additional information about each live range.
240 LiveRangeStage Stage = RS_New;
242 // Cascade - Eviction loop prevention. See canEvictInterference().
243 unsigned Cascade = 0;
248 IndexedMap<RegInfo, VirtReg2IndexFunctor> ExtraRegInfo;
250 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
251 return ExtraRegInfo[VirtReg.reg].Stage;
254 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
255 ExtraRegInfo.resize(MRI->getNumVirtRegs());
256 ExtraRegInfo[VirtReg.reg].Stage = Stage;
259 template<typename Iterator>
260 void setStage(Iterator Begin, Iterator End, LiveRangeStage NewStage) {
261 ExtraRegInfo.resize(MRI->getNumVirtRegs());
262 for (;Begin != End; ++Begin) {
263 unsigned Reg = *Begin;
264 if (ExtraRegInfo[Reg].Stage == RS_New)
265 ExtraRegInfo[Reg].Stage = NewStage;
269 /// Cost of evicting interference.
270 struct EvictionCost {
271 unsigned BrokenHints = 0; ///< Total number of broken hints.
272 float MaxWeight = 0; ///< Maximum spill weight evicted.
274 EvictionCost() = default;
276 bool isMax() const { return BrokenHints == ~0u; }
278 void setMax() { BrokenHints = ~0u; }
280 void setBrokenHints(unsigned NHints) { BrokenHints = NHints; }
282 bool operator<(const EvictionCost &O) const {
283 return std::tie(BrokenHints, MaxWeight) <
284 std::tie(O.BrokenHints, O.MaxWeight);
288 /// EvictionTrack - Keeps track of past evictions in order to optimize region
290 class EvictionTrack {
294 std::pair<unsigned /* evictor */, unsigned /* physreg */>;
295 using EvicteeInfo = llvm::MapVector<unsigned /* evictee */, EvictorInfo>;
298 /// Each Vreg that has been evicted in the last stage of selectOrSplit will
299 /// be mapped to the evictor Vreg and the PhysReg it was evicted from.
300 EvicteeInfo Evictees;
303 /// \brief Clear all eviction information.
304 void clear() { Evictees.clear(); }
306 /// \brief Clear eviction information for the given evictee Vreg.
307 /// E.g. when Vreg get's a new allocation, the old eviction info is no
309 /// \param Evictee The evictee Vreg for whom we want to clear collected
311 void clearEvicteeInfo(unsigned Evictee) { Evictees.erase(Evictee); }
313 /// \brief Track new eviction.
314 /// The Evictor vreg has evicted the Evictee vreg from Physreg.
315 /// \praram PhysReg The phisical register Evictee was evicted from.
316 /// \praram Evictor The evictor Vreg that evicted Evictee.
317 /// \praram Evictee The evictee Vreg.
318 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) {
319 Evictees[Evictee].first = Evictor;
320 Evictees[Evictee].second = PhysReg;
323 /// Return the Evictor Vreg which evicted Evictee Vreg from PhysReg.
324 /// \praram Evictee The evictee vreg.
325 /// \return The Evictor vreg which evicted Evictee vreg from PhysReg. 0 if
326 /// nobody has evicted Evictee from PhysReg.
327 EvictorInfo getEvictor(unsigned Evictee) {
328 if (Evictees.count(Evictee)) {
329 return Evictees[Evictee];
332 return EvictorInfo(0, 0);
336 // Keeps track of past evictions in order to optimize region split decision.
337 EvictionTrack LastEvicted;
340 std::unique_ptr<SplitAnalysis> SA;
341 std::unique_ptr<SplitEditor> SE;
343 /// Cached per-block interference maps
344 InterferenceCache IntfCache;
346 /// All basic blocks where the current register has uses.
347 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
349 /// Global live range splitting candidate info.
350 struct GlobalSplitCandidate {
351 // Register intended for assignment, or 0.
354 // SplitKit interval index for this candidate.
357 // Interference for PhysReg.
358 InterferenceCache::Cursor Intf;
360 // Bundles where this candidate should be live.
361 BitVector LiveBundles;
362 SmallVector<unsigned, 8> ActiveBlocks;
364 void reset(InterferenceCache &Cache, unsigned Reg) {
367 Intf.setPhysReg(Cache, Reg);
369 ActiveBlocks.clear();
372 // Set B[i] = C for every live bundle where B[i] was NoCand.
373 unsigned getBundles(SmallVectorImpl<unsigned> &B, unsigned C) {
375 for (unsigned i : LiveBundles.set_bits())
376 if (B[i] == NoCand) {
384 /// Candidate info for each PhysReg in AllocationOrder.
385 /// This vector never shrinks, but grows to the size of the largest register
387 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
389 enum : unsigned { NoCand = ~0u };
391 /// Candidate map. Each edge bundle is assigned to a GlobalCand entry, or to
392 /// NoCand which indicates the stack interval.
393 SmallVector<unsigned, 32> BundleCand;
395 /// Callee-save register cost, calculated once per machine function.
396 BlockFrequency CSRCost;
398 /// Run or not the local reassignment heuristic. This information is
399 /// obtained from the TargetSubtargetInfo.
400 bool EnableLocalReassign;
402 /// Enable or not the the consideration of the cost of local intervals created
403 /// by a split candidate when choosing the best split candidate.
404 bool EnableAdvancedRASplitCost;
406 /// Set of broken hints that may be reconciled later because of eviction.
407 SmallSetVector<LiveInterval *, 8> SetOfBrokenHints;
412 /// Return the pass name.
413 StringRef getPassName() const override { return "Greedy Register Allocator"; }
415 /// RAGreedy analysis usage.
416 void getAnalysisUsage(AnalysisUsage &AU) const override;
417 void releaseMemory() override;
418 Spiller &spiller() override { return *SpillerInstance; }
419 void enqueue(LiveInterval *LI) override;
420 LiveInterval *dequeue() override;
421 unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
422 void aboutToRemoveInterval(LiveInterval &) override;
424 /// Perform register allocation.
425 bool runOnMachineFunction(MachineFunction &mf) override;
427 MachineFunctionProperties getRequiredProperties() const override {
428 return MachineFunctionProperties().set(
429 MachineFunctionProperties::Property::NoPHIs);
435 unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
436 SmallVirtRegSet &, unsigned = 0);
438 bool LRE_CanEraseVirtReg(unsigned) override;
439 void LRE_WillShrinkVirtReg(unsigned) override;
440 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
441 void enqueue(PQueue &CurQueue, LiveInterval *LI);
442 LiveInterval *dequeue(PQueue &CurQueue);
444 BlockFrequency calcSpillCost();
445 bool addSplitConstraints(InterferenceCache::Cursor, BlockFrequency&);
446 void addThroughConstraints(InterferenceCache::Cursor, ArrayRef<unsigned>);
447 void growRegion(GlobalSplitCandidate &Cand);
448 bool splitCanCauseEvictionChain(unsigned Evictee, GlobalSplitCandidate &Cand,
450 const AllocationOrder &Order);
451 BlockFrequency calcGlobalSplitCost(GlobalSplitCandidate &,
452 const AllocationOrder &Order,
453 bool *CanCauseEvictionChain);
454 bool calcCompactRegion(GlobalSplitCandidate&);
455 void splitAroundRegion(LiveRangeEdit&, ArrayRef<unsigned>);
456 void calcGapWeights(unsigned, SmallVectorImpl<float>&);
457 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
458 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
459 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
460 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
461 SlotIndex Start, SlotIndex End,
462 EvictionCost &MaxCost);
463 unsigned getCheapestEvicteeWeight(const AllocationOrder &Order,
464 LiveInterval &VirtReg, SlotIndex Start,
465 SlotIndex End, float *BestEvictWeight);
466 void evictInterference(LiveInterval&, unsigned,
467 SmallVectorImpl<unsigned>&);
468 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
469 SmallLISet &RecoloringCandidates,
470 const SmallVirtRegSet &FixedRegisters);
472 unsigned tryAssign(LiveInterval&, AllocationOrder&,
473 SmallVectorImpl<unsigned>&);
474 unsigned tryEvict(LiveInterval&, AllocationOrder&,
475 SmallVectorImpl<unsigned>&, unsigned = ~0u);
476 unsigned tryRegionSplit(LiveInterval&, AllocationOrder&,
477 SmallVectorImpl<unsigned>&);
478 /// Calculate cost of region splitting.
479 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
480 AllocationOrder &Order,
481 BlockFrequency &BestCost,
482 unsigned &NumCands, bool IgnoreCSR,
483 bool *CanCauseEvictionChain = nullptr);
484 /// Perform region splitting.
485 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
487 SmallVectorImpl<unsigned> &NewVRegs);
488 /// Check other options before using a callee-saved register for the first
490 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
491 unsigned PhysReg, unsigned &CostPerUseLimit,
492 SmallVectorImpl<unsigned> &NewVRegs);
493 void initializeCSRCost();
494 unsigned tryBlockSplit(LiveInterval&, AllocationOrder&,
495 SmallVectorImpl<unsigned>&);
496 unsigned tryInstructionSplit(LiveInterval&, AllocationOrder&,
497 SmallVectorImpl<unsigned>&);
498 unsigned tryLocalSplit(LiveInterval&, AllocationOrder&,
499 SmallVectorImpl<unsigned>&);
500 unsigned trySplit(LiveInterval&, AllocationOrder&,
501 SmallVectorImpl<unsigned>&);
502 unsigned tryLastChanceRecoloring(LiveInterval &, AllocationOrder &,
503 SmallVectorImpl<unsigned> &,
504 SmallVirtRegSet &, unsigned);
505 bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<unsigned> &,
506 SmallVirtRegSet &, unsigned);
507 void tryHintRecoloring(LiveInterval &);
508 void tryHintsRecoloring();
510 /// Model the information carried by one end of a copy.
512 /// The frequency of the copy.
514 /// The virtual register or physical register.
516 /// Its currently assigned register.
517 /// In case of a physical register Reg == PhysReg.
520 HintInfo(BlockFrequency Freq, unsigned Reg, unsigned PhysReg)
521 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
523 using HintsInfo = SmallVector<HintInfo, 4>;
525 BlockFrequency getBrokenHintFreq(const HintsInfo &, unsigned);
526 void collectHintInfo(unsigned, HintsInfo &);
528 bool isUnusedCalleeSavedReg(unsigned PhysReg) const;
530 /// Compute and report the number of spills and reloads for a loop.
531 void reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
532 unsigned &FoldedReloads, unsigned &Spills,
533 unsigned &FoldedSpills);
535 /// Report the number of spills and reloads for each loop.
536 void reportNumberOfSplillsReloads() {
537 for (MachineLoop *L : *Loops) {
538 unsigned Reloads, FoldedReloads, Spills, FoldedSpills;
539 reportNumberOfSplillsReloads(L, Reloads, FoldedReloads, Spills,
545 } // end anonymous namespace
547 char RAGreedy::ID = 0;
548 char &llvm::RAGreedyID = RAGreedy::ID;
550 INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
551 "Greedy Register Allocator", false, false)
552 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
553 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
554 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
555 INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
556 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
557 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
558 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
559 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
560 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
561 INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
562 INITIALIZE_PASS_DEPENDENCY(EdgeBundles)
563 INITIALIZE_PASS_DEPENDENCY(SpillPlacement)
564 INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
565 INITIALIZE_PASS_END(RAGreedy, "greedy",
566 "Greedy Register Allocator", false, false)
569 const char *const RAGreedy::StageName[] = {
580 // Hysteresis to use when comparing floats.
581 // This helps stabilize decisions based on float comparisons.
582 const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
584 FunctionPass* llvm::createGreedyRegisterAllocator() {
585 return new RAGreedy();
588 RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
591 void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
592 AU.setPreservesCFG();
593 AU.addRequired<MachineBlockFrequencyInfo>();
594 AU.addPreserved<MachineBlockFrequencyInfo>();
595 AU.addRequired<AAResultsWrapperPass>();
596 AU.addPreserved<AAResultsWrapperPass>();
597 AU.addRequired<LiveIntervals>();
598 AU.addPreserved<LiveIntervals>();
599 AU.addRequired<SlotIndexes>();
600 AU.addPreserved<SlotIndexes>();
601 AU.addRequired<LiveDebugVariables>();
602 AU.addPreserved<LiveDebugVariables>();
603 AU.addRequired<LiveStacks>();
604 AU.addPreserved<LiveStacks>();
605 AU.addRequired<MachineDominatorTree>();
606 AU.addPreserved<MachineDominatorTree>();
607 AU.addRequired<MachineLoopInfo>();
608 AU.addPreserved<MachineLoopInfo>();
609 AU.addRequired<VirtRegMap>();
610 AU.addPreserved<VirtRegMap>();
611 AU.addRequired<LiveRegMatrix>();
612 AU.addPreserved<LiveRegMatrix>();
613 AU.addRequired<EdgeBundles>();
614 AU.addRequired<SpillPlacement>();
615 AU.addRequired<MachineOptimizationRemarkEmitterPass>();
616 MachineFunctionPass::getAnalysisUsage(AU);
619 //===----------------------------------------------------------------------===//
620 // LiveRangeEdit delegate methods
621 //===----------------------------------------------------------------------===//
623 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
624 LiveInterval &LI = LIS->getInterval(VirtReg);
625 if (VRM->hasPhys(VirtReg)) {
626 Matrix->unassign(LI);
627 aboutToRemoveInterval(LI);
630 // Unassigned virtreg is probably in the priority queue.
631 // RegAllocBase will erase it after dequeueing.
632 // Nonetheless, clear the live-range so that the debug
633 // dump will show the right state for that VirtReg.
638 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
639 if (!VRM->hasPhys(VirtReg))
642 // Register is assigned, put it back on the queue for reassignment.
643 LiveInterval &LI = LIS->getInterval(VirtReg);
644 Matrix->unassign(LI);
648 void RAGreedy::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
649 // Cloning a register we haven't even heard about yet? Just ignore it.
650 if (!ExtraRegInfo.inBounds(Old))
653 // LRE may clone a virtual register because dead code elimination causes it to
654 // be split into connected components. The new components are much smaller
655 // than the original, so they should get a new chance at being assigned.
656 // same stage as the parent.
657 ExtraRegInfo[Old].Stage = RS_Assign;
658 ExtraRegInfo.grow(New);
659 ExtraRegInfo[New] = ExtraRegInfo[Old];
662 void RAGreedy::releaseMemory() {
663 SpillerInstance.reset();
664 ExtraRegInfo.clear();
668 void RAGreedy::enqueue(LiveInterval *LI) { enqueue(Queue, LI); }
670 void RAGreedy::enqueue(PQueue &CurQueue, LiveInterval *LI) {
671 // Prioritize live ranges by size, assigning larger ranges first.
672 // The queue holds (size, reg) pairs.
673 const unsigned Size = LI->getSize();
674 const unsigned Reg = LI->reg;
675 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
676 "Can only enqueue virtual registers");
679 ExtraRegInfo.grow(Reg);
680 if (ExtraRegInfo[Reg].Stage == RS_New)
681 ExtraRegInfo[Reg].Stage = RS_Assign;
683 if (ExtraRegInfo[Reg].Stage == RS_Split) {
684 // Unsplit ranges that couldn't be allocated immediately are deferred until
685 // everything else has been allocated.
687 } else if (ExtraRegInfo[Reg].Stage == RS_Memory) {
688 // Memory operand should be considered last.
689 // Change the priority such that Memory operand are assigned in
690 // the reverse order that they came in.
691 // TODO: Make this a member variable and probably do something about hints.
692 static unsigned MemOp = 0;
695 // Giant live ranges fall back to the global assignment heuristic, which
696 // prevents excessive spilling in pathological cases.
697 bool ReverseLocal = TRI->reverseLocalAssignment();
698 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
699 bool ForceGlobal = !ReverseLocal &&
700 (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs());
702 if (ExtraRegInfo[Reg].Stage == RS_Assign && !ForceGlobal && !LI->empty() &&
703 LIS->intervalIsInOneMBB(*LI)) {
704 // Allocate original local ranges in linear instruction order. Since they
705 // are singly defined, this produces optimal coloring in the absence of
706 // global interference and other constraints.
708 Prio = LI->beginIndex().getInstrDistance(Indexes->getLastIndex());
710 // Allocating bottom up may allow many short LRGs to be assigned first
711 // to one of the cheap registers. This could be much faster for very
712 // large blocks on targets with many physical registers.
713 Prio = Indexes->getZeroIndex().getInstrDistance(LI->endIndex());
715 Prio |= RC.AllocationPriority << 24;
717 // Allocate global and split ranges in long->short order. Long ranges that
718 // don't fit should be spilled (or split) ASAP so they don't create
719 // interference. Mark a bit to prioritize global above local ranges.
720 Prio = (1u << 29) + Size;
722 // Mark a higher bit to prioritize global and local above RS_Split.
725 // Boost ranges that have a physical register hint.
726 if (VRM->hasKnownPreference(Reg))
729 // The virtual register number is a tie breaker for same-sized ranges.
730 // Give lower vreg numbers higher priority to assign them first.
731 CurQueue.push(std::make_pair(Prio, ~Reg));
734 LiveInterval *RAGreedy::dequeue() { return dequeue(Queue); }
736 LiveInterval *RAGreedy::dequeue(PQueue &CurQueue) {
737 if (CurQueue.empty())
739 LiveInterval *LI = &LIS->getInterval(~CurQueue.top().second);
744 //===----------------------------------------------------------------------===//
746 //===----------------------------------------------------------------------===//
748 /// tryAssign - Try to assign VirtReg to an available register.
749 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg,
750 AllocationOrder &Order,
751 SmallVectorImpl<unsigned> &NewVRegs) {
754 while ((PhysReg = Order.next()))
755 if (!Matrix->checkInterference(VirtReg, PhysReg))
757 if (!PhysReg || Order.isHint())
760 // PhysReg is available, but there may be a better choice.
762 // If we missed a simple hint, try to cheaply evict interference from the
763 // preferred register.
764 if (unsigned Hint = MRI->getSimpleHint(VirtReg.reg))
765 if (Order.isHint(Hint)) {
766 DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n');
767 EvictionCost MaxCost;
768 MaxCost.setBrokenHints(1);
769 if (canEvictInterference(VirtReg, Hint, true, MaxCost)) {
770 evictInterference(VirtReg, Hint, NewVRegs);
773 // Record the missed hint, we may be able to recover
774 // at the end if the surrounding allocation changed.
775 SetOfBrokenHints.insert(&VirtReg);
778 // Try to evict interference from a cheaper alternative.
779 unsigned Cost = TRI->getCostPerUse(PhysReg);
781 // Most registers have 0 additional cost.
785 DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " << Cost
787 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
788 return CheapReg ? CheapReg : PhysReg;
791 //===----------------------------------------------------------------------===//
792 // Interference eviction
793 //===----------------------------------------------------------------------===//
795 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) {
796 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
798 while ((PhysReg = Order.next())) {
799 if (PhysReg == PrevReg)
802 MCRegUnitIterator Units(PhysReg, TRI);
803 for (; Units.isValid(); ++Units) {
804 // Instantiate a "subquery", not to be confused with the Queries array.
805 LiveIntervalUnion::Query subQ(VirtReg, Matrix->getLiveUnions()[*Units]);
806 if (subQ.checkInterference())
809 // If no units have interference, break out with the current PhysReg.
810 if (!Units.isValid())
814 DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
815 << printReg(PrevReg, TRI) << " to " << printReg(PhysReg, TRI)
820 /// shouldEvict - determine if A should evict the assigned live range B. The
821 /// eviction policy defined by this function together with the allocation order
822 /// defined by enqueue() decides which registers ultimately end up being split
825 /// Cascade numbers are used to prevent infinite loops if this function is a
828 /// @param A The live range to be assigned.
829 /// @param IsHint True when A is about to be assigned to its preferred
831 /// @param B The live range to be evicted.
832 /// @param BreaksHint True when B is already assigned to its preferred register.
833 bool RAGreedy::shouldEvict(LiveInterval &A, bool IsHint,
834 LiveInterval &B, bool BreaksHint) {
835 bool CanSplit = getStage(B) < RS_Spill;
837 // Be fairly aggressive about following hints as long as the evictee can be
839 if (CanSplit && IsHint && !BreaksHint)
842 if (A.weight > B.weight) {
843 DEBUG(dbgs() << "should evict: " << B << " w= " << B.weight << '\n');
849 /// canEvictInterference - Return true if all interferences between VirtReg and
850 /// PhysReg can be evicted.
852 /// @param VirtReg Live range that is about to be assigned.
853 /// @param PhysReg Desired register for assignment.
854 /// @param IsHint True when PhysReg is VirtReg's preferred register.
855 /// @param MaxCost Only look for cheaper candidates and update with new cost
856 /// when returning true.
857 /// @returns True when interference can be evicted cheaper than MaxCost.
858 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg,
859 bool IsHint, EvictionCost &MaxCost) {
860 // It is only possible to evict virtual register interference.
861 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
864 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
866 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
867 // involved in an eviction before. If a cascade number was assigned, deny
868 // evicting anything with the same or a newer cascade number. This prevents
869 // infinite eviction loops.
871 // This works out so a register without a cascade number is allowed to evict
872 // anything, and it can be evicted by anything.
873 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
875 Cascade = NextCascade;
878 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
879 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
880 // If there is 10 or more interferences, chances are one is heavier.
881 if (Q.collectInterferingVRegs(10) >= 10)
884 // Check if any interfering live range is heavier than MaxWeight.
885 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
886 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
887 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
888 "Only expecting virtual register interference from query");
889 // Never evict spill products. They cannot split or spill.
890 if (getStage(*Intf) == RS_Done)
892 // Once a live range becomes small enough, it is urgent that we find a
893 // register for it. This is indicated by an infinite spill weight. These
894 // urgent live ranges get to evict almost anything.
896 // Also allow urgent evictions of unspillable ranges from a strictly
897 // larger allocation order.
898 bool Urgent = !VirtReg.isSpillable() &&
899 (Intf->isSpillable() ||
900 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
901 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
902 // Only evict older cascades or live ranges without a cascade.
903 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
904 if (Cascade <= IntfCascade) {
907 // We permit breaking cascades for urgent evictions. It should be the
908 // last resort, though, so make it really expensive.
909 Cost.BrokenHints += 10;
911 // Would this break a satisfied hint?
912 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
913 // Update eviction cost.
914 Cost.BrokenHints += BreaksHint;
915 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
916 // Abort if this would be too expensive.
917 if (!(Cost < MaxCost))
921 // Apply the eviction policy for non-urgent evictions.
922 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
924 // If !MaxCost.isMax(), then we're just looking for a cheap register.
925 // Evicting another local live range in this case could lead to suboptimal
927 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
928 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
937 /// \brief Return true if all interferences between VirtReg and PhysReg between
938 /// Start and End can be evicted.
940 /// \param VirtReg Live range that is about to be assigned.
941 /// \param PhysReg Desired register for assignment.
942 /// \param Start Start of range to look for interferences.
943 /// \param End End of range to look for interferences.
944 /// \param MaxCost Only look for cheaper candidates and update with new cost
945 /// when returning true.
946 /// \return True when interference can be evicted cheaper than MaxCost.
947 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg,
948 unsigned PhysReg, SlotIndex Start,
950 EvictionCost &MaxCost) {
953 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
954 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
956 // Check if any interfering live range is heavier than MaxWeight.
957 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
958 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
960 // Check if interference overlast the segment in interest.
961 if (!Intf->overlaps(Start, End))
964 // Cannot evict non virtual reg interference.
965 if (!TargetRegisterInfo::isVirtualRegister(Intf->reg))
967 // Never evict spill products. They cannot split or spill.
968 if (getStage(*Intf) == RS_Done)
971 // Would this break a satisfied hint?
972 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
973 // Update eviction cost.
974 Cost.BrokenHints += BreaksHint;
975 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
976 // Abort if this would be too expensive.
977 if (!(Cost < MaxCost))
982 if (Cost.MaxWeight == 0)
989 /// \brief Return tthe physical register that will be best
990 /// candidate for eviction by a local split interval that will be created
991 /// between Start and End.
993 /// \param Order The allocation order
994 /// \param VirtReg Live range that is about to be assigned.
995 /// \param Start Start of range to look for interferences
996 /// \param End End of range to look for interferences
997 /// \param BestEvictweight The eviction cost of that eviction
998 /// \return The PhysReg which is the best candidate for eviction and the
999 /// eviction cost in BestEvictweight
1000 unsigned RAGreedy::getCheapestEvicteeWeight(const AllocationOrder &Order,
1001 LiveInterval &VirtReg,
1002 SlotIndex Start, SlotIndex End,
1003 float *BestEvictweight) {
1004 EvictionCost BestEvictCost;
1005 BestEvictCost.setMax();
1006 BestEvictCost.MaxWeight = VirtReg.weight;
1007 unsigned BestEvicteePhys = 0;
1009 // Go over all physical registers and find the best candidate for eviction
1010 for (auto PhysReg : Order.getOrder()) {
1012 if (!canEvictInterferenceInRange(VirtReg, PhysReg, Start, End,
1017 BestEvicteePhys = PhysReg;
1019 *BestEvictweight = BestEvictCost.MaxWeight;
1020 return BestEvicteePhys;
1023 /// evictInterference - Evict any interferring registers that prevent VirtReg
1024 /// from being assigned to Physreg. This assumes that canEvictInterference
1026 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg,
1027 SmallVectorImpl<unsigned> &NewVRegs) {
1028 // Make sure that VirtReg has a cascade number, and assign that cascade
1029 // number to every evicted register. These live ranges than then only be
1030 // evicted by a newer cascade, preventing infinite loops.
1031 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
1033 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
1035 DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
1036 << " interference: Cascade " << Cascade << '\n');
1038 // Collect all interfering virtregs first.
1039 SmallVector<LiveInterval*, 8> Intfs;
1040 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1041 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1042 // We usually have the interfering VRegs cached so collectInterferingVRegs()
1043 // should be fast, we may need to recalculate if when different physregs
1044 // overlap the same register unit so we had different SubRanges queried
1046 Q.collectInterferingVRegs();
1047 ArrayRef<LiveInterval*> IVR = Q.interferingVRegs();
1048 Intfs.append(IVR.begin(), IVR.end());
1051 // Evict them second. This will invalidate the queries.
1052 for (unsigned i = 0, e = Intfs.size(); i != e; ++i) {
1053 LiveInterval *Intf = Intfs[i];
1054 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
1055 if (!VRM->hasPhys(Intf->reg))
1058 LastEvicted.addEviction(PhysReg, VirtReg.reg, Intf->reg);
1060 Matrix->unassign(*Intf);
1061 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
1062 VirtReg.isSpillable() < Intf->isSpillable()) &&
1063 "Cannot decrease cascade number, illegal eviction");
1064 ExtraRegInfo[Intf->reg].Cascade = Cascade;
1066 NewVRegs.push_back(Intf->reg);
1070 /// Returns true if the given \p PhysReg is a callee saved register and has not
1071 /// been used for allocation yet.
1072 bool RAGreedy::isUnusedCalleeSavedReg(unsigned PhysReg) const {
1073 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
1077 return !Matrix->isPhysRegUsed(PhysReg);
1080 /// tryEvict - Try to evict all interferences for a physreg.
1081 /// @param VirtReg Currently unassigned virtual register.
1082 /// @param Order Physregs to try.
1083 /// @return Physreg to assign VirtReg, or 0.
1084 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
1085 AllocationOrder &Order,
1086 SmallVectorImpl<unsigned> &NewVRegs,
1087 unsigned CostPerUseLimit) {
1088 NamedRegionTimer T("evict", "Evict", TimerGroupName, TimerGroupDescription,
1089 TimePassesIsEnabled);
1091 // Keep track of the cheapest interference seen so far.
1092 EvictionCost BestCost;
1094 unsigned BestPhys = 0;
1095 unsigned OrderLimit = Order.getOrder().size();
1097 // When we are just looking for a reduced cost per use, don't break any
1098 // hints, and only evict smaller spill weights.
1099 if (CostPerUseLimit < ~0u) {
1100 BestCost.BrokenHints = 0;
1101 BestCost.MaxWeight = VirtReg.weight;
1103 // Check of any registers in RC are below CostPerUseLimit.
1104 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
1105 unsigned MinCost = RegClassInfo.getMinCost(RC);
1106 if (MinCost >= CostPerUseLimit) {
1107 DEBUG(dbgs() << TRI->getRegClassName(RC) << " minimum cost = " << MinCost
1108 << ", no cheaper registers to be found.\n");
1112 // It is normal for register classes to have a long tail of registers with
1113 // the same cost. We don't need to look at them if they're too expensive.
1114 if (TRI->getCostPerUse(Order.getOrder().back()) >= CostPerUseLimit) {
1115 OrderLimit = RegClassInfo.getLastCostChange(RC);
1116 DEBUG(dbgs() << "Only trying the first " << OrderLimit << " regs.\n");
1121 while (unsigned PhysReg = Order.next(OrderLimit)) {
1122 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
1124 // The first use of a callee-saved register in a function has cost 1.
1125 // Don't start using a CSR when the CostPerUseLimit is low.
1126 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
1127 DEBUG(dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
1128 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1133 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost))
1139 // Stop if the hint can be used.
1147 evictInterference(VirtReg, BestPhys, NewVRegs);
1151 //===----------------------------------------------------------------------===//
1153 //===----------------------------------------------------------------------===//
1155 /// addSplitConstraints - Fill out the SplitConstraints vector based on the
1156 /// interference pattern in Physreg and its aliases. Add the constraints to
1157 /// SpillPlacement and return the static cost of this split in Cost, assuming
1158 /// that all preferences in SplitConstraints are met.
1159 /// Return false if there are no bundles with positive bias.
1160 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
1161 BlockFrequency &Cost) {
1162 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1164 // Reset interference dependent info.
1165 SplitConstraints.resize(UseBlocks.size());
1166 BlockFrequency StaticCost = 0;
1167 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1168 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1169 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1171 BC.Number = BI.MBB->getNumber();
1172 Intf.moveToBlock(BC.Number);
1173 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
1174 BC.Exit = BI.LiveOut ? SpillPlacement::PrefReg : SpillPlacement::DontCare;
1175 BC.ChangesValue = BI.FirstDef.isValid();
1177 if (!Intf.hasInterference())
1180 // Number of spill code instructions to insert.
1183 // Interference for the live-in value.
1185 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
1186 BC.Entry = SpillPlacement::MustSpill;
1188 } else if (Intf.first() < BI.FirstInstr) {
1189 BC.Entry = SpillPlacement::PrefSpill;
1191 } else if (Intf.first() < BI.LastInstr) {
1196 // Interference for the live-out value.
1198 if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
1199 BC.Exit = SpillPlacement::MustSpill;
1201 } else if (Intf.last() > BI.LastInstr) {
1202 BC.Exit = SpillPlacement::PrefSpill;
1204 } else if (Intf.last() > BI.FirstInstr) {
1209 // Accumulate the total frequency of inserted spill code.
1211 StaticCost += SpillPlacer->getBlockFrequency(BC.Number);
1215 // Add constraints for use-blocks. Note that these are the only constraints
1216 // that may add a positive bias, it is downhill from here.
1217 SpillPlacer->addConstraints(SplitConstraints);
1218 return SpillPlacer->scanActiveBundles();
1221 /// addThroughConstraints - Add constraints and links to SpillPlacer from the
1222 /// live-through blocks in Blocks.
1223 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
1224 ArrayRef<unsigned> Blocks) {
1225 const unsigned GroupSize = 8;
1226 SpillPlacement::BlockConstraint BCS[GroupSize];
1227 unsigned TBS[GroupSize];
1228 unsigned B = 0, T = 0;
1230 for (unsigned i = 0; i != Blocks.size(); ++i) {
1231 unsigned Number = Blocks[i];
1232 Intf.moveToBlock(Number);
1234 if (!Intf.hasInterference()) {
1235 assert(T < GroupSize && "Array overflow");
1237 if (++T == GroupSize) {
1238 SpillPlacer->addLinks(makeArrayRef(TBS, T));
1244 assert(B < GroupSize && "Array overflow");
1245 BCS[B].Number = Number;
1247 // Interference for the live-in value.
1248 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
1249 BCS[B].Entry = SpillPlacement::MustSpill;
1251 BCS[B].Entry = SpillPlacement::PrefSpill;
1253 // Interference for the live-out value.
1254 if (Intf.last() >= SA->getLastSplitPoint(Number))
1255 BCS[B].Exit = SpillPlacement::MustSpill;
1257 BCS[B].Exit = SpillPlacement::PrefSpill;
1259 if (++B == GroupSize) {
1260 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
1265 SpillPlacer->addConstraints(makeArrayRef(BCS, B));
1266 SpillPlacer->addLinks(makeArrayRef(TBS, T));
1269 void RAGreedy::growRegion(GlobalSplitCandidate &Cand) {
1270 // Keep track of through blocks that have not been added to SpillPlacer.
1271 BitVector Todo = SA->getThroughBlocks();
1272 SmallVectorImpl<unsigned> &ActiveBlocks = Cand.ActiveBlocks;
1273 unsigned AddedTo = 0;
1275 unsigned Visited = 0;
1279 ArrayRef<unsigned> NewBundles = SpillPlacer->getRecentPositive();
1280 // Find new through blocks in the periphery of PrefRegBundles.
1281 for (int i = 0, e = NewBundles.size(); i != e; ++i) {
1282 unsigned Bundle = NewBundles[i];
1283 // Look at all blocks connected to Bundle in the full graph.
1284 ArrayRef<unsigned> Blocks = Bundles->getBlocks(Bundle);
1285 for (ArrayRef<unsigned>::iterator I = Blocks.begin(), E = Blocks.end();
1287 unsigned Block = *I;
1288 if (!Todo.test(Block))
1291 // This is a new through block. Add it to SpillPlacer later.
1292 ActiveBlocks.push_back(Block);
1298 // Any new blocks to add?
1299 if (ActiveBlocks.size() == AddedTo)
1302 // Compute through constraints from the interference, or assume that all
1303 // through blocks prefer spilling when forming compact regions.
1304 auto NewBlocks = makeArrayRef(ActiveBlocks).slice(AddedTo);
1306 addThroughConstraints(Cand.Intf, NewBlocks);
1308 // Provide a strong negative bias on through blocks to prevent unwanted
1309 // liveness on loop backedges.
1310 SpillPlacer->addPrefSpill(NewBlocks, /* Strong= */ true);
1311 AddedTo = ActiveBlocks.size();
1313 // Perhaps iterating can enable more bundles?
1314 SpillPlacer->iterate();
1316 DEBUG(dbgs() << ", v=" << Visited);
1319 /// calcCompactRegion - Compute the set of edge bundles that should be live
1320 /// when splitting the current live range into compact regions. Compact
1321 /// regions can be computed without looking at interference. They are the
1322 /// regions formed by removing all the live-through blocks from the live range.
1324 /// Returns false if the current live range is already compact, or if the
1325 /// compact regions would form single block regions anyway.
1326 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
1327 // Without any through blocks, the live range is already compact.
1328 if (!SA->getNumThroughBlocks())
1331 // Compact regions don't correspond to any physreg.
1332 Cand.reset(IntfCache, 0);
1334 DEBUG(dbgs() << "Compact region bundles");
1336 // Use the spill placer to determine the live bundles. GrowRegion pretends
1337 // that all the through blocks have interference when PhysReg is unset.
1338 SpillPlacer->prepare(Cand.LiveBundles);
1340 // The static split cost will be zero since Cand.Intf reports no interference.
1341 BlockFrequency Cost;
1342 if (!addSplitConstraints(Cand.Intf, Cost)) {
1343 DEBUG(dbgs() << ", none.\n");
1348 SpillPlacer->finish();
1350 if (!Cand.LiveBundles.any()) {
1351 DEBUG(dbgs() << ", none.\n");
1356 for (int i : Cand.LiveBundles.set_bits())
1357 dbgs() << " EB#" << i;
1363 /// calcSpillCost - Compute how expensive it would be to split the live range in
1364 /// SA around all use blocks instead of forming bundle regions.
1365 BlockFrequency RAGreedy::calcSpillCost() {
1366 BlockFrequency Cost = 0;
1367 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1368 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1369 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1370 unsigned Number = BI.MBB->getNumber();
1371 // We normally only need one spill instruction - a load or a store.
1372 Cost += SpillPlacer->getBlockFrequency(Number);
1374 // Unless the value is redefined in the block.
1375 if (BI.LiveIn && BI.LiveOut && BI.FirstDef)
1376 Cost += SpillPlacer->getBlockFrequency(Number);
1381 /// \brief Check if splitting Evictee will create a local split interval in
1382 /// basic block number BBNumber that may cause a bad eviction chain. This is
1383 /// intended to prevent bad eviction sequences like:
1384 /// movl %ebp, 8(%esp) # 4-byte Spill
1395 /// movl 16(%esp), %ebp # 4 - byte Reload
1397 /// Such sequences are created in 2 scenarios:
1400 /// %0 is evicted from physreg0 by %1.
1401 /// Evictee %0 is intended for region splitting with split candidate
1402 /// physreg0 (the reg %0 was evicted from).
1403 /// Region splitting creates a local interval because of interference with the
1404 /// evictor %1 (normally region spliitting creates 2 interval, the "by reg"
1405 /// and "by stack" intervals and local interval created when interference
1407 /// One of the split intervals ends up evicting %2 from physreg1.
1408 /// Evictee %2 is intended for region splitting with split candidate
1410 /// One of the split intervals ends up evicting %3 from physreg2, etc.
1413 /// %0 is evicted from physreg0 by %1.
1414 /// %2 is evicted from physreg2 by %3 etc.
1415 /// Evictee %0 is intended for region splitting with split candidate
1417 /// Region splitting creates a local interval because of interference with the
1419 /// One of the split intervals ends up evicting back original evictor %1
1420 /// from physreg0 (the reg %0 was evicted from).
1421 /// Another evictee %2 is intended for region splitting with split candidate
1423 /// One of the split intervals ends up evicting %3 from physreg2, etc.
1425 /// \param Evictee The register considered to be split.
1426 /// \param Cand The split candidate that determines the physical register
1427 /// we are splitting for and the interferences.
1428 /// \param BBNumber The number of a BB for which the region split process will
1429 /// create a local split interval.
1430 /// \param Order The phisical registers that may get evicted by a split
1431 /// artifact of Evictee.
1432 /// \return True if splitting Evictee may cause a bad eviction chain, false
1434 bool RAGreedy::splitCanCauseEvictionChain(unsigned Evictee,
1435 GlobalSplitCandidate &Cand,
1437 const AllocationOrder &Order) {
1438 EvictionTrack::EvictorInfo VregEvictorInfo = LastEvicted.getEvictor(Evictee);
1439 unsigned Evictor = VregEvictorInfo.first;
1440 unsigned PhysReg = VregEvictorInfo.second;
1442 // No actual evictor.
1443 if (!Evictor || !PhysReg)
1446 float MaxWeight = 0;
1447 unsigned FutureEvictedPhysReg =
1448 getCheapestEvicteeWeight(Order, LIS->getInterval(Evictee),
1449 Cand.Intf.first(), Cand.Intf.last(), &MaxWeight);
1451 // The bad eviction chain occurs when either the split candidate the the
1452 // evited reg or one of the split artifact will evict the evicting reg.
1453 if ((PhysReg != Cand.PhysReg) && (PhysReg != FutureEvictedPhysReg))
1456 Cand.Intf.moveToBlock(BBNumber);
1458 // Check to see if the Evictor contains interference (with Evictee) in the
1459 // given BB. If so, this interference caused the eviction of Evictee from
1460 // PhysReg. This suggest that we will create a local interval during the
1461 // region split to avoid this interference This local interval may cause a bad
1463 if (!LIS->hasInterval(Evictor))
1465 LiveInterval &EvictorLI = LIS->getInterval(Evictor);
1466 if (EvictorLI.FindSegmentContaining(Cand.Intf.first()) == EvictorLI.end())
1469 // Now, check to see if the local interval we will create is going to be
1470 // expensive enough to evict somebody If so, this may cause a bad eviction
1472 VirtRegAuxInfo VRAI(*MF, *LIS, VRM, getAnalysis<MachineLoopInfo>(), *MBFI);
1473 float splitArtifactWeight =
1474 VRAI.futureWeight(LIS->getInterval(Evictee),
1475 Cand.Intf.first().getPrevIndex(), Cand.Intf.last());
1476 if (splitArtifactWeight >= 0 && splitArtifactWeight < MaxWeight)
1482 /// calcGlobalSplitCost - Return the global split cost of following the split
1483 /// pattern in LiveBundles. This cost should be added to the local cost of the
1484 /// interference pattern in SplitConstraints.
1486 BlockFrequency RAGreedy::calcGlobalSplitCost(GlobalSplitCandidate &Cand,
1487 const AllocationOrder &Order,
1488 bool *CanCauseEvictionChain) {
1489 BlockFrequency GlobalCost = 0;
1490 const BitVector &LiveBundles = Cand.LiveBundles;
1491 unsigned VirtRegToSplit = SA->getParent().reg;
1492 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1493 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1494 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1495 SpillPlacement::BlockConstraint &BC = SplitConstraints[i];
1496 bool RegIn = LiveBundles[Bundles->getBundle(BC.Number, false)];
1497 bool RegOut = LiveBundles[Bundles->getBundle(BC.Number, true)];
1500 Cand.Intf.moveToBlock(BC.Number);
1501 // Check wheather a local interval is going to be created during the region
1503 if (EnableAdvancedRASplitCost && CanCauseEvictionChain &&
1504 Cand.Intf.hasInterference() && BI.LiveIn && BI.LiveOut && RegIn &&
1507 if (splitCanCauseEvictionChain(VirtRegToSplit, Cand, BC.Number, Order)) {
1508 // This interfernce cause our eviction from this assignment, we might
1509 // evict somebody else, add that cost.
1510 // See splitCanCauseEvictionChain for detailed description of scenarios.
1511 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1512 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1514 *CanCauseEvictionChain = true;
1519 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg);
1521 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg);
1523 GlobalCost += SpillPlacer->getBlockFrequency(BC.Number);
1526 for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) {
1527 unsigned Number = Cand.ActiveBlocks[i];
1528 bool RegIn = LiveBundles[Bundles->getBundle(Number, false)];
1529 bool RegOut = LiveBundles[Bundles->getBundle(Number, true)];
1530 if (!RegIn && !RegOut)
1532 if (RegIn && RegOut) {
1533 // We need double spill code if this block has interference.
1534 Cand.Intf.moveToBlock(Number);
1535 if (Cand.Intf.hasInterference()) {
1536 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1537 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1539 // Check wheather a local interval is going to be created during the
1541 if (EnableAdvancedRASplitCost && CanCauseEvictionChain &&
1542 splitCanCauseEvictionChain(VirtRegToSplit, Cand, Number, Order)) {
1543 // This interfernce cause our eviction from this assignment, we might
1544 // evict somebody else, add that cost.
1545 // See splitCanCauseEvictionChain for detailed description of
1547 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1548 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1550 *CanCauseEvictionChain = true;
1555 // live-in / stack-out or stack-in live-out.
1556 GlobalCost += SpillPlacer->getBlockFrequency(Number);
1561 /// splitAroundRegion - Split the current live range around the regions
1562 /// determined by BundleCand and GlobalCand.
1564 /// Before calling this function, GlobalCand and BundleCand must be initialized
1565 /// so each bundle is assigned to a valid candidate, or NoCand for the
1566 /// stack-bound bundles. The shared SA/SE SplitAnalysis and SplitEditor
1567 /// objects must be initialized for the current live range, and intervals
1568 /// created for the used candidates.
1570 /// @param LREdit The LiveRangeEdit object handling the current split.
1571 /// @param UsedCands List of used GlobalCand entries. Every BundleCand value
1572 /// must appear in this list.
1573 void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
1574 ArrayRef<unsigned> UsedCands) {
1575 // These are the intervals created for new global ranges. We may create more
1576 // intervals for local ranges.
1577 const unsigned NumGlobalIntvs = LREdit.size();
1578 DEBUG(dbgs() << "splitAroundRegion with " << NumGlobalIntvs << " globals.\n");
1579 assert(NumGlobalIntvs && "No global intervals configured");
1581 // Isolate even single instructions when dealing with a proper sub-class.
1582 // That guarantees register class inflation for the stack interval because it
1584 unsigned Reg = SA->getParent().reg;
1585 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1587 // First handle all the blocks with uses.
1588 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1589 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1590 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1591 unsigned Number = BI.MBB->getNumber();
1592 unsigned IntvIn = 0, IntvOut = 0;
1593 SlotIndex IntfIn, IntfOut;
1595 unsigned CandIn = BundleCand[Bundles->getBundle(Number, false)];
1596 if (CandIn != NoCand) {
1597 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1598 IntvIn = Cand.IntvIdx;
1599 Cand.Intf.moveToBlock(Number);
1600 IntfIn = Cand.Intf.first();
1604 unsigned CandOut = BundleCand[Bundles->getBundle(Number, true)];
1605 if (CandOut != NoCand) {
1606 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1607 IntvOut = Cand.IntvIdx;
1608 Cand.Intf.moveToBlock(Number);
1609 IntfOut = Cand.Intf.last();
1613 // Create separate intervals for isolated blocks with multiple uses.
1614 if (!IntvIn && !IntvOut) {
1615 DEBUG(dbgs() << printMBBReference(*BI.MBB) << " isolated.\n");
1616 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1617 SE->splitSingleBlock(BI);
1621 if (IntvIn && IntvOut)
1622 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1624 SE->splitRegInBlock(BI, IntvIn, IntfIn);
1626 SE->splitRegOutBlock(BI, IntvOut, IntfOut);
1629 // Handle live-through blocks. The relevant live-through blocks are stored in
1630 // the ActiveBlocks list with each candidate. We need to filter out
1632 BitVector Todo = SA->getThroughBlocks();
1633 for (unsigned c = 0; c != UsedCands.size(); ++c) {
1634 ArrayRef<unsigned> Blocks = GlobalCand[UsedCands[c]].ActiveBlocks;
1635 for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
1636 unsigned Number = Blocks[i];
1637 if (!Todo.test(Number))
1641 unsigned IntvIn = 0, IntvOut = 0;
1642 SlotIndex IntfIn, IntfOut;
1644 unsigned CandIn = BundleCand[Bundles->getBundle(Number, false)];
1645 if (CandIn != NoCand) {
1646 GlobalSplitCandidate &Cand = GlobalCand[CandIn];
1647 IntvIn = Cand.IntvIdx;
1648 Cand.Intf.moveToBlock(Number);
1649 IntfIn = Cand.Intf.first();
1652 unsigned CandOut = BundleCand[Bundles->getBundle(Number, true)];
1653 if (CandOut != NoCand) {
1654 GlobalSplitCandidate &Cand = GlobalCand[CandOut];
1655 IntvOut = Cand.IntvIdx;
1656 Cand.Intf.moveToBlock(Number);
1657 IntfOut = Cand.Intf.last();
1659 if (!IntvIn && !IntvOut)
1661 SE->splitLiveThroughBlock(Number, IntvIn, IntfIn, IntvOut, IntfOut);
1667 SmallVector<unsigned, 8> IntvMap;
1668 SE->finish(&IntvMap);
1669 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1671 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1672 unsigned OrigBlocks = SA->getNumLiveBlocks();
1674 // Sort out the new intervals created by splitting. We get four kinds:
1675 // - Remainder intervals should not be split again.
1676 // - Candidate intervals can be assigned to Cand.PhysReg.
1677 // - Block-local splits are candidates for local splitting.
1678 // - DCE leftovers should go back on the queue.
1679 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1680 LiveInterval &Reg = LIS->getInterval(LREdit.get(i));
1682 // Ignore old intervals from DCE.
1683 if (getStage(Reg) != RS_New)
1686 // Remainder interval. Don't try splitting again, spill if it doesn't
1688 if (IntvMap[i] == 0) {
1689 setStage(Reg, RS_Spill);
1693 // Global intervals. Allow repeated splitting as long as the number of live
1694 // blocks is strictly decreasing.
1695 if (IntvMap[i] < NumGlobalIntvs) {
1696 if (SA->countLiveBlocks(&Reg) >= OrigBlocks) {
1697 DEBUG(dbgs() << "Main interval covers the same " << OrigBlocks
1698 << " blocks as original.\n");
1699 // Don't allow repeated splitting as a safe guard against looping.
1700 setStage(Reg, RS_Split2);
1705 // Other intervals are treated as new. This includes local intervals created
1706 // for blocks with multiple uses, and anything created by DCE.
1710 MF->verify(this, "After splitting live range around region");
1713 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1714 SmallVectorImpl<unsigned> &NewVRegs) {
1715 unsigned NumCands = 0;
1716 BlockFrequency SpillCost = calcSpillCost();
1717 BlockFrequency BestCost;
1719 // Check if we can split this live range around a compact region.
1720 bool HasCompact = calcCompactRegion(GlobalCand.front());
1722 // Yes, keep GlobalCand[0] as the compact region candidate.
1724 BestCost = BlockFrequency::getMaxFrequency();
1726 // No benefit from the compact region, our fallback will be per-block
1727 // splitting. Make sure we find a solution that is cheaper than spilling.
1728 BestCost = SpillCost;
1729 DEBUG(dbgs() << "Cost of isolating all blocks = ";
1730 MBFI->printBlockFreq(dbgs(), BestCost) << '\n');
1733 bool CanCauseEvictionChain = false;
1735 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands,
1736 false /*IgnoreCSR*/, &CanCauseEvictionChain);
1738 // Split candidates with compact regions can cause a bad eviction sequence.
1739 // See splitCanCauseEvictionChain for detailed description of scenarios.
1740 // To avoid it, we need to comapre the cost with the spill cost and not the
1741 // current max frequency.
1742 if (HasCompact && (BestCost > SpillCost) && (BestCand != NoCand) &&
1743 CanCauseEvictionChain) {
1747 // No solutions found, fall back to single block splitting.
1748 if (!HasCompact && BestCand == NoCand)
1751 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1754 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
1755 AllocationOrder &Order,
1756 BlockFrequency &BestCost,
1757 unsigned &NumCands, bool IgnoreCSR,
1758 bool *CanCauseEvictionChain) {
1759 unsigned BestCand = NoCand;
1761 while (unsigned PhysReg = Order.next()) {
1762 if (IgnoreCSR && isUnusedCalleeSavedReg(PhysReg))
1765 // Discard bad candidates before we run out of interference cache cursors.
1766 // This will only affect register classes with a lot of registers (>32).
1767 if (NumCands == IntfCache.getMaxCursors()) {
1768 unsigned WorstCount = ~0u;
1770 for (unsigned i = 0; i != NumCands; ++i) {
1771 if (i == BestCand || !GlobalCand[i].PhysReg)
1773 unsigned Count = GlobalCand[i].LiveBundles.count();
1774 if (Count < WorstCount) {
1780 GlobalCand[Worst] = GlobalCand[NumCands];
1781 if (BestCand == NumCands)
1785 if (GlobalCand.size() <= NumCands)
1786 GlobalCand.resize(NumCands+1);
1787 GlobalSplitCandidate &Cand = GlobalCand[NumCands];
1788 Cand.reset(IntfCache, PhysReg);
1790 SpillPlacer->prepare(Cand.LiveBundles);
1791 BlockFrequency Cost;
1792 if (!addSplitConstraints(Cand.Intf, Cost)) {
1793 DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1796 DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
1797 MBFI->printBlockFreq(dbgs(), Cost));
1798 if (Cost >= BestCost) {
1800 if (BestCand == NoCand)
1801 dbgs() << " worse than no bundles\n";
1803 dbgs() << " worse than "
1804 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1810 SpillPlacer->finish();
1812 // No live bundles, defer to splitSingleBlocks().
1813 if (!Cand.LiveBundles.any()) {
1814 DEBUG(dbgs() << " no bundles.\n");
1818 bool HasEvictionChain = false;
1819 Cost += calcGlobalSplitCost(Cand, Order, &HasEvictionChain);
1821 dbgs() << ", total = "; MBFI->printBlockFreq(dbgs(), Cost)
1823 for (int i : Cand.LiveBundles.set_bits())
1824 dbgs() << " EB#" << i;
1827 if (Cost < BestCost) {
1828 BestCand = NumCands;
1830 // See splitCanCauseEvictionChain for detailed description of bad
1831 // eviction chain scenarios.
1832 if (CanCauseEvictionChain)
1833 *CanCauseEvictionChain = HasEvictionChain;
1838 if (CanCauseEvictionChain && BestCand != NoCand) {
1839 // See splitCanCauseEvictionChain for detailed description of bad
1840 // eviction chain scenarios.
1841 DEBUG(dbgs() << "Best split candidate of vreg "
1842 << printReg(VirtReg.reg, TRI) << " may ");
1843 if (!(*CanCauseEvictionChain))
1844 DEBUG(dbgs() << "not ");
1845 DEBUG(dbgs() << "cause bad eviction chain\n");
1851 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
1853 SmallVectorImpl<unsigned> &NewVRegs) {
1854 SmallVector<unsigned, 8> UsedCands;
1855 // Prepare split editor.
1856 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1857 SE->reset(LREdit, SplitSpillMode);
1859 // Assign all edge bundles to the preferred candidate, or NoCand.
1860 BundleCand.assign(Bundles->getNumBundles(), NoCand);
1862 // Assign bundles for the best candidate region.
1863 if (BestCand != NoCand) {
1864 GlobalSplitCandidate &Cand = GlobalCand[BestCand];
1865 if (unsigned B = Cand.getBundles(BundleCand, BestCand)) {
1866 UsedCands.push_back(BestCand);
1867 Cand.IntvIdx = SE->openIntv();
1868 DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
1869 << B << " bundles, intv " << Cand.IntvIdx << ".\n");
1874 // Assign bundles for the compact region.
1876 GlobalSplitCandidate &Cand = GlobalCand.front();
1877 assert(!Cand.PhysReg && "Compact region has no physreg");
1878 if (unsigned B = Cand.getBundles(BundleCand, 0)) {
1879 UsedCands.push_back(0);
1880 Cand.IntvIdx = SE->openIntv();
1881 DEBUG(dbgs() << "Split for compact region in " << B << " bundles, intv "
1882 << Cand.IntvIdx << ".\n");
1887 splitAroundRegion(LREdit, UsedCands);
1891 //===----------------------------------------------------------------------===//
1892 // Per-Block Splitting
1893 //===----------------------------------------------------------------------===//
1895 /// tryBlockSplit - Split a global live range around every block with uses. This
1896 /// creates a lot of local live ranges, that will be split by tryLocalSplit if
1897 /// they don't allocate.
1898 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1899 SmallVectorImpl<unsigned> &NewVRegs) {
1900 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
1901 unsigned Reg = VirtReg.reg;
1902 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1903 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1904 SE->reset(LREdit, SplitSpillMode);
1905 ArrayRef<SplitAnalysis::BlockInfo> UseBlocks = SA->getUseBlocks();
1906 for (unsigned i = 0; i != UseBlocks.size(); ++i) {
1907 const SplitAnalysis::BlockInfo &BI = UseBlocks[i];
1908 if (SA->shouldSplitSingleBlock(BI, SingleInstrs))
1909 SE->splitSingleBlock(BI);
1911 // No blocks were split.
1915 // We did split for some blocks.
1916 SmallVector<unsigned, 8> IntvMap;
1917 SE->finish(&IntvMap);
1919 // Tell LiveDebugVariables about the new ranges.
1920 DebugVars->splitRegister(Reg, LREdit.regs(), *LIS);
1922 ExtraRegInfo.resize(MRI->getNumVirtRegs());
1924 // Sort out the new intervals created by splitting. The remainder interval
1925 // goes straight to spilling, the new local ranges get to stay RS_New.
1926 for (unsigned i = 0, e = LREdit.size(); i != e; ++i) {
1927 LiveInterval &LI = LIS->getInterval(LREdit.get(i));
1928 if (getStage(LI) == RS_New && IntvMap[i] == 0)
1929 setStage(LI, RS_Spill);
1933 MF->verify(this, "After splitting live range around basic blocks");
1937 //===----------------------------------------------------------------------===//
1938 // Per-Instruction Splitting
1939 //===----------------------------------------------------------------------===//
1941 /// Get the number of allocatable registers that match the constraints of \p Reg
1942 /// on \p MI and that are also in \p SuperRC.
1943 static unsigned getNumAllocatableRegsForConstraints(
1944 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
1945 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1946 const RegisterClassInfo &RCI) {
1947 assert(SuperRC && "Invalid register class");
1949 const TargetRegisterClass *ConstrainedRC =
1950 MI->getRegClassConstraintEffectForVReg(Reg, SuperRC, TII, TRI,
1951 /* ExploreBundle */ true);
1954 return RCI.getNumAllocatableRegs(ConstrainedRC);
1957 /// tryInstructionSplit - Split a live range around individual instructions.
1958 /// This is normally not worthwhile since the spiller is doing essentially the
1959 /// same thing. However, when the live range is in a constrained register
1960 /// class, it may help to insert copies such that parts of the live range can
1961 /// be moved to a larger register class.
1963 /// This is similar to spilling to a larger register class.
1965 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1966 SmallVectorImpl<unsigned> &NewVRegs) {
1967 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
1968 // There is no point to this if there are no larger sub-classes.
1969 if (!RegClassInfo.isProperSubClass(CurRC))
1972 // Always enable split spill mode, since we're effectively spilling to a
1974 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
1975 SE->reset(LREdit, SplitEditor::SM_Size);
1977 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
1978 if (Uses.size() <= 1)
1981 DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
1983 const TargetRegisterClass *SuperRC =
1984 TRI->getLargestLegalSuperClass(CurRC, *MF);
1985 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1986 // Split around every non-copy instruction if this split will relax
1987 // the constraints on the virtual register.
1988 // Otherwise, splitting just inserts uncoalescable copies that do not help
1990 for (unsigned i = 0; i != Uses.size(); ++i) {
1991 if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Uses[i]))
1992 if (MI->isFullCopy() ||
1993 SuperRCNumAllocatableRegs ==
1994 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
1996 DEBUG(dbgs() << " skip:\t" << Uses[i] << '\t' << *MI);
2000 SlotIndex SegStart = SE->enterIntvBefore(Uses[i]);
2001 SlotIndex SegStop = SE->leaveIntvAfter(Uses[i]);
2002 SE->useIntv(SegStart, SegStop);
2005 if (LREdit.empty()) {
2006 DEBUG(dbgs() << "All uses were copies.\n");
2010 SmallVector<unsigned, 8> IntvMap;
2011 SE->finish(&IntvMap);
2012 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
2013 ExtraRegInfo.resize(MRI->getNumVirtRegs());
2015 // Assign all new registers to RS_Spill. This was the last chance.
2016 setStage(LREdit.begin(), LREdit.end(), RS_Spill);
2020 //===----------------------------------------------------------------------===//
2022 //===----------------------------------------------------------------------===//
2024 /// calcGapWeights - Compute the maximum spill weight that needs to be evicted
2025 /// in order to use PhysReg between two entries in SA->UseSlots.
2027 /// GapWeight[i] represents the gap between UseSlots[i] and UseSlots[i+1].
2029 void RAGreedy::calcGapWeights(unsigned PhysReg,
2030 SmallVectorImpl<float> &GapWeight) {
2031 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
2032 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
2033 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
2034 const unsigned NumGaps = Uses.size()-1;
2036 // Start and end points for the interference check.
2037 SlotIndex StartIdx =
2038 BI.LiveIn ? BI.FirstInstr.getBaseIndex() : BI.FirstInstr;
2040 BI.LiveOut ? BI.LastInstr.getBoundaryIndex() : BI.LastInstr;
2042 GapWeight.assign(NumGaps, 0.0f);
2044 // Add interference from each overlapping register.
2045 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2046 if (!Matrix->query(const_cast<LiveInterval&>(SA->getParent()), *Units)
2047 .checkInterference())
2050 // We know that VirtReg is a continuous interval from FirstInstr to
2051 // LastInstr, so we don't need InterferenceQuery.
2053 // Interference that overlaps an instruction is counted in both gaps
2054 // surrounding the instruction. The exception is interference before
2055 // StartIdx and after StopIdx.
2057 LiveIntervalUnion::SegmentIter IntI =
2058 Matrix->getLiveUnions()[*Units] .find(StartIdx);
2059 for (unsigned Gap = 0; IntI.valid() && IntI.start() < StopIdx; ++IntI) {
2060 // Skip the gaps before IntI.
2061 while (Uses[Gap+1].getBoundaryIndex() < IntI.start())
2062 if (++Gap == NumGaps)
2067 // Update the gaps covered by IntI.
2068 const float weight = IntI.value()->weight;
2069 for (; Gap != NumGaps; ++Gap) {
2070 GapWeight[Gap] = std::max(GapWeight[Gap], weight);
2071 if (Uses[Gap+1].getBaseIndex() >= IntI.stop())
2079 // Add fixed interference.
2080 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2081 const LiveRange &LR = LIS->getRegUnit(*Units);
2082 LiveRange::const_iterator I = LR.find(StartIdx);
2083 LiveRange::const_iterator E = LR.end();
2085 // Same loop as above. Mark any overlapped gaps as HUGE_VALF.
2086 for (unsigned Gap = 0; I != E && I->start < StopIdx; ++I) {
2087 while (Uses[Gap+1].getBoundaryIndex() < I->start)
2088 if (++Gap == NumGaps)
2093 for (; Gap != NumGaps; ++Gap) {
2094 GapWeight[Gap] = huge_valf;
2095 if (Uses[Gap+1].getBaseIndex() >= I->end)
2104 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
2107 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
2108 SmallVectorImpl<unsigned> &NewVRegs) {
2109 assert(SA->getUseBlocks().size() == 1 && "Not a local interval");
2110 const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
2112 // Note that it is possible to have an interval that is live-in or live-out
2113 // while only covering a single block - A phi-def can use undef values from
2114 // predecessors, and the block could be a single-block loop.
2115 // We don't bother doing anything clever about such a case, we simply assume
2116 // that the interval is continuous from FirstInstr to LastInstr. We should
2117 // make sure that we don't do anything illegal to such an interval, though.
2119 ArrayRef<SlotIndex> Uses = SA->getUseSlots();
2120 if (Uses.size() <= 2)
2122 const unsigned NumGaps = Uses.size()-1;
2125 dbgs() << "tryLocalSplit: ";
2126 for (unsigned i = 0, e = Uses.size(); i != e; ++i)
2127 dbgs() << ' ' << Uses[i];
2131 // If VirtReg is live across any register mask operands, compute a list of
2132 // gaps with register masks.
2133 SmallVector<unsigned, 8> RegMaskGaps;
2134 if (Matrix->checkRegMaskInterference(VirtReg)) {
2135 // Get regmask slots for the whole block.
2136 ArrayRef<SlotIndex> RMS = LIS->getRegMaskSlotsInBlock(BI.MBB->getNumber());
2137 DEBUG(dbgs() << RMS.size() << " regmasks in block:");
2138 // Constrain to VirtReg's live range.
2139 unsigned ri = std::lower_bound(RMS.begin(), RMS.end(),
2140 Uses.front().getRegSlot()) - RMS.begin();
2141 unsigned re = RMS.size();
2142 for (unsigned i = 0; i != NumGaps && ri != re; ++i) {
2143 // Look for Uses[i] <= RMS <= Uses[i+1].
2144 assert(!SlotIndex::isEarlierInstr(RMS[ri], Uses[i]));
2145 if (SlotIndex::isEarlierInstr(Uses[i+1], RMS[ri]))
2147 // Skip a regmask on the same instruction as the last use. It doesn't
2148 // overlap the live range.
2149 if (SlotIndex::isSameInstr(Uses[i+1], RMS[ri]) && i+1 == NumGaps)
2151 DEBUG(dbgs() << ' ' << RMS[ri] << ':' << Uses[i] << '-' << Uses[i+1]);
2152 RegMaskGaps.push_back(i);
2153 // Advance ri to the next gap. A regmask on one of the uses counts in
2155 while (ri != re && SlotIndex::isEarlierInstr(RMS[ri], Uses[i+1]))
2158 DEBUG(dbgs() << '\n');
2161 // Since we allow local split results to be split again, there is a risk of
2162 // creating infinite loops. It is tempting to require that the new live
2163 // ranges have less instructions than the original. That would guarantee
2164 // convergence, but it is too strict. A live range with 3 instructions can be
2165 // split 2+3 (including the COPY), and we want to allow that.
2167 // Instead we use these rules:
2169 // 1. Allow any split for ranges with getStage() < RS_Split2. (Except for the
2170 // noop split, of course).
2171 // 2. Require progress be made for ranges with getStage() == RS_Split2. All
2172 // the new ranges must have fewer instructions than before the split.
2173 // 3. New ranges with the same number of instructions are marked RS_Split2,
2174 // smaller ranges are marked RS_New.
2176 // These rules allow a 3 -> 2+3 split once, which we need. They also prevent
2177 // excessive splitting and infinite loops.
2179 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
2181 // Best split candidate.
2182 unsigned BestBefore = NumGaps;
2183 unsigned BestAfter = 0;
2186 const float blockFreq =
2187 SpillPlacer->getBlockFrequency(BI.MBB->getNumber()).getFrequency() *
2188 (1.0f / MBFI->getEntryFreq());
2189 SmallVector<float, 8> GapWeight;
2192 while (unsigned PhysReg = Order.next()) {
2193 // Keep track of the largest spill weight that would need to be evicted in
2194 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
2195 calcGapWeights(PhysReg, GapWeight);
2197 // Remove any gaps with regmask clobbers.
2198 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
2199 for (unsigned i = 0, e = RegMaskGaps.size(); i != e; ++i)
2200 GapWeight[RegMaskGaps[i]] = huge_valf;
2202 // Try to find the best sequence of gaps to close.
2203 // The new spill weight must be larger than any gap interference.
2205 // We will split before Uses[SplitBefore] and after Uses[SplitAfter].
2206 unsigned SplitBefore = 0, SplitAfter = 1;
2208 // MaxGap should always be max(GapWeight[SplitBefore..SplitAfter-1]).
2209 // It is the spill weight that needs to be evicted.
2210 float MaxGap = GapWeight[0];
2213 // Live before/after split?
2214 const bool LiveBefore = SplitBefore != 0 || BI.LiveIn;
2215 const bool LiveAfter = SplitAfter != NumGaps || BI.LiveOut;
2217 DEBUG(dbgs() << printReg(PhysReg, TRI) << ' '
2218 << Uses[SplitBefore] << '-' << Uses[SplitAfter]
2219 << " i=" << MaxGap);
2221 // Stop before the interval gets so big we wouldn't be making progress.
2222 if (!LiveBefore && !LiveAfter) {
2223 DEBUG(dbgs() << " all\n");
2226 // Should the interval be extended or shrunk?
2229 // How many gaps would the new range have?
2230 unsigned NewGaps = LiveBefore + SplitAfter - SplitBefore + LiveAfter;
2232 // Legally, without causing looping?
2233 bool Legal = !ProgressRequired || NewGaps < NumGaps;
2235 if (Legal && MaxGap < huge_valf) {
2236 // Estimate the new spill weight. Each instruction reads or writes the
2237 // register. Conservatively assume there are no read-modify-write
2240 // Try to guess the size of the new interval.
2241 const float EstWeight = normalizeSpillWeight(
2242 blockFreq * (NewGaps + 1),
2243 Uses[SplitBefore].distance(Uses[SplitAfter]) +
2244 (LiveBefore + LiveAfter) * SlotIndex::InstrDist,
2246 // Would this split be possible to allocate?
2247 // Never allocate all gaps, we wouldn't be making progress.
2248 DEBUG(dbgs() << " w=" << EstWeight);
2249 if (EstWeight * Hysteresis >= MaxGap) {
2251 float Diff = EstWeight - MaxGap;
2252 if (Diff > BestDiff) {
2253 DEBUG(dbgs() << " (best)");
2254 BestDiff = Hysteresis * Diff;
2255 BestBefore = SplitBefore;
2256 BestAfter = SplitAfter;
2263 if (++SplitBefore < SplitAfter) {
2264 DEBUG(dbgs() << " shrink\n");
2265 // Recompute the max when necessary.
2266 if (GapWeight[SplitBefore - 1] >= MaxGap) {
2267 MaxGap = GapWeight[SplitBefore];
2268 for (unsigned i = SplitBefore + 1; i != SplitAfter; ++i)
2269 MaxGap = std::max(MaxGap, GapWeight[i]);
2276 // Try to extend the interval.
2277 if (SplitAfter >= NumGaps) {
2278 DEBUG(dbgs() << " end\n");
2282 DEBUG(dbgs() << " extend\n");
2283 MaxGap = std::max(MaxGap, GapWeight[SplitAfter++]);
2287 // Didn't find any candidates?
2288 if (BestBefore == NumGaps)
2291 DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore]
2292 << '-' << Uses[BestAfter] << ", " << BestDiff
2293 << ", " << (BestAfter - BestBefore + 1) << " instrs\n");
2295 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2299 SlotIndex SegStart = SE->enterIntvBefore(Uses[BestBefore]);
2300 SlotIndex SegStop = SE->leaveIntvAfter(Uses[BestAfter]);
2301 SE->useIntv(SegStart, SegStop);
2302 SmallVector<unsigned, 8> IntvMap;
2303 SE->finish(&IntvMap);
2304 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
2306 // If the new range has the same number of instructions as before, mark it as
2307 // RS_Split2 so the next split will be forced to make progress. Otherwise,
2308 // leave the new intervals as RS_New so they can compete.
2309 bool LiveBefore = BestBefore != 0 || BI.LiveIn;
2310 bool LiveAfter = BestAfter != NumGaps || BI.LiveOut;
2311 unsigned NewGaps = LiveBefore + BestAfter - BestBefore + LiveAfter;
2312 if (NewGaps >= NumGaps) {
2313 DEBUG(dbgs() << "Tagging non-progress ranges: ");
2314 assert(!ProgressRequired && "Didn't make progress when it was required.");
2315 for (unsigned i = 0, e = IntvMap.size(); i != e; ++i)
2316 if (IntvMap[i] == 1) {
2317 setStage(LIS->getInterval(LREdit.get(i)), RS_Split2);
2318 DEBUG(dbgs() << printReg(LREdit.get(i)));
2320 DEBUG(dbgs() << '\n');
2327 //===----------------------------------------------------------------------===//
2328 // Live Range Splitting
2329 //===----------------------------------------------------------------------===//
2331 /// trySplit - Try to split VirtReg or one of its interferences, making it
2333 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
2334 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
2335 SmallVectorImpl<unsigned>&NewVRegs) {
2336 // Ranges must be Split2 or less.
2337 if (getStage(VirtReg) >= RS_Spill)
2340 // Local intervals are handled separately.
2341 if (LIS->intervalIsInOneMBB(VirtReg)) {
2342 NamedRegionTimer T("local_split", "Local Splitting", TimerGroupName,
2343 TimerGroupDescription, TimePassesIsEnabled);
2344 SA->analyze(&VirtReg);
2345 unsigned PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
2346 if (PhysReg || !NewVRegs.empty())
2348 return tryInstructionSplit(VirtReg, Order, NewVRegs);
2351 NamedRegionTimer T("global_split", "Global Splitting", TimerGroupName,
2352 TimerGroupDescription, TimePassesIsEnabled);
2354 SA->analyze(&VirtReg);
2356 // FIXME: SplitAnalysis may repair broken live ranges coming from the
2357 // coalescer. That may cause the range to become allocatable which means that
2358 // tryRegionSplit won't be making progress. This check should be replaced with
2359 // an assertion when the coalescer is fixed.
2360 if (SA->didRepairRange()) {
2361 // VirtReg has changed, so all cached queries are invalid.
2362 Matrix->invalidateVirtRegs();
2363 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs))
2367 // First try to split around a region spanning multiple blocks. RS_Split2
2368 // ranges already made dubious progress with region splitting, so they go
2369 // straight to single block splitting.
2370 if (getStage(VirtReg) < RS_Split2) {
2371 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
2372 if (PhysReg || !NewVRegs.empty())
2376 // Then isolate blocks.
2377 return tryBlockSplit(VirtReg, Order, NewVRegs);
2380 //===----------------------------------------------------------------------===//
2381 // Last Chance Recoloring
2382 //===----------------------------------------------------------------------===//
2384 /// Return true if \p reg has any tied def operand.
2385 static bool hasTiedDef(MachineRegisterInfo *MRI, unsigned reg) {
2386 for (const MachineOperand &MO : MRI->def_operands(reg))
2393 /// mayRecolorAllInterferences - Check if the virtual registers that
2394 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
2395 /// recolored to free \p PhysReg.
2396 /// When true is returned, \p RecoloringCandidates has been augmented with all
2397 /// the live intervals that need to be recolored in order to free \p PhysReg
2399 /// \p FixedRegisters contains all the virtual registers that cannot be
2402 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
2403 SmallLISet &RecoloringCandidates,
2404 const SmallVirtRegSet &FixedRegisters) {
2405 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2407 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2408 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
2409 // If there is LastChanceRecoloringMaxInterference or more interferences,
2410 // chances are one would not be recolorable.
2411 if (Q.collectInterferingVRegs(LastChanceRecoloringMaxInterference) >=
2412 LastChanceRecoloringMaxInterference && !ExhaustiveSearch) {
2413 DEBUG(dbgs() << "Early abort: too many interferences.\n");
2414 CutOffInfo |= CO_Interf;
2417 for (unsigned i = Q.interferingVRegs().size(); i; --i) {
2418 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
2419 // If Intf is done and sit on the same register class as VirtReg,
2420 // it would not be recolorable as it is in the same state as VirtReg.
2421 // However, if VirtReg has tied defs and Intf doesn't, then
2422 // there is still a point in examining if it can be recolorable.
2423 if (((getStage(*Intf) == RS_Done &&
2424 MRI->getRegClass(Intf->reg) == CurRC) &&
2425 !(hasTiedDef(MRI, VirtReg.reg) && !hasTiedDef(MRI, Intf->reg))) ||
2426 FixedRegisters.count(Intf->reg)) {
2427 DEBUG(dbgs() << "Early abort: the interference is not recolorable.\n");
2430 RecoloringCandidates.insert(Intf);
2436 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
2437 /// its interferences.
2438 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
2439 /// virtual register that was using it. The recoloring process may recursively
2440 /// use the last chance recoloring. Therefore, when a virtual register has been
2441 /// assigned a color by this mechanism, it is marked as Fixed, i.e., it cannot
2442 /// be last-chance-recolored again during this recoloring "session".
2445 /// vA can use {R1, R2 }
2446 /// vB can use { R2, R3}
2447 /// vC can use {R1 }
2448 /// Where vA, vB, and vC cannot be split anymore (they are reloads for
2449 /// instance) and they all interfere.
2451 /// vA is assigned R1
2452 /// vB is assigned R2
2453 /// vC tries to evict vA but vA is already done.
2454 /// Regular register allocation fails.
2456 /// Last chance recoloring kicks in:
2457 /// vC does as if vA was evicted => vC uses R1.
2458 /// vC is marked as fixed.
2459 /// vA needs to find a color.
2460 /// None are available.
2461 /// vA cannot evict vC: vC is a fixed virtual register now.
2462 /// vA does as if vB was evicted => vA uses R2.
2463 /// vB needs to find a color.
2464 /// R3 is available.
2465 /// Recoloring => vC = R1, vA = R2, vB = R3
2467 /// \p Order defines the preferred allocation order for \p VirtReg.
2468 /// \p NewRegs will contain any new virtual register that have been created
2469 /// (split, spill) during the process and that must be assigned.
2470 /// \p FixedRegisters contains all the virtual registers that cannot be
2472 /// \p Depth gives the current depth of the last chance recoloring.
2473 /// \return a physical register that can be used for VirtReg or ~0u if none
2475 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
2476 AllocationOrder &Order,
2477 SmallVectorImpl<unsigned> &NewVRegs,
2478 SmallVirtRegSet &FixedRegisters,
2480 DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
2481 // Ranges must be Done.
2482 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
2483 "Last chance recoloring should really be last chance");
2484 // Set the max depth to LastChanceRecoloringMaxDepth.
2485 // We may want to reconsider that if we end up with a too large search space
2486 // for target with hundreds of registers.
2487 // Indeed, in that case we may want to cut the search space earlier.
2488 if (Depth >= LastChanceRecoloringMaxDepth && !ExhaustiveSearch) {
2489 DEBUG(dbgs() << "Abort because max depth has been reached.\n");
2490 CutOffInfo |= CO_Depth;
2494 // Set of Live intervals that will need to be recolored.
2495 SmallLISet RecoloringCandidates;
2496 // Record the original mapping virtual register to physical register in case
2497 // the recoloring fails.
2498 DenseMap<unsigned, unsigned> VirtRegToPhysReg;
2499 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
2500 // this recoloring "session".
2501 FixedRegisters.insert(VirtReg.reg);
2502 SmallVector<unsigned, 4> CurrentNewVRegs;
2505 while (unsigned PhysReg = Order.next()) {
2506 DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
2507 << printReg(PhysReg, TRI) << '\n');
2508 RecoloringCandidates.clear();
2509 VirtRegToPhysReg.clear();
2510 CurrentNewVRegs.clear();
2512 // It is only possible to recolor virtual register interference.
2513 if (Matrix->checkInterference(VirtReg, PhysReg) >
2514 LiveRegMatrix::IK_VirtReg) {
2515 DEBUG(dbgs() << "Some interferences are not with virtual registers.\n");
2520 // Early give up on this PhysReg if it is obvious we cannot recolor all
2521 // the interferences.
2522 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2524 DEBUG(dbgs() << "Some interferences cannot be recolored.\n");
2528 // RecoloringCandidates contains all the virtual registers that interfer
2529 // with VirtReg on PhysReg (or one of its aliases).
2530 // Enqueue them for recoloring and perform the actual recoloring.
2531 PQueue RecoloringQueue;
2532 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2533 EndIt = RecoloringCandidates.end();
2534 It != EndIt; ++It) {
2535 unsigned ItVirtReg = (*It)->reg;
2536 enqueue(RecoloringQueue, *It);
2537 assert(VRM->hasPhys(ItVirtReg) &&
2538 "Interferences are supposed to be with allocated vairables");
2540 // Record the current allocation.
2541 VirtRegToPhysReg[ItVirtReg] = VRM->getPhys(ItVirtReg);
2542 // unset the related struct.
2543 Matrix->unassign(**It);
2546 // Do as if VirtReg was assigned to PhysReg so that the underlying
2547 // recoloring has the right information about the interferes and
2548 // available colors.
2549 Matrix->assign(VirtReg, PhysReg);
2551 // Save the current recoloring state.
2552 // If we cannot recolor all the interferences, we will have to start again
2553 // at this point for the next physical register.
2554 SmallVirtRegSet SaveFixedRegisters(FixedRegisters);
2555 if (tryRecoloringCandidates(RecoloringQueue, CurrentNewVRegs,
2556 FixedRegisters, Depth)) {
2557 // Push the queued vregs into the main queue.
2558 for (unsigned NewVReg : CurrentNewVRegs)
2559 NewVRegs.push_back(NewVReg);
2560 // Do not mess up with the global assignment process.
2561 // I.e., VirtReg must be unassigned.
2562 Matrix->unassign(VirtReg);
2566 DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2567 << printReg(PhysReg, TRI) << '\n');
2569 // The recoloring attempt failed, undo the changes.
2570 FixedRegisters = SaveFixedRegisters;
2571 Matrix->unassign(VirtReg);
2573 // For a newly created vreg which is also in RecoloringCandidates,
2574 // don't add it to NewVRegs because its physical register will be restored
2575 // below. Other vregs in CurrentNewVRegs are created by calling
2576 // selectOrSplit and should be added into NewVRegs.
2577 for (SmallVectorImpl<unsigned>::iterator Next = CurrentNewVRegs.begin(),
2578 End = CurrentNewVRegs.end();
2579 Next != End; ++Next) {
2580 if (RecoloringCandidates.count(&LIS->getInterval(*Next)))
2582 NewVRegs.push_back(*Next);
2585 for (SmallLISet::iterator It = RecoloringCandidates.begin(),
2586 EndIt = RecoloringCandidates.end();
2587 It != EndIt; ++It) {
2588 unsigned ItVirtReg = (*It)->reg;
2589 if (VRM->hasPhys(ItVirtReg))
2590 Matrix->unassign(**It);
2591 unsigned ItPhysReg = VirtRegToPhysReg[ItVirtReg];
2592 Matrix->assign(**It, ItPhysReg);
2596 // Last chance recoloring did not worked either, give up.
2600 /// tryRecoloringCandidates - Try to assign a new color to every register
2601 /// in \RecoloringQueue.
2602 /// \p NewRegs will contain any new virtual register created during the
2603 /// recoloring process.
2604 /// \p FixedRegisters[in/out] contains all the registers that have been
2606 /// \return true if all virtual registers in RecoloringQueue were successfully
2607 /// recolored, false otherwise.
2608 bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
2609 SmallVectorImpl<unsigned> &NewVRegs,
2610 SmallVirtRegSet &FixedRegisters,
2612 while (!RecoloringQueue.empty()) {
2613 LiveInterval *LI = dequeue(RecoloringQueue);
2614 DEBUG(dbgs() << "Try to recolor: " << *LI << '\n');
2616 PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters, Depth + 1);
2617 // When splitting happens, the live-range may actually be empty.
2618 // In that case, this is okay to continue the recoloring even
2619 // if we did not find an alternative color for it. Indeed,
2620 // there will not be anything to color for LI in the end.
2621 if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
2625 assert(LI->empty() && "Only empty live-range do not require a register");
2626 DEBUG(dbgs() << "Recoloring of " << *LI << " succeeded. Empty LI.\n");
2629 DEBUG(dbgs() << "Recoloring of " << *LI
2630 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2632 Matrix->assign(*LI, PhysReg);
2633 FixedRegisters.insert(LI->reg);
2638 //===----------------------------------------------------------------------===//
2640 //===----------------------------------------------------------------------===//
2642 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2643 SmallVectorImpl<unsigned> &NewVRegs) {
2644 CutOffInfo = CO_None;
2645 LLVMContext &Ctx = MF->getFunction().getContext();
2646 SmallVirtRegSet FixedRegisters;
2647 unsigned Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2648 if (Reg == ~0U && (CutOffInfo != CO_None)) {
2649 uint8_t CutOffEncountered = CutOffInfo & (CO_Depth | CO_Interf);
2650 if (CutOffEncountered == CO_Depth)
2651 Ctx.emitError("register allocation failed: maximum depth for recoloring "
2652 "reached. Use -fexhaustive-register-search to skip "
2654 else if (CutOffEncountered == CO_Interf)
2655 Ctx.emitError("register allocation failed: maximum interference for "
2656 "recoloring reached. Use -fexhaustive-register-search "
2658 else if (CutOffEncountered == (CO_Depth | CO_Interf))
2659 Ctx.emitError("register allocation failed: maximum interference and "
2660 "depth for recoloring reached. Use "
2661 "-fexhaustive-register-search to skip cutoffs");
2666 /// Using a CSR for the first time has a cost because it causes push|pop
2667 /// to be added to prologue|epilogue. Splitting a cold section of the live
2668 /// range can have lower cost than using the CSR for the first time;
2669 /// Spilling a live range in the cold path can have lower cost than using
2670 /// the CSR for the first time. Returns the physical register if we decide
2671 /// to use the CSR; otherwise return 0.
2672 unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg,
2673 AllocationOrder &Order,
2675 unsigned &CostPerUseLimit,
2676 SmallVectorImpl<unsigned> &NewVRegs) {
2677 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2678 // We choose spill over using the CSR for the first time if the spill cost
2679 // is lower than CSRCost.
2680 SA->analyze(&VirtReg);
2681 if (calcSpillCost() >= CSRCost)
2684 // We are going to spill, set CostPerUseLimit to 1 to make sure that
2685 // we will not use a callee-saved register in tryEvict.
2686 CostPerUseLimit = 1;
2689 if (getStage(VirtReg) < RS_Split) {
2690 // We choose pre-splitting over using the CSR for the first time if
2691 // the cost of splitting is lower than CSRCost.
2692 SA->analyze(&VirtReg);
2693 unsigned NumCands = 0;
2694 BlockFrequency BestCost = CSRCost; // Don't modify CSRCost.
2695 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2696 NumCands, true /*IgnoreCSR*/);
2697 if (BestCand == NoCand)
2698 // Use the CSR if we can't find a region split below CSRCost.
2701 // Perform the actual pre-splitting.
2702 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2708 void RAGreedy::aboutToRemoveInterval(LiveInterval &LI) {
2709 // Do not keep invalid information around.
2710 SetOfBrokenHints.remove(&LI);
2713 void RAGreedy::initializeCSRCost() {
2714 // We use the larger one out of the command-line option and the value report
2716 CSRCost = BlockFrequency(
2717 std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
2718 if (!CSRCost.getFrequency())
2721 // Raw cost is relative to Entry == 2^14; scale it appropriately.
2722 uint64_t ActualEntry = MBFI->getEntryFreq();
2727 uint64_t FixedEntry = 1 << 14;
2728 if (ActualEntry < FixedEntry)
2729 CSRCost *= BranchProbability(ActualEntry, FixedEntry);
2730 else if (ActualEntry <= UINT32_MAX)
2731 // Invert the fraction and divide.
2732 CSRCost /= BranchProbability(FixedEntry, ActualEntry);
2734 // Can't use BranchProbability in general, since it takes 32-bit numbers.
2735 CSRCost = CSRCost.getFrequency() * (ActualEntry / FixedEntry);
2738 /// \brief Collect the hint info for \p Reg.
2739 /// The results are stored into \p Out.
2740 /// \p Out is not cleared before being populated.
2741 void RAGreedy::collectHintInfo(unsigned Reg, HintsInfo &Out) {
2742 for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
2743 if (!Instr.isFullCopy())
2745 // Look for the other end of the copy.
2746 unsigned OtherReg = Instr.getOperand(0).getReg();
2747 if (OtherReg == Reg) {
2748 OtherReg = Instr.getOperand(1).getReg();
2749 if (OtherReg == Reg)
2752 // Get the current assignment.
2753 unsigned OtherPhysReg = TargetRegisterInfo::isPhysicalRegister(OtherReg)
2755 : VRM->getPhys(OtherReg);
2756 // Push the collected information.
2757 Out.push_back(HintInfo(MBFI->getBlockFreq(Instr.getParent()), OtherReg,
2762 /// \brief Using the given \p List, compute the cost of the broken hints if
2763 /// \p PhysReg was used.
2764 /// \return The cost of \p List for \p PhysReg.
2765 BlockFrequency RAGreedy::getBrokenHintFreq(const HintsInfo &List,
2767 BlockFrequency Cost = 0;
2768 for (const HintInfo &Info : List) {
2769 if (Info.PhysReg != PhysReg)
2775 /// \brief Using the register assigned to \p VirtReg, try to recolor
2776 /// all the live ranges that are copy-related with \p VirtReg.
2777 /// The recoloring is then propagated to all the live-ranges that have
2778 /// been recolored and so on, until no more copies can be coalesced or
2779 /// it is not profitable.
2780 /// For a given live range, profitability is determined by the sum of the
2781 /// frequencies of the non-identity copies it would introduce with the old
2782 /// and new register.
2783 void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) {
2784 // We have a broken hint, check if it is possible to fix it by
2785 // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
2786 // some register and PhysReg may be available for the other live-ranges.
2787 SmallSet<unsigned, 4> Visited;
2788 SmallVector<unsigned, 2> RecoloringCandidates;
2790 unsigned Reg = VirtReg.reg;
2791 unsigned PhysReg = VRM->getPhys(Reg);
2792 // Start the recoloring algorithm from the input live-interval, then
2793 // it will propagate to the ones that are copy-related with it.
2794 Visited.insert(Reg);
2795 RecoloringCandidates.push_back(Reg);
2797 DEBUG(dbgs() << "Trying to reconcile hints for: " << printReg(Reg, TRI) << '('
2798 << printReg(PhysReg, TRI) << ")\n");
2801 Reg = RecoloringCandidates.pop_back_val();
2803 // We cannot recolor physical register.
2804 if (TargetRegisterInfo::isPhysicalRegister(Reg))
2807 assert(VRM->hasPhys(Reg) && "We have unallocated variable!!");
2809 // Get the live interval mapped with this virtual register to be able
2810 // to check for the interference with the new color.
2811 LiveInterval &LI = LIS->getInterval(Reg);
2812 unsigned CurrPhys = VRM->getPhys(Reg);
2813 // Check that the new color matches the register class constraints and
2814 // that it is free for this live range.
2815 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2816 Matrix->checkInterference(LI, PhysReg)))
2819 DEBUG(dbgs() << printReg(Reg, TRI) << '(' << printReg(CurrPhys, TRI)
2820 << ") is recolorable.\n");
2822 // Gather the hint info.
2824 collectHintInfo(Reg, Info);
2825 // Check if recoloring the live-range will increase the cost of the
2826 // non-identity copies.
2827 if (CurrPhys != PhysReg) {
2828 DEBUG(dbgs() << "Checking profitability:\n");
2829 BlockFrequency OldCopiesCost = getBrokenHintFreq(Info, CurrPhys);
2830 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
2831 DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency()
2832 << "\nNew Cost: " << NewCopiesCost.getFrequency() << '\n');
2833 if (OldCopiesCost < NewCopiesCost) {
2834 DEBUG(dbgs() << "=> Not profitable.\n");
2837 // At this point, the cost is either cheaper or equal. If it is
2838 // equal, we consider this is profitable because it may expose
2839 // more recoloring opportunities.
2840 DEBUG(dbgs() << "=> Profitable.\n");
2841 // Recolor the live-range.
2842 Matrix->unassign(LI);
2843 Matrix->assign(LI, PhysReg);
2845 // Push all copy-related live-ranges to keep reconciling the broken
2847 for (const HintInfo &HI : Info) {
2848 if (Visited.insert(HI.Reg).second)
2849 RecoloringCandidates.push_back(HI.Reg);
2851 } while (!RecoloringCandidates.empty());
2854 /// \brief Try to recolor broken hints.
2855 /// Broken hints may be repaired by recoloring when an evicted variable
2856 /// freed up a register for a larger live-range.
2857 /// Consider the following example:
2865 /// Let us assume b gets split:
2875 /// Because of how the allocation work, b, c, and d may be assigned different
2876 /// colors. Now, if a gets evicted later:
2886 /// e = ld SpillSlot
2888 /// This is likely that we can assign the same register for b, c, and d,
2889 /// getting rid of 2 copies.
2890 void RAGreedy::tryHintsRecoloring() {
2891 for (LiveInterval *LI : SetOfBrokenHints) {
2892 assert(TargetRegisterInfo::isVirtualRegister(LI->reg) &&
2893 "Recoloring is possible only for virtual registers");
2894 // Some dead defs may be around (e.g., because of debug uses).
2896 if (!VRM->hasPhys(LI->reg))
2898 tryHintRecoloring(*LI);
2902 unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
2903 SmallVectorImpl<unsigned> &NewVRegs,
2904 SmallVirtRegSet &FixedRegisters,
2906 unsigned CostPerUseLimit = ~0u;
2907 // First try assigning a free register.
2908 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
2909 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) {
2910 // If VirtReg got an assignment, the eviction info is no longre relevant.
2911 LastEvicted.clearEvicteeInfo(VirtReg.reg);
2912 // When NewVRegs is not empty, we may have made decisions such as evicting
2913 // a virtual register, go with the earlier decisions and use the physical
2915 if (CSRCost.getFrequency() && isUnusedCalleeSavedReg(PhysReg) &&
2917 unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2918 CostPerUseLimit, NewVRegs);
2919 if (CSRReg || !NewVRegs.empty())
2920 // Return now if we decide to use a CSR or create new vregs due to
2927 LiveRangeStage Stage = getStage(VirtReg);
2928 DEBUG(dbgs() << StageName[Stage]
2929 << " Cascade " << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
2931 // Try to evict a less worthy live range, but only for ranges from the primary
2932 // queue. The RS_Split ranges already failed to do this, and they should not
2933 // get a second chance until they have been split.
2934 if (Stage != RS_Split)
2935 if (unsigned PhysReg =
2936 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit)) {
2937 unsigned Hint = MRI->getSimpleHint(VirtReg.reg);
2938 // If VirtReg has a hint and that hint is broken record this
2939 // virtual register as a recoloring candidate for broken hint.
2940 // Indeed, since we evicted a variable in its neighborhood it is
2941 // likely we can at least partially recolor some of the
2942 // copy-related live-ranges.
2943 if (Hint && Hint != PhysReg)
2944 SetOfBrokenHints.insert(&VirtReg);
2945 // If VirtReg eviction someone, the eviction info for it as an evictee is
2946 // no longre relevant.
2947 LastEvicted.clearEvicteeInfo(VirtReg.reg);
2951 assert((NewVRegs.empty() || Depth) && "Cannot append to existing NewVRegs");
2953 // The first time we see a live range, don't try to split or spill.
2954 // Wait until the second time, when all smaller ranges have been allocated.
2955 // This gives a better picture of the interference to split around.
2956 if (Stage < RS_Split) {
2957 setStage(VirtReg, RS_Split);
2958 DEBUG(dbgs() << "wait for second round\n");
2959 NewVRegs.push_back(VirtReg.reg);
2963 if (Stage < RS_Spill) {
2964 // Try splitting VirtReg or interferences.
2965 unsigned NewVRegSizeBefore = NewVRegs.size();
2966 unsigned PhysReg = trySplit(VirtReg, Order, NewVRegs);
2967 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore)) {
2968 // If VirtReg got split, the eviction info is no longre relevant.
2969 LastEvicted.clearEvicteeInfo(VirtReg.reg);
2974 // If we couldn't allocate a register from spilling, there is probably some
2975 // invalid inline assembly. The base class will report it.
2976 if (Stage >= RS_Done || !VirtReg.isSpillable())
2977 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
2980 // Finally spill VirtReg itself.
2981 if (EnableDeferredSpilling && getStage(VirtReg) < RS_Memory) {
2982 // TODO: This is experimental and in particular, we do not model
2983 // the live range splitting done by spilling correctly.
2984 // We would need a deep integration with the spiller to do the
2985 // right thing here. Anyway, that is still good for early testing.
2986 setStage(VirtReg, RS_Memory);
2987 DEBUG(dbgs() << "Do as if this register is in memory\n");
2988 NewVRegs.push_back(VirtReg.reg);
2990 NamedRegionTimer T("spill", "Spiller", TimerGroupName,
2991 TimerGroupDescription, TimePassesIsEnabled);
2992 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2993 spiller().spill(LRE);
2994 setStage(NewVRegs.begin(), NewVRegs.end(), RS_Done);
2997 MF->verify(this, "After spilling");
3000 // The live virtual register requesting allocation was spilled, so tell
3001 // the caller not to allocate anything during this round.
3005 void RAGreedy::reportNumberOfSplillsReloads(MachineLoop *L, unsigned &Reloads,
3006 unsigned &FoldedReloads,
3008 unsigned &FoldedSpills) {
3014 // Sum up the spill and reloads in subloops.
3015 for (MachineLoop *SubLoop : *L) {
3016 unsigned SubReloads;
3017 unsigned SubFoldedReloads;
3019 unsigned SubFoldedSpills;
3021 reportNumberOfSplillsReloads(SubLoop, SubReloads, SubFoldedReloads,
3022 SubSpills, SubFoldedSpills);
3023 Reloads += SubReloads;
3024 FoldedReloads += SubFoldedReloads;
3025 Spills += SubSpills;
3026 FoldedSpills += SubFoldedSpills;
3029 const MachineFrameInfo &MFI = MF->getFrameInfo();
3030 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
3033 for (MachineBasicBlock *MBB : L->getBlocks())
3034 // Handle blocks that were not included in subloops.
3035 if (Loops->getLoopFor(MBB) == L)
3036 for (MachineInstr &MI : *MBB) {
3037 const MachineMemOperand *MMO;
3039 if (TII->isLoadFromStackSlot(MI, FI) && MFI.isSpillSlotObjectIndex(FI))
3041 else if (TII->hasLoadFromStackSlot(MI, MMO, FI) &&
3042 MFI.isSpillSlotObjectIndex(FI))
3044 else if (TII->isStoreToStackSlot(MI, FI) &&
3045 MFI.isSpillSlotObjectIndex(FI))
3047 else if (TII->hasStoreToStackSlot(MI, MMO, FI) &&
3048 MFI.isSpillSlotObjectIndex(FI))
3052 if (Reloads || FoldedReloads || Spills || FoldedSpills) {
3053 using namespace ore;
3056 MachineOptimizationRemarkMissed R(DEBUG_TYPE, "LoopSpillReload",
3057 L->getStartLoc(), L->getHeader());
3059 R << NV("NumSpills", Spills) << " spills ";
3061 R << NV("NumFoldedSpills", FoldedSpills) << " folded spills ";
3063 R << NV("NumReloads", Reloads) << " reloads ";
3065 R << NV("NumFoldedReloads", FoldedReloads) << " folded reloads ";
3066 R << "generated in loop";
3072 bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
3073 DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
3074 << "********** Function: " << mf.getName() << '\n');
3077 TRI = MF->getSubtarget().getRegisterInfo();
3078 TII = MF->getSubtarget().getInstrInfo();
3079 RCI.runOnMachineFunction(mf);
3081 EnableLocalReassign = EnableLocalReassignment ||
3082 MF->getSubtarget().enableRALocalReassignment(
3083 MF->getTarget().getOptLevel());
3085 EnableAdvancedRASplitCost = ConsiderLocalIntervalCost ||
3086 MF->getSubtarget().enableAdvancedRASplitCost();
3089 MF->verify(this, "Before greedy register allocator");
3091 RegAllocBase::init(getAnalysis<VirtRegMap>(),
3092 getAnalysis<LiveIntervals>(),
3093 getAnalysis<LiveRegMatrix>());
3094 Indexes = &getAnalysis<SlotIndexes>();
3095 MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
3096 DomTree = &getAnalysis<MachineDominatorTree>();
3097 ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
3098 SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
3099 Loops = &getAnalysis<MachineLoopInfo>();
3100 Bundles = &getAnalysis<EdgeBundles>();
3101 SpillPlacer = &getAnalysis<SpillPlacement>();
3102 DebugVars = &getAnalysis<LiveDebugVariables>();
3103 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
3105 initializeCSRCost();
3107 calculateSpillWeightsAndHints(*LIS, mf, VRM, *Loops, *MBFI);
3111 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
3112 SE.reset(new SplitEditor(*SA, *AA, *LIS, *VRM, *DomTree, *MBFI));
3113 ExtraRegInfo.clear();
3114 ExtraRegInfo.resize(MRI->getNumVirtRegs());
3116 IntfCache.init(MF, Matrix->getLiveUnions(), Indexes, LIS, TRI);
3117 GlobalCand.resize(32); // This will grow as needed.
3118 SetOfBrokenHints.clear();
3119 LastEvicted.clear();
3122 tryHintsRecoloring();
3124 reportNumberOfSplillsReloads();