lib/Target/AMDGPU/R600RegisterInfo.cpp

   1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 /// R600 implementation of the TargetRegisterInfo class.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "R600RegisterInfo.h"
  16 #include "AMDGPUTargetMachine.h"
  17 #include "R600Defines.h"
  18 #include "R600InstrInfo.h"
  19 #include "R600MachineFunctionInfo.h"
  20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
  21
  22 using namespace llvm;
  23
  24 R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
  25   RCW.RegWeight = 0;
  26   RCW.WeightLimit = 0;
  27 }
  28
  29 #define GET_REGINFO_TARGET_DESC
  30 #include "R600GenRegisterInfo.inc"
  31
  32 BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
  33   BitVector Reserved(getNumRegs());
  34
  35   const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
  36   const R600InstrInfo *TII = ST.getInstrInfo();
  37
  38   reserveRegisterTuples(Reserved, R600::ZERO);
  39   reserveRegisterTuples(Reserved, R600::HALF);
  40   reserveRegisterTuples(Reserved, R600::ONE);
  41   reserveRegisterTuples(Reserved, R600::ONE_INT);
  42   reserveRegisterTuples(Reserved, R600::NEG_HALF);
  43   reserveRegisterTuples(Reserved, R600::NEG_ONE);
  44   reserveRegisterTuples(Reserved, R600::PV_X);
  45   reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
  46   reserveRegisterTuples(Reserved, R600::ALU_CONST);
  47   reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
  48   reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
  49   reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
  50   reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
  51   reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
  52
  53   for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
  54                         E = R600::R600_AddrRegClass.end(); I != E; ++I) {
  55     reserveRegisterTuples(Reserved, *I);
  56   }
  57
  58   TII->reserveIndirectRegisters(Reserved, MF, *this);
  59
  60   return Reserved;
  61 }
  62
  63 // Dummy to not crash RegisterClassInfo.
  64 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
  65
  66 const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
  67   const MachineFunction *) const {
  68   return &CalleeSavedReg;
  69 }
  70
  71 unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
  72   return R600::NoRegister;
  73 }
  74
  75 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
  76   return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
  77 }
  78
  79 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
  80   return GET_REG_INDEX(getEncodingValue(Reg));
  81 }
  82
  83 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
  84                                                                    MVT VT) const {
  85   switch(VT.SimpleTy) {
  86   default:
  87   case MVT::i32: return &R600::R600_TReg32RegClass;
  88   }
  89 }
  90
  91 const RegClassWeight &R600RegisterInfo::getRegClassWeight(
  92   const TargetRegisterClass *RC) const {
  93   return RCW;
  94 }
  95
  96 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
  97   assert(!TargetRegisterInfo::isVirtualRegister(Reg));
  98
  99   switch (Reg) {
 100   case R600::OQAP:
 101   case R600::OQBP:
 102   case R600::AR_X:
 103     return false;
 104   default:
 105     return true;
 106   }
 107 }
 108
 109 void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
 110                                            int SPAdj,
 111                                            unsigned FIOperandNum,
 112                                            RegScavenger *RS) const {
 113   llvm_unreachable("Subroutines not supported yet");
 114 }
 115
 116 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
 117   MCRegAliasIterator R(Reg, this, true);
 118
 119   for (; R.isValid(); ++R)
 120     Reserved.set(*R);
 121 }