1 //===- HexagonVExtract.cpp ------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass will replace multiple occurrences of V6_extractw from the same
10 // vector register with a combination of a vector store and scalar loads.
11 //===----------------------------------------------------------------------===//
14 #include "HexagonInstrInfo.h"
15 #include "HexagonRegisterInfo.h"
16 #include "HexagonSubtarget.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/PassSupport.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/CommandLine.h"
30 static cl::opt<unsigned> VExtractThreshold("hexagon-vextract-threshold",
31 cl::Hidden, cl::ZeroOrMore, cl::init(1),
32 cl::desc("Threshold for triggering vextract replacement"));
35 void initializeHexagonVExtractPass(PassRegistry& Registry);
36 FunctionPass *createHexagonVExtract();
40 class HexagonVExtract : public MachineFunctionPass {
43 HexagonVExtract() : MachineFunctionPass(ID) {}
45 StringRef getPassName() const override {
46 return "Hexagon optimize vextract";
48 void getAnalysisUsage(AnalysisUsage &AU) const override {
49 MachineFunctionPass::getAnalysisUsage(AU);
51 bool runOnMachineFunction(MachineFunction &MF) override;
54 const HexagonSubtarget *HST = nullptr;
55 const HexagonInstrInfo *HII = nullptr;
57 unsigned genElemLoad(MachineInstr *ExtI, unsigned BaseR,
58 MachineRegisterInfo &MRI);
61 char HexagonVExtract::ID = 0;
64 INITIALIZE_PASS(HexagonVExtract, "hexagon-vextract",
65 "Hexagon optimize vextract", false, false)
67 unsigned HexagonVExtract::genElemLoad(MachineInstr *ExtI, unsigned BaseR,
68 MachineRegisterInfo &MRI) {
69 MachineBasicBlock &ExtB = *ExtI->getParent();
70 DebugLoc DL = ExtI->getDebugLoc();
71 unsigned ElemR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
73 unsigned ExtIdxR = ExtI->getOperand(2).getReg();
74 unsigned ExtIdxS = ExtI->getOperand(2).getSubReg();
76 // Simplified check for a compile-time constant value of ExtIdxR.
78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR);
79 if (DI->getOpcode() == Hexagon::A2_tfrsi) {
80 unsigned V = DI->getOperand(1).getImm();
81 V &= (HST->getVectorLength()-1) & -4u;
83 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L2_loadri_io), ElemR)
90 unsigned IdxR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
91 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::A2_andir), IdxR)
92 .add(ExtI->getOperand(2))
94 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::L4_loadri_rr), ElemR)
101 bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
102 HST = &MF.getSubtarget<HexagonSubtarget>();
103 HII = HST->getInstrInfo();
104 const auto &HRI = *HST->getRegisterInfo();
105 MachineRegisterInfo &MRI = MF.getRegInfo();
106 MachineFrameInfo &MFI = MF.getFrameInfo();
107 std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap;
108 bool Changed = false;
110 for (MachineBasicBlock &MBB : MF) {
111 for (MachineInstr &MI : MBB) {
112 unsigned Opc = MI.getOpcode();
113 if (Opc != Hexagon::V6_extractw)
115 unsigned VecR = MI.getOperand(1).getReg();
116 VExtractMap[VecR].push_back(&MI);
120 for (auto &P : VExtractMap) {
121 unsigned VecR = P.first;
122 if (P.second.size() <= VExtractThreshold)
125 const auto &VecRC = *MRI.getRegClass(VecR);
126 int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC),
127 HRI.getSpillAlignment(VecRC));
128 MachineInstr *DefI = MRI.getVRegDef(VecR);
129 MachineBasicBlock::iterator At = std::next(DefI->getIterator());
130 MachineBasicBlock &DefB = *DefI->getParent();
131 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID
132 ? Hexagon::V6_vS32b_ai
133 : Hexagon::PS_vstorerw_ai;
134 BuildMI(DefB, At, DefI->getDebugLoc(), HII->get(StoreOpc))
139 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8;
141 for (MachineInstr *ExtI : P.second) {
142 assert(ExtI->getOpcode() == Hexagon::V6_extractw);
143 unsigned SR = ExtI->getOperand(1).getSubReg();
144 assert(ExtI->getOperand(1).getReg() == VecR);
146 MachineBasicBlock &ExtB = *ExtI->getParent();
147 DebugLoc DL = ExtI->getDebugLoc();
148 unsigned BaseR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass);
149 BuildMI(ExtB, ExtI, DL, HII->get(Hexagon::PS_fi), BaseR)
151 .addImm(SR == 0 ? 0 : VecSize/2);
153 unsigned ElemR = genElemLoad(ExtI, BaseR, MRI);
154 unsigned ExtR = ExtI->getOperand(0).getReg();
155 MRI.replaceRegWith(ExtR, ElemR);
164 FunctionPass *llvm::createHexagonVExtract() {
165 return new HexagonVExtract();