1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCSymbolELF.h"
27 #include "llvm/Support/SourceMgr.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Support/raw_ostream.h"
33 DEFINE_PPC_REGCLASSES;
35 // Evaluate an expression containing condition register
36 // or condition register field symbols. Returns positive
37 // value on success, or -1 on error.
39 EvaluateCRExpr(const MCExpr *E) {
40 switch (E->getKind()) {
44 case MCExpr::Constant: {
45 int64_t Res = cast<MCConstantExpr>(E)->getValue();
46 return Res < 0 ? -1 : Res;
49 case MCExpr::SymbolRef: {
50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
51 StringRef Name = SRE->getSymbol().getName();
53 if (Name == "lt") return 0;
54 if (Name == "gt") return 1;
55 if (Name == "eq") return 2;
56 if (Name == "so") return 3;
57 if (Name == "un") return 3;
59 if (Name == "cr0") return 0;
60 if (Name == "cr1") return 1;
61 if (Name == "cr2") return 2;
62 if (Name == "cr3") return 3;
63 if (Name == "cr4") return 4;
64 if (Name == "cr5") return 5;
65 if (Name == "cr6") return 6;
66 if (Name == "cr7") return 7;
74 case MCExpr::Binary: {
75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
80 if (LHSVal < 0 || RHSVal < 0)
83 switch (BE->getOpcode()) {
85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
89 return Res < 0 ? -1 : Res;
93 llvm_unreachable("Invalid expression kind!");
100 class PPCAsmParser : public MCTargetAsmParser {
104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
106 bool isPPC64() const { return IsPPC64; }
107 bool isDarwin() const { return IsDarwin; }
109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
113 const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
114 PPCMCExpr::VariantKind &Variant);
115 const MCExpr *FixupVariantKind(const MCExpr *E);
116 bool ParseExpression(const MCExpr *&EVal);
117 bool ParseDarwinExpression(const MCExpr *&EVal);
119 bool ParseOperand(OperandVector &Operands);
121 bool ParseDirectiveWord(unsigned Size, AsmToken ID);
122 bool ParseDirectiveTC(unsigned Size, AsmToken ID);
123 bool ParseDirectiveMachine(SMLoc L);
124 bool ParseDarwinDirectiveMachine(SMLoc L);
125 bool ParseDirectiveAbiVersion(SMLoc L);
126 bool ParseDirectiveLocalEntry(SMLoc L);
128 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
129 OperandVector &Operands, MCStreamer &Out,
131 bool MatchingInlineAsm) override;
133 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
135 /// @name Auto-generated Match Functions
138 #define GET_ASSEMBLER_HEADER
139 #include "PPCGenAsmMatcher.inc"
145 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
146 const MCInstrInfo &MII, const MCTargetOptions &Options)
147 : MCTargetAsmParser(Options, STI, MII) {
148 // Check for 64-bit vs. 32-bit pointer mode.
149 const Triple &TheTriple = STI.getTargetTriple();
150 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
151 TheTriple.getArch() == Triple::ppc64le);
152 IsDarwin = TheTriple.isMacOSX();
153 // Initialize the set of available features.
154 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
157 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
158 SMLoc NameLoc, OperandVector &Operands) override;
160 bool ParseDirective(AsmToken DirectiveID) override;
162 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
163 unsigned Kind) override;
165 const MCExpr *applyModifierToExpr(const MCExpr *E,
166 MCSymbolRefExpr::VariantKind,
167 MCContext &Ctx) override;
170 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
172 struct PPCOperand : public MCParsedAsmOperand {
181 SMLoc StartLoc, EndLoc;
195 int64_t CRVal; // Cached result of EvaluateCRExpr(Val)
199 const MCSymbolRefExpr *Sym;
206 struct TLSRegOp TLSReg;
209 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
211 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
213 StartLoc = o.StartLoc;
221 case ContextImmediate:
233 // Disable use of sized deallocation due to overallocation of PPCOperand
234 // objects in CreateTokenWithStringCopy.
235 void operator delete(void *p) { ::operator delete(p); }
237 /// getStartLoc - Get the location of the first token of this operand.
238 SMLoc getStartLoc() const override { return StartLoc; }
240 /// getEndLoc - Get the location of the last token of this operand.
241 SMLoc getEndLoc() const override { return EndLoc; }
243 /// getLocRange - Get the range between the first and last token of this
245 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
247 /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
248 bool isPPC64() const { return IsPPC64; }
250 int64_t getImm() const {
251 assert(Kind == Immediate && "Invalid access!");
254 int64_t getImmS16Context() const {
255 assert((Kind == Immediate || Kind == ContextImmediate) &&
257 if (Kind == Immediate)
259 return static_cast<int16_t>(Imm.Val);
261 int64_t getImmU16Context() const {
262 assert((Kind == Immediate || Kind == ContextImmediate) &&
267 const MCExpr *getExpr() const {
268 assert(Kind == Expression && "Invalid access!");
272 int64_t getExprCRVal() const {
273 assert(Kind == Expression && "Invalid access!");
277 const MCExpr *getTLSReg() const {
278 assert(Kind == TLSRegister && "Invalid access!");
282 unsigned getReg() const override {
283 assert(isRegNumber() && "Invalid access!");
284 return (unsigned) Imm.Val;
287 unsigned getVSReg() const {
288 assert(isVSRegNumber() && "Invalid access!");
289 return (unsigned) Imm.Val;
292 unsigned getCCReg() const {
293 assert(isCCRegNumber() && "Invalid access!");
294 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
297 unsigned getCRBit() const {
298 assert(isCRBitNumber() && "Invalid access!");
299 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
302 unsigned getCRBitMask() const {
303 assert(isCRBitMask() && "Invalid access!");
304 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
307 bool isToken() const override { return Kind == Token; }
308 bool isImm() const override {
309 return Kind == Immediate || Kind == Expression;
311 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
312 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
313 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
314 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
315 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
316 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
317 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
318 bool isU6ImmX2() const { return Kind == Immediate &&
319 isUInt<6>(getImm()) &&
320 (getImm() & 1) == 0; }
321 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
322 bool isU7ImmX4() const { return Kind == Immediate &&
323 isUInt<7>(getImm()) &&
324 (getImm() & 3) == 0; }
325 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
326 bool isU8ImmX8() const { return Kind == Immediate &&
327 isUInt<8>(getImm()) &&
328 (getImm() & 7) == 0; }
330 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
331 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
332 bool isU16Imm() const {
337 case ContextImmediate:
338 return isUInt<16>(getImmU16Context());
343 bool isS16Imm() const {
348 case ContextImmediate:
349 return isInt<16>(getImmS16Context());
354 bool isS16ImmX4() const { return Kind == Expression ||
355 (Kind == Immediate && isInt<16>(getImm()) &&
356 (getImm() & 3) == 0); }
357 bool isS16ImmX16() const { return Kind == Expression ||
358 (Kind == Immediate && isInt<16>(getImm()) &&
359 (getImm() & 15) == 0); }
360 bool isS17Imm() const {
365 case ContextImmediate:
366 return isInt<17>(getImmS16Context());
371 bool isTLSReg() const { return Kind == TLSRegister; }
372 bool isDirectBr() const {
373 if (Kind == Expression)
375 if (Kind != Immediate)
377 // Operand must be 64-bit aligned, signed 27-bit immediate.
378 if ((getImm() & 3) != 0)
380 if (isInt<26>(getImm()))
383 // In 32-bit mode, large 32-bit quantities wrap around.
384 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
389 bool isCondBr() const { return Kind == Expression ||
390 (Kind == Immediate && isInt<16>(getImm()) &&
391 (getImm() & 3) == 0); }
392 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
393 bool isVSRegNumber() const {
394 return Kind == Immediate && isUInt<6>(getImm());
396 bool isCCRegNumber() const { return (Kind == Expression
397 && isUInt<3>(getExprCRVal())) ||
399 && isUInt<3>(getImm())); }
400 bool isCRBitNumber() const { return (Kind == Expression
401 && isUInt<5>(getExprCRVal())) ||
403 && isUInt<5>(getImm())); }
404 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
405 isPowerOf2_32(getImm()); }
406 bool isATBitsAsHint() const { return false; }
407 bool isMem() const override { return false; }
408 bool isReg() const override { return false; }
410 void addRegOperands(MCInst &Inst, unsigned N) const {
411 llvm_unreachable("addRegOperands");
414 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
415 assert(N == 1 && "Invalid number of operands!");
416 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
419 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
420 assert(N == 1 && "Invalid number of operands!");
421 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
424 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
425 assert(N == 1 && "Invalid number of operands!");
426 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
429 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
430 assert(N == 1 && "Invalid number of operands!");
431 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
434 void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
436 addRegG8RCOperands(Inst, N);
438 addRegGPRCOperands(Inst, N);
441 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
443 addRegG8RCNoX0Operands(Inst, N);
445 addRegGPRCNoR0Operands(Inst, N);
448 void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
449 assert(N == 1 && "Invalid number of operands!");
450 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
453 void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
454 assert(N == 1 && "Invalid number of operands!");
455 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
458 void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
459 assert(N == 1 && "Invalid number of operands!");
460 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
463 void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
464 assert(N == 1 && "Invalid number of operands!");
465 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
468 void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
469 assert(N == 1 && "Invalid number of operands!");
470 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
473 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
474 assert(N == 1 && "Invalid number of operands!");
475 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
478 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
479 assert(N == 1 && "Invalid number of operands!");
480 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
483 void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
484 assert(N == 1 && "Invalid number of operands!");
485 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
488 void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
489 assert(N == 1 && "Invalid number of operands!");
490 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
493 void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
494 assert(N == 1 && "Invalid number of operands!");
495 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
498 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const {
499 assert(N == 1 && "Invalid number of operands!");
500 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
503 void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
504 assert(N == 1 && "Invalid number of operands!");
505 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
508 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
509 assert(N == 1 && "Invalid number of operands!");
510 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
513 void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
514 assert(N == 1 && "Invalid number of operands!");
515 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
518 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
519 assert(N == 1 && "Invalid number of operands!");
520 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
523 void addImmOperands(MCInst &Inst, unsigned N) const {
524 assert(N == 1 && "Invalid number of operands!");
525 if (Kind == Immediate)
526 Inst.addOperand(MCOperand::createImm(getImm()));
528 Inst.addOperand(MCOperand::createExpr(getExpr()));
531 void addS16ImmOperands(MCInst &Inst, unsigned N) const {
532 assert(N == 1 && "Invalid number of operands!");
535 Inst.addOperand(MCOperand::createImm(getImm()));
537 case ContextImmediate:
538 Inst.addOperand(MCOperand::createImm(getImmS16Context()));
541 Inst.addOperand(MCOperand::createExpr(getExpr()));
546 void addU16ImmOperands(MCInst &Inst, unsigned N) const {
547 assert(N == 1 && "Invalid number of operands!");
550 Inst.addOperand(MCOperand::createImm(getImm()));
552 case ContextImmediate:
553 Inst.addOperand(MCOperand::createImm(getImmU16Context()));
556 Inst.addOperand(MCOperand::createExpr(getExpr()));
561 void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
562 assert(N == 1 && "Invalid number of operands!");
563 if (Kind == Immediate)
564 Inst.addOperand(MCOperand::createImm(getImm() / 4));
566 Inst.addOperand(MCOperand::createExpr(getExpr()));
569 void addTLSRegOperands(MCInst &Inst, unsigned N) const {
570 assert(N == 1 && "Invalid number of operands!");
571 Inst.addOperand(MCOperand::createExpr(getTLSReg()));
574 StringRef getToken() const {
575 assert(Kind == Token && "Invalid access!");
576 return StringRef(Tok.Data, Tok.Length);
579 void print(raw_ostream &OS) const override;
581 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
583 auto Op = make_unique<PPCOperand>(Token);
584 Op->Tok.Data = Str.data();
585 Op->Tok.Length = Str.size();
588 Op->IsPPC64 = IsPPC64;
592 static std::unique_ptr<PPCOperand>
593 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
594 // Allocate extra memory for the string and copy it.
595 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
596 // deleter which will destroy them by simply using "delete", not correctly
597 // calling operator delete on this extra memory after calling the dtor
599 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
600 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
601 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
602 Op->Tok.Length = Str.size();
603 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
606 Op->IsPPC64 = IsPPC64;
610 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
612 auto Op = make_unique<PPCOperand>(Immediate);
616 Op->IsPPC64 = IsPPC64;
620 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
621 SMLoc E, bool IsPPC64) {
622 auto Op = make_unique<PPCOperand>(Expression);
624 Op->Expr.CRVal = EvaluateCRExpr(Val);
627 Op->IsPPC64 = IsPPC64;
631 static std::unique_ptr<PPCOperand>
632 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
633 auto Op = make_unique<PPCOperand>(TLSRegister);
634 Op->TLSReg.Sym = Sym;
637 Op->IsPPC64 = IsPPC64;
641 static std::unique_ptr<PPCOperand>
642 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
643 auto Op = make_unique<PPCOperand>(ContextImmediate);
647 Op->IsPPC64 = IsPPC64;
651 static std::unique_ptr<PPCOperand>
652 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
653 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
654 return CreateImm(CE->getValue(), S, E, IsPPC64);
656 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
657 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
658 return CreateTLSReg(SRE, S, E, IsPPC64);
660 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
662 if (TE->evaluateAsConstant(Res))
663 return CreateContextImm(Res, S, E, IsPPC64);
666 return CreateExpr(Val, S, E, IsPPC64);
670 } // end anonymous namespace.
672 void PPCOperand::print(raw_ostream &OS) const {
675 OS << "'" << getToken() << "'";
678 case ContextImmediate:
691 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
693 Inst.addOperand(MCOperand::createImm(-Op.getImm()));
696 const MCExpr *Expr = Op.getExpr();
697 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
698 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
699 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
702 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
703 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
704 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
705 BinExpr->getLHS(), Ctx);
706 Inst.addOperand(MCOperand::createExpr(NE));
710 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
713 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
714 const OperandVector &Operands) {
715 int Opcode = Inst.getOpcode();
722 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
723 PPC::DCBT : PPC::DCBTST);
724 TmpInst.addOperand(MCOperand::createImm(
725 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
726 TmpInst.addOperand(Inst.getOperand(0));
727 TmpInst.addOperand(Inst.getOperand(1));
734 TmpInst.setOpcode(PPC::DCBT);
735 TmpInst.addOperand(Inst.getOperand(2));
736 TmpInst.addOperand(Inst.getOperand(0));
737 TmpInst.addOperand(Inst.getOperand(1));
742 case PPC::DCBTSTDS: {
744 TmpInst.setOpcode(PPC::DCBTST);
745 TmpInst.addOperand(Inst.getOperand(2));
746 TmpInst.addOperand(Inst.getOperand(0));
747 TmpInst.addOperand(Inst.getOperand(1));
755 if (Opcode == PPC::DCBFL)
757 else if (Opcode == PPC::DCBFLP)
761 TmpInst.setOpcode(PPC::DCBF);
762 TmpInst.addOperand(MCOperand::createImm(L));
763 TmpInst.addOperand(Inst.getOperand(0));
764 TmpInst.addOperand(Inst.getOperand(1));
770 TmpInst.setOpcode(PPC::LA);
771 TmpInst.addOperand(Inst.getOperand(0));
772 TmpInst.addOperand(Inst.getOperand(2));
773 TmpInst.addOperand(Inst.getOperand(1));
779 TmpInst.setOpcode(PPC::ADDI);
780 TmpInst.addOperand(Inst.getOperand(0));
781 TmpInst.addOperand(Inst.getOperand(1));
782 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
788 TmpInst.setOpcode(PPC::ADDIS);
789 TmpInst.addOperand(Inst.getOperand(0));
790 TmpInst.addOperand(Inst.getOperand(1));
791 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
797 TmpInst.setOpcode(PPC::ADDIC);
798 TmpInst.addOperand(Inst.getOperand(0));
799 TmpInst.addOperand(Inst.getOperand(1));
800 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
806 TmpInst.setOpcode(PPC::ADDICo);
807 TmpInst.addOperand(Inst.getOperand(0));
808 TmpInst.addOperand(Inst.getOperand(1));
809 addNegOperand(TmpInst, Inst.getOperand(2), getContext());
816 int64_t N = Inst.getOperand(2).getImm();
817 int64_t B = Inst.getOperand(3).getImm();
818 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
819 TmpInst.addOperand(Inst.getOperand(0));
820 TmpInst.addOperand(Inst.getOperand(1));
821 TmpInst.addOperand(MCOperand::createImm(B));
822 TmpInst.addOperand(MCOperand::createImm(0));
823 TmpInst.addOperand(MCOperand::createImm(N - 1));
830 int64_t N = Inst.getOperand(2).getImm();
831 int64_t B = Inst.getOperand(3).getImm();
832 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
833 TmpInst.addOperand(Inst.getOperand(0));
834 TmpInst.addOperand(Inst.getOperand(1));
835 TmpInst.addOperand(MCOperand::createImm(B + N));
836 TmpInst.addOperand(MCOperand::createImm(32 - N));
837 TmpInst.addOperand(MCOperand::createImm(31));
844 int64_t N = Inst.getOperand(2).getImm();
845 int64_t B = Inst.getOperand(3).getImm();
846 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
847 TmpInst.addOperand(Inst.getOperand(0));
848 TmpInst.addOperand(Inst.getOperand(0));
849 TmpInst.addOperand(Inst.getOperand(1));
850 TmpInst.addOperand(MCOperand::createImm(32 - B));
851 TmpInst.addOperand(MCOperand::createImm(B));
852 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
859 int64_t N = Inst.getOperand(2).getImm();
860 int64_t B = Inst.getOperand(3).getImm();
861 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
862 TmpInst.addOperand(Inst.getOperand(0));
863 TmpInst.addOperand(Inst.getOperand(0));
864 TmpInst.addOperand(Inst.getOperand(1));
865 TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
866 TmpInst.addOperand(MCOperand::createImm(B));
867 TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
874 int64_t N = Inst.getOperand(2).getImm();
875 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
876 TmpInst.addOperand(Inst.getOperand(0));
877 TmpInst.addOperand(Inst.getOperand(1));
878 TmpInst.addOperand(MCOperand::createImm(32 - N));
879 TmpInst.addOperand(MCOperand::createImm(0));
880 TmpInst.addOperand(MCOperand::createImm(31));
887 int64_t N = Inst.getOperand(2).getImm();
888 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
889 TmpInst.addOperand(Inst.getOperand(0));
890 TmpInst.addOperand(Inst.getOperand(1));
891 TmpInst.addOperand(MCOperand::createImm(N));
892 TmpInst.addOperand(MCOperand::createImm(0));
893 TmpInst.addOperand(MCOperand::createImm(31 - N));
900 int64_t N = Inst.getOperand(2).getImm();
901 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
902 TmpInst.addOperand(Inst.getOperand(0));
903 TmpInst.addOperand(Inst.getOperand(1));
904 TmpInst.addOperand(MCOperand::createImm(32 - N));
905 TmpInst.addOperand(MCOperand::createImm(N));
906 TmpInst.addOperand(MCOperand::createImm(31));
913 int64_t N = Inst.getOperand(2).getImm();
914 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
915 TmpInst.addOperand(Inst.getOperand(0));
916 TmpInst.addOperand(Inst.getOperand(1));
917 TmpInst.addOperand(MCOperand::createImm(0));
918 TmpInst.addOperand(MCOperand::createImm(0));
919 TmpInst.addOperand(MCOperand::createImm(31 - N));
924 case PPC::CLRLSLWIo: {
926 int64_t B = Inst.getOperand(2).getImm();
927 int64_t N = Inst.getOperand(3).getImm();
928 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
929 TmpInst.addOperand(Inst.getOperand(0));
930 TmpInst.addOperand(Inst.getOperand(1));
931 TmpInst.addOperand(MCOperand::createImm(N));
932 TmpInst.addOperand(MCOperand::createImm(B - N));
933 TmpInst.addOperand(MCOperand::createImm(31 - N));
940 int64_t N = Inst.getOperand(2).getImm();
941 int64_t B = Inst.getOperand(3).getImm();
942 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
943 TmpInst.addOperand(Inst.getOperand(0));
944 TmpInst.addOperand(Inst.getOperand(1));
945 TmpInst.addOperand(MCOperand::createImm(B));
946 TmpInst.addOperand(MCOperand::createImm(N - 1));
953 int64_t N = Inst.getOperand(2).getImm();
954 int64_t B = Inst.getOperand(3).getImm();
955 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
956 TmpInst.addOperand(Inst.getOperand(0));
957 TmpInst.addOperand(Inst.getOperand(1));
958 TmpInst.addOperand(MCOperand::createImm(B + N));
959 TmpInst.addOperand(MCOperand::createImm(64 - N));
966 int64_t N = Inst.getOperand(2).getImm();
967 int64_t B = Inst.getOperand(3).getImm();
968 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
969 TmpInst.addOperand(Inst.getOperand(0));
970 TmpInst.addOperand(Inst.getOperand(0));
971 TmpInst.addOperand(Inst.getOperand(1));
972 TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
973 TmpInst.addOperand(MCOperand::createImm(B));
980 int64_t N = Inst.getOperand(2).getImm();
981 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
982 TmpInst.addOperand(Inst.getOperand(0));
983 TmpInst.addOperand(Inst.getOperand(1));
984 TmpInst.addOperand(MCOperand::createImm(64 - N));
985 TmpInst.addOperand(MCOperand::createImm(0));
992 int64_t N = Inst.getOperand(2).getImm();
993 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
994 TmpInst.addOperand(Inst.getOperand(0));
995 TmpInst.addOperand(Inst.getOperand(1));
996 TmpInst.addOperand(MCOperand::createImm(N));
997 TmpInst.addOperand(MCOperand::createImm(63 - N));
1001 case PPC::SUBPCIS: {
1003 int64_t N = Inst.getOperand(1).getImm();
1004 TmpInst.setOpcode(PPC::ADDPCIS);
1005 TmpInst.addOperand(Inst.getOperand(0));
1006 TmpInst.addOperand(MCOperand::createImm(-N));
1013 int64_t N = Inst.getOperand(2).getImm();
1014 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1015 TmpInst.addOperand(Inst.getOperand(0));
1016 TmpInst.addOperand(Inst.getOperand(1));
1017 TmpInst.addOperand(MCOperand::createImm(64 - N));
1018 TmpInst.addOperand(MCOperand::createImm(N));
1023 case PPC::CLRRDIo: {
1025 int64_t N = Inst.getOperand(2).getImm();
1026 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1027 TmpInst.addOperand(Inst.getOperand(0));
1028 TmpInst.addOperand(Inst.getOperand(1));
1029 TmpInst.addOperand(MCOperand::createImm(0));
1030 TmpInst.addOperand(MCOperand::createImm(63 - N));
1035 case PPC::CLRLSLDIo: {
1037 int64_t B = Inst.getOperand(2).getImm();
1038 int64_t N = Inst.getOperand(3).getImm();
1039 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1040 TmpInst.addOperand(Inst.getOperand(0));
1041 TmpInst.addOperand(Inst.getOperand(1));
1042 TmpInst.addOperand(MCOperand::createImm(N));
1043 TmpInst.addOperand(MCOperand::createImm(B - N));
1048 case PPC::RLWINMobm: {
1050 int64_t BM = Inst.getOperand(3).getImm();
1051 if (!isRunOfOnes(BM, MB, ME))
1055 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1056 TmpInst.addOperand(Inst.getOperand(0));
1057 TmpInst.addOperand(Inst.getOperand(1));
1058 TmpInst.addOperand(Inst.getOperand(2));
1059 TmpInst.addOperand(MCOperand::createImm(MB));
1060 TmpInst.addOperand(MCOperand::createImm(ME));
1065 case PPC::RLWIMIobm: {
1067 int64_t BM = Inst.getOperand(3).getImm();
1068 if (!isRunOfOnes(BM, MB, ME))
1072 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1073 TmpInst.addOperand(Inst.getOperand(0));
1074 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1075 TmpInst.addOperand(Inst.getOperand(1));
1076 TmpInst.addOperand(Inst.getOperand(2));
1077 TmpInst.addOperand(MCOperand::createImm(MB));
1078 TmpInst.addOperand(MCOperand::createImm(ME));
1083 case PPC::RLWNMobm: {
1085 int64_t BM = Inst.getOperand(3).getImm();
1086 if (!isRunOfOnes(BM, MB, ME))
1090 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1091 TmpInst.addOperand(Inst.getOperand(0));
1092 TmpInst.addOperand(Inst.getOperand(1));
1093 TmpInst.addOperand(Inst.getOperand(2));
1094 TmpInst.addOperand(MCOperand::createImm(MB));
1095 TmpInst.addOperand(MCOperand::createImm(ME));
1100 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1101 assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1102 Inst.setOpcode(PPC::MFSPR);
1107 case PPC::CP_COPY_FIRST: {
1109 TmpInst.setOpcode(PPC::CP_COPY);
1110 TmpInst.addOperand(Inst.getOperand(0));
1111 TmpInst.addOperand(Inst.getOperand(1));
1112 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1117 case PPC::CP_PASTEx :
1118 case PPC::CP_PASTE_LAST: {
1120 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1121 PPC::CP_PASTE : PPC::CP_PASTEo);
1122 TmpInst.addOperand(Inst.getOperand(0));
1123 TmpInst.addOperand(Inst.getOperand(1));
1124 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1132 static std::string PPCMnemonicSpellCheck(StringRef S, uint64_t FBS,
1133 unsigned VariantID = 0);
1135 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1136 OperandVector &Operands,
1137 MCStreamer &Out, uint64_t &ErrorInfo,
1138 bool MatchingInlineAsm) {
1141 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1143 // Post-process instructions (typically extended mnemonics)
1144 ProcessInstruction(Inst, Operands);
1146 Out.EmitInstruction(Inst, getSTI());
1148 case Match_MissingFeature:
1149 return Error(IDLoc, "instruction use requires an option to be enabled");
1150 case Match_MnemonicFail: {
1151 uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
1152 std::string Suggestion = PPCMnemonicSpellCheck(
1153 ((PPCOperand &)*Operands[0]).getToken(), FBS);
1154 return Error(IDLoc, "invalid instruction" + Suggestion,
1155 ((PPCOperand &)*Operands[0]).getLocRange());
1157 case Match_InvalidOperand: {
1158 SMLoc ErrorLoc = IDLoc;
1159 if (ErrorInfo != ~0ULL) {
1160 if (ErrorInfo >= Operands.size())
1161 return Error(IDLoc, "too few operands for instruction");
1163 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1164 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1167 return Error(ErrorLoc, "invalid operand for instruction");
1171 llvm_unreachable("Implement any new match types added!");
1174 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1175 if (getParser().getTok().is(AsmToken::Identifier)) {
1176 StringRef Name = getParser().getTok().getString();
1177 if (Name.equals_lower("lr")) {
1178 RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1180 } else if (Name.equals_lower("ctr")) {
1181 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1183 } else if (Name.equals_lower("vrsave")) {
1184 RegNo = PPC::VRSAVE;
1186 } else if (Name.startswith_lower("r") &&
1187 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1188 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1189 } else if (Name.startswith_lower("f") &&
1190 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1191 RegNo = FRegs[IntVal];
1192 } else if (Name.startswith_lower("vs") &&
1193 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1194 RegNo = VSRegs[IntVal];
1195 } else if (Name.startswith_lower("v") &&
1196 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1197 RegNo = VRegs[IntVal];
1198 } else if (Name.startswith_lower("q") &&
1199 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1200 RegNo = QFRegs[IntVal];
1201 } else if (Name.startswith_lower("cr") &&
1202 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1203 RegNo = CRRegs[IntVal];
1213 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1214 const AsmToken &Tok = getParser().getTok();
1215 StartLoc = Tok.getLoc();
1216 EndLoc = Tok.getEndLoc();
1219 if (MatchRegisterName(RegNo, IntVal))
1220 return TokError("invalid register name");
1224 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan
1225 /// the expression and check for VK_PPC_LO/HI/HA
1226 /// symbol variants. If all symbols with modifier use the same
1227 /// variant, return the corresponding PPCMCExpr::VariantKind,
1228 /// and a modified expression using the default symbol variant.
1229 /// Otherwise, return NULL.
1230 const MCExpr *PPCAsmParser::
1231 ExtractModifierFromExpr(const MCExpr *E,
1232 PPCMCExpr::VariantKind &Variant) {
1233 MCContext &Context = getParser().getContext();
1234 Variant = PPCMCExpr::VK_PPC_None;
1236 switch (E->getKind()) {
1237 case MCExpr::Target:
1238 case MCExpr::Constant:
1241 case MCExpr::SymbolRef: {
1242 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1244 switch (SRE->getKind()) {
1245 case MCSymbolRefExpr::VK_PPC_LO:
1246 Variant = PPCMCExpr::VK_PPC_LO;
1248 case MCSymbolRefExpr::VK_PPC_HI:
1249 Variant = PPCMCExpr::VK_PPC_HI;
1251 case MCSymbolRefExpr::VK_PPC_HA:
1252 Variant = PPCMCExpr::VK_PPC_HA;
1254 case MCSymbolRefExpr::VK_PPC_HIGH:
1255 Variant = PPCMCExpr::VK_PPC_HIGH;
1257 case MCSymbolRefExpr::VK_PPC_HIGHA:
1258 Variant = PPCMCExpr::VK_PPC_HIGHA;
1260 case MCSymbolRefExpr::VK_PPC_HIGHER:
1261 Variant = PPCMCExpr::VK_PPC_HIGHER;
1263 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1264 Variant = PPCMCExpr::VK_PPC_HIGHERA;
1266 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1267 Variant = PPCMCExpr::VK_PPC_HIGHEST;
1269 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1270 Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1276 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1279 case MCExpr::Unary: {
1280 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1281 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1284 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1287 case MCExpr::Binary: {
1288 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1289 PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1290 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1291 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1296 if (!LHS) LHS = BE->getLHS();
1297 if (!RHS) RHS = BE->getRHS();
1299 if (LHSVariant == PPCMCExpr::VK_PPC_None)
1300 Variant = RHSVariant;
1301 else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1302 Variant = LHSVariant;
1303 else if (LHSVariant == RHSVariant)
1304 Variant = LHSVariant;
1308 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1312 llvm_unreachable("Invalid expression kind!");
1315 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1316 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having
1317 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1318 /// FIXME: This is a hack.
1319 const MCExpr *PPCAsmParser::
1320 FixupVariantKind(const MCExpr *E) {
1321 MCContext &Context = getParser().getContext();
1323 switch (E->getKind()) {
1324 case MCExpr::Target:
1325 case MCExpr::Constant:
1328 case MCExpr::SymbolRef: {
1329 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1330 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1332 switch (SRE->getKind()) {
1333 case MCSymbolRefExpr::VK_TLSGD:
1334 Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1336 case MCSymbolRefExpr::VK_TLSLD:
1337 Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1342 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1345 case MCExpr::Unary: {
1346 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1347 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1348 if (Sub == UE->getSubExpr())
1350 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1353 case MCExpr::Binary: {
1354 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1355 const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1356 const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1357 if (LHS == BE->getLHS() && RHS == BE->getRHS())
1359 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1363 llvm_unreachable("Invalid expression kind!");
1366 /// ParseExpression. This differs from the default "parseExpression" in that
1367 /// it handles modifiers.
1369 ParseExpression(const MCExpr *&EVal) {
1372 return ParseDarwinExpression(EVal);
1375 // Handle \code @l/@ha \endcode
1376 if (getParser().parseExpression(EVal))
1379 EVal = FixupVariantKind(EVal);
1381 PPCMCExpr::VariantKind Variant;
1382 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1384 EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1389 /// ParseDarwinExpression. (MachO Platforms)
1390 /// This differs from the default "parseExpression" in that it handles detection
1391 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present,
1392 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1393 /// syntax form so it is done here. TODO: Determine if there is merit in
1394 /// arranging for this to be done at a higher level.
1396 ParseDarwinExpression(const MCExpr *&EVal) {
1397 MCAsmParser &Parser = getParser();
1398 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1399 switch (getLexer().getKind()) {
1402 case AsmToken::Identifier:
1403 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1404 // something starting with any other char should be part of the
1405 // asm syntax. If handwritten asm includes an identifier like lo16,
1406 // then all bets are off - but no-one would do that, right?
1407 StringRef poss = Parser.getTok().getString();
1408 if (poss.equals_lower("lo16")) {
1409 Variant = PPCMCExpr::VK_PPC_LO;
1410 } else if (poss.equals_lower("hi16")) {
1411 Variant = PPCMCExpr::VK_PPC_HI;
1412 } else if (poss.equals_lower("ha16")) {
1413 Variant = PPCMCExpr::VK_PPC_HA;
1415 if (Variant != PPCMCExpr::VK_PPC_None) {
1416 Parser.Lex(); // Eat the xx16
1417 if (getLexer().isNot(AsmToken::LParen))
1418 return Error(Parser.getTok().getLoc(), "expected '('");
1419 Parser.Lex(); // Eat the '('
1424 if (getParser().parseExpression(EVal))
1427 if (Variant != PPCMCExpr::VK_PPC_None) {
1428 if (getLexer().isNot(AsmToken::RParen))
1429 return Error(Parser.getTok().getLoc(), "expected ')'");
1430 Parser.Lex(); // Eat the ')'
1431 EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1437 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1439 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1440 MCAsmParser &Parser = getParser();
1441 SMLoc S = Parser.getTok().getLoc();
1442 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1445 // Attempt to parse the next token as an immediate
1446 switch (getLexer().getKind()) {
1447 // Special handling for register names. These are interpreted
1448 // as immediates corresponding to the register number.
1449 case AsmToken::Percent:
1450 Parser.Lex(); // Eat the '%'.
1453 if (MatchRegisterName(RegNo, IntVal))
1454 return Error(S, "invalid register name");
1456 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1459 case AsmToken::Identifier:
1460 case AsmToken::LParen:
1461 case AsmToken::Plus:
1462 case AsmToken::Minus:
1463 case AsmToken::Integer:
1465 case AsmToken::Dollar:
1466 case AsmToken::Exclaim:
1467 case AsmToken::Tilde:
1468 // Note that non-register-name identifiers from the compiler will begin
1469 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include
1470 // identifiers like r31foo - so we fall through in the event that parsing
1471 // a register name fails.
1475 if (!MatchRegisterName(RegNo, IntVal)) {
1476 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1480 // All other expressions
1482 if (!ParseExpression(EVal))
1487 return Error(S, "unknown operand");
1490 // Push the parsed operand into the list of operands
1491 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1493 // Check whether this is a TLS call expression
1494 bool TLSCall = false;
1495 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1496 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1498 if (TLSCall && getLexer().is(AsmToken::LParen)) {
1499 const MCExpr *TLSSym;
1501 Parser.Lex(); // Eat the '('.
1502 S = Parser.getTok().getLoc();
1503 if (ParseExpression(TLSSym))
1504 return Error(S, "invalid TLS call expression");
1505 if (getLexer().isNot(AsmToken::RParen))
1506 return Error(Parser.getTok().getLoc(), "missing ')'");
1507 E = Parser.getTok().getLoc();
1508 Parser.Lex(); // Eat the ')'.
1510 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1513 // Otherwise, check for D-form memory operands
1514 if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1515 Parser.Lex(); // Eat the '('.
1516 S = Parser.getTok().getLoc();
1519 switch (getLexer().getKind()) {
1520 case AsmToken::Percent:
1521 Parser.Lex(); // Eat the '%'.
1523 if (MatchRegisterName(RegNo, IntVal))
1524 return Error(S, "invalid register name");
1527 case AsmToken::Integer:
1529 return Error(S, "unexpected integer value");
1530 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1532 return Error(S, "invalid register number");
1534 case AsmToken::Identifier:
1537 if (!MatchRegisterName(RegNo, IntVal)) {
1544 return Error(S, "invalid memory operand");
1547 E = Parser.getTok().getLoc();
1548 if (parseToken(AsmToken::RParen, "missing ')'"))
1550 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1556 /// Parse an instruction mnemonic followed by its operands.
1557 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1558 SMLoc NameLoc, OperandVector &Operands) {
1559 // The first operand is the token for the instruction name.
1560 // If the next character is a '+' or '-', we need to add it to the
1561 // instruction name, to match what TableGen is doing.
1562 std::string NewOpcode;
1563 if (parseOptionalToken(AsmToken::Plus)) {
1568 if (parseOptionalToken(AsmToken::Minus)) {
1573 // If the instruction ends in a '.', we need to create a separate
1574 // token for it, to match what TableGen is doing.
1575 size_t Dot = Name.find('.');
1576 StringRef Mnemonic = Name.slice(0, Dot);
1577 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1579 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1581 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1582 if (Dot != StringRef::npos) {
1583 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1584 StringRef DotStr = Name.slice(Dot, StringRef::npos);
1585 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1587 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1589 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1592 // If there are no more operands then finish
1593 if (parseOptionalToken(AsmToken::EndOfStatement))
1596 // Parse the first operand
1597 if (ParseOperand(Operands))
1600 while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1601 if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1605 // We'll now deal with an unfortunate special case: the syntax for the dcbt
1606 // and dcbtst instructions differs for server vs. embedded cores.
1607 // The syntax for dcbt is:
1608 // dcbt ra, rb, th [server]
1609 // dcbt th, ra, rb [embedded]
1610 // where th can be omitted when it is 0. dcbtst is the same. We take the
1611 // server form to be the default, so swap the operands if we're parsing for
1612 // an embedded core (they'll be swapped again upon printing).
1613 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1614 Operands.size() == 4 &&
1615 (Name == "dcbt" || Name == "dcbtst")) {
1616 std::swap(Operands[1], Operands[3]);
1617 std::swap(Operands[2], Operands[1]);
1623 /// ParseDirective parses the PPC specific directives
1624 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1625 StringRef IDVal = DirectiveID.getIdentifier();
1627 if (IDVal == ".machine")
1628 ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1631 } else if (IDVal == ".word")
1632 ParseDirectiveWord(2, DirectiveID);
1633 else if (IDVal == ".llong")
1634 ParseDirectiveWord(8, DirectiveID);
1635 else if (IDVal == ".tc")
1636 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1637 else if (IDVal == ".machine")
1638 ParseDirectiveMachine(DirectiveID.getLoc());
1639 else if (IDVal == ".abiversion")
1640 ParseDirectiveAbiVersion(DirectiveID.getLoc());
1641 else if (IDVal == ".localentry")
1642 ParseDirectiveLocalEntry(DirectiveID.getLoc());
1648 /// ParseDirectiveWord
1649 /// ::= .word [ expression (, expression)* ]
1650 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1651 auto parseOp = [&]() -> bool {
1652 const MCExpr *Value;
1653 SMLoc ExprLoc = getParser().getTok().getLoc();
1654 if (getParser().parseExpression(Value))
1656 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1657 assert(Size <= 8 && "Invalid size");
1658 uint64_t IntValue = MCE->getValue();
1659 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1660 return Error(ExprLoc, "literal value out of range for '" +
1661 ID.getIdentifier() + "' directive");
1662 getStreamer().EmitIntValue(IntValue, Size);
1664 getStreamer().EmitValue(Value, Size, ExprLoc);
1668 if (parseMany(parseOp))
1669 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1673 /// ParseDirectiveTC
1674 /// ::= .tc [ symbol (, expression)* ]
1675 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1676 MCAsmParser &Parser = getParser();
1677 // Skip TC symbol, which is only used with XCOFF.
1678 while (getLexer().isNot(AsmToken::EndOfStatement)
1679 && getLexer().isNot(AsmToken::Comma))
1681 if (parseToken(AsmToken::Comma))
1682 return addErrorSuffix(" in '.tc' directive");
1684 // Align to word size.
1685 getParser().getStreamer().EmitValueToAlignment(Size);
1687 // Emit expressions.
1688 return ParseDirectiveWord(Size, ID);
1691 /// ParseDirectiveMachine (ELF platforms)
1692 /// ::= .machine [ cpu | "push" | "pop" ]
1693 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1694 MCAsmParser &Parser = getParser();
1695 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1696 Parser.getTok().isNot(AsmToken::String))
1697 return Error(L, "unexpected token in '.machine' directive");
1699 StringRef CPU = Parser.getTok().getIdentifier();
1701 // FIXME: Right now, the parser always allows any available
1702 // instruction, so the .machine directive is not useful.
1703 // Implement ".machine any" (by doing nothing) for the benefit
1704 // of existing assembler code. Likewise, we can then implement
1705 // ".machine push" and ".machine pop" as no-op.
1706 if (CPU != "any" && CPU != "push" && CPU != "pop")
1707 return TokError("unrecognized machine type");
1711 if (parseToken(AsmToken::EndOfStatement))
1712 return addErrorSuffix(" in '.machine' directive");
1714 PPCTargetStreamer &TStreamer =
1715 *static_cast<PPCTargetStreamer *>(
1716 getParser().getStreamer().getTargetStreamer());
1717 TStreamer.emitMachine(CPU);
1722 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1723 /// ::= .machine cpu-identifier
1724 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1725 MCAsmParser &Parser = getParser();
1726 if (Parser.getTok().isNot(AsmToken::Identifier) &&
1727 Parser.getTok().isNot(AsmToken::String))
1728 return Error(L, "unexpected token in directive");
1730 StringRef CPU = Parser.getTok().getIdentifier();
1733 // FIXME: this is only the 'default' set of cpu variants.
1734 // However we don't act on this information at present, this is simply
1735 // allowing parsing to proceed with minimal sanity checking.
1736 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L,
1737 "unrecognized cpu type") ||
1738 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L,
1739 "wrong cpu type specified for 64bit") ||
1740 check(!isPPC64() && CPU == "ppc64", L,
1741 "wrong cpu type specified for 32bit") ||
1742 parseToken(AsmToken::EndOfStatement))
1743 return addErrorSuffix(" in '.machine' directive");
1747 /// ParseDirectiveAbiVersion
1748 /// ::= .abiversion constant-expression
1749 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1751 if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1752 "expected constant expression") ||
1753 parseToken(AsmToken::EndOfStatement))
1754 return addErrorSuffix(" in '.abiversion' directive");
1756 PPCTargetStreamer &TStreamer =
1757 *static_cast<PPCTargetStreamer *>(
1758 getParser().getStreamer().getTargetStreamer());
1759 TStreamer.emitAbiVersion(AbiVersion);
1764 /// ParseDirectiveLocalEntry
1765 /// ::= .localentry symbol, expression
1766 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1768 if (getParser().parseIdentifier(Name))
1769 return Error(L, "expected identifier in '.localentry' directive");
1771 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1774 if (parseToken(AsmToken::Comma) ||
1775 check(getParser().parseExpression(Expr), L, "expected expression") ||
1776 parseToken(AsmToken::EndOfStatement))
1777 return addErrorSuffix(" in '.localentry' directive");
1779 PPCTargetStreamer &TStreamer =
1780 *static_cast<PPCTargetStreamer *>(
1781 getParser().getStreamer().getTargetStreamer());
1782 TStreamer.emitLocalEntry(Sym, Expr);
1789 /// Force static initialization.
1790 extern "C" void LLVMInitializePowerPCAsmParser() {
1791 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1792 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target());
1793 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget());
1796 #define GET_REGISTER_MATCHER
1797 #define GET_MATCHER_IMPLEMENTATION
1798 #define GET_MNEMONIC_SPELL_CHECKER
1799 #include "PPCGenAsmMatcher.inc"
1801 // Define this matcher function after the auto-generated include so we
1802 // have the match class enum definitions.
1803 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1805 // If the kind is a token for a literal immediate, check if our asm
1806 // operand matches. This is for InstAliases which have a fixed-value
1807 // immediate in the syntax.
1810 case MCK_0: ImmVal = 0; break;
1811 case MCK_1: ImmVal = 1; break;
1812 case MCK_2: ImmVal = 2; break;
1813 case MCK_3: ImmVal = 3; break;
1814 case MCK_4: ImmVal = 4; break;
1815 case MCK_5: ImmVal = 5; break;
1816 case MCK_6: ImmVal = 6; break;
1817 case MCK_7: ImmVal = 7; break;
1818 default: return Match_InvalidOperand;
1821 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1822 if (Op.isImm() && Op.getImm() == ImmVal)
1823 return Match_Success;
1825 return Match_InvalidOperand;
1829 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1830 MCSymbolRefExpr::VariantKind Variant,
1833 case MCSymbolRefExpr::VK_PPC_LO:
1834 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1835 case MCSymbolRefExpr::VK_PPC_HI:
1836 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1837 case MCSymbolRefExpr::VK_PPC_HA:
1838 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1839 case MCSymbolRefExpr::VK_PPC_HIGH:
1840 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, false, Ctx);
1841 case MCSymbolRefExpr::VK_PPC_HIGHA:
1842 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, false, Ctx);
1843 case MCSymbolRefExpr::VK_PPC_HIGHER:
1844 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1845 case MCSymbolRefExpr::VK_PPC_HIGHERA:
1846 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1847 case MCSymbolRefExpr::VK_PPC_HIGHEST:
1848 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1849 case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1850 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);