1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCExpr.h"
11 #include "MCTargetDesc/SparcMCTargetDesc.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/ADT/SmallVector.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/ADT/Triple.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCObjectFileInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/SMLoc.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
40 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
41 // namespace. But SPARC backend uses "SP" as its namespace.
47 } // end namespace Sparc
48 } // end namespace llvm
54 class SparcAsmParser : public MCTargetAsmParser {
57 /// @name Auto-generated Match Functions
60 #define GET_ASSEMBLER_HEADER
61 #include "SparcGenAsmMatcher.inc"
65 // public interface of the MCTargetAsmParser.
66 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
67 OperandVector &Operands, MCStreamer &Out,
69 bool MatchingInlineAsm) override;
70 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
71 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
72 SMLoc NameLoc, OperandVector &Operands) override;
73 bool ParseDirective(AsmToken DirectiveID) override;
75 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
76 unsigned Kind) override;
78 // Custom parse functions for Sparc specific operands.
79 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
81 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
84 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
87 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
89 // Helper function for dealing with %lo / %hi in PIC mode.
90 const SparcMCExpr *adjustPICRelocation(SparcMCExpr::VariantKind VK,
91 const MCExpr *subExpr);
93 // returns true if Tok is matched to a register and returns register in RegNo.
94 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
97 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
99 bool is64Bit() const {
100 return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
103 bool expandSET(MCInst &Inst, SMLoc IDLoc,
104 SmallVectorImpl<MCInst> &Instructions);
107 SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
108 const MCInstrInfo &MII,
109 const MCTargetOptions &Options)
110 : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
111 Parser.addAliasForDirective(".half", ".2byte");
112 Parser.addAliasForDirective(".uahalf", ".2byte");
113 Parser.addAliasForDirective(".word", ".4byte");
114 Parser.addAliasForDirective(".uaword", ".4byte");
115 Parser.addAliasForDirective(".nword", is64Bit() ? ".8byte" : ".4byte");
117 Parser.addAliasForDirective(".xword", ".8byte");
119 // Initialize the set of available features.
120 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
124 } // end anonymous namespace
126 static const MCPhysReg IntRegs[32] = {
127 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
128 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
129 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
130 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
131 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
132 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
133 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
134 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
136 static const MCPhysReg FloatRegs[32] = {
137 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
138 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
139 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
140 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
141 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
142 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
143 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
144 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
146 static const MCPhysReg DoubleRegs[32] = {
147 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
148 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
149 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
150 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
151 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
152 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
153 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
154 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
156 static const MCPhysReg QuadFPRegs[32] = {
157 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
158 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
159 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
160 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
162 static const MCPhysReg ASRRegs[32] = {
163 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
164 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
165 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
166 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
167 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
168 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
169 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
170 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
172 static const MCPhysReg IntPairRegs[] = {
173 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
174 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
175 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
176 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
178 static const MCPhysReg CoprocRegs[32] = {
179 Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,
180 Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
181 Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
182 Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
183 Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
184 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
185 Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
186 Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
188 static const MCPhysReg CoprocPairRegs[] = {
189 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
190 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
191 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
192 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
196 /// SparcOperand - Instances of this class represent a parsed Sparc machine
198 class SparcOperand : public MCParsedAsmOperand {
221 SMLoc StartLoc, EndLoc;
251 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
253 bool isToken() const override { return Kind == k_Token; }
254 bool isReg() const override { return Kind == k_Register; }
255 bool isImm() const override { return Kind == k_Immediate; }
256 bool isMem() const override { return isMEMrr() || isMEMri(); }
257 bool isMEMrr() const { return Kind == k_MemoryReg; }
258 bool isMEMri() const { return Kind == k_MemoryImm; }
260 bool isIntReg() const {
261 return (Kind == k_Register && Reg.Kind == rk_IntReg);
264 bool isFloatReg() const {
265 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
268 bool isFloatOrDoubleReg() const {
269 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
270 || Reg.Kind == rk_DoubleReg));
273 bool isCoprocReg() const {
274 return (Kind == k_Register && Reg.Kind == rk_CoprocReg);
277 StringRef getToken() const {
278 assert(Kind == k_Token && "Invalid access!");
279 return StringRef(Tok.Data, Tok.Length);
282 unsigned getReg() const override {
283 assert((Kind == k_Register) && "Invalid access!");
287 const MCExpr *getImm() const {
288 assert((Kind == k_Immediate) && "Invalid access!");
292 unsigned getMemBase() const {
293 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
297 unsigned getMemOffsetReg() const {
298 assert((Kind == k_MemoryReg) && "Invalid access!");
299 return Mem.OffsetReg;
302 const MCExpr *getMemOff() const {
303 assert((Kind == k_MemoryImm) && "Invalid access!");
307 /// getStartLoc - Get the location of the first token of this operand.
308 SMLoc getStartLoc() const override {
311 /// getEndLoc - Get the location of the last token of this operand.
312 SMLoc getEndLoc() const override {
316 void print(raw_ostream &OS) const override {
318 case k_Token: OS << "Token: " << getToken() << "\n"; break;
319 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
320 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
321 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
322 << getMemOffsetReg() << "\n"; break;
323 case k_MemoryImm: assert(getMemOff() != nullptr);
324 OS << "Mem: " << getMemBase()
325 << "+" << *getMemOff()
330 void addRegOperands(MCInst &Inst, unsigned N) const {
331 assert(N == 1 && "Invalid number of operands!");
332 Inst.addOperand(MCOperand::createReg(getReg()));
335 void addImmOperands(MCInst &Inst, unsigned N) const {
336 assert(N == 1 && "Invalid number of operands!");
337 const MCExpr *Expr = getImm();
341 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
342 // Add as immediate when possible. Null MCExpr = 0.
344 Inst.addOperand(MCOperand::createImm(0));
345 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
346 Inst.addOperand(MCOperand::createImm(CE->getValue()));
348 Inst.addOperand(MCOperand::createExpr(Expr));
351 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
352 assert(N == 2 && "Invalid number of operands!");
354 Inst.addOperand(MCOperand::createReg(getMemBase()));
356 assert(getMemOffsetReg() != 0 && "Invalid offset");
357 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
360 void addMEMriOperands(MCInst &Inst, unsigned N) const {
361 assert(N == 2 && "Invalid number of operands!");
363 Inst.addOperand(MCOperand::createReg(getMemBase()));
365 const MCExpr *Expr = getMemOff();
369 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
370 auto Op = make_unique<SparcOperand>(k_Token);
371 Op->Tok.Data = Str.data();
372 Op->Tok.Length = Str.size();
378 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
380 auto Op = make_unique<SparcOperand>(k_Register);
381 Op->Reg.RegNum = RegNum;
382 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
388 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
390 auto Op = make_unique<SparcOperand>(k_Immediate);
397 static bool MorphToIntPairReg(SparcOperand &Op) {
398 unsigned Reg = Op.getReg();
399 assert(Op.Reg.Kind == rk_IntReg);
400 unsigned regIdx = 32;
401 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
402 regIdx = Reg - Sparc::G0;
403 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
404 regIdx = Reg - Sparc::O0 + 8;
405 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
406 regIdx = Reg - Sparc::L0 + 16;
407 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
408 regIdx = Reg - Sparc::I0 + 24;
409 if (regIdx % 2 || regIdx > 31)
411 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
412 Op.Reg.Kind = rk_IntPairReg;
416 static bool MorphToDoubleReg(SparcOperand &Op) {
417 unsigned Reg = Op.getReg();
418 assert(Op.Reg.Kind == rk_FloatReg);
419 unsigned regIdx = Reg - Sparc::F0;
420 if (regIdx % 2 || regIdx > 31)
422 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
423 Op.Reg.Kind = rk_DoubleReg;
427 static bool MorphToQuadReg(SparcOperand &Op) {
428 unsigned Reg = Op.getReg();
430 switch (Op.Reg.Kind) {
431 default: llvm_unreachable("Unexpected register kind!");
433 regIdx = Reg - Sparc::F0;
434 if (regIdx % 4 || regIdx > 31)
436 Reg = QuadFPRegs[regIdx / 4];
439 regIdx = Reg - Sparc::D0;
440 if (regIdx % 2 || regIdx > 31)
442 Reg = QuadFPRegs[regIdx / 2];
446 Op.Reg.Kind = rk_QuadReg;
450 static bool MorphToCoprocPairReg(SparcOperand &Op) {
451 unsigned Reg = Op.getReg();
452 assert(Op.Reg.Kind == rk_CoprocReg);
453 unsigned regIdx = 32;
454 if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
455 regIdx = Reg - Sparc::C0;
456 if (regIdx % 2 || regIdx > 31)
458 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
459 Op.Reg.Kind = rk_CoprocPairReg;
463 static std::unique_ptr<SparcOperand>
464 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
465 unsigned offsetReg = Op->getReg();
466 Op->Kind = k_MemoryReg;
468 Op->Mem.OffsetReg = offsetReg;
469 Op->Mem.Off = nullptr;
473 static std::unique_ptr<SparcOperand>
474 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
475 auto Op = make_unique<SparcOperand>(k_MemoryReg);
477 Op->Mem.OffsetReg = Sparc::G0; // always 0
478 Op->Mem.Off = nullptr;
484 static std::unique_ptr<SparcOperand>
485 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
486 const MCExpr *Imm = Op->getImm();
487 Op->Kind = k_MemoryImm;
489 Op->Mem.OffsetReg = 0;
495 } // end anonymous namespace
497 bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
498 SmallVectorImpl<MCInst> &Instructions) {
499 MCOperand MCRegOp = Inst.getOperand(0);
500 MCOperand MCValOp = Inst.getOperand(1);
501 assert(MCRegOp.isReg());
502 assert(MCValOp.isImm() || MCValOp.isExpr());
504 // the imm operand can be either an expression or an immediate.
505 bool IsImm = Inst.getOperand(1).isImm();
506 int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
508 // Allow either a signed or unsigned 32-bit immediate.
509 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
511 "set: argument must be between -2147483648 and 4294967295");
514 // If the value was expressed as a large unsigned number, that's ok.
515 // We want to see if it "looks like" a small signed number.
516 int32_t ImmValue = RawImmValue;
517 // For 'set' you can't use 'or' with a negative operand on V9 because
518 // that would splat the sign bit across the upper half of the destination
519 // register, whereas 'set' is defined to zero the high 32 bits.
520 bool IsEffectivelyImm13 =
521 IsImm && ((is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
522 const MCExpr *ValExpr;
524 ValExpr = MCConstantExpr::create(ImmValue, getContext());
526 ValExpr = MCValOp.getExpr();
528 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
530 // If not just a signed imm13 value, then either we use a 'sethi' with a
531 // following 'or', or a 'sethi' by itself if there are no more 1 bits.
532 // In either case, start with the 'sethi'.
533 if (!IsEffectivelyImm13) {
535 const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr);
536 TmpInst.setLoc(IDLoc);
537 TmpInst.setOpcode(SP::SETHIi);
538 TmpInst.addOperand(MCRegOp);
539 TmpInst.addOperand(MCOperand::createExpr(Expr));
540 Instructions.push_back(TmpInst);
544 // The low bits require touching in 3 cases:
545 // * A non-immediate value will always require both instructions.
546 // * An effectively imm13 value needs only an 'or' instruction.
547 // * Otherwise, an immediate that is not effectively imm13 requires the
548 // 'or' only if bits remain after clearing the 22 bits that 'sethi' set.
549 // If the low bits are known zeros, there's nothing to do.
550 // In the second case, and only in that case, must we NOT clear
551 // bits of the immediate value via the %lo() assembler function.
552 // Note also, the 'or' instruction doesn't mind a large value in the case
553 // where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean.
554 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
557 if (IsEffectivelyImm13)
560 Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
561 TmpInst.setLoc(IDLoc);
562 TmpInst.setOpcode(SP::ORri);
563 TmpInst.addOperand(MCRegOp);
564 TmpInst.addOperand(PrevReg);
565 TmpInst.addOperand(MCOperand::createExpr(Expr));
566 Instructions.push_back(TmpInst);
571 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
572 OperandVector &Operands,
575 bool MatchingInlineAsm) {
577 SmallVector<MCInst, 8> Instructions;
578 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
580 switch (MatchResult) {
581 case Match_Success: {
582 switch (Inst.getOpcode()) {
585 Instructions.push_back(Inst);
588 if (expandSET(Inst, IDLoc, Instructions))
593 for (const MCInst &I : Instructions) {
594 Out.EmitInstruction(I, getSTI());
599 case Match_MissingFeature:
601 "instruction requires a CPU feature not currently enabled");
603 case Match_InvalidOperand: {
604 SMLoc ErrorLoc = IDLoc;
605 if (ErrorInfo != ~0ULL) {
606 if (ErrorInfo >= Operands.size())
607 return Error(IDLoc, "too few operands for instruction");
609 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
610 if (ErrorLoc == SMLoc())
614 return Error(ErrorLoc, "invalid operand for instruction");
616 case Match_MnemonicFail:
617 return Error(IDLoc, "invalid instruction mnemonic");
619 llvm_unreachable("Implement any new match types added!");
622 bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
624 const AsmToken &Tok = Parser.getTok();
625 StartLoc = Tok.getLoc();
626 EndLoc = Tok.getEndLoc();
628 if (getLexer().getKind() != AsmToken::Percent)
631 unsigned regKind = SparcOperand::rk_None;
632 if (matchRegisterName(Tok, RegNo, regKind)) {
637 return Error(StartLoc, "invalid register name");
640 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
643 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
644 StringRef Name, SMLoc NameLoc,
645 OperandVector &Operands) {
647 // First operand in MCInst is instruction mnemonic.
648 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
650 // apply mnemonic aliases, if any, so that we can parse operands correctly.
651 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
653 if (getLexer().isNot(AsmToken::EndOfStatement)) {
654 // Read the first operand.
655 if (getLexer().is(AsmToken::Comma)) {
656 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
657 SMLoc Loc = getLexer().getLoc();
658 return Error(Loc, "unexpected token");
661 if (parseOperand(Operands, Name) != MatchOperand_Success) {
662 SMLoc Loc = getLexer().getLoc();
663 return Error(Loc, "unexpected token");
666 while (getLexer().is(AsmToken::Comma) || getLexer().is(AsmToken::Plus)) {
667 if (getLexer().is(AsmToken::Plus)) {
668 // Plus tokens are significant in software_traps (p83, sparcv8.pdf). We must capture them.
669 Operands.push_back(SparcOperand::CreateToken("+", Parser.getTok().getLoc()));
671 Parser.Lex(); // Eat the comma or plus.
672 // Parse and remember the operand.
673 if (parseOperand(Operands, Name) != MatchOperand_Success) {
674 SMLoc Loc = getLexer().getLoc();
675 return Error(Loc, "unexpected token");
679 if (getLexer().isNot(AsmToken::EndOfStatement)) {
680 SMLoc Loc = getLexer().getLoc();
681 return Error(Loc, "unexpected token");
683 Parser.Lex(); // Consume the EndOfStatement.
687 bool SparcAsmParser::
688 ParseDirective(AsmToken DirectiveID)
690 StringRef IDVal = DirectiveID.getString();
692 if (IDVal == ".register") {
693 // For now, ignore .register directive.
694 Parser.eatToEndOfStatement();
697 if (IDVal == ".proc") {
698 // For compatibility, ignore this directive.
699 // (It's supposed to be an "optimization" in the Sun assembler)
700 Parser.eatToEndOfStatement();
704 // Let the MC layer to handle other directives.
709 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
711 unsigned BaseReg = 0;
713 if (ParseRegister(BaseReg, S, E)) {
714 return MatchOperand_NoMatch;
717 switch (getLexer().getKind()) {
718 default: return MatchOperand_NoMatch;
720 case AsmToken::Comma:
721 case AsmToken::RBrac:
722 case AsmToken::EndOfStatement:
723 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
724 return MatchOperand_Success;
726 case AsmToken:: Plus:
727 Parser.Lex(); // Eat the '+'
729 case AsmToken::Minus:
733 std::unique_ptr<SparcOperand> Offset;
734 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
735 if (ResTy != MatchOperand_Success || !Offset)
736 return MatchOperand_NoMatch;
739 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
740 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
742 return MatchOperand_Success;
746 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
748 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
750 // If there wasn't a custom match, try the generic matcher below. Otherwise,
751 // there was a match, but an error occurred, in which case, just return that
752 // the operand parsing failed.
753 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
756 if (getLexer().is(AsmToken::LBrac)) {
758 Operands.push_back(SparcOperand::CreateToken("[",
759 Parser.getTok().getLoc()));
760 Parser.Lex(); // Eat the [
762 if (Mnemonic == "cas" || Mnemonic == "casx" || Mnemonic == "casa") {
763 SMLoc S = Parser.getTok().getLoc();
764 if (getLexer().getKind() != AsmToken::Percent)
765 return MatchOperand_NoMatch;
766 Parser.Lex(); // eat %
768 unsigned RegNo, RegKind;
769 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
770 return MatchOperand_NoMatch;
772 Parser.Lex(); // Eat the identifier token.
773 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
774 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
775 ResTy = MatchOperand_Success;
777 ResTy = parseMEMOperand(Operands);
780 if (ResTy != MatchOperand_Success)
783 if (!getLexer().is(AsmToken::RBrac))
784 return MatchOperand_ParseFail;
786 Operands.push_back(SparcOperand::CreateToken("]",
787 Parser.getTok().getLoc()));
788 Parser.Lex(); // Eat the ]
790 // Parse an optional address-space identifier after the address.
791 if (getLexer().is(AsmToken::Integer)) {
792 std::unique_ptr<SparcOperand> Op;
793 ResTy = parseSparcAsmOperand(Op, false);
794 if (ResTy != MatchOperand_Success || !Op)
795 return MatchOperand_ParseFail;
796 Operands.push_back(std::move(Op));
798 return MatchOperand_Success;
801 std::unique_ptr<SparcOperand> Op;
803 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
804 if (ResTy != MatchOperand_Success || !Op)
805 return MatchOperand_ParseFail;
807 // Push the parsed operand into the list of operands
808 Operands.push_back(std::move(Op));
810 return MatchOperand_Success;
814 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
816 SMLoc S = Parser.getTok().getLoc();
817 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
821 switch (getLexer().getKind()) {
824 case AsmToken::Percent:
825 Parser.Lex(); // Eat the '%'.
828 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
829 StringRef name = Parser.getTok().getString();
830 Parser.Lex(); // Eat the identifier token.
831 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
834 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
837 Op = SparcOperand::CreateToken("%psr", S);
840 Op = SparcOperand::CreateToken("%fsr", S);
843 Op = SparcOperand::CreateToken("%fq", S);
846 Op = SparcOperand::CreateToken("%csr", S);
849 Op = SparcOperand::CreateToken("%cq", S);
852 Op = SparcOperand::CreateToken("%wim", S);
855 Op = SparcOperand::CreateToken("%tbr", S);
859 Op = SparcOperand::CreateToken("%xcc", S);
861 Op = SparcOperand::CreateToken("%icc", S);
866 if (matchSparcAsmModifiers(EVal, E)) {
867 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
868 Op = SparcOperand::CreateImm(EVal, S, E);
872 case AsmToken::Minus:
873 case AsmToken::Integer:
874 case AsmToken::LParen:
876 if (!getParser().parseExpression(EVal, E))
877 Op = SparcOperand::CreateImm(EVal, S, E);
880 case AsmToken::Identifier: {
881 StringRef Identifier;
882 if (!getParser().parseIdentifier(Identifier)) {
883 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
884 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
886 const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
888 SparcMCExpr::VariantKind Kind = SparcMCExpr::VK_Sparc_13;
890 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
892 Kind = SparcMCExpr::VK_Sparc_WPLT30;
894 Kind = SparcMCExpr::VK_Sparc_GOT13;
897 Res = SparcMCExpr::create(Kind, Res, getContext());
899 Op = SparcOperand::CreateImm(Res, S, E);
904 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
908 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
909 // parse (,a|,pn|,pt)+
911 while (getLexer().is(AsmToken::Comma)) {
912 Parser.Lex(); // Eat the comma
914 if (!getLexer().is(AsmToken::Identifier))
915 return MatchOperand_ParseFail;
916 StringRef modName = Parser.getTok().getString();
917 if (modName == "a" || modName == "pn" || modName == "pt") {
918 Operands.push_back(SparcOperand::CreateToken(modName,
919 Parser.getTok().getLoc()));
920 Parser.Lex(); // eat the identifier.
923 return MatchOperand_Success;
926 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
930 RegKind = SparcOperand::rk_None;
931 if (Tok.is(AsmToken::Identifier)) {
932 StringRef name = Tok.getString();
935 if (name.equals("fp")) {
937 RegKind = SparcOperand::rk_IntReg;
941 if (name.equals("sp")) {
943 RegKind = SparcOperand::rk_IntReg;
947 if (name.equals("y")) {
949 RegKind = SparcOperand::rk_Special;
953 if (name.substr(0, 3).equals_lower("asr")
954 && !name.substr(3).getAsInteger(10, intVal)
955 && intVal > 0 && intVal < 32) {
956 RegNo = ASRRegs[intVal];
957 RegKind = SparcOperand::rk_Special;
961 // %fprs is an alias of %asr6.
962 if (name.equals("fprs")) {
964 RegKind = SparcOperand::rk_Special;
968 if (name.equals("icc")) {
970 RegKind = SparcOperand::rk_Special;
974 if (name.equals("psr")) {
976 RegKind = SparcOperand::rk_Special;
980 if (name.equals("fsr")) {
982 RegKind = SparcOperand::rk_Special;
986 if (name.equals("fq")) {
988 RegKind = SparcOperand::rk_Special;
992 if (name.equals("csr")) {
994 RegKind = SparcOperand::rk_Special;
998 if (name.equals("cq")) {
1000 RegKind = SparcOperand::rk_Special;
1004 if (name.equals("wim")) {
1006 RegKind = SparcOperand::rk_Special;
1010 if (name.equals("tbr")) {
1012 RegKind = SparcOperand::rk_Special;
1016 if (name.equals("xcc")) {
1017 // FIXME:: check 64bit.
1019 RegKind = SparcOperand::rk_Special;
1024 if (name.substr(0, 3).equals_lower("fcc")
1025 && !name.substr(3).getAsInteger(10, intVal)
1027 // FIXME: check 64bit and handle %fcc1 - %fcc3
1028 RegNo = Sparc::FCC0 + intVal;
1029 RegKind = SparcOperand::rk_Special;
1034 if (name.substr(0, 1).equals_lower("g")
1035 && !name.substr(1).getAsInteger(10, intVal)
1037 RegNo = IntRegs[intVal];
1038 RegKind = SparcOperand::rk_IntReg;
1042 if (name.substr(0, 1).equals_lower("o")
1043 && !name.substr(1).getAsInteger(10, intVal)
1045 RegNo = IntRegs[8 + intVal];
1046 RegKind = SparcOperand::rk_IntReg;
1049 if (name.substr(0, 1).equals_lower("l")
1050 && !name.substr(1).getAsInteger(10, intVal)
1052 RegNo = IntRegs[16 + intVal];
1053 RegKind = SparcOperand::rk_IntReg;
1056 if (name.substr(0, 1).equals_lower("i")
1057 && !name.substr(1).getAsInteger(10, intVal)
1059 RegNo = IntRegs[24 + intVal];
1060 RegKind = SparcOperand::rk_IntReg;
1064 if (name.substr(0, 1).equals_lower("f")
1065 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1066 RegNo = FloatRegs[intVal];
1067 RegKind = SparcOperand::rk_FloatReg;
1071 if (name.substr(0, 1).equals_lower("f")
1072 && !name.substr(1, 2).getAsInteger(10, intVal)
1073 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
1075 RegNo = DoubleRegs[intVal/2];
1076 RegKind = SparcOperand::rk_DoubleReg;
1081 if (name.substr(0, 1).equals_lower("r")
1082 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1083 RegNo = IntRegs[intVal];
1084 RegKind = SparcOperand::rk_IntReg;
1089 if (name.substr(0, 1).equals_lower("c")
1090 && !name.substr(1).getAsInteger(10, intVal)
1092 RegNo = CoprocRegs[intVal];
1093 RegKind = SparcOperand::rk_CoprocReg;
1097 if (name.equals("tpc")) {
1099 RegKind = SparcOperand::rk_Special;
1102 if (name.equals("tnpc")) {
1103 RegNo = Sparc::TNPC;
1104 RegKind = SparcOperand::rk_Special;
1107 if (name.equals("tstate")) {
1108 RegNo = Sparc::TSTATE;
1109 RegKind = SparcOperand::rk_Special;
1112 if (name.equals("tt")) {
1114 RegKind = SparcOperand::rk_Special;
1117 if (name.equals("tick")) {
1118 RegNo = Sparc::TICK;
1119 RegKind = SparcOperand::rk_Special;
1122 if (name.equals("tba")) {
1124 RegKind = SparcOperand::rk_Special;
1127 if (name.equals("pstate")) {
1128 RegNo = Sparc::PSTATE;
1129 RegKind = SparcOperand::rk_Special;
1132 if (name.equals("tl")) {
1134 RegKind = SparcOperand::rk_Special;
1137 if (name.equals("pil")) {
1139 RegKind = SparcOperand::rk_Special;
1142 if (name.equals("cwp")) {
1144 RegKind = SparcOperand::rk_Special;
1147 if (name.equals("cansave")) {
1148 RegNo = Sparc::CANSAVE;
1149 RegKind = SparcOperand::rk_Special;
1152 if (name.equals("canrestore")) {
1153 RegNo = Sparc::CANRESTORE;
1154 RegKind = SparcOperand::rk_Special;
1157 if (name.equals("cleanwin")) {
1158 RegNo = Sparc::CLEANWIN;
1159 RegKind = SparcOperand::rk_Special;
1162 if (name.equals("otherwin")) {
1163 RegNo = Sparc::OTHERWIN;
1164 RegKind = SparcOperand::rk_Special;
1167 if (name.equals("wstate")) {
1168 RegNo = Sparc::WSTATE;
1169 RegKind = SparcOperand::rk_Special;
1176 // Determine if an expression contains a reference to the symbol
1177 // "_GLOBAL_OFFSET_TABLE_".
1178 static bool hasGOTReference(const MCExpr *Expr) {
1179 switch (Expr->getKind()) {
1180 case MCExpr::Target:
1181 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1182 return hasGOTReference(SE->getSubExpr());
1185 case MCExpr::Constant:
1188 case MCExpr::Binary: {
1189 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
1190 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
1193 case MCExpr::SymbolRef: {
1194 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
1195 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
1199 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
1205 SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK,
1206 const MCExpr *subExpr) {
1207 // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently.
1208 // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is
1209 // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted
1210 // as %got10 or %got22 relocation.
1212 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1215 case SparcMCExpr::VK_Sparc_LO:
1216 VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC10
1217 : SparcMCExpr::VK_Sparc_GOT10);
1219 case SparcMCExpr::VK_Sparc_HI:
1220 VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC22
1221 : SparcMCExpr::VK_Sparc_GOT22);
1226 return SparcMCExpr::create(VK, subExpr, getContext());
1229 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
1231 AsmToken Tok = Parser.getTok();
1232 if (!Tok.is(AsmToken::Identifier))
1235 StringRef name = Tok.getString();
1237 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
1239 if (VK == SparcMCExpr::VK_Sparc_None)
1242 Parser.Lex(); // Eat the identifier.
1243 if (Parser.getTok().getKind() != AsmToken::LParen)
1246 Parser.Lex(); // Eat the LParen token.
1247 const MCExpr *subExpr;
1248 if (Parser.parseParenExpression(subExpr, EndLoc))
1251 EVal = adjustPICRelocation(VK, subExpr);
1255 extern "C" void LLVMInitializeSparcAsmParser() {
1256 RegisterMCAsmParser<SparcAsmParser> A(getTheSparcTarget());
1257 RegisterMCAsmParser<SparcAsmParser> B(getTheSparcV9Target());
1258 RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget());
1261 #define GET_REGISTER_MATCHER
1262 #define GET_MATCHER_IMPLEMENTATION
1263 #include "SparcGenAsmMatcher.inc"
1265 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1267 SparcOperand &Op = (SparcOperand &)GOp;
1268 if (Op.isFloatOrDoubleReg()) {
1272 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1273 return MCTargetAsmParser::Match_Success;
1276 if (SparcOperand::MorphToQuadReg(Op))
1277 return MCTargetAsmParser::Match_Success;
1281 if (Op.isIntReg() && Kind == MCK_IntPair) {
1282 if (SparcOperand::MorphToIntPairReg(Op))
1283 return MCTargetAsmParser::Match_Success;
1285 if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {
1286 if (SparcOperand::MorphToCoprocPairReg(Op))
1287 return MCTargetAsmParser::Match_Success;
1289 return Match_InvalidOperand;