src/arm/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52                 rtc0 = &ds1341;
  53         };
  54
  55         mdio1: mdio {
  56                 compatible = "virtual,mdio-gpio";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_mdio1>;
  61                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  62                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  63
  64                 phy: ethernet-phy@0 {
  65                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  66                         pinctrl-names = "default";
  67                         reg = <0>;
  68                         interrupt-parent = <&gpio3>;
  69                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  70                 };
  71         };
  72
  73         reg_28p0v: regulator-28p0v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "28V_IN";
  76                 regulator-min-microvolt = <28000000>;
  77                 regulator-max-microvolt = <28000000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_12p0v: regulator-12p0v {
  82                 compatible = "regulator-fixed";
  83                 vin-supply = <&reg_28p0v>;
  84                 regulator-name = "12V_MAIN";
  85                 regulator-min-microvolt = <12000000>;
  86                 regulator-max-microvolt = <12000000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v_main: regulator-5p0v-main {
  91                 compatible = "regulator-fixed";
  92                 vin-supply = <&reg_12p0v>;
  93                 regulator-name = "5V_MAIN";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_5p0v_user_usb: regulator-5p0v-user-usb {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 103                 vin-supply = <&reg_5p0v_main>;
 104                 regulator-name = "5V_USER_USB";
 105                 regulator-min-microvolt = <5000000>;
 106                 regulator-max-microvolt = <5000000>;
 107                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 108                 startup-delay-us = <1000>;
 109         };
 110
 111         reg_3p3v_pmic: regulator-3p3v-pmic {
 112                 compatible = "regulator-fixed";
 113                 vin-supply = <&reg_12p0v>;
 114                 regulator-name = "PMIC_3V3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 regulator-always-on;
 118         };
 119
 120         reg_3p3v: regulator-3p3v {
 121                 compatible = "regulator-fixed";
 122                 vin-supply = <&reg_3p3v_pmic>;
 123                 regulator-name = "GEN_3V3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 regulator-always-on;
 127         };
 128
 129         reg_3p3v_sd: regulator-3p3v-sd {
 130                 compatible = "regulator-fixed";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 133                 vin-supply = <&reg_3p3v>;
 134                 regulator-name = "3V3_SD";
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-max-microvolt = <3300000>;
 137                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 138                 startup-delay-us = <1000>;
 139                 enable-active-high;
 140                 regulator-always-on;
 141         };
 142
 143         reg_3p3v_display: regulator-3p3v-display {
 144                 compatible = "regulator-fixed";
 145                 vin-supply = <&reg_12p0v>;
 146                 regulator-name = "3V3_DISPLAY";
 147                 regulator-min-microvolt = <3300000>;
 148                 regulator-max-microvolt = <3300000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_3p3v_ssd: regulator-3p3v-ssd {
 153                 compatible = "regulator-fixed";
 154                 vin-supply = <&reg_12p0v>;
 155                 regulator-name = "3V3_SSD";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 regulator-always-on;
 159         };
 160
 161         sound1 {
 162                 compatible = "simple-audio-card";
 163                 simple-audio-card,name = "Front";
 164                 simple-audio-card,format = "i2s";
 165                 simple-audio-card,bitclock-master = <&sound1_codec>;
 166                 simple-audio-card,frame-master = <&sound1_codec>;
 167                 simple-audio-card,widgets =
 168                         "Headphone", "Headphone Jack";
 169                 simple-audio-card,routing =
 170                         "Headphone Jack", "HPLEFT",
 171                         "Headphone Jack", "HPRIGHT",
 172                         "LEFTIN", "HPL",
 173                         "RIGHTIN", "HPR";
 174                 simple-audio-card,aux-devs = <&hpa1>;
 175
 176                 sound1_cpu: simple-audio-card,cpu {
 177                         sound-dai = <&ssi2>;
 178                 };
 179
 180                 sound1_codec: simple-audio-card,codec {
 181                         sound-dai = <&codec1>;
 182                         clocks = <&cs2000>;
 183                 };
 184         };
 185
 186         sound2 {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "Back";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,bitclock-master = <&sound2_codec>;
 191                 simple-audio-card,frame-master = <&sound2_codec>;
 192                 simple-audio-card,widgets =
 193                         "Headphone", "Headphone Jack";
 194                 simple-audio-card,routing =
 195                         "Headphone Jack", "HPLEFT",
 196                         "Headphone Jack", "HPRIGHT",
 197                         "LEFTIN", "HPL",
 198                         "RIGHTIN", "HPR";
 199                 simple-audio-card,aux-devs = <&hpa2>;
 200
 201                 sound2_cpu: simple-audio-card,cpu {
 202                         sound-dai = <&ssi1>;
 203                 };
 204
 205                 sound2_codec: simple-audio-card,codec {
 206                         sound-dai = <&codec2>;
 207                         clocks = <&cs2000>;
 208                 };
 209         };
 210
 211         panel {
 212                 power-supply = <&reg_3p3v_display>;
 213                 status = "disabled";
 214
 215                 port {
 216                         panel_in: endpoint {
 217                                 remote-endpoint = <&lvds0_out>;
 218                         };
 219                 };
 220         };
 221
 222         disp0: disp0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "fsl,imx-parallel-display";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_disp0>;
 228                 status = "disabled";
 229
 230                 port@0 {
 231                         reg = <0>;
 232
 233                         disp0_in_0: endpoint {
 234                                 remote-endpoint = <&ipu1_di0_disp0>;
 235                         };
 236                 };
 237
 238                 port@1 {
 239                         reg = <1>;
 240
 241                         disp0_out: endpoint {
 242                                 remote-endpoint = <&tc358767_in>;
 243                         };
 244                 };
 245         };
 246
 247         cs2000_ref: cs2000-ref {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <24576000>;
 251         };
 252
 253         cs2000_in_dummy: cs2000-in-dummy {
 254                 compatible = "fixed-clock";
 255                 #clock-cells = <0>;
 256                 clock-frequency = <0>;
 257         };
 258
 259         edp_refclk: edp-refclk {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <19200000>;
 263         };
 264 };
 265
 266 &cpu0 {
 267         fsl,soc-operating-points = <
 268                 /* ARM kHz  SOC-PU uV */
 269                 1200000 1300000
 270                 996000  1275000
 271                 852000  1275000
 272                 792000  1200000
 273                 396000  1200000
 274         >;
 275 };
 276
 277 &reg_arm {
 278         vin-supply = <&sw1a_reg>;
 279 };
 280
 281 &reg_pu {
 282         vin-supply = <&sw1c_reg>;
 283 };
 284
 285 &reg_soc {
 286         vin-supply = <&sw1c_reg>;
 287 };
 288
 289 &ldb {
 290         lvds-channel@0 {
 291                 port@4 {
 292                         reg = <4>;
 293
 294                         lvds0_out: endpoint {
 295                                 remote-endpoint = <&panel_in>;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &uart1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_uart1>;
 304         status = "okay";
 305 };
 306
 307 &uart3 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_uart3>;
 310         uart-has-rtscts;
 311         linux,rs485-enabled-at-boot-time;
 312         status = "okay";
 313 };
 314
 315 &uart4 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart4>;
 318         status = "okay";
 319
 320         rave-sp {
 321                 compatible = "zii,rave-sp-rdu2";
 322                 current-speed = <1000000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <1>;
 325
 326                 watchdog {
 327                         compatible = "zii,rave-sp-watchdog";
 328                 };
 329
 330                 backlight {
 331                         compatible = "zii,rave-sp-backlight";
 332                 };
 333
 334                 pwrbutton {
 335                         compatible = "zii,rave-sp-pwrbutton";
 336                 };
 337
 338                 eeprom@a3 {
 339                         compatible = "zii,rave-sp-eeprom";
 340                         reg = <0xa3 0x4000>;
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343                         zii,eeprom-name = "dds-eeprom";
 344                 };
 345
 346                 eeprom@a4 {
 347                         compatible = "zii,rave-sp-eeprom";
 348                         reg = <0xa4 0x4000>;
 349                         #address-cells = <1>;
 350                         #size-cells = <1>;
 351                         zii,eeprom-name = "main-eeprom";
 352                 };
 353         };
 354 };
 355
 356 &ecspi1 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_ecspi1>;
 359         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 360         status = "okay";
 361
 362         flash@0 {
 363                 compatible = "st,m25p128", "jedec,spi-nor";
 364                 spi-max-frequency = <20000000>;
 365                 reg = <0>;
 366         };
 367 };
 368
 369 &i2c1 {
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&pinctrl_i2c1>;
 372         clock-frequency = <100000>;
 373         status = "okay";
 374
 375         codec2: codec@18 {
 376                 compatible = "ti,tlv320dac3100";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&pinctrl_codec2>;
 379                 reg = <0x18>;
 380                 #sound-dai-cells = <0>;
 381                 HPVDD-supply = <&reg_3p3v>;
 382                 SPRVDD-supply = <&reg_3p3v>;
 383                 SPLVDD-supply = <&reg_3p3v>;
 384                 AVDD-supply = <&reg_3p3v>;
 385                 IOVDD-supply = <&reg_3p3v>;
 386                 DVDD-supply = <&vgen4_reg>;
 387                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 388         };
 389
 390         accel@1c {
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&pinctrl_accel>;
 393                 compatible = "fsl,mma8451";
 394                 reg = <0x1c>;
 395                 interrupt-parent = <&gpio1>;
 396                 interrupt-names = "int1", "int2";
 397                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 398         };
 399
 400         hpa2: amp@60 {
 401                 compatible = "ti,tpa6130a2";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&pinctrl_tpa2>;
 404                 reg = <0x60>;
 405                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 406                 Vdd-supply = <&reg_5p0v_main>;
 407         };
 408
 409         edp-bridge@68 {
 410                 compatible = "toshiba,tc358767";
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&pinctrl_tc358767>;
 413                 reg = <0x68>;
 414                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 415                 clock-names = "ref";
 416                 clocks = <&edp_refclk>;
 417                 status = "disabled";
 418
 419                 ports {
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422
 423                         port@1 {
 424                                 reg = <1>;
 425
 426                                 tc358767_in: endpoint {
 427                                         remote-endpoint = <&disp0_out>;
 428                                 };
 429                         };
 430                 };
 431         };
 432 };
 433
 434 &i2c2 {
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&pinctrl_i2c2>;
 437         clock-frequency = <100000>;
 438         status = "okay";
 439
 440         pmic@8 {
 441                 compatible = "fsl,pfuze100";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 444                 reg = <0x08>;
 445                 interrupt-parent = <&gpio7>;
 446                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 447
 448                 regulators {
 449                         sw1a_reg: sw1ab {
 450                                 regulator-min-microvolt = <300000>;
 451                                 regulator-max-microvolt = <1875000>;
 452                                 regulator-boot-on;
 453                                 regulator-always-on;
 454                                 regulator-ramp-delay = <6250>;
 455                         };
 456
 457                         sw1c_reg: sw1c {
 458                                 regulator-min-microvolt = <300000>;
 459                                 regulator-max-microvolt = <1875000>;
 460                                 regulator-boot-on;
 461                                 regulator-always-on;
 462                                 regulator-ramp-delay = <6250>;
 463                         };
 464
 465                         sw2_reg: sw2 {
 466                                 regulator-min-microvolt = <800000>;
 467                                 regulator-max-microvolt = <3000000>;
 468                                 regulator-boot-on;
 469                                 regulator-always-on;
 470                         };
 471
 472                         sw3a_reg: sw3a {
 473                                 regulator-min-microvolt = <400000>;
 474                                 regulator-max-microvolt = <1500000>;
 475                                 regulator-boot-on;
 476                                 regulator-always-on;
 477                         };
 478
 479                         sw3b_reg: sw3b {
 480                                 regulator-min-microvolt = <400000>;
 481                                 regulator-max-microvolt = <1500000>;
 482                                 regulator-boot-on;
 483                                 regulator-always-on;
 484                         };
 485
 486                         sw4_reg: sw4 {
 487                                 regulator-min-microvolt = <800000>;
 488                                 regulator-max-microvolt = <1800000>;
 489                                 regulator-boot-on;
 490                                 regulator-always-on;
 491                         };
 492
 493                         snvs_reg: vsnvs {
 494                                 regulator-min-microvolt = <1000000>;
 495                                 regulator-max-microvolt = <3000000>;
 496                                 regulator-boot-on;
 497                                 regulator-always-on;
 498                         };
 499
 500                         vref_reg: vrefddr {
 501                                 regulator-boot-on;
 502                                 regulator-always-on;
 503                         };
 504
 505                         vgen2_reg: vgen2 {
 506                                 regulator-min-microvolt = <1000000>;
 507                                 regulator-max-microvolt = <1500000>;
 508                                 regulator-always-on;
 509                         };
 510
 511                         vgen4_reg: vgen4 {
 512                                 regulator-min-microvolt = <1200000>;
 513                                 regulator-max-microvolt = <1800000>;
 514                                 regulator-always-on;
 515                         };
 516
 517                         vgen5_reg: vgen5 {
 518                                 regulator-min-microvolt = <1800000>;
 519                                 regulator-max-microvolt = <2500000>;
 520                                 regulator-always-on;
 521                         };
 522
 523                         vgen6_reg: vgen6 {
 524                                 regulator-min-microvolt = <1800000>;
 525                                 regulator-max-microvolt = <2800000>;
 526                                 regulator-always-on;
 527                         };
 528                 };
 529         };
 530
 531         temp-sense@48 {
 532                 compatible = "national,lm75";
 533                 reg = <0x48>;
 534         };
 535
 536         cs2000: clkgen@4e {
 537                 compatible = "cirrus,cs2000-cp";
 538                 reg = <0x4e>;
 539                 #clock-cells = <0>;
 540                 clock-names = "clk_in", "ref_clk";
 541                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 542                 assigned-clocks = <&cs2000>;
 543                 assigned-clock-rates = <24000000>;
 544         };
 545
 546         eeprom@54 {
 547                 compatible = "atmel,24c128";
 548                 reg = <0x54>;
 549         };
 550
 551         ds1341: rtc@68 {
 552                 compatible = "dallas,ds1341";
 553                 reg = <0x68>;
 554         };
 555 };
 556
 557 &i2c3 {
 558         pinctrl-names = "default";
 559         pinctrl-0 = <&pinctrl_i2c3>;
 560         clock-frequency = <400000>;
 561         status = "okay";
 562
 563         codec1: codec@18 {
 564                 compatible = "ti,tlv320dac3100";
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&pinctrl_codec1>;
 567                 reg = <0x18>;
 568                 #sound-dai-cells = <0>;
 569                 HPVDD-supply = <&reg_3p3v>;
 570                 SPRVDD-supply = <&reg_3p3v>;
 571                 SPLVDD-supply = <&reg_3p3v>;
 572                 AVDD-supply = <&reg_3p3v>;
 573                 IOVDD-supply = <&reg_3p3v>;
 574                 DVDD-supply = <&vgen4_reg>;
 575                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 576         };
 577
 578         touchscreen@20 {
 579                 compatible = "syna,rmi4-i2c";
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pinctrl_ts>;
 582                 reg = <0x20>;
 583                 interrupt-parent = <&gpio1>;
 584                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 585                 vdd-supply = <&reg_5p0v_main>;
 586                 vio-supply = <&reg_3p3v>;
 587
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590
 591                 rmi4-f01@1 {
 592                         reg = <0x1>;
 593                         syna,nosleep-mode = <2>;
 594                 };
 595
 596                 rmi4-f11@11 {
 597                         reg = <0x11>;
 598                         touchscreen-inverted-x;
 599                         touchscreen-swapped-x-y;
 600                         syna,sensor-type = <1>;
 601                 };
 602
 603                 rmi4-f12@12 {
 604                         reg = <0x12>;
 605                         touchscreen-inverted-x;
 606                         touchscreen-swapped-x-y;
 607                         syna,sensor-type = <1>;
 608                 };
 609         };
 610
 611         touchscreen@2a {
 612                 compatible = "eeti,egalax_ts";
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&pinctrl_ts>;
 615                 reg = <0x2a>;
 616                 interrupt-parent = <&gpio1>;
 617                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 618                 wakeup-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 619                 status = "disabled";
 620         };
 621
 622         hpa1: amp@60 {
 623                 compatible = "ti,tpa6130a2";
 624                 pinctrl-names = "default";
 625                 pinctrl-0 = <&pinctrl_tpa1>;
 626                 reg = <0x60>;
 627                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 628                 Vdd-supply = <&reg_5p0v_main>;
 629         };
 630 };
 631
 632 &ipu1_di0_disp0 {
 633         remote-endpoint = <&disp0_in_0>;
 634 };
 635
 636 &pcie {
 637         pinctrl-names = "default";
 638         pinctrl-0 = <&pinctrl_pcie>;
 639         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 640         status = "okay";
 641
 642         host@0 {
 643                 reg = <0 0 0 0 0>;
 644
 645                 #address-cells = <3>;
 646                 #size-cells = <2>;
 647
 648                 i210: i210@0 {
 649                         reg = <0 0 0 0 0>;
 650                 };
 651         };
 652 };
 653
 654 &usdhc2 {
 655         pinctrl-names = "default";
 656         pinctrl-0 = <&pinctrl_usdhc2>;
 657         bus-width = <4>;
 658         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 659         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 660         vmmc-supply = <&reg_3p3v_sd>;
 661         vqmmc-supply = <&reg_3p3v>;
 662         no-1-8-v;
 663         no-sdio;
 664         status = "okay";
 665 };
 666
 667 &usdhc3 {
 668         pinctrl-names = "default";
 669         pinctrl-0 = <&pinctrl_usdhc3>;
 670         bus-width = <4>;
 671         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 672         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 673         vmmc-supply = <&reg_3p3v_sd>;
 674         vqmmc-supply = <&reg_3p3v>;
 675         no-1-8-v;
 676         no-sdio;
 677         status = "okay";
 678 };
 679
 680 &usdhc4 {
 681         pinctrl-names = "default";
 682         pinctrl-0 = <&pinctrl_usdhc4>;
 683         bus-width = <8>;
 684         vmmc-supply = <&reg_3p3v>;
 685         vqmmc-supply = <&reg_3p3v>;
 686         no-1-8-v;
 687         non-removable;
 688         no-sdio;
 689         no-sd;
 690         status = "okay";
 691 };
 692
 693 &sata {
 694         target-supply = <&reg_3p3v_ssd>;
 695         status = "okay";
 696 };
 697
 698 &fec {
 699         pinctrl-names = "default";
 700         pinctrl-0 = <&pinctrl_enet>;
 701         phy-mode = "rmii";
 702         phy-handle = <&phy>;
 703         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 704         phy-reset-duration = <100>;
 705         phy-supply = <&reg_3p3v>;
 706         status = "okay";
 707
 708         mdio {
 709                 #address-cells = <1>;
 710                 #size-cells = <0>;
 711                 status = "okay";
 712
 713                 switch: switch@0 {
 714                         compatible = "marvell,mv88e6085";
 715                         pinctrl-0 = <&pinctrl_switch_irq>;
 716                         pinctrl-names = "default";
 717                         reg = <0>;
 718                         dsa,member = <0 0>;
 719                         eeprom-length = <512>;
 720                         interrupt-parent = <&gpio6>;
 721                         interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 722                         interrupt-controller;
 723                         #interrupt-cells = <2>;
 724
 725                         ports {
 726                                 #address-cells = <1>;
 727                                 #size-cells = <0>;
 728
 729                                 port@0 {
 730                                         reg = <0>;
 731                                         label = "gigabit_proc";
 732                                         phy-handle = <&switchphy0>;
 733                                 };
 734
 735                                 port@1 {
 736                                         reg = <1>;
 737                                         label = "netaux";
 738                                         phy-handle = <&switchphy1>;
 739                                 };
 740
 741                                 port@2 {
 742                                         reg = <2>;
 743                                         label = "cpu";
 744                                         ethernet = <&fec>;
 745
 746                                         fixed-link {
 747                                                 speed = <100>;
 748                                                 full-duplex;
 749                                         };
 750                                 };
 751
 752                                 port@3 {
 753                                         reg = <3>;
 754                                         label = "netright";
 755                                         phy-handle = <&switchphy3>;
 756                                 };
 757
 758                                 port@4 {
 759                                         reg = <4>;
 760                                         label = "netleft";
 761                                         phy-handle = <&switchphy4>;
 762                                 };
 763                         };
 764
 765                         mdio {
 766                                 #address-cells = <1>;
 767                                 #size-cells = <0>;
 768
 769                                 switchphy0: switchphy@0 {
 770                                         reg = <0>;
 771                                         interrupt-parent = <&switch>;
 772                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 773                                 };
 774
 775                                 switchphy1: switchphy@1 {
 776                                         reg = <1>;
 777                                         interrupt-parent = <&switch>;
 778                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 779                                 };
 780
 781                                 switchphy2: switchphy@2 {
 782                                         reg = <2>;
 783                                         interrupt-parent = <&switch>;
 784                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 785                                 };
 786
 787                                 switchphy3: switchphy@3 {
 788                                         reg = <3>;
 789                                         interrupt-parent = <&switch>;
 790                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 791                                 };
 792
 793                                 switchphy4: switchphy@4 {
 794                                         reg = <4>;
 795                                         interrupt-parent = <&switch>;
 796                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 797                                 };
 798                         };
 799                 };
 800         };
 801 };
 802
 803 &usbh1 {
 804         vbus-supply = <&reg_5p0v_main>;
 805         disable-over-current;
 806         status = "okay";
 807 };
 808
 809 &usbotg {
 810         vbus-supply = <&reg_5p0v_user_usb>;
 811         disable-over-current;
 812         dr_mode = "host";
 813         status = "okay";
 814 };
 815
 816 &ssi1 {
 817         status = "okay";
 818 };
 819
 820 &ssi2 {
 821         status = "okay";
 822 };
 823
 824 &audmux {
 825         pinctrl-names = "default";
 826         pinctrl-0 = <&pinctrl_audmux>;
 827         status = "okay";
 828
 829         ssi1 {
 830                 fsl,audmux-port = <0>;
 831                 fsl,port-config = <
 832                         (IMX_AUDMUX_V2_PTCR_SYN |
 833                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 834                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 835                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 836                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 837                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 838                 >;
 839         };
 840
 841         aud3 {
 842                 fsl,audmux-port = <2>;
 843                 fsl,port-config = <
 844                         IMX_AUDMUX_V2_PTCR_SYN
 845                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 846                 >;
 847         };
 848
 849         ssi2 {
 850                 fsl,audmux-port = <1>;
 851                 fsl,port-config = <
 852                         (IMX_AUDMUX_V2_PTCR_SYN |
 853                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 854                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 855                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 856                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 857                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 858                 >;
 859         };
 860
 861         aud5 {
 862                 fsl,audmux-port = <4>;
 863                 fsl,port-config = <
 864                         IMX_AUDMUX_V2_PTCR_SYN
 865                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 866                 >;
 867         };
 868 };
 869
 870 &wdog1 {
 871         status = "disabled";
 872 };
 873
 874 &iomuxc {
 875         pinctrl_accel: accelgrp {
 876                 fsl,pins = <
 877                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 878                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 879                 >;
 880         };
 881
 882         pinctrl_audmux: audmuxgrp {
 883                 fsl,pins = <
 884                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 885                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 886                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 887                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 888                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 889                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 890                 >;
 891         };
 892
 893         pinctrl_codec1: dac1grp {
 894                 fsl,pins = <
 895                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 896                 >;
 897         };
 898
 899         pinctrl_codec2: dac2grp {
 900                 fsl,pins = <
 901                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 902                 >;
 903         };
 904
 905         pinctrl_disp0: disp0grp {
 906                 fsl,pins = <
 907                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 908                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 909                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 910                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 911                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 912                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 913                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 914                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 915                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 916                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 917                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 918                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 919                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 920                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 921                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 922                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 923                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 924                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 925                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 926                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 927                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 928                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 929                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 930                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 931                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 932                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 933                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 934                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 935                 >;
 936         };
 937
 938         pinctrl_ecspi1: ecspi1grp {
 939                 fsl,pins = <
 940                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 941                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 942                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 943                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 944                 >;
 945         };
 946
 947         pinctrl_enet: enetgrp {
 948                 fsl,pins = <
 949                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 950                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 951                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 952                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 953                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 954                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 955                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 956                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 957                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 958                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 959                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 960                 >;
 961         };
 962
 963         pinctrl_i2c1: i2c1grp {
 964                 fsl,pins = <
 965                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 966                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 967                 >;
 968         };
 969
 970         pinctrl_i2c2: i2c2grp {
 971                 fsl,pins = <
 972                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 973                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 974                 >;
 975         };
 976
 977         pinctrl_i2c3: i2c3grp {
 978                 fsl,pins = <
 979                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 980                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 981                 >;
 982         };
 983
 984         pinctrl_mdio1: bitbangmdiogrp {
 985                 fsl,pins = <
 986                         /* Bitbang MDIO for DEB Switch */
 987                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 988                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 989                 >;
 990         };
 991
 992         pinctrl_pcie: pciegrp {
 993                 fsl,pins = <
 994                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 995                 >;
 996         };
 997
 998         pinctrl_pfuze100_irq: pfuze100grp {
 999                 fsl,pins = <
1000                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
1001                 >;
1002         };
1003
1004         pinctrl_reg_3p3v_sd: mmcsupply1grp {
1005                 fsl,pins = <
1006                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
1007                 >;
1008         };
1009
1010         pinctrl_reg_user_usb: usbotggrp {
1011                 fsl,pins = <
1012                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
1013                 >;
1014         };
1015
1016         pinctrl_rmii_phy_irq: phygrp {
1017                 fsl,pins = <
1018                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
1019                 >;
1020         };
1021
1022         pinctrl_switch_irq: switchgrp {
1023                 fsl,pins = <
1024                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
1025                 >;
1026         };
1027
1028         pinctrl_tc358767: tc358767grp {
1029                 fsl,pins = <
1030                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
1031                 >;
1032         };
1033
1034         pinctrl_tpa1: tpa6130-1grp {
1035                 fsl,pins = <
1036                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
1037                 >;
1038         };
1039
1040         pinctrl_tpa2: tpa6130-2grp {
1041                 fsl,pins = <
1042                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
1043                 >;
1044         };
1045
1046         pinctrl_ts: tsgrp {
1047                 fsl,pins = <
1048                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1049                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1050                 >;
1051         };
1052
1053         pinctrl_uart1: uart1grp {
1054                 fsl,pins = <
1055                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1056                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1057                 >;
1058         };
1059
1060         pinctrl_uart3: uart3grp {
1061                 fsl,pins = <
1062                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1063                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1064                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1065                 >;
1066         };
1067
1068         pinctrl_uart4: uart4grp {
1069                 fsl,pins = <
1070                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1071                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1072                 >;
1073         };
1074
1075         pinctrl_usdhc2: usdhc2grp {
1076                 fsl,pins = <
1077                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1078                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1079                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1080                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1081                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1082                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1083                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1084                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1085                 >;
1086         };
1087
1088         pinctrl_usdhc3: usdhc3grp {
1089                 fsl,pins = <
1090                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1091                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1092                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1093                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1094                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1095                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1096                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1097                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1098
1099                 >;
1100         };
1101
1102         pinctrl_usdhc4: usdhc4grp {
1103                 fsl,pins = <
1104                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1105                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1106                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1107                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1108                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1109                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1110                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1111                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1112                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1113                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1114                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1115                 >;
1116         };
1117 };