1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&gic>;
29 compatible = "arm,cortex-a7";
31 resets = <&cru SRST_CORE0>;
32 operating-points-v2 = <&cpu0_opp_table>;
33 #cooling-cells = <2>; /* min followed by max */
34 clock-latency = <40000>;
35 clocks = <&cru ARMCLK>;
36 enable-method = "psci";
41 compatible = "arm,cortex-a7";
43 resets = <&cru SRST_CORE1>;
44 operating-points-v2 = <&cpu0_opp_table>;
45 #cooling-cells = <2>; /* min followed by max */
46 enable-method = "psci";
51 compatible = "arm,cortex-a7";
53 resets = <&cru SRST_CORE2>;
54 operating-points-v2 = <&cpu0_opp_table>;
55 #cooling-cells = <2>; /* min followed by max */
56 enable-method = "psci";
61 compatible = "arm,cortex-a7";
63 resets = <&cru SRST_CORE3>;
64 operating-points-v2 = <&cpu0_opp_table>;
65 #cooling-cells = <2>; /* min followed by max */
66 enable-method = "psci";
70 cpu0_opp_table: opp_table0 {
71 compatible = "operating-points-v2";
75 opp-hz = /bits/ 64 <408000000>;
76 opp-microvolt = <950000>;
77 clock-latency-ns = <40000>;
81 opp-hz = /bits/ 64 <600000000>;
82 opp-microvolt = <975000>;
85 opp-hz = /bits/ 64 <816000000>;
86 opp-microvolt = <1000000>;
89 opp-hz = /bits/ 64 <1008000000>;
90 opp-microvolt = <1175000>;
93 opp-hz = /bits/ 64 <1200000000>;
94 opp-microvolt = <1275000>;
99 compatible = "simple-bus";
100 #address-cells = <1>;
104 pdma: pdma@110f0000 {
105 compatible = "arm,pl330", "arm,primecell";
106 reg = <0x110f0000 0x4000>;
107 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru ACLK_DMAC>;
111 clock-names = "apb_pclk";
116 compatible = "arm,cortex-a7-pmu";
117 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
120 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
121 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2";
130 compatible = "arm,armv7-timer";
131 arm,cpu-registers-not-fw-configured;
132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
136 clock-frequency = <24000000>;
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-output-names = "xin24m";
146 display_subsystem: display-subsystem {
147 compatible = "rockchip,display-subsystem";
151 i2s1: i2s1@100b0000 {
152 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
153 reg = <0x100b0000 0x4000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 clock-names = "i2s_clk", "i2s_hclk";
156 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
157 dmas = <&pdma 14>, <&pdma 15>;
158 dma-names = "tx", "rx";
159 pinctrl-names = "default";
160 pinctrl-0 = <&i2s1_bus>;
164 i2s0: i2s0@100c0000 {
165 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
166 reg = <0x100c0000 0x4000>;
167 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
168 clock-names = "i2s_clk", "i2s_hclk";
169 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
170 dmas = <&pdma 11>, <&pdma 12>;
171 dma-names = "tx", "rx";
175 spdif: spdif@100d0000 {
176 compatible = "rockchip,rk3228-spdif";
177 reg = <0x100d0000 0x1000>;
178 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
180 clock-names = "mclk", "hclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&spdif_tx>;
188 i2s2: i2s2@100e0000 {
189 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
190 reg = <0x100e0000 0x4000>;
191 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
192 clock-names = "i2s_clk", "i2s_hclk";
193 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
194 dmas = <&pdma 0>, <&pdma 1>;
195 dma-names = "tx", "rx";
199 grf: syscon@11000000 {
200 compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd";
201 reg = <0x11000000 0x1000>;
202 #address-cells = <1>;
205 io_domains: io-domains {
206 compatible = "rockchip,rk3228-io-voltage-domain";
210 u2phy0: usb2-phy@760 {
211 compatible = "rockchip,rk3228-usb2phy";
213 clocks = <&cru SCLK_OTGPHY0>;
214 clock-names = "phyclk";
215 clock-output-names = "usb480m_phy0";
219 u2phy0_otg: otg-port {
220 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
223 interrupt-names = "otg-bvalid", "otg-id",
229 u2phy0_host: host-port {
230 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
231 interrupt-names = "linestate";
237 u2phy1: usb2-phy@800 {
238 compatible = "rockchip,rk3228-usb2phy";
240 clocks = <&cru SCLK_OTGPHY1>;
241 clock-names = "phyclk";
242 clock-output-names = "usb480m_phy1";
246 u2phy1_otg: otg-port {
247 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
248 interrupt-names = "linestate";
253 u2phy1_host: host-port {
254 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
255 interrupt-names = "linestate";
262 uart0: serial@11010000 {
263 compatible = "snps,dw-apb-uart";
264 reg = <0x11010000 0x100>;
265 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
266 clock-frequency = <24000000>;
267 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
268 clock-names = "baudclk", "apb_pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
276 uart1: serial@11020000 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x11020000 0x100>;
279 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
280 clock-frequency = <24000000>;
281 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
282 clock-names = "baudclk", "apb_pclk";
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart1_xfer>;
290 uart2: serial@11030000 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x11030000 0x100>;
293 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
294 clock-frequency = <24000000>;
295 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
296 clock-names = "baudclk", "apb_pclk";
297 pinctrl-names = "default";
298 pinctrl-0 = <&uart2_xfer>;
304 efuse: efuse@11040000 {
305 compatible = "rockchip,rk3228-efuse";
306 reg = <0x11040000 0x20>;
307 clocks = <&cru PCLK_EFUSE_256>;
308 clock-names = "pclk_efuse";
309 #address-cells = <1>;
316 cpu_leakage: cpu_leakage@17 {
322 compatible = "rockchip,rk3228-i2c";
323 reg = <0x11050000 0x1000>;
324 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
328 clocks = <&cru PCLK_I2C0>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c0_xfer>;
335 compatible = "rockchip,rk3228-i2c";
336 reg = <0x11060000 0x1000>;
337 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
341 clocks = <&cru PCLK_I2C1>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c1_xfer>;
348 compatible = "rockchip,rk3228-i2c";
349 reg = <0x11070000 0x1000>;
350 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
354 clocks = <&cru PCLK_I2C2>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c2_xfer>;
361 compatible = "rockchip,rk3228-i2c";
362 reg = <0x11080000 0x1000>;
363 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
367 clocks = <&cru PCLK_I2C3>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c3_xfer>;
374 compatible = "rockchip,rk3228-spi";
375 reg = <0x11090000 0x1000>;
376 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
377 #address-cells = <1>;
379 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
380 clock-names = "spiclk", "apb_pclk";
381 pinctrl-names = "default";
382 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
386 wdt: watchdog@110a0000 {
387 compatible = "snps,dw-wdt";
388 reg = <0x110a0000 0x100>;
389 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru PCLK_CPU>;
395 compatible = "rockchip,rk3288-pwm";
396 reg = <0x110b0000 0x10>;
398 clocks = <&cru PCLK_PWM>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pwm0_pin>;
406 compatible = "rockchip,rk3288-pwm";
407 reg = <0x110b0010 0x10>;
409 clocks = <&cru PCLK_PWM>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm1_pin>;
417 compatible = "rockchip,rk3288-pwm";
418 reg = <0x110b0020 0x10>;
420 clocks = <&cru PCLK_PWM>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&pwm2_pin>;
428 compatible = "rockchip,rk3288-pwm";
429 reg = <0x110b0030 0x10>;
431 clocks = <&cru PCLK_PWM>;
433 pinctrl-names = "default";
434 pinctrl-0 = <&pwm3_pin>;
438 timer: timer@110c0000 {
439 compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
440 reg = <0x110c0000 0x20>;
441 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&xin24m>, <&cru PCLK_TIMER>;
443 clock-names = "timer", "pclk";
446 cru: clock-controller@110e0000 {
447 compatible = "rockchip,rk3228-cru";
448 reg = <0x110e0000 0x1000>;
449 rockchip,grf = <&grf>;
453 <&cru PLL_GPLL>, <&cru ARMCLK>,
454 <&cru PLL_CPLL>, <&cru ACLK_PERI>,
455 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
456 <&cru ACLK_CPU>, <&cru HCLK_CPU>,
458 assigned-clock-rates =
459 <594000000>, <816000000>,
460 <500000000>, <150000000>,
461 <150000000>, <75000000>,
462 <150000000>, <150000000>,
467 cpu_thermal: cpu-thermal {
468 polling-delay-passive = <100>; /* milliseconds */
469 polling-delay = <5000>; /* milliseconds */
471 thermal-sensors = <&tsadc 0>;
474 cpu_alert0: cpu_alert0 {
475 temperature = <70000>; /* millicelsius */
476 hysteresis = <2000>; /* millicelsius */
479 cpu_alert1: cpu_alert1 {
480 temperature = <75000>; /* millicelsius */
481 hysteresis = <2000>; /* millicelsius */
485 temperature = <90000>; /* millicelsius */
486 hysteresis = <2000>; /* millicelsius */
493 trip = <&cpu_alert0>;
495 <&cpu0 THERMAL_NO_LIMIT 6>,
496 <&cpu1 THERMAL_NO_LIMIT 6>,
497 <&cpu2 THERMAL_NO_LIMIT 6>,
498 <&cpu3 THERMAL_NO_LIMIT 6>;
501 trip = <&cpu_alert1>;
503 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
504 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
505 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
506 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
512 tsadc: tsadc@11150000 {
513 compatible = "rockchip,rk3228-tsadc";
514 reg = <0x11150000 0x100>;
515 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
517 clock-names = "tsadc", "apb_pclk";
518 assigned-clocks = <&cru SCLK_TSADC>;
519 assigned-clock-rates = <32768>;
520 resets = <&cru SRST_TSADC>;
521 reset-names = "tsadc-apb";
522 pinctrl-names = "init", "default", "sleep";
523 pinctrl-0 = <&otp_gpio>;
524 pinctrl-1 = <&otp_out>;
525 pinctrl-2 = <&otp_gpio>;
526 #thermal-sensor-cells = <0>;
527 rockchip,hw-tshut-temp = <95000>;
531 hdmi_phy: hdmi-phy@12030000 {
532 compatible = "rockchip,rk3228-hdmi-phy";
533 reg = <0x12030000 0x10000>;
534 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
535 clock-names = "sysclk", "refoclk", "refpclk";
537 clock-output-names = "hdmiphy_phy";
543 compatible = "rockchip,rk3228-mali", "arm,mali-400";
544 reg = <0x20000000 0x10000>;
545 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-names = "gp",
557 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
558 clock-names = "bus", "core";
559 resets = <&cru SRST_GPU_A>;
563 vpu_mmu: iommu@20020800 {
564 compatible = "rockchip,iommu";
565 reg = <0x20020800 0x100>;
566 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
567 interrupt-names = "vpu_mmu";
568 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
569 clock-names = "aclk", "iface";
574 vdec_mmu: iommu@20030480 {
575 compatible = "rockchip,iommu";
576 reg = <0x20030480 0x40>, <0x200304c0 0x40>;
577 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
578 interrupt-names = "vdec_mmu";
579 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
580 clock-names = "aclk", "iface";
586 compatible = "rockchip,rk3228-vop";
587 reg = <0x20050000 0x1ffc>;
588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
590 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
591 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
592 reset-names = "axi", "ahb", "dclk";
597 #address-cells = <1>;
600 vop_out_hdmi: endpoint@0 {
602 remote-endpoint = <&hdmi_in_vop>;
607 vop_mmu: iommu@20053f00 {
608 compatible = "rockchip,iommu";
609 reg = <0x20053f00 0x100>;
610 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
611 interrupt-names = "vop_mmu";
612 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
613 clock-names = "aclk", "iface";
619 compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga";
620 reg = <0x20060000 0x1000>;
621 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
623 clock-names = "aclk", "hclk", "sclk";
624 resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
625 reset-names = "core", "axi", "ahb";
628 iep_mmu: iommu@20070800 {
629 compatible = "rockchip,iommu";
630 reg = <0x20070800 0x100>;
631 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
632 interrupt-names = "iep_mmu";
633 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
634 clock-names = "aclk", "iface";
639 hdmi: hdmi@200a0000 {
640 compatible = "rockchip,rk3228-dw-hdmi";
641 reg = <0x200a0000 0x20000>;
643 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
644 assigned-clocks = <&cru SCLK_HDMI_PHY>;
645 assigned-clock-parents = <&hdmi_phy>;
646 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>;
647 clock-names = "isfr", "iahb", "cec";
648 pinctrl-names = "default";
649 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
650 resets = <&cru SRST_HDMI_P>;
651 reset-names = "hdmi";
654 rockchip,grf = <&grf>;
659 #address-cells = <1>;
661 hdmi_in_vop: endpoint@0 {
663 remote-endpoint = <&vop_out_hdmi>;
669 sdmmc: mmc@30000000 {
670 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
671 reg = <0x30000000 0x4000>;
672 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
674 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
675 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
676 fifo-depth = <0x100>;
677 pinctrl-names = "default";
678 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
683 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
684 reg = <0x30010000 0x4000>;
685 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
687 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
688 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
689 fifo-depth = <0x100>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
696 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
697 reg = <0x30020000 0x4000>;
698 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
699 clock-frequency = <37500000>;
700 max-frequency = <37500000>;
701 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
702 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
703 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
705 rockchip,default-sample-phase = <158>;
706 fifo-depth = <0x100>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
709 resets = <&cru SRST_EMMC>;
710 reset-names = "reset";
714 usb_otg: usb@30040000 {
715 compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb",
717 reg = <0x30040000 0x40000>;
718 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&cru HCLK_OTG>;
722 g-np-tx-fifo-size = <16>;
723 g-rx-fifo-size = <280>;
724 g-tx-fifo-size = <256 128 128 64 32 16>;
725 phys = <&u2phy0_otg>;
726 phy-names = "usb2-phy";
730 usb_host0_ehci: usb@30080000 {
731 compatible = "generic-ehci";
732 reg = <0x30080000 0x20000>;
733 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
735 phys = <&u2phy0_host>;
740 usb_host0_ohci: usb@300a0000 {
741 compatible = "generic-ohci";
742 reg = <0x300a0000 0x20000>;
743 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
745 phys = <&u2phy0_host>;
750 usb_host1_ehci: usb@300c0000 {
751 compatible = "generic-ehci";
752 reg = <0x300c0000 0x20000>;
753 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
755 phys = <&u2phy1_otg>;
760 usb_host1_ohci: usb@300e0000 {
761 compatible = "generic-ohci";
762 reg = <0x300e0000 0x20000>;
763 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
765 phys = <&u2phy1_otg>;
770 usb_host2_ehci: usb@30100000 {
771 compatible = "generic-ehci";
772 reg = <0x30100000 0x20000>;
773 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
775 phys = <&u2phy1_host>;
780 usb_host2_ohci: usb@30120000 {
781 compatible = "generic-ohci";
782 reg = <0x30120000 0x20000>;
783 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
785 phys = <&u2phy1_host>;
790 gmac: ethernet@30200000 {
791 compatible = "rockchip,rk3228-gmac";
792 reg = <0x30200000 0x10000>;
793 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "macirq";
795 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
796 <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
797 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
799 clock-names = "stmmaceth", "mac_clk_rx",
800 "mac_clk_tx", "clk_mac_ref",
801 "clk_mac_refout", "aclk_mac",
803 resets = <&cru SRST_GMAC>;
804 reset-names = "stmmaceth";
805 rockchip,grf = <&grf>;
809 gic: interrupt-controller@32010000 {
810 compatible = "arm,gic-400";
811 interrupt-controller;
812 #interrupt-cells = <3>;
813 #address-cells = <0>;
815 reg = <0x32011000 0x1000>,
819 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
823 compatible = "rockchip,rk3228-pinctrl";
824 rockchip,grf = <&grf>;
825 #address-cells = <1>;
829 gpio0: gpio0@11110000 {
830 compatible = "rockchip,gpio-bank";
831 reg = <0x11110000 0x100>;
832 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&cru PCLK_GPIO0>;
838 interrupt-controller;
839 #interrupt-cells = <2>;
842 gpio1: gpio1@11120000 {
843 compatible = "rockchip,gpio-bank";
844 reg = <0x11120000 0x100>;
845 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
846 clocks = <&cru PCLK_GPIO1>;
851 interrupt-controller;
852 #interrupt-cells = <2>;
855 gpio2: gpio2@11130000 {
856 compatible = "rockchip,gpio-bank";
857 reg = <0x11130000 0x100>;
858 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&cru PCLK_GPIO2>;
864 interrupt-controller;
865 #interrupt-cells = <2>;
868 gpio3: gpio3@11140000 {
869 compatible = "rockchip,gpio-bank";
870 reg = <0x11140000 0x100>;
871 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&cru PCLK_GPIO3>;
877 interrupt-controller;
878 #interrupt-cells = <2>;
881 pcfg_pull_up: pcfg-pull-up {
885 pcfg_pull_down: pcfg-pull-down {
889 pcfg_pull_none: pcfg-pull-none {
893 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
894 drive-strength = <12>;
898 sdmmc_clk: sdmmc-clk {
899 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>;
902 sdmmc_cmd: sdmmc-cmd {
903 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>;
906 sdmmc_bus4: sdmmc-bus4 {
907 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
908 <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
909 <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>,
910 <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>;
916 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>;
920 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>;
923 sdio_bus4: sdio-bus4 {
924 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>,
925 <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>,
926 <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>,
927 <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>;
933 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
937 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>;
940 emmc_bus8: emmc-bus8 {
941 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>,
942 <1 RK_PD1 2 &pcfg_pull_none>,
943 <1 RK_PD2 2 &pcfg_pull_none>,
944 <1 RK_PD3 2 &pcfg_pull_none>,
945 <1 RK_PD4 2 &pcfg_pull_none>,
946 <1 RK_PD5 2 &pcfg_pull_none>,
947 <1 RK_PD6 2 &pcfg_pull_none>,
948 <1 RK_PD7 2 &pcfg_pull_none>;
953 rgmii_pins: rgmii-pins {
954 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
955 <2 RK_PB4 1 &pcfg_pull_none>,
956 <2 RK_PD1 1 &pcfg_pull_none>,
957 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
958 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
959 <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>,
960 <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>,
961 <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>,
962 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
963 <2 RK_PC1 1 &pcfg_pull_none>,
964 <2 RK_PC0 1 &pcfg_pull_none>,
965 <2 RK_PC5 2 &pcfg_pull_none>,
966 <2 RK_PC4 2 &pcfg_pull_none>,
967 <2 RK_PB3 1 &pcfg_pull_none>,
968 <2 RK_PB0 1 &pcfg_pull_none>;
971 rmii_pins: rmii-pins {
972 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>,
973 <2 RK_PB4 1 &pcfg_pull_none>,
974 <2 RK_PD1 1 &pcfg_pull_none>,
975 <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>,
976 <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>,
977 <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>,
978 <2 RK_PC1 1 &pcfg_pull_none>,
979 <2 RK_PC0 1 &pcfg_pull_none>,
980 <2 RK_PB0 1 &pcfg_pull_none>,
981 <2 RK_PB7 1 &pcfg_pull_none>;
985 rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>,
986 <2 RK_PB0 2 &pcfg_pull_none>;
992 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>;
995 hdmii2c_xfer: hdmii2c-xfer {
996 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
997 <0 RK_PA7 2 &pcfg_pull_none>;
1000 hdmi_cec: hdmi-cec {
1001 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
1006 i2c0_xfer: i2c0-xfer {
1007 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
1008 <0 RK_PA1 1 &pcfg_pull_none>;
1013 i2c1_xfer: i2c1-xfer {
1014 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
1015 <0 RK_PA3 1 &pcfg_pull_none>;
1020 i2c2_xfer: i2c2-xfer {
1021 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
1022 <2 RK_PC5 1 &pcfg_pull_none>;
1027 i2c3_xfer: i2c3-xfer {
1028 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1029 <0 RK_PA7 1 &pcfg_pull_none>;
1034 spi0_clk: spi0-clk {
1035 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>;
1037 spi0_cs0: spi0-cs0 {
1038 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>;
1041 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1044 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1046 spi0_cs1: spi0-cs1 {
1047 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>;
1052 spi1_clk: spi1-clk {
1053 rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>;
1055 spi1_cs0: spi1-cs0 {
1056 rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>;
1059 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>;
1062 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>;
1064 spi1_cs1: spi1-cs1 {
1065 rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>;
1070 i2s1_bus: i2s1-bus {
1071 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
1072 <0 RK_PB1 1 &pcfg_pull_none>,
1073 <0 RK_PB3 1 &pcfg_pull_none>,
1074 <0 RK_PB4 1 &pcfg_pull_none>,
1075 <0 RK_PB5 1 &pcfg_pull_none>,
1076 <0 RK_PB6 1 &pcfg_pull_none>,
1077 <1 RK_PA2 2 &pcfg_pull_none>,
1078 <1 RK_PA4 2 &pcfg_pull_none>,
1079 <1 RK_PA5 2 &pcfg_pull_none>;
1084 pwm0_pin: pwm0-pin {
1085 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>;
1090 pwm1_pin: pwm1-pin {
1091 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1096 pwm2_pin: pwm2-pin {
1097 rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>;
1102 pwm3_pin: pwm3-pin {
1103 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1108 spdif_tx: spdif-tx {
1109 rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>;
1114 otp_gpio: otp-gpio {
1115 rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
1119 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>;
1124 uart0_xfer: uart0-xfer {
1125 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>,
1126 <2 RK_PD3 1 &pcfg_pull_none>;
1129 uart0_cts: uart0-cts {
1130 rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>;
1133 uart0_rts: uart0-rts {
1134 rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>;
1139 uart1_xfer: uart1-xfer {
1140 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>,
1141 <1 RK_PB2 1 &pcfg_pull_none>;
1144 uart1_cts: uart1-cts {
1145 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>;
1148 uart1_rts: uart1-rts {
1149 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1154 uart2_xfer: uart2-xfer {
1155 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1156 <1 RK_PC3 2 &pcfg_pull_none>;
1159 uart21_xfer: uart21-xfer {
1160 rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>,
1161 <1 RK_PB1 2 &pcfg_pull_none>;
1164 uart2_cts: uart2-cts {
1165 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1168 uart2_rts: uart2-rts {
1169 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;