src/arm/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
  49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72                                  <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82                                  <&ccu CLK_DRAM_DE_BE0>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer-lcd0-tve0 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91                                  <&ccu CLK_AHB_DE_BE0>,
  92                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93                                  <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         cpus {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 960000  1400000
 111                                 912000  1400000
 112                                 864000  1300000
 113                                 720000  1200000
 114                                 528000  1100000
 115                                 312000  1000000
 116                                 144000  1000000
 117                                 >;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu1: cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                         clocks = <&ccu CLK_CPU>;
 126                         clock-latency = <244144>; /* 8 32k periods */
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 960000  1400000
 130                                 912000  1400000
 131                                 864000  1300000
 132                                 720000  1200000
 133                                 528000  1100000
 134                                 312000  1000000
 135                                 144000  1000000
 136                                 >;
 137                         #cooling-cells = <2>;
 138                 };
 139         };
 140
 141         thermal-zones {
 142                 cpu_thermal {
 143                         /* milliseconds */
 144                         polling-delay-passive = <250>;
 145                         polling-delay = <1000>;
 146                         thermal-sensors = <&rtp>;
 147
 148                         cooling-maps {
 149                                 map0 {
 150                                         trip = <&cpu_alert0>;
 151                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 152                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 153                                 };
 154                         };
 155
 156                         trips {
 157                                 cpu_alert0: cpu_alert0 {
 158                                         /* milliCelsius */
 159                                         temperature = <75000>;
 160                                         hysteresis = <2000>;
 161                                         type = "passive";
 162                                 };
 163
 164                                 cpu_crit: cpu_crit {
 165                                         /* milliCelsius */
 166                                         temperature = <100000>;
 167                                         hysteresis = <2000>;
 168                                         type = "critical";
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         reserved-memory {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 ranges;
 178
 179                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 180                 default-pool {
 181                         compatible = "shared-dma-pool";
 182                         size = <0x6000000>;
 183                         alloc-ranges = <0x4a000000 0x6000000>;
 184                         reusable;
 185                         linux,cma-default;
 186                 };
 187         };
 188
 189         timer {
 190                 compatible = "arm,armv7-timer";
 191                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 194                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 195         };
 196
 197         pmu {
 198                 compatible = "arm,cortex-a7-pmu";
 199                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         clocks {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 osc24M: clk-24M {
 209                         #clock-cells = <0>;
 210                         compatible = "fixed-clock";
 211                         clock-frequency = <24000000>;
 212                         clock-output-names = "osc24M";
 213                 };
 214
 215                 osc32k: clk-32k {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <32768>;
 219                         clock-output-names = "osc32k";
 220                 };
 221
 222                 /*
 223                  * The following two are dummy clocks, placeholders
 224                  * used in the gmac_tx clock. The gmac driver will
 225                  * choose one parent depending on the PHY interface
 226                  * mode, using clk_set_rate auto-reparenting.
 227                  *
 228                  * The actual TX clock rate is not controlled by the
 229                  * gmac_tx clock.
 230                  */
 231                 mii_phy_tx_clk: clk-mii-phy-tx {
 232                         #clock-cells = <0>;
 233                         compatible = "fixed-clock";
 234                         clock-frequency = <25000000>;
 235                         clock-output-names = "mii_phy_tx";
 236                 };
 237
 238                 gmac_int_tx_clk: clk-gmac-int-tx {
 239                         #clock-cells = <0>;
 240                         compatible = "fixed-clock";
 241                         clock-frequency = <125000000>;
 242                         clock-output-names = "gmac_int_tx";
 243                 };
 244
 245                 gmac_tx_clk: clk@1c20164 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun7i-a20-gmac-clk";
 248                         reg = <0x01c20164 0x4>;
 249                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 250                         clock-output-names = "gmac_tx";
 251                 };
 252         };
 253
 254
 255         de: display-engine {
 256                 compatible = "allwinner,sun7i-a20-display-engine";
 257                 allwinner,pipelines = <&fe0>, <&fe1>;
 258                 status = "disabled";
 259         };
 260
 261         soc {
 262                 compatible = "simple-bus";
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 ranges;
 266
 267                 system-control@1c00000 {
 268                         compatible = "allwinner,sun7i-a20-system-control",
 269                                      "allwinner,sun4i-a10-system-control";
 270                         reg = <0x01c00000 0x30>;
 271                         #address-cells = <1>;
 272                         #size-cells = <1>;
 273                         ranges;
 274
 275                         sram_a: sram@0 {
 276                                 compatible = "mmio-sram";
 277                                 reg = <0x00000000 0xc000>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <1>;
 280                                 ranges = <0 0x00000000 0xc000>;
 281
 282                                 emac_sram: sram-section@8000 {
 283                                         compatible = "allwinner,sun7i-a20-sram-a3-a4",
 284                                                      "allwinner,sun4i-a10-sram-a3-a4";
 285                                         reg = <0x8000 0x4000>;
 286                                         status = "disabled";
 287                                 };
 288                         };
 289
 290                         sram_d: sram@10000 {
 291                                 compatible = "mmio-sram";
 292                                 reg = <0x00010000 0x1000>;
 293                                 #address-cells = <1>;
 294                                 #size-cells = <1>;
 295                                 ranges = <0 0x00010000 0x1000>;
 296
 297                                 otg_sram: sram-section@0 {
 298                                         compatible = "allwinner,sun7i-a20-sram-d",
 299                                                      "allwinner,sun4i-a10-sram-d";
 300                                         reg = <0x0000 0x1000>;
 301                                         status = "disabled";
 302                                 };
 303                         };
 304
 305                         sram_c: sram@1d00000 {
 306                                 compatible = "mmio-sram";
 307                                 reg = <0x01d00000 0xd0000>;
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges = <0 0x01d00000 0xd0000>;
 311
 312                                 ve_sram: sram-section@0 {
 313                                         compatible = "allwinner,sun7i-a20-sram-c1",
 314                                                      "allwinner,sun4i-a10-sram-c1";
 315                                         reg = <0x000000 0x80000>;
 316                                 };
 317                         };
 318                 };
 319
 320                 nmi_intc: interrupt-controller@1c00030 {
 321                         compatible = "allwinner,sun7i-a20-sc-nmi";
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x01c00030 0x0c>;
 325                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 326                 };
 327
 328                 dma: dma-controller@1c02000 {
 329                         compatible = "allwinner,sun4i-a10-dma";
 330                         reg = <0x01c02000 0x1000>;
 331                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&ccu CLK_AHB_DMA>;
 333                         #dma-cells = <2>;
 334                 };
 335
 336                 nfc: nand@1c03000 {
 337                         compatible = "allwinner,sun4i-a10-nand";
 338                         reg = <0x01c03000 0x1000>;
 339                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 341                         clock-names = "ahb", "mod";
 342                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 343                         dma-names = "rxtx";
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 spi0: spi@1c05000 {
 350                         compatible = "allwinner,sun4i-a10-spi";
 351                         reg = <0x01c05000 0x1000>;
 352                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 354                         clock-names = "ahb", "mod";
 355                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 356                                <&dma SUN4I_DMA_DEDICATED 26>;
 357                         dma-names = "rx", "tx";
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         num-cs = <4>;
 362                 };
 363
 364                 spi1: spi@1c06000 {
 365                         compatible = "allwinner,sun4i-a10-spi";
 366                         reg = <0x01c06000 0x1000>;
 367                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 369                         clock-names = "ahb", "mod";
 370                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 371                                <&dma SUN4I_DMA_DEDICATED 8>;
 372                         dma-names = "rx", "tx";
 373                         status = "disabled";
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         num-cs = <1>;
 377                 };
 378
 379                 emac: ethernet@1c0b000 {
 380                         compatible = "allwinner,sun4i-a10-emac";
 381                         reg = <0x01c0b000 0x1000>;
 382                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&ccu CLK_AHB_EMAC>;
 384                         allwinner,sram = <&emac_sram 1>;
 385                         status = "disabled";
 386                 };
 387
 388                 mdio: mdio@1c0b080 {
 389                         compatible = "allwinner,sun4i-a10-mdio";
 390                         reg = <0x01c0b080 0x14>;
 391                         status = "disabled";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                 };
 395
 396                 tcon0: lcd-controller@1c0c000 {
 397                         compatible = "allwinner,sun7i-a20-tcon";
 398                         reg = <0x01c0c000 0x1000>;
 399                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 400                         resets = <&ccu RST_TCON0>;
 401                         reset-names = "lcd";
 402                         clocks = <&ccu CLK_AHB_LCD0>,
 403                                  <&ccu CLK_TCON0_CH0>,
 404                                  <&ccu CLK_TCON0_CH1>;
 405                         clock-names = "ahb",
 406                                       "tcon-ch0",
 407                                       "tcon-ch1";
 408                         clock-output-names = "tcon0-pixel-clock";
 409                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 410
 411                         ports {
 412                                 #address-cells = <1>;
 413                                 #size-cells = <0>;
 414
 415                                 tcon0_in: port@0 {
 416                                         #address-cells = <1>;
 417                                         #size-cells = <0>;
 418                                         reg = <0>;
 419
 420                                         tcon0_in_be0: endpoint@0 {
 421                                                 reg = <0>;
 422                                                 remote-endpoint = <&be0_out_tcon0>;
 423                                         };
 424
 425                                         tcon0_in_be1: endpoint@1 {
 426                                                 reg = <1>;
 427                                                 remote-endpoint = <&be1_out_tcon0>;
 428                                         };
 429                                 };
 430
 431                                 tcon0_out: port@1 {
 432                                         #address-cells = <1>;
 433                                         #size-cells = <0>;
 434                                         reg = <1>;
 435
 436                                         tcon0_out_hdmi: endpoint@1 {
 437                                                 reg = <1>;
 438                                                 remote-endpoint = <&hdmi_in_tcon0>;
 439                                                 allwinner,tcon-channel = <1>;
 440                                         };
 441                                 };
 442                         };
 443                 };
 444
 445                 tcon1: lcd-controller@1c0d000 {
 446                         compatible = "allwinner,sun7i-a20-tcon";
 447                         reg = <0x01c0d000 0x1000>;
 448                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 449                         resets = <&ccu RST_TCON1>;
 450                         reset-names = "lcd";
 451                         clocks = <&ccu CLK_AHB_LCD1>,
 452                                  <&ccu CLK_TCON1_CH0>,
 453                                  <&ccu CLK_TCON1_CH1>;
 454                         clock-names = "ahb",
 455                                       "tcon-ch0",
 456                                       "tcon-ch1";
 457                         clock-output-names = "tcon1-pixel-clock";
 458                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 459
 460                         ports {
 461                                 #address-cells = <1>;
 462                                 #size-cells = <0>;
 463
 464                                 tcon1_in: port@0 {
 465                                         #address-cells = <1>;
 466                                         #size-cells = <0>;
 467                                         reg = <0>;
 468
 469                                         tcon1_in_be0: endpoint@0 {
 470                                                 reg = <0>;
 471                                                 remote-endpoint = <&be0_out_tcon1>;
 472                                         };
 473
 474                                         tcon1_in_be1: endpoint@1 {
 475                                                 reg = <1>;
 476                                                 remote-endpoint = <&be1_out_tcon1>;
 477                                         };
 478                                 };
 479
 480                                 tcon1_out: port@1 {
 481                                         #address-cells = <1>;
 482                                         #size-cells = <0>;
 483                                         reg = <1>;
 484
 485                                         tcon1_out_hdmi: endpoint@1 {
 486                                                 reg = <1>;
 487                                                 remote-endpoint = <&hdmi_in_tcon1>;
 488                                                 allwinner,tcon-channel = <1>;
 489                                         };
 490                                 };
 491                         };
 492                 };
 493
 494                 video-codec@1c0e000 {
 495                         compatible = "allwinner,sun7i-a20-video-engine";
 496                         reg = <0x01c0e000 0x1000>;
 497                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 498                                  <&ccu CLK_DRAM_VE>;
 499                         clock-names = "ahb", "mod", "ram";
 500                         resets = <&ccu RST_VE>;
 501                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 502                         allwinner,sram = <&ve_sram 1>;
 503                 };
 504
 505                 mmc0: mmc@1c0f000 {
 506                         compatible = "allwinner,sun7i-a20-mmc";
 507                         reg = <0x01c0f000 0x1000>;
 508                         clocks = <&ccu CLK_AHB_MMC0>,
 509                                  <&ccu CLK_MMC0>,
 510                                  <&ccu CLK_MMC0_OUTPUT>,
 511                                  <&ccu CLK_MMC0_SAMPLE>;
 512                         clock-names = "ahb",
 513                                       "mmc",
 514                                       "output",
 515                                       "sample";
 516                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 517                         pinctrl-names = "default";
 518                         pinctrl-0 = <&mmc0_pins>;
 519                         status = "disabled";
 520                         #address-cells = <1>;
 521                         #size-cells = <0>;
 522                 };
 523
 524                 mmc1: mmc@1c10000 {
 525                         compatible = "allwinner,sun7i-a20-mmc";
 526                         reg = <0x01c10000 0x1000>;
 527                         clocks = <&ccu CLK_AHB_MMC1>,
 528                                  <&ccu CLK_MMC1>,
 529                                  <&ccu CLK_MMC1_OUTPUT>,
 530                                  <&ccu CLK_MMC1_SAMPLE>;
 531                         clock-names = "ahb",
 532                                       "mmc",
 533                                       "output",
 534                                       "sample";
 535                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 536                         status = "disabled";
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                 };
 540
 541                 mmc2: mmc@1c11000 {
 542                         compatible = "allwinner,sun7i-a20-mmc";
 543                         reg = <0x01c11000 0x1000>;
 544                         clocks = <&ccu CLK_AHB_MMC2>,
 545                                  <&ccu CLK_MMC2>,
 546                                  <&ccu CLK_MMC2_OUTPUT>,
 547                                  <&ccu CLK_MMC2_SAMPLE>;
 548                         clock-names = "ahb",
 549                                       "mmc",
 550                                       "output",
 551                                       "sample";
 552                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 553                         pinctrl-names = "default";
 554                         pinctrl-0 = <&mmc2_pins>;
 555                         status = "disabled";
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                 };
 559
 560                 mmc3: mmc@1c12000 {
 561                         compatible = "allwinner,sun7i-a20-mmc";
 562                         reg = <0x01c12000 0x1000>;
 563                         clocks = <&ccu CLK_AHB_MMC3>,
 564                                  <&ccu CLK_MMC3>,
 565                                  <&ccu CLK_MMC3_OUTPUT>,
 566                                  <&ccu CLK_MMC3_SAMPLE>;
 567                         clock-names = "ahb",
 568                                       "mmc",
 569                                       "output",
 570                                       "sample";
 571                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 572                         pinctrl-names = "default";
 573                         pinctrl-0 = <&mmc3_pins>;
 574                         status = "disabled";
 575                         #address-cells = <1>;
 576                         #size-cells = <0>;
 577                 };
 578
 579                 usb_otg: usb@1c13000 {
 580                         compatible = "allwinner,sun4i-a10-musb";
 581                         reg = <0x01c13000 0x0400>;
 582                         clocks = <&ccu CLK_AHB_OTG>;
 583                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 584                         interrupt-names = "mc";
 585                         phys = <&usbphy 0>;
 586                         phy-names = "usb";
 587                         extcon = <&usbphy 0>;
 588                         allwinner,sram = <&otg_sram 1>;
 589                         status = "disabled";
 590                 };
 591
 592                 usbphy: phy@1c13400 {
 593                         #phy-cells = <1>;
 594                         compatible = "allwinner,sun7i-a20-usb-phy";
 595                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 596                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 597                         clocks = <&ccu CLK_USB_PHY>;
 598                         clock-names = "usb_phy";
 599                         resets = <&ccu RST_USB_PHY0>,
 600                                  <&ccu RST_USB_PHY1>,
 601                                  <&ccu RST_USB_PHY2>;
 602                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 603                         status = "disabled";
 604                 };
 605
 606                 ehci0: usb@1c14000 {
 607                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 608                         reg = <0x01c14000 0x100>;
 609                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&ccu CLK_AHB_EHCI0>;
 611                         phys = <&usbphy 1>;
 612                         phy-names = "usb";
 613                         status = "disabled";
 614                 };
 615
 616                 ohci0: usb@1c14400 {
 617                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 618                         reg = <0x01c14400 0x100>;
 619                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 620                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 621                         phys = <&usbphy 1>;
 622                         phy-names = "usb";
 623                         status = "disabled";
 624                 };
 625
 626                 crypto: crypto-engine@1c15000 {
 627                         compatible = "allwinner,sun7i-a20-crypto",
 628                                      "allwinner,sun4i-a10-crypto";
 629                         reg = <0x01c15000 0x1000>;
 630                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 632                         clock-names = "ahb", "mod";
 633                 };
 634
 635                 hdmi: hdmi@1c16000 {
 636                         compatible = "allwinner,sun7i-a20-hdmi",
 637                                      "allwinner,sun5i-a10s-hdmi";
 638                         reg = <0x01c16000 0x1000>;
 639                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 640                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 641                                  <&ccu CLK_PLL_VIDEO0_2X>,
 642                                  <&ccu CLK_PLL_VIDEO1_2X>;
 643                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 644                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 645                                <&dma SUN4I_DMA_NORMAL 16>,
 646                                <&dma SUN4I_DMA_DEDICATED 24>;
 647                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 648                         status = "disabled";
 649
 650                         ports {
 651                                 #address-cells = <1>;
 652                                 #size-cells = <0>;
 653
 654                                 hdmi_in: port@0 {
 655                                         #address-cells = <1>;
 656                                         #size-cells = <0>;
 657                                         reg = <0>;
 658
 659                                         hdmi_in_tcon0: endpoint@0 {
 660                                                 reg = <0>;
 661                                                 remote-endpoint = <&tcon0_out_hdmi>;
 662                                         };
 663
 664                                         hdmi_in_tcon1: endpoint@1 {
 665                                                 reg = <1>;
 666                                                 remote-endpoint = <&tcon1_out_hdmi>;
 667                                         };
 668                                 };
 669
 670                                 hdmi_out: port@1 {
 671                                         reg = <1>;
 672                                 };
 673                         };
 674                 };
 675
 676                 spi2: spi@1c17000 {
 677                         compatible = "allwinner,sun4i-a10-spi";
 678                         reg = <0x01c17000 0x1000>;
 679                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 680                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 681                         clock-names = "ahb", "mod";
 682                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 683                                <&dma SUN4I_DMA_DEDICATED 28>;
 684                         dma-names = "rx", "tx";
 685                         status = "disabled";
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         num-cs = <1>;
 689                 };
 690
 691                 ahci: sata@1c18000 {
 692                         compatible = "allwinner,sun4i-a10-ahci";
 693                         reg = <0x01c18000 0x1000>;
 694                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 695                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 696                         status = "disabled";
 697                 };
 698
 699                 ehci1: usb@1c1c000 {
 700                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 701                         reg = <0x01c1c000 0x100>;
 702                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&ccu CLK_AHB_EHCI1>;
 704                         phys = <&usbphy 2>;
 705                         phy-names = "usb";
 706                         status = "disabled";
 707                 };
 708
 709                 ohci1: usb@1c1c400 {
 710                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 711                         reg = <0x01c1c400 0x100>;
 712                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 714                         phys = <&usbphy 2>;
 715                         phy-names = "usb";
 716                         status = "disabled";
 717                 };
 718
 719                 spi3: spi@1c1f000 {
 720                         compatible = "allwinner,sun4i-a10-spi";
 721                         reg = <0x01c1f000 0x1000>;
 722                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 723                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 724                         clock-names = "ahb", "mod";
 725                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 726                                <&dma SUN4I_DMA_DEDICATED 30>;
 727                         dma-names = "rx", "tx";
 728                         status = "disabled";
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         num-cs = <1>;
 732                 };
 733
 734                 ccu: clock@1c20000 {
 735                         compatible = "allwinner,sun7i-a20-ccu";
 736                         reg = <0x01c20000 0x400>;
 737                         clocks = <&osc24M>, <&osc32k>;
 738                         clock-names = "hosc", "losc";
 739                         #clock-cells = <1>;
 740                         #reset-cells = <1>;
 741                 };
 742
 743                 pio: pinctrl@1c20800 {
 744                         compatible = "allwinner,sun7i-a20-pinctrl";
 745                         reg = <0x01c20800 0x400>;
 746                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 747                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 748                         clock-names = "apb", "hosc", "losc";
 749                         gpio-controller;
 750                         interrupt-controller;
 751                         #interrupt-cells = <3>;
 752                         #gpio-cells = <3>;
 753
 754                         can_ph_pins: can-ph-pins {
 755                                 pins = "PH20", "PH21";
 756                                 function = "can";
 757                         };
 758
 759                         clk_out_a_pin: clk-out-a-pin {
 760                                 pins = "PI12";
 761                                 function = "clk_out_a";
 762                         };
 763
 764                         clk_out_b_pin: clk-out-b-pin {
 765                                 pins = "PI13";
 766                                 function = "clk_out_b";
 767                         };
 768
 769                         emac_pa_pins: emac-pa-pins {
 770                                 pins = "PA0", "PA1", "PA2",
 771                                        "PA3", "PA4", "PA5", "PA6",
 772                                        "PA7", "PA8", "PA9", "PA10",
 773                                        "PA11", "PA12", "PA13", "PA14",
 774                                        "PA15", "PA16";
 775                                 function = "emac";
 776                         };
 777
 778                         gmac_mii_pins: gmac-mii-pins {
 779                                 pins = "PA0", "PA1", "PA2",
 780                                        "PA3", "PA4", "PA5", "PA6",
 781                                        "PA7", "PA8", "PA9", "PA10",
 782                                        "PA11", "PA12", "PA13", "PA14",
 783                                        "PA15", "PA16";
 784                                 function = "gmac";
 785                         };
 786
 787                         gmac_rgmii_pins: gmac-rgmii-pins {
 788                                 pins = "PA0", "PA1", "PA2",
 789                                        "PA3", "PA4", "PA5", "PA6",
 790                                         "PA7", "PA8", "PA10",
 791                                        "PA11", "PA12", "PA13",
 792                                        "PA15", "PA16";
 793                                 function = "gmac";
 794                                 /*
 795                                  * data lines in RGMII mode use DDR mode
 796                                  * and need a higher signal drive strength
 797                                  */
 798                                 drive-strength = <40>;
 799                         };
 800
 801                         i2c0_pins: i2c0-pins {
 802                                 pins = "PB0", "PB1";
 803                                 function = "i2c0";
 804                         };
 805
 806                         i2c1_pins: i2c1-pins {
 807                                 pins = "PB18", "PB19";
 808                                 function = "i2c1";
 809                         };
 810
 811                         i2c2_pins: i2c2-pins {
 812                                 pins = "PB20", "PB21";
 813                                 function = "i2c2";
 814                         };
 815
 816                         i2c3_pins: i2c3-pins {
 817                                 pins = "PI0", "PI1";
 818                                 function = "i2c3";
 819                         };
 820
 821                         ir0_rx_pin: ir0-rx-pin {
 822                                 pins = "PB4";
 823                                 function = "ir0";
 824                         };
 825
 826                         ir0_tx_pin: ir0-tx-pin {
 827                                 pins = "PB3";
 828                                 function = "ir0";
 829                         };
 830
 831                         ir1_rx_pin: ir1-rx-pin {
 832                                 pins = "PB23";
 833                                 function = "ir1";
 834                         };
 835
 836                         ir1_tx_pin: ir1-tx-pin {
 837                                 pins = "PB22";
 838                                 function = "ir1";
 839                         };
 840
 841                         mmc0_pins: mmc0-pins {
 842                                 pins = "PF0", "PF1", "PF2",
 843                                        "PF3", "PF4", "PF5";
 844                                 function = "mmc0";
 845                                 drive-strength = <30>;
 846                                 bias-pull-up;
 847                         };
 848
 849                         mmc2_pins: mmc2-pins {
 850                                 pins = "PC6", "PC7", "PC8",
 851                                        "PC9", "PC10", "PC11";
 852                                 function = "mmc2";
 853                                 drive-strength = <30>;
 854                                 bias-pull-up;
 855                         };
 856
 857                         mmc3_pins: mmc3-pins {
 858                                 pins = "PI4", "PI5", "PI6",
 859                                        "PI7", "PI8", "PI9";
 860                                 function = "mmc3";
 861                                 drive-strength = <30>;
 862                                 bias-pull-up;
 863                         };
 864
 865                         ps2_0_pins: ps2-0-pins {
 866                                 pins = "PI20", "PI21";
 867                                 function = "ps2";
 868                         };
 869
 870                         ps2_1_ph_pins: ps2-1-ph-pins {
 871                                 pins = "PH12", "PH13";
 872                                 function = "ps2";
 873                         };
 874
 875                         pwm0_pin: pwm0-pin {
 876                                 pins = "PB2";
 877                                 function = "pwm";
 878                         };
 879
 880                         pwm1_pin: pwm1-pin {
 881                                 pins = "PI3";
 882                                 function = "pwm";
 883                         };
 884
 885                         spdif_tx_pin: spdif-tx-pin {
 886                                 pins = "PB13";
 887                                 function = "spdif";
 888                                 bias-pull-up;
 889                         };
 890
 891                         spi0_pi_pins: spi0-pi-pins {
 892                                 pins = "PI11", "PI12", "PI13";
 893                                 function = "spi0";
 894                         };
 895
 896                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 897                                 pins = "PI10";
 898                                 function = "spi0";
 899                         };
 900
 901                         spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 902                                 pins = "PI14";
 903                                 function = "spi0";
 904                         };
 905
 906                         spi1_pi_pins: spi1-pi-pins {
 907                                 pins = "PI17", "PI18", "PI19";
 908                                 function = "spi1";
 909                         };
 910
 911                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 912                                 pins = "PI16";
 913                                 function = "spi1";
 914                         };
 915
 916                         spi2_pb_pins: spi2-pb-pins {
 917                                 pins = "PB15", "PB16", "PB17";
 918                                 function = "spi2";
 919                         };
 920
 921                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 922                                 pins = "PB14";
 923                                 function = "spi2";
 924                         };
 925
 926                         spi2_pc_pins: spi2-pc-pins {
 927                                 pins = "PC20", "PC21", "PC22";
 928                                 function = "spi2";
 929                         };
 930
 931                         spi2_cs0_pc_pin: spi2-cs0-pc-pin {
 932                                 pins = "PC19";
 933                                 function = "spi2";
 934                         };
 935
 936                         uart0_pb_pins: uart0-pb-pins {
 937                                 pins = "PB22", "PB23";
 938                                 function = "uart0";
 939                         };
 940
 941                         uart2_pi_pins: uart2-pi-pins {
 942                                 pins = "PI18", "PI19";
 943                                 function = "uart2";
 944                         };
 945
 946                         uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
 947                                 pins = "PI16", "PI17";
 948                                 function = "uart2";
 949                         };
 950
 951                         uart3_pg_pins: uart3-pg-pins {
 952                                 pins = "PG6", "PG7";
 953                                 function = "uart3";
 954                         };
 955
 956                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
 957                                 pins = "PG8", "PG9";
 958                                 function = "uart3";
 959                         };
 960
 961                         uart3_ph_pins: uart3-ph-pins {
 962                                 pins = "PH0", "PH1";
 963                                 function = "uart3";
 964                         };
 965
 966                         uart4_pg_pins: uart4-pg-pins {
 967                                 pins = "PG10", "PG11";
 968                                 function = "uart4";
 969                         };
 970
 971                         uart4_ph_pins: uart4-ph-pins {
 972                                 pins = "PH4", "PH5";
 973                                 function = "uart4";
 974                         };
 975
 976                         uart5_pi_pins: uart5-pi-pins {
 977                                 pins = "PI10", "PI11";
 978                                 function = "uart5";
 979                         };
 980
 981                         uart6_pi_pins: uart6-pi-pins {
 982                                 pins = "PI12", "PI13";
 983                                 function = "uart6";
 984                         };
 985
 986                         uart7_pi_pins: uart7-pi-pins {
 987                                 pins = "PI20", "PI21";
 988                                 function = "uart7";
 989                         };
 990                 };
 991
 992                 timer@1c20c00 {
 993                         compatible = "allwinner,sun4i-a10-timer";
 994                         reg = <0x01c20c00 0x90>;
 995                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 997                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 998                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 999                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1000                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1001                         clocks = <&osc24M>;
1002                 };
1003
1004                 wdt: watchdog@1c20c90 {
1005                         compatible = "allwinner,sun4i-a10-wdt";
1006                         reg = <0x01c20c90 0x10>;
1007                 };
1008
1009                 rtc: rtc@1c20d00 {
1010                         compatible = "allwinner,sun7i-a20-rtc";
1011                         reg = <0x01c20d00 0x20>;
1012                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1013                 };
1014
1015                 pwm: pwm@1c20e00 {
1016                         compatible = "allwinner,sun7i-a20-pwm";
1017                         reg = <0x01c20e00 0xc>;
1018                         clocks = <&osc24M>;
1019                         #pwm-cells = <3>;
1020                         status = "disabled";
1021                 };
1022
1023                 spdif: spdif@1c21000 {
1024                         #sound-dai-cells = <0>;
1025                         compatible = "allwinner,sun4i-a10-spdif";
1026                         reg = <0x01c21000 0x400>;
1027                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1028                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1029                         clock-names = "apb", "spdif";
1030                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1031                                <&dma SUN4I_DMA_NORMAL 2>;
1032                         dma-names = "rx", "tx";
1033                         status = "disabled";
1034                 };
1035
1036                 ir0: ir@1c21800 {
1037                         compatible = "allwinner,sun4i-a10-ir";
1038                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1039                         clock-names = "apb", "ir";
1040                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1041                         reg = <0x01c21800 0x40>;
1042                         status = "disabled";
1043                 };
1044
1045                 ir1: ir@1c21c00 {
1046                         compatible = "allwinner,sun4i-a10-ir";
1047                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1048                         clock-names = "apb", "ir";
1049                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1050                         reg = <0x01c21c00 0x40>;
1051                         status = "disabled";
1052                 };
1053
1054                 i2s1: i2s@1c22000 {
1055                         #sound-dai-cells = <0>;
1056                         compatible = "allwinner,sun4i-a10-i2s";
1057                         reg = <0x01c22000 0x400>;
1058                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1059                         clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1060                         clock-names = "apb", "mod";
1061                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1062                                <&dma SUN4I_DMA_NORMAL 4>;
1063                         dma-names = "rx", "tx";
1064                         status = "disabled";
1065                 };
1066
1067                 i2s0: i2s@1c22400 {
1068                         #sound-dai-cells = <0>;
1069                         compatible = "allwinner,sun4i-a10-i2s";
1070                         reg = <0x01c22400 0x400>;
1071                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1072                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1073                         clock-names = "apb", "mod";
1074                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1075                                <&dma SUN4I_DMA_NORMAL 3>;
1076                         dma-names = "rx", "tx";
1077                         status = "disabled";
1078                 };
1079
1080                 lradc: lradc@1c22800 {
1081                         compatible = "allwinner,sun4i-a10-lradc-keys";
1082                         reg = <0x01c22800 0x100>;
1083                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1084                         status = "disabled";
1085                 };
1086
1087                 codec: codec@1c22c00 {
1088                         #sound-dai-cells = <0>;
1089                         compatible = "allwinner,sun7i-a20-codec";
1090                         reg = <0x01c22c00 0x40>;
1091                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1092                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1093                         clock-names = "apb", "codec";
1094                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1095                                <&dma SUN4I_DMA_NORMAL 19>;
1096                         dma-names = "rx", "tx";
1097                         status = "disabled";
1098                 };
1099
1100                 sid: eeprom@1c23800 {
1101                         compatible = "allwinner,sun7i-a20-sid";
1102                         reg = <0x01c23800 0x200>;
1103                 };
1104
1105                 i2s2: i2s@1c24400 {
1106                         #sound-dai-cells = <0>;
1107                         compatible = "allwinner,sun4i-a10-i2s";
1108                         reg = <0x01c24400 0x400>;
1109                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1110                         clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1111                         clock-names = "apb", "mod";
1112                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1113                                <&dma SUN4I_DMA_NORMAL 6>;
1114                         dma-names = "rx", "tx";
1115                         status = "disabled";
1116                 };
1117
1118                 rtp: rtp@1c25000 {
1119                         compatible = "allwinner,sun5i-a13-ts";
1120                         reg = <0x01c25000 0x100>;
1121                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1122                         #thermal-sensor-cells = <0>;
1123                 };
1124
1125                 uart0: serial@1c28000 {
1126                         compatible = "snps,dw-apb-uart";
1127                         reg = <0x01c28000 0x400>;
1128                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1129                         reg-shift = <2>;
1130                         reg-io-width = <4>;
1131                         clocks = <&ccu CLK_APB1_UART0>;
1132                         status = "disabled";
1133                 };
1134
1135                 uart1: serial@1c28400 {
1136                         compatible = "snps,dw-apb-uart";
1137                         reg = <0x01c28400 0x400>;
1138                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1139                         reg-shift = <2>;
1140                         reg-io-width = <4>;
1141                         clocks = <&ccu CLK_APB1_UART1>;
1142                         status = "disabled";
1143                 };
1144
1145                 uart2: serial@1c28800 {
1146                         compatible = "snps,dw-apb-uart";
1147                         reg = <0x01c28800 0x400>;
1148                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1149                         reg-shift = <2>;
1150                         reg-io-width = <4>;
1151                         clocks = <&ccu CLK_APB1_UART2>;
1152                         status = "disabled";
1153                 };
1154
1155                 uart3: serial@1c28c00 {
1156                         compatible = "snps,dw-apb-uart";
1157                         reg = <0x01c28c00 0x400>;
1158                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1159                         reg-shift = <2>;
1160                         reg-io-width = <4>;
1161                         clocks = <&ccu CLK_APB1_UART3>;
1162                         status = "disabled";
1163                 };
1164
1165                 uart4: serial@1c29000 {
1166                         compatible = "snps,dw-apb-uart";
1167                         reg = <0x01c29000 0x400>;
1168                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1169                         reg-shift = <2>;
1170                         reg-io-width = <4>;
1171                         clocks = <&ccu CLK_APB1_UART4>;
1172                         status = "disabled";
1173                 };
1174
1175                 uart5: serial@1c29400 {
1176                         compatible = "snps,dw-apb-uart";
1177                         reg = <0x01c29400 0x400>;
1178                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1179                         reg-shift = <2>;
1180                         reg-io-width = <4>;
1181                         clocks = <&ccu CLK_APB1_UART5>;
1182                         status = "disabled";
1183                 };
1184
1185                 uart6: serial@1c29800 {
1186                         compatible = "snps,dw-apb-uart";
1187                         reg = <0x01c29800 0x400>;
1188                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1189                         reg-shift = <2>;
1190                         reg-io-width = <4>;
1191                         clocks = <&ccu CLK_APB1_UART6>;
1192                         status = "disabled";
1193                 };
1194
1195                 uart7: serial@1c29c00 {
1196                         compatible = "snps,dw-apb-uart";
1197                         reg = <0x01c29c00 0x400>;
1198                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1199                         reg-shift = <2>;
1200                         reg-io-width = <4>;
1201                         clocks = <&ccu CLK_APB1_UART7>;
1202                         status = "disabled";
1203                 };
1204
1205                 ps20: ps2@1c2a000 {
1206                         compatible = "allwinner,sun4i-a10-ps2";
1207                         reg = <0x01c2a000 0x400>;
1208                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1209                         clocks = <&ccu CLK_APB1_PS20>;
1210                         status = "disabled";
1211                 };
1212
1213                 ps21: ps2@1c2a400 {
1214                         compatible = "allwinner,sun4i-a10-ps2";
1215                         reg = <0x01c2a400 0x400>;
1216                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1217                         clocks = <&ccu CLK_APB1_PS21>;
1218                         status = "disabled";
1219                 };
1220
1221                 i2c0: i2c@1c2ac00 {
1222                         compatible = "allwinner,sun7i-a20-i2c",
1223                                      "allwinner,sun4i-a10-i2c";
1224                         reg = <0x01c2ac00 0x400>;
1225                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1226                         clocks = <&ccu CLK_APB1_I2C0>;
1227                         pinctrl-names = "default";
1228                         pinctrl-0 = <&i2c0_pins>;
1229                         status = "disabled";
1230                         #address-cells = <1>;
1231                         #size-cells = <0>;
1232                 };
1233
1234                 i2c1: i2c@1c2b000 {
1235                         compatible = "allwinner,sun7i-a20-i2c",
1236                                      "allwinner,sun4i-a10-i2c";
1237                         reg = <0x01c2b000 0x400>;
1238                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1239                         clocks = <&ccu CLK_APB1_I2C1>;
1240                         pinctrl-names = "default";
1241                         pinctrl-0 = <&i2c1_pins>;
1242                         status = "disabled";
1243                         #address-cells = <1>;
1244                         #size-cells = <0>;
1245                 };
1246
1247                 i2c2: i2c@1c2b400 {
1248                         compatible = "allwinner,sun7i-a20-i2c",
1249                                      "allwinner,sun4i-a10-i2c";
1250                         reg = <0x01c2b400 0x400>;
1251                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1252                         clocks = <&ccu CLK_APB1_I2C2>;
1253                         pinctrl-names = "default";
1254                         pinctrl-0 = <&i2c2_pins>;
1255                         status = "disabled";
1256                         #address-cells = <1>;
1257                         #size-cells = <0>;
1258                 };
1259
1260                 i2c3: i2c@1c2b800 {
1261                         compatible = "allwinner,sun7i-a20-i2c",
1262                                      "allwinner,sun4i-a10-i2c";
1263                         reg = <0x01c2b800 0x400>;
1264                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1265                         clocks = <&ccu CLK_APB1_I2C3>;
1266                         pinctrl-names = "default";
1267                         pinctrl-0 = <&i2c3_pins>;
1268                         status = "disabled";
1269                         #address-cells = <1>;
1270                         #size-cells = <0>;
1271                 };
1272
1273                 can0: can@1c2bc00 {
1274                         compatible = "allwinner,sun7i-a20-can",
1275                                      "allwinner,sun4i-a10-can";
1276                         reg = <0x01c2bc00 0x400>;
1277                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1278                         clocks = <&ccu CLK_APB1_CAN>;
1279                         status = "disabled";
1280                 };
1281
1282                 i2c4: i2c@1c2c000 {
1283                         compatible = "allwinner,sun7i-a20-i2c",
1284                                      "allwinner,sun4i-a10-i2c";
1285                         reg = <0x01c2c000 0x400>;
1286                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1287                         clocks = <&ccu CLK_APB1_I2C4>;
1288                         status = "disabled";
1289                         #address-cells = <1>;
1290                         #size-cells = <0>;
1291                 };
1292
1293                 mali: gpu@1c40000 {
1294                         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1295                         reg = <0x01c40000 0x10000>;
1296                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1297                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1298                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1299                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1300                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1301                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1302                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1303                         interrupt-names = "gp",
1304                                           "gpmmu",
1305                                           "pp0",
1306                                           "ppmmu0",
1307                                           "pp1",
1308                                           "ppmmu1",
1309                                           "pmu";
1310                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1311                         clock-names = "bus", "core";
1312                         resets = <&ccu RST_GPU>;
1313
1314                         assigned-clocks = <&ccu CLK_GPU>;
1315                         assigned-clock-rates = <384000000>;
1316                 };
1317
1318                 gmac: ethernet@1c50000 {
1319                         compatible = "allwinner,sun7i-a20-gmac";
1320                         reg = <0x01c50000 0x10000>;
1321                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1322                         interrupt-names = "macirq";
1323                         clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1324                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1325                         snps,pbl = <2>;
1326                         snps,fixed-burst;
1327                         snps,force_sf_dma_mode;
1328                         status = "disabled";
1329                         #address-cells = <1>;
1330                         #size-cells = <0>;
1331                 };
1332
1333                 hstimer@1c60000 {
1334                         compatible = "allwinner,sun7i-a20-hstimer";
1335                         reg = <0x01c60000 0x1000>;
1336                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1337                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1338                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1339                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1340                         clocks = <&ccu CLK_AHB_HSTIMER>;
1341                 };
1342
1343                 gic: interrupt-controller@1c81000 {
1344                         compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1345                         reg = <0x01c81000 0x1000>,
1346                               <0x01c82000 0x2000>,
1347                               <0x01c84000 0x2000>,
1348                               <0x01c86000 0x2000>;
1349                         interrupt-controller;
1350                         #interrupt-cells = <3>;
1351                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1352                 };
1353
1354                 fe0: display-frontend@1e00000 {
1355                         compatible = "allwinner,sun7i-a20-display-frontend";
1356                         reg = <0x01e00000 0x20000>;
1357                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1358                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1359                                  <&ccu CLK_DRAM_DE_FE0>;
1360                         clock-names = "ahb", "mod",
1361                                       "ram";
1362                         resets = <&ccu RST_DE_FE0>;
1363
1364                         ports {
1365                                 #address-cells = <1>;
1366                                 #size-cells = <0>;
1367
1368                                 fe0_out: port@1 {
1369                                         #address-cells = <1>;
1370                                         #size-cells = <0>;
1371                                         reg = <1>;
1372
1373                                         fe0_out_be0: endpoint@0 {
1374                                                 reg = <0>;
1375                                                 remote-endpoint = <&be0_in_fe0>;
1376                                         };
1377
1378                                         fe0_out_be1: endpoint@1 {
1379                                                 reg = <1>;
1380                                                 remote-endpoint = <&be1_in_fe0>;
1381                                         };
1382                                 };
1383                         };
1384                 };
1385
1386                 fe1: display-frontend@1e20000 {
1387                         compatible = "allwinner,sun7i-a20-display-frontend";
1388                         reg = <0x01e20000 0x20000>;
1389                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1390                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1391                                  <&ccu CLK_DRAM_DE_FE1>;
1392                         clock-names = "ahb", "mod",
1393                                       "ram";
1394                         resets = <&ccu RST_DE_FE1>;
1395
1396                         ports {
1397                                 #address-cells = <1>;
1398                                 #size-cells = <0>;
1399
1400                                 fe1_out: port@1 {
1401                                         #address-cells = <1>;
1402                                         #size-cells = <0>;
1403                                         reg = <1>;
1404
1405                                         fe1_out_be0: endpoint@0 {
1406                                                 reg = <0>;
1407                                                 remote-endpoint = <&be0_in_fe1>;
1408                                         };
1409
1410                                         fe1_out_be1: endpoint@1 {
1411                                                 reg = <1>;
1412                                                 remote-endpoint = <&be1_in_fe1>;
1413                                         };
1414                                 };
1415                         };
1416                 };
1417
1418                 be1: display-backend@1e40000 {
1419                         compatible = "allwinner,sun7i-a20-display-backend";
1420                         reg = <0x01e40000 0x10000>;
1421                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1422                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1423                                  <&ccu CLK_DRAM_DE_BE1>;
1424                         clock-names = "ahb", "mod",
1425                                       "ram";
1426                         resets = <&ccu RST_DE_BE1>;
1427
1428                         ports {
1429                                 #address-cells = <1>;
1430                                 #size-cells = <0>;
1431
1432                                 be1_in: port@0 {
1433                                         #address-cells = <1>;
1434                                         #size-cells = <0>;
1435                                         reg = <0>;
1436
1437                                         be1_in_fe0: endpoint@0 {
1438                                                 reg = <0>;
1439                                                 remote-endpoint = <&fe0_out_be1>;
1440                                         };
1441
1442                                         be1_in_fe1: endpoint@1 {
1443                                                 reg = <1>;
1444                                                 remote-endpoint = <&fe1_out_be1>;
1445                                         };
1446                                 };
1447
1448                                 be1_out: port@1 {
1449                                         #address-cells = <1>;
1450                                         #size-cells = <0>;
1451                                         reg = <1>;
1452
1453                                         be1_out_tcon0: endpoint@0 {
1454                                                 reg = <0>;
1455                                                 remote-endpoint = <&tcon0_in_be1>;
1456                                         };
1457
1458                                         be1_out_tcon1: endpoint@1 {
1459                                                 reg = <1>;
1460                                                 remote-endpoint = <&tcon1_in_be1>;
1461                                         };
1462                                 };
1463                         };
1464                 };
1465
1466                 be0: display-backend@1e60000 {
1467                         compatible = "allwinner,sun7i-a20-display-backend";
1468                         reg = <0x01e60000 0x10000>;
1469                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1470                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1471                                  <&ccu CLK_DRAM_DE_BE0>;
1472                         clock-names = "ahb", "mod",
1473                                       "ram";
1474                         resets = <&ccu RST_DE_BE0>;
1475
1476                         ports {
1477                                 #address-cells = <1>;
1478                                 #size-cells = <0>;
1479
1480                                 be0_in: port@0 {
1481                                         #address-cells = <1>;
1482                                         #size-cells = <0>;
1483                                         reg = <0>;
1484
1485                                         be0_in_fe0: endpoint@0 {
1486                                                 reg = <0>;
1487                                                 remote-endpoint = <&fe0_out_be0>;
1488                                         };
1489
1490                                         be0_in_fe1: endpoint@1 {
1491                                                 reg = <1>;
1492                                                 remote-endpoint = <&fe1_out_be0>;
1493                                         };
1494                                 };
1495
1496                                 be0_out: port@1 {
1497                                         #address-cells = <1>;
1498                                         #size-cells = <0>;
1499                                         reg = <1>;
1500
1501                                         be0_out_tcon0: endpoint@0 {
1502                                                 reg = <0>;
1503                                                 remote-endpoint = <&tcon0_in_be0>;
1504                                         };
1505
1506                                         be0_out_tcon1: endpoint@1 {
1507                                                 reg = <1>;
1508                                                 remote-endpoint = <&tcon1_in_be0>;
1509                                         };
1510                                 };
1511                         };
1512                 };
1513         };
1514 };