src/arm/sun8i-a83t.dtsi

   1 /*
   2  * Copyright 2015 Vishnu Patekar
   3  *
   4  * Vishnu Patekar <vishnupatekar0510@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
  48 #include <dt-bindings/clock/sun8i-de2.h>
  49 #include <dt-bindings/clock/sun8i-r-ccu.h>
  50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
  51 #include <dt-bindings/reset/sun8i-de2.h>
  52 #include <dt-bindings/reset/sun8i-r-ccu.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56         #address-cells = <1>;
  57         #size-cells = <1>;
  58
  59         cpus {
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 cpu0: cpu@0 {
  64                         clocks = <&ccu CLK_C0CPUX>;
  65                         clock-names = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         device_type = "cpu";
  68                         operating-points-v2 = <&cpu0_opp_table>;
  69                         cci-control-port = <&cci_control0>;
  70                         enable-method = "allwinner,sun8i-a83t-smp";
  71                         reg = <0>;
  72                 };
  73
  74                 cpu@1 {
  75                         compatible = "arm,cortex-a7";
  76                         device_type = "cpu";
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                         cci-control-port = <&cci_control0>;
  79                         enable-method = "allwinner,sun8i-a83t-smp";
  80                         reg = <1>;
  81                 };
  82
  83                 cpu@2 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         operating-points-v2 = <&cpu0_opp_table>;
  87                         cci-control-port = <&cci_control0>;
  88                         enable-method = "allwinner,sun8i-a83t-smp";
  89                         reg = <2>;
  90                 };
  91
  92                 cpu@3 {
  93                         compatible = "arm,cortex-a7";
  94                         device_type = "cpu";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cci-control-port = <&cci_control0>;
  97                         enable-method = "allwinner,sun8i-a83t-smp";
  98                         reg = <3>;
  99                 };
 100
 101                 cpu100: cpu@100 {
 102                         clocks = <&ccu CLK_C1CPUX>;
 103                         clock-names = "cpu";
 104                         compatible = "arm,cortex-a7";
 105                         device_type = "cpu";
 106                         operating-points-v2 = <&cpu1_opp_table>;
 107                         cci-control-port = <&cci_control1>;
 108                         enable-method = "allwinner,sun8i-a83t-smp";
 109                         reg = <0x100>;
 110                 };
 111
 112                 cpu@101 {
 113                         compatible = "arm,cortex-a7";
 114                         device_type = "cpu";
 115                         operating-points-v2 = <&cpu1_opp_table>;
 116                         cci-control-port = <&cci_control1>;
 117                         enable-method = "allwinner,sun8i-a83t-smp";
 118                         reg = <0x101>;
 119                 };
 120
 121                 cpu@102 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         operating-points-v2 = <&cpu1_opp_table>;
 125                         cci-control-port = <&cci_control1>;
 126                         enable-method = "allwinner,sun8i-a83t-smp";
 127                         reg = <0x102>;
 128                 };
 129
 130                 cpu@103 {
 131                         compatible = "arm,cortex-a7";
 132                         device_type = "cpu";
 133                         operating-points-v2 = <&cpu1_opp_table>;
 134                         cci-control-port = <&cci_control1>;
 135                         enable-method = "allwinner,sun8i-a83t-smp";
 136                         reg = <0x103>;
 137                 };
 138         };
 139
 140         timer {
 141                 compatible = "arm,armv7-timer";
 142                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 143                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 144                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 145                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 146         };
 147
 148         clocks {
 149                 #address-cells = <1>;
 150                 #size-cells = <1>;
 151                 ranges;
 152
 153                 /* TODO: PRCM block has a mux for this. */
 154                 osc24M: osc24M_clk {
 155                         #clock-cells = <0>;
 156                         compatible = "fixed-clock";
 157                         clock-frequency = <24000000>;
 158                         clock-accuracy = <50000>;
 159                         clock-output-names = "osc24M";
 160                 };
 161
 162                 /*
 163                  * This is called "internal OSC" in some places.
 164                  * It is an internal RC-based oscillator.
 165                  * TODO: Its controls are in the PRCM block.
 166                  */
 167                 osc16M: osc16M_clk {
 168                         #clock-cells = <0>;
 169                         compatible = "fixed-clock";
 170                         clock-frequency = <16000000>;
 171                         clock-output-names = "osc16M";
 172                 };
 173
 174                 osc16Md512: osc16Md512_clk {
 175                         #clock-cells = <0>;
 176                         compatible = "fixed-factor-clock";
 177                         clock-div = <512>;
 178                         clock-mult = <1>;
 179                         clocks = <&osc16M>;
 180                         clock-output-names = "osc16M-d512";
 181                 };
 182         };
 183
 184         de: display-engine {
 185                 compatible = "allwinner,sun8i-a83t-display-engine";
 186                 allwinner,pipelines = <&mixer0>, <&mixer1>;
 187                 status = "disabled";
 188         };
 189
 190         cpu0_opp_table: opp_table0 {
 191                 compatible = "operating-points-v2";
 192                 opp-shared;
 193
 194                 opp-480000000 {
 195                         opp-hz = /bits/ 64 <480000000>;
 196                         opp-microvolt = <840000>;
 197                         clock-latency-ns = <244144>; /* 8 32k periods */
 198                 };
 199
 200                 opp-600000000 {
 201                         opp-hz = /bits/ 64 <600000000>;
 202                         opp-microvolt = <840000>;
 203                         clock-latency-ns = <244144>; /* 8 32k periods */
 204                 };
 205
 206                 opp-720000000 {
 207                         opp-hz = /bits/ 64 <720000000>;
 208                         opp-microvolt = <840000>;
 209                         clock-latency-ns = <244144>; /* 8 32k periods */
 210                 };
 211
 212                 opp-864000000 {
 213                         opp-hz = /bits/ 64 <864000000>;
 214                         opp-microvolt = <840000>;
 215                         clock-latency-ns = <244144>; /* 8 32k periods */
 216                 };
 217
 218                 opp-912000000 {
 219                         opp-hz = /bits/ 64 <912000000>;
 220                         opp-microvolt = <840000>;
 221                         clock-latency-ns = <244144>; /* 8 32k periods */
 222                 };
 223
 224                 opp-1008000000 {
 225                         opp-hz = /bits/ 64 <1008000000>;
 226                         opp-microvolt = <840000>;
 227                         clock-latency-ns = <244144>; /* 8 32k periods */
 228                 };
 229
 230                 opp-1128000000 {
 231                         opp-hz = /bits/ 64 <1128000000>;
 232                         opp-microvolt = <840000>;
 233                         clock-latency-ns = <244144>; /* 8 32k periods */
 234                 };
 235
 236                 opp-1200000000 {
 237                         opp-hz = /bits/ 64 <1200000000>;
 238                         opp-microvolt = <840000>;
 239                         clock-latency-ns = <244144>; /* 8 32k periods */
 240                 };
 241         };
 242
 243         cpu1_opp_table: opp_table1 {
 244                 compatible = "operating-points-v2";
 245                 opp-shared;
 246
 247                 opp-480000000 {
 248                         opp-hz = /bits/ 64 <480000000>;
 249                         opp-microvolt = <840000>;
 250                         clock-latency-ns = <244144>; /* 8 32k periods */
 251                 };
 252
 253                 opp-600000000 {
 254                         opp-hz = /bits/ 64 <600000000>;
 255                         opp-microvolt = <840000>;
 256                         clock-latency-ns = <244144>; /* 8 32k periods */
 257                 };
 258
 259                 opp-720000000 {
 260                         opp-hz = /bits/ 64 <720000000>;
 261                         opp-microvolt = <840000>;
 262                         clock-latency-ns = <244144>; /* 8 32k periods */
 263                 };
 264
 265                 opp-864000000 {
 266                         opp-hz = /bits/ 64 <864000000>;
 267                         opp-microvolt = <840000>;
 268                         clock-latency-ns = <244144>; /* 8 32k periods */
 269                 };
 270
 271                 opp-912000000 {
 272                         opp-hz = /bits/ 64 <912000000>;
 273                         opp-microvolt = <840000>;
 274                         clock-latency-ns = <244144>; /* 8 32k periods */
 275                 };
 276
 277                 opp-1008000000 {
 278                         opp-hz = /bits/ 64 <1008000000>;
 279                         opp-microvolt = <840000>;
 280                         clock-latency-ns = <244144>; /* 8 32k periods */
 281                 };
 282
 283                 opp-1128000000 {
 284                         opp-hz = /bits/ 64 <1128000000>;
 285                         opp-microvolt = <840000>;
 286                         clock-latency-ns = <244144>; /* 8 32k periods */
 287                 };
 288
 289                 opp-1200000000 {
 290                         opp-hz = /bits/ 64 <1200000000>;
 291                         opp-microvolt = <840000>;
 292                         clock-latency-ns = <244144>; /* 8 32k periods */
 293                 };
 294         };
 295
 296         soc {
 297                 compatible = "simple-bus";
 298                 #address-cells = <1>;
 299                 #size-cells = <1>;
 300                 ranges;
 301
 302                 display_clocks: clock@1000000 {
 303                         compatible = "allwinner,sun8i-a83t-de2-clk";
 304                         reg = <0x01000000 0x100000>;
 305                         clocks = <&ccu CLK_PLL_DE>,
 306                                  <&ccu CLK_BUS_DE>;
 307                         clock-names = "mod",
 308                                       "bus";
 309                         resets = <&ccu RST_BUS_DE>;
 310                         #clock-cells = <1>;
 311                         #reset-cells = <1>;
 312                 };
 313
 314                 mixer0: mixer@1100000 {
 315                         compatible = "allwinner,sun8i-a83t-de2-mixer-0";
 316                         reg = <0x01100000 0x100000>;
 317                         clocks = <&display_clocks CLK_BUS_MIXER0>,
 318                                  <&display_clocks CLK_MIXER0>;
 319                         clock-names = "bus",
 320                                       "mod";
 321                         resets = <&display_clocks RST_MIXER0>;
 322
 323                         ports {
 324                                 #address-cells = <1>;
 325                                 #size-cells = <0>;
 326
 327                                 mixer0_out: port@1 {
 328                                         #address-cells = <1>;
 329                                         #size-cells = <0>;
 330                                         reg = <1>;
 331
 332                                         mixer0_out_tcon0: endpoint@0 {
 333                                                 reg = <0>;
 334                                                 remote-endpoint = <&tcon0_in_mixer0>;
 335                                         };
 336                                 };
 337                         };
 338                 };
 339
 340                 mixer1: mixer@1200000 {
 341                         compatible = "allwinner,sun8i-a83t-de2-mixer-1";
 342                         reg = <0x01200000 0x100000>;
 343                         clocks = <&display_clocks CLK_BUS_MIXER1>,
 344                                  <&display_clocks CLK_MIXER1>;
 345                         clock-names = "bus",
 346                                       "mod";
 347                         resets = <&display_clocks RST_WB>;
 348
 349                         ports {
 350                                 #address-cells = <1>;
 351                                 #size-cells = <0>;
 352
 353                                 mixer1_out: port@1 {
 354                                         reg = <1>;
 355
 356                                         mixer1_out_tcon1: endpoint {
 357                                                 remote-endpoint = <&tcon1_in_mixer1>;
 358                                         };
 359                                 };
 360                         };
 361                 };
 362
 363                 cpucfg@1700000 {
 364                         compatible = "allwinner,sun8i-a83t-cpucfg";
 365                         reg = <0x01700000 0x400>;
 366                 };
 367
 368                 cci@1790000 {
 369                         compatible = "arm,cci-400";
 370                         #address-cells = <1>;
 371                         #size-cells = <1>;
 372                         reg = <0x01790000 0x10000>;
 373                         ranges = <0x0 0x01790000 0x10000>;
 374
 375                         cci_control0: slave-if@4000 {
 376                                 compatible = "arm,cci-400-ctrl-if";
 377                                 interface-type = "ace";
 378                                 reg = <0x4000 0x1000>;
 379                         };
 380
 381                         cci_control1: slave-if@5000 {
 382                                 compatible = "arm,cci-400-ctrl-if";
 383                                 interface-type = "ace";
 384                                 reg = <0x5000 0x1000>;
 385                         };
 386
 387                         pmu@9000 {
 388                                 compatible = "arm,cci-400-pmu,r1";
 389                                 reg = <0x9000 0x5000>;
 390                                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 391                                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 392                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 394                                              <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 395                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 396                                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 397                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 398                         };
 399                 };
 400
 401                 syscon: syscon@1c00000 {
 402                         compatible = "allwinner,sun8i-a83t-system-controller",
 403                                 "syscon";
 404                         reg = <0x01c00000 0x1000>;
 405                 };
 406
 407                 dma: dma-controller@1c02000 {
 408                         compatible = "allwinner,sun8i-a83t-dma";
 409                         reg = <0x01c02000 0x1000>;
 410                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&ccu CLK_BUS_DMA>;
 412                         resets = <&ccu RST_BUS_DMA>;
 413                         #dma-cells = <1>;
 414                 };
 415
 416                 tcon0: lcd-controller@1c0c000 {
 417                         compatible = "allwinner,sun8i-a83t-tcon-lcd";
 418                         reg = <0x01c0c000 0x1000>;
 419                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
 421                         clock-names = "ahb", "tcon-ch0";
 422                         clock-output-names = "tcon-pixel-clock";
 423                         resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
 424                         reset-names = "lcd", "lvds";
 425
 426                         ports {
 427                                 #address-cells = <1>;
 428                                 #size-cells = <0>;
 429
 430                                 tcon0_in: port@0 {
 431                                         #address-cells = <1>;
 432                                         #size-cells = <0>;
 433                                         reg = <0>;
 434
 435                                         tcon0_in_mixer0: endpoint@0 {
 436                                                 reg = <0>;
 437                                                 remote-endpoint = <&mixer0_out_tcon0>;
 438                                         };
 439                                 };
 440
 441                                 tcon0_out: port@1 {
 442                                         #address-cells = <1>;
 443                                         #size-cells = <0>;
 444                                         reg = <1>;
 445                                 };
 446                         };
 447                 };
 448
 449                 tcon1: lcd-controller@1c0d000 {
 450                         compatible = "allwinner,sun8i-a83t-tcon-tv";
 451                         reg = <0x01c0d000 0x1000>;
 452                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 453                         clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
 454                         clock-names = "ahb", "tcon-ch1";
 455                         resets = <&ccu RST_BUS_TCON1>;
 456                         reset-names = "lcd";
 457
 458                         ports {
 459                                 #address-cells = <1>;
 460                                 #size-cells = <0>;
 461
 462                                 tcon1_in: port@0 {
 463                                         reg = <0>;
 464
 465                                         tcon1_in_mixer1: endpoint {
 466                                                 remote-endpoint = <&mixer1_out_tcon1>;
 467                                         };
 468                                 };
 469
 470                                 tcon1_out: port@1 {
 471                                         #address-cells = <1>;
 472                                         #size-cells = <0>;
 473                                         reg = <1>;
 474
 475                                         tcon1_out_hdmi: endpoint@1 {
 476                                                 reg = <1>;
 477                                                 remote-endpoint = <&hdmi_in_tcon1>;
 478                                         };
 479                                 };
 480                         };
 481                 };
 482
 483                 mmc0: mmc@1c0f000 {
 484                         compatible = "allwinner,sun8i-a83t-mmc",
 485                                      "allwinner,sun7i-a20-mmc";
 486                         reg = <0x01c0f000 0x1000>;
 487                         clocks = <&ccu CLK_BUS_MMC0>,
 488                                  <&ccu CLK_MMC0>,
 489                                  <&ccu CLK_MMC0_OUTPUT>,
 490                                  <&ccu CLK_MMC0_SAMPLE>;
 491                         clock-names = "ahb",
 492                                       "mmc",
 493                                       "output",
 494                                       "sample";
 495                         resets = <&ccu RST_BUS_MMC0>;
 496                         reset-names = "ahb";
 497                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 498                         status = "disabled";
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501                 };
 502
 503                 mmc1: mmc@1c10000 {
 504                         compatible = "allwinner,sun8i-a83t-mmc",
 505                                      "allwinner,sun7i-a20-mmc";
 506                         reg = <0x01c10000 0x1000>;
 507                         clocks = <&ccu CLK_BUS_MMC1>,
 508                                  <&ccu CLK_MMC1>,
 509                                  <&ccu CLK_MMC1_OUTPUT>,
 510                                  <&ccu CLK_MMC1_SAMPLE>;
 511                         clock-names = "ahb",
 512                                       "mmc",
 513                                       "output",
 514                                       "sample";
 515                         resets = <&ccu RST_BUS_MMC1>;
 516                         reset-names = "ahb";
 517                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 518                         pinctrl-names = "default";
 519                         pinctrl-0 = <&mmc1_pins>;
 520                         status = "disabled";
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                 };
 524
 525                 mmc2: mmc@1c11000 {
 526                         compatible = "allwinner,sun8i-a83t-emmc";
 527                         reg = <0x01c11000 0x1000>;
 528                         clocks = <&ccu CLK_BUS_MMC2>,
 529                                  <&ccu CLK_MMC2>,
 530                                  <&ccu CLK_MMC2_OUTPUT>,
 531                                  <&ccu CLK_MMC2_SAMPLE>;
 532                         clock-names = "ahb",
 533                                       "mmc",
 534                                       "output",
 535                                       "sample";
 536                         resets = <&ccu RST_BUS_MMC2>;
 537                         reset-names = "ahb";
 538                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 539                         status = "disabled";
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                 };
 543
 544                 sid: eeprom@1c14000 {
 545                         compatible = "allwinner,sun8i-a83t-sid";
 546                         reg = <0x1c14000 0x400>;
 547                 };
 548
 549                 usb_otg: usb@1c19000 {
 550                         compatible = "allwinner,sun8i-a83t-musb",
 551                                      "allwinner,sun8i-a33-musb";
 552                         reg = <0x01c19000 0x0400>;
 553                         clocks = <&ccu CLK_BUS_OTG>;
 554                         resets = <&ccu RST_BUS_OTG>;
 555                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 556                         interrupt-names = "mc";
 557                         phys = <&usbphy 0>;
 558                         phy-names = "usb";
 559                         extcon = <&usbphy 0>;
 560                         status = "disabled";
 561                 };
 562
 563                 usbphy: phy@1c19400 {
 564                         compatible = "allwinner,sun8i-a83t-usb-phy";
 565                         reg = <0x01c19400 0x10>,
 566                               <0x01c1a800 0x14>,
 567                               <0x01c1b800 0x14>;
 568                         reg-names = "phy_ctrl",
 569                                     "pmu1",
 570                                     "pmu2";
 571                         clocks = <&ccu CLK_USB_PHY0>,
 572                                  <&ccu CLK_USB_PHY1>,
 573                                  <&ccu CLK_USB_HSIC>,
 574                                  <&ccu CLK_USB_HSIC_12M>;
 575                         clock-names = "usb0_phy",
 576                                       "usb1_phy",
 577                                       "usb2_phy",
 578                                       "usb2_hsic_12M";
 579                         resets = <&ccu RST_USB_PHY0>,
 580                                  <&ccu RST_USB_PHY1>,
 581                                  <&ccu RST_USB_HSIC>;
 582                         reset-names = "usb0_reset",
 583                                       "usb1_reset",
 584                                       "usb2_reset";
 585                         status = "disabled";
 586                         #phy-cells = <1>;
 587                 };
 588
 589                 ehci0: usb@1c1a000 {
 590                         compatible = "allwinner,sun8i-a83t-ehci",
 591                                      "generic-ehci";
 592                         reg = <0x01c1a000 0x100>;
 593                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 594                         clocks = <&ccu CLK_BUS_EHCI0>;
 595                         resets = <&ccu RST_BUS_EHCI0>;
 596                         phys = <&usbphy 1>;
 597                         phy-names = "usb";
 598                         status = "disabled";
 599                 };
 600
 601                 ohci0: usb@1c1a400 {
 602                         compatible = "allwinner,sun8i-a83t-ohci",
 603                                      "generic-ohci";
 604                         reg = <0x01c1a400 0x100>;
 605                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 606                         clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
 607                         resets = <&ccu RST_BUS_OHCI0>;
 608                         phys = <&usbphy 1>;
 609                         phy-names = "usb";
 610                         status = "disabled";
 611                 };
 612
 613                 ehci1: usb@1c1b000 {
 614                         compatible = "allwinner,sun8i-a83t-ehci",
 615                                      "generic-ehci";
 616                         reg = <0x01c1b000 0x100>;
 617                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 618                         clocks = <&ccu CLK_BUS_EHCI1>;
 619                         resets = <&ccu RST_BUS_EHCI1>;
 620                         phys = <&usbphy 2>;
 621                         phy-names = "usb";
 622                         status = "disabled";
 623                 };
 624
 625                 ccu: clock@1c20000 {
 626                         compatible = "allwinner,sun8i-a83t-ccu";
 627                         reg = <0x01c20000 0x400>;
 628                         clocks = <&osc24M>, <&osc16Md512>;
 629                         clock-names = "hosc", "losc";
 630                         #clock-cells = <1>;
 631                         #reset-cells = <1>;
 632                 };
 633
 634                 pio: pinctrl@1c20800 {
 635                         compatible = "allwinner,sun8i-a83t-pinctrl";
 636                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 638                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 639                         reg = <0x01c20800 0x400>;
 640                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
 641                         clock-names = "apb", "hosc", "losc";
 642                         gpio-controller;
 643                         interrupt-controller;
 644                         #interrupt-cells = <3>;
 645                         #gpio-cells = <3>;
 646
 647                         emac_rgmii_pins: emac-rgmii-pins {
 648                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 649                                        "PD11", "PD12", "PD13", "PD14", "PD18",
 650                                        "PD19", "PD21", "PD22", "PD23";
 651                                 function = "gmac";
 652                                 /*
 653                                  * data lines in RGMII mode use DDR mode
 654                                  * and need a higher signal drive strength
 655                                  */
 656                                 drive-strength = <40>;
 657                         };
 658
 659                         hdmi_pins: hdmi-pins {
 660                                 pins = "PH6", "PH7", "PH8";
 661                                 function = "hdmi";
 662                         };
 663
 664                         i2c0_pins: i2c0-pins {
 665                                 pins = "PH0", "PH1";
 666                                 function = "i2c0";
 667                         };
 668
 669                         i2c1_pins: i2c1-pins {
 670                                 pins = "PH2", "PH3";
 671                                 function = "i2c1";
 672                         };
 673
 674                         i2c2_ph_pins: i2c2-ph-pins {
 675                                 pins = "PH4", "PH5";
 676                                 function = "i2c2";
 677                         };
 678
 679                         i2s1_pins: i2s1-pins {
 680                                 /* I2S1 does not have external MCLK pin */
 681                                 pins = "PG10", "PG11", "PG12", "PG13";
 682                                 function = "i2s1";
 683                         };
 684
 685                         lcd_lvds_pins: lcd-lvds-pins {
 686                                 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
 687                                        "PD23", "PD24", "PD25", "PD26", "PD27";
 688                                 function = "lvds0";
 689                         };
 690
 691                         mmc0_pins: mmc0-pins {
 692                                 pins = "PF0", "PF1", "PF2",
 693                                        "PF3", "PF4", "PF5";
 694                                 function = "mmc0";
 695                                 drive-strength = <30>;
 696                                 bias-pull-up;
 697                         };
 698
 699                         mmc1_pins: mmc1-pins {
 700                                 pins = "PG0", "PG1", "PG2",
 701                                        "PG3", "PG4", "PG5";
 702                                 function = "mmc1";
 703                                 drive-strength = <30>;
 704                                 bias-pull-up;
 705                         };
 706
 707                         mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
 708                                 pins = "PC5", "PC6", "PC8", "PC9",
 709                                        "PC10", "PC11", "PC12", "PC13",
 710                                        "PC14", "PC15", "PC16";
 711                                 function = "mmc2";
 712                                 drive-strength = <30>;
 713                                 bias-pull-up;
 714                         };
 715
 716                         pwm_pin: pwm-pin {
 717                                 pins = "PD28";
 718                                 function = "pwm";
 719                         };
 720
 721                         spdif_tx_pin: spdif-tx-pin {
 722                                 pins = "PE18";
 723                                 function = "spdif";
 724                         };
 725
 726                         uart0_pb_pins: uart0-pb-pins {
 727                                 pins = "PB9", "PB10";
 728                                 function = "uart0";
 729                         };
 730
 731                         uart0_pf_pins: uart0-pf-pins {
 732                                 pins = "PF2", "PF4";
 733                                 function = "uart0";
 734                         };
 735
 736                         uart1_pins: uart1-pins {
 737                                 pins = "PG6", "PG7";
 738                                 function = "uart1";
 739                         };
 740
 741                         uart1_rts_cts_pins: uart1-rts-cts-pins {
 742                                 pins = "PG8", "PG9";
 743                                 function = "uart1";
 744                         };
 745                 };
 746
 747                 timer@1c20c00 {
 748                         compatible = "allwinner,sun4i-a10-timer";
 749                         reg = <0x01c20c00 0xa0>;
 750                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&osc24M>;
 753                 };
 754
 755                 watchdog@1c20ca0 {
 756                         compatible = "allwinner,sun6i-a31-wdt";
 757                         reg = <0x01c20ca0 0x20>;
 758                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&osc24M>;
 760                 };
 761
 762                 spdif: spdif@1c21000 {
 763                         #sound-dai-cells = <0>;
 764                         compatible = "allwinner,sun8i-a83t-spdif",
 765                                      "allwinner,sun8i-h3-spdif";
 766                         reg = <0x01c21000 0x400>;
 767                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 768                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 769                         resets = <&ccu RST_BUS_SPDIF>;
 770                         clock-names = "apb", "spdif";
 771                         dmas = <&dma 2>;
 772                         dma-names = "tx";
 773                         pinctrl-names = "default";
 774                         pinctrl-0 = <&spdif_tx_pin>;
 775                         status = "disabled";
 776                 };
 777
 778                 i2s0: i2s@1c22000 {
 779                         #sound-dai-cells = <0>;
 780                         compatible = "allwinner,sun8i-a83t-i2s";
 781                         reg = <0x01c22000 0x400>;
 782                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 783                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 784                         clock-names = "apb", "mod";
 785                         dmas = <&dma 3>, <&dma 3>;
 786                         resets = <&ccu RST_BUS_I2S0>;
 787                         dma-names = "rx", "tx";
 788                         status = "disabled";
 789                 };
 790
 791                 i2s1: i2s@1c22400 {
 792                         #sound-dai-cells = <0>;
 793                         compatible = "allwinner,sun8i-a83t-i2s";
 794                         reg = <0x01c22400 0x400>;
 795                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 796                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 797                         clock-names = "apb", "mod";
 798                         dmas = <&dma 4>, <&dma 4>;
 799                         resets = <&ccu RST_BUS_I2S1>;
 800                         dma-names = "rx", "tx";
 801                         pinctrl-names = "default";
 802                         pinctrl-0 = <&i2s1_pins>;
 803                         status = "disabled";
 804                 };
 805
 806                 i2s2: i2s@1c22800 {
 807                         #sound-dai-cells = <0>;
 808                         compatible = "allwinner,sun8i-a83t-i2s";
 809                         reg = <0x01c22800 0x400>;
 810                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
 812                         clock-names = "apb", "mod";
 813                         dmas = <&dma 27>;
 814                         resets = <&ccu RST_BUS_I2S2>;
 815                         dma-names = "tx";
 816                         status = "disabled";
 817                 };
 818
 819                 pwm: pwm@1c21400 {
 820                         compatible = "allwinner,sun8i-a83t-pwm",
 821                                      "allwinner,sun8i-h3-pwm";
 822                         reg = <0x01c21400 0x400>;
 823                         clocks = <&osc24M>;
 824                         #pwm-cells = <3>;
 825                         status = "disabled";
 826                 };
 827
 828                 uart0: serial@1c28000 {
 829                         compatible = "snps,dw-apb-uart";
 830                         reg = <0x01c28000 0x400>;
 831                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 832                         reg-shift = <2>;
 833                         reg-io-width = <4>;
 834                         clocks = <&ccu CLK_BUS_UART0>;
 835                         resets = <&ccu RST_BUS_UART0>;
 836                         status = "disabled";
 837                 };
 838
 839                 uart1: serial@1c28400 {
 840                         compatible = "snps,dw-apb-uart";
 841                         reg = <0x01c28400 0x400>;
 842                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 843                         reg-shift = <2>;
 844                         reg-io-width = <4>;
 845                         clocks = <&ccu CLK_BUS_UART1>;
 846                         resets = <&ccu RST_BUS_UART1>;
 847                         status = "disabled";
 848                 };
 849
 850                 i2c0: i2c@1c2ac00 {
 851                         compatible = "allwinner,sun8i-a83t-i2c",
 852                                      "allwinner,sun6i-a31-i2c";
 853                         reg = <0x01c2ac00 0x400>;
 854                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 855                         clocks = <&ccu CLK_BUS_I2C0>;
 856                         resets = <&ccu RST_BUS_I2C0>;
 857                         pinctrl-names = "default";
 858                         pinctrl-0 = <&i2c0_pins>;
 859                         status = "disabled";
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                 };
 863
 864                 i2c1: i2c@1c2b000 {
 865                         compatible = "allwinner,sun8i-a83t-i2c",
 866                                      "allwinner,sun6i-a31-i2c";
 867                         reg = <0x01c2b000 0x400>;
 868                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&ccu CLK_BUS_I2C1>;
 870                         resets = <&ccu RST_BUS_I2C1>;
 871                         pinctrl-names = "default";
 872                         pinctrl-0 = <&i2c1_pins>;
 873                         status = "disabled";
 874                         #address-cells = <1>;
 875                         #size-cells = <0>;
 876                 };
 877
 878                 i2c2: i2c@1c2b400 {
 879                         compatible = "allwinner,sun8i-a83t-i2c",
 880                                      "allwinner,sun6i-a31-i2c";
 881                         reg = <0x01c2b400 0x400>;
 882                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 883                         clocks = <&ccu CLK_BUS_I2C2>;
 884                         resets = <&ccu RST_BUS_I2C2>;
 885                         status = "disabled";
 886                         #address-cells = <1>;
 887                         #size-cells = <0>;
 888                 };
 889
 890                 emac: ethernet@1c30000 {
 891                         compatible = "allwinner,sun8i-a83t-emac";
 892                         syscon = <&syscon>;
 893                         reg = <0x01c30000 0x104>;
 894                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 895                         interrupt-names = "macirq";
 896                         resets = <&ccu 13>;
 897                         reset-names = "stmmaceth";
 898                         clocks = <&ccu 27>;
 899                         clock-names = "stmmaceth";
 900                         status = "disabled";
 901
 902                         mdio: mdio {
 903                                 compatible = "snps,dwmac-mdio";
 904                                 #address-cells = <1>;
 905                                 #size-cells = <0>;
 906                         };
 907                 };
 908
 909                 gic: interrupt-controller@1c81000 {
 910                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 911                         reg = <0x01c81000 0x1000>,
 912                               <0x01c82000 0x2000>,
 913                               <0x01c84000 0x2000>,
 914                               <0x01c86000 0x2000>;
 915                         interrupt-controller;
 916                         #interrupt-cells = <3>;
 917                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 918                 };
 919
 920                 hdmi: hdmi@1ee0000 {
 921                         compatible = "allwinner,sun8i-a83t-dw-hdmi";
 922                         reg = <0x01ee0000 0x10000>;
 923                         reg-io-width = <1>;
 924                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 925                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 926                                  <&ccu CLK_HDMI>;
 927                         clock-names = "iahb", "isfr", "tmds";
 928                         resets = <&ccu RST_BUS_HDMI1>;
 929                         reset-names = "ctrl";
 930                         phys = <&hdmi_phy>;
 931                         phy-names = "hdmi-phy";
 932                         pinctrl-names = "default";
 933                         pinctrl-0 = <&hdmi_pins>;
 934                         status = "disabled";
 935
 936                         ports {
 937                                 #address-cells = <1>;
 938                                 #size-cells = <0>;
 939
 940                                 hdmi_in: port@0 {
 941                                         reg = <0>;
 942
 943                                         hdmi_in_tcon1: endpoint {
 944                                                 remote-endpoint = <&tcon1_out_hdmi>;
 945                                         };
 946                                 };
 947
 948                                 hdmi_out: port@1 {
 949                                         reg = <1>;
 950                                 };
 951                         };
 952                 };
 953
 954                 hdmi_phy: hdmi-phy@1ef0000 {
 955                         compatible = "allwinner,sun8i-a83t-hdmi-phy";
 956                         reg = <0x01ef0000 0x10000>;
 957                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 958                         clock-names = "bus", "mod";
 959                         resets = <&ccu RST_BUS_HDMI0>;
 960                         reset-names = "phy";
 961                         #phy-cells = <0>;
 962                 };
 963
 964                 r_intc: interrupt-controller@1f00c00 {
 965                         compatible = "allwinner,sun8i-a83t-r-intc",
 966                                      "allwinner,sun6i-a31-r-intc";
 967                         interrupt-controller;
 968                         #interrupt-cells = <2>;
 969                         reg = <0x01f00c00 0x400>;
 970                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 971                 };
 972
 973                 r_ccu: clock@1f01400 {
 974                         compatible = "allwinner,sun8i-a83t-r-ccu";
 975                         reg = <0x01f01400 0x400>;
 976                         clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
 977                                  <&ccu 6>;
 978                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 979                         #clock-cells = <1>;
 980                         #reset-cells = <1>;
 981                 };
 982
 983                 r_cpucfg@1f01c00 {
 984                         compatible = "allwinner,sun8i-a83t-r-cpucfg";
 985                         reg = <0x1f01c00 0x400>;
 986                 };
 987
 988                 r_cir: ir@1f02000 {
 989                         compatible = "allwinner,sun8i-a83t-ir",
 990                                 "allwinner,sun5i-a13-ir";
 991                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 992                         clock-names = "apb", "ir";
 993                         resets = <&r_ccu RST_APB0_IR>;
 994                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 995                         reg = <0x01f02000 0x400>;
 996                         pinctrl-names = "default";
 997                         pinctrl-0 = <&r_cir_pin>;
 998                         status = "disabled";
 999                 };
1000
1001                 r_pio: pinctrl@1f02c00 {
1002                         compatible = "allwinner,sun8i-a83t-r-pinctrl";
1003                         reg = <0x01f02c00 0x400>;
1004                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1005                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1006                                  <&osc16Md512>;
1007                         clock-names = "apb", "hosc", "losc";
1008                         gpio-controller;
1009                         #gpio-cells = <3>;
1010                         interrupt-controller;
1011                         #interrupt-cells = <3>;
1012
1013                         r_cir_pin: r-cir-pin {
1014                                 pins = "PL12";
1015                                 function = "s_cir_rx";
1016                         };
1017
1018                         r_rsb_pins: r-rsb-pins {
1019                                 pins = "PL0", "PL1";
1020                                 function = "s_rsb";
1021                                 drive-strength = <20>;
1022                                 bias-pull-up;
1023                         };
1024                 };
1025
1026                 r_rsb: rsb@1f03400 {
1027                         compatible = "allwinner,sun8i-a83t-rsb",
1028                                      "allwinner,sun8i-a23-rsb";
1029                         reg = <0x01f03400 0x400>;
1030                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1031                         clocks = <&r_ccu CLK_APB0_RSB>;
1032                         clock-frequency = <3000000>;
1033                         resets = <&r_ccu RST_APB0_RSB>;
1034                         pinctrl-names = "default";
1035                         pinctrl-0 = <&r_rsb_pins>;
1036                         status = "disabled";
1037                         #address-cells = <1>;
1038                         #size-cells = <0>;
1039                 };
1040         };
1041 };