2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
87 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 next-level-cache = <&L2>;
95 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 next-level-cache = <&L2>;
103 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 next-level-cache = <&L2>;
111 compatible = "arm,cortex-a53";
114 enable-method = "psci";
115 next-level-cache = <&L2>;
119 compatible = "cache";
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "ext-osc32k";
146 compatible = "arm,psci-0.2";
151 compatible = "simple-audio-card";
152 simple-audio-card,name = "sun50i-a64-audio";
153 simple-audio-card,format = "i2s";
154 simple-audio-card,frame-master = <&cpudai>;
155 simple-audio-card,bitclock-master = <&cpudai>;
156 simple-audio-card,mclk-fs = <128>;
157 simple-audio-card,aux-devs = <&codec_analog>;
158 simple-audio-card,routing =
159 "Left DAC", "AIF1 Slot 0 Left",
160 "Right DAC", "AIF1 Slot 0 Right",
161 "AIF1 Slot 0 Left ADC", "Left ADC",
162 "AIF1 Slot 0 Right ADC", "Right ADC";
165 cpudai: simple-audio-card,cpu {
169 link_codec: simple-audio-card,codec {
170 sound-dai = <&codec>;
175 compatible = "simple-audio-card";
176 simple-audio-card,name = "On-board SPDIF";
178 simple-audio-card,cpu {
179 sound-dai = <&spdif>;
182 simple-audio-card,codec {
183 sound-dai = <&spdif_out>;
187 spdif_out: spdif-out {
188 #sound-dai-cells = <0>;
189 compatible = "linux,spdif-dit";
193 compatible = "arm,armv8-timer";
194 allwinner,erratum-unknown1;
195 interrupts = <GIC_PPI 13
196 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
198 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
200 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
202 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 compatible = "simple-bus";
207 #address-cells = <1>;
212 compatible = "allwinner,sun50i-a64-de2";
213 reg = <0x1000000 0x400000>;
214 allwinner,sram = <&de2_sram 1>;
215 #address-cells = <1>;
217 ranges = <0 0x1000000 0x400000>;
219 display_clocks: clock@0 {
220 compatible = "allwinner,sun50i-a64-de2-clk";
221 reg = <0x0 0x100000>;
222 clocks = <&ccu CLK_BUS_DE>,
226 resets = <&ccu RST_BUS_DE>;
231 mixer0: mixer@100000 {
232 compatible = "allwinner,sun50i-a64-de2-mixer-0";
233 reg = <0x100000 0x100000>;
234 clocks = <&display_clocks CLK_BUS_MIXER0>,
235 <&display_clocks CLK_MIXER0>;
238 resets = <&display_clocks RST_MIXER0>;
241 #address-cells = <1>;
245 #address-cells = <1>;
249 mixer0_out_tcon0: endpoint@0 {
251 remote-endpoint = <&tcon0_in_mixer0>;
254 mixer0_out_tcon1: endpoint@1 {
256 remote-endpoint = <&tcon1_in_mixer0>;
262 mixer1: mixer@200000 {
263 compatible = "allwinner,sun50i-a64-de2-mixer-1";
264 reg = <0x200000 0x100000>;
265 clocks = <&display_clocks CLK_BUS_MIXER1>,
266 <&display_clocks CLK_MIXER1>;
269 resets = <&display_clocks RST_MIXER1>;
272 #address-cells = <1>;
276 #address-cells = <1>;
280 mixer1_out_tcon0: endpoint@0 {
282 remote-endpoint = <&tcon0_in_mixer1>;
285 mixer1_out_tcon1: endpoint@1 {
287 remote-endpoint = <&tcon1_in_mixer1>;
294 syscon: syscon@1c00000 {
295 compatible = "allwinner,sun50i-a64-system-control";
296 reg = <0x01c00000 0x1000>;
297 #address-cells = <1>;
302 compatible = "mmio-sram";
303 reg = <0x00018000 0x28000>;
304 #address-cells = <1>;
306 ranges = <0 0x00018000 0x28000>;
308 de2_sram: sram-section@0 {
309 compatible = "allwinner,sun50i-a64-sram-c";
310 reg = <0x0000 0x28000>;
314 sram_c1: sram@1d00000 {
315 compatible = "mmio-sram";
316 reg = <0x01d00000 0x40000>;
317 #address-cells = <1>;
319 ranges = <0 0x01d00000 0x40000>;
321 ve_sram: sram-section@0 {
322 compatible = "allwinner,sun50i-a64-sram-c1",
323 "allwinner,sun4i-a10-sram-c1";
324 reg = <0x000000 0x40000>;
329 dma: dma-controller@1c02000 {
330 compatible = "allwinner,sun50i-a64-dma";
331 reg = <0x01c02000 0x1000>;
332 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&ccu CLK_BUS_DMA>;
336 resets = <&ccu RST_BUS_DMA>;
340 tcon0: lcd-controller@1c0c000 {
341 compatible = "allwinner,sun50i-a64-tcon-lcd",
342 "allwinner,sun8i-a83t-tcon-lcd";
343 reg = <0x01c0c000 0x1000>;
344 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
346 clock-names = "ahb", "tcon-ch0";
347 clock-output-names = "tcon-pixel-clock";
349 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
350 reset-names = "lcd", "lvds";
353 #address-cells = <1>;
357 #address-cells = <1>;
361 tcon0_in_mixer0: endpoint@0 {
363 remote-endpoint = <&mixer0_out_tcon0>;
366 tcon0_in_mixer1: endpoint@1 {
368 remote-endpoint = <&mixer1_out_tcon0>;
373 #address-cells = <1>;
380 tcon1: lcd-controller@1c0d000 {
381 compatible = "allwinner,sun50i-a64-tcon-tv",
382 "allwinner,sun8i-a83t-tcon-tv";
383 reg = <0x01c0d000 0x1000>;
384 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
386 clock-names = "ahb", "tcon-ch1";
387 resets = <&ccu RST_BUS_TCON1>;
391 #address-cells = <1>;
395 #address-cells = <1>;
399 tcon1_in_mixer0: endpoint@0 {
401 remote-endpoint = <&mixer0_out_tcon1>;
404 tcon1_in_mixer1: endpoint@1 {
406 remote-endpoint = <&mixer1_out_tcon1>;
411 #address-cells = <1>;
415 tcon1_out_hdmi: endpoint@1 {
417 remote-endpoint = <&hdmi_in_tcon1>;
423 video-codec@1c0e000 {
424 compatible = "allwinner,sun50i-a64-video-engine";
425 reg = <0x01c0e000 0x1000>;
426 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
428 clock-names = "ahb", "mod", "ram";
429 resets = <&ccu RST_BUS_VE>;
430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
431 allwinner,sram = <&ve_sram 1>;
435 compatible = "allwinner,sun50i-a64-mmc";
436 reg = <0x01c0f000 0x1000>;
437 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
438 clock-names = "ahb", "mmc";
439 resets = <&ccu RST_BUS_MMC0>;
441 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
442 max-frequency = <150000000>;
444 #address-cells = <1>;
449 compatible = "allwinner,sun50i-a64-mmc";
450 reg = <0x01c10000 0x1000>;
451 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
452 clock-names = "ahb", "mmc";
453 resets = <&ccu RST_BUS_MMC1>;
455 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
456 max-frequency = <150000000>;
458 #address-cells = <1>;
463 compatible = "allwinner,sun50i-a64-emmc";
464 reg = <0x01c11000 0x1000>;
465 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
466 clock-names = "ahb", "mmc";
467 resets = <&ccu RST_BUS_MMC2>;
469 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
470 max-frequency = <200000000>;
472 #address-cells = <1>;
476 sid: eeprom@1c14000 {
477 compatible = "allwinner,sun50i-a64-sid";
478 reg = <0x1c14000 0x400>;
481 usb_otg: usb@1c19000 {
482 compatible = "allwinner,sun8i-a33-musb";
483 reg = <0x01c19000 0x0400>;
484 clocks = <&ccu CLK_BUS_OTG>;
485 resets = <&ccu RST_BUS_OTG>;
486 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "mc";
490 extcon = <&usbphy 0>;
495 usbphy: phy@1c19400 {
496 compatible = "allwinner,sun50i-a64-usb-phy";
497 reg = <0x01c19400 0x14>,
500 reg-names = "phy_ctrl",
503 clocks = <&ccu CLK_USB_PHY0>,
505 clock-names = "usb0_phy",
507 resets = <&ccu RST_USB_PHY0>,
509 reset-names = "usb0_reset",
516 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
517 reg = <0x01c1a000 0x100>;
518 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&ccu CLK_BUS_OHCI0>,
520 <&ccu CLK_BUS_EHCI0>,
521 <&ccu CLK_USB_OHCI0>;
522 resets = <&ccu RST_BUS_OHCI0>,
523 <&ccu RST_BUS_EHCI0>;
528 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
529 reg = <0x01c1a400 0x100>;
530 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&ccu CLK_BUS_OHCI0>,
532 <&ccu CLK_USB_OHCI0>;
533 resets = <&ccu RST_BUS_OHCI0>;
538 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
539 reg = <0x01c1b000 0x100>;
540 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&ccu CLK_BUS_OHCI1>,
542 <&ccu CLK_BUS_EHCI1>,
543 <&ccu CLK_USB_OHCI1>;
544 resets = <&ccu RST_BUS_OHCI1>,
545 <&ccu RST_BUS_EHCI1>;
552 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
553 reg = <0x01c1b400 0x100>;
554 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&ccu CLK_BUS_OHCI1>,
556 <&ccu CLK_USB_OHCI1>;
557 resets = <&ccu RST_BUS_OHCI1>;
564 compatible = "allwinner,sun50i-a64-ccu";
565 reg = <0x01c20000 0x400>;
566 clocks = <&osc24M>, <&rtc 0>;
567 clock-names = "hosc", "losc";
572 pio: pinctrl@1c20800 {
573 compatible = "allwinner,sun50i-a64-pinctrl";
574 reg = <0x01c20800 0x400>;
575 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&ccu 58>, <&osc24M>, <&rtc 0>;
579 clock-names = "apb", "hosc", "losc";
582 interrupt-controller;
583 #interrupt-cells = <3>;
586 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
587 "PE7", "PE8", "PE9", "PE10", "PE11";
592 csi_mclk_pin: csi-mclk-pin {
597 i2c0_pins: i2c0-pins {
602 i2c1_pins: i2c1-pins {
608 lcd_rgb666_pins: lcd-rgb666-pins {
609 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
610 "PD5", "PD6", "PD7", "PD8", "PD9",
611 "PD10", "PD11", "PD12", "PD13",
612 "PD14", "PD15", "PD16", "PD17",
613 "PD18", "PD19", "PD20", "PD21";
617 mmc0_pins: mmc0-pins {
618 pins = "PF0", "PF1", "PF2", "PF3",
621 drive-strength = <30>;
625 mmc1_pins: mmc1-pins {
626 pins = "PG0", "PG1", "PG2", "PG3",
629 drive-strength = <30>;
633 mmc2_pins: mmc2-pins {
634 pins = "PC5", "PC6", "PC8", "PC9",
635 "PC10","PC11", "PC12", "PC13",
636 "PC14", "PC15", "PC16";
638 drive-strength = <30>;
642 mmc2_ds_pin: mmc2-ds-pin {
645 drive-strength = <30>;
654 rmii_pins: rmii-pins {
655 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
656 "PD18", "PD19", "PD20", "PD22", "PD23";
658 drive-strength = <40>;
661 rgmii_pins: rgmii-pins {
662 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
663 "PD13", "PD15", "PD16", "PD17", "PD18",
664 "PD19", "PD20", "PD21", "PD22", "PD23";
666 drive-strength = <40>;
669 spdif_tx_pin: spdif-tx-pin {
674 spi0_pins: spi0-pins {
675 pins = "PC0", "PC1", "PC2", "PC3";
679 spi1_pins: spi1-pins {
680 pins = "PD0", "PD1", "PD2", "PD3";
684 uart0_pb_pins: uart0-pb-pins {
689 uart1_pins: uart1-pins {
694 uart1_rts_cts_pins: uart1-rts-cts-pins {
699 uart2_pins: uart2-pins {
704 uart3_pins: uart3-pins {
709 uart4_pins: uart4-pins {
714 uart4_rts_cts_pins: uart4-rts-cts-pins {
720 spdif: spdif@1c21000 {
721 #sound-dai-cells = <0>;
722 compatible = "allwinner,sun50i-a64-spdif",
723 "allwinner,sun8i-h3-spdif";
724 reg = <0x01c21000 0x400>;
725 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
727 resets = <&ccu RST_BUS_SPDIF>;
728 clock-names = "apb", "spdif";
731 pinctrl-names = "default";
732 pinctrl-0 = <&spdif_tx_pin>;
736 lradc: lradc@1c21800 {
737 compatible = "allwinner,sun50i-a64-lradc",
738 "allwinner,sun8i-a83t-r-lradc";
739 reg = <0x01c21800 0x400>;
740 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
745 #sound-dai-cells = <0>;
746 compatible = "allwinner,sun50i-a64-i2s",
747 "allwinner,sun8i-h3-i2s";
748 reg = <0x01c22000 0x400>;
749 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
750 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
751 clock-names = "apb", "mod";
752 resets = <&ccu RST_BUS_I2S0>;
753 dma-names = "rx", "tx";
754 dmas = <&dma 3>, <&dma 3>;
759 #sound-dai-cells = <0>;
760 compatible = "allwinner,sun50i-a64-i2s",
761 "allwinner,sun8i-h3-i2s";
762 reg = <0x01c22400 0x400>;
763 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
765 clock-names = "apb", "mod";
766 resets = <&ccu RST_BUS_I2S1>;
767 dma-names = "rx", "tx";
768 dmas = <&dma 4>, <&dma 4>;
773 #sound-dai-cells = <0>;
774 compatible = "allwinner,sun50i-a64-codec-i2s";
775 reg = <0x01c22c00 0x200>;
776 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
778 clock-names = "apb", "mod";
779 resets = <&ccu RST_BUS_CODEC>;
780 dmas = <&dma 15>, <&dma 15>;
781 dma-names = "rx", "tx";
785 codec: codec@1c22e00 {
786 #sound-dai-cells = <0>;
787 compatible = "allwinner,sun8i-a33-codec";
788 reg = <0x01c22e00 0x600>;
789 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
791 clock-names = "bus", "mod";
795 uart0: serial@1c28000 {
796 compatible = "snps,dw-apb-uart";
797 reg = <0x01c28000 0x400>;
798 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&ccu CLK_BUS_UART0>;
802 resets = <&ccu RST_BUS_UART0>;
806 uart1: serial@1c28400 {
807 compatible = "snps,dw-apb-uart";
808 reg = <0x01c28400 0x400>;
809 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&ccu CLK_BUS_UART1>;
813 resets = <&ccu RST_BUS_UART1>;
817 uart2: serial@1c28800 {
818 compatible = "snps,dw-apb-uart";
819 reg = <0x01c28800 0x400>;
820 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&ccu CLK_BUS_UART2>;
824 resets = <&ccu RST_BUS_UART2>;
828 uart3: serial@1c28c00 {
829 compatible = "snps,dw-apb-uart";
830 reg = <0x01c28c00 0x400>;
831 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&ccu CLK_BUS_UART3>;
835 resets = <&ccu RST_BUS_UART3>;
839 uart4: serial@1c29000 {
840 compatible = "snps,dw-apb-uart";
841 reg = <0x01c29000 0x400>;
842 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&ccu CLK_BUS_UART4>;
846 resets = <&ccu RST_BUS_UART4>;
851 compatible = "allwinner,sun6i-a31-i2c";
852 reg = <0x01c2ac00 0x400>;
853 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&ccu CLK_BUS_I2C0>;
855 resets = <&ccu RST_BUS_I2C0>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&i2c0_pins>;
859 #address-cells = <1>;
864 compatible = "allwinner,sun6i-a31-i2c";
865 reg = <0x01c2b000 0x400>;
866 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&ccu CLK_BUS_I2C1>;
868 resets = <&ccu RST_BUS_I2C1>;
869 pinctrl-names = "default";
870 pinctrl-0 = <&i2c1_pins>;
872 #address-cells = <1>;
877 compatible = "allwinner,sun6i-a31-i2c";
878 reg = <0x01c2b400 0x400>;
879 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&ccu CLK_BUS_I2C2>;
881 resets = <&ccu RST_BUS_I2C2>;
883 #address-cells = <1>;
889 compatible = "allwinner,sun8i-h3-spi";
890 reg = <0x01c68000 0x1000>;
891 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
893 clock-names = "ahb", "mod";
894 dmas = <&dma 23>, <&dma 23>;
895 dma-names = "rx", "tx";
896 pinctrl-names = "default";
897 pinctrl-0 = <&spi0_pins>;
898 resets = <&ccu RST_BUS_SPI0>;
901 #address-cells = <1>;
906 compatible = "allwinner,sun8i-h3-spi";
907 reg = <0x01c69000 0x1000>;
908 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
910 clock-names = "ahb", "mod";
911 dmas = <&dma 24>, <&dma 24>;
912 dma-names = "rx", "tx";
913 pinctrl-names = "default";
914 pinctrl-0 = <&spi1_pins>;
915 resets = <&ccu RST_BUS_SPI1>;
918 #address-cells = <1>;
922 emac: ethernet@1c30000 {
923 compatible = "allwinner,sun50i-a64-emac";
925 reg = <0x01c30000 0x10000>;
926 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
927 interrupt-names = "macirq";
928 resets = <&ccu RST_BUS_EMAC>;
929 reset-names = "stmmaceth";
930 clocks = <&ccu CLK_BUS_EMAC>;
931 clock-names = "stmmaceth";
935 compatible = "snps,dwmac-mdio";
936 #address-cells = <1>;
942 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400";
943 reg = <0x01c40000 0x10000>;
944 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
951 interrupt-names = "gp",
958 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
959 clock-names = "bus", "core";
960 resets = <&ccu RST_BUS_GPU>;
963 gic: interrupt-controller@1c81000 {
964 compatible = "arm,gic-400";
965 reg = <0x01c81000 0x1000>,
969 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
970 interrupt-controller;
971 #interrupt-cells = <3>;
975 compatible = "allwinner,sun50i-a64-pwm",
976 "allwinner,sun5i-a13-pwm";
977 reg = <0x01c21400 0x400>;
979 pinctrl-names = "default";
980 pinctrl-0 = <&pwm_pin>;
986 compatible = "allwinner,sun50i-a64-csi";
987 reg = <0x01cb0000 0x1000>;
988 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&ccu CLK_BUS_CSI>,
992 clock-names = "bus", "mod", "ram";
993 resets = <&ccu RST_BUS_CSI>;
994 pinctrl-names = "default";
995 pinctrl-0 = <&csi_pins>;
1000 compatible = "allwinner,sun50i-a64-dw-hdmi",
1001 "allwinner,sun8i-a83t-dw-hdmi";
1002 reg = <0x01ee0000 0x10000>;
1004 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1005 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1007 clock-names = "iahb", "isfr", "tmds";
1008 resets = <&ccu RST_BUS_HDMI1>;
1009 reset-names = "ctrl";
1012 status = "disabled";
1015 #address-cells = <1>;
1021 hdmi_in_tcon1: endpoint {
1022 remote-endpoint = <&tcon1_out_hdmi>;
1032 hdmi_phy: hdmi-phy@1ef0000 {
1033 compatible = "allwinner,sun50i-a64-hdmi-phy";
1034 reg = <0x01ef0000 0x10000>;
1035 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
1037 clock-names = "bus", "mod", "pll-0";
1038 resets = <&ccu RST_BUS_HDMI0>;
1039 reset-names = "phy";
1044 compatible = "allwinner,sun50i-a64-rtc",
1045 "allwinner,sun8i-h3-rtc";
1046 reg = <0x01f00000 0x400>;
1047 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1049 clock-output-names = "osc32k", "osc32k-out", "iosc";
1054 r_intc: interrupt-controller@1f00c00 {
1055 compatible = "allwinner,sun50i-a64-r-intc",
1056 "allwinner,sun6i-a31-r-intc";
1057 interrupt-controller;
1058 #interrupt-cells = <2>;
1059 reg = <0x01f00c00 0x400>;
1060 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1063 r_ccu: clock@1f01400 {
1064 compatible = "allwinner,sun50i-a64-r-ccu";
1065 reg = <0x01f01400 0x100>;
1066 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 11>;
1067 clock-names = "hosc", "losc", "iosc", "pll-periph";
1072 codec_analog: codec-analog@1f015c0 {
1073 compatible = "allwinner,sun50i-a64-codec-analog";
1074 reg = <0x01f015c0 0x4>;
1075 status = "disabled";
1078 r_i2c: i2c@1f02400 {
1079 compatible = "allwinner,sun50i-a64-i2c",
1080 "allwinner,sun6i-a31-i2c";
1081 reg = <0x01f02400 0x400>;
1082 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&r_ccu CLK_APB0_I2C>;
1084 resets = <&r_ccu RST_APB0_I2C>;
1085 status = "disabled";
1086 #address-cells = <1>;
1091 compatible = "allwinner,sun50i-a64-ir",
1092 "allwinner,sun6i-a31-ir";
1093 reg = <0x01f02000 0x400>;
1094 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1095 clock-names = "apb", "ir";
1096 resets = <&r_ccu RST_APB0_IR>;
1097 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1098 pinctrl-names = "default";
1099 pinctrl-0 = <&r_ir_rx_pin>;
1100 status = "disabled";
1103 r_pwm: pwm@1f03800 {
1104 compatible = "allwinner,sun50i-a64-pwm",
1105 "allwinner,sun5i-a13-pwm";
1106 reg = <0x01f03800 0x400>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&r_pwm_pin>;
1111 status = "disabled";
1114 r_pio: pinctrl@1f02c00 {
1115 compatible = "allwinner,sun50i-a64-r-pinctrl";
1116 reg = <0x01f02c00 0x400>;
1117 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1118 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
1119 clock-names = "apb", "hosc", "losc";
1122 interrupt-controller;
1123 #interrupt-cells = <3>;
1125 r_i2c_pl89_pins: r-i2c-pl89-pins {
1126 pins = "PL8", "PL9";
1130 r_ir_rx_pin: r-ir-rx-pin {
1132 function = "s_cir_rx";
1135 r_pwm_pin: r-pwm-pin {
1140 r_rsb_pins: r-rsb-pins {
1141 pins = "PL0", "PL1";
1146 r_rsb: rsb@1f03400 {
1147 compatible = "allwinner,sun8i-a23-rsb";
1148 reg = <0x01f03400 0x400>;
1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&r_ccu 6>;
1151 clock-frequency = <3000000>;
1152 resets = <&r_ccu 2>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&r_rsb_pins>;
1155 status = "disabled";
1156 #address-cells = <1>;
1160 wdt0: watchdog@1c20ca0 {
1161 compatible = "allwinner,sun50i-a64-wdt",
1162 "allwinner,sun6i-a31-wdt";
1163 reg = <0x01c20ca0 0x20>;
1164 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;