src/arm64/amlogic/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         soc {
  17                 usb0: usb@c9000000 {
  18                         status = "disabled";
  19                         compatible = "amlogic,meson-gxl-dwc3";
  20                         #address-cells = <2>;
  21                         #size-cells = <2>;
  22                         ranges;
  23
  24                         clocks = <&clkc CLKID_USB>;
  25                         clock-names = "usb_general";
  26                         resets = <&reset RESET_USB_OTG>;
  27                         reset-names = "usb_otg";
  28
  29                         dwc3: dwc3@c9000000 {
  30                                 compatible = "snps,dwc3";
  31                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  32                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  33                                 dr_mode = "host";
  34                                 maximum-speed = "high-speed";
  35                                 snps,dis_u2_susphy_quirk;
  36                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  37                         };
  38                 };
  39         };
  40 };
  41
  42 &apb {
  43         usb2_phy0: phy@78000 {
  44                 compatible = "amlogic,meson-gxl-usb2-phy";
  45                 #phy-cells = <0>;
  46                 reg = <0x0 0x78000 0x0 0x20>;
  47                 clocks = <&clkc CLKID_USB>;
  48                 clock-names = "phy";
  49                 resets = <&reset RESET_USB_OTG>;
  50                 reset-names = "phy";
  51                 status = "okay";
  52         };
  53
  54         usb2_phy1: phy@78020 {
  55                 compatible = "amlogic,meson-gxl-usb2-phy";
  56                 #phy-cells = <0>;
  57                 reg = <0x0 0x78020 0x0 0x20>;
  58                 clocks = <&clkc CLKID_USB>;
  59                 clock-names = "phy";
  60                 resets = <&reset RESET_USB_OTG>;
  61                 reset-names = "phy";
  62                 status = "okay";
  63         };
  64
  65         usb3_phy: phy@78080 {
  66                 compatible = "amlogic,meson-gxl-usb3-phy";
  67                 #phy-cells = <0>;
  68                 reg = <0x0 0x78080 0x0 0x20>;
  69                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  70                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  71                 clock-names = "phy", "peripheral";
  72                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  73                 reset-names = "phy", "peripheral";
  74                 status = "okay";
  75         };
  76 };
  77
  78 &ethmac {
  79         reg = <0x0 0xc9410000 0x0 0x10000
  80                0x0 0xc8834540 0x0 0x4>;
  81
  82         clocks = <&clkc CLKID_ETH>,
  83                  <&clkc CLKID_FCLK_DIV2>,
  84                  <&clkc CLKID_MPLL2>;
  85         clock-names = "stmmaceth", "clkin0", "clkin1";
  86
  87         mdio0: mdio {
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90                 compatible = "snps,dwmac-mdio";
  91         };
  92 };
  93
  94 &aobus {
  95         pinctrl_aobus: pinctrl@14 {
  96                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  97                 #address-cells = <2>;
  98                 #size-cells = <2>;
  99                 ranges;
 100
 101                 gpio_ao: bank@14 {
 102                         reg = <0x0 0x00014 0x0 0x8>,
 103                               <0x0 0x0002c 0x0 0x4>,
 104                               <0x0 0x00024 0x0 0x8>;
 105                         reg-names = "mux", "pull", "gpio";
 106                         gpio-controller;
 107                         #gpio-cells = <2>;
 108                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 109                 };
 110
 111                 uart_ao_a_pins: uart_ao_a {
 112                         mux {
 113                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 114                                 function = "uart_ao";
 115                         };
 116                 };
 117
 118                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 119                         mux {
 120                                 groups = "uart_cts_ao_a",
 121                                        "uart_rts_ao_a";
 122                                 function = "uart_ao";
 123                         };
 124                 };
 125
 126                 uart_ao_b_pins: uart_ao_b {
 127                         mux {
 128                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 129                                 function = "uart_ao_b";
 130                         };
 131                 };
 132
 133                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 134                         mux {
 135                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 136                                 function = "uart_ao_b";
 137                         };
 138                 };
 139
 140                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 141                         mux {
 142                                 groups = "uart_cts_ao_b",
 143                                        "uart_rts_ao_b";
 144                                 function = "uart_ao_b";
 145                         };
 146                 };
 147
 148                 remote_input_ao_pins: remote_input_ao {
 149                         mux {
 150                                 groups = "remote_input_ao";
 151                                 function = "remote_input_ao";
 152                         };
 153                 };
 154
 155                 i2c_ao_pins: i2c_ao {
 156                         mux {
 157                                 groups = "i2c_sck_ao",
 158                                        "i2c_sda_ao";
 159                                 function = "i2c_ao";
 160                         };
 161                 };
 162
 163                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 164                         mux {
 165                                 groups = "pwm_ao_a_3";
 166                                 function = "pwm_ao_a";
 167                         };
 168                 };
 169
 170                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 171                         mux {
 172                                 groups = "pwm_ao_a_8";
 173                                 function = "pwm_ao_a";
 174                         };
 175                 };
 176
 177                 pwm_ao_b_pins: pwm_ao_b {
 178                         mux {
 179                                 groups = "pwm_ao_b";
 180                                 function = "pwm_ao_b";
 181                         };
 182                 };
 183
 184                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 185                         mux {
 186                                 groups = "pwm_ao_b_6";
 187                                 function = "pwm_ao_b";
 188                         };
 189                 };
 190
 191                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 192                         mux {
 193                                 groups = "i2s_out_ch23_ao";
 194                                 function = "i2s_out_ao";
 195                         };
 196                 };
 197
 198                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 199                         mux {
 200                                 groups = "i2s_out_ch45_ao";
 201                                 function = "i2s_out_ao";
 202                         };
 203                 };
 204
 205                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 206                         mux {
 207                                 groups = "spdif_out_ao_6";
 208                                 function = "spdif_out_ao";
 209                         };
 210                 };
 211
 212                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 213                         mux {
 214                                 groups = "spdif_out_ao_9";
 215                                 function = "spdif_out_ao";
 216                         };
 217                 };
 218
 219                 ao_cec_pins: ao_cec {
 220                         mux {
 221                                 groups = "ao_cec";
 222                                 function = "cec_ao";
 223                         };
 224                 };
 225
 226                 ee_cec_pins: ee_cec {
 227                         mux {
 228                                 groups = "ee_cec";
 229                                 function = "cec_ao";
 230                         };
 231                 };
 232         };
 233 };
 234
 235 &cec_AO {
 236         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 237         clock-names = "core";
 238 };
 239
 240 &clkc_AO {
 241         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 242 };
 243
 244 &gpio_intc {
 245         compatible = "amlogic,meson-gpio-intc",
 246                      "amlogic,meson-gxl-gpio-intc";
 247         status = "okay";
 248 };
 249
 250 &hdmi_tx {
 251         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 252         resets = <&reset RESET_HDMITX_CAPB3>,
 253                  <&reset RESET_HDMI_SYSTEM_RESET>,
 254                  <&reset RESET_HDMI_TX>;
 255         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 256         clocks = <&clkc CLKID_HDMI_PCLK>,
 257                  <&clkc CLKID_CLK81>,
 258                  <&clkc CLKID_GCLK_VENCI_INT0>;
 259         clock-names = "isfr", "iahb", "venci";
 260 };
 261
 262 &sysctrl {
 263         clkc: clock-controller {
 264                 compatible = "amlogic,gxl-clkc";
 265                 #clock-cells = <1>;
 266         };
 267 };
 268
 269 &i2c_A {
 270         clocks = <&clkc CLKID_I2C>;
 271 };
 272
 273 &i2c_AO {
 274         clocks = <&clkc CLKID_AO_I2C>;
 275 };
 276
 277 &i2c_B {
 278         clocks = <&clkc CLKID_I2C>;
 279 };
 280
 281 &i2c_C {
 282         clocks = <&clkc CLKID_I2C>;
 283 };
 284
 285 &periphs {
 286         pinctrl_periphs: pinctrl@4b0 {
 287                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 288                 #address-cells = <2>;
 289                 #size-cells = <2>;
 290                 ranges;
 291
 292                 gpio: bank@4b0 {
 293                         reg = <0x0 0x004b0 0x0 0x28>,
 294                               <0x0 0x004e8 0x0 0x14>,
 295                               <0x0 0x00520 0x0 0x14>,
 296                               <0x0 0x00430 0x0 0x40>;
 297                         reg-names = "mux", "pull", "pull-enable", "gpio";
 298                         gpio-controller;
 299                         #gpio-cells = <2>;
 300                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 301                 };
 302
 303                 emmc_pins: emmc {
 304                         mux {
 305                                 groups = "emmc_nand_d07",
 306                                        "emmc_cmd",
 307                                        "emmc_clk";
 308                                 function = "emmc";
 309                         };
 310                 };
 311
 312                 emmc_ds_pins: emmc-ds {
 313                         mux {
 314                                 groups = "emmc_ds";
 315                                 function = "emmc";
 316                         };
 317                 };
 318
 319                 emmc_clk_gate_pins: emmc_clk_gate {
 320                         mux {
 321                                 groups = "BOOT_8";
 322                                 function = "gpio_periphs";
 323                         };
 324                         cfg-pull-down {
 325                                 pins = "BOOT_8";
 326                                 bias-pull-down;
 327                         };
 328                 };
 329
 330                 nor_pins: nor {
 331                         mux {
 332                                 groups = "nor_d",
 333                                        "nor_q",
 334                                        "nor_c",
 335                                        "nor_cs";
 336                                 function = "nor";
 337                         };
 338                 };
 339
 340                 spi_pins: spi-pins {
 341                         mux {
 342                                 groups = "spi_miso",
 343                                         "spi_mosi",
 344                                         "spi_sclk";
 345                                 function = "spi";
 346                         };
 347                 };
 348
 349                 spi_ss0_pins: spi-ss0 {
 350                         mux {
 351                                 groups = "spi_ss0";
 352                                 function = "spi";
 353                         };
 354                 };
 355
 356                 sdcard_pins: sdcard {
 357                         mux {
 358                                 groups = "sdcard_d0",
 359                                        "sdcard_d1",
 360                                        "sdcard_d2",
 361                                        "sdcard_d3",
 362                                        "sdcard_cmd",
 363                                        "sdcard_clk";
 364                                 function = "sdcard";
 365                         };
 366                 };
 367
 368                 sdcard_clk_gate_pins: sdcard_clk_gate {
 369                         mux {
 370                                 groups = "CARD_2";
 371                                 function = "gpio_periphs";
 372                         };
 373                         cfg-pull-down {
 374                                 pins = "CARD_2";
 375                                 bias-pull-down;
 376                         };
 377                 };
 378
 379                 sdio_pins: sdio {
 380                         mux {
 381                                 groups = "sdio_d0",
 382                                        "sdio_d1",
 383                                        "sdio_d2",
 384                                        "sdio_d3",
 385                                        "sdio_cmd",
 386                                        "sdio_clk";
 387                                 function = "sdio";
 388                         };
 389                 };
 390
 391                 sdio_clk_gate_pins: sdio_clk_gate {
 392                         mux {
 393                                 groups = "GPIOX_4";
 394                                 function = "gpio_periphs";
 395                         };
 396                         cfg-pull-down {
 397                                 pins = "GPIOX_4";
 398                                 bias-pull-down;
 399                         };
 400                 };
 401
 402                 sdio_irq_pins: sdio_irq {
 403                         mux {
 404                                 groups = "sdio_irq";
 405                                 function = "sdio";
 406                         };
 407                 };
 408
 409                 uart_a_pins: uart_a {
 410                         mux {
 411                                 groups = "uart_tx_a",
 412                                        "uart_rx_a";
 413                                 function = "uart_a";
 414                         };
 415                 };
 416
 417                 uart_a_cts_rts_pins: uart_a_cts_rts {
 418                         mux {
 419                                 groups = "uart_cts_a",
 420                                        "uart_rts_a";
 421                                 function = "uart_a";
 422                         };
 423                 };
 424
 425                 uart_b_pins: uart_b {
 426                         mux {
 427                                 groups = "uart_tx_b",
 428                                        "uart_rx_b";
 429                                 function = "uart_b";
 430                         };
 431                 };
 432
 433                 uart_b_cts_rts_pins: uart_b_cts_rts {
 434                         mux {
 435                                 groups = "uart_cts_b",
 436                                        "uart_rts_b";
 437                                 function = "uart_b";
 438                         };
 439                 };
 440
 441                 uart_c_pins: uart_c {
 442                         mux {
 443                                 groups = "uart_tx_c",
 444                                        "uart_rx_c";
 445                                 function = "uart_c";
 446                         };
 447                 };
 448
 449                 uart_c_cts_rts_pins: uart_c_cts_rts {
 450                         mux {
 451                                 groups = "uart_cts_c",
 452                                        "uart_rts_c";
 453                                 function = "uart_c";
 454                         };
 455                 };
 456
 457                 i2c_a_pins: i2c_a {
 458                         mux {
 459                                 groups = "i2c_sck_a",
 460                                      "i2c_sda_a";
 461                                 function = "i2c_a";
 462                         };
 463                 };
 464
 465                 i2c_b_pins: i2c_b {
 466                         mux {
 467                                 groups = "i2c_sck_b",
 468                                       "i2c_sda_b";
 469                                 function = "i2c_b";
 470                         };
 471                 };
 472
 473                 i2c_c_pins: i2c_c {
 474                         mux {
 475                                 groups = "i2c_sck_c",
 476                                       "i2c_sda_c";
 477                                 function = "i2c_c";
 478                         };
 479                 };
 480
 481                 eth_pins: eth_c {
 482                         mux {
 483                                 groups = "eth_mdio",
 484                                        "eth_mdc",
 485                                        "eth_clk_rx_clk",
 486                                        "eth_rx_dv",
 487                                        "eth_rxd0",
 488                                        "eth_rxd1",
 489                                        "eth_rxd2",
 490                                        "eth_rxd3",
 491                                        "eth_rgmii_tx_clk",
 492                                        "eth_tx_en",
 493                                        "eth_txd0",
 494                                        "eth_txd1",
 495                                        "eth_txd2",
 496                                        "eth_txd3";
 497                                 function = "eth";
 498                         };
 499                 };
 500
 501                 eth_link_led_pins: eth_link_led {
 502                         mux {
 503                                 groups = "eth_link_led";
 504                                 function = "eth_led";
 505                         };
 506                 };
 507
 508                 eth_act_led_pins: eth_act_led {
 509                         mux {
 510                                 groups = "eth_act_led";
 511                                 function = "eth_led";
 512                         };
 513                 };
 514
 515                 pwm_a_pins: pwm_a {
 516                         mux {
 517                                 groups = "pwm_a";
 518                                 function = "pwm_a";
 519                         };
 520                 };
 521
 522                 pwm_b_pins: pwm_b {
 523                         mux {
 524                                 groups = "pwm_b";
 525                                 function = "pwm_b";
 526                         };
 527                 };
 528
 529                 pwm_c_pins: pwm_c {
 530                         mux {
 531                                 groups = "pwm_c";
 532                                 function = "pwm_c";
 533                         };
 534                 };
 535
 536                 pwm_d_pins: pwm_d {
 537                         mux {
 538                                 groups = "pwm_d";
 539                                 function = "pwm_d";
 540                         };
 541                 };
 542
 543                 pwm_e_pins: pwm_e {
 544                         mux {
 545                                 groups = "pwm_e";
 546                                 function = "pwm_e";
 547                         };
 548                 };
 549
 550                 pwm_f_clk_pins: pwm_f_clk {
 551                         mux {
 552                                 groups = "pwm_f_clk";
 553                                 function = "pwm_f";
 554                         };
 555                 };
 556
 557                 pwm_f_x_pins: pwm_f_x {
 558                         mux {
 559                                 groups = "pwm_f_x";
 560                                 function = "pwm_f";
 561                         };
 562                 };
 563
 564                 hdmi_hpd_pins: hdmi_hpd {
 565                         mux {
 566                                 groups = "hdmi_hpd";
 567                                 function = "hdmi_hpd";
 568                         };
 569                 };
 570
 571                 hdmi_i2c_pins: hdmi_i2c {
 572                         mux {
 573                                 groups = "hdmi_sda", "hdmi_scl";
 574                                 function = "hdmi_i2c";
 575                         };
 576                 };
 577
 578                 i2s_am_clk_pins: i2s_am_clk {
 579                         mux {
 580                                 groups = "i2s_am_clk";
 581                                 function = "i2s_out";
 582                         };
 583                 };
 584
 585                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 586                         mux {
 587                                 groups = "i2s_out_ao_clk";
 588                                 function = "i2s_out";
 589                         };
 590                 };
 591
 592                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 593                         mux {
 594                                 groups = "i2s_out_lr_clk";
 595                                 function = "i2s_out";
 596                         };
 597                 };
 598
 599                 i2s_out_ch01_pins: i2s_out_ch01 {
 600                         mux {
 601                                 groups = "i2s_out_ch01";
 602                                 function = "i2s_out";
 603                         };
 604                 };
 605                 i2sout_ch23_z_pins: i2sout_ch23_z {
 606                         mux {
 607                                 groups = "i2sout_ch23_z";
 608                                 function = "i2s_out";
 609                         };
 610                 };
 611
 612                 i2sout_ch45_z_pins: i2sout_ch45_z {
 613                         mux {
 614                                 groups = "i2sout_ch45_z";
 615                                 function = "i2s_out";
 616                         };
 617                 };
 618
 619                 i2sout_ch67_z_pins: i2sout_ch67_z {
 620                         mux {
 621                                 groups = "i2sout_ch67_z";
 622                                 function = "i2s_out";
 623                         };
 624                 };
 625
 626                 spdif_out_h_pins: spdif_out_ao_h {
 627                         mux {
 628                                 groups = "spdif_out_h";
 629                                 function = "spdif_out";
 630                         };
 631                 };
 632         };
 633
 634         eth-phy-mux {
 635                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638                 reg = <0x0 0x55c 0x0 0x4>;
 639                 mux-mask = <0xffffffff>;
 640                 mdio-parent-bus = <&mdio0>;
 641
 642                 internal_mdio: mdio@e40908ff {
 643                         reg = <0xe40908ff>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646
 647                         internal_phy: ethernet-phy@8 {
 648                                 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
 649                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 650                                 reg = <8>;
 651                                 max-speed = <100>;
 652                         };
 653                 };
 654
 655                 external_mdio: mdio@2009087f {
 656                         reg = <0x2009087f>;
 657                         #address-cells = <1>;
 658                         #size-cells = <0>;
 659                 };
 660         };
 661 };
 662
 663 &pwrc_vpu {
 664         resets = <&reset RESET_VIU>,
 665                  <&reset RESET_VENC>,
 666                  <&reset RESET_VCBUS>,
 667                  <&reset RESET_BT656>,
 668                  <&reset RESET_DVIN_RESET>,
 669                  <&reset RESET_RDMA>,
 670                  <&reset RESET_VENCI>,
 671                  <&reset RESET_VENCP>,
 672                  <&reset RESET_VDAC>,
 673                  <&reset RESET_VDI6>,
 674                  <&reset RESET_VENCL>,
 675                  <&reset RESET_VID_LOCK>;
 676         clocks = <&clkc CLKID_VPU>,
 677                  <&clkc CLKID_VAPB>;
 678         clock-names = "vpu", "vapb";
 679         /*
 680          * VPU clocking is provided by two identical clock paths
 681          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 682          * free mux to safely change frequency while running.
 683          * Same for VAPB but with a final gate after the glitch free mux.
 684          */
 685         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 686                           <&clkc CLKID_VPU_0>,
 687                           <&clkc CLKID_VPU>, /* Glitch free mux */
 688                           <&clkc CLKID_VAPB_0_SEL>,
 689                           <&clkc CLKID_VAPB_0>,
 690                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 691         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 692                                  <0>, /* Do Nothing */
 693                                  <&clkc CLKID_VPU_0>,
 694                                  <&clkc CLKID_FCLK_DIV4>,
 695                                  <0>, /* Do Nothing */
 696                                  <&clkc CLKID_VAPB_0>;
 697         assigned-clock-rates = <0>, /* Do Nothing */
 698                                <666666666>,
 699                                <0>, /* Do Nothing */
 700                                <0>, /* Do Nothing */
 701                                <250000000>,
 702                                <0>; /* Do Nothing */
 703 };
 704
 705 &saradc {
 706         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 707         clocks = <&xtal>,
 708                  <&clkc CLKID_SAR_ADC>,
 709                  <&clkc CLKID_SAR_ADC_CLK>,
 710                  <&clkc CLKID_SAR_ADC_SEL>;
 711         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 712 };
 713
 714 &sd_emmc_a {
 715         clocks = <&clkc CLKID_SD_EMMC_A>,
 716                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 717                  <&clkc CLKID_FCLK_DIV2>;
 718         clock-names = "core", "clkin0", "clkin1";
 719         resets = <&reset RESET_SD_EMMC_A>;
 720 };
 721
 722 &sd_emmc_b {
 723         clocks = <&clkc CLKID_SD_EMMC_B>,
 724                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 725                  <&clkc CLKID_FCLK_DIV2>;
 726         clock-names = "core", "clkin0", "clkin1";
 727         resets = <&reset RESET_SD_EMMC_B>;
 728 };
 729
 730 &sd_emmc_c {
 731         clocks = <&clkc CLKID_SD_EMMC_C>,
 732                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 733                  <&clkc CLKID_FCLK_DIV2>;
 734         clock-names = "core", "clkin0", "clkin1";
 735         resets = <&reset RESET_SD_EMMC_C>;
 736 };
 737
 738 &spicc {
 739         clocks = <&clkc CLKID_SPICC>;
 740         clock-names = "core";
 741         resets = <&reset RESET_PERIPHS_SPICC>;
 742         num-cs = <1>;
 743 };
 744
 745 &spifc {
 746         clocks = <&clkc CLKID_SPI>;
 747 };
 748
 749 &uart_A {
 750         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 751         clock-names = "xtal", "pclk", "baud";
 752 };
 753
 754 &uart_AO {
 755         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 756         clock-names = "xtal", "pclk", "baud";
 757 };
 758
 759 &uart_AO_B {
 760         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 761         clock-names = "xtal", "pclk", "baud";
 762 };
 763
 764 &uart_B {
 765         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 766         clock-names = "xtal", "pclk", "baud";
 767 };
 768
 769 &uart_C {
 770         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 771         clock-names = "xtal", "pclk", "baud";
 772 };
 773
 774 &vpu {
 775         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 776         power-domains = <&pwrc_vpu>;
 777 };