src/arm64/freescale/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4  *
   5  * Copyright 2017 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1088a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x0>;
  32                         clocks = <&clockgen 1 0>;
  33                         cpu-idle-states = <&CPU_PH20>;
  34                         #cooling-cells = <2>;
  35                 };
  36
  37                 cpu1: cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53";
  40                         reg = <0x1>;
  41                         clocks = <&clockgen 1 0>;
  42                         cpu-idle-states = <&CPU_PH20>;
  43                         #cooling-cells = <2>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x2>;
  50                         clocks = <&clockgen 1 0>;
  51                         cpu-idle-states = <&CPU_PH20>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         reg = <0x3>;
  59                         clocks = <&clockgen 1 0>;
  60                         cpu-idle-states = <&CPU_PH20>;
  61                         #cooling-cells = <2>;
  62                 };
  63
  64                 cpu4: cpu@100 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x100>;
  68                         clocks = <&clockgen 1 1>;
  69                         cpu-idle-states = <&CPU_PH20>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu5: cpu@101 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0x101>;
  77                         clocks = <&clockgen 1 1>;
  78                         cpu-idle-states = <&CPU_PH20>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu6: cpu@102 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x102>;
  86                         clocks = <&clockgen 1 1>;
  87                         cpu-idle-states = <&CPU_PH20>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 cpu7: cpu@103 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53";
  94                         reg = <0x103>;
  95                         clocks = <&clockgen 1 1>;
  96                         cpu-idle-states = <&CPU_PH20>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 CPU_PH20: cpu-ph20 {
 101                         compatible = "arm,idle-state";
 102                         idle-state-name = "PH20";
 103                         arm,psci-suspend-param = <0x0>;
 104                         entry-latency-us = <1000>;
 105                         exit-latency-us = <1000>;
 106                         min-residency-us = <3000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@6000000 {
 111                 compatible = "arm,gic-v3";
 112                 #interrupt-cells = <3>;
 113                 interrupt-controller;
 114                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 115                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 116                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 117                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 118                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 119                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 its: gic-its@6020000 {
 125                         compatible = "arm,gic-v3-its";
 126                         msi-controller;
 127                         reg = <0x0 0x6020000 0 0x20000>;
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 cpu_thermal: cpu-thermal {
 133                         polling-delay-passive = <1000>;
 134                         polling-delay = <5000>;
 135                         thermal-sensors = <&tmu 0>;
 136
 137                         trips {
 138                                 cpu_alert: cpu-alert {
 139                                         temperature = <85000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 cpu_crit: cpu-crit {
 145                                         temperature = <95000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150
 151                         cooling-maps {
 152                                 map0 {
 153                                         trip = <&cpu_alert>;
 154                                         cooling-device =
 155                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 156                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 157                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 158                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 163                                 };
 164                         };
 165                 };
 166         };
 167
 168         timer {
 169                 compatible = "arm,armv8-timer";
 170                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 171                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 172                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 173                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 174         };
 175
 176         psci {
 177                 compatible = "arm,psci-0.2";
 178                 method = "smc";
 179         };
 180
 181         sysclk: sysclk {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <100000000>;
 185                 clock-output-names = "sysclk";
 186         };
 187
 188         soc {
 189                 compatible = "simple-bus";
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192                 ranges;
 193                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 194
 195                 clockgen: clocking@1300000 {
 196                         compatible = "fsl,ls1088a-clockgen";
 197                         reg = <0 0x1300000 0 0xa0000>;
 198                         #clock-cells = <2>;
 199                         clocks = <&sysclk>;
 200                 };
 201
 202                 dcfg: dcfg@1e00000 {
 203                         compatible = "fsl,ls1088a-dcfg", "syscon";
 204                         reg = <0x0 0x1e00000 0x0 0x10000>;
 205                         little-endian;
 206                 };
 207
 208                 tmu: tmu@1f80000 {
 209                         compatible = "fsl,qoriq-tmu";
 210                         reg = <0x0 0x1f80000 0x0 0x10000>;
 211                         interrupts = <0 23 0x4>;
 212                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 213                         fsl,tmu-calibration =
 214                                 /* Calibration data group 1 */
 215                                 <0x00000000 0x00000026
 216                                 0x00000001 0x0000002d
 217                                 0x00000002 0x00000032
 218                                 0x00000003 0x00000039
 219                                 0x00000004 0x0000003f
 220                                 0x00000005 0x00000046
 221                                 0x00000006 0x0000004d
 222                                 0x00000007 0x00000054
 223                                 0x00000008 0x0000005a
 224                                 0x00000009 0x00000061
 225                                 0x0000000a 0x0000006a
 226                                 0x0000000b 0x00000071
 227                                 /* Calibration data group 2 */
 228                                 0x00010000 0x00000025
 229                                 0x00010001 0x0000002c
 230                                 0x00010002 0x00000035
 231                                 0x00010003 0x0000003d
 232                                 0x00010004 0x00000045
 233                                 0x00010005 0x0000004e
 234                                 0x00010006 0x00000057
 235                                 0x00010007 0x00000061
 236                                 0x00010008 0x0000006b
 237                                 0x00010009 0x00000076
 238                                 /* Calibration data group 3 */
 239                                 0x00020000 0x00000029
 240                                 0x00020001 0x00000033
 241                                 0x00020002 0x0000003d
 242                                 0x00020003 0x00000049
 243                                 0x00020004 0x00000056
 244                                 0x00020005 0x00000061
 245                                 0x00020006 0x0000006d
 246                                 /* Calibration data group 4 */
 247                                 0x00030000 0x00000021
 248                                 0x00030001 0x0000002a
 249                                 0x00030002 0x0000003c
 250                                 0x00030003 0x0000004e>;
 251                         little-endian;
 252                         #thermal-sensor-cells = <1>;
 253                 };
 254
 255                 duart0: serial@21c0500 {
 256                         compatible = "fsl,ns16550", "ns16550a";
 257                         reg = <0x0 0x21c0500 0x0 0x100>;
 258                         clocks = <&clockgen 4 3>;
 259                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 260                         status = "disabled";
 261                 };
 262
 263                 duart1: serial@21c0600 {
 264                         compatible = "fsl,ns16550", "ns16550a";
 265                         reg = <0x0 0x21c0600 0x0 0x100>;
 266                         clocks = <&clockgen 4 3>;
 267                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 268                         status = "disabled";
 269                 };
 270
 271                 gpio0: gpio@2300000 {
 272                         compatible = "fsl,qoriq-gpio";
 273                         reg = <0x0 0x2300000 0x0 0x10000>;
 274                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 275                         gpio-controller;
 276                         #gpio-cells = <2>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                 };
 280
 281                 gpio1: gpio@2310000 {
 282                         compatible = "fsl,qoriq-gpio";
 283                         reg = <0x0 0x2310000 0x0 0x10000>;
 284                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 285                         gpio-controller;
 286                         #gpio-cells = <2>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <2>;
 289                 };
 290
 291                 gpio2: gpio@2320000 {
 292                         compatible = "fsl,qoriq-gpio";
 293                         reg = <0x0 0x2320000 0x0 0x10000>;
 294                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio3: gpio@2330000 {
 302                         compatible = "fsl,qoriq-gpio";
 303                         reg = <0x0 0x2330000 0x0 0x10000>;
 304                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                         interrupt-controller;
 308                         #interrupt-cells = <2>;
 309                 };
 310
 311                 ifc: ifc@2240000 {
 312                         compatible = "fsl,ifc", "simple-bus";
 313                         reg = <0x0 0x2240000 0x0 0x20000>;
 314                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 315                         little-endian;
 316                         #address-cells = <2>;
 317                         #size-cells = <1>;
 318                         status = "disabled";
 319                 };
 320
 321                 i2c0: i2c@2000000 {
 322                         compatible = "fsl,vf610-i2c";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         reg = <0x0 0x2000000 0x0 0x10000>;
 326                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&clockgen 4 3>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c1: i2c@2010000 {
 332                         compatible = "fsl,vf610-i2c";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         reg = <0x0 0x2010000 0x0 0x10000>;
 336                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&clockgen 4 3>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c2: i2c@2020000 {
 342                         compatible = "fsl,vf610-i2c";
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         reg = <0x0 0x2020000 0x0 0x10000>;
 346                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&clockgen 4 3>;
 348                         status = "disabled";
 349                 };
 350
 351                 i2c3: i2c@2030000 {
 352                         compatible = "fsl,vf610-i2c";
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         reg = <0x0 0x2030000 0x0 0x10000>;
 356                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&clockgen 4 3>;
 358                         status = "disabled";
 359                 };
 360
 361                 esdhc: esdhc@2140000 {
 362                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 363                         reg = <0x0 0x2140000 0x0 0x10000>;
 364                         interrupts = <0 28 0x4>; /* Level high type */
 365                         clock-frequency = <0>;
 366                         voltage-ranges = <1800 1800 3300 3300>;
 367                         sdhci,auto-cmd12;
 368                         little-endian;
 369                         bus-width = <4>;
 370                         status = "disabled";
 371                 };
 372
 373                 usb0: usb3@3100000 {
 374                         compatible = "snps,dwc3";
 375                         reg = <0x0 0x3100000 0x0 0x10000>;
 376                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 377                         dr_mode = "host";
 378                         snps,quirk-frame-length-adjustment = <0x20>;
 379                         snps,dis_rxdet_inp3_quirk;
 380                         status = "disabled";
 381                 };
 382
 383                 usb1: usb3@3110000 {
 384                         compatible = "snps,dwc3";
 385                         reg = <0x0 0x3110000 0x0 0x10000>;
 386                         interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 387                         dr_mode = "host";
 388                         snps,quirk-frame-length-adjustment = <0x20>;
 389                         snps,dis_rxdet_inp3_quirk;
 390                         status = "disabled";
 391                 };
 392
 393                 sata: sata@3200000 {
 394                         compatible = "fsl,ls1088a-ahci";
 395                         reg = <0x0 0x3200000 0x0 0x10000>,
 396                                 <0x7 0x100520 0x0 0x4>;
 397                         reg-names = "ahci", "sata-ecc";
 398                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&clockgen 4 3>;
 400                         dma-coherent;
 401                         status = "disabled";
 402                 };
 403
 404                 crypto: crypto@8000000 {
 405                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 406                         fsl,sec-era = <8>;
 407                         #address-cells = <1>;
 408                         #size-cells = <1>;
 409                         ranges = <0x0 0x00 0x8000000 0x100000>;
 410                         reg = <0x00 0x8000000 0x0 0x100000>;
 411                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 412                         dma-coherent;
 413
 414                         sec_jr0: jr@10000 {
 415                                 compatible = "fsl,sec-v5.0-job-ring",
 416                                              "fsl,sec-v4.0-job-ring";
 417                                 reg        = <0x10000 0x10000>;
 418                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 419                         };
 420
 421                         sec_jr1: jr@20000 {
 422                                 compatible = "fsl,sec-v5.0-job-ring",
 423                                              "fsl,sec-v4.0-job-ring";
 424                                 reg        = <0x20000 0x10000>;
 425                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 426                         };
 427
 428                         sec_jr2: jr@30000 {
 429                                 compatible = "fsl,sec-v5.0-job-ring",
 430                                              "fsl,sec-v4.0-job-ring";
 431                                 reg        = <0x30000 0x10000>;
 432                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 433                         };
 434
 435                         sec_jr3: jr@40000 {
 436                                 compatible = "fsl,sec-v5.0-job-ring",
 437                                              "fsl,sec-v4.0-job-ring";
 438                                 reg        = <0x40000 0x10000>;
 439                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 440                         };
 441                 };
 442
 443                 pcie@3400000 {
 444                         compatible = "fsl,ls1088a-pcie";
 445                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 446                                0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 447                         reg-names = "regs", "config";
 448                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 449                         interrupt-names = "aer";
 450                         #address-cells = <3>;
 451                         #size-cells = <2>;
 452                         device_type = "pci";
 453                         dma-coherent;
 454                         num-lanes = <4>;
 455                         bus-range = <0x0 0xff>;
 456                         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 457                                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 458                         msi-parent = <&its>;
 459                         #interrupt-cells = <1>;
 460                         interrupt-map-mask = <0 0 0 7>;
 461                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 462                                         <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 463                                         <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 464                                         <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 465                         status = "disabled";
 466                 };
 467
 468                 pcie@3500000 {
 469                         compatible = "fsl,ls1088a-pcie";
 470                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 471                                0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 472                         reg-names = "regs", "config";
 473                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 474                         interrupt-names = "aer";
 475                         #address-cells = <3>;
 476                         #size-cells = <2>;
 477                         device_type = "pci";
 478                         dma-coherent;
 479                         num-lanes = <4>;
 480                         bus-range = <0x0 0xff>;
 481                         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 482                                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 483                         msi-parent = <&its>;
 484                         #interrupt-cells = <1>;
 485                         interrupt-map-mask = <0 0 0 7>;
 486                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 487                                         <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 488                                         <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 489                                         <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 490                         status = "disabled";
 491                 };
 492
 493                 pcie@3600000 {
 494                         compatible = "fsl,ls1088a-pcie";
 495                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 496                                0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 497                         reg-names = "regs", "config";
 498                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 499                         interrupt-names = "aer";
 500                         #address-cells = <3>;
 501                         #size-cells = <2>;
 502                         device_type = "pci";
 503                         dma-coherent;
 504                         num-lanes = <8>;
 505                         bus-range = <0x0 0xff>;
 506                         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 507                                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 508                         msi-parent = <&its>;
 509                         #interrupt-cells = <1>;
 510                         interrupt-map-mask = <0 0 0 7>;
 511                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 512                                         <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 513                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 514                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 515                         status = "disabled";
 516                 };
 517
 518                 cluster1_core0_watchdog: wdt@c000000 {
 519                         compatible = "arm,sp805-wdt", "arm,primecell";
 520                         reg = <0x0 0xc000000 0x0 0x1000>;
 521                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 522                         clock-names = "apb_pclk", "wdog_clk";
 523                 };
 524
 525                 cluster1_core1_watchdog: wdt@c010000 {
 526                         compatible = "arm,sp805-wdt", "arm,primecell";
 527                         reg = <0x0 0xc010000 0x0 0x1000>;
 528                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 529                         clock-names = "apb_pclk", "wdog_clk";
 530                 };
 531
 532                 cluster1_core2_watchdog: wdt@c020000 {
 533                         compatible = "arm,sp805-wdt", "arm,primecell";
 534                         reg = <0x0 0xc020000 0x0 0x1000>;
 535                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 536                         clock-names = "apb_pclk", "wdog_clk";
 537                 };
 538
 539                 cluster1_core3_watchdog: wdt@c030000 {
 540                         compatible = "arm,sp805-wdt", "arm,primecell";
 541                         reg = <0x0 0xc030000 0x0 0x1000>;
 542                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 543                         clock-names = "apb_pclk", "wdog_clk";
 544                 };
 545
 546                 cluster2_core0_watchdog: wdt@c100000 {
 547                         compatible = "arm,sp805-wdt", "arm,primecell";
 548                         reg = <0x0 0xc100000 0x0 0x1000>;
 549                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 550                         clock-names = "apb_pclk", "wdog_clk";
 551                 };
 552
 553                 cluster2_core1_watchdog: wdt@c110000 {
 554                         compatible = "arm,sp805-wdt", "arm,primecell";
 555                         reg = <0x0 0xc110000 0x0 0x1000>;
 556                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 557                         clock-names = "apb_pclk", "wdog_clk";
 558                 };
 559
 560                 cluster2_core2_watchdog: wdt@c120000 {
 561                         compatible = "arm,sp805-wdt", "arm,primecell";
 562                         reg = <0x0 0xc120000 0x0 0x1000>;
 563                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 564                         clock-names = "apb_pclk", "wdog_clk";
 565                 };
 566
 567                 cluster2_core3_watchdog: wdt@c130000 {
 568                         compatible = "arm,sp805-wdt", "arm,primecell";
 569                         reg = <0x0 0xc130000 0x0 0x1000>;
 570                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 571                         clock-names = "apb_pclk", "wdog_clk";
 572                 };
 573
 574                 fsl_mc: fsl-mc@80c000000 {
 575                         compatible = "fsl,qoriq-mc";
 576                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 577                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 578                         msi-parent = <&its>;
 579                         #address-cells = <3>;
 580                         #size-cells = <1>;
 581
 582                         /*
 583                          * Region type 0x0 - MC portals
 584                          * Region type 0x1 - QBMAN portals
 585                          */
 586                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 587                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 588
 589                         dpmacs {
 590                                 #address-cells = <1>;
 591                                 #size-cells = <0>;
 592
 593                                 dpmac1: dpmac@1 {
 594                                         compatible = "fsl,qoriq-mc-dpmac";
 595                                         reg = <1>;
 596                                 };
 597
 598                                 dpmac2: dpmac@2 {
 599                                         compatible = "fsl,qoriq-mc-dpmac";
 600                                         reg = <2>;
 601                                 };
 602
 603                                 dpmac3: dpmac@3 {
 604                                         compatible = "fsl,qoriq-mc-dpmac";
 605                                         reg = <3>;
 606                                 };
 607
 608                                 dpmac4: dpmac@4 {
 609                                         compatible = "fsl,qoriq-mc-dpmac";
 610                                         reg = <4>;
 611                                 };
 612
 613                                 dpmac5: dpmac@5 {
 614                                         compatible = "fsl,qoriq-mc-dpmac";
 615                                         reg = <5>;
 616                                 };
 617
 618                                 dpmac6: dpmac@6 {
 619                                         compatible = "fsl,qoriq-mc-dpmac";
 620                                         reg = <6>;
 621                                 };
 622
 623                                 dpmac7: dpmac@7 {
 624                                         compatible = "fsl,qoriq-mc-dpmac";
 625                                         reg = <7>;
 626                                 };
 627
 628                                 dpmac8: dpmac@8 {
 629                                         compatible = "fsl,qoriq-mc-dpmac";
 630                                         reg = <8>;
 631                                 };
 632
 633                                 dpmac9: dpmac@9 {
 634                                         compatible = "fsl,qoriq-mc-dpmac";
 635                                         reg = <9>;
 636                                 };
 637
 638                                 dpmac10: dpmac@a {
 639                                         compatible = "fsl,qoriq-mc-dpmac";
 640                                         reg = <0xa>;
 641                                 };
 642                         };
 643                 };
 644         };
 645
 646         firmware {
 647                 optee {
 648                         compatible = "linaro,optee-tz";
 649                         method = "smc";
 650                 };
 651         };
 652
 653 };