src/arm64/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
   9 #include <dt-bindings/clock/qcom,rpmh.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo-board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <38400000>;
  24                         clock-output-names = "xo_board";
  25                 };
  26
  27                 sleep_clk: sleep-clk {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <32764>;
  31                         clock-output-names = "sleep_clk";
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <2>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "qcom,kryo485";
  42                         reg = <0x0 0x0>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&L2_0>;
  45                         L2_0: l2-cache {
  46                                 compatible = "cache";
  47                                 next-level-cache = <&L3_0>;
  48                                 L3_0: l3-cache {
  49                                       compatible = "cache";
  50                                 };
  51                         };
  52                 };
  53
  54                 CPU1: cpu@100 {
  55                         device_type = "cpu";
  56                         compatible = "qcom,kryo485";
  57                         reg = <0x0 0x100>;
  58                         enable-method = "psci";
  59                         next-level-cache = <&L2_100>;
  60                         L2_100: l2-cache {
  61                                 compatible = "cache";
  62                                 next-level-cache = <&L3_0>;
  63                         };
  64
  65                 };
  66
  67                 CPU2: cpu@200 {
  68                         device_type = "cpu";
  69                         compatible = "qcom,kryo485";
  70                         reg = <0x0 0x200>;
  71                         enable-method = "psci";
  72                         next-level-cache = <&L2_200>;
  73                         L2_200: l2-cache {
  74                                 compatible = "cache";
  75                                 next-level-cache = <&L3_0>;
  76                         };
  77                 };
  78
  79                 CPU3: cpu@300 {
  80                         device_type = "cpu";
  81                         compatible = "qcom,kryo485";
  82                         reg = <0x0 0x300>;
  83                         enable-method = "psci";
  84                         next-level-cache = <&L2_300>;
  85                         L2_300: l2-cache {
  86                                 compatible = "cache";
  87                                 next-level-cache = <&L3_0>;
  88                         };
  89                 };
  90
  91                 CPU4: cpu@400 {
  92                         device_type = "cpu";
  93                         compatible = "qcom,kryo485";
  94                         reg = <0x0 0x400>;
  95                         enable-method = "psci";
  96                         next-level-cache = <&L2_400>;
  97                         L2_400: l2-cache {
  98                                 compatible = "cache";
  99                                 next-level-cache = <&L3_0>;
 100                         };
 101                 };
 102
 103                 CPU5: cpu@500 {
 104                         device_type = "cpu";
 105                         compatible = "qcom,kryo485";
 106                         reg = <0x0 0x500>;
 107                         enable-method = "psci";
 108                         next-level-cache = <&L2_500>;
 109                         L2_500: l2-cache {
 110                                 compatible = "cache";
 111                                 next-level-cache = <&L3_0>;
 112                         };
 113                 };
 114
 115                 CPU6: cpu@600 {
 116                         device_type = "cpu";
 117                         compatible = "qcom,kryo485";
 118                         reg = <0x0 0x600>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_600>;
 121                         L2_600: l2-cache {
 122                                 compatible = "cache";
 123                                 next-level-cache = <&L3_0>;
 124                         };
 125                 };
 126
 127                 CPU7: cpu@700 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo485";
 130                         reg = <0x0 0x700>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&L2_700>;
 133                         L2_700: l2-cache {
 134                                 compatible = "cache";
 135                                 next-level-cache = <&L3_0>;
 136                         };
 137                 };
 138         };
 139
 140         firmware {
 141                 scm: scm {
 142                         compatible = "qcom,scm-sm8150", "qcom,scm";
 143                         #reset-cells = <1>;
 144                 };
 145         };
 146
 147         tcsr_mutex: hwlock {
 148                 compatible = "qcom,tcsr-mutex";
 149                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 150                 #hwlock-cells = <1>;
 151         };
 152
 153         memory@80000000 {
 154                 device_type = "memory";
 155                 /* We expect the bootloader to fill in the size */
 156                 reg = <0x0 0x80000000 0x0 0x0>;
 157         };
 158
 159         pmu {
 160                 compatible = "arm,armv8-pmuv3";
 161                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 162         };
 163
 164         psci {
 165                 compatible = "arm,psci-1.0";
 166                 method = "smc";
 167         };
 168
 169         reserved-memory {
 170                 #address-cells = <2>;
 171                 #size-cells = <2>;
 172                 ranges;
 173
 174                 hyp_mem: memory@85700000 {
 175                         reg = <0x0 0x85700000 0x0 0x600000>;
 176                         no-map;
 177                 };
 178
 179                 xbl_mem: memory@85d00000 {
 180                         reg = <0x0 0x85d00000 0x0 0x140000>;
 181                         no-map;
 182                 };
 183
 184                 aop_mem: memory@85f00000 {
 185                         reg = <0x0 0x85f00000 0x0 0x20000>;
 186                         no-map;
 187                 };
 188
 189                 aop_cmd_db: memory@85f20000 {
 190                         compatible = "qcom,cmd-db";
 191                         reg = <0x0 0x85f20000 0x0 0x20000>;
 192                         no-map;
 193                 };
 194
 195                 smem_mem: memory@86000000 {
 196                         reg = <0x0 0x86000000 0x0 0x200000>;
 197                         no-map;
 198                 };
 199
 200                 tz_mem: memory@86200000 {
 201                         reg = <0x0 0x86200000 0x0 0x3900000>;
 202                         no-map;
 203                 };
 204
 205                 rmtfs_mem: memory@89b00000 {
 206                         compatible = "qcom,rmtfs-mem";
 207                         reg = <0x0 0x89b00000 0x0 0x200000>;
 208                         no-map;
 209
 210                         qcom,client-id = <1>;
 211                         qcom,vmid = <15>;
 212                 };
 213
 214                 camera_mem: memory@8b700000 {
 215                         reg = <0x0 0x8b700000 0x0 0x500000>;
 216                         no-map;
 217                 };
 218
 219                 wlan_mem: memory@8bc00000 {
 220                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 221                         no-map;
 222                 };
 223
 224                 npu_mem: memory@8bd80000 {
 225                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 226                         no-map;
 227                 };
 228
 229                 adsp_mem: memory@8be00000 {
 230                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 231                         no-map;
 232                 };
 233
 234                 mpss_mem: memory@8d800000 {
 235                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 236                         no-map;
 237                 };
 238
 239                 venus_mem: memory@96e00000 {
 240                         reg = <0x0 0x96e00000 0x0 0x500000>;
 241                         no-map;
 242                 };
 243
 244                 slpi_mem: memory@97300000 {
 245                         reg = <0x0 0x97300000 0x0 0x1400000>;
 246                         no-map;
 247                 };
 248
 249                 ipa_fw_mem: memory@98700000 {
 250                         reg = <0x0 0x98700000 0x0 0x10000>;
 251                         no-map;
 252                 };
 253
 254                 ipa_gsi_mem: memory@98710000 {
 255                         reg = <0x0 0x98710000 0x0 0x5000>;
 256                         no-map;
 257                 };
 258
 259                 gpu_mem: memory@98715000 {
 260                         reg = <0x0 0x98715000 0x0 0x2000>;
 261                         no-map;
 262                 };
 263
 264                 spss_mem: memory@98800000 {
 265                         reg = <0x0 0x98800000 0x0 0x100000>;
 266                         no-map;
 267                 };
 268
 269                 cdsp_mem: memory@98900000 {
 270                         reg = <0x0 0x98900000 0x0 0x1400000>;
 271                         no-map;
 272                 };
 273
 274                 qseecom_mem: memory@9e400000 {
 275                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 276                         no-map;
 277                 };
 278         };
 279
 280         smem {
 281                 compatible = "qcom,smem";
 282                 memory-region = <&smem_mem>;
 283                 hwlocks = <&tcsr_mutex 3>;
 284         };
 285
 286         soc: soc@0 {
 287                 #address-cells = <2>;
 288                 #size-cells = <2>;
 289                 ranges = <0 0 0 0 0x10 0>;
 290                 dma-ranges = <0 0 0 0 0x10 0>;
 291                 compatible = "simple-bus";
 292
 293                 gcc: clock-controller@100000 {
 294                         compatible = "qcom,gcc-sm8150";
 295                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 296                         #clock-cells = <1>;
 297                         #reset-cells = <1>;
 298                         #power-domain-cells = <1>;
 299                         clock-names = "bi_tcxo",
 300                                       "sleep_clk";
 301                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 302                                  <&sleep_clk>;
 303                 };
 304
 305                 qupv3_id_1: geniqup@ac0000 {
 306                         compatible = "qcom,geni-se-qup";
 307                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 308                         clock-names = "m-ahb", "s-ahb";
 309                         clocks = <&gcc 123>,
 310                                  <&gcc 124>;
 311                         #address-cells = <2>;
 312                         #size-cells = <2>;
 313                         ranges;
 314                         status = "disabled";
 315
 316                         uart2: serial@a90000 {
 317                                 compatible = "qcom,geni-debug-uart";
 318                                 reg = <0x0 0x00a90000 0x0 0x4000>;
 319                                 clock-names = "se";
 320                                 clocks = <&gcc 105>;
 321                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 322                                 status = "disabled";
 323                         };
 324                 };
 325
 326                 tcsr_mutex_regs: syscon@1f40000 {
 327                         compatible = "syscon";
 328                         reg = <0x0 0x01f40000 0x0 0x40000>;
 329                 };
 330
 331                 tlmm: pinctrl@3100000 {
 332                         compatible = "qcom,sm8150-pinctrl";
 333                         reg = <0x0 0x03100000 0x0 0x300000>,
 334                               <0x0 0x03500000 0x0 0x300000>,
 335                               <0x0 0x03900000 0x0 0x300000>,
 336                               <0x0 0x03D00000 0x0 0x300000>;
 337                         reg-names = "west", "east", "north", "south";
 338                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 339                         gpio-ranges = <&tlmm 0 0 175>;
 340                         gpio-controller;
 341                         #gpio-cells = <2>;
 342                         interrupt-controller;
 343                         #interrupt-cells = <2>;
 344                 };
 345
 346                 aoss_qmp: power-controller@c300000 {
 347                         compatible = "qcom,sm8150-aoss-qmp";
 348                         reg = <0x0 0x0c300000 0x0 0x100000>;
 349                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 350                         mboxes = <&apss_shared 0>;
 351
 352                         #clock-cells = <0>;
 353                         #power-domain-cells = <1>;
 354                 };
 355
 356                 spmi_bus: spmi@c440000 {
 357                         compatible = "qcom,spmi-pmic-arb";
 358                         reg = <0x0 0x0c440000 0x0 0x0001100>,
 359                               <0x0 0x0c600000 0x0 0x2000000>,
 360                               <0x0 0x0e600000 0x0 0x0100000>,
 361                               <0x0 0x0e700000 0x0 0x00a0000>,
 362                               <0x0 0x0c40a000 0x0 0x0026000>;
 363                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 364                         interrupt-names = "periph_irq";
 365                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
 366                         qcom,ee = <0>;
 367                         qcom,channel = <0>;
 368                         #address-cells = <2>;
 369                         #size-cells = <0>;
 370                         interrupt-controller;
 371                         #interrupt-cells = <4>;
 372                         cell-index = <0>;
 373                 };
 374
 375                 intc: interrupt-controller@17a00000 {
 376                         compatible = "arm,gic-v3";
 377                         interrupt-controller;
 378                         #interrupt-cells = <3>;
 379                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
 380                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
 381                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 382                 };
 383
 384                 apss_shared: mailbox@17c00000 {
 385                         compatible = "qcom,sm8150-apss-shared";
 386                         reg = <0x0 0x17c00000 0x0 0x1000>;
 387                         #mbox-cells = <1>;
 388                 };
 389
 390                 timer@17c20000 {
 391                         #address-cells = <2>;
 392                         #size-cells = <2>;
 393                         ranges;
 394                         compatible = "arm,armv7-timer-mem";
 395                         reg = <0x0 0x17c20000 0x0 0x1000>;
 396                         clock-frequency = <19200000>;
 397
 398                         frame@17c21000{
 399                                 frame-number = <0>;
 400                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 401                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 402                                 reg = <0x0 0x17c21000 0x0 0x1000>,
 403                                       <0x0 0x17c22000 0x0 0x1000>;
 404                         };
 405
 406                         frame@17c23000 {
 407                                 frame-number = <1>;
 408                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 409                                 reg = <0x0 0x17c23000 0x0 0x1000>;
 410                                 status = "disabled";
 411                         };
 412
 413                         frame@17c25000 {
 414                                 frame-number = <2>;
 415                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 416                                 reg = <0x0 0x17c25000 0x0 0x1000>;
 417                                 status = "disabled";
 418                         };
 419
 420                         frame@17c27000 {
 421                                 frame-number = <3>;
 422                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 423                                 reg = <0x0 0x17c26000 0x0 0x1000>;
 424                                 status = "disabled";
 425                         };
 426
 427                         frame@17c29000 {
 428                                 frame-number = <4>;
 429                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 430                                 reg = <0x0 0x17c29000 0x0 0x1000>;
 431                                 status = "disabled";
 432                         };
 433
 434                         frame@17c2b000 {
 435                                 frame-number = <5>;
 436                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 437                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
 438                                 status = "disabled";
 439                         };
 440
 441                         frame@17c2d000 {
 442                                 frame-number = <6>;
 443                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 444                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
 445                                 status = "disabled";
 446                         };
 447                 };
 448
 449                 apps_rsc: rsc@18200000 {
 450                         label = "apps_rsc";
 451                         compatible = "qcom,rpmh-rsc";
 452                         reg = <0x0 0x18200000 0x0 0x10000>,
 453                               <0x0 0x18210000 0x0 0x10000>,
 454                               <0x0 0x18220000 0x0 0x10000>;
 455                         reg-names = "drv-0", "drv-1", "drv-2";
 456                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 457                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 459                         qcom,tcs-offset = <0xd00>;
 460                         qcom,drv-id = <2>;
 461                         qcom,tcs-config = <ACTIVE_TCS  2>,
 462                                           <SLEEP_TCS   1>,
 463                                           <WAKE_TCS    1>,
 464                                           <CONTROL_TCS 0>;
 465
 466                         rpmhcc: clock-controller {
 467                                 compatible = "qcom,sm8150-rpmh-clk";
 468                                 #clock-cells = <1>;
 469                                 clock-names = "xo";
 470                                 clocks = <&xo_board>;
 471                         };
 472                 };
 473         };
 474
 475         timer {
 476                 compatible = "arm,armv8-timer";
 477                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 478                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 479                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 480                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 481         };
 482 };