src/arm64/renesas/r8a77961.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
   4  *
   5  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   6  */
   7
   8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/power/r8a77961-sysc.h>
  11
  12 #define CPG_AUDIO_CLK_I         R8A77961_CLK_S0D4
  13
  14 / {
  15         compatible = "renesas,r8a77961";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         /*
  20          * The external audio clocks are configured as 0 Hz fixed frequency
  21          * clocks by default.
  22          * Boards that provide audio clocks should override them.
  23          */
  24         audio_clk_a: audio_clk_a {
  25                 compatible = "fixed-clock";
  26                 #clock-cells = <0>;
  27                 clock-frequency = <0>;
  28         };
  29
  30         audio_clk_b: audio_clk_b {
  31                 compatible = "fixed-clock";
  32                 #clock-cells = <0>;
  33                 clock-frequency = <0>;
  34         };
  35
  36         audio_clk_c: audio_clk_c {
  37                 compatible = "fixed-clock";
  38                 #clock-cells = <0>;
  39                 clock-frequency = <0>;
  40         };
  41
  42         /* External CAN clock - to be overridden by boards that provide it */
  43         can_clk: can {
  44                 compatible = "fixed-clock";
  45                 #clock-cells = <0>;
  46                 clock-frequency = <0>;
  47         };
  48
  49         cluster0_opp: opp_table0 {
  50                 compatible = "operating-points-v2";
  51                 opp-shared;
  52
  53                 opp-500000000 {
  54                         opp-hz = /bits/ 64 <500000000>;
  55                         opp-microvolt = <820000>;
  56                         clock-latency-ns = <300000>;
  57                 };
  58                 opp-1000000000 {
  59                         opp-hz = /bits/ 64 <1000000000>;
  60                         opp-microvolt = <820000>;
  61                         clock-latency-ns = <300000>;
  62                 };
  63                 opp-1500000000 {
  64                         opp-hz = /bits/ 64 <1500000000>;
  65                         opp-microvolt = <820000>;
  66                         clock-latency-ns = <300000>;
  67                 };
  68                 opp-1600000000 {
  69                         opp-hz = /bits/ 64 <1600000000>;
  70                         opp-microvolt = <900000>;
  71                         clock-latency-ns = <300000>;
  72                         turbo-mode;
  73                 };
  74                 opp-1700000000 {
  75                         opp-hz = /bits/ 64 <1700000000>;
  76                         opp-microvolt = <900000>;
  77                         clock-latency-ns = <300000>;
  78                         turbo-mode;
  79                 };
  80                 opp-1800000000 {
  81                         opp-hz = /bits/ 64 <1800000000>;
  82                         opp-microvolt = <960000>;
  83                         clock-latency-ns = <300000>;
  84                         turbo-mode;
  85                 };
  86         };
  87
  88         cluster1_opp: opp_table1 {
  89                 compatible = "operating-points-v2";
  90                 opp-shared;
  91
  92                 opp-800000000 {
  93                         opp-hz = /bits/ 64 <800000000>;
  94                         opp-microvolt = <820000>;
  95                         clock-latency-ns = <300000>;
  96                 };
  97                 opp-1000000000 {
  98                         opp-hz = /bits/ 64 <1000000000>;
  99                         opp-microvolt = <820000>;
 100                         clock-latency-ns = <300000>;
 101                 };
 102                 opp-1200000000 {
 103                         opp-hz = /bits/ 64 <1200000000>;
 104                         opp-microvolt = <820000>;
 105                         clock-latency-ns = <300000>;
 106                 };
 107                 opp-1300000000 {
 108                         opp-hz = /bits/ 64 <1300000000>;
 109                         opp-microvolt = <820000>;
 110                         clock-latency-ns = <300000>;
 111                         turbo-mode;
 112                 };
 113         };
 114
 115         cpus {
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118
 119                 cpu-map {
 120                         cluster0 {
 121                                 core0 {
 122                                         cpu = <&a57_0>;
 123                                 };
 124                                 core1 {
 125                                         cpu = <&a57_1>;
 126                                 };
 127                         };
 128
 129                         cluster1 {
 130                                 core0 {
 131                                         cpu = <&a53_0>;
 132                                 };
 133                                 core1 {
 134                                         cpu = <&a53_1>;
 135                                 };
 136                                 core2 {
 137                                         cpu = <&a53_2>;
 138                                 };
 139                                 core3 {
 140                                         cpu = <&a53_3>;
 141                                 };
 142                         };
 143                 };
 144
 145                 a57_0: cpu@0 {
 146                         compatible = "arm,cortex-a57";
 147                         reg = <0x0>;
 148                         device_type = "cpu";
 149                         power-domains = <&sysc R8A77961_PD_CA57_CPU0>;
 150                         next-level-cache = <&L2_CA57>;
 151                         enable-method = "psci";
 152                         cpu-idle-states = <&CPU_SLEEP_0>;
 153                         dynamic-power-coefficient = <854>;
 154                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
 155                         operating-points-v2 = <&cluster0_opp>;
 156                         capacity-dmips-mhz = <1024>;
 157                         #cooling-cells = <2>;
 158                 };
 159
 160                 a57_1: cpu@1 {
 161                         compatible = "arm,cortex-a57";
 162                         reg = <0x1>;
 163                         device_type = "cpu";
 164                         power-domains = <&sysc R8A77961_PD_CA57_CPU1>;
 165                         next-level-cache = <&L2_CA57>;
 166                         enable-method = "psci";
 167                         cpu-idle-states = <&CPU_SLEEP_0>;
 168                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z>;
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         capacity-dmips-mhz = <1024>;
 171                         #cooling-cells = <2>;
 172                 };
 173
 174                 a53_0: cpu@100 {
 175                         compatible = "arm,cortex-a53";
 176                         reg = <0x100>;
 177                         device_type = "cpu";
 178                         power-domains = <&sysc R8A77961_PD_CA53_CPU0>;
 179                         next-level-cache = <&L2_CA53>;
 180                         enable-method = "psci";
 181                         cpu-idle-states = <&CPU_SLEEP_1>;
 182                         #cooling-cells = <2>;
 183                         dynamic-power-coefficient = <277>;
 184                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                         capacity-dmips-mhz = <535>;
 187                 };
 188
 189                 a53_1: cpu@101 {
 190                         compatible = "arm,cortex-a53";
 191                         reg = <0x101>;
 192                         device_type = "cpu";
 193                         power-domains = <&sysc R8A77961_PD_CA53_CPU1>;
 194                         next-level-cache = <&L2_CA53>;
 195                         enable-method = "psci";
 196                         cpu-idle-states = <&CPU_SLEEP_1>;
 197                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 198                         operating-points-v2 = <&cluster1_opp>;
 199                         capacity-dmips-mhz = <535>;
 200                 };
 201
 202                 a53_2: cpu@102 {
 203                         compatible = "arm,cortex-a53";
 204                         reg = <0x102>;
 205                         device_type = "cpu";
 206                         power-domains = <&sysc R8A77961_PD_CA53_CPU2>;
 207                         next-level-cache = <&L2_CA53>;
 208                         enable-method = "psci";
 209                         cpu-idle-states = <&CPU_SLEEP_1>;
 210                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 211                         operating-points-v2 = <&cluster1_opp>;
 212                         capacity-dmips-mhz = <535>;
 213                 };
 214
 215                 a53_3: cpu@103 {
 216                         compatible = "arm,cortex-a53";
 217                         reg = <0x103>;
 218                         device_type = "cpu";
 219                         power-domains = <&sysc R8A77961_PD_CA53_CPU3>;
 220                         next-level-cache = <&L2_CA53>;
 221                         enable-method = "psci";
 222                         cpu-idle-states = <&CPU_SLEEP_1>;
 223                         clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>;
 224                         operating-points-v2 = <&cluster1_opp>;
 225                         capacity-dmips-mhz = <535>;
 226                 };
 227
 228                 L2_CA57: cache-controller-0 {
 229                         compatible = "cache";
 230                         power-domains = <&sysc R8A77961_PD_CA57_SCU>;
 231                         cache-unified;
 232                         cache-level = <2>;
 233                 };
 234
 235                 L2_CA53: cache-controller-1 {
 236                         compatible = "cache";
 237                         power-domains = <&sysc R8A77961_PD_CA53_SCU>;
 238                         cache-unified;
 239                         cache-level = <2>;
 240                 };
 241
 242                 idle-states {
 243                         entry-method = "psci";
 244
 245                         CPU_SLEEP_0: cpu-sleep-0 {
 246                                 compatible = "arm,idle-state";
 247                                 arm,psci-suspend-param = <0x0010000>;
 248                                 local-timer-stop;
 249                                 entry-latency-us = <400>;
 250                                 exit-latency-us = <500>;
 251                                 min-residency-us = <4000>;
 252                         };
 253
 254                         CPU_SLEEP_1: cpu-sleep-1 {
 255                                 compatible = "arm,idle-state";
 256                                 arm,psci-suspend-param = <0x0010000>;
 257                                 local-timer-stop;
 258                                 entry-latency-us = <700>;
 259                                 exit-latency-us = <700>;
 260                                 min-residency-us = <5000>;
 261                         };
 262                 };
 263         };
 264
 265         extal_clk: extal {
 266                 compatible = "fixed-clock";
 267                 #clock-cells = <0>;
 268                 /* This value must be overridden by the board */
 269                 clock-frequency = <0>;
 270         };
 271
 272         extalr_clk: extalr {
 273                 compatible = "fixed-clock";
 274                 #clock-cells = <0>;
 275                 /* This value must be overridden by the board */
 276                 clock-frequency = <0>;
 277         };
 278
 279         /* External PCIe clock - can be overridden by the board */
 280         pcie_bus_clk: pcie_bus {
 281                 compatible = "fixed-clock";
 282                 #clock-cells = <0>;
 283                 clock-frequency = <0>;
 284         };
 285
 286         pmu_a53 {
 287                 compatible = "arm,cortex-a53-pmu";
 288                 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
 289                                       <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 290                                       <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
 291                                       <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 292                 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
 293         };
 294
 295         pmu_a57 {
 296                 compatible = "arm,cortex-a57-pmu";
 297                 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 298                                       <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 299                 interrupt-affinity = <&a57_0>, <&a57_1>;
 300         };
 301
 302         psci {
 303                 compatible = "arm,psci-1.0", "arm,psci-0.2";
 304                 method = "smc";
 305         };
 306
 307         /* External SCIF clock - to be overridden by boards that provide it */
 308         scif_clk: scif {
 309                 compatible = "fixed-clock";
 310                 #clock-cells = <0>;
 311                 clock-frequency = <0>;
 312         };
 313
 314         soc {
 315                 compatible = "simple-bus";
 316                 interrupt-parent = <&gic>;
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 ranges;
 320
 321                 rwdt: watchdog@e6020000 {
 322                         compatible = "renesas,r8a77961-wdt",
 323                                      "renesas,rcar-gen3-wdt";
 324                         reg = <0 0xe6020000 0 0x0c>;
 325                         clocks = <&cpg CPG_MOD 402>;
 326                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 327                         resets = <&cpg 402>;
 328                         status = "disabled";
 329                 };
 330
 331                 gpio0: gpio@e6050000 {
 332                         compatible = "renesas,gpio-r8a77961",
 333                                      "renesas,rcar-gen3-gpio";
 334                         reg = <0 0xe6050000 0 0x50>;
 335                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 336                         #gpio-cells = <2>;
 337                         gpio-controller;
 338                         gpio-ranges = <&pfc 0 0 16>;
 339                         #interrupt-cells = <2>;
 340                         interrupt-controller;
 341                         clocks = <&cpg CPG_MOD 912>;
 342                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 343                         resets = <&cpg 912>;
 344                 };
 345
 346                 gpio1: gpio@e6051000 {
 347                         compatible = "renesas,gpio-r8a77961",
 348                                      "renesas,rcar-gen3-gpio";
 349                         reg = <0 0xe6051000 0 0x50>;
 350                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 351                         #gpio-cells = <2>;
 352                         gpio-controller;
 353                         gpio-ranges = <&pfc 0 32 29>;
 354                         #interrupt-cells = <2>;
 355                         interrupt-controller;
 356                         clocks = <&cpg CPG_MOD 911>;
 357                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 358                         resets = <&cpg 911>;
 359                 };
 360
 361                 gpio2: gpio@e6052000 {
 362                         compatible = "renesas,gpio-r8a77961",
 363                                      "renesas,rcar-gen3-gpio";
 364                         reg = <0 0xe6052000 0 0x50>;
 365                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 366                         #gpio-cells = <2>;
 367                         gpio-controller;
 368                         gpio-ranges = <&pfc 0 64 15>;
 369                         #interrupt-cells = <2>;
 370                         interrupt-controller;
 371                         clocks = <&cpg CPG_MOD 910>;
 372                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 373                         resets = <&cpg 910>;
 374                 };
 375
 376                 gpio3: gpio@e6053000 {
 377                         compatible = "renesas,gpio-r8a77961",
 378                                      "renesas,rcar-gen3-gpio";
 379                         reg = <0 0xe6053000 0 0x50>;
 380                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 381                         #gpio-cells = <2>;
 382                         gpio-controller;
 383                         gpio-ranges = <&pfc 0 96 16>;
 384                         #interrupt-cells = <2>;
 385                         interrupt-controller;
 386                         clocks = <&cpg CPG_MOD 909>;
 387                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 388                         resets = <&cpg 909>;
 389                 };
 390
 391                 gpio4: gpio@e6054000 {
 392                         compatible = "renesas,gpio-r8a77961",
 393                                      "renesas,rcar-gen3-gpio";
 394                         reg = <0 0xe6054000 0 0x50>;
 395                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 396                         #gpio-cells = <2>;
 397                         gpio-controller;
 398                         gpio-ranges = <&pfc 0 128 18>;
 399                         #interrupt-cells = <2>;
 400                         interrupt-controller;
 401                         clocks = <&cpg CPG_MOD 908>;
 402                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 403                         resets = <&cpg 908>;
 404                 };
 405
 406                 gpio5: gpio@e6055000 {
 407                         compatible = "renesas,gpio-r8a77961",
 408                                      "renesas,rcar-gen3-gpio";
 409                         reg = <0 0xe6055000 0 0x50>;
 410                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 411                         #gpio-cells = <2>;
 412                         gpio-controller;
 413                         gpio-ranges = <&pfc 0 160 26>;
 414                         #interrupt-cells = <2>;
 415                         interrupt-controller;
 416                         clocks = <&cpg CPG_MOD 907>;
 417                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 418                         resets = <&cpg 907>;
 419                 };
 420
 421                 gpio6: gpio@e6055400 {
 422                         compatible = "renesas,gpio-r8a77961",
 423                                      "renesas,rcar-gen3-gpio";
 424                         reg = <0 0xe6055400 0 0x50>;
 425                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 426                         #gpio-cells = <2>;
 427                         gpio-controller;
 428                         gpio-ranges = <&pfc 0 192 32>;
 429                         #interrupt-cells = <2>;
 430                         interrupt-controller;
 431                         clocks = <&cpg CPG_MOD 906>;
 432                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 433                         resets = <&cpg 906>;
 434                 };
 435
 436                 gpio7: gpio@e6055800 {
 437                         compatible = "renesas,gpio-r8a77961",
 438                                      "renesas,rcar-gen3-gpio";
 439                         reg = <0 0xe6055800 0 0x50>;
 440                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 441                         #gpio-cells = <2>;
 442                         gpio-controller;
 443                         gpio-ranges = <&pfc 0 224 4>;
 444                         #interrupt-cells = <2>;
 445                         interrupt-controller;
 446                         clocks = <&cpg CPG_MOD 905>;
 447                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 448                         resets = <&cpg 905>;
 449                 };
 450
 451                 pfc: pin-controller@e6060000 {
 452                         compatible = "renesas,pfc-r8a77961";
 453                         reg = <0 0xe6060000 0 0x50c>;
 454                 };
 455
 456                 cpg: clock-controller@e6150000 {
 457                         compatible = "renesas,r8a77961-cpg-mssr";
 458                         reg = <0 0xe6150000 0 0x1000>;
 459                         clocks = <&extal_clk>, <&extalr_clk>;
 460                         clock-names = "extal", "extalr";
 461                         #clock-cells = <2>;
 462                         #power-domain-cells = <0>;
 463                         #reset-cells = <1>;
 464                 };
 465
 466                 rst: reset-controller@e6160000 {
 467                         compatible = "renesas,r8a77961-rst";
 468                         reg = <0 0xe6160000 0 0x0200>;
 469                 };
 470
 471                 sysc: system-controller@e6180000 {
 472                         compatible = "renesas,r8a77961-sysc";
 473                         reg = <0 0xe6180000 0 0x0400>;
 474                         #power-domain-cells = <1>;
 475                 };
 476
 477                 intc_ex: interrupt-controller@e61c0000 {
 478                         #interrupt-cells = <2>;
 479                         interrupt-controller;
 480                         reg = <0 0xe61c0000 0 0x200>;
 481                         /* placeholder */
 482                 };
 483
 484                 i2c0: i2c@e6500000 {
 485                         #address-cells = <1>;
 486                         #size-cells = <0>;
 487                         compatible = "renesas,i2c-r8a77961",
 488                                      "renesas,rcar-gen3-i2c";
 489                         reg = <0 0xe6500000 0 0x40>;
 490                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 491                         clocks = <&cpg CPG_MOD 931>;
 492                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 493                         resets = <&cpg 931>;
 494                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 495                                <&dmac2 0x91>, <&dmac2 0x90>;
 496                         dma-names = "tx", "rx", "tx", "rx";
 497                         i2c-scl-internal-delay-ns = <110>;
 498                         status = "disabled";
 499                 };
 500
 501                 i2c1: i2c@e6508000 {
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         compatible = "renesas,i2c-r8a77961",
 505                                      "renesas,rcar-gen3-i2c";
 506                         reg = <0 0xe6508000 0 0x40>;
 507                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&cpg CPG_MOD 930>;
 509                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 510                         resets = <&cpg 930>;
 511                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 512                                <&dmac2 0x93>, <&dmac2 0x92>;
 513                         dma-names = "tx", "rx", "tx", "rx";
 514                         i2c-scl-internal-delay-ns = <6>;
 515                         status = "disabled";
 516                 };
 517
 518                 i2c2: i2c@e6510000 {
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         compatible = "renesas,i2c-r8a77961",
 522                                      "renesas,rcar-gen3-i2c";
 523                         reg = <0 0xe6510000 0 0x40>;
 524                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 525                         clocks = <&cpg CPG_MOD 929>;
 526                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 527                         resets = <&cpg 929>;
 528                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 529                                <&dmac2 0x95>, <&dmac2 0x94>;
 530                         dma-names = "tx", "rx", "tx", "rx";
 531                         i2c-scl-internal-delay-ns = <6>;
 532                         status = "disabled";
 533                 };
 534
 535                 i2c3: i2c@e66d0000 {
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         compatible = "renesas,i2c-r8a77961",
 539                                      "renesas,rcar-gen3-i2c";
 540                         reg = <0 0xe66d0000 0 0x40>;
 541                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&cpg CPG_MOD 928>;
 543                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 544                         resets = <&cpg 928>;
 545                         dmas = <&dmac0 0x97>, <&dmac0 0x96>;
 546                         dma-names = "tx", "rx";
 547                         i2c-scl-internal-delay-ns = <110>;
 548                         status = "disabled";
 549                 };
 550
 551                 i2c4: i2c@e66d8000 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         compatible = "renesas,i2c-r8a77961",
 555                                      "renesas,rcar-gen3-i2c";
 556                         reg = <0 0xe66d8000 0 0x40>;
 557                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&cpg CPG_MOD 927>;
 559                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 560                         resets = <&cpg 927>;
 561                         dmas = <&dmac0 0x99>, <&dmac0 0x98>;
 562                         dma-names = "tx", "rx";
 563                         i2c-scl-internal-delay-ns = <110>;
 564                         status = "disabled";
 565                 };
 566
 567                 i2c5: i2c@e66e0000 {
 568                         #address-cells = <1>;
 569                         #size-cells = <0>;
 570                         compatible = "renesas,i2c-r8a77961",
 571                                      "renesas,rcar-gen3-i2c";
 572                         reg = <0 0xe66e0000 0 0x40>;
 573                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&cpg CPG_MOD 919>;
 575                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 576                         resets = <&cpg 919>;
 577                         dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
 578                         dma-names = "tx", "rx";
 579                         i2c-scl-internal-delay-ns = <110>;
 580                         status = "disabled";
 581                 };
 582
 583                 i2c6: i2c@e66e8000 {
 584                         #address-cells = <1>;
 585                         #size-cells = <0>;
 586                         compatible = "renesas,i2c-r8a77961",
 587                                      "renesas,rcar-gen3-i2c";
 588                         reg = <0 0xe66e8000 0 0x40>;
 589                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cpg CPG_MOD 918>;
 591                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 592                         resets = <&cpg 918>;
 593                         dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
 594                         dma-names = "tx", "rx";
 595                         i2c-scl-internal-delay-ns = <6>;
 596                         status = "disabled";
 597                 };
 598
 599                 i2c_dvfs: i2c@e60b0000 {
 600                         #address-cells = <1>;
 601                         #size-cells = <0>;
 602                         compatible = "renesas,iic-r8a77961",
 603                                      "renesas,rcar-gen3-iic",
 604                                      "renesas,rmobile-iic";
 605                         reg = <0 0xe60b0000 0 0x425>;
 606                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 607                         clocks = <&cpg CPG_MOD 926>;
 608                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 609                         resets = <&cpg 926>;
 610                         dmas = <&dmac0 0x11>, <&dmac0 0x10>;
 611                         dma-names = "tx", "rx";
 612                         status = "disabled";
 613                 };
 614
 615
 616                 hscif1: serial@e6550000 {
 617                         reg = <0 0xe6550000 0 0x60>;
 618                         /* placeholder */
 619                 };
 620
 621                 hsusb: usb@e6590000 {
 622                         reg = <0 0xe6590000 0 0x200>;
 623                         /* placeholder */
 624                 };
 625
 626                 usb3_phy0: usb-phy@e65ee000 {
 627                         reg = <0 0xe65ee000 0 0x90>;
 628                         #phy-cells = <0>;
 629                         /* placeholder */
 630                 };
 631
 632                 dmac0: dma-controller@e6700000 {
 633                         compatible = "renesas,dmac-r8a77961",
 634                                      "renesas,rcar-dmac";
 635                         reg = <0 0xe6700000 0 0x10000>;
 636                         interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 638                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 643                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 644                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 646                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
 647                                      <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 648                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 652                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
 653                         interrupt-names = "error",
 654                                         "ch0", "ch1", "ch2", "ch3",
 655                                         "ch4", "ch5", "ch6", "ch7",
 656                                         "ch8", "ch9", "ch10", "ch11",
 657                                         "ch12", "ch13", "ch14", "ch15";
 658                         clocks = <&cpg CPG_MOD 219>;
 659                         clock-names = "fck";
 660                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 661                         resets = <&cpg 219>;
 662                         #dma-cells = <1>;
 663                         dma-channels = <16>;
 664                 };
 665
 666                 dmac1: dma-controller@e7300000 {
 667                         compatible = "renesas,dmac-r8a77961",
 668                                      "renesas,rcar-dmac";
 669                         reg = <0 0xe7300000 0 0x10000>;
 670                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 671                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 672                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 673                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 674                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 675                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
 679                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
 680                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
 681                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 687                         interrupt-names = "error",
 688                                         "ch0", "ch1", "ch2", "ch3",
 689                                         "ch4", "ch5", "ch6", "ch7",
 690                                         "ch8", "ch9", "ch10", "ch11",
 691                                         "ch12", "ch13", "ch14", "ch15";
 692                         clocks = <&cpg CPG_MOD 218>;
 693                         clock-names = "fck";
 694                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 695                         resets = <&cpg 218>;
 696                         #dma-cells = <1>;
 697                         dma-channels = <16>;
 698                 };
 699
 700                 dmac2: dma-controller@e7310000 {
 701                         compatible = "renesas,dmac-r8a77961",
 702                                      "renesas,rcar-dmac";
 703                         reg = <0 0xe7310000 0 0x10000>;
 704                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
 721                         interrupt-names = "error",
 722                                         "ch0", "ch1", "ch2", "ch3",
 723                                         "ch4", "ch5", "ch6", "ch7",
 724                                         "ch8", "ch9", "ch10", "ch11",
 725                                         "ch12", "ch13", "ch14", "ch15";
 726                         clocks = <&cpg CPG_MOD 217>;
 727                         clock-names = "fck";
 728                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 729                         resets = <&cpg 217>;
 730                         #dma-cells = <1>;
 731                         dma-channels = <16>;
 732                 };
 733
 734                 avb: ethernet@e6800000 {
 735                         compatible = "renesas,etheravb-r8a77961",
 736                                      "renesas,etheravb-rcar-gen3";
 737                         reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
 738                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 762                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 763                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 764                                           "ch4", "ch5", "ch6", "ch7",
 765                                           "ch8", "ch9", "ch10", "ch11",
 766                                           "ch12", "ch13", "ch14", "ch15",
 767                                           "ch16", "ch17", "ch18", "ch19",
 768                                           "ch20", "ch21", "ch22", "ch23",
 769                                           "ch24";
 770                         clocks = <&cpg CPG_MOD 812>;
 771                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 772                         resets = <&cpg 812>;
 773                         phy-mode = "rgmii";
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776                         status = "disabled";
 777                 };
 778
 779                 pwm1: pwm@e6e31000 {
 780                         reg = <0 0xe6e31000 0 8>;
 781                         #pwm-cells = <2>;
 782                         /* placeholder */
 783                 };
 784
 785                 scif1: serial@e6e68000 {
 786                         reg = <0 0xe6e68000 0 64>;
 787                         /* placeholder */
 788                 };
 789
 790                 scif2: serial@e6e88000 {
 791                         compatible = "renesas,scif-r8a77961",
 792                                      "renesas,rcar-gen3-scif", "renesas,scif";
 793                         reg = <0 0xe6e88000 0 64>;
 794                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&cpg CPG_MOD 310>,
 796                                  <&cpg CPG_CORE R8A77961_CLK_S3D1>,
 797                                  <&scif_clk>;
 798                         clock-names = "fck", "brg_int", "scif_clk";
 799                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 800                         resets = <&cpg 310>;
 801                         status = "disabled";
 802                 };
 803
 804                 vin0: video@e6ef0000 {
 805                         reg = <0 0xe6ef0000 0 0x1000>;
 806                         /* placeholder */
 807                 };
 808
 809                 vin1: video@e6ef1000 {
 810                         reg = <0 0xe6ef1000 0 0x1000>;
 811                         /* placeholder */
 812                 };
 813
 814                 vin2: video@e6ef2000 {
 815                         reg = <0 0xe6ef2000 0 0x1000>;
 816                         /* placeholder */
 817                 };
 818
 819                 vin3: video@e6ef3000 {
 820                         reg = <0 0xe6ef3000 0 0x1000>;
 821                         /* placeholder */
 822                 };
 823
 824                 vin4: video@e6ef4000 {
 825                         reg = <0 0xe6ef4000 0 0x1000>;
 826                         /* placeholder */
 827                 };
 828
 829                 vin5: video@e6ef5000 {
 830                         reg = <0 0xe6ef5000 0 0x1000>;
 831                         /* placeholder */
 832                 };
 833
 834                 vin6: video@e6ef6000 {
 835                         reg = <0 0xe6ef6000 0 0x1000>;
 836                         /* placeholder */
 837                 };
 838
 839                 vin7: video@e6ef7000 {
 840                         reg = <0 0xe6ef7000 0 0x1000>;
 841                         /* placeholder */
 842                 };
 843
 844                 rcar_sound: sound@ec500000 {
 845                         reg = <0 0xec500000 0 0x1000>, /* SCU */
 846                               <0 0xec5a0000 0 0x100>,  /* ADG */
 847                               <0 0xec540000 0 0x1000>, /* SSIU */
 848                               <0 0xec541000 0 0x280>,  /* SSI */
 849                               <0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
 850                         /* placeholder */
 851                         rcar_sound,dvc {
 852                                 dvc0: dvc-0 { };
 853                                 dvc1: dvc-1 { };
 854                         };
 855
 856                         rcar_sound,src {
 857                                 src0: src-0 { };
 858                                 src1: src-1 { };
 859                         };
 860
 861                         rcar_sound,ssi {
 862                                 ssi0: ssi-0 { };
 863                                 ssi1: ssi-1 { };
 864                         };
 865                 };
 866
 867                 xhci0: usb@ee000000 {
 868                         reg = <0 0xee000000 0 0xc00>;
 869                         /* placeholder */
 870                 };
 871
 872                 usb3_peri0: usb@ee020000 {
 873                         reg = <0 0xee020000 0 0x400>;
 874                         /* placeholder */
 875                 };
 876
 877                 ohci0: usb@ee080000 {
 878                         reg = <0 0xee080000 0 0x100>;
 879                         /* placeholder */
 880                 };
 881
 882                 ohci1: usb@ee0a0000 {
 883                         reg = <0 0xee0a0000 0 0x100>;
 884                         /* placeholder */
 885                 };
 886
 887                 ehci0: usb@ee080100 {
 888                         reg = <0 0xee080100 0 0x100>;
 889                         /* placeholder */
 890                 };
 891
 892                 ehci1: usb@ee0a0100 {
 893                         reg = <0 0xee0a0100 0 0x100>;
 894                         /* placeholder */
 895                 };
 896
 897                 usb2_phy0: usb-phy@ee080200 {
 898                         reg = <0 0xee080200 0 0x700>;
 899                         /* placeholder */
 900                 };
 901
 902                 usb2_phy1: usb-phy@ee0a0200 {
 903                         reg = <0 0xee0a0200 0 0x700>;
 904                         /* placeholder */
 905                 };
 906
 907                 sdhi0: sd@ee100000 {
 908                         compatible = "renesas,sdhi-r8a77961",
 909                                      "renesas,rcar-gen3-sdhi";
 910                         reg = <0 0xee100000 0 0x2000>;
 911                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 912                         clocks = <&cpg CPG_MOD 314>;
 913                         max-frequency = <200000000>;
 914                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 915                         resets = <&cpg 314>;
 916                         status = "disabled";
 917                 };
 918
 919                 sdhi1: sd@ee120000 {
 920                         compatible = "renesas,sdhi-r8a77961",
 921                                      "renesas,rcar-gen3-sdhi";
 922                         reg = <0 0xee120000 0 0x2000>;
 923                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 924                         clocks = <&cpg CPG_MOD 313>;
 925                         max-frequency = <200000000>;
 926                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 927                         resets = <&cpg 313>;
 928                         status = "disabled";
 929                 };
 930
 931                 sdhi2: sd@ee140000 {
 932                         compatible = "renesas,sdhi-r8a77961",
 933                                      "renesas,rcar-gen3-sdhi";
 934                         reg = <0 0xee140000 0 0x2000>;
 935                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 936                         clocks = <&cpg CPG_MOD 312>;
 937                         max-frequency = <200000000>;
 938                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 939                         resets = <&cpg 312>;
 940                         status = "disabled";
 941                 };
 942
 943                 sdhi3: sd@ee160000 {
 944                         compatible = "renesas,sdhi-r8a77961",
 945                                      "renesas,rcar-gen3-sdhi";
 946                         reg = <0 0xee160000 0 0x2000>;
 947                         interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&cpg CPG_MOD 311>;
 949                         max-frequency = <200000000>;
 950                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 951                         resets = <&cpg 311>;
 952                         status = "disabled";
 953                 };
 954
 955                 gic: interrupt-controller@f1010000 {
 956                         compatible = "arm,gic-400";
 957                         #interrupt-cells = <3>;
 958                         #address-cells = <0>;
 959                         interrupt-controller;
 960                         reg = <0x0 0xf1010000 0 0x1000>,
 961                               <0x0 0xf1020000 0 0x20000>,
 962                               <0x0 0xf1040000 0 0x20000>,
 963                               <0x0 0xf1060000 0 0x20000>;
 964                         interrupts = <GIC_PPI 9
 965                                         (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 966                         clocks = <&cpg CPG_MOD 408>;
 967                         clock-names = "clk";
 968                         power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
 969                         resets = <&cpg 408>;
 970                 };
 971
 972                 pciec0: pcie@fe000000 {
 973                         reg = <0 0xfe000000 0 0x80000>;
 974                         /* placeholder */
 975                 };
 976
 977                 pciec1: pcie@ee800000 {
 978                         reg = <0 0xee800000 0 0x80000>;
 979                         /* placeholder */
 980                 };
 981
 982                 csi20: csi2@fea80000 {
 983                         reg = <0 0xfea80000 0 0x10000>;
 984                         /* placeholder */
 985
 986                         ports {
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989
 990                                 port@1 {
 991                                         #address-cells = <1>;
 992                                         #size-cells = <0>;
 993                                         reg = <1>;
 994                                 };
 995                         };
 996                 };
 997
 998                 csi40: csi2@feaa0000 {
 999                         reg = <0 0xfeaa0000 0 0x10000>;
1000                         /* placeholder */
1001
1002                         ports {
1003                                 #address-cells = <1>;
1004                                 #size-cells = <0>;
1005
1006                                 port@1 {
1007                                         #address-cells = <1>;
1008                                         #size-cells = <0>;
1009
1010                                         reg = <1>;
1011                                 };
1012                         };
1013                 };
1014
1015                 hdmi0: hdmi@fead0000 {
1016                         reg = <0 0xfead0000 0 0x10000>;
1017                         /* placeholder */
1018
1019                         ports {
1020                                 #address-cells = <1>;
1021                                 #size-cells = <0>;
1022                                 port@0 {
1023                                         reg = <0>;
1024                                 };
1025                                 port@1 {
1026                                         reg = <1>;
1027                                 };
1028                                 port@2 {
1029                                         /* HDMI sound */
1030                                         reg = <2>;
1031                                 };
1032                         };
1033                 };
1034
1035                 du: display@feb00000 {
1036                         reg = <0 0xfeb00000 0 0x70000>;
1037                         /* placeholder */
1038
1039                         ports {
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042
1043                                 port@0 {
1044                                         reg = <0>;
1045                                         du_out_rgb: endpoint {
1046                                         };
1047                                 };
1048                                 port@1 {
1049                                         reg = <1>;
1050                                         du_out_hdmi0: endpoint {
1051                                         };
1052                                 };
1053                                 port@2 {
1054                                         reg = <2>;
1055                                         du_out_lvds0: endpoint {
1056                                         };
1057                                 };
1058                         };
1059                 };
1060
1061                 prr: chipid@fff00044 {
1062                         compatible = "renesas,prr";
1063                         reg = <0 0xfff00044 0 4>;
1064                 };
1065         };
1066
1067         timer {
1068                 compatible = "arm,armv8-timer";
1069                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1070                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1071                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
1072                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
1073         };
1074
1075         /* External USB clocks - can be overridden by the board */
1076         usb3s0_clk: usb3s0 {
1077                 compatible = "fixed-clock";
1078                 #clock-cells = <0>;
1079                 clock-frequency = <0>;
1080         };
1081
1082         usb_extal_clk: usb_extal {
1083                 compatible = "fixed-clock";
1084                 #clock-cells = <0>;
1085                 clock-frequency = <0>;
1086         };
1087 };