2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1990 William Jolitz.
5 * Copyright (c) 1991 The Regents of the University of California.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * from: @(#)npx.c 7.2 (Berkeley) 5/12/91
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/mutex.h>
48 #include <sys/sysctl.h>
49 #include <sys/sysent.h>
50 #include <machine/bus.h>
52 #include <sys/signalvar.h>
55 #include <machine/cputypes.h>
56 #include <machine/frame.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/md_var.h>
59 #include <machine/pcb.h>
60 #include <machine/psl.h>
61 #include <machine/resource.h>
62 #include <machine/specialreg.h>
63 #include <machine/segments.h>
64 #include <machine/ucontext.h>
65 #include <x86/ifunc.h>
68 * Floating point support.
71 #if defined(__GNUCLIKE_ASM) && !defined(lint)
73 #define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
74 #define fnclex() __asm __volatile("fnclex")
75 #define fninit() __asm __volatile("fninit")
76 #define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
77 #define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
78 #define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
79 #define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
80 #define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
81 #define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
84 xrstor32(char *addr, uint64_t mask)
90 __asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
94 xrstor64(char *addr, uint64_t mask)
100 __asm __volatile("xrstor64 %0" : : "m" (*addr), "a" (low), "d" (hi));
104 xsave32(char *addr, uint64_t mask)
110 __asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
115 xsave64(char *addr, uint64_t mask)
121 __asm __volatile("xsave64 %0" : "=m" (*addr) : "a" (low), "d" (hi) :
126 xsaveopt32(char *addr, uint64_t mask)
132 __asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
137 xsaveopt64(char *addr, uint64_t mask)
143 __asm __volatile("xsaveopt64 %0" : "=m" (*addr) : "a" (low), "d" (hi) :
147 #else /* !(__GNUCLIKE_ASM && !lint) */
149 void fldcw(u_short cw);
152 void fnstcw(caddr_t addr);
153 void fnstsw(caddr_t addr);
154 void fxsave(caddr_t addr);
155 void fxrstor(caddr_t addr);
156 void ldmxcsr(u_int csr);
157 void stmxcsr(u_int *csr);
158 void xrstor32(char *addr, uint64_t mask);
159 void xrstor64(char *addr, uint64_t mask);
160 void xsave32(char *addr, uint64_t mask);
161 void xsave64(char *addr, uint64_t mask);
162 void xsaveopt32(char *addr, uint64_t mask);
163 void xsaveopt64(char *addr, uint64_t mask);
165 #endif /* __GNUCLIKE_ASM && !lint */
167 #define start_emulating() load_cr0(rcr0() | CR0_TS)
168 #define stop_emulating() clts()
170 CTASSERT(sizeof(struct savefpu) == 512);
171 CTASSERT(sizeof(struct xstate_hdr) == 64);
172 CTASSERT(sizeof(struct savefpu_ymm) == 832);
175 * This requirement is to make it easier for asm code to calculate
176 * offset of the fpu save area from the pcb address. FPU save area
177 * must be 64-byte aligned.
179 CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
182 * Ensure the copy of XCR0 saved in a core is contained in the padding
185 CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savefpu, sv_pad) &&
186 X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savefpu));
188 static void fpu_clean_state(void);
190 SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
191 SYSCTL_NULL_INT_PTR, 1, "Floating point instructions executed in hardware");
193 int lazy_fpu_switch = 0;
194 SYSCTL_INT(_hw, OID_AUTO, lazy_fpu_switch, CTLFLAG_RD,
196 "Lazily load FPU context after context switch");
198 int use_xsave; /* non-static for cpu_switch.S */
199 uint64_t xsave_mask; /* the same */
200 static uma_zone_t fpu_save_area_zone;
201 static struct savefpu *fpu_initialstate;
203 struct xsave_area_elm_descr {
209 fpusave_xsaveopt64(void *addr)
211 xsaveopt64((char *)addr, xsave_mask);
215 fpusave_xsaveopt3264(void *addr)
217 if (SV_CURPROC_FLAG(SV_ILP32))
218 xsaveopt32((char *)addr, xsave_mask);
220 xsaveopt64((char *)addr, xsave_mask);
224 fpusave_xsave64(void *addr)
226 xsave64((char *)addr, xsave_mask);
230 fpusave_xsave3264(void *addr)
232 if (SV_CURPROC_FLAG(SV_ILP32))
233 xsave32((char *)addr, xsave_mask);
235 xsave64((char *)addr, xsave_mask);
239 fpurestore_xrstor64(void *addr)
241 xrstor64((char *)addr, xsave_mask);
245 fpurestore_xrstor3264(void *addr)
247 if (SV_CURPROC_FLAG(SV_ILP32))
248 xrstor32((char *)addr, xsave_mask);
250 xrstor64((char *)addr, xsave_mask);
254 fpusave_fxsave(void *addr)
257 fxsave((char *)addr);
261 fpurestore_fxrstor(void *addr)
264 fxrstor((char *)addr);
273 if ((cpu_feature2 & CPUID2_XSAVE) == 0)
276 TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
279 DEFINE_IFUNC(, void, fpusave, (void *), static)
284 return (fpusave_fxsave);
285 if ((cpu_stdext_feature & CPUID_EXTSTATE_XSAVEOPT) != 0) {
286 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
287 fpusave_xsaveopt64 : fpusave_xsaveopt3264);
289 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
290 fpusave_xsave64 : fpusave_xsave3264);
293 DEFINE_IFUNC(, void, fpurestore, (void *), static)
298 return (fpurestore_fxrstor);
299 return ((cpu_stdext_feature & CPUID_STDEXT_NFPUSG) != 0 ?
300 fpurestore_xrstor64 : fpurestore_xrstor3264);
304 fpususpend(void *addr)
315 fpuresume(void *addr)
323 load_xcr(XCR0, xsave_mask);
329 * Enable XSAVE if supported and allowed by user.
330 * Calculate the xsave_mask.
336 uint64_t xsave_mask_user;
341 cpuid_count(0xd, 0x0, cp);
342 xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
343 if ((cp[0] & xsave_mask) != xsave_mask)
344 panic("CPU0 does not support X87 or SSE: %x", cp[0]);
345 xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
346 xsave_mask_user = xsave_mask;
347 TUNABLE_ULONG_FETCH("hw.xsave_mask", &xsave_mask_user);
348 xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
349 xsave_mask &= xsave_mask_user;
350 if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
351 xsave_mask &= ~XFEATURE_AVX512;
352 if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
353 xsave_mask &= ~XFEATURE_MPX;
355 cpuid_count(0xd, 0x1, cp);
356 if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0) {
358 * Patch the XSAVE instruction in the cpu_switch code
359 * to XSAVEOPT. We assume that XSAVE encoding used
360 * REX byte, and set the bit 4 of the r/m byte.
362 * It seems that some BIOSes give control to the OS
363 * with CR0.WP already set, making the kernel text
364 * read-only before cpu_startup().
366 old_wp = disable_wp();
367 ctx_switch_xsave32[3] |= 0x10;
368 ctx_switch_xsave[3] |= 0x10;
374 * Calculate the fpu save area size.
382 cpuid_count(0xd, 0x0, cp);
383 cpu_max_ext_state_size = cp[1];
386 * Reload the cpu_feature2, since we enabled OSXSAVE.
389 cpu_feature2 = cp[2];
391 cpu_max_ext_state_size = sizeof(struct savefpu);
395 * Initialize the floating point unit.
408 load_cr4(rcr4() | CR4_XSAVE);
409 load_xcr(XCR0, xsave_mask);
413 * XCR0 shall be set up before CPU can report the save area size.
419 * It is too early for critical_enter() to work on AP.
421 saveintr = intr_disable();
424 control = __INITIAL_FPUCW__;
426 mxcsr = __INITIAL_MXCSR__;
429 intr_restore(saveintr);
433 * On the boot CPU we generate a clean state that is used to
434 * initialize the floating point unit when it is first used by a
438 fpuinitstate(void *arg __unused)
442 int cp[4], i, max_ext_n;
444 fpu_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
446 saveintr = intr_disable();
449 fpusave_fxsave(fpu_initialstate);
450 if (fpu_initialstate->sv_env.en_mxcsr_mask)
451 cpu_mxcsr_mask = fpu_initialstate->sv_env.en_mxcsr_mask;
453 cpu_mxcsr_mask = 0xFFBF;
456 * The fninit instruction does not modify XMM registers or x87
457 * registers (MM/ST). The fpusave call dumped the garbage
458 * contained in the registers after reset to the initial state
459 * saved. Clear XMM and x87 registers file image to make the
460 * startup program state and signal handler XMM/x87 register
461 * content predictable.
463 bzero(fpu_initialstate->sv_fp, sizeof(fpu_initialstate->sv_fp));
464 bzero(fpu_initialstate->sv_xmm, sizeof(fpu_initialstate->sv_xmm));
467 * Create a table describing the layout of the CPU Extended
471 xstate_bv = (uint64_t *)((char *)(fpu_initialstate + 1) +
472 offsetof(struct xstate_hdr, xstate_bv));
473 *xstate_bv = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
475 max_ext_n = flsl(xsave_mask);
476 xsave_area_desc = malloc(max_ext_n * sizeof(struct
477 xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
479 xsave_area_desc[0].offset = 0;
480 xsave_area_desc[0].size = 160;
482 xsave_area_desc[1].offset = 160;
483 xsave_area_desc[1].size = 416 - 160;
485 for (i = 2; i < max_ext_n; i++) {
486 cpuid_count(0xd, i, cp);
487 xsave_area_desc[i].offset = cp[1];
488 xsave_area_desc[i].size = cp[0];
492 fpu_save_area_zone = uma_zcreate("FPU_save_area",
493 cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
494 XSAVE_AREA_ALIGN - 1, 0);
497 intr_restore(saveintr);
499 /* EFIRT needs this to be initialized before we can enter our EFI environment */
500 SYSINIT(fpuinitstate, SI_SUB_DRIVERS, SI_ORDER_FIRST, fpuinitstate, NULL);
503 * Free coprocessor (if we have it).
506 fpuexit(struct thread *td)
510 if (curthread == PCPU_GET(fpcurthread)) {
512 fpusave(curpcb->pcb_save);
514 PCPU_SET(fpcurthread, NULL);
523 return (_MC_FPFMT_XMM);
527 * The following mechanism is used to ensure that the FPE_... value
528 * that is passed as a trapcode to the signal handler of the user
529 * process does not have more than one bit set.
531 * Multiple bits may be set if the user process modifies the control
532 * word while a status word bit is already set. While this is a sign
533 * of bad coding, we have no choise than to narrow them down to one
534 * bit, since we must not send a trapcode that is not exactly one of
537 * The mechanism has a static table with 127 entries. Each combination
538 * of the 7 FPU status word exception bits directly translates to a
539 * position in this table, where a single FPE_... value is stored.
540 * This FPE_... value stored there is considered the "most important"
541 * of the exception bits and will be sent as the signal code. The
542 * precedence of the bits is based upon Intel Document "Numerical
543 * Applications", Chapter "Special Computational Situations".
545 * The macro to choose one of these values does these steps: 1) Throw
546 * away status word bits that cannot be masked. 2) Throw away the bits
547 * currently masked in the control word, assuming the user isn't
548 * interested in them anymore. 3) Reinsert status word bit 7 (stack
549 * fault) if it is set, which cannot be masked but must be presered.
550 * 4) Use the remaining bits to point into the trapcode table.
552 * The 6 maskable bits in order of their preference, as stated in the
553 * above referenced Intel manual:
554 * 1 Invalid operation (FP_X_INV)
557 * 1c Operand of unsupported format
559 * 2 QNaN operand (not an exception, irrelavant here)
560 * 3 Any other invalid-operation not mentioned above or zero divide
561 * (FP_X_INV, FP_X_DZ)
562 * 4 Denormal operand (FP_X_DNML)
563 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
564 * 6 Inexact result (FP_X_IMP)
566 static char fpetable[128] = {
568 FPE_FLTINV, /* 1 - INV */
569 FPE_FLTUND, /* 2 - DNML */
570 FPE_FLTINV, /* 3 - INV | DNML */
571 FPE_FLTDIV, /* 4 - DZ */
572 FPE_FLTINV, /* 5 - INV | DZ */
573 FPE_FLTDIV, /* 6 - DNML | DZ */
574 FPE_FLTINV, /* 7 - INV | DNML | DZ */
575 FPE_FLTOVF, /* 8 - OFL */
576 FPE_FLTINV, /* 9 - INV | OFL */
577 FPE_FLTUND, /* A - DNML | OFL */
578 FPE_FLTINV, /* B - INV | DNML | OFL */
579 FPE_FLTDIV, /* C - DZ | OFL */
580 FPE_FLTINV, /* D - INV | DZ | OFL */
581 FPE_FLTDIV, /* E - DNML | DZ | OFL */
582 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
583 FPE_FLTUND, /* 10 - UFL */
584 FPE_FLTINV, /* 11 - INV | UFL */
585 FPE_FLTUND, /* 12 - DNML | UFL */
586 FPE_FLTINV, /* 13 - INV | DNML | UFL */
587 FPE_FLTDIV, /* 14 - DZ | UFL */
588 FPE_FLTINV, /* 15 - INV | DZ | UFL */
589 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
590 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
591 FPE_FLTOVF, /* 18 - OFL | UFL */
592 FPE_FLTINV, /* 19 - INV | OFL | UFL */
593 FPE_FLTUND, /* 1A - DNML | OFL | UFL */
594 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
595 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
596 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
597 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
598 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
599 FPE_FLTRES, /* 20 - IMP */
600 FPE_FLTINV, /* 21 - INV | IMP */
601 FPE_FLTUND, /* 22 - DNML | IMP */
602 FPE_FLTINV, /* 23 - INV | DNML | IMP */
603 FPE_FLTDIV, /* 24 - DZ | IMP */
604 FPE_FLTINV, /* 25 - INV | DZ | IMP */
605 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
606 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
607 FPE_FLTOVF, /* 28 - OFL | IMP */
608 FPE_FLTINV, /* 29 - INV | OFL | IMP */
609 FPE_FLTUND, /* 2A - DNML | OFL | IMP */
610 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
611 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
612 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
613 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
614 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
615 FPE_FLTUND, /* 30 - UFL | IMP */
616 FPE_FLTINV, /* 31 - INV | UFL | IMP */
617 FPE_FLTUND, /* 32 - DNML | UFL | IMP */
618 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
619 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
620 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
621 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
622 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
623 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
624 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
625 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
626 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
627 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
628 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
629 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
630 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
631 FPE_FLTSUB, /* 40 - STK */
632 FPE_FLTSUB, /* 41 - INV | STK */
633 FPE_FLTUND, /* 42 - DNML | STK */
634 FPE_FLTSUB, /* 43 - INV | DNML | STK */
635 FPE_FLTDIV, /* 44 - DZ | STK */
636 FPE_FLTSUB, /* 45 - INV | DZ | STK */
637 FPE_FLTDIV, /* 46 - DNML | DZ | STK */
638 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
639 FPE_FLTOVF, /* 48 - OFL | STK */
640 FPE_FLTSUB, /* 49 - INV | OFL | STK */
641 FPE_FLTUND, /* 4A - DNML | OFL | STK */
642 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
643 FPE_FLTDIV, /* 4C - DZ | OFL | STK */
644 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
645 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
646 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
647 FPE_FLTUND, /* 50 - UFL | STK */
648 FPE_FLTSUB, /* 51 - INV | UFL | STK */
649 FPE_FLTUND, /* 52 - DNML | UFL | STK */
650 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
651 FPE_FLTDIV, /* 54 - DZ | UFL | STK */
652 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
653 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
654 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
655 FPE_FLTOVF, /* 58 - OFL | UFL | STK */
656 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
657 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
658 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
659 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
660 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
661 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
662 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
663 FPE_FLTRES, /* 60 - IMP | STK */
664 FPE_FLTSUB, /* 61 - INV | IMP | STK */
665 FPE_FLTUND, /* 62 - DNML | IMP | STK */
666 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
667 FPE_FLTDIV, /* 64 - DZ | IMP | STK */
668 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
669 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
670 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
671 FPE_FLTOVF, /* 68 - OFL | IMP | STK */
672 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
673 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
674 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
675 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
676 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
677 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
678 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
679 FPE_FLTUND, /* 70 - UFL | IMP | STK */
680 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
681 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
682 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
683 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
684 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
685 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
686 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
687 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
688 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
689 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
690 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
691 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
692 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
693 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
694 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
698 * Read the FP status and control words, then generate si_code value
699 * for SIGFPE. The error code chosen will be one of the
700 * FPE_... macros. It will be sent as the second argument to old
701 * BSD-style signal handlers and as "siginfo_t->si_code" (second
702 * argument) to SA_SIGINFO signal handlers.
704 * Some time ago, we cleared the x87 exceptions with FNCLEX there.
705 * Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
706 * usermode code which understands the FPU hardware enough to enable
707 * the exceptions, can also handle clearing the exception state in the
708 * handler. The only consequence of not clearing the exception is the
709 * rethrow of the SIGFPE on return from the signal handler and
710 * reexecution of the corresponding instruction.
712 * For XMM traps, the exceptions were never cleared.
717 struct savefpu *pcb_save;
718 u_short control, status;
723 * Interrupt handling (for another interrupt) may have pushed the
724 * state to memory. Fetch the relevant parts of the state from
727 if (PCPU_GET(fpcurthread) != curthread) {
728 pcb_save = curpcb->pcb_save;
729 control = pcb_save->sv_env.en_cw;
730 status = pcb_save->sv_env.en_sw;
737 return (fpetable[status & ((~control & 0x3f) | 0x40)]);
746 if (PCPU_GET(fpcurthread) != curthread)
747 mxcsr = curpcb->pcb_save->sv_env.en_mxcsr;
751 return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
755 restore_fpu_curthread(struct thread *td)
760 * Record new context early in case frstor causes a trap.
762 PCPU_SET(fpcurthread, td);
768 if ((pcb->pcb_flags & PCB_FPUINITDONE) == 0) {
770 * This is the first time this thread has used the FPU or
771 * the PCB doesn't contain a clean FPU state. Explicitly
772 * load an initial state.
774 * We prefer to restore the state from the actual save
775 * area in PCB instead of directly loading from
776 * fpu_initialstate, to ignite the XSAVEOPT
779 bcopy(fpu_initialstate, pcb->pcb_save,
780 cpu_max_ext_state_size);
781 fpurestore(pcb->pcb_save);
782 if (pcb->pcb_initial_fpucw != __INITIAL_FPUCW__)
783 fldcw(pcb->pcb_initial_fpucw);
784 if (PCB_USER_FPU(pcb))
785 set_pcb_flags(pcb, PCB_FPUINITDONE |
786 PCB_USERFPUINITDONE);
788 set_pcb_flags(pcb, PCB_FPUINITDONE);
790 fpurestore(pcb->pcb_save);
794 * Device Not Available (DNA, #NM) exception handler.
796 * It would be better to switch FP context here (if curthread !=
797 * fpcurthread) and not necessarily for every context switch, but it
798 * is too hard to access foreign pcb's.
807 * This handler is entered with interrupts enabled, so context
808 * switches may occur before critical_enter() is executed. If
809 * a context switch occurs, then when we regain control, our
810 * state will have been completely restored. The CPU may
811 * change underneath us, but the only part of our context that
812 * lives in the CPU is CR0.TS and that will be "restored" by
813 * setting it on the new CPU.
817 KASSERT((curpcb->pcb_flags & PCB_FPUNOSAVE) == 0,
818 ("fpudna while in fpu_kern_enter(FPU_KERN_NOCTX)"));
819 if (__predict_false(PCPU_GET(fpcurthread) == td)) {
821 * Some virtual machines seems to set %cr0.TS at
822 * arbitrary moments. Silently clear the TS bit
823 * regardless of the eager/lazy FPU context switch
828 if (__predict_false(PCPU_GET(fpcurthread) != NULL)) {
830 "fpudna: fpcurthread = %p (%d), curthread = %p (%d)\n",
831 PCPU_GET(fpcurthread),
832 PCPU_GET(fpcurthread)->td_tid, td, td->td_tid);
834 restore_fpu_curthread(td);
839 void fpu_activate_sw(struct thread *td); /* Called from the context switch */
841 fpu_activate_sw(struct thread *td)
844 if ((td->td_pflags & TDP_KTHREAD) != 0 || !PCB_USER_FPU(td->td_pcb)) {
845 PCPU_SET(fpcurthread, NULL);
847 } else if (PCPU_GET(fpcurthread) != td) {
848 restore_fpu_curthread(td);
857 td = PCPU_GET(fpcurthread);
858 KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
860 PCPU_SET(fpcurthread, NULL);
861 clear_pcb_flags(td->td_pcb, PCB_FPUINITDONE);
866 * Get the user state of the FPU into pcb->pcb_user_save without
867 * dropping ownership (if possible). It returns the FPU ownership
871 fpugetregs(struct thread *td)
874 uint64_t *xstate_bv, bit;
876 int max_ext_n, i, owned;
880 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) == 0) {
881 bcopy(fpu_initialstate, get_pcb_user_save_pcb(pcb),
882 cpu_max_ext_state_size);
883 get_pcb_user_save_pcb(pcb)->sv_env.en_cw =
884 pcb->pcb_initial_fpucw;
887 return (_MC_FPOWNED_PCB);
889 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
890 fpusave(get_pcb_user_save_pcb(pcb));
891 owned = _MC_FPOWNED_FPU;
893 owned = _MC_FPOWNED_PCB;
897 * Handle partially saved state.
899 sa = (char *)get_pcb_user_save_pcb(pcb);
900 xstate_bv = (uint64_t *)(sa + sizeof(struct savefpu) +
901 offsetof(struct xstate_hdr, xstate_bv));
902 max_ext_n = flsl(xsave_mask);
903 for (i = 0; i < max_ext_n; i++) {
905 if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
907 bcopy((char *)fpu_initialstate +
908 xsave_area_desc[i].offset,
909 sa + xsave_area_desc[i].offset,
910 xsave_area_desc[i].size);
919 fpuuserinited(struct thread *td)
925 if (PCB_USER_FPU(pcb))
927 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
929 set_pcb_flags(pcb, PCB_FPUINITDONE);
933 fpusetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
935 struct xstate_hdr *hdr, *ehdr;
939 /* XXXKIB should we clear all extended state in xstate_bv instead ? */
940 if (xfpustate == NULL)
945 len = xfpustate_size;
946 if (len < sizeof(struct xstate_hdr))
948 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
952 ehdr = (struct xstate_hdr *)xfpustate;
953 bv = ehdr->xstate_bv;
958 if (bv & ~xsave_mask)
961 hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
964 bcopy(xfpustate + sizeof(struct xstate_hdr),
965 (char *)(hdr + 1), len - sizeof(struct xstate_hdr));
971 * Set the state of the FPU.
974 fpusetregs(struct thread *td, struct savefpu *addr, char *xfpustate,
975 size_t xfpustate_size)
980 addr->sv_env.en_mxcsr &= cpu_mxcsr_mask;
984 if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
985 error = fpusetxstate(td, xfpustate, xfpustate_size);
987 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
988 fpurestore(get_pcb_user_save_td(td));
989 set_pcb_flags(pcb, PCB_FPUINITDONE |
990 PCB_USERFPUINITDONE);
993 error = fpusetxstate(td, xfpustate, xfpustate_size);
995 bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
1004 * On AuthenticAMD processors, the fxrstor instruction does not restore
1005 * the x87's stored last instruction pointer, last data pointer, and last
1006 * opcode values, except in the rare case in which the exception summary
1007 * (ES) bit in the x87 status word is set to 1.
1009 * In order to avoid leaking this information across processes, we clean
1010 * these values by performing a dummy load before executing fxrstor().
1013 fpu_clean_state(void)
1015 static float dummy_variable = 0.0;
1019 * Clear the ES bit in the x87 status word if it is currently
1020 * set, in order to avoid causing a fault in the upcoming load.
1027 * Load the dummy variable into the x87 stack. This mangles
1028 * the x87 stack, but we don't care since we're about to call
1031 __asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
1035 * This really sucks. We want the acpi version only, but it requires
1036 * the isa_if.h file in order to get the definitions.
1038 #include "opt_isa.h"
1040 #include <isa/isavar.h>
1042 * This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
1044 static struct isa_pnp_id fpupnp_ids[] = {
1045 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
1050 fpupnp_probe(device_t dev)
1054 result = ISA_PNP_PROBE(device_get_parent(dev), dev, fpupnp_ids);
1061 fpupnp_attach(device_t dev)
1067 static device_method_t fpupnp_methods[] = {
1068 /* Device interface */
1069 DEVMETHOD(device_probe, fpupnp_probe),
1070 DEVMETHOD(device_attach, fpupnp_attach),
1071 DEVMETHOD(device_detach, bus_generic_detach),
1072 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1073 DEVMETHOD(device_suspend, bus_generic_suspend),
1074 DEVMETHOD(device_resume, bus_generic_resume),
1079 static driver_t fpupnp_driver = {
1085 static devclass_t fpupnp_devclass;
1087 DRIVER_MODULE(fpupnp, acpi, fpupnp_driver, fpupnp_devclass, 0, 0);
1088 ISA_PNP_INFO(fpupnp_ids);
1089 #endif /* DEV_ISA */
1091 static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
1092 "Kernel contexts for FPU state");
1094 #define FPU_KERN_CTX_FPUINITDONE 0x01
1095 #define FPU_KERN_CTX_DUMMY 0x02 /* avoided save for the kern thread */
1096 #define FPU_KERN_CTX_INUSE 0x04
1098 struct fpu_kern_ctx {
1099 struct savefpu *prev;
1104 struct fpu_kern_ctx *
1105 fpu_kern_alloc_ctx(u_int flags)
1107 struct fpu_kern_ctx *res;
1110 sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
1111 cpu_max_ext_state_size;
1112 res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
1113 M_NOWAIT : M_WAITOK) | M_ZERO);
1118 fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
1121 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
1122 /* XXXKIB clear the memory ? */
1123 free(ctx, M_FPUKERN_CTX);
1126 static struct savefpu *
1127 fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
1131 p = (vm_offset_t)&ctx->hwstate1;
1132 p = roundup2(p, XSAVE_AREA_ALIGN);
1133 return ((struct savefpu *)p);
1137 fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
1142 KASSERT((flags & FPU_KERN_NOCTX) != 0 || ctx != NULL,
1143 ("ctx is required when !FPU_KERN_NOCTX"));
1144 KASSERT(ctx == NULL || (ctx->flags & FPU_KERN_CTX_INUSE) == 0,
1145 ("using inuse ctx"));
1146 KASSERT((pcb->pcb_flags & PCB_FPUNOSAVE) == 0,
1147 ("recursive fpu_kern_enter while in PCB_FPUNOSAVE state"));
1149 if ((flags & FPU_KERN_NOCTX) != 0) {
1152 if (curthread == PCPU_GET(fpcurthread)) {
1153 fpusave(curpcb->pcb_save);
1154 PCPU_SET(fpcurthread, NULL);
1156 KASSERT(PCPU_GET(fpcurthread) == NULL,
1157 ("invalid fpcurthread"));
1161 * This breaks XSAVEOPT tracker, but
1162 * PCB_FPUNOSAVE state is supposed to never need to
1163 * save FPU context at all.
1165 fpurestore(fpu_initialstate);
1166 set_pcb_flags(pcb, PCB_KERNFPU | PCB_FPUNOSAVE |
1170 if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
1171 ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
1175 KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
1176 get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
1177 ctx->flags = FPU_KERN_CTX_INUSE;
1178 if ((pcb->pcb_flags & PCB_FPUINITDONE) != 0)
1179 ctx->flags |= FPU_KERN_CTX_FPUINITDONE;
1181 ctx->prev = pcb->pcb_save;
1182 pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
1183 set_pcb_flags(pcb, PCB_KERNFPU);
1184 clear_pcb_flags(pcb, PCB_FPUINITDONE);
1189 fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
1195 if ((pcb->pcb_flags & PCB_FPUNOSAVE) != 0) {
1196 KASSERT(ctx == NULL, ("non-null ctx after FPU_KERN_NOCTX"));
1197 KASSERT(PCPU_GET(fpcurthread) == NULL,
1198 ("non-NULL fpcurthread for PCB_FPUNOSAVE"));
1199 CRITICAL_ASSERT(td);
1201 clear_pcb_flags(pcb, PCB_FPUNOSAVE | PCB_FPUINITDONE);
1204 KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
1205 ("leaving not inuse ctx"));
1206 ctx->flags &= ~FPU_KERN_CTX_INUSE;
1208 if (is_fpu_kern_thread(0) &&
1209 (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
1211 KASSERT((ctx->flags & FPU_KERN_CTX_DUMMY) == 0,
1214 if (curthread == PCPU_GET(fpcurthread))
1216 pcb->pcb_save = ctx->prev;
1219 if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
1220 if ((pcb->pcb_flags & PCB_USERFPUINITDONE) != 0) {
1221 set_pcb_flags(pcb, PCB_FPUINITDONE);
1222 if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0)
1223 clear_pcb_flags(pcb, PCB_KERNFPU);
1224 } else if ((pcb->pcb_flags & PCB_KERNFPU_THR) == 0)
1225 clear_pcb_flags(pcb, PCB_FPUINITDONE | PCB_KERNFPU);
1227 if ((ctx->flags & FPU_KERN_CTX_FPUINITDONE) != 0)
1228 set_pcb_flags(pcb, PCB_FPUINITDONE);
1230 clear_pcb_flags(pcb, PCB_FPUINITDONE);
1231 KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
1238 fpu_kern_thread(u_int flags)
1241 KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
1242 ("Only kthread may use fpu_kern_thread"));
1243 KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
1244 ("mangled pcb_save"));
1245 KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
1247 set_pcb_flags(curpcb, PCB_KERNFPU | PCB_KERNFPU_THR);
1252 is_fpu_kern_thread(u_int flags)
1255 if ((curthread->td_pflags & TDP_KTHREAD) == 0)
1257 return ((curpcb->pcb_flags & PCB_KERNFPU_THR) != 0);
1261 * FPU save area alloc/free/init utility routines
1264 fpu_save_area_alloc(void)
1267 return (uma_zalloc(fpu_save_area_zone, 0));
1271 fpu_save_area_free(struct savefpu *fsa)
1274 uma_zfree(fpu_save_area_zone, fsa);
1278 fpu_save_area_reset(struct savefpu *fsa)
1281 bcopy(fpu_initialstate, fsa, cpu_max_ext_state_size);