2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
128 #include <sys/turnstile.h>
129 #include <sys/vmem.h>
130 #include <sys/vmmeter.h>
131 #include <sys/sched.h>
132 #include <sys/sysctl.h>
140 #include <vm/vm_param.h>
141 #include <vm/vm_kern.h>
142 #include <vm/vm_page.h>
143 #include <vm/vm_map.h>
144 #include <vm/vm_object.h>
145 #include <vm/vm_extern.h>
146 #include <vm/vm_pageout.h>
147 #include <vm/vm_pager.h>
148 #include <vm/vm_phys.h>
149 #include <vm/vm_radix.h>
150 #include <vm/vm_reserv.h>
153 #include <machine/intr_machdep.h>
154 #include <x86/apicvar.h>
155 #include <x86/ifunc.h>
156 #include <machine/cpu.h>
157 #include <machine/cputypes.h>
158 #include <machine/md_var.h>
159 #include <machine/pcb.h>
160 #include <machine/specialreg.h>
162 #include <machine/smp.h>
164 #include <machine/sysarch.h>
165 #include <machine/tss.h>
167 static __inline boolean_t
168 pmap_type_guest(pmap_t pmap)
171 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
174 static __inline boolean_t
175 pmap_emulate_ad_bits(pmap_t pmap)
178 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
181 static __inline pt_entry_t
182 pmap_valid_bit(pmap_t pmap)
186 switch (pmap->pm_type) {
192 if (pmap_emulate_ad_bits(pmap))
193 mask = EPT_PG_EMUL_V;
198 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
204 static __inline pt_entry_t
205 pmap_rw_bit(pmap_t pmap)
209 switch (pmap->pm_type) {
215 if (pmap_emulate_ad_bits(pmap))
216 mask = EPT_PG_EMUL_RW;
221 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
227 static pt_entry_t pg_g;
229 static __inline pt_entry_t
230 pmap_global_bit(pmap_t pmap)
234 switch (pmap->pm_type) {
243 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
249 static __inline pt_entry_t
250 pmap_accessed_bit(pmap_t pmap)
254 switch (pmap->pm_type) {
260 if (pmap_emulate_ad_bits(pmap))
266 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
272 static __inline pt_entry_t
273 pmap_modified_bit(pmap_t pmap)
277 switch (pmap->pm_type) {
283 if (pmap_emulate_ad_bits(pmap))
289 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
295 static __inline pt_entry_t
296 pmap_pku_mask_bit(pmap_t pmap)
299 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
302 #if !defined(DIAGNOSTIC)
303 #ifdef __GNUC_GNU_INLINE__
304 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
306 #define PMAP_INLINE extern inline
313 #define PV_STAT(x) do { x ; } while (0)
315 #define PV_STAT(x) do { } while (0)
318 #define pa_index(pa) ((pa) >> PDRSHIFT)
319 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
321 #define NPV_LIST_LOCKS MAXCPU
323 #define PHYS_TO_PV_LIST_LOCK(pa) \
324 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
326 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
327 struct rwlock **_lockp = (lockp); \
328 struct rwlock *_new_lock; \
330 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
331 if (_new_lock != *_lockp) { \
332 if (*_lockp != NULL) \
333 rw_wunlock(*_lockp); \
334 *_lockp = _new_lock; \
339 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
340 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
342 #define RELEASE_PV_LIST_LOCK(lockp) do { \
343 struct rwlock **_lockp = (lockp); \
345 if (*_lockp != NULL) { \
346 rw_wunlock(*_lockp); \
351 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
352 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
354 struct pmap kernel_pmap_store;
356 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
357 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
360 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
361 "Number of kernel page table pages allocated on bootup");
364 vm_paddr_t dmaplimit;
365 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
368 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
370 /* Unused, kept for ABI stability on the stable branch. */
371 static int pat_works = 1;
372 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
373 "Is page attribute table fully functional?");
375 static int pg_ps_enabled = 1;
376 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
377 &pg_ps_enabled, 0, "Are large page mappings enabled?");
379 #define PAT_INDEX_SIZE 8
380 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
382 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
383 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
384 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
385 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
387 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
388 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
389 static int ndmpdpphys; /* number of DMPDPphys pages */
391 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
394 * pmap_mapdev support pre initialization (i.e. console)
396 #define PMAP_PREINIT_MAPPING_COUNT 8
397 static struct pmap_preinit_mapping {
402 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
403 static int pmap_initialized;
406 * Data for the pv entry allocation mechanism.
407 * Updates to pv_invl_gen are protected by the pv_list_locks[]
408 * elements, but reads are not.
410 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
411 static struct mtx __exclusive_cache_line pv_chunks_mutex;
412 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
413 static u_long pv_invl_gen[NPV_LIST_LOCKS];
414 static struct md_page *pv_table;
415 static struct md_page pv_dummy;
418 * All those kernel PT submaps that BSD is so fond of
420 pt_entry_t *CMAP1 = NULL;
422 static vm_offset_t qframe = 0;
423 static struct mtx qframe_mtx;
425 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
427 static vmem_t *large_vmem;
428 static u_int lm_ents;
429 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
430 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
432 int pmap_pcid_enabled = 1;
433 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
434 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
435 int invpcid_works = 0;
436 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
437 "Is the invpcid instruction available ?");
439 int __read_frequently pti = 0;
440 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
442 "Page Table Isolation enabled");
443 static vm_object_t pti_obj;
444 static pml4_entry_t *pti_pml4;
445 static vm_pindex_t pti_pg_idx;
446 static bool pti_finalized;
448 struct pmap_pkru_range {
449 struct rs_el pkru_rs_el;
454 static uma_zone_t pmap_pkru_ranges_zone;
455 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
456 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
457 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
458 static void *pkru_dup_range(void *ctx, void *data);
459 static void pkru_free_range(void *ctx, void *node);
460 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
461 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
462 static void pmap_pkru_deassign_all(pmap_t pmap);
465 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
472 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
474 return (sysctl_handle_64(oidp, &res, 0, req));
476 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
477 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
478 "Count of saved TLB context on switch");
480 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
481 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
482 static struct mtx invl_gen_mtx;
483 /* Fake lock object to satisfy turnstiles interface. */
484 static struct lock_object invl_gen_ts = {
487 static struct pmap_invl_gen pmap_invl_gen_head = {
491 static u_long pmap_invl_gen = 1;
492 static int pmap_invl_waiters;
493 static struct callout pmap_invl_callout;
494 static bool pmap_invl_callout_inited;
496 #define PMAP_ASSERT_NOT_IN_DI() \
497 KASSERT(pmap_not_in_di(), ("DI already started"))
504 if ((cpu_feature2 & CPUID2_CX16) == 0)
507 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
512 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
516 locked = pmap_di_locked();
517 return (sysctl_handle_int(oidp, &locked, 0, req));
519 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
520 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
521 "Locked delayed invalidation");
523 static bool pmap_not_in_di_l(void);
524 static bool pmap_not_in_di_u(void);
525 DEFINE_IFUNC(, bool, pmap_not_in_di, (void), static)
528 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
532 pmap_not_in_di_l(void)
534 struct pmap_invl_gen *invl_gen;
536 invl_gen = &curthread->td_md.md_invl_gen;
537 return (invl_gen->gen == 0);
541 pmap_thread_init_invl_gen_l(struct thread *td)
543 struct pmap_invl_gen *invl_gen;
545 invl_gen = &td->td_md.md_invl_gen;
550 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
552 struct turnstile *ts;
554 ts = turnstile_trywait(&invl_gen_ts);
555 if (*m_gen > atomic_load_long(invl_gen))
556 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
558 turnstile_cancel(ts);
562 pmap_delayed_invl_finish_unblock(u_long new_gen)
564 struct turnstile *ts;
566 turnstile_chain_lock(&invl_gen_ts);
567 ts = turnstile_lookup(&invl_gen_ts);
569 pmap_invl_gen = new_gen;
571 turnstile_broadcast(ts, TS_SHARED_QUEUE);
572 turnstile_unpend(ts);
574 turnstile_chain_unlock(&invl_gen_ts);
578 * Start a new Delayed Invalidation (DI) block of code, executed by
579 * the current thread. Within a DI block, the current thread may
580 * destroy both the page table and PV list entries for a mapping and
581 * then release the corresponding PV list lock before ensuring that
582 * the mapping is flushed from the TLBs of any processors with the
586 pmap_delayed_invl_start_l(void)
588 struct pmap_invl_gen *invl_gen;
591 invl_gen = &curthread->td_md.md_invl_gen;
592 PMAP_ASSERT_NOT_IN_DI();
593 mtx_lock(&invl_gen_mtx);
594 if (LIST_EMPTY(&pmap_invl_gen_tracker))
595 currgen = pmap_invl_gen;
597 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
598 invl_gen->gen = currgen + 1;
599 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
600 mtx_unlock(&invl_gen_mtx);
604 * Finish the DI block, previously started by the current thread. All
605 * required TLB flushes for the pages marked by
606 * pmap_delayed_invl_page() must be finished before this function is
609 * This function works by bumping the global DI generation number to
610 * the generation number of the current thread's DI, unless there is a
611 * pending DI that started earlier. In the latter case, bumping the
612 * global DI generation number would incorrectly signal that the
613 * earlier DI had finished. Instead, this function bumps the earlier
614 * DI's generation number to match the generation number of the
615 * current thread's DI.
618 pmap_delayed_invl_finish_l(void)
620 struct pmap_invl_gen *invl_gen, *next;
622 invl_gen = &curthread->td_md.md_invl_gen;
623 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
624 mtx_lock(&invl_gen_mtx);
625 next = LIST_NEXT(invl_gen, link);
627 pmap_delayed_invl_finish_unblock(invl_gen->gen);
629 next->gen = invl_gen->gen;
630 LIST_REMOVE(invl_gen, link);
631 mtx_unlock(&invl_gen_mtx);
636 pmap_not_in_di_u(void)
638 struct pmap_invl_gen *invl_gen;
640 invl_gen = &curthread->td_md.md_invl_gen;
641 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
645 pmap_thread_init_invl_gen_u(struct thread *td)
647 struct pmap_invl_gen *invl_gen;
649 invl_gen = &td->td_md.md_invl_gen;
651 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
655 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
657 uint64_t new_high, new_low, old_high, old_low;
660 old_low = new_low = 0;
661 old_high = new_high = (uintptr_t)0;
663 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
664 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
665 : "b"(new_low), "c" (new_high)
668 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
671 out->next = (void *)old_high;
674 out->next = (void *)new_high;
680 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
681 struct pmap_invl_gen *new_val)
683 uint64_t new_high, new_low, old_high, old_low;
686 new_low = new_val->gen;
687 new_high = (uintptr_t)new_val->next;
688 old_low = old_val->gen;
689 old_high = (uintptr_t)old_val->next;
691 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
692 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
693 : "b"(new_low), "c" (new_high)
699 static long invl_start_restart;
700 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
701 &invl_start_restart, 0,
703 static long invl_finish_restart;
704 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
705 &invl_finish_restart, 0,
707 static int invl_max_qlen;
708 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
713 static struct lock_delay_config __read_frequently di_delay;
714 LOCK_DELAY_SYSINIT_DEFAULT(di_delay);
717 pmap_delayed_invl_start_u(void)
719 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
721 struct lock_delay_arg lda;
729 invl_gen = &td->td_md.md_invl_gen;
730 PMAP_ASSERT_NOT_IN_DI();
731 lock_delay_arg_init(&lda, &di_delay);
732 invl_gen->saved_pri = 0;
733 pri = td->td_base_pri;
736 pri = td->td_base_pri;
738 invl_gen->saved_pri = pri;
745 for (p = &pmap_invl_gen_head;; p = prev.next) {
747 prevl = atomic_load_ptr(&p->next);
748 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
749 PV_STAT(atomic_add_long(&invl_start_restart, 1));
755 prev.next = (void *)prevl;
758 if ((ii = invl_max_qlen) < i)
759 atomic_cmpset_int(&invl_max_qlen, ii, i);
762 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
763 PV_STAT(atomic_add_long(&invl_start_restart, 1));
768 new_prev.gen = prev.gen;
769 new_prev.next = invl_gen;
770 invl_gen->gen = prev.gen + 1;
772 /* Formal fence between store to invl->gen and updating *p. */
773 atomic_thread_fence_rel();
776 * After inserting an invl_gen element with invalid bit set,
777 * this thread blocks any other thread trying to enter the
778 * delayed invalidation block. Do not allow to remove us from
779 * the CPU, because it causes starvation for other threads.
784 * ABA for *p is not possible there, since p->gen can only
785 * increase. So if the *p thread finished its di, then
786 * started a new one and got inserted into the list at the
787 * same place, its gen will appear greater than the previously
790 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
792 PV_STAT(atomic_add_long(&invl_start_restart, 1));
798 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
799 * invl_gen->next, allowing other threads to iterate past us.
800 * pmap_di_store_invl() provides fence between the generation
801 * write and the update of next.
803 invl_gen->next = NULL;
808 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
809 struct pmap_invl_gen *p)
811 struct pmap_invl_gen prev, new_prev;
815 * Load invl_gen->gen after setting invl_gen->next
816 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
817 * generations to propagate to our invl_gen->gen. Lock prefix
818 * in atomic_set_ptr() worked as seq_cst fence.
820 mygen = atomic_load_long(&invl_gen->gen);
822 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
825 KASSERT(prev.gen < mygen,
826 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
827 new_prev.gen = mygen;
828 new_prev.next = (void *)((uintptr_t)invl_gen->next &
829 ~PMAP_INVL_GEN_NEXT_INVALID);
831 /* Formal fence between load of prev and storing update to it. */
832 atomic_thread_fence_rel();
834 return (pmap_di_store_invl(p, &prev, &new_prev));
838 pmap_delayed_invl_finish_u(void)
840 struct pmap_invl_gen *invl_gen, *p;
842 struct lock_delay_arg lda;
846 invl_gen = &td->td_md.md_invl_gen;
847 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
848 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
849 ("missed invl_start: INVALID"));
850 lock_delay_arg_init(&lda, &di_delay);
853 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
854 prevl = atomic_load_ptr(&p->next);
855 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
856 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
860 if ((void *)prevl == invl_gen)
865 * It is legitimate to not find ourself on the list if a
866 * thread before us finished its DI and started it again.
868 if (__predict_false(p == NULL)) {
869 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
875 atomic_set_ptr((uintptr_t *)&invl_gen->next,
876 PMAP_INVL_GEN_NEXT_INVALID);
877 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
878 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
879 PMAP_INVL_GEN_NEXT_INVALID);
881 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
886 if (atomic_load_int(&pmap_invl_waiters) > 0)
887 pmap_delayed_invl_finish_unblock(0);
888 if (invl_gen->saved_pri != 0) {
890 sched_prio(td, invl_gen->saved_pri);
896 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
898 struct pmap_invl_gen *p, *pn;
903 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
905 nextl = atomic_load_ptr(&p->next);
906 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
907 td = first ? NULL : __containerof(p, struct thread,
909 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
910 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
911 td != NULL ? td->td_tid : -1);
917 static long invl_wait;
918 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
919 "Number of times DI invalidation blocked pmap_remove_all/write");
920 static long invl_wait_slow;
921 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
922 "Number of slow invalidation waits for lockless DI");
926 pmap_delayed_invl_genp(vm_page_t m)
929 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
933 pmap_delayed_invl_callout_func(void *arg __unused)
936 if (atomic_load_int(&pmap_invl_waiters) == 0)
938 pmap_delayed_invl_finish_unblock(0);
942 pmap_delayed_invl_callout_init(void *arg __unused)
945 if (pmap_di_locked())
947 callout_init(&pmap_invl_callout, 1);
948 pmap_invl_callout_inited = true;
950 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
951 pmap_delayed_invl_callout_init, NULL);
954 * Ensure that all currently executing DI blocks, that need to flush
955 * TLB for the given page m, actually flushed the TLB at the time the
956 * function returned. If the page m has an empty PV list and we call
957 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
958 * valid mapping for the page m in either its page table or TLB.
960 * This function works by blocking until the global DI generation
961 * number catches up with the generation number associated with the
962 * given page m and its PV list. Since this function's callers
963 * typically own an object lock and sometimes own a page lock, it
964 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
968 pmap_delayed_invl_wait_l(vm_page_t m)
972 bool accounted = false;
975 m_gen = pmap_delayed_invl_genp(m);
976 while (*m_gen > pmap_invl_gen) {
979 atomic_add_long(&invl_wait, 1);
983 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
988 pmap_delayed_invl_wait_u(vm_page_t m)
991 struct lock_delay_arg lda;
995 m_gen = pmap_delayed_invl_genp(m);
996 lock_delay_arg_init(&lda, &di_delay);
997 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
998 if (fast || !pmap_invl_callout_inited) {
999 PV_STAT(atomic_add_long(&invl_wait, 1));
1004 * The page's invalidation generation number
1005 * is still below the current thread's number.
1006 * Prepare to block so that we do not waste
1007 * CPU cycles or worse, suffer livelock.
1009 * Since it is impossible to block without
1010 * racing with pmap_delayed_invl_finish_u(),
1011 * prepare for the race by incrementing
1012 * pmap_invl_waiters and arming a 1-tick
1013 * callout which will unblock us if we lose
1016 atomic_add_int(&pmap_invl_waiters, 1);
1019 * Re-check the current thread's invalidation
1020 * generation after incrementing
1021 * pmap_invl_waiters, so that there is no race
1022 * with pmap_delayed_invl_finish_u() setting
1023 * the page generation and checking
1024 * pmap_invl_waiters. The only race allowed
1025 * is for a missed unblock, which is handled
1029 atomic_load_long(&pmap_invl_gen_head.gen)) {
1030 callout_reset(&pmap_invl_callout, 1,
1031 pmap_delayed_invl_callout_func, NULL);
1032 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1033 pmap_delayed_invl_wait_block(m_gen,
1034 &pmap_invl_gen_head.gen);
1036 atomic_add_int(&pmap_invl_waiters, -1);
1041 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *), static)
1044 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1045 pmap_thread_init_invl_gen_u);
1048 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void), static)
1051 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1052 pmap_delayed_invl_start_u);
1055 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void), static)
1058 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1059 pmap_delayed_invl_finish_u);
1062 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t), static)
1065 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1066 pmap_delayed_invl_wait_u);
1070 * Mark the page m's PV list as participating in the current thread's
1071 * DI block. Any threads concurrently using m's PV list to remove or
1072 * restrict all mappings to m will wait for the current thread's DI
1073 * block to complete before proceeding.
1075 * The function works by setting the DI generation number for m's PV
1076 * list to at least the DI generation number of the current thread.
1077 * This forces a caller of pmap_delayed_invl_wait() to block until
1078 * current thread calls pmap_delayed_invl_finish().
1081 pmap_delayed_invl_page(vm_page_t m)
1085 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1086 gen = curthread->td_md.md_invl_gen.gen;
1089 m_gen = pmap_delayed_invl_genp(m);
1097 static caddr_t crashdumpmap;
1100 * Internal flags for pmap_enter()'s helper functions.
1102 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1103 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1106 * Internal flags for pmap_mapdev_internal() and
1107 * pmap_change_attr_locked().
1109 #define MAPDEV_FLUSHCACHE 0x0000001 /* Flush cache after mapping. */
1110 #define MAPDEV_SETATTR 0x0000002 /* Modify existing attrs. */
1112 static void free_pv_chunk(struct pv_chunk *pc);
1113 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1114 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1115 static int popcnt_pc_map_pq(uint64_t *map);
1116 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1117 static void reserve_pv_entries(pmap_t pmap, int needed,
1118 struct rwlock **lockp);
1119 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1120 struct rwlock **lockp);
1121 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1122 u_int flags, struct rwlock **lockp);
1123 #if VM_NRESERVLEVEL > 0
1124 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1125 struct rwlock **lockp);
1127 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1128 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1131 static int pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode,
1133 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1134 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1135 vm_offset_t va, struct rwlock **lockp);
1136 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1138 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1139 vm_prot_t prot, struct rwlock **lockp);
1140 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1141 u_int flags, vm_page_t m, struct rwlock **lockp);
1142 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1143 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1144 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1145 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1146 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1148 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1150 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1152 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1153 static vm_page_t pmap_large_map_getptp_unlocked(void);
1154 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1155 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask);
1156 #if VM_NRESERVLEVEL > 0
1157 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1158 struct rwlock **lockp);
1160 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1162 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask);
1163 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1165 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1166 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1167 static void pmap_pti_wire_pte(void *pte);
1168 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1169 struct spglist *free, struct rwlock **lockp);
1170 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1171 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1172 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1173 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1174 struct spglist *free);
1175 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1176 pd_entry_t *pde, struct spglist *free,
1177 struct rwlock **lockp);
1178 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1179 vm_page_t m, struct rwlock **lockp);
1180 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1182 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1184 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1185 struct rwlock **lockp);
1186 static vm_page_t pmap_allocpde(pmap_t pmap, vm_offset_t va,
1187 struct rwlock **lockp);
1188 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1189 struct rwlock **lockp);
1191 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1192 struct spglist *free);
1193 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1195 /********************/
1196 /* Inline functions */
1197 /********************/
1199 /* Return a non-clipped PD index for a given VA */
1200 static __inline vm_pindex_t
1201 pmap_pde_pindex(vm_offset_t va)
1203 return (va >> PDRSHIFT);
1207 /* Return a pointer to the PML4 slot that corresponds to a VA */
1208 static __inline pml4_entry_t *
1209 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1212 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1215 /* Return a pointer to the PDP slot that corresponds to a VA */
1216 static __inline pdp_entry_t *
1217 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1221 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1222 return (&pdpe[pmap_pdpe_index(va)]);
1225 /* Return a pointer to the PDP slot that corresponds to a VA */
1226 static __inline pdp_entry_t *
1227 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1229 pml4_entry_t *pml4e;
1232 PG_V = pmap_valid_bit(pmap);
1233 pml4e = pmap_pml4e(pmap, va);
1234 if ((*pml4e & PG_V) == 0)
1236 return (pmap_pml4e_to_pdpe(pml4e, va));
1239 /* Return a pointer to the PD slot that corresponds to a VA */
1240 static __inline pd_entry_t *
1241 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1245 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1246 return (&pde[pmap_pde_index(va)]);
1249 /* Return a pointer to the PD slot that corresponds to a VA */
1250 static __inline pd_entry_t *
1251 pmap_pde(pmap_t pmap, vm_offset_t va)
1256 PG_V = pmap_valid_bit(pmap);
1257 pdpe = pmap_pdpe(pmap, va);
1258 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1260 return (pmap_pdpe_to_pde(pdpe, va));
1263 /* Return a pointer to the PT slot that corresponds to a VA */
1264 static __inline pt_entry_t *
1265 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1269 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1270 return (&pte[pmap_pte_index(va)]);
1273 /* Return a pointer to the PT slot that corresponds to a VA */
1274 static __inline pt_entry_t *
1275 pmap_pte(pmap_t pmap, vm_offset_t va)
1280 PG_V = pmap_valid_bit(pmap);
1281 pde = pmap_pde(pmap, va);
1282 if (pde == NULL || (*pde & PG_V) == 0)
1284 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1285 return ((pt_entry_t *)pde);
1286 return (pmap_pde_to_pte(pde, va));
1289 static __inline void
1290 pmap_resident_count_inc(pmap_t pmap, int count)
1293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1294 pmap->pm_stats.resident_count += count;
1297 static __inline void
1298 pmap_resident_count_dec(pmap_t pmap, int count)
1301 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1302 KASSERT(pmap->pm_stats.resident_count >= count,
1303 ("pmap %p resident count underflow %ld %d", pmap,
1304 pmap->pm_stats.resident_count, count));
1305 pmap->pm_stats.resident_count -= count;
1308 PMAP_INLINE pt_entry_t *
1309 vtopte(vm_offset_t va)
1311 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1313 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1315 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1318 static __inline pd_entry_t *
1319 vtopde(vm_offset_t va)
1321 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1323 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1325 return (PDmap + ((va >> PDRSHIFT) & mask));
1329 allocpages(vm_paddr_t *firstaddr, int n)
1334 bzero((void *)ret, n * PAGE_SIZE);
1335 *firstaddr += n * PAGE_SIZE;
1339 CTASSERT(powerof2(NDMPML4E));
1341 /* number of kernel PDP slots */
1342 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1345 nkpt_init(vm_paddr_t addr)
1352 pt_pages = howmany(addr, 1 << PDRSHIFT);
1353 pt_pages += NKPDPE(pt_pages);
1356 * Add some slop beyond the bare minimum required for bootstrapping
1359 * This is quite important when allocating KVA for kernel modules.
1360 * The modules are required to be linked in the negative 2GB of
1361 * the address space. If we run out of KVA in this region then
1362 * pmap_growkernel() will need to allocate page table pages to map
1363 * the entire 512GB of KVA space which is an unnecessary tax on
1366 * Secondly, device memory mapped as part of setting up the low-
1367 * level console(s) is taken from KVA, starting at virtual_avail.
1368 * This is because cninit() is called after pmap_bootstrap() but
1369 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1372 pt_pages += 32; /* 64MB additional slop. */
1378 * Returns the proper write/execute permission for a physical page that is
1379 * part of the initial boot allocations.
1381 * If the page has kernel text, it is marked as read-only. If the page has
1382 * kernel read-only data, it is marked as read-only/not-executable. If the
1383 * page has only read-write data, it is marked as read-write/not-executable.
1384 * If the page is below/above the kernel range, it is marked as read-write.
1386 * This function operates on 2M pages, since we map the kernel space that
1389 * Note that this doesn't currently provide any protection for modules.
1391 static inline pt_entry_t
1392 bootaddr_rwx(vm_paddr_t pa)
1396 * Everything in the same 2M page as the start of the kernel
1397 * should be static. On the other hand, things in the same 2M
1398 * page as the end of the kernel could be read-write/executable,
1399 * as the kernel image is not guaranteed to end on a 2M boundary.
1401 if (pa < trunc_2mpage(btext - KERNBASE) ||
1402 pa >= trunc_2mpage(_end - KERNBASE))
1405 * The linker should ensure that the read-only and read-write
1406 * portions don't share the same 2M page, so this shouldn't
1407 * impact read-only data. However, in any case, any page with
1408 * read-write data needs to be read-write.
1410 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1411 return (X86_PG_RW | pg_nx);
1413 * Mark any 2M page containing kernel text as read-only. Mark
1414 * other pages with read-only data as read-only and not executable.
1415 * (It is likely a small portion of the read-only data section will
1416 * be marked as read-only, but executable. This should be acceptable
1417 * since the read-only protection will keep the data from changing.)
1418 * Note that fixups to the .text section will still work until we
1421 if (pa < round_2mpage(etext - KERNBASE))
1427 create_pagetables(vm_paddr_t *firstaddr)
1429 int i, j, ndm1g, nkpdpe, nkdmpde;
1433 uint64_t DMPDkernphys;
1435 /* Allocate page table pages for the direct map */
1436 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1437 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1439 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1440 if (ndmpdpphys > NDMPML4E) {
1442 * Each NDMPML4E allows 512 GB, so limit to that,
1443 * and then readjust ndmpdp and ndmpdpphys.
1445 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1446 Maxmem = atop(NDMPML4E * NBPML4);
1447 ndmpdpphys = NDMPML4E;
1448 ndmpdp = NDMPML4E * NPDEPG;
1450 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1452 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1454 * Calculate the number of 1G pages that will fully fit in
1457 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1460 * Allocate 2M pages for the kernel. These will be used in
1461 * place of the first one or more 1G pages from ndm1g.
1463 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1464 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1467 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1468 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1470 /* Allocate pages */
1471 KPML4phys = allocpages(firstaddr, 1);
1472 KPDPphys = allocpages(firstaddr, NKPML4E);
1475 * Allocate the initial number of kernel page table pages required to
1476 * bootstrap. We defer this until after all memory-size dependent
1477 * allocations are done (e.g. direct map), so that we don't have to
1478 * build in too much slop in our estimate.
1480 * Note that when NKPML4E > 1, we have an empty page underneath
1481 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1482 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1484 nkpt_init(*firstaddr);
1485 nkpdpe = NKPDPE(nkpt);
1487 KPTphys = allocpages(firstaddr, nkpt);
1488 KPDphys = allocpages(firstaddr, nkpdpe);
1491 * Connect the zero-filled PT pages to their PD entries. This
1492 * implicitly maps the PT pages at their correct locations within
1495 pd_p = (pd_entry_t *)KPDphys;
1496 for (i = 0; i < nkpt; i++)
1497 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1500 * Map from physical address zero to the end of loader preallocated
1501 * memory using 2MB pages. This replaces some of the PD entries
1504 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1505 /* Preset PG_M and PG_A because demotion expects it. */
1506 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1507 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1510 * Because we map the physical blocks in 2M pages, adjust firstaddr
1511 * to record the physical blocks we've actually mapped into kernel
1512 * virtual address space.
1514 if (*firstaddr < round_2mpage(KERNend))
1515 *firstaddr = round_2mpage(KERNend);
1517 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1518 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1519 for (i = 0; i < nkpdpe; i++)
1520 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1523 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1524 * the end of physical memory is not aligned to a 1GB page boundary,
1525 * then the residual physical memory is mapped with 2MB pages. Later,
1526 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1527 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1528 * that are partially used.
1530 pd_p = (pd_entry_t *)DMPDphys;
1531 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1532 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1533 /* Preset PG_M and PG_A because demotion expects it. */
1534 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1535 X86_PG_M | X86_PG_A | pg_nx;
1537 pdp_p = (pdp_entry_t *)DMPDPphys;
1538 for (i = 0; i < ndm1g; i++) {
1539 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1540 /* Preset PG_M and PG_A because demotion expects it. */
1541 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1542 X86_PG_M | X86_PG_A | pg_nx;
1544 for (j = 0; i < ndmpdp; i++, j++) {
1545 pdp_p[i] = DMPDphys + ptoa(j);
1546 pdp_p[i] |= X86_PG_RW | X86_PG_V;
1550 * Instead of using a 1G page for the memory containing the kernel,
1551 * use 2M pages with appropriate permissions. (If using 1G pages,
1552 * this will partially overwrite the PDPEs above.)
1555 pd_p = (pd_entry_t *)DMPDkernphys;
1556 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1557 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1558 X86_PG_M | X86_PG_A | pg_nx |
1559 bootaddr_rwx(i << PDRSHIFT);
1560 for (i = 0; i < nkdmpde; i++)
1561 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1565 /* And recursively map PML4 to itself in order to get PTmap */
1566 p4_p = (pml4_entry_t *)KPML4phys;
1567 p4_p[PML4PML4I] = KPML4phys;
1568 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1570 /* Connect the Direct Map slot(s) up to the PML4. */
1571 for (i = 0; i < ndmpdpphys; i++) {
1572 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1573 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V;
1576 /* Connect the KVA slots up to the PML4 */
1577 for (i = 0; i < NKPML4E; i++) {
1578 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1579 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1584 * Bootstrap the system enough to run with virtual memory.
1586 * On amd64 this is called after mapping has already been enabled
1587 * and just syncs the pmap module with what has already been done.
1588 * [We can't call it easily with mapping off since the kernel is not
1589 * mapped with PA == VA, hence we would have to relocate every address
1590 * from the linked base (virtual) address "KERNBASE" to the actual
1591 * (physical) address starting relative to 0]
1594 pmap_bootstrap(vm_paddr_t *firstaddr)
1602 KERNend = *firstaddr;
1603 res = atop(KERNend - (vm_paddr_t)kernphys);
1609 * Create an initial set of page tables to run the kernel in.
1611 create_pagetables(firstaddr);
1614 * Add a physical memory segment (vm_phys_seg) corresponding to the
1615 * preallocated kernel page table pages so that vm_page structures
1616 * representing these pages will be created. The vm_page structures
1617 * are required for promotion of the corresponding kernel virtual
1618 * addresses to superpage mappings.
1620 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1623 * Account for the virtual addresses mapped by create_pagetables().
1625 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1626 virtual_end = VM_MAX_KERNEL_ADDRESS;
1629 * Enable PG_G global pages, then switch to the kernel page
1630 * table from the bootstrap page table. After the switch, it
1631 * is possible to enable SMEP and SMAP since PG_U bits are
1637 load_cr3(KPML4phys);
1638 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1640 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1645 * Initialize the kernel pmap (which is statically allocated).
1646 * Count bootstrap data as being resident in case any of this data is
1647 * later unmapped (using pmap_remove()) and freed.
1649 PMAP_LOCK_INIT(kernel_pmap);
1650 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1651 kernel_pmap->pm_cr3 = KPML4phys;
1652 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1653 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1654 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1655 kernel_pmap->pm_stats.resident_count = res;
1656 kernel_pmap->pm_flags = pmap_flags;
1659 * Initialize the TLB invalidations generation number lock.
1661 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1664 * Reserve some special page table entries/VA space for temporary
1667 #define SYSMAP(c, p, v, n) \
1668 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1674 * Crashdump maps. The first page is reused as CMAP1 for the
1677 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1678 CADDR1 = crashdumpmap;
1683 * Initialize the PAT MSR.
1684 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1685 * side-effect, invalidates stale PG_G TLB entries that might
1686 * have been created in our pre-boot environment.
1690 /* Initialize TLB Context Id. */
1691 if (pmap_pcid_enabled) {
1692 for (i = 0; i < MAXCPU; i++) {
1693 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1694 kernel_pmap->pm_pcids[i].pm_gen = 1;
1698 * PMAP_PCID_KERN + 1 is used for initialization of
1699 * proc0 pmap. The pmap' pcid state might be used by
1700 * EFIRT entry before first context switch, so it
1701 * needs to be valid.
1703 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1704 PCPU_SET(pcid_gen, 1);
1707 * pcpu area for APs is zeroed during AP startup.
1708 * pc_pcid_next and pc_pcid_gen are initialized by AP
1709 * during pcpu setup.
1711 load_cr4(rcr4() | CR4_PCIDE);
1716 * Setup the PAT MSR.
1725 /* Bail if this CPU doesn't implement PAT. */
1726 if ((cpu_feature & CPUID_PAT) == 0)
1729 /* Set default PAT index table. */
1730 for (i = 0; i < PAT_INDEX_SIZE; i++)
1732 pat_index[PAT_WRITE_BACK] = 0;
1733 pat_index[PAT_WRITE_THROUGH] = 1;
1734 pat_index[PAT_UNCACHEABLE] = 3;
1735 pat_index[PAT_WRITE_COMBINING] = 6;
1736 pat_index[PAT_WRITE_PROTECTED] = 5;
1737 pat_index[PAT_UNCACHED] = 2;
1740 * Initialize default PAT entries.
1741 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1742 * Program 5 and 6 as WP and WC.
1744 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1745 * mapping for a 2M page uses a PAT value with the bit 3 set due
1746 * to its overload with PG_PS.
1748 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1749 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1750 PAT_VALUE(2, PAT_UNCACHED) |
1751 PAT_VALUE(3, PAT_UNCACHEABLE) |
1752 PAT_VALUE(4, PAT_WRITE_BACK) |
1753 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1754 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1755 PAT_VALUE(7, PAT_UNCACHEABLE);
1759 load_cr4(cr4 & ~CR4_PGE);
1761 /* Disable caches (CD = 1, NW = 0). */
1763 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1765 /* Flushes caches and TLBs. */
1769 /* Update PAT and index table. */
1770 wrmsr(MSR_PAT, pat_msr);
1772 /* Flush caches and TLBs again. */
1776 /* Restore caches and PGE. */
1782 * Initialize a vm_page's machine-dependent fields.
1785 pmap_page_init(vm_page_t m)
1788 TAILQ_INIT(&m->md.pv_list);
1789 m->md.pat_mode = PAT_WRITE_BACK;
1792 static int pmap_allow_2m_x_ept;
1793 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1794 &pmap_allow_2m_x_ept, 0,
1795 "Allow executable superpage mappings in EPT");
1798 pmap_allow_2m_x_ept_recalculate(void)
1801 * SKL002, SKL012S. Since the EPT format is only used by
1802 * Intel CPUs, the vendor check is merely a formality.
1804 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1805 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1806 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1807 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1808 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1809 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1810 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1811 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1812 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1813 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1814 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1815 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1816 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1817 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1818 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1819 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1820 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1821 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1822 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1823 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1824 CPUID_TO_MODEL(cpu_id) == 0x85))))
1825 pmap_allow_2m_x_ept = 1;
1826 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1830 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1833 return (pmap->pm_type != PT_EPT || !executable ||
1834 !pmap_allow_2m_x_ept);
1838 * Initialize the pmap module.
1839 * Called by vm_init, to initialize any structures that the pmap
1840 * system needs to map virtual memory.
1845 struct pmap_preinit_mapping *ppim;
1848 int error, i, pv_npg, ret, skz63;
1850 /* L1TF, reserve page @0 unconditionally */
1851 vm_page_blacklist_add(0, bootverbose);
1853 /* Detect bare-metal Skylake Server and Skylake-X. */
1854 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
1855 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
1857 * Skylake-X errata SKZ63. Processor May Hang When
1858 * Executing Code In an HLE Transaction Region between
1859 * 40000000H and 403FFFFFH.
1861 * Mark the pages in the range as preallocated. It
1862 * seems to be impossible to distinguish between
1863 * Skylake Server and Skylake X.
1866 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
1869 printf("SKZ63: skipping 4M RAM starting "
1870 "at physical 1G\n");
1871 for (i = 0; i < atop(0x400000); i++) {
1872 ret = vm_page_blacklist_add(0x40000000 +
1874 if (!ret && bootverbose)
1875 printf("page at %#lx already used\n",
1876 0x40000000 + ptoa(i));
1882 pmap_allow_2m_x_ept_recalculate();
1885 * Initialize the vm page array entries for the kernel pmap's
1888 PMAP_LOCK(kernel_pmap);
1889 for (i = 0; i < nkpt; i++) {
1890 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
1891 KASSERT(mpte >= vm_page_array &&
1892 mpte < &vm_page_array[vm_page_array_size],
1893 ("pmap_init: page table page is out of range"));
1894 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
1895 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
1896 mpte->wire_count = 1;
1899 * Collect the page table pages that were replaced by a 2MB
1900 * page in create_pagetables(). They are zero filled.
1902 if (i << PDRSHIFT < KERNend &&
1903 pmap_insert_pt_page(kernel_pmap, mpte, false))
1904 panic("pmap_init: pmap_insert_pt_page failed");
1906 PMAP_UNLOCK(kernel_pmap);
1910 * If the kernel is running on a virtual machine, then it must assume
1911 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1912 * be prepared for the hypervisor changing the vendor and family that
1913 * are reported by CPUID. Consequently, the workaround for AMD Family
1914 * 10h Erratum 383 is enabled if the processor's feature set does not
1915 * include at least one feature that is only supported by older Intel
1916 * or newer AMD processors.
1918 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1919 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1920 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1922 workaround_erratum383 = 1;
1925 * Are large page mappings enabled?
1927 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1928 if (pg_ps_enabled) {
1929 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1930 ("pmap_init: can't assign to pagesizes[1]"));
1931 pagesizes[1] = NBPDR;
1935 * Initialize the pv chunk list mutex.
1937 mtx_init(&pv_chunks_mutex, "pmap pv chunk list", NULL, MTX_DEF);
1940 * Initialize the pool of pv list locks.
1942 for (i = 0; i < NPV_LIST_LOCKS; i++)
1943 rw_init(&pv_list_locks[i], "pmap pv list");
1946 * Calculate the size of the pv head table for superpages.
1948 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
1951 * Allocate memory for the pv head table for superpages.
1953 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1955 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
1956 for (i = 0; i < pv_npg; i++)
1957 TAILQ_INIT(&pv_table[i].pv_list);
1958 TAILQ_INIT(&pv_dummy.pv_list);
1960 pmap_initialized = 1;
1961 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1962 ppim = pmap_preinit_mapping + i;
1965 /* Make the direct map consistent */
1966 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
1967 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
1968 ppim->sz, ppim->mode);
1972 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
1973 ppim->pa, ppim->va, ppim->sz, ppim->mode);
1976 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
1977 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
1978 (vmem_addr_t *)&qframe);
1980 panic("qframe allocation failed");
1983 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
1984 if (lm_ents > LMEPML4I - LMSPML4I + 1)
1985 lm_ents = LMEPML4I - LMSPML4I + 1;
1987 printf("pmap: large map %u PML4 slots (%lu Gb)\n",
1988 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
1990 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
1991 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
1992 if (large_vmem == NULL) {
1993 printf("pmap: cannot create large map\n");
1996 for (i = 0; i < lm_ents; i++) {
1997 m = pmap_large_map_getptp_unlocked();
1998 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
1999 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2005 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
2006 "2MB page mapping counters");
2008 static u_long pmap_pde_demotions;
2009 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2010 &pmap_pde_demotions, 0, "2MB page demotions");
2012 static u_long pmap_pde_mappings;
2013 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2014 &pmap_pde_mappings, 0, "2MB page mappings");
2016 static u_long pmap_pde_p_failures;
2017 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2018 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2020 static u_long pmap_pde_promotions;
2021 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2022 &pmap_pde_promotions, 0, "2MB page promotions");
2024 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
2025 "1GB page mapping counters");
2027 static u_long pmap_pdpe_demotions;
2028 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2029 &pmap_pdpe_demotions, 0, "1GB page demotions");
2031 /***************************************************
2032 * Low level helper routines.....
2033 ***************************************************/
2036 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2038 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2040 switch (pmap->pm_type) {
2043 /* Verify that both PAT bits are not set at the same time */
2044 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2045 ("Invalid PAT bits in entry %#lx", entry));
2047 /* Swap the PAT bits if one of them is set */
2048 if ((entry & x86_pat_bits) != 0)
2049 entry ^= x86_pat_bits;
2053 * Nothing to do - the memory attributes are represented
2054 * the same way for regular pages and superpages.
2058 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2065 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2068 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2069 pat_index[(int)mode] >= 0);
2073 * Determine the appropriate bits to set in a PTE or PDE for a specified
2077 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2079 int cache_bits, pat_flag, pat_idx;
2081 if (!pmap_is_valid_memattr(pmap, mode))
2082 panic("Unknown caching mode %d\n", mode);
2084 switch (pmap->pm_type) {
2087 /* The PAT bit is different for PTE's and PDE's. */
2088 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2090 /* Map the caching mode to a PAT index. */
2091 pat_idx = pat_index[mode];
2093 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2096 cache_bits |= pat_flag;
2098 cache_bits |= PG_NC_PCD;
2100 cache_bits |= PG_NC_PWT;
2104 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2108 panic("unsupported pmap type %d", pmap->pm_type);
2111 return (cache_bits);
2115 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2119 switch (pmap->pm_type) {
2122 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2125 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2128 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2135 pmap_ps_enabled(pmap_t pmap)
2138 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2142 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2145 switch (pmap->pm_type) {
2152 * This is a little bogus since the generation number is
2153 * supposed to be bumped up when a region of the address
2154 * space is invalidated in the page tables.
2156 * In this case the old PDE entry is valid but yet we want
2157 * to make sure that any mappings using the old entry are
2158 * invalidated in the TLB.
2160 * The reason this works as expected is because we rendezvous
2161 * "all" host cpus and force any vcpu context to exit as a
2164 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2167 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2169 pde_store(pde, newpde);
2173 * After changing the page size for the specified virtual address in the page
2174 * table, flush the corresponding entries from the processor's TLB. Only the
2175 * calling processor's TLB is affected.
2177 * The calling thread must be pinned to a processor.
2180 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2184 if (pmap_type_guest(pmap))
2187 KASSERT(pmap->pm_type == PT_X86,
2188 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2190 PG_G = pmap_global_bit(pmap);
2192 if ((newpde & PG_PS) == 0)
2193 /* Demotion: flush a specific 2MB page mapping. */
2195 else if ((newpde & PG_G) == 0)
2197 * Promotion: flush every 4KB page mapping from the TLB
2198 * because there are too many to flush individually.
2203 * Promotion: flush every 4KB page mapping from the TLB,
2204 * including any global (PG_G) mappings.
2212 * For SMP, these functions have to use the IPI mechanism for coherence.
2214 * N.B.: Before calling any of the following TLB invalidation functions,
2215 * the calling processor must ensure that all stores updating a non-
2216 * kernel page table are globally performed. Otherwise, another
2217 * processor could cache an old, pre-update entry without being
2218 * invalidated. This can happen one of two ways: (1) The pmap becomes
2219 * active on another processor after its pm_active field is checked by
2220 * one of the following functions but before a store updating the page
2221 * table is globally performed. (2) The pmap becomes active on another
2222 * processor before its pm_active field is checked but due to
2223 * speculative loads one of the following functions stills reads the
2224 * pmap as inactive on the other processor.
2226 * The kernel page table is exempt because its pm_active field is
2227 * immutable. The kernel page table is always active on every
2232 * Interrupt the cpus that are executing in the guest context.
2233 * This will force the vcpu to exit and the cached EPT mappings
2234 * will be invalidated by the host before the next vmresume.
2236 static __inline void
2237 pmap_invalidate_ept(pmap_t pmap)
2242 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2243 ("pmap_invalidate_ept: absurd pm_active"));
2246 * The TLB mappings associated with a vcpu context are not
2247 * flushed each time a different vcpu is chosen to execute.
2249 * This is in contrast with a process's vtop mappings that
2250 * are flushed from the TLB on each context switch.
2252 * Therefore we need to do more than just a TLB shootdown on
2253 * the active cpus in 'pmap->pm_active'. To do this we keep
2254 * track of the number of invalidations performed on this pmap.
2256 * Each vcpu keeps a cache of this counter and compares it
2257 * just before a vmresume. If the counter is out-of-date an
2258 * invept will be done to flush stale mappings from the TLB.
2260 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2263 * Force the vcpu to exit and trap back into the hypervisor.
2265 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2266 ipi_selected(pmap->pm_active, ipinum);
2271 pmap_invalidate_cpu_mask(pmap_t pmap)
2274 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2278 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2279 const bool invpcid_works1)
2281 struct invpcid_descr d;
2282 uint64_t kcr3, ucr3;
2286 cpuid = PCPU_GET(cpuid);
2287 if (pmap == PCPU_GET(curpmap)) {
2288 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2290 * Because pm_pcid is recalculated on a
2291 * context switch, we must disable switching.
2292 * Otherwise, we might use a stale value
2296 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2297 if (invpcid_works1) {
2298 d.pcid = pcid | PMAP_PCID_USER_PT;
2301 invpcid(&d, INVPCID_ADDR);
2303 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2304 ucr3 = pmap->pm_ucr3 | pcid |
2305 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2306 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2311 pmap->pm_pcids[cpuid].pm_gen = 0;
2315 pmap->pm_pcids[i].pm_gen = 0;
2319 * The fence is between stores to pm_gen and the read of the
2320 * pm_active mask. We need to ensure that it is impossible
2321 * for us to miss the bit update in pm_active and
2322 * simultaneously observe a non-zero pm_gen in
2323 * pmap_activate_sw(), otherwise TLB update is missed.
2324 * Without the fence, IA32 allows such an outcome. Note that
2325 * pm_active is updated by a locked operation, which provides
2326 * the reciprocal fence.
2328 atomic_thread_fence_seq_cst();
2332 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2335 pmap_invalidate_page_pcid(pmap, va, true);
2339 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2342 pmap_invalidate_page_pcid(pmap, va, false);
2346 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2350 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t),
2354 if (pmap_pcid_enabled)
2355 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2356 pmap_invalidate_page_pcid_noinvpcid);
2357 return (pmap_invalidate_page_nopcid);
2361 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2364 if (pmap_type_guest(pmap)) {
2365 pmap_invalidate_ept(pmap);
2369 KASSERT(pmap->pm_type == PT_X86,
2370 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2373 if (pmap == kernel_pmap) {
2376 if (pmap == PCPU_GET(curpmap))
2378 pmap_invalidate_page_mode(pmap, va);
2380 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2384 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2385 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2388 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2389 const bool invpcid_works1)
2391 struct invpcid_descr d;
2392 uint64_t kcr3, ucr3;
2396 cpuid = PCPU_GET(cpuid);
2397 if (pmap == PCPU_GET(curpmap)) {
2398 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2400 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2401 if (invpcid_works1) {
2402 d.pcid = pcid | PMAP_PCID_USER_PT;
2405 for (; d.addr < eva; d.addr += PAGE_SIZE)
2406 invpcid(&d, INVPCID_ADDR);
2408 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2409 ucr3 = pmap->pm_ucr3 | pcid |
2410 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2411 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2416 pmap->pm_pcids[cpuid].pm_gen = 0;
2420 pmap->pm_pcids[i].pm_gen = 0;
2422 /* See the comment in pmap_invalidate_page_pcid(). */
2423 atomic_thread_fence_seq_cst();
2427 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2431 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2435 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2439 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2443 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2447 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2448 vm_offset_t), static)
2451 if (pmap_pcid_enabled)
2452 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2453 pmap_invalidate_range_pcid_noinvpcid);
2454 return (pmap_invalidate_range_nopcid);
2458 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2462 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2463 pmap_invalidate_all(pmap);
2467 if (pmap_type_guest(pmap)) {
2468 pmap_invalidate_ept(pmap);
2472 KASSERT(pmap->pm_type == PT_X86,
2473 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2476 if (pmap == kernel_pmap) {
2477 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2480 if (pmap == PCPU_GET(curpmap)) {
2481 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2484 pmap_invalidate_range_mode(pmap, sva, eva);
2486 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2491 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2493 struct invpcid_descr d;
2494 uint64_t kcr3, ucr3;
2498 if (pmap == kernel_pmap) {
2499 if (invpcid_works1) {
2500 bzero(&d, sizeof(d));
2501 invpcid(&d, INVPCID_CTXGLOB);
2506 cpuid = PCPU_GET(cpuid);
2507 if (pmap == PCPU_GET(curpmap)) {
2509 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2510 if (invpcid_works1) {
2514 invpcid(&d, INVPCID_CTX);
2515 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2516 d.pcid |= PMAP_PCID_USER_PT;
2517 invpcid(&d, INVPCID_CTX);
2520 kcr3 = pmap->pm_cr3 | pcid;
2521 ucr3 = pmap->pm_ucr3;
2522 if (ucr3 != PMAP_NO_CR3) {
2523 ucr3 |= pcid | PMAP_PCID_USER_PT;
2524 pmap_pti_pcid_invalidate(ucr3, kcr3);
2531 pmap->pm_pcids[cpuid].pm_gen = 0;
2534 pmap->pm_pcids[i].pm_gen = 0;
2537 /* See the comment in pmap_invalidate_page_pcid(). */
2538 atomic_thread_fence_seq_cst();
2542 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2545 pmap_invalidate_all_pcid(pmap, true);
2549 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2552 pmap_invalidate_all_pcid(pmap, false);
2556 pmap_invalidate_all_nopcid(pmap_t pmap)
2559 if (pmap == kernel_pmap)
2561 else if (pmap == PCPU_GET(curpmap))
2565 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t), static)
2568 if (pmap_pcid_enabled)
2569 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2570 pmap_invalidate_all_pcid_noinvpcid);
2571 return (pmap_invalidate_all_nopcid);
2575 pmap_invalidate_all(pmap_t pmap)
2578 if (pmap_type_guest(pmap)) {
2579 pmap_invalidate_ept(pmap);
2583 KASSERT(pmap->pm_type == PT_X86,
2584 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2587 pmap_invalidate_all_mode(pmap);
2588 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2593 pmap_invalidate_cache(void)
2603 cpuset_t invalidate; /* processors that invalidate their TLB */
2608 u_int store; /* processor that updates the PDE */
2612 pmap_update_pde_action(void *arg)
2614 struct pde_action *act = arg;
2616 if (act->store == PCPU_GET(cpuid))
2617 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2621 pmap_update_pde_teardown(void *arg)
2623 struct pde_action *act = arg;
2625 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2626 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2630 * Change the page size for the specified virtual address in a way that
2631 * prevents any possibility of the TLB ever having two entries that map the
2632 * same virtual address using different page sizes. This is the recommended
2633 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2634 * machine check exception for a TLB state that is improperly diagnosed as a
2638 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2640 struct pde_action act;
2641 cpuset_t active, other_cpus;
2645 cpuid = PCPU_GET(cpuid);
2646 other_cpus = all_cpus;
2647 CPU_CLR(cpuid, &other_cpus);
2648 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2651 active = pmap->pm_active;
2653 if (CPU_OVERLAP(&active, &other_cpus)) {
2655 act.invalidate = active;
2659 act.newpde = newpde;
2660 CPU_SET(cpuid, &active);
2661 smp_rendezvous_cpus(active,
2662 smp_no_rendezvous_barrier, pmap_update_pde_action,
2663 pmap_update_pde_teardown, &act);
2665 pmap_update_pde_store(pmap, pde, newpde);
2666 if (CPU_ISSET(cpuid, &active))
2667 pmap_update_pde_invalidate(pmap, va, newpde);
2673 * Normal, non-SMP, invalidation functions.
2676 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2678 struct invpcid_descr d;
2679 uint64_t kcr3, ucr3;
2682 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2686 KASSERT(pmap->pm_type == PT_X86,
2687 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2689 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2691 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2692 pmap->pm_ucr3 != PMAP_NO_CR3) {
2694 pcid = pmap->pm_pcids[0].pm_pcid;
2695 if (invpcid_works) {
2696 d.pcid = pcid | PMAP_PCID_USER_PT;
2699 invpcid(&d, INVPCID_ADDR);
2701 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2702 ucr3 = pmap->pm_ucr3 | pcid |
2703 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2704 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2708 } else if (pmap_pcid_enabled)
2709 pmap->pm_pcids[0].pm_gen = 0;
2713 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2715 struct invpcid_descr d;
2717 uint64_t kcr3, ucr3;
2719 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2723 KASSERT(pmap->pm_type == PT_X86,
2724 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2726 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2727 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2729 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2730 pmap->pm_ucr3 != PMAP_NO_CR3) {
2732 if (invpcid_works) {
2733 d.pcid = pmap->pm_pcids[0].pm_pcid |
2737 for (; d.addr < eva; d.addr += PAGE_SIZE)
2738 invpcid(&d, INVPCID_ADDR);
2740 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2741 pm_pcid | CR3_PCID_SAVE;
2742 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2743 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2744 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2748 } else if (pmap_pcid_enabled) {
2749 pmap->pm_pcids[0].pm_gen = 0;
2754 pmap_invalidate_all(pmap_t pmap)
2756 struct invpcid_descr d;
2757 uint64_t kcr3, ucr3;
2759 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2763 KASSERT(pmap->pm_type == PT_X86,
2764 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2766 if (pmap == kernel_pmap) {
2767 if (pmap_pcid_enabled && invpcid_works) {
2768 bzero(&d, sizeof(d));
2769 invpcid(&d, INVPCID_CTXGLOB);
2773 } else if (pmap == PCPU_GET(curpmap)) {
2774 if (pmap_pcid_enabled) {
2776 if (invpcid_works) {
2777 d.pcid = pmap->pm_pcids[0].pm_pcid;
2780 invpcid(&d, INVPCID_CTX);
2781 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2782 d.pcid |= PMAP_PCID_USER_PT;
2783 invpcid(&d, INVPCID_CTX);
2786 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
2787 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2788 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
2789 0].pm_pcid | PMAP_PCID_USER_PT;
2790 pmap_pti_pcid_invalidate(ucr3, kcr3);
2798 } else if (pmap_pcid_enabled) {
2799 pmap->pm_pcids[0].pm_gen = 0;
2804 pmap_invalidate_cache(void)
2811 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2814 pmap_update_pde_store(pmap, pde, newpde);
2815 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
2816 pmap_update_pde_invalidate(pmap, va, newpde);
2818 pmap->pm_pcids[0].pm_gen = 0;
2823 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
2827 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
2828 * by a promotion that did not invalidate the 512 4KB page mappings
2829 * that might exist in the TLB. Consequently, at this point, the TLB
2830 * may hold both 4KB and 2MB page mappings for the address range [va,
2831 * va + NBPDR). Therefore, the entire range must be invalidated here.
2832 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
2833 * 4KB page mappings for the address range [va, va + NBPDR), and so a
2834 * single INVLPG suffices to invalidate the 2MB page mapping from the
2837 if ((pde & PG_PROMOTED) != 0)
2838 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
2840 pmap_invalidate_page(pmap, va);
2843 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
2844 (vm_offset_t sva, vm_offset_t eva), static)
2847 if ((cpu_feature & CPUID_SS) != 0)
2848 return (pmap_invalidate_cache_range_selfsnoop);
2849 if ((cpu_feature & CPUID_CLFSH) != 0)
2850 return (pmap_force_invalidate_cache_range);
2851 return (pmap_invalidate_cache_range_all);
2854 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
2857 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
2860 KASSERT((sva & PAGE_MASK) == 0,
2861 ("pmap_invalidate_cache_range: sva not page-aligned"));
2862 KASSERT((eva & PAGE_MASK) == 0,
2863 ("pmap_invalidate_cache_range: eva not page-aligned"));
2867 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
2870 pmap_invalidate_cache_range_check_align(sva, eva);
2874 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
2877 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
2880 * XXX: Some CPUs fault, hang, or trash the local APIC
2881 * registers if we use CLFLUSH on the local APIC range. The
2882 * local APIC is always uncached, so we don't need to flush
2883 * for that range anyway.
2885 if (pmap_kextract(sva) == lapic_paddr)
2888 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
2890 * Do per-cache line flush. Use the sfence
2891 * instruction to insure that previous stores are
2892 * included in the write-back. The processor
2893 * propagates flush to other processors in the cache
2897 for (; sva < eva; sva += cpu_clflush_line_size)
2902 * Writes are ordered by CLFLUSH on Intel CPUs.
2904 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2906 for (; sva < eva; sva += cpu_clflush_line_size)
2908 if (cpu_vendor_id != CPU_VENDOR_INTEL)
2914 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
2917 pmap_invalidate_cache_range_check_align(sva, eva);
2918 pmap_invalidate_cache();
2922 * Remove the specified set of pages from the data and instruction caches.
2924 * In contrast to pmap_invalidate_cache_range(), this function does not
2925 * rely on the CPU's self-snoop feature, because it is intended for use
2926 * when moving pages into a different cache domain.
2929 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
2931 vm_offset_t daddr, eva;
2935 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
2936 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
2937 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
2938 pmap_invalidate_cache();
2942 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2944 for (i = 0; i < count; i++) {
2945 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
2946 eva = daddr + PAGE_SIZE;
2947 for (; daddr < eva; daddr += cpu_clflush_line_size) {
2956 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
2962 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
2965 pmap_invalidate_cache_range_check_align(sva, eva);
2967 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
2968 pmap_force_invalidate_cache_range(sva, eva);
2972 /* See comment in pmap_force_invalidate_cache_range(). */
2973 if (pmap_kextract(sva) == lapic_paddr)
2977 for (; sva < eva; sva += cpu_clflush_line_size)
2983 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
2987 int error, pte_bits;
2989 KASSERT((spa & PAGE_MASK) == 0,
2990 ("pmap_flush_cache_phys_range: spa not page-aligned"));
2991 KASSERT((epa & PAGE_MASK) == 0,
2992 ("pmap_flush_cache_phys_range: epa not page-aligned"));
2994 if (spa < dmaplimit) {
2995 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
2997 if (dmaplimit >= epa)
3002 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3004 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3006 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3007 pte = vtopte(vaddr);
3008 for (; spa < epa; spa += PAGE_SIZE) {
3010 pte_store(pte, spa | pte_bits);
3012 /* XXXKIB sfences inside flush_cache_range are excessive */
3013 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3016 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3020 * Routine: pmap_extract
3022 * Extract the physical page address associated
3023 * with the given map/virtual_address pair.
3026 pmap_extract(pmap_t pmap, vm_offset_t va)
3030 pt_entry_t *pte, PG_V;
3034 PG_V = pmap_valid_bit(pmap);
3036 pdpe = pmap_pdpe(pmap, va);
3037 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3038 if ((*pdpe & PG_PS) != 0)
3039 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3041 pde = pmap_pdpe_to_pde(pdpe, va);
3042 if ((*pde & PG_V) != 0) {
3043 if ((*pde & PG_PS) != 0) {
3044 pa = (*pde & PG_PS_FRAME) |
3047 pte = pmap_pde_to_pte(pde, va);
3048 pa = (*pte & PG_FRAME) |
3059 * Routine: pmap_extract_and_hold
3061 * Atomically extract and hold the physical page
3062 * with the given pmap and virtual address pair
3063 * if that mapping permits the given protection.
3066 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3068 pd_entry_t pde, *pdep;
3069 pt_entry_t pte, PG_RW, PG_V;
3075 PG_RW = pmap_rw_bit(pmap);
3076 PG_V = pmap_valid_bit(pmap);
3079 pdep = pmap_pde(pmap, va);
3080 if (pdep != NULL && (pde = *pdep)) {
3082 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
3083 if (vm_page_pa_tryrelock(pmap, (pde &
3084 PG_PS_FRAME) | (va & PDRMASK), &pa))
3086 m = PHYS_TO_VM_PAGE(pa);
3089 pte = *pmap_pde_to_pte(pdep, va);
3091 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
3092 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
3095 m = PHYS_TO_VM_PAGE(pa);
3107 pmap_kextract(vm_offset_t va)
3112 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3113 pa = DMAP_TO_PHYS(va);
3114 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3115 pa = pmap_large_map_kextract(va);
3119 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3122 * Beware of a concurrent promotion that changes the
3123 * PDE at this point! For example, vtopte() must not
3124 * be used to access the PTE because it would use the
3125 * new PDE. It is, however, safe to use the old PDE
3126 * because the page table page is preserved by the
3129 pa = *pmap_pde_to_pte(&pde, va);
3130 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3136 /***************************************************
3137 * Low level mapping routines.....
3138 ***************************************************/
3141 * Add a wired page to the kva.
3142 * Note: not SMP coherent.
3145 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3150 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g);
3153 static __inline void
3154 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3160 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3161 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | cache_bits);
3165 * Remove a page from the kernel pagetables.
3166 * Note: not SMP coherent.
3169 pmap_kremove(vm_offset_t va)
3178 * Used to map a range of physical addresses into kernel
3179 * virtual address space.
3181 * The value passed in '*virt' is a suggested virtual address for
3182 * the mapping. Architectures which can support a direct-mapped
3183 * physical to virtual region can return the appropriate address
3184 * within that region, leaving '*virt' unchanged. Other
3185 * architectures should map the pages starting at '*virt' and
3186 * update '*virt' with the first usable address after the mapped
3190 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3192 return PHYS_TO_DMAP(start);
3197 * Add a list of wired pages to the kva
3198 * this routine is only used for temporary
3199 * kernel mappings that do not need to have
3200 * page modification or references recorded.
3201 * Note that old mappings are simply written
3202 * over. The page *must* be wired.
3203 * Note: SMP coherent. Uses a ranged shootdown IPI.
3206 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3208 pt_entry_t *endpte, oldpte, pa, *pte;
3214 endpte = pte + count;
3215 while (pte < endpte) {
3217 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3218 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3219 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3221 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3225 if (__predict_false((oldpte & X86_PG_V) != 0))
3226 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3231 * This routine tears out page mappings from the
3232 * kernel -- it is meant only for temporary mappings.
3233 * Note: SMP coherent. Uses a ranged shootdown IPI.
3236 pmap_qremove(vm_offset_t sva, int count)
3241 while (count-- > 0) {
3242 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3246 pmap_invalidate_range(kernel_pmap, sva, va);
3249 /***************************************************
3250 * Page table page management routines.....
3251 ***************************************************/
3253 * Schedule the specified unused page table page to be freed. Specifically,
3254 * add the page to the specified list of pages that will be released to the
3255 * physical memory manager after the TLB has been updated.
3257 static __inline void
3258 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3259 boolean_t set_PG_ZERO)
3263 m->flags |= PG_ZERO;
3265 m->flags &= ~PG_ZERO;
3266 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3270 * Inserts the specified page table page into the specified pmap's collection
3271 * of idle page table pages. Each of a pmap's page table pages is responsible
3272 * for mapping a distinct range of virtual addresses. The pmap's collection is
3273 * ordered by this virtual address range.
3275 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3278 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3281 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3282 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3283 return (vm_radix_insert(&pmap->pm_root, mpte));
3287 * Removes the page table page mapping the specified virtual address from the
3288 * specified pmap's collection of idle page table pages, and returns it.
3289 * Otherwise, returns NULL if there is no page table page corresponding to the
3290 * specified virtual address.
3292 static __inline vm_page_t
3293 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3296 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3297 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3301 * Decrements a page table page's wire count, which is used to record the
3302 * number of valid page table entries within the page. If the wire count
3303 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3304 * page table page was unmapped and FALSE otherwise.
3306 static inline boolean_t
3307 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3311 if (m->wire_count == 0) {
3312 _pmap_unwire_ptp(pmap, va, m, free);
3319 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3322 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3324 * unmap the page table page
3326 if (m->pindex >= (NUPDE + NUPDPE)) {
3329 pml4 = pmap_pml4e(pmap, va);
3331 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3332 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3335 } else if (m->pindex >= NUPDE) {
3338 pdp = pmap_pdpe(pmap, va);
3343 pd = pmap_pde(pmap, va);
3346 pmap_resident_count_dec(pmap, 1);
3347 if (m->pindex < NUPDE) {
3348 /* We just released a PT, unhold the matching PD */
3351 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3352 pmap_unwire_ptp(pmap, va, pdpg, free);
3354 if (m->pindex >= NUPDE && m->pindex < (NUPDE + NUPDPE)) {
3355 /* We just released a PD, unhold the matching PDP */
3358 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3359 pmap_unwire_ptp(pmap, va, pdppg, free);
3363 * Put page on a list so that it is released after
3364 * *ALL* TLB shootdown is done
3366 pmap_add_delayed_free_list(m, free, TRUE);
3370 * After removing a page table entry, this routine is used to
3371 * conditionally free the page, and manage the hold/wire counts.
3374 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3375 struct spglist *free)
3379 if (va >= VM_MAXUSER_ADDRESS)
3381 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3382 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3383 return (pmap_unwire_ptp(pmap, va, mpte, free));
3387 pmap_pinit0(pmap_t pmap)
3393 PMAP_LOCK_INIT(pmap);
3394 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3395 pmap->pm_pml4u = NULL;
3396 pmap->pm_cr3 = KPML4phys;
3397 /* hack to keep pmap_pti_pcid_invalidate() alive */
3398 pmap->pm_ucr3 = PMAP_NO_CR3;
3399 pmap->pm_root.rt_root = 0;
3400 CPU_ZERO(&pmap->pm_active);
3401 TAILQ_INIT(&pmap->pm_pvchunk);
3402 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3403 pmap->pm_flags = pmap_flags;
3405 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3406 pmap->pm_pcids[i].pm_gen = 1;
3408 pmap_activate_boot(pmap);
3413 p->p_amd64_md_flags |= P_MD_KPTI;
3416 pmap_thread_init_invl_gen(td);
3418 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3419 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3420 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3426 pmap_pinit_pml4(vm_page_t pml4pg)
3428 pml4_entry_t *pm_pml4;
3431 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3433 /* Wire in kernel global address entries. */
3434 for (i = 0; i < NKPML4E; i++) {
3435 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3438 for (i = 0; i < ndmpdpphys; i++) {
3439 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3443 /* install self-referential address mapping entry(s) */
3444 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3445 X86_PG_A | X86_PG_M;
3447 /* install large map entries if configured */
3448 for (i = 0; i < lm_ents; i++)
3449 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3453 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3455 pml4_entry_t *pm_pml4;
3458 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3459 for (i = 0; i < NPML4EPG; i++)
3460 pm_pml4[i] = pti_pml4[i];
3464 * Initialize a preallocated and zeroed pmap structure,
3465 * such as one in a vmspace structure.
3468 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3470 vm_page_t pml4pg, pml4pgu;
3471 vm_paddr_t pml4phys;
3475 * allocate the page directory page
3477 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3478 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3480 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3481 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3483 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3484 pmap->pm_pcids[i].pm_gen = 0;
3486 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3487 pmap->pm_ucr3 = PMAP_NO_CR3;
3488 pmap->pm_pml4u = NULL;
3490 pmap->pm_type = pm_type;
3491 if ((pml4pg->flags & PG_ZERO) == 0)
3492 pagezero(pmap->pm_pml4);
3495 * Do not install the host kernel mappings in the nested page
3496 * tables. These mappings are meaningless in the guest physical
3498 * Install minimal kernel mappings in PTI case.
3500 if (pm_type == PT_X86) {
3501 pmap->pm_cr3 = pml4phys;
3502 pmap_pinit_pml4(pml4pg);
3503 if ((curproc->p_amd64_md_flags & P_MD_KPTI) != 0) {
3504 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3505 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3506 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3507 VM_PAGE_TO_PHYS(pml4pgu));
3508 pmap_pinit_pml4_pti(pml4pgu);
3509 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3511 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3512 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3513 pkru_free_range, pmap, M_NOWAIT);
3517 pmap->pm_root.rt_root = 0;
3518 CPU_ZERO(&pmap->pm_active);
3519 TAILQ_INIT(&pmap->pm_pvchunk);
3520 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3521 pmap->pm_flags = flags;
3522 pmap->pm_eptgen = 0;
3528 pmap_pinit(pmap_t pmap)
3531 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3535 * This routine is called if the desired page table page does not exist.
3537 * If page table page allocation fails, this routine may sleep before
3538 * returning NULL. It sleeps only if a lock pointer was given.
3540 * Note: If a page allocation fails at page table level two or three,
3541 * one or two pages may be held during the wait, only to be released
3542 * afterwards. This conservative approach is easily argued to avoid
3546 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3548 vm_page_t m, pdppg, pdpg;
3549 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3551 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3553 PG_A = pmap_accessed_bit(pmap);
3554 PG_M = pmap_modified_bit(pmap);
3555 PG_V = pmap_valid_bit(pmap);
3556 PG_RW = pmap_rw_bit(pmap);
3559 * Allocate a page table page.
3561 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3562 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3563 if (lockp != NULL) {
3564 RELEASE_PV_LIST_LOCK(lockp);
3566 PMAP_ASSERT_NOT_IN_DI();
3572 * Indicate the need to retry. While waiting, the page table
3573 * page may have been allocated.
3577 if ((m->flags & PG_ZERO) == 0)
3581 * Map the pagetable page into the process address space, if
3582 * it isn't already there.
3585 if (ptepindex >= (NUPDE + NUPDPE)) {
3586 pml4_entry_t *pml4, *pml4u;
3587 vm_pindex_t pml4index;
3589 /* Wire up a new PDPE page */
3590 pml4index = ptepindex - (NUPDE + NUPDPE);
3591 pml4 = &pmap->pm_pml4[pml4index];
3592 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3593 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3595 * PTI: Make all user-space mappings in the
3596 * kernel-mode page table no-execute so that
3597 * we detect any programming errors that leave
3598 * the kernel-mode page table active on return
3601 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3604 pml4u = &pmap->pm_pml4u[pml4index];
3605 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3609 } else if (ptepindex >= NUPDE) {
3610 vm_pindex_t pml4index;
3611 vm_pindex_t pdpindex;
3615 /* Wire up a new PDE page */
3616 pdpindex = ptepindex - NUPDE;
3617 pml4index = pdpindex >> NPML4EPGSHIFT;
3619 pml4 = &pmap->pm_pml4[pml4index];
3620 if ((*pml4 & PG_V) == 0) {
3621 /* Have to allocate a new pdp, recurse */
3622 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3624 vm_page_unwire_noq(m);
3625 vm_page_free_zero(m);
3629 /* Add reference to pdp page */
3630 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3631 pdppg->wire_count++;
3633 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3635 /* Now find the pdp page */
3636 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3637 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3640 vm_pindex_t pml4index;
3641 vm_pindex_t pdpindex;
3646 /* Wire up a new PTE page */
3647 pdpindex = ptepindex >> NPDPEPGSHIFT;
3648 pml4index = pdpindex >> NPML4EPGSHIFT;
3650 /* First, find the pdp and check that its valid. */
3651 pml4 = &pmap->pm_pml4[pml4index];
3652 if ((*pml4 & PG_V) == 0) {
3653 /* Have to allocate a new pd, recurse */
3654 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3656 vm_page_unwire_noq(m);
3657 vm_page_free_zero(m);
3660 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3661 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3663 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3664 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3665 if ((*pdp & PG_V) == 0) {
3666 /* Have to allocate a new pd, recurse */
3667 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3669 vm_page_unwire_noq(m);
3670 vm_page_free_zero(m);
3674 /* Add reference to the pd page */
3675 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3679 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3681 /* Now we know where the page directory page is */
3682 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3683 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3686 pmap_resident_count_inc(pmap, 1);
3692 pmap_allocpde(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3694 vm_pindex_t pdpindex, ptepindex;
3695 pdp_entry_t *pdpe, PG_V;
3698 PG_V = pmap_valid_bit(pmap);
3701 pdpe = pmap_pdpe(pmap, va);
3702 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3703 /* Add a reference to the pd page. */
3704 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3707 /* Allocate a pd page. */
3708 ptepindex = pmap_pde_pindex(va);
3709 pdpindex = ptepindex >> NPDPEPGSHIFT;
3710 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3711 if (pdpg == NULL && lockp != NULL)
3718 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3720 vm_pindex_t ptepindex;
3721 pd_entry_t *pd, PG_V;
3724 PG_V = pmap_valid_bit(pmap);
3727 * Calculate pagetable page index
3729 ptepindex = pmap_pde_pindex(va);
3732 * Get the page directory entry
3734 pd = pmap_pde(pmap, va);
3737 * This supports switching from a 2MB page to a
3740 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3741 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3743 * Invalidation of the 2MB page mapping may have caused
3744 * the deallocation of the underlying PD page.
3751 * If the page table page is mapped, we just increment the
3752 * hold count, and activate it.
3754 if (pd != NULL && (*pd & PG_V) != 0) {
3755 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
3759 * Here if the pte page isn't mapped, or if it has been
3762 m = _pmap_allocpte(pmap, ptepindex, lockp);
3763 if (m == NULL && lockp != NULL)
3770 /***************************************************
3771 * Pmap allocation/deallocation routines.
3772 ***************************************************/
3775 * Release any resources held by the given physical map.
3776 * Called when a pmap initialized by pmap_pinit is being released.
3777 * Should only be called if the map contains no valid mappings.
3780 pmap_release(pmap_t pmap)
3785 KASSERT(pmap->pm_stats.resident_count == 0,
3786 ("pmap_release: pmap resident count %ld != 0",
3787 pmap->pm_stats.resident_count));
3788 KASSERT(vm_radix_is_empty(&pmap->pm_root),
3789 ("pmap_release: pmap has reserved page table page(s)"));
3790 KASSERT(CPU_EMPTY(&pmap->pm_active),
3791 ("releasing active pmap %p", pmap));
3793 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
3795 for (i = 0; i < NKPML4E; i++) /* KVA */
3796 pmap->pm_pml4[KPML4BASE + i] = 0;
3797 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
3798 pmap->pm_pml4[DMPML4I + i] = 0;
3799 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
3800 for (i = 0; i < lm_ents; i++) /* Large Map */
3801 pmap->pm_pml4[LMSPML4I + i] = 0;
3803 vm_page_unwire_noq(m);
3804 vm_page_free_zero(m);
3806 if (pmap->pm_pml4u != NULL) {
3807 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
3808 vm_page_unwire_noq(m);
3811 if (pmap->pm_type == PT_X86 &&
3812 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
3813 rangeset_fini(&pmap->pm_pkru);
3817 kvm_size(SYSCTL_HANDLER_ARGS)
3819 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
3821 return sysctl_handle_long(oidp, &ksize, 0, req);
3823 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
3824 0, 0, kvm_size, "LU", "Size of KVM");
3827 kvm_free(SYSCTL_HANDLER_ARGS)
3829 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
3831 return sysctl_handle_long(oidp, &kfree, 0, req);
3833 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
3834 0, 0, kvm_free, "LU", "Amount of KVM free");
3837 * grow the number of kernel page table entries, if needed
3840 pmap_growkernel(vm_offset_t addr)
3844 pd_entry_t *pde, newpdir;
3847 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
3850 * Return if "addr" is within the range of kernel page table pages
3851 * that were preallocated during pmap bootstrap. Moreover, leave
3852 * "kernel_vm_end" and the kernel page table as they were.
3854 * The correctness of this action is based on the following
3855 * argument: vm_map_insert() allocates contiguous ranges of the
3856 * kernel virtual address space. It calls this function if a range
3857 * ends after "kernel_vm_end". If the kernel is mapped between
3858 * "kernel_vm_end" and "addr", then the range cannot begin at
3859 * "kernel_vm_end". In fact, its beginning address cannot be less
3860 * than the kernel. Thus, there is no immediate need to allocate
3861 * any new kernel page table pages between "kernel_vm_end" and
3864 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
3867 addr = roundup2(addr, NBPDR);
3868 if (addr - 1 >= vm_map_max(kernel_map))
3869 addr = vm_map_max(kernel_map);
3870 while (kernel_vm_end < addr) {
3871 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
3872 if ((*pdpe & X86_PG_V) == 0) {
3873 /* We need a new PDP entry */
3874 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
3875 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
3876 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
3878 panic("pmap_growkernel: no memory to grow kernel");
3879 if ((nkpg->flags & PG_ZERO) == 0)
3880 pmap_zero_page(nkpg);
3881 paddr = VM_PAGE_TO_PHYS(nkpg);
3882 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
3883 X86_PG_A | X86_PG_M);
3884 continue; /* try again */
3886 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
3887 if ((*pde & X86_PG_V) != 0) {
3888 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3889 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3890 kernel_vm_end = vm_map_max(kernel_map);
3896 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
3897 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
3900 panic("pmap_growkernel: no memory to grow kernel");
3901 if ((nkpg->flags & PG_ZERO) == 0)
3902 pmap_zero_page(nkpg);
3903 paddr = VM_PAGE_TO_PHYS(nkpg);
3904 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
3905 pde_store(pde, newpdir);
3907 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
3908 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
3909 kernel_vm_end = vm_map_max(kernel_map);
3916 /***************************************************
3917 * page management routines.
3918 ***************************************************/
3920 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
3921 CTASSERT(_NPCM == 3);
3922 CTASSERT(_NPCPV == 168);
3924 static __inline struct pv_chunk *
3925 pv_to_chunk(pv_entry_t pv)
3928 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
3931 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
3933 #define PC_FREE0 0xfffffffffffffffful
3934 #define PC_FREE1 0xfffffffffffffffful
3935 #define PC_FREE2 0x000000fffffffffful
3937 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
3940 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
3942 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
3943 "Current number of pv entry chunks");
3944 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
3945 "Current number of pv entry chunks allocated");
3946 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
3947 "Current number of pv entry chunks frees");
3948 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
3949 "Number of times tried to get a chunk page but failed.");
3951 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
3952 static int pv_entry_spare;
3954 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
3955 "Current number of pv entry frees");
3956 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
3957 "Current number of pv entry allocs");
3958 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
3959 "Current number of pv entries");
3960 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
3961 "Current number of spare pv entries");
3965 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
3970 pmap_invalidate_all(pmap);
3971 if (pmap != locked_pmap)
3974 pmap_delayed_invl_finish();
3978 * We are in a serious low memory condition. Resort to
3979 * drastic measures to free some pages so we can allocate
3980 * another pv entry chunk.
3982 * Returns NULL if PV entries were reclaimed from the specified pmap.
3984 * We do not, however, unmap 2mpages because subsequent accesses will
3985 * allocate per-page pv entries until repromotion occurs, thereby
3986 * exacerbating the shortage of free pv entries.
3989 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
3991 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
3992 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
3993 struct md_page *pvh;
3995 pmap_t next_pmap, pmap;
3996 pt_entry_t *pte, tpte;
3997 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4001 struct spglist free;
4003 int bit, field, freed;
4005 static int active_reclaims = 0;
4007 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4008 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4011 PG_G = PG_A = PG_M = PG_RW = 0;
4013 bzero(&pc_marker_b, sizeof(pc_marker_b));
4014 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4015 pc_marker = (struct pv_chunk *)&pc_marker_b;
4016 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4019 * A delayed invalidation block should already be active if
4020 * pmap_advise() or pmap_remove() called this function by way
4021 * of pmap_demote_pde_locked().
4023 start_di = pmap_not_in_di();
4025 mtx_lock(&pv_chunks_mutex);
4027 TAILQ_INSERT_HEAD(&pv_chunks, pc_marker, pc_lru);
4028 TAILQ_INSERT_TAIL(&pv_chunks, pc_marker_end, pc_lru);
4029 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4030 SLIST_EMPTY(&free)) {
4031 next_pmap = pc->pc_pmap;
4032 if (next_pmap == NULL) {
4034 * The next chunk is a marker. However, it is
4035 * not our marker, so active_reclaims must be
4036 * > 1. Consequently, the next_chunk code
4037 * will not rotate the pv_chunks list.
4041 mtx_unlock(&pv_chunks_mutex);
4044 * A pv_chunk can only be removed from the pc_lru list
4045 * when both pc_chunks_mutex is owned and the
4046 * corresponding pmap is locked.
4048 if (pmap != next_pmap) {
4049 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4052 /* Avoid deadlock and lock recursion. */
4053 if (pmap > locked_pmap) {
4054 RELEASE_PV_LIST_LOCK(lockp);
4057 pmap_delayed_invl_start();
4058 mtx_lock(&pv_chunks_mutex);
4060 } else if (pmap != locked_pmap) {
4061 if (PMAP_TRYLOCK(pmap)) {
4063 pmap_delayed_invl_start();
4064 mtx_lock(&pv_chunks_mutex);
4067 pmap = NULL; /* pmap is not locked */
4068 mtx_lock(&pv_chunks_mutex);
4069 pc = TAILQ_NEXT(pc_marker, pc_lru);
4071 pc->pc_pmap != next_pmap)
4075 } else if (start_di)
4076 pmap_delayed_invl_start();
4077 PG_G = pmap_global_bit(pmap);
4078 PG_A = pmap_accessed_bit(pmap);
4079 PG_M = pmap_modified_bit(pmap);
4080 PG_RW = pmap_rw_bit(pmap);
4084 * Destroy every non-wired, 4 KB page mapping in the chunk.
4087 for (field = 0; field < _NPCM; field++) {
4088 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4089 inuse != 0; inuse &= ~(1UL << bit)) {
4091 pv = &pc->pc_pventry[field * 64 + bit];
4093 pde = pmap_pde(pmap, va);
4094 if ((*pde & PG_PS) != 0)
4096 pte = pmap_pde_to_pte(pde, va);
4097 if ((*pte & PG_W) != 0)
4099 tpte = pte_load_clear(pte);
4100 if ((tpte & PG_G) != 0)
4101 pmap_invalidate_page(pmap, va);
4102 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4103 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4105 if ((tpte & PG_A) != 0)
4106 vm_page_aflag_set(m, PGA_REFERENCED);
4107 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4108 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4110 if (TAILQ_EMPTY(&m->md.pv_list) &&
4111 (m->flags & PG_FICTITIOUS) == 0) {
4112 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4113 if (TAILQ_EMPTY(&pvh->pv_list)) {
4114 vm_page_aflag_clear(m,
4118 pmap_delayed_invl_page(m);
4119 pc->pc_map[field] |= 1UL << bit;
4120 pmap_unuse_pt(pmap, va, *pde, &free);
4125 mtx_lock(&pv_chunks_mutex);
4128 /* Every freed mapping is for a 4 KB page. */
4129 pmap_resident_count_dec(pmap, freed);
4130 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4131 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4132 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4133 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4134 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4135 pc->pc_map[2] == PC_FREE2) {
4136 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4137 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4138 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4139 /* Entire chunk is free; return it. */
4140 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4141 dump_drop_page(m_pc->phys_addr);
4142 mtx_lock(&pv_chunks_mutex);
4143 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4146 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4147 mtx_lock(&pv_chunks_mutex);
4148 /* One freed pv entry in locked_pmap is sufficient. */
4149 if (pmap == locked_pmap)
4152 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4153 TAILQ_INSERT_AFTER(&pv_chunks, pc, pc_marker, pc_lru);
4154 if (active_reclaims == 1 && pmap != NULL) {
4156 * Rotate the pv chunks list so that we do not
4157 * scan the same pv chunks that could not be
4158 * freed (because they contained a wired
4159 * and/or superpage mapping) on every
4160 * invocation of reclaim_pv_chunk().
4162 while ((pc = TAILQ_FIRST(&pv_chunks)) != pc_marker) {
4163 MPASS(pc->pc_pmap != NULL);
4164 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4165 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4169 TAILQ_REMOVE(&pv_chunks, pc_marker, pc_lru);
4170 TAILQ_REMOVE(&pv_chunks, pc_marker_end, pc_lru);
4172 mtx_unlock(&pv_chunks_mutex);
4173 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4174 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4175 m_pc = SLIST_FIRST(&free);
4176 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4177 /* Recycle a freed page table page. */
4178 m_pc->wire_count = 1;
4180 vm_page_free_pages_toq(&free, true);
4185 * free the pv_entry back to the free list
4188 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4190 struct pv_chunk *pc;
4191 int idx, field, bit;
4193 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4194 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4195 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4196 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4197 pc = pv_to_chunk(pv);
4198 idx = pv - &pc->pc_pventry[0];
4201 pc->pc_map[field] |= 1ul << bit;
4202 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4203 pc->pc_map[2] != PC_FREE2) {
4204 /* 98% of the time, pc is already at the head of the list. */
4205 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4206 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4207 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4211 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4216 free_pv_chunk(struct pv_chunk *pc)
4220 mtx_lock(&pv_chunks_mutex);
4221 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
4222 mtx_unlock(&pv_chunks_mutex);
4223 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4224 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4225 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4226 /* entire chunk is free, return it */
4227 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4228 dump_drop_page(m->phys_addr);
4229 vm_page_unwire_noq(m);
4234 * Returns a new PV entry, allocating a new PV chunk from the system when
4235 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4236 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4239 * The given PV list lock may be released.
4242 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4246 struct pv_chunk *pc;
4249 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4250 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4252 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4254 for (field = 0; field < _NPCM; field++) {
4255 if (pc->pc_map[field]) {
4256 bit = bsfq(pc->pc_map[field]);
4260 if (field < _NPCM) {
4261 pv = &pc->pc_pventry[field * 64 + bit];
4262 pc->pc_map[field] &= ~(1ul << bit);
4263 /* If this was the last item, move it to tail */
4264 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4265 pc->pc_map[2] == 0) {
4266 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4267 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4270 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4271 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4275 /* No free items, allocate another chunk */
4276 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4279 if (lockp == NULL) {
4280 PV_STAT(pc_chunk_tryfail++);
4283 m = reclaim_pv_chunk(pmap, lockp);
4287 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4288 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4289 dump_add_page(m->phys_addr);
4290 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4292 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4293 pc->pc_map[1] = PC_FREE1;
4294 pc->pc_map[2] = PC_FREE2;
4295 mtx_lock(&pv_chunks_mutex);
4296 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
4297 mtx_unlock(&pv_chunks_mutex);
4298 pv = &pc->pc_pventry[0];
4299 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4300 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4301 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4306 * Returns the number of one bits within the given PV chunk map.
4308 * The erratas for Intel processors state that "POPCNT Instruction May
4309 * Take Longer to Execute Than Expected". It is believed that the
4310 * issue is the spurious dependency on the destination register.
4311 * Provide a hint to the register rename logic that the destination
4312 * value is overwritten, by clearing it, as suggested in the
4313 * optimization manual. It should be cheap for unaffected processors
4316 * Reference numbers for erratas are
4317 * 4th Gen Core: HSD146
4318 * 5th Gen Core: BDM85
4319 * 6th Gen Core: SKL029
4322 popcnt_pc_map_pq(uint64_t *map)
4326 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4327 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4328 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4329 : "=&r" (result), "=&r" (tmp)
4330 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4335 * Ensure that the number of spare PV entries in the specified pmap meets or
4336 * exceeds the given count, "needed".
4338 * The given PV list lock may be released.
4341 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4343 struct pch new_tail;
4344 struct pv_chunk *pc;
4349 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4350 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4353 * Newly allocated PV chunks must be stored in a private list until
4354 * the required number of PV chunks have been allocated. Otherwise,
4355 * reclaim_pv_chunk() could recycle one of these chunks. In
4356 * contrast, these chunks must be added to the pmap upon allocation.
4358 TAILQ_INIT(&new_tail);
4361 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4363 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4364 bit_count((bitstr_t *)pc->pc_map, 0,
4365 sizeof(pc->pc_map) * NBBY, &free);
4368 free = popcnt_pc_map_pq(pc->pc_map);
4372 if (avail >= needed)
4375 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4376 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4379 m = reclaim_pv_chunk(pmap, lockp);
4384 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4385 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4386 dump_add_page(m->phys_addr);
4387 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4389 pc->pc_map[0] = PC_FREE0;
4390 pc->pc_map[1] = PC_FREE1;
4391 pc->pc_map[2] = PC_FREE2;
4392 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4393 TAILQ_INSERT_TAIL(&new_tail, pc, pc_lru);
4394 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4397 * The reclaim might have freed a chunk from the current pmap.
4398 * If that chunk contained available entries, we need to
4399 * re-count the number of available entries.
4404 if (!TAILQ_EMPTY(&new_tail)) {
4405 mtx_lock(&pv_chunks_mutex);
4406 TAILQ_CONCAT(&pv_chunks, &new_tail, pc_lru);
4407 mtx_unlock(&pv_chunks_mutex);
4412 * First find and then remove the pv entry for the specified pmap and virtual
4413 * address from the specified pv list. Returns the pv entry if found and NULL
4414 * otherwise. This operation can be performed on pv lists for either 4KB or
4415 * 2MB page mappings.
4417 static __inline pv_entry_t
4418 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4422 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4423 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4424 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4433 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4434 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4435 * entries for each of the 4KB page mappings.
4438 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4439 struct rwlock **lockp)
4441 struct md_page *pvh;
4442 struct pv_chunk *pc;
4444 vm_offset_t va_last;
4448 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4449 KASSERT((pa & PDRMASK) == 0,
4450 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4451 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4454 * Transfer the 2mpage's pv entry for this mapping to the first
4455 * page's pv list. Once this transfer begins, the pv list lock
4456 * must not be released until the last pv entry is reinstantiated.
4458 pvh = pa_to_pvh(pa);
4459 va = trunc_2mpage(va);
4460 pv = pmap_pvh_remove(pvh, pmap, va);
4461 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4462 m = PHYS_TO_VM_PAGE(pa);
4463 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4465 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4466 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4467 va_last = va + NBPDR - PAGE_SIZE;
4469 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4470 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4471 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4472 for (field = 0; field < _NPCM; field++) {
4473 while (pc->pc_map[field]) {
4474 bit = bsfq(pc->pc_map[field]);
4475 pc->pc_map[field] &= ~(1ul << bit);
4476 pv = &pc->pc_pventry[field * 64 + bit];
4480 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4481 ("pmap_pv_demote_pde: page %p is not managed", m));
4482 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4488 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4489 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4492 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4493 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4494 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4496 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4497 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4500 #if VM_NRESERVLEVEL > 0
4502 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4503 * replace the many pv entries for the 4KB page mappings by a single pv entry
4504 * for the 2MB page mapping.
4507 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4508 struct rwlock **lockp)
4510 struct md_page *pvh;
4512 vm_offset_t va_last;
4515 KASSERT((pa & PDRMASK) == 0,
4516 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4517 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4520 * Transfer the first page's pv entry for this mapping to the 2mpage's
4521 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4522 * a transfer avoids the possibility that get_pv_entry() calls
4523 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4524 * mappings that is being promoted.
4526 m = PHYS_TO_VM_PAGE(pa);
4527 va = trunc_2mpage(va);
4528 pv = pmap_pvh_remove(&m->md, pmap, va);
4529 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4530 pvh = pa_to_pvh(pa);
4531 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4533 /* Free the remaining NPTEPG - 1 pv entries. */
4534 va_last = va + NBPDR - PAGE_SIZE;
4538 pmap_pvh_free(&m->md, pmap, va);
4539 } while (va < va_last);
4541 #endif /* VM_NRESERVLEVEL > 0 */
4544 * First find and then destroy the pv entry for the specified pmap and virtual
4545 * address. This operation can be performed on pv lists for either 4KB or 2MB
4549 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4553 pv = pmap_pvh_remove(pvh, pmap, va);
4554 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4555 free_pv_entry(pmap, pv);
4559 * Conditionally create the PV entry for a 4KB page mapping if the required
4560 * memory can be allocated without resorting to reclamation.
4563 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4564 struct rwlock **lockp)
4568 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4569 /* Pass NULL instead of the lock pointer to disable reclamation. */
4570 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4572 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4573 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4581 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4582 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4583 * false if the PV entry cannot be allocated without resorting to reclamation.
4586 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4587 struct rwlock **lockp)
4589 struct md_page *pvh;
4593 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4594 /* Pass NULL instead of the lock pointer to disable reclamation. */
4595 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4596 NULL : lockp)) == NULL)
4599 pa = pde & PG_PS_FRAME;
4600 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4601 pvh = pa_to_pvh(pa);
4602 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4608 * Fills a page table page with mappings to consecutive physical pages.
4611 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4615 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4617 newpte += PAGE_SIZE;
4622 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4623 * mapping is invalidated.
4626 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4628 struct rwlock *lock;
4632 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4639 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4643 pt_entry_t *xpte, *ypte;
4645 for (xpte = firstpte; xpte < firstpte + NPTEPG;
4646 xpte++, newpte += PAGE_SIZE) {
4647 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
4648 printf("pmap_demote_pde: xpte %zd and newpte map "
4649 "different pages: found %#lx, expected %#lx\n",
4650 xpte - firstpte, *xpte, newpte);
4651 printf("page table dump\n");
4652 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
4653 printf("%zd %#lx\n", ypte - firstpte, *ypte);
4658 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
4659 ("pmap_demote_pde: firstpte and newpte map different physical"
4666 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4667 pd_entry_t oldpde, struct rwlock **lockp)
4669 struct spglist free;
4673 sva = trunc_2mpage(va);
4674 pmap_remove_pde(pmap, pde, sva, &free, lockp);
4675 if ((oldpde & pmap_global_bit(pmap)) == 0)
4676 pmap_invalidate_pde_page(pmap, sva, oldpde);
4677 vm_page_free_pages_toq(&free, true);
4678 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
4683 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
4684 struct rwlock **lockp)
4686 pd_entry_t newpde, oldpde;
4687 pt_entry_t *firstpte, newpte;
4688 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
4694 PG_A = pmap_accessed_bit(pmap);
4695 PG_G = pmap_global_bit(pmap);
4696 PG_M = pmap_modified_bit(pmap);
4697 PG_RW = pmap_rw_bit(pmap);
4698 PG_V = pmap_valid_bit(pmap);
4699 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
4700 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
4702 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4703 in_kernel = va >= VM_MAXUSER_ADDRESS;
4705 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
4706 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
4709 * Invalidate the 2MB page mapping and return "failure" if the
4710 * mapping was never accessed.
4712 if ((oldpde & PG_A) == 0) {
4713 KASSERT((oldpde & PG_W) == 0,
4714 ("pmap_demote_pde: a wired mapping is missing PG_A"));
4715 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4719 mpte = pmap_remove_pt_page(pmap, va);
4721 KASSERT((oldpde & PG_W) == 0,
4722 ("pmap_demote_pde: page table page for a wired mapping"
4726 * If the page table page is missing and the mapping
4727 * is for a kernel address, the mapping must belong to
4728 * the direct map. Page table pages are preallocated
4729 * for every other part of the kernel address space,
4730 * so the direct map region is the only part of the
4731 * kernel address space that must be handled here.
4733 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
4734 va < DMAP_MAX_ADDRESS),
4735 ("pmap_demote_pde: No saved mpte for va %#lx", va));
4738 * If the 2MB page mapping belongs to the direct map
4739 * region of the kernel's address space, then the page
4740 * allocation request specifies the highest possible
4741 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
4742 * priority is normal.
4744 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
4745 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
4746 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
4749 * If the allocation of the new page table page fails,
4750 * invalidate the 2MB page mapping and return "failure".
4753 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
4758 mpte->wire_count = NPTEPG;
4759 pmap_resident_count_inc(pmap, 1);
4762 mptepa = VM_PAGE_TO_PHYS(mpte);
4763 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
4764 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
4765 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
4766 ("pmap_demote_pde: oldpde is missing PG_M"));
4767 newpte = oldpde & ~PG_PS;
4768 newpte = pmap_swap_pat(pmap, newpte);
4771 * If the page table page is not leftover from an earlier promotion,
4774 if (mpte->valid == 0)
4775 pmap_fill_ptp(firstpte, newpte);
4777 pmap_demote_pde_check(firstpte, newpte);
4780 * If the mapping has changed attributes, update the page table
4783 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
4784 pmap_fill_ptp(firstpte, newpte);
4787 * The spare PV entries must be reserved prior to demoting the
4788 * mapping, that is, prior to changing the PDE. Otherwise, the state
4789 * of the PDE and the PV lists will be inconsistent, which can result
4790 * in reclaim_pv_chunk() attempting to remove a PV entry from the
4791 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
4792 * PV entry for the 2MB page mapping that is being demoted.
4794 if ((oldpde & PG_MANAGED) != 0)
4795 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
4798 * Demote the mapping. This pmap is locked. The old PDE has
4799 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
4800 * set. Thus, there is no danger of a race with another
4801 * processor changing the setting of PG_A and/or PG_M between
4802 * the read above and the store below.
4804 if (workaround_erratum383)
4805 pmap_update_pde(pmap, va, pde, newpde);
4807 pde_store(pde, newpde);
4810 * Invalidate a stale recursive mapping of the page table page.
4813 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4816 * Demote the PV entry.
4818 if ((oldpde & PG_MANAGED) != 0)
4819 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
4821 atomic_add_long(&pmap_pde_demotions, 1);
4822 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
4828 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
4831 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4837 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
4838 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4839 mpte = pmap_remove_pt_page(pmap, va);
4841 panic("pmap_remove_kernel_pde: Missing pt page.");
4843 mptepa = VM_PAGE_TO_PHYS(mpte);
4844 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
4847 * If this page table page was unmapped by a promotion, then it
4848 * contains valid mappings. Zero it to invalidate those mappings.
4850 if (mpte->valid != 0)
4851 pagezero((void *)PHYS_TO_DMAP(mptepa));
4854 * Demote the mapping.
4856 if (workaround_erratum383)
4857 pmap_update_pde(pmap, va, pde, newpde);
4859 pde_store(pde, newpde);
4862 * Invalidate a stale recursive mapping of the page table page.
4864 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
4868 * pmap_remove_pde: do the things to unmap a superpage in a process
4871 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
4872 struct spglist *free, struct rwlock **lockp)
4874 struct md_page *pvh;
4876 vm_offset_t eva, va;
4878 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4880 PG_G = pmap_global_bit(pmap);
4881 PG_A = pmap_accessed_bit(pmap);
4882 PG_M = pmap_modified_bit(pmap);
4883 PG_RW = pmap_rw_bit(pmap);
4885 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4886 KASSERT((sva & PDRMASK) == 0,
4887 ("pmap_remove_pde: sva is not 2mpage aligned"));
4888 oldpde = pte_load_clear(pdq);
4890 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
4891 if ((oldpde & PG_G) != 0)
4892 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
4893 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
4894 if (oldpde & PG_MANAGED) {
4895 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
4896 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
4897 pmap_pvh_free(pvh, pmap, sva);
4899 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
4900 va < eva; va += PAGE_SIZE, m++) {
4901 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
4904 vm_page_aflag_set(m, PGA_REFERENCED);
4905 if (TAILQ_EMPTY(&m->md.pv_list) &&
4906 TAILQ_EMPTY(&pvh->pv_list))
4907 vm_page_aflag_clear(m, PGA_WRITEABLE);
4908 pmap_delayed_invl_page(m);
4911 if (pmap == kernel_pmap) {
4912 pmap_remove_kernel_pde(pmap, pdq, sva);
4914 mpte = pmap_remove_pt_page(pmap, sva);
4916 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
4917 ("pmap_remove_pde: pte page not promoted"));
4918 pmap_resident_count_dec(pmap, 1);
4919 KASSERT(mpte->wire_count == NPTEPG,
4920 ("pmap_remove_pde: pte page wire count error"));
4921 mpte->wire_count = 0;
4922 pmap_add_delayed_free_list(mpte, free, FALSE);
4925 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
4929 * pmap_remove_pte: do the things to unmap a page in a process
4932 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
4933 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
4935 struct md_page *pvh;
4936 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
4939 PG_A = pmap_accessed_bit(pmap);
4940 PG_M = pmap_modified_bit(pmap);
4941 PG_RW = pmap_rw_bit(pmap);
4943 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4944 oldpte = pte_load_clear(ptq);
4946 pmap->pm_stats.wired_count -= 1;
4947 pmap_resident_count_dec(pmap, 1);
4948 if (oldpte & PG_MANAGED) {
4949 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
4950 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4953 vm_page_aflag_set(m, PGA_REFERENCED);
4954 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4955 pmap_pvh_free(&m->md, pmap, va);
4956 if (TAILQ_EMPTY(&m->md.pv_list) &&
4957 (m->flags & PG_FICTITIOUS) == 0) {
4958 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4959 if (TAILQ_EMPTY(&pvh->pv_list))
4960 vm_page_aflag_clear(m, PGA_WRITEABLE);
4962 pmap_delayed_invl_page(m);
4964 return (pmap_unuse_pt(pmap, va, ptepde, free));
4968 * Remove a single page from a process address space
4971 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
4972 struct spglist *free)
4974 struct rwlock *lock;
4975 pt_entry_t *pte, PG_V;
4977 PG_V = pmap_valid_bit(pmap);
4978 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4979 if ((*pde & PG_V) == 0)
4981 pte = pmap_pde_to_pte(pde, va);
4982 if ((*pte & PG_V) == 0)
4985 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
4988 pmap_invalidate_page(pmap, va);
4992 * Removes the specified range of addresses from the page table page.
4995 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
4996 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
4998 pt_entry_t PG_G, *pte;
5002 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5003 PG_G = pmap_global_bit(pmap);
5006 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5010 pmap_invalidate_range(pmap, va, sva);
5015 if ((*pte & PG_G) == 0)
5019 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5025 pmap_invalidate_range(pmap, va, sva);
5030 * Remove the given range of addresses from the specified map.
5032 * It is assumed that the start and end are properly
5033 * rounded to the page size.
5036 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5038 struct rwlock *lock;
5039 vm_offset_t va_next;
5040 pml4_entry_t *pml4e;
5042 pd_entry_t ptpaddr, *pde;
5043 pt_entry_t PG_G, PG_V;
5044 struct spglist free;
5047 PG_G = pmap_global_bit(pmap);
5048 PG_V = pmap_valid_bit(pmap);
5051 * Perform an unsynchronized read. This is, however, safe.
5053 if (pmap->pm_stats.resident_count == 0)
5059 pmap_delayed_invl_start();
5061 pmap_pkru_on_remove(pmap, sva, eva);
5064 * special handling of removing one page. a very
5065 * common operation and easy to short circuit some
5068 if (sva + PAGE_SIZE == eva) {
5069 pde = pmap_pde(pmap, sva);
5070 if (pde && (*pde & PG_PS) == 0) {
5071 pmap_remove_page(pmap, sva, pde, &free);
5077 for (; sva < eva; sva = va_next) {
5079 if (pmap->pm_stats.resident_count == 0)
5082 pml4e = pmap_pml4e(pmap, sva);
5083 if ((*pml4e & PG_V) == 0) {
5084 va_next = (sva + NBPML4) & ~PML4MASK;
5090 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5091 if ((*pdpe & PG_V) == 0) {
5092 va_next = (sva + NBPDP) & ~PDPMASK;
5099 * Calculate index for next page table.
5101 va_next = (sva + NBPDR) & ~PDRMASK;
5105 pde = pmap_pdpe_to_pde(pdpe, sva);
5109 * Weed out invalid mappings.
5115 * Check for large page.
5117 if ((ptpaddr & PG_PS) != 0) {
5119 * Are we removing the entire large page? If not,
5120 * demote the mapping and fall through.
5122 if (sva + NBPDR == va_next && eva >= va_next) {
5124 * The TLB entry for a PG_G mapping is
5125 * invalidated by pmap_remove_pde().
5127 if ((ptpaddr & PG_G) == 0)
5129 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5131 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5133 /* The large page mapping was destroyed. */
5140 * Limit our scan to either the end of the va represented
5141 * by the current page table page, or to the end of the
5142 * range being removed.
5147 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5154 pmap_invalidate_all(pmap);
5156 pmap_delayed_invl_finish();
5157 vm_page_free_pages_toq(&free, true);
5161 * Routine: pmap_remove_all
5163 * Removes this physical page from
5164 * all physical maps in which it resides.
5165 * Reflects back modify bits to the pager.
5168 * Original versions of this routine were very
5169 * inefficient because they iteratively called
5170 * pmap_remove (slow...)
5174 pmap_remove_all(vm_page_t m)
5176 struct md_page *pvh;
5179 struct rwlock *lock;
5180 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5183 struct spglist free;
5184 int pvh_gen, md_gen;
5186 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5187 ("pmap_remove_all: page %p is not managed", m));
5189 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5190 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5191 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5194 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5196 if (!PMAP_TRYLOCK(pmap)) {
5197 pvh_gen = pvh->pv_gen;
5201 if (pvh_gen != pvh->pv_gen) {
5208 pde = pmap_pde(pmap, va);
5209 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5212 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5214 if (!PMAP_TRYLOCK(pmap)) {
5215 pvh_gen = pvh->pv_gen;
5216 md_gen = m->md.pv_gen;
5220 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5226 PG_A = pmap_accessed_bit(pmap);
5227 PG_M = pmap_modified_bit(pmap);
5228 PG_RW = pmap_rw_bit(pmap);
5229 pmap_resident_count_dec(pmap, 1);
5230 pde = pmap_pde(pmap, pv->pv_va);
5231 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5232 " a 2mpage in page %p's pv list", m));
5233 pte = pmap_pde_to_pte(pde, pv->pv_va);
5234 tpte = pte_load_clear(pte);
5236 pmap->pm_stats.wired_count--;
5238 vm_page_aflag_set(m, PGA_REFERENCED);
5241 * Update the vm_page_t clean and reference bits.
5243 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5245 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5246 pmap_invalidate_page(pmap, pv->pv_va);
5247 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5249 free_pv_entry(pmap, pv);
5252 vm_page_aflag_clear(m, PGA_WRITEABLE);
5254 pmap_delayed_invl_wait(m);
5255 vm_page_free_pages_toq(&free, true);
5259 * pmap_protect_pde: do the things to protect a 2mpage in a process
5262 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5264 pd_entry_t newpde, oldpde;
5265 vm_offset_t eva, va;
5267 boolean_t anychanged;
5268 pt_entry_t PG_G, PG_M, PG_RW;
5270 PG_G = pmap_global_bit(pmap);
5271 PG_M = pmap_modified_bit(pmap);
5272 PG_RW = pmap_rw_bit(pmap);
5274 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5275 KASSERT((sva & PDRMASK) == 0,
5276 ("pmap_protect_pde: sva is not 2mpage aligned"));
5279 oldpde = newpde = *pde;
5280 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5281 (PG_MANAGED | PG_M | PG_RW)) {
5283 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5284 va < eva; va += PAGE_SIZE, m++)
5287 if ((prot & VM_PROT_WRITE) == 0)
5288 newpde &= ~(PG_RW | PG_M);
5289 if ((prot & VM_PROT_EXECUTE) == 0)
5291 if (newpde != oldpde) {
5293 * As an optimization to future operations on this PDE, clear
5294 * PG_PROMOTED. The impending invalidation will remove any
5295 * lingering 4KB page mappings from the TLB.
5297 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5299 if ((oldpde & PG_G) != 0)
5300 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5304 return (anychanged);
5308 * Set the physical protection on the
5309 * specified range of this map as requested.
5312 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5314 vm_offset_t va_next;
5315 pml4_entry_t *pml4e;
5317 pd_entry_t ptpaddr, *pde;
5318 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5319 boolean_t anychanged;
5321 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5322 if (prot == VM_PROT_NONE) {
5323 pmap_remove(pmap, sva, eva);
5327 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5328 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5331 PG_G = pmap_global_bit(pmap);
5332 PG_M = pmap_modified_bit(pmap);
5333 PG_V = pmap_valid_bit(pmap);
5334 PG_RW = pmap_rw_bit(pmap);
5338 * Although this function delays and batches the invalidation
5339 * of stale TLB entries, it does not need to call
5340 * pmap_delayed_invl_start() and
5341 * pmap_delayed_invl_finish(), because it does not
5342 * ordinarily destroy mappings. Stale TLB entries from
5343 * protection-only changes need only be invalidated before the
5344 * pmap lock is released, because protection-only changes do
5345 * not destroy PV entries. Even operations that iterate over
5346 * a physical page's PV list of mappings, like
5347 * pmap_remove_write(), acquire the pmap lock for each
5348 * mapping. Consequently, for protection-only changes, the
5349 * pmap lock suffices to synchronize both page table and TLB
5352 * This function only destroys a mapping if pmap_demote_pde()
5353 * fails. In that case, stale TLB entries are immediately
5358 for (; sva < eva; sva = va_next) {
5360 pml4e = pmap_pml4e(pmap, sva);
5361 if ((*pml4e & PG_V) == 0) {
5362 va_next = (sva + NBPML4) & ~PML4MASK;
5368 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5369 if ((*pdpe & PG_V) == 0) {
5370 va_next = (sva + NBPDP) & ~PDPMASK;
5376 va_next = (sva + NBPDR) & ~PDRMASK;
5380 pde = pmap_pdpe_to_pde(pdpe, sva);
5384 * Weed out invalid mappings.
5390 * Check for large page.
5392 if ((ptpaddr & PG_PS) != 0) {
5394 * Are we protecting the entire large page? If not,
5395 * demote the mapping and fall through.
5397 if (sva + NBPDR == va_next && eva >= va_next) {
5399 * The TLB entry for a PG_G mapping is
5400 * invalidated by pmap_protect_pde().
5402 if (pmap_protect_pde(pmap, pde, sva, prot))
5405 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5407 * The large page mapping was destroyed.
5416 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5418 pt_entry_t obits, pbits;
5422 obits = pbits = *pte;
5423 if ((pbits & PG_V) == 0)
5426 if ((prot & VM_PROT_WRITE) == 0) {
5427 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5428 (PG_MANAGED | PG_M | PG_RW)) {
5429 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5432 pbits &= ~(PG_RW | PG_M);
5434 if ((prot & VM_PROT_EXECUTE) == 0)
5437 if (pbits != obits) {
5438 if (!atomic_cmpset_long(pte, obits, pbits))
5441 pmap_invalidate_page(pmap, sva);
5448 pmap_invalidate_all(pmap);
5452 #if VM_NRESERVLEVEL > 0
5454 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5457 if (pmap->pm_type != PT_EPT)
5459 return ((pde & EPT_PG_EXECUTE) != 0);
5463 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5464 * single page table page (PTP) to a single 2MB page mapping. For promotion
5465 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5466 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5467 * identical characteristics.
5470 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5471 struct rwlock **lockp)
5474 pt_entry_t *firstpte, oldpte, pa, *pte;
5475 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5479 PG_A = pmap_accessed_bit(pmap);
5480 PG_G = pmap_global_bit(pmap);
5481 PG_M = pmap_modified_bit(pmap);
5482 PG_V = pmap_valid_bit(pmap);
5483 PG_RW = pmap_rw_bit(pmap);
5484 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5485 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5487 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5490 * Examine the first PTE in the specified PTP. Abort if this PTE is
5491 * either invalid, unused, or does not map the first 4KB physical page
5492 * within a 2MB page.
5494 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5497 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5498 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5500 atomic_add_long(&pmap_pde_p_failures, 1);
5501 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5502 " in pmap %p", va, pmap);
5505 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5507 * When PG_M is already clear, PG_RW can be cleared without
5508 * a TLB invalidation.
5510 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5516 * Examine each of the other PTEs in the specified PTP. Abort if this
5517 * PTE maps an unexpected 4KB physical page or does not have identical
5518 * characteristics to the first PTE.
5520 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5521 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5524 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5525 atomic_add_long(&pmap_pde_p_failures, 1);
5526 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5527 " in pmap %p", va, pmap);
5530 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5532 * When PG_M is already clear, PG_RW can be cleared
5533 * without a TLB invalidation.
5535 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5538 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5539 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5540 (va & ~PDRMASK), pmap);
5542 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5543 atomic_add_long(&pmap_pde_p_failures, 1);
5544 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5545 " in pmap %p", va, pmap);
5552 * Save the page table page in its current state until the PDE
5553 * mapping the superpage is demoted by pmap_demote_pde() or
5554 * destroyed by pmap_remove_pde().
5556 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5557 KASSERT(mpte >= vm_page_array &&
5558 mpte < &vm_page_array[vm_page_array_size],
5559 ("pmap_promote_pde: page table page is out of range"));
5560 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5561 ("pmap_promote_pde: page table page's pindex is wrong"));
5562 if (pmap_insert_pt_page(pmap, mpte, true)) {
5563 atomic_add_long(&pmap_pde_p_failures, 1);
5565 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5571 * Promote the pv entries.
5573 if ((newpde & PG_MANAGED) != 0)
5574 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5577 * Propagate the PAT index to its proper position.
5579 newpde = pmap_swap_pat(pmap, newpde);
5582 * Map the superpage.
5584 if (workaround_erratum383)
5585 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5587 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5589 atomic_add_long(&pmap_pde_promotions, 1);
5590 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5591 " in pmap %p", va, pmap);
5593 #endif /* VM_NRESERVLEVEL > 0 */
5596 * Insert the given physical page (p) at
5597 * the specified virtual address (v) in the
5598 * target physical map with the protection requested.
5600 * If specified, the page will be wired down, meaning
5601 * that the related pte can not be reclaimed.
5603 * NB: This is the only routine which MAY NOT lazy-evaluate
5604 * or lose information. That is, this routine must actually
5605 * insert this page into the given map NOW.
5607 * When destroying both a page table and PV entry, this function
5608 * performs the TLB invalidation before releasing the PV list
5609 * lock, so we do not need pmap_delayed_invl_page() calls here.
5612 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5613 u_int flags, int8_t psind)
5615 struct rwlock *lock;
5617 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5618 pt_entry_t newpte, origpte;
5625 PG_A = pmap_accessed_bit(pmap);
5626 PG_G = pmap_global_bit(pmap);
5627 PG_M = pmap_modified_bit(pmap);
5628 PG_V = pmap_valid_bit(pmap);
5629 PG_RW = pmap_rw_bit(pmap);
5631 va = trunc_page(va);
5632 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5633 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5634 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5636 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5637 va >= kmi.clean_eva,
5638 ("pmap_enter: managed mapping within the clean submap"));
5639 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
5640 VM_OBJECT_ASSERT_LOCKED(m->object);
5641 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5642 ("pmap_enter: flags %u has reserved bits set", flags));
5643 pa = VM_PAGE_TO_PHYS(m);
5644 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5645 if ((flags & VM_PROT_WRITE) != 0)
5647 if ((prot & VM_PROT_WRITE) != 0)
5649 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
5650 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
5651 if ((prot & VM_PROT_EXECUTE) == 0)
5653 if ((flags & PMAP_ENTER_WIRED) != 0)
5655 if (va < VM_MAXUSER_ADDRESS)
5657 if (pmap == kernel_pmap)
5659 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
5662 * Set modified bit gratuitously for writeable mappings if
5663 * the page is unmanaged. We do not want to take a fault
5664 * to do the dirty bit accounting for these mappings.
5666 if ((m->oflags & VPO_UNMANAGED) != 0) {
5667 if ((newpte & PG_RW) != 0)
5670 newpte |= PG_MANAGED;
5675 /* Assert the required virtual and physical alignment. */
5676 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
5677 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
5678 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
5684 * In the case that a page table page is not
5685 * resident, we are creating it here.
5688 pde = pmap_pde(pmap, va);
5689 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
5690 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
5691 pte = pmap_pde_to_pte(pde, va);
5692 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
5693 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5696 } else if (va < VM_MAXUSER_ADDRESS) {
5698 * Here if the pte page isn't mapped, or if it has been
5701 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
5702 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
5703 nosleep ? NULL : &lock);
5704 if (mpte == NULL && nosleep) {
5705 rv = KERN_RESOURCE_SHORTAGE;
5710 panic("pmap_enter: invalid page directory va=%#lx", va);
5714 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
5715 newpte |= pmap_pkru_get(pmap, va);
5718 * Is the specified virtual address already mapped?
5720 if ((origpte & PG_V) != 0) {
5722 * Wiring change, just update stats. We don't worry about
5723 * wiring PT pages as they remain resident as long as there
5724 * are valid mappings in them. Hence, if a user page is wired,
5725 * the PT page will be also.
5727 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
5728 pmap->pm_stats.wired_count++;
5729 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
5730 pmap->pm_stats.wired_count--;
5733 * Remove the extra PT page reference.
5737 KASSERT(mpte->wire_count > 0,
5738 ("pmap_enter: missing reference to page table page,"
5743 * Has the physical page changed?
5745 opa = origpte & PG_FRAME;
5748 * No, might be a protection or wiring change.
5750 if ((origpte & PG_MANAGED) != 0 &&
5751 (newpte & PG_RW) != 0)
5752 vm_page_aflag_set(m, PGA_WRITEABLE);
5753 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
5759 * The physical page has changed. Temporarily invalidate
5760 * the mapping. This ensures that all threads sharing the
5761 * pmap keep a consistent view of the mapping, which is
5762 * necessary for the correct handling of COW faults. It
5763 * also permits reuse of the old mapping's PV entry,
5764 * avoiding an allocation.
5766 * For consistency, handle unmanaged mappings the same way.
5768 origpte = pte_load_clear(pte);
5769 KASSERT((origpte & PG_FRAME) == opa,
5770 ("pmap_enter: unexpected pa update for %#lx", va));
5771 if ((origpte & PG_MANAGED) != 0) {
5772 om = PHYS_TO_VM_PAGE(opa);
5775 * The pmap lock is sufficient to synchronize with
5776 * concurrent calls to pmap_page_test_mappings() and
5777 * pmap_ts_referenced().
5779 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5781 if ((origpte & PG_A) != 0)
5782 vm_page_aflag_set(om, PGA_REFERENCED);
5783 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
5784 pv = pmap_pvh_remove(&om->md, pmap, va);
5786 ("pmap_enter: no PV entry for %#lx", va));
5787 if ((newpte & PG_MANAGED) == 0)
5788 free_pv_entry(pmap, pv);
5789 if ((om->aflags & PGA_WRITEABLE) != 0 &&
5790 TAILQ_EMPTY(&om->md.pv_list) &&
5791 ((om->flags & PG_FICTITIOUS) != 0 ||
5792 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
5793 vm_page_aflag_clear(om, PGA_WRITEABLE);
5795 if ((origpte & PG_A) != 0)
5796 pmap_invalidate_page(pmap, va);
5800 * Increment the counters.
5802 if ((newpte & PG_W) != 0)
5803 pmap->pm_stats.wired_count++;
5804 pmap_resident_count_inc(pmap, 1);
5808 * Enter on the PV list if part of our managed memory.
5810 if ((newpte & PG_MANAGED) != 0) {
5812 pv = get_pv_entry(pmap, &lock);
5815 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
5816 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5818 if ((newpte & PG_RW) != 0)
5819 vm_page_aflag_set(m, PGA_WRITEABLE);
5825 if ((origpte & PG_V) != 0) {
5827 origpte = pte_load_store(pte, newpte);
5828 KASSERT((origpte & PG_FRAME) == pa,
5829 ("pmap_enter: unexpected pa update for %#lx", va));
5830 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
5832 if ((origpte & PG_MANAGED) != 0)
5836 * Although the PTE may still have PG_RW set, TLB
5837 * invalidation may nonetheless be required because
5838 * the PTE no longer has PG_M set.
5840 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
5842 * This PTE change does not require TLB invalidation.
5846 if ((origpte & PG_A) != 0)
5847 pmap_invalidate_page(pmap, va);
5849 pte_store(pte, newpte);
5853 #if VM_NRESERVLEVEL > 0
5855 * If both the page table page and the reservation are fully
5856 * populated, then attempt promotion.
5858 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
5859 pmap_ps_enabled(pmap) &&
5860 (m->flags & PG_FICTITIOUS) == 0 &&
5861 vm_reserv_level_iffullpop(m) == 0)
5862 pmap_promote_pde(pmap, pde, va, &lock);
5874 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
5875 * if successful. Returns false if (1) a page table page cannot be allocated
5876 * without sleeping, (2) a mapping already exists at the specified virtual
5877 * address, or (3) a PV entry cannot be allocated without reclaiming another
5881 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5882 struct rwlock **lockp)
5887 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5888 PG_V = pmap_valid_bit(pmap);
5889 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
5891 if ((m->oflags & VPO_UNMANAGED) == 0)
5892 newpde |= PG_MANAGED;
5893 if ((prot & VM_PROT_EXECUTE) == 0)
5895 if (va < VM_MAXUSER_ADDRESS)
5897 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
5898 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
5903 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
5904 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
5905 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
5906 * a mapping already exists at the specified virtual address. Returns
5907 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
5908 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
5909 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
5911 * The parameter "m" is only used when creating a managed, writeable mapping.
5914 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
5915 vm_page_t m, struct rwlock **lockp)
5917 struct spglist free;
5918 pd_entry_t oldpde, *pde;
5919 pt_entry_t PG_G, PG_RW, PG_V;
5922 PG_G = pmap_global_bit(pmap);
5923 PG_RW = pmap_rw_bit(pmap);
5924 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
5925 ("pmap_enter_pde: newpde is missing PG_M"));
5926 PG_V = pmap_valid_bit(pmap);
5927 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5929 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5931 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
5932 " in pmap %p", va, pmap);
5933 return (KERN_FAILURE);
5935 if ((pdpg = pmap_allocpde(pmap, va, (flags & PMAP_ENTER_NOSLEEP) != 0 ?
5936 NULL : lockp)) == NULL) {
5937 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5938 " in pmap %p", va, pmap);
5939 return (KERN_RESOURCE_SHORTAGE);
5943 * If pkru is not same for the whole pde range, return failure
5944 * and let vm_fault() cope. Check after pde allocation, since
5947 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
5949 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
5950 pmap_invalidate_page(pmap, va);
5951 vm_page_free_pages_toq(&free, true);
5953 return (KERN_FAILURE);
5955 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
5956 newpde &= ~X86_PG_PKU_MASK;
5957 newpde |= pmap_pkru_get(pmap, va);
5960 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
5961 pde = &pde[pmap_pde_index(va)];
5963 if ((oldpde & PG_V) != 0) {
5964 KASSERT(pdpg->wire_count > 1,
5965 ("pmap_enter_pde: pdpg's wire count is too low"));
5966 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
5968 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
5969 " in pmap %p", va, pmap);
5970 return (KERN_FAILURE);
5972 /* Break the existing mapping(s). */
5974 if ((oldpde & PG_PS) != 0) {
5976 * The reference to the PD page that was acquired by
5977 * pmap_allocpde() ensures that it won't be freed.
5978 * However, if the PDE resulted from a promotion, then
5979 * a reserved PT page could be freed.
5981 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
5982 if ((oldpde & PG_G) == 0)
5983 pmap_invalidate_pde_page(pmap, va, oldpde);
5985 pmap_delayed_invl_start();
5986 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
5988 pmap_invalidate_all(pmap);
5989 pmap_delayed_invl_finish();
5991 vm_page_free_pages_toq(&free, true);
5992 if (va >= VM_MAXUSER_ADDRESS) {
5994 * Both pmap_remove_pde() and pmap_remove_ptes() will
5995 * leave the kernel page table page zero filled.
5997 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5998 if (pmap_insert_pt_page(pmap, mt, false))
5999 panic("pmap_enter_pde: trie insert failed");
6001 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6004 if ((newpde & PG_MANAGED) != 0) {
6006 * Abort this mapping if its PV entry could not be created.
6008 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6010 if (pmap_unwire_ptp(pmap, va, pdpg, &free)) {
6012 * Although "va" is not mapped, paging-
6013 * structure caches could nonetheless have
6014 * entries that refer to the freed page table
6015 * pages. Invalidate those entries.
6017 pmap_invalidate_page(pmap, va);
6018 vm_page_free_pages_toq(&free, true);
6020 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6021 " in pmap %p", va, pmap);
6022 return (KERN_RESOURCE_SHORTAGE);
6024 if ((newpde & PG_RW) != 0) {
6025 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6026 vm_page_aflag_set(mt, PGA_WRITEABLE);
6031 * Increment counters.
6033 if ((newpde & PG_W) != 0)
6034 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6035 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6038 * Map the superpage. (This is not a promoted mapping; there will not
6039 * be any lingering 4KB page mappings in the TLB.)
6041 pde_store(pde, newpde);
6043 atomic_add_long(&pmap_pde_mappings, 1);
6044 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
6045 " in pmap %p", va, pmap);
6046 return (KERN_SUCCESS);
6050 * Maps a sequence of resident pages belonging to the same object.
6051 * The sequence begins with the given page m_start. This page is
6052 * mapped at the given virtual address start. Each subsequent page is
6053 * mapped at a virtual address that is offset from start by the same
6054 * amount as the page is offset from m_start within the object. The
6055 * last page in the sequence is the page with the largest offset from
6056 * m_start that can be mapped at a virtual address less than the given
6057 * virtual address end. Not every virtual page between start and end
6058 * is mapped; only those for which a resident page exists with the
6059 * corresponding offset from m_start are mapped.
6062 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6063 vm_page_t m_start, vm_prot_t prot)
6065 struct rwlock *lock;
6068 vm_pindex_t diff, psize;
6070 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6072 psize = atop(end - start);
6077 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6078 va = start + ptoa(diff);
6079 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6080 m->psind == 1 && pmap_ps_enabled(pmap) &&
6081 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6082 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6083 m = &m[NBPDR / PAGE_SIZE - 1];
6085 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6087 m = TAILQ_NEXT(m, listq);
6095 * this code makes some *MAJOR* assumptions:
6096 * 1. Current pmap & pmap exists.
6099 * 4. No page table pages.
6100 * but is *MUCH* faster than pmap_enter...
6104 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6106 struct rwlock *lock;
6110 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6117 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6118 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6120 struct spglist free;
6121 pt_entry_t newpte, *pte, PG_V;
6123 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6124 (m->oflags & VPO_UNMANAGED) != 0,
6125 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6126 PG_V = pmap_valid_bit(pmap);
6127 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6130 * In the case that a page table page is not
6131 * resident, we are creating it here.
6133 if (va < VM_MAXUSER_ADDRESS) {
6134 vm_pindex_t ptepindex;
6138 * Calculate pagetable page index
6140 ptepindex = pmap_pde_pindex(va);
6141 if (mpte && (mpte->pindex == ptepindex)) {
6145 * Get the page directory entry
6147 ptepa = pmap_pde(pmap, va);
6150 * If the page table page is mapped, we just increment
6151 * the hold count, and activate it. Otherwise, we
6152 * attempt to allocate a page table page. If this
6153 * attempt fails, we don't retry. Instead, we give up.
6155 if (ptepa && (*ptepa & PG_V) != 0) {
6158 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6162 * Pass NULL instead of the PV list lock
6163 * pointer, because we don't intend to sleep.
6165 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6170 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6171 pte = &pte[pmap_pte_index(va)];
6185 * Enter on the PV list if part of our managed memory.
6187 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6188 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6191 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
6193 * Although "va" is not mapped, paging-
6194 * structure caches could nonetheless have
6195 * entries that refer to the freed page table
6196 * pages. Invalidate those entries.
6198 pmap_invalidate_page(pmap, va);
6199 vm_page_free_pages_toq(&free, true);
6207 * Increment counters
6209 pmap_resident_count_inc(pmap, 1);
6211 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6212 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6213 if ((m->oflags & VPO_UNMANAGED) == 0)
6214 newpte |= PG_MANAGED;
6215 if ((prot & VM_PROT_EXECUTE) == 0)
6217 if (va < VM_MAXUSER_ADDRESS)
6218 newpte |= PG_U | pmap_pkru_get(pmap, va);
6219 pte_store(pte, newpte);
6224 * Make a temporary mapping for a physical address. This is only intended
6225 * to be used for panic dumps.
6228 pmap_kenter_temporary(vm_paddr_t pa, int i)
6232 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6233 pmap_kenter(va, pa);
6235 return ((void *)crashdumpmap);
6239 * This code maps large physical mmap regions into the
6240 * processor address space. Note that some shortcuts
6241 * are taken, but the code works.
6244 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6245 vm_pindex_t pindex, vm_size_t size)
6248 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6249 vm_paddr_t pa, ptepa;
6253 PG_A = pmap_accessed_bit(pmap);
6254 PG_M = pmap_modified_bit(pmap);
6255 PG_V = pmap_valid_bit(pmap);
6256 PG_RW = pmap_rw_bit(pmap);
6258 VM_OBJECT_ASSERT_WLOCKED(object);
6259 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6260 ("pmap_object_init_pt: non-device object"));
6261 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6262 if (!pmap_ps_enabled(pmap))
6264 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6266 p = vm_page_lookup(object, pindex);
6267 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6268 ("pmap_object_init_pt: invalid page %p", p));
6269 pat_mode = p->md.pat_mode;
6272 * Abort the mapping if the first page is not physically
6273 * aligned to a 2MB page boundary.
6275 ptepa = VM_PAGE_TO_PHYS(p);
6276 if (ptepa & (NBPDR - 1))
6280 * Skip the first page. Abort the mapping if the rest of
6281 * the pages are not physically contiguous or have differing
6282 * memory attributes.
6284 p = TAILQ_NEXT(p, listq);
6285 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6287 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6288 ("pmap_object_init_pt: invalid page %p", p));
6289 if (pa != VM_PAGE_TO_PHYS(p) ||
6290 pat_mode != p->md.pat_mode)
6292 p = TAILQ_NEXT(p, listq);
6296 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6297 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6298 * will not affect the termination of this loop.
6301 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6302 pa < ptepa + size; pa += NBPDR) {
6303 pdpg = pmap_allocpde(pmap, addr, NULL);
6306 * The creation of mappings below is only an
6307 * optimization. If a page directory page
6308 * cannot be allocated without blocking,
6309 * continue on to the next mapping rather than
6315 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
6316 pde = &pde[pmap_pde_index(addr)];
6317 if ((*pde & PG_V) == 0) {
6318 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6319 PG_U | PG_RW | PG_V);
6320 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6321 atomic_add_long(&pmap_pde_mappings, 1);
6323 /* Continue on if the PDE is already valid. */
6325 KASSERT(pdpg->wire_count > 0,
6326 ("pmap_object_init_pt: missing reference "
6327 "to page directory page, va: 0x%lx", addr));
6336 * Clear the wired attribute from the mappings for the specified range of
6337 * addresses in the given pmap. Every valid mapping within that range
6338 * must have the wired attribute set. In contrast, invalid mappings
6339 * cannot have the wired attribute set, so they are ignored.
6341 * The wired attribute of the page table entry is not a hardware
6342 * feature, so there is no need to invalidate any TLB entries.
6343 * Since pmap_demote_pde() for the wired entry must never fail,
6344 * pmap_delayed_invl_start()/finish() calls around the
6345 * function are not needed.
6348 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6350 vm_offset_t va_next;
6351 pml4_entry_t *pml4e;
6354 pt_entry_t *pte, PG_V;
6356 PG_V = pmap_valid_bit(pmap);
6358 for (; sva < eva; sva = va_next) {
6359 pml4e = pmap_pml4e(pmap, sva);
6360 if ((*pml4e & PG_V) == 0) {
6361 va_next = (sva + NBPML4) & ~PML4MASK;
6366 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6367 if ((*pdpe & PG_V) == 0) {
6368 va_next = (sva + NBPDP) & ~PDPMASK;
6373 va_next = (sva + NBPDR) & ~PDRMASK;
6376 pde = pmap_pdpe_to_pde(pdpe, sva);
6377 if ((*pde & PG_V) == 0)
6379 if ((*pde & PG_PS) != 0) {
6380 if ((*pde & PG_W) == 0)
6381 panic("pmap_unwire: pde %#jx is missing PG_W",
6385 * Are we unwiring the entire large page? If not,
6386 * demote the mapping and fall through.
6388 if (sva + NBPDR == va_next && eva >= va_next) {
6389 atomic_clear_long(pde, PG_W);
6390 pmap->pm_stats.wired_count -= NBPDR /
6393 } else if (!pmap_demote_pde(pmap, pde, sva))
6394 panic("pmap_unwire: demotion failed");
6398 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6400 if ((*pte & PG_V) == 0)
6402 if ((*pte & PG_W) == 0)
6403 panic("pmap_unwire: pte %#jx is missing PG_W",
6407 * PG_W must be cleared atomically. Although the pmap
6408 * lock synchronizes access to PG_W, another processor
6409 * could be setting PG_M and/or PG_A concurrently.
6411 atomic_clear_long(pte, PG_W);
6412 pmap->pm_stats.wired_count--;
6419 * Copy the range specified by src_addr/len
6420 * from the source map to the range dst_addr/len
6421 * in the destination map.
6423 * This routine is only advisory and need not do anything.
6427 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6428 vm_offset_t src_addr)
6430 struct rwlock *lock;
6431 struct spglist free;
6433 vm_offset_t end_addr = src_addr + len;
6434 vm_offset_t va_next;
6435 vm_page_t dst_pdpg, dstmpte, srcmpte;
6436 pt_entry_t PG_A, PG_M, PG_V;
6438 if (dst_addr != src_addr)
6441 if (dst_pmap->pm_type != src_pmap->pm_type)
6445 * EPT page table entries that require emulation of A/D bits are
6446 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6447 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6448 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6449 * implementations flag an EPT misconfiguration for exec-only
6450 * mappings we skip this function entirely for emulated pmaps.
6452 if (pmap_emulate_ad_bits(dst_pmap))
6456 if (dst_pmap < src_pmap) {
6457 PMAP_LOCK(dst_pmap);
6458 PMAP_LOCK(src_pmap);
6460 PMAP_LOCK(src_pmap);
6461 PMAP_LOCK(dst_pmap);
6464 PG_A = pmap_accessed_bit(dst_pmap);
6465 PG_M = pmap_modified_bit(dst_pmap);
6466 PG_V = pmap_valid_bit(dst_pmap);
6468 for (addr = src_addr; addr < end_addr; addr = va_next) {
6469 pt_entry_t *src_pte, *dst_pte;
6470 pml4_entry_t *pml4e;
6472 pd_entry_t srcptepaddr, *pde;
6474 KASSERT(addr < UPT_MIN_ADDRESS,
6475 ("pmap_copy: invalid to pmap_copy page tables"));
6477 pml4e = pmap_pml4e(src_pmap, addr);
6478 if ((*pml4e & PG_V) == 0) {
6479 va_next = (addr + NBPML4) & ~PML4MASK;
6485 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6486 if ((*pdpe & PG_V) == 0) {
6487 va_next = (addr + NBPDP) & ~PDPMASK;
6493 va_next = (addr + NBPDR) & ~PDRMASK;
6497 pde = pmap_pdpe_to_pde(pdpe, addr);
6499 if (srcptepaddr == 0)
6502 if (srcptepaddr & PG_PS) {
6503 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6505 dst_pdpg = pmap_allocpde(dst_pmap, addr, NULL);
6506 if (dst_pdpg == NULL)
6508 pde = (pd_entry_t *)
6509 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dst_pdpg));
6510 pde = &pde[pmap_pde_index(addr)];
6511 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6512 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6513 PMAP_ENTER_NORECLAIM, &lock))) {
6514 *pde = srcptepaddr & ~PG_W;
6515 pmap_resident_count_inc(dst_pmap, NBPDR / PAGE_SIZE);
6516 atomic_add_long(&pmap_pde_mappings, 1);
6518 dst_pdpg->wire_count--;
6522 srcptepaddr &= PG_FRAME;
6523 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6524 KASSERT(srcmpte->wire_count > 0,
6525 ("pmap_copy: source page table page is unused"));
6527 if (va_next > end_addr)
6530 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6531 src_pte = &src_pte[pmap_pte_index(addr)];
6533 while (addr < va_next) {
6537 * we only virtual copy managed pages
6539 if ((ptetemp & PG_MANAGED) != 0) {
6540 if (dstmpte != NULL &&
6541 dstmpte->pindex == pmap_pde_pindex(addr))
6542 dstmpte->wire_count++;
6543 else if ((dstmpte = pmap_allocpte(dst_pmap,
6544 addr, NULL)) == NULL)
6546 dst_pte = (pt_entry_t *)
6547 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6548 dst_pte = &dst_pte[pmap_pte_index(addr)];
6549 if (*dst_pte == 0 &&
6550 pmap_try_insert_pv_entry(dst_pmap, addr,
6551 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME),
6554 * Clear the wired, modified, and
6555 * accessed (referenced) bits
6558 *dst_pte = ptetemp & ~(PG_W | PG_M |
6560 pmap_resident_count_inc(dst_pmap, 1);
6563 if (pmap_unwire_ptp(dst_pmap, addr,
6566 * Although "addr" is not
6567 * mapped, paging-structure
6568 * caches could nonetheless
6569 * have entries that refer to
6570 * the freed page table pages.
6571 * Invalidate those entries.
6573 pmap_invalidate_page(dst_pmap,
6575 vm_page_free_pages_toq(&free,
6580 if (dstmpte->wire_count >= srcmpte->wire_count)
6590 PMAP_UNLOCK(src_pmap);
6591 PMAP_UNLOCK(dst_pmap);
6595 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6599 if (dst_pmap->pm_type != src_pmap->pm_type ||
6600 dst_pmap->pm_type != PT_X86 ||
6601 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6604 if (dst_pmap < src_pmap) {
6605 PMAP_LOCK(dst_pmap);
6606 PMAP_LOCK(src_pmap);
6608 PMAP_LOCK(src_pmap);
6609 PMAP_LOCK(dst_pmap);
6611 error = pmap_pkru_copy(dst_pmap, src_pmap);
6612 /* Clean up partial copy on failure due to no memory. */
6613 if (error == ENOMEM)
6614 pmap_pkru_deassign_all(dst_pmap);
6615 PMAP_UNLOCK(src_pmap);
6616 PMAP_UNLOCK(dst_pmap);
6617 if (error != ENOMEM)
6625 * Zero the specified hardware page.
6628 pmap_zero_page(vm_page_t m)
6630 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6632 pagezero((void *)va);
6636 * Zero an an area within a single hardware page. off and size must not
6637 * cover an area beyond a single hardware page.
6640 pmap_zero_page_area(vm_page_t m, int off, int size)
6642 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6644 if (off == 0 && size == PAGE_SIZE)
6645 pagezero((void *)va);
6647 bzero((char *)va + off, size);
6651 * Copy 1 specified hardware page to another.
6654 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6656 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6657 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6659 pagecopy((void *)src, (void *)dst);
6662 int unmapped_buf_allowed = 1;
6665 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
6666 vm_offset_t b_offset, int xfersize)
6670 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
6674 while (xfersize > 0) {
6675 a_pg_offset = a_offset & PAGE_MASK;
6676 pages[0] = ma[a_offset >> PAGE_SHIFT];
6677 b_pg_offset = b_offset & PAGE_MASK;
6678 pages[1] = mb[b_offset >> PAGE_SHIFT];
6679 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
6680 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
6681 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
6682 a_cp = (char *)vaddr[0] + a_pg_offset;
6683 b_cp = (char *)vaddr[1] + b_pg_offset;
6684 bcopy(a_cp, b_cp, cnt);
6685 if (__predict_false(mapped))
6686 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
6694 * Returns true if the pmap's pv is one of the first
6695 * 16 pvs linked to from this page. This count may
6696 * be changed upwards or downwards in the future; it
6697 * is only necessary that true be returned for a small
6698 * subset of pmaps for proper page aging.
6701 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
6703 struct md_page *pvh;
6704 struct rwlock *lock;
6709 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6710 ("pmap_page_exists_quick: page %p is not managed", m));
6712 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6714 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6715 if (PV_PMAP(pv) == pmap) {
6723 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
6724 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6725 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6726 if (PV_PMAP(pv) == pmap) {
6740 * pmap_page_wired_mappings:
6742 * Return the number of managed mappings to the given physical page
6746 pmap_page_wired_mappings(vm_page_t m)
6748 struct rwlock *lock;
6749 struct md_page *pvh;
6753 int count, md_gen, pvh_gen;
6755 if ((m->oflags & VPO_UNMANAGED) != 0)
6757 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6761 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
6763 if (!PMAP_TRYLOCK(pmap)) {
6764 md_gen = m->md.pv_gen;
6768 if (md_gen != m->md.pv_gen) {
6773 pte = pmap_pte(pmap, pv->pv_va);
6774 if ((*pte & PG_W) != 0)
6778 if ((m->flags & PG_FICTITIOUS) == 0) {
6779 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
6780 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
6782 if (!PMAP_TRYLOCK(pmap)) {
6783 md_gen = m->md.pv_gen;
6784 pvh_gen = pvh->pv_gen;
6788 if (md_gen != m->md.pv_gen ||
6789 pvh_gen != pvh->pv_gen) {
6794 pte = pmap_pde(pmap, pv->pv_va);
6795 if ((*pte & PG_W) != 0)
6805 * Returns TRUE if the given page is mapped individually or as part of
6806 * a 2mpage. Otherwise, returns FALSE.
6809 pmap_page_is_mapped(vm_page_t m)
6811 struct rwlock *lock;
6814 if ((m->oflags & VPO_UNMANAGED) != 0)
6816 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6818 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
6819 ((m->flags & PG_FICTITIOUS) == 0 &&
6820 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
6826 * Destroy all managed, non-wired mappings in the given user-space
6827 * pmap. This pmap cannot be active on any processor besides the
6830 * This function cannot be applied to the kernel pmap. Moreover, it
6831 * is not intended for general use. It is only to be used during
6832 * process termination. Consequently, it can be implemented in ways
6833 * that make it faster than pmap_remove(). First, it can more quickly
6834 * destroy mappings by iterating over the pmap's collection of PV
6835 * entries, rather than searching the page table. Second, it doesn't
6836 * have to test and clear the page table entries atomically, because
6837 * no processor is currently accessing the user address space. In
6838 * particular, a page table entry's dirty bit won't change state once
6839 * this function starts.
6841 * Although this function destroys all of the pmap's managed,
6842 * non-wired mappings, it can delay and batch the invalidation of TLB
6843 * entries without calling pmap_delayed_invl_start() and
6844 * pmap_delayed_invl_finish(). Because the pmap is not active on
6845 * any other processor, none of these TLB entries will ever be used
6846 * before their eventual invalidation. Consequently, there is no need
6847 * for either pmap_remove_all() or pmap_remove_write() to wait for
6848 * that eventual TLB invalidation.
6851 pmap_remove_pages(pmap_t pmap)
6854 pt_entry_t *pte, tpte;
6855 pt_entry_t PG_M, PG_RW, PG_V;
6856 struct spglist free;
6857 vm_page_t m, mpte, mt;
6859 struct md_page *pvh;
6860 struct pv_chunk *pc, *npc;
6861 struct rwlock *lock;
6863 uint64_t inuse, bitmask;
6864 int allfree, field, freed, idx;
6865 boolean_t superpage;
6869 * Assert that the given pmap is only active on the current
6870 * CPU. Unfortunately, we cannot block another CPU from
6871 * activating the pmap while this function is executing.
6873 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
6876 cpuset_t other_cpus;
6878 other_cpus = all_cpus;
6880 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
6881 CPU_AND(&other_cpus, &pmap->pm_active);
6883 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
6888 PG_M = pmap_modified_bit(pmap);
6889 PG_V = pmap_valid_bit(pmap);
6890 PG_RW = pmap_rw_bit(pmap);
6894 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
6897 for (field = 0; field < _NPCM; field++) {
6898 inuse = ~pc->pc_map[field] & pc_freemask[field];
6899 while (inuse != 0) {
6901 bitmask = 1UL << bit;
6902 idx = field * 64 + bit;
6903 pv = &pc->pc_pventry[idx];
6906 pte = pmap_pdpe(pmap, pv->pv_va);
6908 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
6910 if ((tpte & (PG_PS | PG_V)) == PG_V) {
6913 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
6915 pte = &pte[pmap_pte_index(pv->pv_va)];
6919 * Keep track whether 'tpte' is a
6920 * superpage explicitly instead of
6921 * relying on PG_PS being set.
6923 * This is because PG_PS is numerically
6924 * identical to PG_PTE_PAT and thus a
6925 * regular page could be mistaken for
6931 if ((tpte & PG_V) == 0) {
6932 panic("bad pte va %lx pte %lx",
6937 * We cannot remove wired pages from a process' mapping at this time
6945 pa = tpte & PG_PS_FRAME;
6947 pa = tpte & PG_FRAME;
6949 m = PHYS_TO_VM_PAGE(pa);
6950 KASSERT(m->phys_addr == pa,
6951 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
6952 m, (uintmax_t)m->phys_addr,
6955 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
6956 m < &vm_page_array[vm_page_array_size],
6957 ("pmap_remove_pages: bad tpte %#jx",
6963 * Update the vm_page_t clean/reference bits.
6965 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
6967 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6973 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
6976 pc->pc_map[field] |= bitmask;
6978 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
6979 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
6980 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
6982 if (TAILQ_EMPTY(&pvh->pv_list)) {
6983 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6984 if ((mt->aflags & PGA_WRITEABLE) != 0 &&
6985 TAILQ_EMPTY(&mt->md.pv_list))
6986 vm_page_aflag_clear(mt, PGA_WRITEABLE);
6988 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
6990 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
6991 ("pmap_remove_pages: pte page not promoted"));
6992 pmap_resident_count_dec(pmap, 1);
6993 KASSERT(mpte->wire_count == NPTEPG,
6994 ("pmap_remove_pages: pte page wire count error"));
6995 mpte->wire_count = 0;
6996 pmap_add_delayed_free_list(mpte, &free, FALSE);
6999 pmap_resident_count_dec(pmap, 1);
7000 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7002 if ((m->aflags & PGA_WRITEABLE) != 0 &&
7003 TAILQ_EMPTY(&m->md.pv_list) &&
7004 (m->flags & PG_FICTITIOUS) == 0) {
7005 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7006 if (TAILQ_EMPTY(&pvh->pv_list))
7007 vm_page_aflag_clear(m, PGA_WRITEABLE);
7010 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7014 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7015 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7016 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7018 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7024 pmap_invalidate_all(pmap);
7025 pmap_pkru_deassign_all(pmap);
7027 vm_page_free_pages_toq(&free, true);
7031 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7033 struct rwlock *lock;
7035 struct md_page *pvh;
7036 pt_entry_t *pte, mask;
7037 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7039 int md_gen, pvh_gen;
7043 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7046 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7048 if (!PMAP_TRYLOCK(pmap)) {
7049 md_gen = m->md.pv_gen;
7053 if (md_gen != m->md.pv_gen) {
7058 pte = pmap_pte(pmap, pv->pv_va);
7061 PG_M = pmap_modified_bit(pmap);
7062 PG_RW = pmap_rw_bit(pmap);
7063 mask |= PG_RW | PG_M;
7066 PG_A = pmap_accessed_bit(pmap);
7067 PG_V = pmap_valid_bit(pmap);
7068 mask |= PG_V | PG_A;
7070 rv = (*pte & mask) == mask;
7075 if ((m->flags & PG_FICTITIOUS) == 0) {
7076 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7077 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7079 if (!PMAP_TRYLOCK(pmap)) {
7080 md_gen = m->md.pv_gen;
7081 pvh_gen = pvh->pv_gen;
7085 if (md_gen != m->md.pv_gen ||
7086 pvh_gen != pvh->pv_gen) {
7091 pte = pmap_pde(pmap, pv->pv_va);
7094 PG_M = pmap_modified_bit(pmap);
7095 PG_RW = pmap_rw_bit(pmap);
7096 mask |= PG_RW | PG_M;
7099 PG_A = pmap_accessed_bit(pmap);
7100 PG_V = pmap_valid_bit(pmap);
7101 mask |= PG_V | PG_A;
7103 rv = (*pte & mask) == mask;
7117 * Return whether or not the specified physical page was modified
7118 * in any physical maps.
7121 pmap_is_modified(vm_page_t m)
7124 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7125 ("pmap_is_modified: page %p is not managed", m));
7128 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7129 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
7130 * is clear, no PTEs can have PG_M set.
7132 VM_OBJECT_ASSERT_WLOCKED(m->object);
7133 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7135 return (pmap_page_test_mappings(m, FALSE, TRUE));
7139 * pmap_is_prefaultable:
7141 * Return whether or not the specified virtual address is eligible
7145 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7148 pt_entry_t *pte, PG_V;
7151 PG_V = pmap_valid_bit(pmap);
7154 pde = pmap_pde(pmap, addr);
7155 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7156 pte = pmap_pde_to_pte(pde, addr);
7157 rv = (*pte & PG_V) == 0;
7164 * pmap_is_referenced:
7166 * Return whether or not the specified physical page was referenced
7167 * in any physical maps.
7170 pmap_is_referenced(vm_page_t m)
7173 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7174 ("pmap_is_referenced: page %p is not managed", m));
7175 return (pmap_page_test_mappings(m, TRUE, FALSE));
7179 * Clear the write and modified bits in each of the given page's mappings.
7182 pmap_remove_write(vm_page_t m)
7184 struct md_page *pvh;
7186 struct rwlock *lock;
7187 pv_entry_t next_pv, pv;
7189 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7191 int pvh_gen, md_gen;
7193 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7194 ("pmap_remove_write: page %p is not managed", m));
7197 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
7198 * set by another thread while the object is locked. Thus,
7199 * if PGA_WRITEABLE is clear, no page table entries need updating.
7201 VM_OBJECT_ASSERT_WLOCKED(m->object);
7202 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
7204 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7205 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7206 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7209 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7211 if (!PMAP_TRYLOCK(pmap)) {
7212 pvh_gen = pvh->pv_gen;
7216 if (pvh_gen != pvh->pv_gen) {
7222 PG_RW = pmap_rw_bit(pmap);
7224 pde = pmap_pde(pmap, va);
7225 if ((*pde & PG_RW) != 0)
7226 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7227 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7228 ("inconsistent pv lock %p %p for page %p",
7229 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7232 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7234 if (!PMAP_TRYLOCK(pmap)) {
7235 pvh_gen = pvh->pv_gen;
7236 md_gen = m->md.pv_gen;
7240 if (pvh_gen != pvh->pv_gen ||
7241 md_gen != m->md.pv_gen) {
7247 PG_M = pmap_modified_bit(pmap);
7248 PG_RW = pmap_rw_bit(pmap);
7249 pde = pmap_pde(pmap, pv->pv_va);
7250 KASSERT((*pde & PG_PS) == 0,
7251 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7253 pte = pmap_pde_to_pte(pde, pv->pv_va);
7256 if (oldpte & PG_RW) {
7257 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7260 if ((oldpte & PG_M) != 0)
7262 pmap_invalidate_page(pmap, pv->pv_va);
7267 vm_page_aflag_clear(m, PGA_WRITEABLE);
7268 pmap_delayed_invl_wait(m);
7271 static __inline boolean_t
7272 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7275 if (!pmap_emulate_ad_bits(pmap))
7278 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7281 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7282 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7283 * if the EPT_PG_WRITE bit is set.
7285 if ((pte & EPT_PG_WRITE) != 0)
7289 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7291 if ((pte & EPT_PG_EXECUTE) == 0 ||
7292 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7299 * pmap_ts_referenced:
7301 * Return a count of reference bits for a page, clearing those bits.
7302 * It is not necessary for every reference bit to be cleared, but it
7303 * is necessary that 0 only be returned when there are truly no
7304 * reference bits set.
7306 * As an optimization, update the page's dirty field if a modified bit is
7307 * found while counting reference bits. This opportunistic update can be
7308 * performed at low cost and can eliminate the need for some future calls
7309 * to pmap_is_modified(). However, since this function stops after
7310 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7311 * dirty pages. Those dirty pages will only be detected by a future call
7312 * to pmap_is_modified().
7314 * A DI block is not needed within this function, because
7315 * invalidations are performed before the PV list lock is
7319 pmap_ts_referenced(vm_page_t m)
7321 struct md_page *pvh;
7324 struct rwlock *lock;
7325 pd_entry_t oldpde, *pde;
7326 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7329 int cleared, md_gen, not_cleared, pvh_gen;
7330 struct spglist free;
7333 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7334 ("pmap_ts_referenced: page %p is not managed", m));
7337 pa = VM_PAGE_TO_PHYS(m);
7338 lock = PHYS_TO_PV_LIST_LOCK(pa);
7339 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7343 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7344 goto small_mappings;
7350 if (!PMAP_TRYLOCK(pmap)) {
7351 pvh_gen = pvh->pv_gen;
7355 if (pvh_gen != pvh->pv_gen) {
7360 PG_A = pmap_accessed_bit(pmap);
7361 PG_M = pmap_modified_bit(pmap);
7362 PG_RW = pmap_rw_bit(pmap);
7364 pde = pmap_pde(pmap, pv->pv_va);
7366 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7368 * Although "oldpde" is mapping a 2MB page, because
7369 * this function is called at a 4KB page granularity,
7370 * we only update the 4KB page under test.
7374 if ((oldpde & PG_A) != 0) {
7376 * Since this reference bit is shared by 512 4KB
7377 * pages, it should not be cleared every time it is
7378 * tested. Apply a simple "hash" function on the
7379 * physical page number, the virtual superpage number,
7380 * and the pmap address to select one 4KB page out of
7381 * the 512 on which testing the reference bit will
7382 * result in clearing that reference bit. This
7383 * function is designed to avoid the selection of the
7384 * same 4KB page for every 2MB page mapping.
7386 * On demotion, a mapping that hasn't been referenced
7387 * is simply destroyed. To avoid the possibility of a
7388 * subsequent page fault on a demoted wired mapping,
7389 * always leave its reference bit set. Moreover,
7390 * since the superpage is wired, the current state of
7391 * its reference bit won't affect page replacement.
7393 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7394 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7395 (oldpde & PG_W) == 0) {
7396 if (safe_to_clear_referenced(pmap, oldpde)) {
7397 atomic_clear_long(pde, PG_A);
7398 pmap_invalidate_page(pmap, pv->pv_va);
7400 } else if (pmap_demote_pde_locked(pmap, pde,
7401 pv->pv_va, &lock)) {
7403 * Remove the mapping to a single page
7404 * so that a subsequent access may
7405 * repromote. Since the underlying
7406 * page table page is fully populated,
7407 * this removal never frees a page
7411 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7413 pte = pmap_pde_to_pte(pde, va);
7414 pmap_remove_pte(pmap, pte, va, *pde,
7416 pmap_invalidate_page(pmap, va);
7422 * The superpage mapping was removed
7423 * entirely and therefore 'pv' is no
7431 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7432 ("inconsistent pv lock %p %p for page %p",
7433 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7438 /* Rotate the PV list if it has more than one entry. */
7439 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7440 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7441 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7444 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7446 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7448 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7455 if (!PMAP_TRYLOCK(pmap)) {
7456 pvh_gen = pvh->pv_gen;
7457 md_gen = m->md.pv_gen;
7461 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7466 PG_A = pmap_accessed_bit(pmap);
7467 PG_M = pmap_modified_bit(pmap);
7468 PG_RW = pmap_rw_bit(pmap);
7469 pde = pmap_pde(pmap, pv->pv_va);
7470 KASSERT((*pde & PG_PS) == 0,
7471 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7473 pte = pmap_pde_to_pte(pde, pv->pv_va);
7474 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7476 if ((*pte & PG_A) != 0) {
7477 if (safe_to_clear_referenced(pmap, *pte)) {
7478 atomic_clear_long(pte, PG_A);
7479 pmap_invalidate_page(pmap, pv->pv_va);
7481 } else if ((*pte & PG_W) == 0) {
7483 * Wired pages cannot be paged out so
7484 * doing accessed bit emulation for
7485 * them is wasted effort. We do the
7486 * hard work for unwired pages only.
7488 pmap_remove_pte(pmap, pte, pv->pv_va,
7489 *pde, &free, &lock);
7490 pmap_invalidate_page(pmap, pv->pv_va);
7495 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7496 ("inconsistent pv lock %p %p for page %p",
7497 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7502 /* Rotate the PV list if it has more than one entry. */
7503 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7504 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7505 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7508 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7509 not_cleared < PMAP_TS_REFERENCED_MAX);
7512 vm_page_free_pages_toq(&free, true);
7513 return (cleared + not_cleared);
7517 * Apply the given advice to the specified range of addresses within the
7518 * given pmap. Depending on the advice, clear the referenced and/or
7519 * modified flags in each mapping and set the mapped page's dirty field.
7522 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7524 struct rwlock *lock;
7525 pml4_entry_t *pml4e;
7527 pd_entry_t oldpde, *pde;
7528 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7529 vm_offset_t va, va_next;
7533 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7537 * A/D bit emulation requires an alternate code path when clearing
7538 * the modified and accessed bits below. Since this function is
7539 * advisory in nature we skip it entirely for pmaps that require
7540 * A/D bit emulation.
7542 if (pmap_emulate_ad_bits(pmap))
7545 PG_A = pmap_accessed_bit(pmap);
7546 PG_G = pmap_global_bit(pmap);
7547 PG_M = pmap_modified_bit(pmap);
7548 PG_V = pmap_valid_bit(pmap);
7549 PG_RW = pmap_rw_bit(pmap);
7551 pmap_delayed_invl_start();
7553 for (; sva < eva; sva = va_next) {
7554 pml4e = pmap_pml4e(pmap, sva);
7555 if ((*pml4e & PG_V) == 0) {
7556 va_next = (sva + NBPML4) & ~PML4MASK;
7561 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7562 if ((*pdpe & PG_V) == 0) {
7563 va_next = (sva + NBPDP) & ~PDPMASK;
7568 va_next = (sva + NBPDR) & ~PDRMASK;
7571 pde = pmap_pdpe_to_pde(pdpe, sva);
7573 if ((oldpde & PG_V) == 0)
7575 else if ((oldpde & PG_PS) != 0) {
7576 if ((oldpde & PG_MANAGED) == 0)
7579 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7584 * The large page mapping was destroyed.
7590 * Unless the page mappings are wired, remove the
7591 * mapping to a single page so that a subsequent
7592 * access may repromote. Choosing the last page
7593 * within the address range [sva, min(va_next, eva))
7594 * generally results in more repromotions. Since the
7595 * underlying page table page is fully populated, this
7596 * removal never frees a page table page.
7598 if ((oldpde & PG_W) == 0) {
7604 ("pmap_advise: no address gap"));
7605 pte = pmap_pde_to_pte(pde, va);
7606 KASSERT((*pte & PG_V) != 0,
7607 ("pmap_advise: invalid PTE"));
7608 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7618 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7620 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7622 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7623 if (advice == MADV_DONTNEED) {
7625 * Future calls to pmap_is_modified()
7626 * can be avoided by making the page
7629 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7632 atomic_clear_long(pte, PG_M | PG_A);
7633 } else if ((*pte & PG_A) != 0)
7634 atomic_clear_long(pte, PG_A);
7638 if ((*pte & PG_G) != 0) {
7645 if (va != va_next) {
7646 pmap_invalidate_range(pmap, va, sva);
7651 pmap_invalidate_range(pmap, va, sva);
7654 pmap_invalidate_all(pmap);
7656 pmap_delayed_invl_finish();
7660 * Clear the modify bits on the specified physical page.
7663 pmap_clear_modify(vm_page_t m)
7665 struct md_page *pvh;
7667 pv_entry_t next_pv, pv;
7668 pd_entry_t oldpde, *pde;
7669 pt_entry_t oldpte, *pte, PG_M, PG_RW, PG_V;
7670 struct rwlock *lock;
7672 int md_gen, pvh_gen;
7674 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7675 ("pmap_clear_modify: page %p is not managed", m));
7676 VM_OBJECT_ASSERT_WLOCKED(m->object);
7677 KASSERT(!vm_page_xbusied(m),
7678 ("pmap_clear_modify: page %p is exclusive busied", m));
7681 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
7682 * If the object containing the page is locked and the page is not
7683 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
7685 if ((m->aflags & PGA_WRITEABLE) == 0)
7687 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7688 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7689 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7692 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7694 if (!PMAP_TRYLOCK(pmap)) {
7695 pvh_gen = pvh->pv_gen;
7699 if (pvh_gen != pvh->pv_gen) {
7704 PG_M = pmap_modified_bit(pmap);
7705 PG_V = pmap_valid_bit(pmap);
7706 PG_RW = pmap_rw_bit(pmap);
7708 pde = pmap_pde(pmap, va);
7710 if ((oldpde & PG_RW) != 0) {
7711 if (pmap_demote_pde_locked(pmap, pde, va, &lock)) {
7712 if ((oldpde & PG_W) == 0) {
7714 * Write protect the mapping to a
7715 * single page so that a subsequent
7716 * write access may repromote.
7718 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7720 pte = pmap_pde_to_pte(pde, va);
7722 if ((oldpte & PG_V) != 0) {
7723 while (!atomic_cmpset_long(pte,
7725 oldpte & ~(PG_M | PG_RW)))
7728 pmap_invalidate_page(pmap, va);
7735 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7737 if (!PMAP_TRYLOCK(pmap)) {
7738 md_gen = m->md.pv_gen;
7739 pvh_gen = pvh->pv_gen;
7743 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7748 PG_M = pmap_modified_bit(pmap);
7749 PG_RW = pmap_rw_bit(pmap);
7750 pde = pmap_pde(pmap, pv->pv_va);
7751 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
7752 " a 2mpage in page %p's pv list", m));
7753 pte = pmap_pde_to_pte(pde, pv->pv_va);
7754 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7755 atomic_clear_long(pte, PG_M);
7756 pmap_invalidate_page(pmap, pv->pv_va);
7764 * Miscellaneous support routines follow
7767 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
7768 static __inline void
7769 pmap_pte_attr(pt_entry_t *pte, int cache_bits, int mask)
7774 * The cache mode bits are all in the low 32-bits of the
7775 * PTE, so we can just spin on updating the low 32-bits.
7778 opte = *(u_int *)pte;
7779 npte = opte & ~mask;
7781 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
7784 /* Adjust the cache mode for a 2MB page mapped via a PDE. */
7785 static __inline void
7786 pmap_pde_attr(pd_entry_t *pde, int cache_bits, int mask)
7791 * The cache mode bits are all in the low 32-bits of the
7792 * PDE, so we can just spin on updating the low 32-bits.
7795 opde = *(u_int *)pde;
7796 npde = opde & ~mask;
7798 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
7802 * Map a set of physical memory pages into the kernel virtual
7803 * address space. Return a pointer to where it is mapped. This
7804 * routine is intended to be used for mapping device memory,
7808 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
7810 struct pmap_preinit_mapping *ppim;
7811 vm_offset_t va, offset;
7815 offset = pa & PAGE_MASK;
7816 size = round_page(offset + size);
7817 pa = trunc_page(pa);
7819 if (!pmap_initialized) {
7821 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7822 ppim = pmap_preinit_mapping + i;
7823 if (ppim->va == 0) {
7827 ppim->va = virtual_avail;
7828 virtual_avail += size;
7834 panic("%s: too many preinit mappings", __func__);
7837 * If we have a preinit mapping, re-use it.
7839 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7840 ppim = pmap_preinit_mapping + i;
7841 if (ppim->pa == pa && ppim->sz == size &&
7842 (ppim->mode == mode ||
7843 (flags & MAPDEV_SETATTR) == 0))
7844 return ((void *)(ppim->va + offset));
7847 * If the specified range of physical addresses fits within
7848 * the direct map window, use the direct map.
7850 if (pa < dmaplimit && pa + size <= dmaplimit) {
7851 va = PHYS_TO_DMAP(pa);
7852 if ((flags & MAPDEV_SETATTR) != 0) {
7853 PMAP_LOCK(kernel_pmap);
7854 i = pmap_change_attr_locked(va, size, mode, flags);
7855 PMAP_UNLOCK(kernel_pmap);
7859 return ((void *)(va + offset));
7861 va = kva_alloc(size);
7863 panic("%s: Couldn't allocate KVA", __func__);
7865 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
7866 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
7867 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
7868 if ((flags & MAPDEV_FLUSHCACHE) != 0)
7869 pmap_invalidate_cache_range(va, va + tmpsize);
7870 return ((void *)(va + offset));
7874 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
7877 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
7882 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
7885 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
7889 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
7892 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
7897 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
7900 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
7901 MAPDEV_FLUSHCACHE));
7905 pmap_unmapdev(vm_offset_t va, vm_size_t size)
7907 struct pmap_preinit_mapping *ppim;
7911 /* If we gave a direct map region in pmap_mapdev, do nothing */
7912 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
7914 offset = va & PAGE_MASK;
7915 size = round_page(offset + size);
7916 va = trunc_page(va);
7917 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
7918 ppim = pmap_preinit_mapping + i;
7919 if (ppim->va == va && ppim->sz == size) {
7920 if (pmap_initialized)
7926 if (va + size == virtual_avail)
7931 if (pmap_initialized)
7936 * Tries to demote a 1GB page mapping.
7939 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
7941 pdp_entry_t newpdpe, oldpdpe;
7942 pd_entry_t *firstpde, newpde, *pde;
7943 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7947 PG_A = pmap_accessed_bit(pmap);
7948 PG_M = pmap_modified_bit(pmap);
7949 PG_V = pmap_valid_bit(pmap);
7950 PG_RW = pmap_rw_bit(pmap);
7952 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7954 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
7955 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
7956 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
7957 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
7958 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
7959 " in pmap %p", va, pmap);
7962 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
7963 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
7964 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
7965 KASSERT((oldpdpe & PG_A) != 0,
7966 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
7967 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
7968 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
7972 * Initialize the page directory page.
7974 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
7980 * Demote the mapping.
7985 * Invalidate a stale recursive mapping of the page directory page.
7987 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
7989 pmap_pdpe_demotions++;
7990 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
7991 " in pmap %p", va, pmap);
7996 * Sets the memory attribute for the specified page.
7999 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8002 m->md.pat_mode = ma;
8005 * If "m" is a normal page, update its direct mapping. This update
8006 * can be relied upon to perform any cache operations that are
8007 * required for data coherence.
8009 if ((m->flags & PG_FICTITIOUS) == 0 &&
8010 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8012 panic("memory attribute change on the direct map failed");
8016 * Changes the specified virtual address range's memory type to that given by
8017 * the parameter "mode". The specified virtual address range must be
8018 * completely contained within either the direct map or the kernel map. If
8019 * the virtual address range is contained within the kernel map, then the
8020 * memory type for each of the corresponding ranges of the direct map is also
8021 * changed. (The corresponding ranges of the direct map are those ranges that
8022 * map the same physical pages as the specified virtual address range.) These
8023 * changes to the direct map are necessary because Intel describes the
8024 * behavior of their processors as "undefined" if two or more mappings to the
8025 * same physical page have different memory types.
8027 * Returns zero if the change completed successfully, and either EINVAL or
8028 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8029 * of the virtual address range was not mapped, and ENOMEM is returned if
8030 * there was insufficient memory available to complete the change. In the
8031 * latter case, the memory type may have been changed on some part of the
8032 * virtual address range or the direct map.
8035 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8039 PMAP_LOCK(kernel_pmap);
8040 error = pmap_change_attr_locked(va, size, mode, MAPDEV_FLUSHCACHE);
8041 PMAP_UNLOCK(kernel_pmap);
8046 pmap_change_attr_locked(vm_offset_t va, vm_size_t size, int mode, int flags)
8048 vm_offset_t base, offset, tmpva;
8049 vm_paddr_t pa_start, pa_end, pa_end1;
8053 int cache_bits_pte, cache_bits_pde, error;
8056 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8057 base = trunc_page(va);
8058 offset = va & PAGE_MASK;
8059 size = round_page(offset + size);
8062 * Only supported on kernel virtual addresses, including the direct
8063 * map but excluding the recursive map.
8065 if (base < DMAP_MIN_ADDRESS)
8068 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, 1);
8069 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, 0);
8073 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8074 * into 4KB pages if required.
8076 for (tmpva = base; tmpva < base + size; ) {
8077 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8078 if (pdpe == NULL || *pdpe == 0)
8080 if (*pdpe & PG_PS) {
8082 * If the current 1GB page already has the required
8083 * memory type, then we need not demote this page. Just
8084 * increment tmpva to the next 1GB page frame.
8086 if ((*pdpe & X86_PG_PDE_CACHE) == cache_bits_pde) {
8087 tmpva = trunc_1gpage(tmpva) + NBPDP;
8092 * If the current offset aligns with a 1GB page frame
8093 * and there is at least 1GB left within the range, then
8094 * we need not break down this page into 2MB pages.
8096 if ((tmpva & PDPMASK) == 0 &&
8097 tmpva + PDPMASK < base + size) {
8101 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8104 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8109 * If the current 2MB page already has the required
8110 * memory type, then we need not demote this page. Just
8111 * increment tmpva to the next 2MB page frame.
8113 if ((*pde & X86_PG_PDE_CACHE) == cache_bits_pde) {
8114 tmpva = trunc_2mpage(tmpva) + NBPDR;
8119 * If the current offset aligns with a 2MB page frame
8120 * and there is at least 2MB left within the range, then
8121 * we need not break down this page into 4KB pages.
8123 if ((tmpva & PDRMASK) == 0 &&
8124 tmpva + PDRMASK < base + size) {
8128 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8131 pte = pmap_pde_to_pte(pde, tmpva);
8139 * Ok, all the pages exist, so run through them updating their
8140 * cache mode if required.
8142 pa_start = pa_end = 0;
8143 for (tmpva = base; tmpva < base + size; ) {
8144 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8145 if (*pdpe & PG_PS) {
8146 if ((*pdpe & X86_PG_PDE_CACHE) != cache_bits_pde) {
8147 pmap_pde_attr(pdpe, cache_bits_pde,
8151 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8152 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8153 if (pa_start == pa_end) {
8154 /* Start physical address run. */
8155 pa_start = *pdpe & PG_PS_FRAME;
8156 pa_end = pa_start + NBPDP;
8157 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8160 /* Run ended, update direct map. */
8161 error = pmap_change_attr_locked(
8162 PHYS_TO_DMAP(pa_start),
8163 pa_end - pa_start, mode, flags);
8166 /* Start physical address run. */
8167 pa_start = *pdpe & PG_PS_FRAME;
8168 pa_end = pa_start + NBPDP;
8171 tmpva = trunc_1gpage(tmpva) + NBPDP;
8174 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8176 if ((*pde & X86_PG_PDE_CACHE) != cache_bits_pde) {
8177 pmap_pde_attr(pde, cache_bits_pde,
8181 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8182 (*pde & PG_PS_FRAME) < dmaplimit) {
8183 if (pa_start == pa_end) {
8184 /* Start physical address run. */
8185 pa_start = *pde & PG_PS_FRAME;
8186 pa_end = pa_start + NBPDR;
8187 } else if (pa_end == (*pde & PG_PS_FRAME))
8190 /* Run ended, update direct map. */
8191 error = pmap_change_attr_locked(
8192 PHYS_TO_DMAP(pa_start),
8193 pa_end - pa_start, mode, flags);
8196 /* Start physical address run. */
8197 pa_start = *pde & PG_PS_FRAME;
8198 pa_end = pa_start + NBPDR;
8201 tmpva = trunc_2mpage(tmpva) + NBPDR;
8203 pte = pmap_pde_to_pte(pde, tmpva);
8204 if ((*pte & X86_PG_PTE_CACHE) != cache_bits_pte) {
8205 pmap_pte_attr(pte, cache_bits_pte,
8209 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8210 (*pte & PG_FRAME) < dmaplimit) {
8211 if (pa_start == pa_end) {
8212 /* Start physical address run. */
8213 pa_start = *pte & PG_FRAME;
8214 pa_end = pa_start + PAGE_SIZE;
8215 } else if (pa_end == (*pte & PG_FRAME))
8216 pa_end += PAGE_SIZE;
8218 /* Run ended, update direct map. */
8219 error = pmap_change_attr_locked(
8220 PHYS_TO_DMAP(pa_start),
8221 pa_end - pa_start, mode, flags);
8224 /* Start physical address run. */
8225 pa_start = *pte & PG_FRAME;
8226 pa_end = pa_start + PAGE_SIZE;
8232 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8233 pa_end1 = MIN(pa_end, dmaplimit);
8234 if (pa_start != pa_end1)
8235 error = pmap_change_attr_locked(PHYS_TO_DMAP(pa_start),
8236 pa_end1 - pa_start, mode, flags);
8240 * Flush CPU caches if required to make sure any data isn't cached that
8241 * shouldn't be, etc.
8244 pmap_invalidate_range(kernel_pmap, base, tmpva);
8245 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8246 pmap_invalidate_cache_range(base, tmpva);
8252 * Demotes any mapping within the direct map region that covers more than the
8253 * specified range of physical addresses. This range's size must be a power
8254 * of two and its starting address must be a multiple of its size. Since the
8255 * demotion does not change any attributes of the mapping, a TLB invalidation
8256 * is not mandatory. The caller may, however, request a TLB invalidation.
8259 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8268 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8269 KASSERT((base & (len - 1)) == 0,
8270 ("pmap_demote_DMAP: base is not a multiple of len"));
8271 if (len < NBPDP && base < dmaplimit) {
8272 va = PHYS_TO_DMAP(base);
8274 PMAP_LOCK(kernel_pmap);
8275 pdpe = pmap_pdpe(kernel_pmap, va);
8276 if ((*pdpe & X86_PG_V) == 0)
8277 panic("pmap_demote_DMAP: invalid PDPE");
8278 if ((*pdpe & PG_PS) != 0) {
8279 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8280 panic("pmap_demote_DMAP: PDPE failed");
8284 pde = pmap_pdpe_to_pde(pdpe, va);
8285 if ((*pde & X86_PG_V) == 0)
8286 panic("pmap_demote_DMAP: invalid PDE");
8287 if ((*pde & PG_PS) != 0) {
8288 if (!pmap_demote_pde(kernel_pmap, pde, va))
8289 panic("pmap_demote_DMAP: PDE failed");
8293 if (changed && invalidate)
8294 pmap_invalidate_page(kernel_pmap, va);
8295 PMAP_UNLOCK(kernel_pmap);
8300 * perform the pmap work for mincore
8303 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
8306 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8310 PG_A = pmap_accessed_bit(pmap);
8311 PG_M = pmap_modified_bit(pmap);
8312 PG_V = pmap_valid_bit(pmap);
8313 PG_RW = pmap_rw_bit(pmap);
8317 pdep = pmap_pde(pmap, addr);
8318 if (pdep != NULL && (*pdep & PG_V)) {
8319 if (*pdep & PG_PS) {
8321 /* Compute the physical address of the 4KB page. */
8322 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8324 val = MINCORE_SUPER;
8326 pte = *pmap_pde_to_pte(pdep, addr);
8327 pa = pte & PG_FRAME;
8335 if ((pte & PG_V) != 0) {
8336 val |= MINCORE_INCORE;
8337 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8338 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8339 if ((pte & PG_A) != 0)
8340 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8342 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8343 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8344 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8345 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
8346 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
8349 PA_UNLOCK_COND(*locked_pa);
8355 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8357 uint32_t gen, new_gen, pcid_next;
8359 CRITICAL_ASSERT(curthread);
8360 gen = PCPU_GET(pcid_gen);
8361 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8362 return (pti ? 0 : CR3_PCID_SAVE);
8363 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8364 return (CR3_PCID_SAVE);
8365 pcid_next = PCPU_GET(pcid_next);
8366 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8367 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8368 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8369 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8370 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8374 PCPU_SET(pcid_gen, new_gen);
8375 pcid_next = PMAP_PCID_KERN + 1;
8379 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8380 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8381 PCPU_SET(pcid_next, pcid_next + 1);
8386 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8390 cached = pmap_pcid_alloc(pmap, cpuid);
8391 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8392 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8393 pmap->pm_pcids[cpuid].pm_pcid));
8394 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8395 pmap == kernel_pmap,
8396 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8397 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8402 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8405 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8406 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_pcb;
8410 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8412 struct invpcid_descr d;
8413 uint64_t cached, cr3, kcr3, ucr3;
8415 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8417 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8418 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8419 PCPU_SET(curpmap, pmap);
8420 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8421 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8424 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8426 * Explicitly invalidate translations cached from the
8427 * user page table. They are not automatically
8428 * flushed by reload of cr3 with the kernel page table
8431 * Note that the if() condition is resolved statically
8432 * by using the function argument instead of
8433 * runtime-evaluated invpcid_works value.
8435 if (invpcid_works1) {
8436 d.pcid = PMAP_PCID_USER_PT |
8437 pmap->pm_pcids[cpuid].pm_pcid;
8440 invpcid(&d, INVPCID_CTX);
8442 pmap_pti_pcid_invalidate(ucr3, kcr3);
8446 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8447 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8449 PCPU_INC(pm_save_cnt);
8453 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8456 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8457 pmap_activate_sw_pti_post(td, pmap);
8461 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8467 * If the INVPCID instruction is not available,
8468 * invltlb_pcid_handler() is used to handle an invalidate_all
8469 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8470 * sequence of operations has a window where %CR3 is loaded
8471 * with the new pmap's PML4 address, but the curpmap value has
8472 * not yet been updated. This causes the invltlb IPI handler,
8473 * which is called between the updates, to execute as a NOP,
8474 * which leaves stale TLB entries.
8476 * Note that the most typical use of pmap_activate_sw(), from
8477 * the context switch, is immune to this race, because
8478 * interrupts are disabled (while the thread lock is owned),
8479 * and the IPI happens after curpmap is updated. Protect
8480 * other callers in a similar way, by disabling interrupts
8481 * around the %cr3 register reload and curpmap assignment.
8483 rflags = intr_disable();
8484 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8485 intr_restore(rflags);
8486 pmap_activate_sw_pti_post(td, pmap);
8490 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8493 uint64_t cached, cr3;
8495 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8497 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8498 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8500 PCPU_SET(curpmap, pmap);
8502 PCPU_INC(pm_save_cnt);
8506 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8511 rflags = intr_disable();
8512 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8513 intr_restore(rflags);
8517 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8518 u_int cpuid __unused)
8521 load_cr3(pmap->pm_cr3);
8522 PCPU_SET(curpmap, pmap);
8526 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8527 u_int cpuid __unused)
8530 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8531 PCPU_SET(kcr3, pmap->pm_cr3);
8532 PCPU_SET(ucr3, pmap->pm_ucr3);
8533 pmap_activate_sw_pti_post(td, pmap);
8536 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8540 if (pmap_pcid_enabled && pti && invpcid_works)
8541 return (pmap_activate_sw_pcid_invpcid_pti);
8542 else if (pmap_pcid_enabled && pti && !invpcid_works)
8543 return (pmap_activate_sw_pcid_noinvpcid_pti);
8544 else if (pmap_pcid_enabled && !pti && invpcid_works)
8545 return (pmap_activate_sw_pcid_nopti);
8546 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8547 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8548 else if (!pmap_pcid_enabled && pti)
8549 return (pmap_activate_sw_nopcid_pti);
8550 else /* if (!pmap_pcid_enabled && !pti) */
8551 return (pmap_activate_sw_nopcid_nopti);
8555 pmap_activate_sw(struct thread *td)
8557 pmap_t oldpmap, pmap;
8560 oldpmap = PCPU_GET(curpmap);
8561 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8562 if (oldpmap == pmap)
8564 cpuid = PCPU_GET(cpuid);
8566 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8568 CPU_SET(cpuid, &pmap->pm_active);
8570 pmap_activate_sw_mode(td, pmap, cpuid);
8572 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8574 CPU_CLR(cpuid, &oldpmap->pm_active);
8579 pmap_activate(struct thread *td)
8583 pmap_activate_sw(td);
8588 pmap_activate_boot(pmap_t pmap)
8594 * kernel_pmap must be never deactivated, and we ensure that
8595 * by never activating it at all.
8597 MPASS(pmap != kernel_pmap);
8599 cpuid = PCPU_GET(cpuid);
8601 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8603 CPU_SET(cpuid, &pmap->pm_active);
8605 PCPU_SET(curpmap, pmap);
8607 kcr3 = pmap->pm_cr3;
8608 if (pmap_pcid_enabled)
8609 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8613 PCPU_SET(kcr3, kcr3);
8614 PCPU_SET(ucr3, PMAP_NO_CR3);
8618 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8623 * Increase the starting virtual address of the given mapping if a
8624 * different alignment might result in more superpage mappings.
8627 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8628 vm_offset_t *addr, vm_size_t size)
8630 vm_offset_t superpage_offset;
8634 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8635 offset += ptoa(object->pg_color);
8636 superpage_offset = offset & PDRMASK;
8637 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8638 (*addr & PDRMASK) == superpage_offset)
8640 if ((*addr & PDRMASK) < superpage_offset)
8641 *addr = (*addr & ~PDRMASK) + superpage_offset;
8643 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
8647 static unsigned long num_dirty_emulations;
8648 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
8649 &num_dirty_emulations, 0, NULL);
8651 static unsigned long num_accessed_emulations;
8652 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
8653 &num_accessed_emulations, 0, NULL);
8655 static unsigned long num_superpage_accessed_emulations;
8656 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
8657 &num_superpage_accessed_emulations, 0, NULL);
8659 static unsigned long ad_emulation_superpage_promotions;
8660 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
8661 &ad_emulation_superpage_promotions, 0, NULL);
8662 #endif /* INVARIANTS */
8665 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
8668 struct rwlock *lock;
8669 #if VM_NRESERVLEVEL > 0
8673 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
8675 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
8676 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
8678 if (!pmap_emulate_ad_bits(pmap))
8681 PG_A = pmap_accessed_bit(pmap);
8682 PG_M = pmap_modified_bit(pmap);
8683 PG_V = pmap_valid_bit(pmap);
8684 PG_RW = pmap_rw_bit(pmap);
8690 pde = pmap_pde(pmap, va);
8691 if (pde == NULL || (*pde & PG_V) == 0)
8694 if ((*pde & PG_PS) != 0) {
8695 if (ftype == VM_PROT_READ) {
8697 atomic_add_long(&num_superpage_accessed_emulations, 1);
8705 pte = pmap_pde_to_pte(pde, va);
8706 if ((*pte & PG_V) == 0)
8709 if (ftype == VM_PROT_WRITE) {
8710 if ((*pte & PG_RW) == 0)
8713 * Set the modified and accessed bits simultaneously.
8715 * Intel EPT PTEs that do software emulation of A/D bits map
8716 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
8717 * An EPT misconfiguration is triggered if the PTE is writable
8718 * but not readable (WR=10). This is avoided by setting PG_A
8719 * and PG_M simultaneously.
8721 *pte |= PG_M | PG_A;
8726 #if VM_NRESERVLEVEL > 0
8727 /* try to promote the mapping */
8728 if (va < VM_MAXUSER_ADDRESS)
8729 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
8733 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8735 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
8736 pmap_ps_enabled(pmap) &&
8737 (m->flags & PG_FICTITIOUS) == 0 &&
8738 vm_reserv_level_iffullpop(m) == 0) {
8739 pmap_promote_pde(pmap, pde, va, &lock);
8741 atomic_add_long(&ad_emulation_superpage_promotions, 1);
8747 if (ftype == VM_PROT_WRITE)
8748 atomic_add_long(&num_dirty_emulations, 1);
8750 atomic_add_long(&num_accessed_emulations, 1);
8752 rv = 0; /* success */
8761 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
8766 pt_entry_t *pte, PG_V;
8770 PG_V = pmap_valid_bit(pmap);
8773 pml4 = pmap_pml4e(pmap, va);
8775 if ((*pml4 & PG_V) == 0)
8778 pdp = pmap_pml4e_to_pdpe(pml4, va);
8780 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
8783 pde = pmap_pdpe_to_pde(pdp, va);
8785 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
8788 pte = pmap_pde_to_pte(pde, va);
8797 * Get the kernel virtual address of a set of physical pages. If there are
8798 * physical addresses not covered by the DMAP perform a transient mapping
8799 * that will be removed when calling pmap_unmap_io_transient.
8801 * \param page The pages the caller wishes to obtain the virtual
8802 * address on the kernel memory map.
8803 * \param vaddr On return contains the kernel virtual memory address
8804 * of the pages passed in the page parameter.
8805 * \param count Number of pages passed in.
8806 * \param can_fault TRUE if the thread using the mapped pages can take
8807 * page faults, FALSE otherwise.
8809 * \returns TRUE if the caller must call pmap_unmap_io_transient when
8810 * finished or FALSE otherwise.
8814 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8815 boolean_t can_fault)
8818 boolean_t needs_mapping;
8820 int cache_bits, error __unused, i;
8823 * Allocate any KVA space that we need, this is done in a separate
8824 * loop to prevent calling vmem_alloc while pinned.
8826 needs_mapping = FALSE;
8827 for (i = 0; i < count; i++) {
8828 paddr = VM_PAGE_TO_PHYS(page[i]);
8829 if (__predict_false(paddr >= dmaplimit)) {
8830 error = vmem_alloc(kernel_arena, PAGE_SIZE,
8831 M_BESTFIT | M_WAITOK, &vaddr[i]);
8832 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
8833 needs_mapping = TRUE;
8835 vaddr[i] = PHYS_TO_DMAP(paddr);
8839 /* Exit early if everything is covered by the DMAP */
8844 * NB: The sequence of updating a page table followed by accesses
8845 * to the corresponding pages used in the !DMAP case is subject to
8846 * the situation described in the "AMD64 Architecture Programmer's
8847 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
8848 * Coherency Considerations". Therefore, issuing the INVLPG right
8849 * after modifying the PTE bits is crucial.
8853 for (i = 0; i < count; i++) {
8854 paddr = VM_PAGE_TO_PHYS(page[i]);
8855 if (paddr >= dmaplimit) {
8858 * Slow path, since we can get page faults
8859 * while mappings are active don't pin the
8860 * thread to the CPU and instead add a global
8861 * mapping visible to all CPUs.
8863 pmap_qenter(vaddr[i], &page[i], 1);
8865 pte = vtopte(vaddr[i]);
8866 cache_bits = pmap_cache_bits(kernel_pmap,
8867 page[i]->md.pat_mode, 0);
8868 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
8875 return (needs_mapping);
8879 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
8880 boolean_t can_fault)
8887 for (i = 0; i < count; i++) {
8888 paddr = VM_PAGE_TO_PHYS(page[i]);
8889 if (paddr >= dmaplimit) {
8891 pmap_qremove(vaddr[i], 1);
8892 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
8898 pmap_quick_enter_page(vm_page_t m)
8902 paddr = VM_PAGE_TO_PHYS(m);
8903 if (paddr < dmaplimit)
8904 return (PHYS_TO_DMAP(paddr));
8905 mtx_lock_spin(&qframe_mtx);
8906 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
8907 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
8908 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
8913 pmap_quick_remove_page(vm_offset_t addr)
8918 pte_store(vtopte(qframe), 0);
8920 mtx_unlock_spin(&qframe_mtx);
8924 * Pdp pages from the large map are managed differently from either
8925 * kernel or user page table pages. They are permanently allocated at
8926 * initialization time, and their wire count is permanently set to
8927 * zero. The pml4 entries pointing to those pages are copied into
8928 * each allocated pmap.
8930 * In contrast, pd and pt pages are managed like user page table
8931 * pages. They are dynamically allocated, and their wire count
8932 * represents the number of valid entries within the page.
8935 pmap_large_map_getptp_unlocked(void)
8939 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
8941 if (m != NULL && (m->flags & PG_ZERO) == 0)
8947 pmap_large_map_getptp(void)
8951 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8952 m = pmap_large_map_getptp_unlocked();
8954 PMAP_UNLOCK(kernel_pmap);
8956 PMAP_LOCK(kernel_pmap);
8957 /* Callers retry. */
8962 static pdp_entry_t *
8963 pmap_large_map_pdpe(vm_offset_t va)
8965 vm_pindex_t pml4_idx;
8968 pml4_idx = pmap_pml4e_index(va);
8969 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
8970 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
8972 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8973 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
8974 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
8975 "LMSPML4I %#jx lm_ents %d",
8976 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
8977 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
8978 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
8982 pmap_large_map_pde(vm_offset_t va)
8989 pdpe = pmap_large_map_pdpe(va);
8991 m = pmap_large_map_getptp();
8994 mphys = VM_PAGE_TO_PHYS(m);
8995 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
8997 MPASS((*pdpe & X86_PG_PS) == 0);
8998 mphys = *pdpe & PG_FRAME;
9000 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9004 pmap_large_map_pte(vm_offset_t va)
9011 pde = pmap_large_map_pde(va);
9013 m = pmap_large_map_getptp();
9016 mphys = VM_PAGE_TO_PHYS(m);
9017 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9018 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->wire_count++;
9020 MPASS((*pde & X86_PG_PS) == 0);
9021 mphys = *pde & PG_FRAME;
9023 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9027 pmap_large_map_kextract(vm_offset_t va)
9029 pdp_entry_t *pdpe, pdp;
9030 pd_entry_t *pde, pd;
9031 pt_entry_t *pte, pt;
9033 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9034 ("not largemap range %#lx", (u_long)va));
9035 pdpe = pmap_large_map_pdpe(va);
9037 KASSERT((pdp & X86_PG_V) != 0,
9038 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9039 (u_long)pdpe, pdp));
9040 if ((pdp & X86_PG_PS) != 0) {
9041 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9042 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9043 (u_long)pdpe, pdp));
9044 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9046 pde = pmap_pdpe_to_pde(pdpe, va);
9048 KASSERT((pd & X86_PG_V) != 0,
9049 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9050 if ((pd & X86_PG_PS) != 0)
9051 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9052 pte = pmap_pde_to_pte(pde, va);
9054 KASSERT((pt & X86_PG_V) != 0,
9055 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9056 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9060 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9061 vmem_addr_t *vmem_res)
9065 * Large mappings are all but static. Consequently, there
9066 * is no point in waiting for an earlier allocation to be
9069 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9070 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9074 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9080 vm_offset_t va, inc;
9081 vmem_addr_t vmem_res;
9085 if (len == 0 || spa + len < spa)
9088 /* See if DMAP can serve. */
9089 if (spa + len <= dmaplimit) {
9090 va = PHYS_TO_DMAP(spa);
9092 return (pmap_change_attr(va, len, mattr));
9096 * No, allocate KVA. Fit the address with best possible
9097 * alignment for superpages. Fall back to worse align if
9101 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9102 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9103 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9105 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9107 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9110 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9115 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9116 * in the pagetable to minimize flushing. No need to
9117 * invalidate TLB, since we only update invalid entries.
9119 PMAP_LOCK(kernel_pmap);
9120 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9122 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9123 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9124 pdpe = pmap_large_map_pdpe(va);
9126 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9127 X86_PG_V | X86_PG_A | pg_nx |
9128 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9130 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9131 (va & PDRMASK) == 0) {
9132 pde = pmap_large_map_pde(va);
9134 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9135 X86_PG_V | X86_PG_A | pg_nx |
9136 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9137 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9141 pte = pmap_large_map_pte(va);
9143 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9144 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9146 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9151 PMAP_UNLOCK(kernel_pmap);
9154 *addr = (void *)vmem_res;
9159 pmap_large_unmap(void *svaa, vm_size_t len)
9161 vm_offset_t sva, va;
9163 pdp_entry_t *pdpe, pdp;
9164 pd_entry_t *pde, pd;
9167 struct spglist spgf;
9169 sva = (vm_offset_t)svaa;
9170 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9171 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9175 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9176 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9177 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9178 PMAP_LOCK(kernel_pmap);
9179 for (va = sva; va < sva + len; va += inc) {
9180 pdpe = pmap_large_map_pdpe(va);
9182 KASSERT((pdp & X86_PG_V) != 0,
9183 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9184 (u_long)pdpe, pdp));
9185 if ((pdp & X86_PG_PS) != 0) {
9186 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9187 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9188 (u_long)pdpe, pdp));
9189 KASSERT((va & PDPMASK) == 0,
9190 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9191 (u_long)pdpe, pdp));
9192 KASSERT(va + NBPDP <= sva + len,
9193 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9194 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9195 (u_long)pdpe, pdp, len));
9200 pde = pmap_pdpe_to_pde(pdpe, va);
9202 KASSERT((pd & X86_PG_V) != 0,
9203 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9205 if ((pd & X86_PG_PS) != 0) {
9206 KASSERT((va & PDRMASK) == 0,
9207 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9209 KASSERT(va + NBPDR <= sva + len,
9210 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9211 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9215 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9217 if (m->wire_count == 0) {
9219 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9223 pte = pmap_pde_to_pte(pde, va);
9224 KASSERT((*pte & X86_PG_V) != 0,
9225 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9226 (u_long)pte, *pte));
9229 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9231 if (m->wire_count == 0) {
9233 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9234 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9236 if (m->wire_count == 0) {
9238 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9242 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9243 PMAP_UNLOCK(kernel_pmap);
9244 vm_page_free_pages_toq(&spgf, false);
9245 vmem_free(large_vmem, sva, len);
9249 pmap_large_map_wb_fence_mfence(void)
9256 pmap_large_map_wb_fence_sfence(void)
9263 pmap_large_map_wb_fence_nop(void)
9267 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void), static)
9270 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9271 return (pmap_large_map_wb_fence_mfence);
9272 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9273 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9274 return (pmap_large_map_wb_fence_sfence);
9276 /* clflush is strongly enough ordered */
9277 return (pmap_large_map_wb_fence_nop);
9281 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9284 for (; len > 0; len -= cpu_clflush_line_size,
9285 va += cpu_clflush_line_size)
9290 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9293 for (; len > 0; len -= cpu_clflush_line_size,
9294 va += cpu_clflush_line_size)
9299 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9302 for (; len > 0; len -= cpu_clflush_line_size,
9303 va += cpu_clflush_line_size)
9308 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9312 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t),
9316 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9317 return (pmap_large_map_flush_range_clwb);
9318 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9319 return (pmap_large_map_flush_range_clflushopt);
9320 else if ((cpu_feature & CPUID_CLFSH) != 0)
9321 return (pmap_large_map_flush_range_clflush);
9323 return (pmap_large_map_flush_range_nop);
9327 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9329 volatile u_long *pe;
9335 for (va = sva; va < eva; va += inc) {
9337 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9338 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9340 if ((p & X86_PG_PS) != 0)
9344 pe = (volatile u_long *)pmap_large_map_pde(va);
9346 if ((p & X86_PG_PS) != 0)
9350 pe = (volatile u_long *)pmap_large_map_pte(va);
9356 if ((p & X86_PG_AVAIL1) != 0) {
9358 * Spin-wait for the end of a parallel
9365 * If we saw other write-back
9366 * occuring, we cannot rely on PG_M to
9367 * indicate state of the cache. The
9368 * PG_M bit is cleared before the
9369 * flush to avoid ignoring new writes,
9370 * and writes which are relevant for
9371 * us might happen after.
9377 if ((p & X86_PG_M) != 0 || seen_other) {
9378 if (!atomic_fcmpset_long(pe, &p,
9379 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9381 * If we saw PG_M without
9382 * PG_AVAIL1, and then on the
9383 * next attempt we do not
9384 * observe either PG_M or
9385 * PG_AVAIL1, the other
9386 * write-back started after us
9387 * and finished before us. We
9388 * can rely on it doing our
9392 pmap_large_map_flush_range(va, inc);
9393 atomic_clear_long(pe, X86_PG_AVAIL1);
9402 * Write-back cache lines for the given address range.
9404 * Must be called only on the range or sub-range returned from
9405 * pmap_large_map(). Must not be called on the coalesced ranges.
9407 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9408 * instructions support.
9411 pmap_large_map_wb(void *svap, vm_size_t len)
9413 vm_offset_t eva, sva;
9415 sva = (vm_offset_t)svap;
9417 pmap_large_map_wb_fence();
9418 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9419 pmap_large_map_flush_range(sva, len);
9421 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9422 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9423 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9424 pmap_large_map_wb_large(sva, eva);
9426 pmap_large_map_wb_fence();
9430 pmap_pti_alloc_page(void)
9434 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9435 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9436 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9441 pmap_pti_free_page(vm_page_t m)
9444 KASSERT(m->wire_count > 0, ("page %p not wired", m));
9445 if (!vm_page_unwire_noq(m))
9447 vm_page_free_zero(m);
9461 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9462 VM_OBJECT_WLOCK(pti_obj);
9463 pml4_pg = pmap_pti_alloc_page();
9464 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9465 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9466 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9467 pdpe = pmap_pti_pdpe(va);
9468 pmap_pti_wire_pte(pdpe);
9470 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9471 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9472 pmap_pti_add_kva_locked((vm_offset_t)gdt, (vm_offset_t)gdt +
9473 sizeof(struct user_segment_descriptor) * NGDT * MAXCPU, false);
9474 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9475 sizeof(struct gate_descriptor) * NIDT, false);
9476 pmap_pti_add_kva_locked((vm_offset_t)common_tss,
9477 (vm_offset_t)common_tss + sizeof(struct amd64tss) * MAXCPU, false);
9479 /* Doublefault stack IST 1 */
9480 va = common_tss[i].tss_ist1;
9481 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9482 /* NMI stack IST 2 */
9483 va = common_tss[i].tss_ist2 + sizeof(struct nmi_pcpu);
9484 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9485 /* MC# stack IST 3 */
9486 va = common_tss[i].tss_ist3 + sizeof(struct nmi_pcpu);
9487 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9488 /* DB# stack IST 4 */
9489 va = common_tss[i].tss_ist4 + sizeof(struct nmi_pcpu);
9490 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9492 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9493 (vm_offset_t)etext, true);
9494 pti_finalized = true;
9495 VM_OBJECT_WUNLOCK(pti_obj);
9497 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9499 static pdp_entry_t *
9500 pmap_pti_pdpe(vm_offset_t va)
9502 pml4_entry_t *pml4e;
9505 vm_pindex_t pml4_idx;
9508 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9510 pml4_idx = pmap_pml4e_index(va);
9511 pml4e = &pti_pml4[pml4_idx];
9515 panic("pml4 alloc after finalization\n");
9516 m = pmap_pti_alloc_page();
9518 pmap_pti_free_page(m);
9519 mphys = *pml4e & ~PAGE_MASK;
9521 mphys = VM_PAGE_TO_PHYS(m);
9522 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9525 mphys = *pml4e & ~PAGE_MASK;
9527 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9532 pmap_pti_wire_pte(void *pte)
9536 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9537 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9542 pmap_pti_unwire_pde(void *pde, bool only_ref)
9546 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9547 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9548 MPASS(m->wire_count > 0);
9549 MPASS(only_ref || m->wire_count > 1);
9550 pmap_pti_free_page(m);
9554 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9559 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9560 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9561 MPASS(m->wire_count > 0);
9562 if (pmap_pti_free_page(m)) {
9563 pde = pmap_pti_pde(va);
9564 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9566 pmap_pti_unwire_pde(pde, false);
9571 pmap_pti_pde(vm_offset_t va)
9579 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9581 pdpe = pmap_pti_pdpe(va);
9583 m = pmap_pti_alloc_page();
9585 pmap_pti_free_page(m);
9586 MPASS((*pdpe & X86_PG_PS) == 0);
9587 mphys = *pdpe & ~PAGE_MASK;
9589 mphys = VM_PAGE_TO_PHYS(m);
9590 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9593 MPASS((*pdpe & X86_PG_PS) == 0);
9594 mphys = *pdpe & ~PAGE_MASK;
9597 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9598 pd_idx = pmap_pde_index(va);
9604 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9611 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9613 pde = pmap_pti_pde(va);
9614 if (unwire_pde != NULL) {
9616 pmap_pti_wire_pte(pde);
9619 m = pmap_pti_alloc_page();
9621 pmap_pti_free_page(m);
9622 MPASS((*pde & X86_PG_PS) == 0);
9623 mphys = *pde & ~(PAGE_MASK | pg_nx);
9625 mphys = VM_PAGE_TO_PHYS(m);
9626 *pde = mphys | X86_PG_RW | X86_PG_V;
9627 if (unwire_pde != NULL)
9628 *unwire_pde = false;
9631 MPASS((*pde & X86_PG_PS) == 0);
9632 mphys = *pde & ~(PAGE_MASK | pg_nx);
9635 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9636 pte += pmap_pte_index(va);
9642 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9646 pt_entry_t *pte, ptev;
9649 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9651 sva = trunc_page(sva);
9652 MPASS(sva > VM_MAXUSER_ADDRESS);
9653 eva = round_page(eva);
9655 for (; sva < eva; sva += PAGE_SIZE) {
9656 pte = pmap_pti_pte(sva, &unwire_pde);
9657 pa = pmap_kextract(sva);
9658 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
9659 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
9660 VM_MEMATTR_DEFAULT, FALSE);
9662 pte_store(pte, ptev);
9663 pmap_pti_wire_pte(pte);
9665 KASSERT(!pti_finalized,
9666 ("pti overlap after fin %#lx %#lx %#lx",
9668 KASSERT(*pte == ptev,
9669 ("pti non-identical pte after fin %#lx %#lx %#lx",
9673 pde = pmap_pti_pde(sva);
9674 pmap_pti_unwire_pde(pde, true);
9680 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
9685 VM_OBJECT_WLOCK(pti_obj);
9686 pmap_pti_add_kva_locked(sva, eva, exec);
9687 VM_OBJECT_WUNLOCK(pti_obj);
9691 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
9698 sva = rounddown2(sva, PAGE_SIZE);
9699 MPASS(sva > VM_MAXUSER_ADDRESS);
9700 eva = roundup2(eva, PAGE_SIZE);
9702 VM_OBJECT_WLOCK(pti_obj);
9703 for (va = sva; va < eva; va += PAGE_SIZE) {
9704 pte = pmap_pti_pte(va, NULL);
9705 KASSERT((*pte & X86_PG_V) != 0,
9706 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9707 (u_long)pte, *pte));
9709 pmap_pti_unwire_pte(pte, va);
9711 pmap_invalidate_range(kernel_pmap, sva, eva);
9712 VM_OBJECT_WUNLOCK(pti_obj);
9716 pkru_dup_range(void *ctx __unused, void *data)
9718 struct pmap_pkru_range *node, *new_node;
9720 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9721 if (new_node == NULL)
9724 memcpy(new_node, node, sizeof(*node));
9729 pkru_free_range(void *ctx __unused, void *node)
9732 uma_zfree(pmap_pkru_ranges_zone, node);
9736 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9739 struct pmap_pkru_range *ppr;
9742 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9743 MPASS(pmap->pm_type == PT_X86);
9744 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9745 if ((flags & AMD64_PKRU_EXCL) != 0 &&
9746 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
9748 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
9751 ppr->pkru_keyidx = keyidx;
9752 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
9753 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
9755 uma_zfree(pmap_pkru_ranges_zone, ppr);
9760 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9764 MPASS(pmap->pm_type == PT_X86);
9765 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9766 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
9770 pmap_pkru_deassign_all(pmap_t pmap)
9773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9774 if (pmap->pm_type == PT_X86 &&
9775 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
9776 rangeset_remove_all(&pmap->pm_pkru);
9780 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9782 struct pmap_pkru_range *ppr, *prev_ppr;
9785 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9786 if (pmap->pm_type != PT_X86 ||
9787 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9788 sva >= VM_MAXUSER_ADDRESS)
9790 MPASS(eva <= VM_MAXUSER_ADDRESS);
9791 for (va = sva, prev_ppr = NULL; va < eva;) {
9792 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9793 if ((ppr == NULL) ^ (prev_ppr == NULL))
9799 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
9801 va = ppr->pkru_rs_el.re_end;
9807 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
9809 struct pmap_pkru_range *ppr;
9811 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9812 if (pmap->pm_type != PT_X86 ||
9813 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
9814 va >= VM_MAXUSER_ADDRESS)
9816 ppr = rangeset_lookup(&pmap->pm_pkru, va);
9818 return (X86_PG_PKU(ppr->pkru_keyidx));
9823 pred_pkru_on_remove(void *ctx __unused, void *r)
9825 struct pmap_pkru_range *ppr;
9828 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
9832 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9835 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9836 if (pmap->pm_type == PT_X86 &&
9837 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
9838 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
9839 pred_pkru_on_remove);
9844 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
9847 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
9848 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
9849 MPASS(dst_pmap->pm_type == PT_X86);
9850 MPASS(src_pmap->pm_type == PT_X86);
9851 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
9852 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
9854 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
9858 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9861 pml4_entry_t *pml4e;
9863 pd_entry_t newpde, ptpaddr, *pde;
9864 pt_entry_t newpte, *ptep, pte;
9865 vm_offset_t va, va_next;
9868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
9869 MPASS(pmap->pm_type == PT_X86);
9870 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
9872 for (changed = false, va = sva; va < eva; va = va_next) {
9873 pml4e = pmap_pml4e(pmap, va);
9874 if ((*pml4e & X86_PG_V) == 0) {
9875 va_next = (va + NBPML4) & ~PML4MASK;
9881 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
9882 if ((*pdpe & X86_PG_V) == 0) {
9883 va_next = (va + NBPDP) & ~PDPMASK;
9889 va_next = (va + NBPDR) & ~PDRMASK;
9893 pde = pmap_pdpe_to_pde(pdpe, va);
9898 MPASS((ptpaddr & X86_PG_V) != 0);
9899 if ((ptpaddr & PG_PS) != 0) {
9900 if (va + NBPDR == va_next && eva >= va_next) {
9901 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
9903 if (newpde != ptpaddr) {
9908 } else if (!pmap_demote_pde(pmap, pde, va)) {
9916 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
9917 ptep++, va += PAGE_SIZE) {
9919 if ((pte & X86_PG_V) == 0)
9921 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
9922 if (newpte != pte) {
9929 pmap_invalidate_range(pmap, sva, eva);
9933 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
9934 u_int keyidx, int flags)
9937 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
9938 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
9940 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
9942 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
9948 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
9953 sva = trunc_page(sva);
9954 eva = round_page(eva);
9955 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
9960 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
9962 pmap_pkru_update_range(pmap, sva, eva, keyidx);
9964 if (error != ENOMEM)
9972 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
9976 sva = trunc_page(sva);
9977 eva = round_page(eva);
9978 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
9983 error = pmap_pkru_deassign(pmap, sva, eva);
9985 pmap_pkru_update_range(pmap, sva, eva, 0);
9987 if (error != ENOMEM)
9995 DB_SHOW_COMMAND(pte, pmap_print_pte)
10001 pt_entry_t *pte, PG_V;
10005 db_printf("show pte addr\n");
10008 va = (vm_offset_t)addr;
10010 if (kdb_thread != NULL)
10011 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10013 pmap = PCPU_GET(curpmap);
10015 PG_V = pmap_valid_bit(pmap);
10016 pml4 = pmap_pml4e(pmap, va);
10017 db_printf("VA %#016lx pml4e %#016lx", va, *pml4);
10018 if ((*pml4 & PG_V) == 0) {
10022 pdp = pmap_pml4e_to_pdpe(pml4, va);
10023 db_printf(" pdpe %#016lx", *pdp);
10024 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10028 pde = pmap_pdpe_to_pde(pdp, va);
10029 db_printf(" pde %#016lx", *pde);
10030 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10034 pte = pmap_pde_to_pte(pde, va);
10035 db_printf(" pte %#016lx\n", *pte);
10038 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10043 a = (vm_paddr_t)addr;
10044 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10046 db_printf("show phys2dmap addr\n");