2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
130 #include <sys/turnstile.h>
131 #include <sys/vmem.h>
132 #include <sys/vmmeter.h>
133 #include <sys/sched.h>
134 #include <sys/sysctl.h>
142 #include <vm/vm_param.h>
143 #include <vm/vm_kern.h>
144 #include <vm/vm_page.h>
145 #include <vm/vm_map.h>
146 #include <vm/vm_object.h>
147 #include <vm/vm_extern.h>
148 #include <vm/vm_pageout.h>
149 #include <vm/vm_pager.h>
150 #include <vm/vm_phys.h>
151 #include <vm/vm_radix.h>
152 #include <vm/vm_reserv.h>
153 #include <vm/vm_dumpset.h>
156 #include <machine/intr_machdep.h>
157 #include <x86/apicvar.h>
158 #include <x86/ifunc.h>
159 #include <machine/cpu.h>
160 #include <machine/cputypes.h>
161 #include <machine/intr_machdep.h>
162 #include <machine/md_var.h>
163 #include <machine/pcb.h>
164 #include <machine/specialreg.h>
166 #include <machine/smp.h>
168 #include <machine/sysarch.h>
169 #include <machine/tss.h>
172 #define PMAP_MEMDOM MAXMEMDOM
174 #define PMAP_MEMDOM 1
177 static __inline boolean_t
178 pmap_type_guest(pmap_t pmap)
181 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
184 static __inline boolean_t
185 pmap_emulate_ad_bits(pmap_t pmap)
188 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
191 static __inline pt_entry_t
192 pmap_valid_bit(pmap_t pmap)
196 switch (pmap->pm_type) {
202 if (pmap_emulate_ad_bits(pmap))
203 mask = EPT_PG_EMUL_V;
208 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
214 static __inline pt_entry_t
215 pmap_rw_bit(pmap_t pmap)
219 switch (pmap->pm_type) {
225 if (pmap_emulate_ad_bits(pmap))
226 mask = EPT_PG_EMUL_RW;
231 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
237 static pt_entry_t pg_g;
239 static __inline pt_entry_t
240 pmap_global_bit(pmap_t pmap)
244 switch (pmap->pm_type) {
253 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
259 static __inline pt_entry_t
260 pmap_accessed_bit(pmap_t pmap)
264 switch (pmap->pm_type) {
270 if (pmap_emulate_ad_bits(pmap))
276 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
282 static __inline pt_entry_t
283 pmap_modified_bit(pmap_t pmap)
287 switch (pmap->pm_type) {
293 if (pmap_emulate_ad_bits(pmap))
299 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
305 static __inline pt_entry_t
306 pmap_pku_mask_bit(pmap_t pmap)
309 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
312 #if !defined(DIAGNOSTIC)
313 #ifdef __GNUC_GNU_INLINE__
314 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
316 #define PMAP_INLINE extern inline
323 #define PV_STAT(x) do { x ; } while (0)
325 #define PV_STAT(x) do { } while (0)
330 #define pa_index(pa) ({ \
331 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
332 ("address %lx beyond the last segment", (pa))); \
335 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
336 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
337 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
338 struct rwlock *_lock; \
339 if (__predict_false((pa) > pmap_last_pa)) \
340 _lock = &pv_dummy_large.pv_lock; \
342 _lock = &(pa_to_pmdp(pa)->pv_lock); \
346 #define pa_index(pa) ((pa) >> PDRSHIFT)
347 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
349 #define NPV_LIST_LOCKS MAXCPU
351 #define PHYS_TO_PV_LIST_LOCK(pa) \
352 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
355 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
356 struct rwlock **_lockp = (lockp); \
357 struct rwlock *_new_lock; \
359 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
360 if (_new_lock != *_lockp) { \
361 if (*_lockp != NULL) \
362 rw_wunlock(*_lockp); \
363 *_lockp = _new_lock; \
368 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
369 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
371 #define RELEASE_PV_LIST_LOCK(lockp) do { \
372 struct rwlock **_lockp = (lockp); \
374 if (*_lockp != NULL) { \
375 rw_wunlock(*_lockp); \
380 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
381 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
383 struct pmap kernel_pmap_store;
385 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
386 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
389 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
390 "Number of kernel page table pages allocated on bootup");
393 vm_paddr_t dmaplimit;
394 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
397 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
398 "VM/pmap parameters");
400 static int pg_ps_enabled = 1;
401 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
402 &pg_ps_enabled, 0, "Are large page mappings enabled?");
404 int __read_frequently la57 = 0;
405 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
407 "5-level paging for host is enabled");
410 pmap_is_la57(pmap_t pmap)
412 if (pmap->pm_type == PT_X86)
414 return (false); /* XXXKIB handle EPT */
417 #define PAT_INDEX_SIZE 8
418 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
420 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
421 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
422 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
423 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
424 u_int64_t KPML5phys; /* phys addr of kernel level 5,
427 static pml4_entry_t *kernel_pml4;
428 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
429 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
430 static int ndmpdpphys; /* number of DMPDPphys pages */
432 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
435 * pmap_mapdev support pre initialization (i.e. console)
437 #define PMAP_PREINIT_MAPPING_COUNT 8
438 static struct pmap_preinit_mapping {
443 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
444 static int pmap_initialized;
447 * Data for the pv entry allocation mechanism.
448 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
452 pc_to_domain(struct pv_chunk *pc)
455 return (vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
459 pc_to_domain(struct pv_chunk *pc __unused)
466 struct pv_chunks_list {
468 TAILQ_HEAD(pch, pv_chunk) pvc_list;
470 } __aligned(CACHE_LINE_SIZE);
472 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
475 struct pmap_large_md_page {
476 struct rwlock pv_lock;
477 struct md_page pv_page;
480 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
481 #define pv_dummy pv_dummy_large.pv_page
482 __read_mostly static struct pmap_large_md_page *pv_table;
483 __read_mostly vm_paddr_t pmap_last_pa;
485 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
486 static u_long pv_invl_gen[NPV_LIST_LOCKS];
487 static struct md_page *pv_table;
488 static struct md_page pv_dummy;
492 * All those kernel PT submaps that BSD is so fond of
494 pt_entry_t *CMAP1 = NULL;
496 static vm_offset_t qframe = 0;
497 static struct mtx qframe_mtx;
499 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
501 static vmem_t *large_vmem;
502 static u_int lm_ents;
503 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
504 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
506 int pmap_pcid_enabled = 1;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
508 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
509 int invpcid_works = 0;
510 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
511 "Is the invpcid instruction available ?");
513 int __read_frequently pti = 0;
514 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
516 "Page Table Isolation enabled");
517 static vm_object_t pti_obj;
518 static pml4_entry_t *pti_pml4;
519 static vm_pindex_t pti_pg_idx;
520 static bool pti_finalized;
522 struct pmap_pkru_range {
523 struct rs_el pkru_rs_el;
528 static uma_zone_t pmap_pkru_ranges_zone;
529 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
530 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
531 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
532 static void *pkru_dup_range(void *ctx, void *data);
533 static void pkru_free_range(void *ctx, void *node);
534 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
535 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
536 static void pmap_pkru_deassign_all(pmap_t pmap);
539 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
546 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
548 return (sysctl_handle_64(oidp, &res, 0, req));
550 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
551 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
552 "Count of saved TLB context on switch");
554 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
555 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
556 static struct mtx invl_gen_mtx;
557 /* Fake lock object to satisfy turnstiles interface. */
558 static struct lock_object invl_gen_ts = {
561 static struct pmap_invl_gen pmap_invl_gen_head = {
565 static u_long pmap_invl_gen = 1;
566 static int pmap_invl_waiters;
567 static struct callout pmap_invl_callout;
568 static bool pmap_invl_callout_inited;
570 #define PMAP_ASSERT_NOT_IN_DI() \
571 KASSERT(pmap_not_in_di(), ("DI already started"))
578 if ((cpu_feature2 & CPUID2_CX16) == 0)
581 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
586 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
590 locked = pmap_di_locked();
591 return (sysctl_handle_int(oidp, &locked, 0, req));
593 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
594 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
595 "Locked delayed invalidation");
597 static bool pmap_not_in_di_l(void);
598 static bool pmap_not_in_di_u(void);
599 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
602 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
606 pmap_not_in_di_l(void)
608 struct pmap_invl_gen *invl_gen;
610 invl_gen = &curthread->td_md.md_invl_gen;
611 return (invl_gen->gen == 0);
615 pmap_thread_init_invl_gen_l(struct thread *td)
617 struct pmap_invl_gen *invl_gen;
619 invl_gen = &td->td_md.md_invl_gen;
624 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
626 struct turnstile *ts;
628 ts = turnstile_trywait(&invl_gen_ts);
629 if (*m_gen > atomic_load_long(invl_gen))
630 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
632 turnstile_cancel(ts);
636 pmap_delayed_invl_finish_unblock(u_long new_gen)
638 struct turnstile *ts;
640 turnstile_chain_lock(&invl_gen_ts);
641 ts = turnstile_lookup(&invl_gen_ts);
643 pmap_invl_gen = new_gen;
645 turnstile_broadcast(ts, TS_SHARED_QUEUE);
646 turnstile_unpend(ts);
648 turnstile_chain_unlock(&invl_gen_ts);
652 * Start a new Delayed Invalidation (DI) block of code, executed by
653 * the current thread. Within a DI block, the current thread may
654 * destroy both the page table and PV list entries for a mapping and
655 * then release the corresponding PV list lock before ensuring that
656 * the mapping is flushed from the TLBs of any processors with the
660 pmap_delayed_invl_start_l(void)
662 struct pmap_invl_gen *invl_gen;
665 invl_gen = &curthread->td_md.md_invl_gen;
666 PMAP_ASSERT_NOT_IN_DI();
667 mtx_lock(&invl_gen_mtx);
668 if (LIST_EMPTY(&pmap_invl_gen_tracker))
669 currgen = pmap_invl_gen;
671 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
672 invl_gen->gen = currgen + 1;
673 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
674 mtx_unlock(&invl_gen_mtx);
678 * Finish the DI block, previously started by the current thread. All
679 * required TLB flushes for the pages marked by
680 * pmap_delayed_invl_page() must be finished before this function is
683 * This function works by bumping the global DI generation number to
684 * the generation number of the current thread's DI, unless there is a
685 * pending DI that started earlier. In the latter case, bumping the
686 * global DI generation number would incorrectly signal that the
687 * earlier DI had finished. Instead, this function bumps the earlier
688 * DI's generation number to match the generation number of the
689 * current thread's DI.
692 pmap_delayed_invl_finish_l(void)
694 struct pmap_invl_gen *invl_gen, *next;
696 invl_gen = &curthread->td_md.md_invl_gen;
697 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
698 mtx_lock(&invl_gen_mtx);
699 next = LIST_NEXT(invl_gen, link);
701 pmap_delayed_invl_finish_unblock(invl_gen->gen);
703 next->gen = invl_gen->gen;
704 LIST_REMOVE(invl_gen, link);
705 mtx_unlock(&invl_gen_mtx);
710 pmap_not_in_di_u(void)
712 struct pmap_invl_gen *invl_gen;
714 invl_gen = &curthread->td_md.md_invl_gen;
715 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
719 pmap_thread_init_invl_gen_u(struct thread *td)
721 struct pmap_invl_gen *invl_gen;
723 invl_gen = &td->td_md.md_invl_gen;
725 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
729 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
731 uint64_t new_high, new_low, old_high, old_low;
734 old_low = new_low = 0;
735 old_high = new_high = (uintptr_t)0;
737 __asm volatile("lock;cmpxchg16b\t%1"
738 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
739 : "b"(new_low), "c" (new_high)
742 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
745 out->next = (void *)old_high;
748 out->next = (void *)new_high;
754 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
755 struct pmap_invl_gen *new_val)
757 uint64_t new_high, new_low, old_high, old_low;
760 new_low = new_val->gen;
761 new_high = (uintptr_t)new_val->next;
762 old_low = old_val->gen;
763 old_high = (uintptr_t)old_val->next;
765 __asm volatile("lock;cmpxchg16b\t%1"
766 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
767 : "b"(new_low), "c" (new_high)
773 static long invl_start_restart;
774 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
775 &invl_start_restart, 0,
777 static long invl_finish_restart;
778 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
779 &invl_finish_restart, 0,
781 static int invl_max_qlen;
782 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
787 #define di_delay locks_delay
790 pmap_delayed_invl_start_u(void)
792 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
794 struct lock_delay_arg lda;
802 invl_gen = &td->td_md.md_invl_gen;
803 PMAP_ASSERT_NOT_IN_DI();
804 lock_delay_arg_init(&lda, &di_delay);
805 invl_gen->saved_pri = 0;
806 pri = td->td_base_pri;
809 pri = td->td_base_pri;
811 invl_gen->saved_pri = pri;
818 for (p = &pmap_invl_gen_head;; p = prev.next) {
820 prevl = (uintptr_t)atomic_load_ptr(&p->next);
821 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
822 PV_STAT(atomic_add_long(&invl_start_restart, 1));
828 prev.next = (void *)prevl;
831 if ((ii = invl_max_qlen) < i)
832 atomic_cmpset_int(&invl_max_qlen, ii, i);
835 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
836 PV_STAT(atomic_add_long(&invl_start_restart, 1));
841 new_prev.gen = prev.gen;
842 new_prev.next = invl_gen;
843 invl_gen->gen = prev.gen + 1;
845 /* Formal fence between store to invl->gen and updating *p. */
846 atomic_thread_fence_rel();
849 * After inserting an invl_gen element with invalid bit set,
850 * this thread blocks any other thread trying to enter the
851 * delayed invalidation block. Do not allow to remove us from
852 * the CPU, because it causes starvation for other threads.
857 * ABA for *p is not possible there, since p->gen can only
858 * increase. So if the *p thread finished its di, then
859 * started a new one and got inserted into the list at the
860 * same place, its gen will appear greater than the previously
863 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
865 PV_STAT(atomic_add_long(&invl_start_restart, 1));
871 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
872 * invl_gen->next, allowing other threads to iterate past us.
873 * pmap_di_store_invl() provides fence between the generation
874 * write and the update of next.
876 invl_gen->next = NULL;
881 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
882 struct pmap_invl_gen *p)
884 struct pmap_invl_gen prev, new_prev;
888 * Load invl_gen->gen after setting invl_gen->next
889 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
890 * generations to propagate to our invl_gen->gen. Lock prefix
891 * in atomic_set_ptr() worked as seq_cst fence.
893 mygen = atomic_load_long(&invl_gen->gen);
895 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
898 KASSERT(prev.gen < mygen,
899 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
900 new_prev.gen = mygen;
901 new_prev.next = (void *)((uintptr_t)invl_gen->next &
902 ~PMAP_INVL_GEN_NEXT_INVALID);
904 /* Formal fence between load of prev and storing update to it. */
905 atomic_thread_fence_rel();
907 return (pmap_di_store_invl(p, &prev, &new_prev));
911 pmap_delayed_invl_finish_u(void)
913 struct pmap_invl_gen *invl_gen, *p;
915 struct lock_delay_arg lda;
919 invl_gen = &td->td_md.md_invl_gen;
920 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
921 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
922 ("missed invl_start: INVALID"));
923 lock_delay_arg_init(&lda, &di_delay);
926 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
927 prevl = (uintptr_t)atomic_load_ptr(&p->next);
928 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
929 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
933 if ((void *)prevl == invl_gen)
938 * It is legitimate to not find ourself on the list if a
939 * thread before us finished its DI and started it again.
941 if (__predict_false(p == NULL)) {
942 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
948 atomic_set_ptr((uintptr_t *)&invl_gen->next,
949 PMAP_INVL_GEN_NEXT_INVALID);
950 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
951 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
952 PMAP_INVL_GEN_NEXT_INVALID);
954 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
959 if (atomic_load_int(&pmap_invl_waiters) > 0)
960 pmap_delayed_invl_finish_unblock(0);
961 if (invl_gen->saved_pri != 0) {
963 sched_prio(td, invl_gen->saved_pri);
969 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
971 struct pmap_invl_gen *p, *pn;
976 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
978 nextl = (uintptr_t)atomic_load_ptr(&p->next);
979 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
980 td = first ? NULL : __containerof(p, struct thread,
982 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
983 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
984 td != NULL ? td->td_tid : -1);
990 static long invl_wait;
991 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
992 "Number of times DI invalidation blocked pmap_remove_all/write");
993 static long invl_wait_slow;
994 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
995 "Number of slow invalidation waits for lockless DI");
1000 pmap_delayed_invl_genp(vm_page_t m)
1005 pa = VM_PAGE_TO_PHYS(m);
1006 if (__predict_false((pa) > pmap_last_pa))
1007 gen = &pv_dummy_large.pv_invl_gen;
1009 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1015 pmap_delayed_invl_genp(vm_page_t m)
1018 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1023 pmap_delayed_invl_callout_func(void *arg __unused)
1026 if (atomic_load_int(&pmap_invl_waiters) == 0)
1028 pmap_delayed_invl_finish_unblock(0);
1032 pmap_delayed_invl_callout_init(void *arg __unused)
1035 if (pmap_di_locked())
1037 callout_init(&pmap_invl_callout, 1);
1038 pmap_invl_callout_inited = true;
1040 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1041 pmap_delayed_invl_callout_init, NULL);
1044 * Ensure that all currently executing DI blocks, that need to flush
1045 * TLB for the given page m, actually flushed the TLB at the time the
1046 * function returned. If the page m has an empty PV list and we call
1047 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1048 * valid mapping for the page m in either its page table or TLB.
1050 * This function works by blocking until the global DI generation
1051 * number catches up with the generation number associated with the
1052 * given page m and its PV list. Since this function's callers
1053 * typically own an object lock and sometimes own a page lock, it
1054 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1058 pmap_delayed_invl_wait_l(vm_page_t m)
1062 bool accounted = false;
1065 m_gen = pmap_delayed_invl_genp(m);
1066 while (*m_gen > pmap_invl_gen) {
1069 atomic_add_long(&invl_wait, 1);
1073 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1078 pmap_delayed_invl_wait_u(vm_page_t m)
1081 struct lock_delay_arg lda;
1085 m_gen = pmap_delayed_invl_genp(m);
1086 lock_delay_arg_init(&lda, &di_delay);
1087 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1088 if (fast || !pmap_invl_callout_inited) {
1089 PV_STAT(atomic_add_long(&invl_wait, 1));
1094 * The page's invalidation generation number
1095 * is still below the current thread's number.
1096 * Prepare to block so that we do not waste
1097 * CPU cycles or worse, suffer livelock.
1099 * Since it is impossible to block without
1100 * racing with pmap_delayed_invl_finish_u(),
1101 * prepare for the race by incrementing
1102 * pmap_invl_waiters and arming a 1-tick
1103 * callout which will unblock us if we lose
1106 atomic_add_int(&pmap_invl_waiters, 1);
1109 * Re-check the current thread's invalidation
1110 * generation after incrementing
1111 * pmap_invl_waiters, so that there is no race
1112 * with pmap_delayed_invl_finish_u() setting
1113 * the page generation and checking
1114 * pmap_invl_waiters. The only race allowed
1115 * is for a missed unblock, which is handled
1119 atomic_load_long(&pmap_invl_gen_head.gen)) {
1120 callout_reset(&pmap_invl_callout, 1,
1121 pmap_delayed_invl_callout_func, NULL);
1122 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1123 pmap_delayed_invl_wait_block(m_gen,
1124 &pmap_invl_gen_head.gen);
1126 atomic_add_int(&pmap_invl_waiters, -1);
1131 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1134 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1135 pmap_thread_init_invl_gen_u);
1138 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1141 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1142 pmap_delayed_invl_start_u);
1145 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1148 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1149 pmap_delayed_invl_finish_u);
1152 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1155 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1156 pmap_delayed_invl_wait_u);
1160 * Mark the page m's PV list as participating in the current thread's
1161 * DI block. Any threads concurrently using m's PV list to remove or
1162 * restrict all mappings to m will wait for the current thread's DI
1163 * block to complete before proceeding.
1165 * The function works by setting the DI generation number for m's PV
1166 * list to at least the DI generation number of the current thread.
1167 * This forces a caller of pmap_delayed_invl_wait() to block until
1168 * current thread calls pmap_delayed_invl_finish().
1171 pmap_delayed_invl_page(vm_page_t m)
1175 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1176 gen = curthread->td_md.md_invl_gen.gen;
1179 m_gen = pmap_delayed_invl_genp(m);
1187 static caddr_t crashdumpmap;
1190 * Internal flags for pmap_enter()'s helper functions.
1192 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1193 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1196 * Internal flags for pmap_mapdev_internal() and
1197 * pmap_change_props_locked().
1199 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1200 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1201 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1203 TAILQ_HEAD(pv_chunklist, pv_chunk);
1205 static void free_pv_chunk(struct pv_chunk *pc);
1206 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1207 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1208 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1209 static int popcnt_pc_map_pq(uint64_t *map);
1210 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1211 static void reserve_pv_entries(pmap_t pmap, int needed,
1212 struct rwlock **lockp);
1213 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1214 struct rwlock **lockp);
1215 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1216 u_int flags, struct rwlock **lockp);
1217 #if VM_NRESERVLEVEL > 0
1218 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1219 struct rwlock **lockp);
1221 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1222 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1225 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1226 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1227 vm_prot_t prot, int mode, int flags);
1228 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1229 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1230 vm_offset_t va, struct rwlock **lockp);
1231 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1233 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1234 vm_prot_t prot, struct rwlock **lockp);
1235 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1236 u_int flags, vm_page_t m, struct rwlock **lockp);
1237 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1238 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1239 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1240 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1241 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1243 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1245 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1247 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1248 static vm_page_t pmap_large_map_getptp_unlocked(void);
1249 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1250 #if VM_NRESERVLEVEL > 0
1251 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1252 struct rwlock **lockp);
1254 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1256 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1257 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1259 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1260 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1261 static void pmap_pti_wire_pte(void *pte);
1262 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1263 struct spglist *free, struct rwlock **lockp);
1264 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1265 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1266 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1267 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1268 struct spglist *free);
1269 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1270 pd_entry_t *pde, struct spglist *free,
1271 struct rwlock **lockp);
1272 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1273 vm_page_t m, struct rwlock **lockp);
1274 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1276 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1278 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1279 struct rwlock **lockp, vm_offset_t va);
1280 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1281 struct rwlock **lockp);
1282 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1283 struct rwlock **lockp);
1285 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1286 struct spglist *free);
1287 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1289 /********************/
1290 /* Inline functions */
1291 /********************/
1294 * Return a non-clipped indexes for a given VA, which are page table
1295 * pages indexes at the corresponding level.
1297 static __inline vm_pindex_t
1298 pmap_pde_pindex(vm_offset_t va)
1300 return (va >> PDRSHIFT);
1303 static __inline vm_pindex_t
1304 pmap_pdpe_pindex(vm_offset_t va)
1306 return (NUPDE + (va >> PDPSHIFT));
1309 static __inline vm_pindex_t
1310 pmap_pml4e_pindex(vm_offset_t va)
1312 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1315 static __inline vm_pindex_t
1316 pmap_pml5e_pindex(vm_offset_t va)
1318 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1321 static __inline pml4_entry_t *
1322 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1325 MPASS(pmap_is_la57(pmap));
1326 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1329 static __inline pml4_entry_t *
1330 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1333 MPASS(pmap_is_la57(pmap));
1334 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1337 static __inline pml4_entry_t *
1338 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1340 pml4_entry_t *pml4e;
1342 /* XXX MPASS(pmap_is_la57(pmap); */
1343 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1344 return (&pml4e[pmap_pml4e_index(va)]);
1347 /* Return a pointer to the PML4 slot that corresponds to a VA */
1348 static __inline pml4_entry_t *
1349 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1351 pml5_entry_t *pml5e;
1352 pml4_entry_t *pml4e;
1355 if (pmap_is_la57(pmap)) {
1356 pml5e = pmap_pml5e(pmap, va);
1357 PG_V = pmap_valid_bit(pmap);
1358 if ((*pml5e & PG_V) == 0)
1360 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1362 pml4e = pmap->pm_pmltop;
1364 return (&pml4e[pmap_pml4e_index(va)]);
1367 static __inline pml4_entry_t *
1368 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1370 MPASS(!pmap_is_la57(pmap));
1371 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1374 /* Return a pointer to the PDP slot that corresponds to a VA */
1375 static __inline pdp_entry_t *
1376 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1380 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1381 return (&pdpe[pmap_pdpe_index(va)]);
1384 /* Return a pointer to the PDP slot that corresponds to a VA */
1385 static __inline pdp_entry_t *
1386 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1388 pml4_entry_t *pml4e;
1391 PG_V = pmap_valid_bit(pmap);
1392 pml4e = pmap_pml4e(pmap, va);
1393 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1395 return (pmap_pml4e_to_pdpe(pml4e, va));
1398 /* Return a pointer to the PD slot that corresponds to a VA */
1399 static __inline pd_entry_t *
1400 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1404 KASSERT((*pdpe & PG_PS) == 0,
1405 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1406 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1407 return (&pde[pmap_pde_index(va)]);
1410 /* Return a pointer to the PD slot that corresponds to a VA */
1411 static __inline pd_entry_t *
1412 pmap_pde(pmap_t pmap, vm_offset_t va)
1417 PG_V = pmap_valid_bit(pmap);
1418 pdpe = pmap_pdpe(pmap, va);
1419 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1421 KASSERT((*pdpe & PG_PS) == 0,
1422 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1423 return (pmap_pdpe_to_pde(pdpe, va));
1426 /* Return a pointer to the PT slot that corresponds to a VA */
1427 static __inline pt_entry_t *
1428 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1432 KASSERT((*pde & PG_PS) == 0,
1433 ("%s: pde %#lx is a leaf", __func__, *pde));
1434 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1435 return (&pte[pmap_pte_index(va)]);
1438 /* Return a pointer to the PT slot that corresponds to a VA */
1439 static __inline pt_entry_t *
1440 pmap_pte(pmap_t pmap, vm_offset_t va)
1445 PG_V = pmap_valid_bit(pmap);
1446 pde = pmap_pde(pmap, va);
1447 if (pde == NULL || (*pde & PG_V) == 0)
1449 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1450 return ((pt_entry_t *)pde);
1451 return (pmap_pde_to_pte(pde, va));
1454 static __inline void
1455 pmap_resident_count_inc(pmap_t pmap, int count)
1458 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1459 pmap->pm_stats.resident_count += count;
1462 static __inline void
1463 pmap_resident_count_dec(pmap_t pmap, int count)
1466 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1467 KASSERT(pmap->pm_stats.resident_count >= count,
1468 ("pmap %p resident count underflow %ld %d", pmap,
1469 pmap->pm_stats.resident_count, count));
1470 pmap->pm_stats.resident_count -= count;
1473 PMAP_INLINE pt_entry_t *
1474 vtopte(vm_offset_t va)
1478 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1481 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1482 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1483 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1485 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1486 NPML4EPGSHIFT)) - 1);
1487 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1491 static __inline pd_entry_t *
1492 vtopde(vm_offset_t va)
1496 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1499 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1500 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1501 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1503 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1504 NPML4EPGSHIFT)) - 1);
1505 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1510 allocpages(vm_paddr_t *firstaddr, int n)
1515 bzero((void *)ret, n * PAGE_SIZE);
1516 *firstaddr += n * PAGE_SIZE;
1520 CTASSERT(powerof2(NDMPML4E));
1522 /* number of kernel PDP slots */
1523 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1526 nkpt_init(vm_paddr_t addr)
1533 pt_pages = howmany(addr, 1 << PDRSHIFT);
1534 pt_pages += NKPDPE(pt_pages);
1537 * Add some slop beyond the bare minimum required for bootstrapping
1540 * This is quite important when allocating KVA for kernel modules.
1541 * The modules are required to be linked in the negative 2GB of
1542 * the address space. If we run out of KVA in this region then
1543 * pmap_growkernel() will need to allocate page table pages to map
1544 * the entire 512GB of KVA space which is an unnecessary tax on
1547 * Secondly, device memory mapped as part of setting up the low-
1548 * level console(s) is taken from KVA, starting at virtual_avail.
1549 * This is because cninit() is called after pmap_bootstrap() but
1550 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1553 pt_pages += 32; /* 64MB additional slop. */
1559 * Returns the proper write/execute permission for a physical page that is
1560 * part of the initial boot allocations.
1562 * If the page has kernel text, it is marked as read-only. If the page has
1563 * kernel read-only data, it is marked as read-only/not-executable. If the
1564 * page has only read-write data, it is marked as read-write/not-executable.
1565 * If the page is below/above the kernel range, it is marked as read-write.
1567 * This function operates on 2M pages, since we map the kernel space that
1570 static inline pt_entry_t
1571 bootaddr_rwx(vm_paddr_t pa)
1575 * The kernel is loaded at a 2MB-aligned address, and memory below that
1576 * need not be executable. The .bss section is padded to a 2MB
1577 * boundary, so memory following the kernel need not be executable
1578 * either. Preloaded kernel modules have their mapping permissions
1579 * fixed up by the linker.
1581 if (pa < trunc_2mpage(btext - KERNBASE) ||
1582 pa >= trunc_2mpage(_end - KERNBASE))
1583 return (X86_PG_RW | pg_nx);
1586 * The linker should ensure that the read-only and read-write
1587 * portions don't share the same 2M page, so this shouldn't
1588 * impact read-only data. However, in any case, any page with
1589 * read-write data needs to be read-write.
1591 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1592 return (X86_PG_RW | pg_nx);
1595 * Mark any 2M page containing kernel text as read-only. Mark
1596 * other pages with read-only data as read-only and not executable.
1597 * (It is likely a small portion of the read-only data section will
1598 * be marked as read-only, but executable. This should be acceptable
1599 * since the read-only protection will keep the data from changing.)
1600 * Note that fixups to the .text section will still work until we
1603 if (pa < round_2mpage(etext - KERNBASE))
1609 create_pagetables(vm_paddr_t *firstaddr)
1611 int i, j, ndm1g, nkpdpe, nkdmpde;
1615 uint64_t DMPDkernphys;
1617 /* Allocate page table pages for the direct map */
1618 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1619 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1621 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1622 if (ndmpdpphys > NDMPML4E) {
1624 * Each NDMPML4E allows 512 GB, so limit to that,
1625 * and then readjust ndmpdp and ndmpdpphys.
1627 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1628 Maxmem = atop(NDMPML4E * NBPML4);
1629 ndmpdpphys = NDMPML4E;
1630 ndmpdp = NDMPML4E * NPDEPG;
1632 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1634 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1636 * Calculate the number of 1G pages that will fully fit in
1639 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1642 * Allocate 2M pages for the kernel. These will be used in
1643 * place of the first one or more 1G pages from ndm1g.
1645 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1646 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1649 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1650 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1652 /* Allocate pages */
1653 KPML4phys = allocpages(firstaddr, 1);
1654 KPDPphys = allocpages(firstaddr, NKPML4E);
1657 * Allocate the initial number of kernel page table pages required to
1658 * bootstrap. We defer this until after all memory-size dependent
1659 * allocations are done (e.g. direct map), so that we don't have to
1660 * build in too much slop in our estimate.
1662 * Note that when NKPML4E > 1, we have an empty page underneath
1663 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1664 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1666 nkpt_init(*firstaddr);
1667 nkpdpe = NKPDPE(nkpt);
1669 KPTphys = allocpages(firstaddr, nkpt);
1670 KPDphys = allocpages(firstaddr, nkpdpe);
1673 * Connect the zero-filled PT pages to their PD entries. This
1674 * implicitly maps the PT pages at their correct locations within
1677 pd_p = (pd_entry_t *)KPDphys;
1678 for (i = 0; i < nkpt; i++)
1679 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1682 * Map from physical address zero to the end of loader preallocated
1683 * memory using 2MB pages. This replaces some of the PD entries
1686 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1687 /* Preset PG_M and PG_A because demotion expects it. */
1688 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1689 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1692 * Because we map the physical blocks in 2M pages, adjust firstaddr
1693 * to record the physical blocks we've actually mapped into kernel
1694 * virtual address space.
1696 if (*firstaddr < round_2mpage(KERNend))
1697 *firstaddr = round_2mpage(KERNend);
1699 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1700 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1701 for (i = 0; i < nkpdpe; i++)
1702 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1705 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1706 * the end of physical memory is not aligned to a 1GB page boundary,
1707 * then the residual physical memory is mapped with 2MB pages. Later,
1708 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1709 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1710 * that are partially used.
1712 pd_p = (pd_entry_t *)DMPDphys;
1713 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1714 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1715 /* Preset PG_M and PG_A because demotion expects it. */
1716 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1717 X86_PG_M | X86_PG_A | pg_nx;
1719 pdp_p = (pdp_entry_t *)DMPDPphys;
1720 for (i = 0; i < ndm1g; i++) {
1721 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1722 /* Preset PG_M and PG_A because demotion expects it. */
1723 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1724 X86_PG_M | X86_PG_A | pg_nx;
1726 for (j = 0; i < ndmpdp; i++, j++) {
1727 pdp_p[i] = DMPDphys + ptoa(j);
1728 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1732 * Instead of using a 1G page for the memory containing the kernel,
1733 * use 2M pages with read-only and no-execute permissions. (If using 1G
1734 * pages, this will partially overwrite the PDPEs above.)
1737 pd_p = (pd_entry_t *)DMPDkernphys;
1738 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1739 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1740 X86_PG_M | X86_PG_A | pg_nx |
1741 bootaddr_rwx(i << PDRSHIFT);
1742 for (i = 0; i < nkdmpde; i++)
1743 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1747 /* And recursively map PML4 to itself in order to get PTmap */
1748 p4_p = (pml4_entry_t *)KPML4phys;
1749 p4_p[PML4PML4I] = KPML4phys;
1750 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1752 /* Connect the Direct Map slot(s) up to the PML4. */
1753 for (i = 0; i < ndmpdpphys; i++) {
1754 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1755 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1758 /* Connect the KVA slots up to the PML4 */
1759 for (i = 0; i < NKPML4E; i++) {
1760 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1761 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1764 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1768 * Bootstrap the system enough to run with virtual memory.
1770 * On amd64 this is called after mapping has already been enabled
1771 * and just syncs the pmap module with what has already been done.
1772 * [We can't call it easily with mapping off since the kernel is not
1773 * mapped with PA == VA, hence we would have to relocate every address
1774 * from the linked base (virtual) address "KERNBASE" to the actual
1775 * (physical) address starting relative to 0]
1778 pmap_bootstrap(vm_paddr_t *firstaddr)
1781 pt_entry_t *pte, *pcpu_pte;
1782 struct region_descriptor r_gdt;
1783 uint64_t cr4, pcpu_phys;
1787 KERNend = *firstaddr;
1788 res = atop(KERNend - (vm_paddr_t)kernphys);
1794 * Create an initial set of page tables to run the kernel in.
1796 create_pagetables(firstaddr);
1798 pcpu_phys = allocpages(firstaddr, MAXCPU);
1801 * Add a physical memory segment (vm_phys_seg) corresponding to the
1802 * preallocated kernel page table pages so that vm_page structures
1803 * representing these pages will be created. The vm_page structures
1804 * are required for promotion of the corresponding kernel virtual
1805 * addresses to superpage mappings.
1807 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1810 * Account for the virtual addresses mapped by create_pagetables().
1812 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1813 virtual_end = VM_MAX_KERNEL_ADDRESS;
1816 * Enable PG_G global pages, then switch to the kernel page
1817 * table from the bootstrap page table. After the switch, it
1818 * is possible to enable SMEP and SMAP since PG_U bits are
1824 load_cr3(KPML4phys);
1825 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1827 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1832 * Initialize the kernel pmap (which is statically allocated).
1833 * Count bootstrap data as being resident in case any of this data is
1834 * later unmapped (using pmap_remove()) and freed.
1836 PMAP_LOCK_INIT(kernel_pmap);
1837 kernel_pmap->pm_pmltop = kernel_pml4;
1838 kernel_pmap->pm_cr3 = KPML4phys;
1839 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1840 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1841 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1842 kernel_pmap->pm_stats.resident_count = res;
1843 kernel_pmap->pm_flags = pmap_flags;
1846 * Initialize the TLB invalidations generation number lock.
1848 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1851 * Reserve some special page table entries/VA space for temporary
1854 #define SYSMAP(c, p, v, n) \
1855 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1861 * Crashdump maps. The first page is reused as CMAP1 for the
1864 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1865 CADDR1 = crashdumpmap;
1867 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1870 for (i = 0; i < MAXCPU; i++) {
1871 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1872 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1876 * Re-initialize PCPU area for BSP after switching.
1877 * Make hardware use gdt and common_tss from the new PCPU.
1879 STAILQ_INIT(&cpuhead);
1880 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1881 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1882 amd64_bsp_pcpu_init1(&__pcpu[0]);
1883 amd64_bsp_ist_init(&__pcpu[0]);
1884 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1886 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1887 sizeof(struct user_segment_descriptor));
1888 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1889 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1890 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1891 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1892 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1894 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1895 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1896 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1897 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1900 * Initialize the PAT MSR.
1901 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1902 * side-effect, invalidates stale PG_G TLB entries that might
1903 * have been created in our pre-boot environment.
1907 /* Initialize TLB Context Id. */
1908 if (pmap_pcid_enabled) {
1909 for (i = 0; i < MAXCPU; i++) {
1910 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1911 kernel_pmap->pm_pcids[i].pm_gen = 1;
1915 * PMAP_PCID_KERN + 1 is used for initialization of
1916 * proc0 pmap. The pmap' pcid state might be used by
1917 * EFIRT entry before first context switch, so it
1918 * needs to be valid.
1920 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1921 PCPU_SET(pcid_gen, 1);
1924 * pcpu area for APs is zeroed during AP startup.
1925 * pc_pcid_next and pc_pcid_gen are initialized by AP
1926 * during pcpu setup.
1928 load_cr4(rcr4() | CR4_PCIDE);
1933 * Setup the PAT MSR.
1942 /* Bail if this CPU doesn't implement PAT. */
1943 if ((cpu_feature & CPUID_PAT) == 0)
1946 /* Set default PAT index table. */
1947 for (i = 0; i < PAT_INDEX_SIZE; i++)
1949 pat_index[PAT_WRITE_BACK] = 0;
1950 pat_index[PAT_WRITE_THROUGH] = 1;
1951 pat_index[PAT_UNCACHEABLE] = 3;
1952 pat_index[PAT_WRITE_COMBINING] = 6;
1953 pat_index[PAT_WRITE_PROTECTED] = 5;
1954 pat_index[PAT_UNCACHED] = 2;
1957 * Initialize default PAT entries.
1958 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1959 * Program 5 and 6 as WP and WC.
1961 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1962 * mapping for a 2M page uses a PAT value with the bit 3 set due
1963 * to its overload with PG_PS.
1965 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1966 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1967 PAT_VALUE(2, PAT_UNCACHED) |
1968 PAT_VALUE(3, PAT_UNCACHEABLE) |
1969 PAT_VALUE(4, PAT_WRITE_BACK) |
1970 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1971 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1972 PAT_VALUE(7, PAT_UNCACHEABLE);
1976 load_cr4(cr4 & ~CR4_PGE);
1978 /* Disable caches (CD = 1, NW = 0). */
1980 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1982 /* Flushes caches and TLBs. */
1986 /* Update PAT and index table. */
1987 wrmsr(MSR_PAT, pat_msr);
1989 /* Flush caches and TLBs again. */
1993 /* Restore caches and PGE. */
1998 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1999 la57_trampoline_gdt[], la57_trampoline_end[];
2002 pmap_bootstrap_la57(void *arg __unused)
2005 pml5_entry_t *v_pml5;
2006 pml4_entry_t *v_pml4;
2010 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2011 void (*la57_tramp)(uint64_t pml5);
2012 struct region_descriptor r_gdt;
2014 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2016 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2021 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2022 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2024 m_code = vm_page_alloc_contig(NULL, 0,
2025 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2026 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2027 if ((m_code->flags & PG_ZERO) == 0)
2028 pmap_zero_page(m_code);
2029 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2030 m_pml5 = vm_page_alloc_contig(NULL, 0,
2031 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2032 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2033 if ((m_pml5->flags & PG_ZERO) == 0)
2034 pmap_zero_page(m_pml5);
2035 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2036 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2037 m_pml4 = vm_page_alloc_contig(NULL, 0,
2038 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2039 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2040 if ((m_pml4->flags & PG_ZERO) == 0)
2041 pmap_zero_page(m_pml4);
2042 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2043 m_pdp = vm_page_alloc_contig(NULL, 0,
2044 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2045 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2046 if ((m_pdp->flags & PG_ZERO) == 0)
2047 pmap_zero_page(m_pdp);
2048 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2049 m_pd = vm_page_alloc_contig(NULL, 0,
2050 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2051 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2052 if ((m_pd->flags & PG_ZERO) == 0)
2053 pmap_zero_page(m_pd);
2054 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2055 m_pt = vm_page_alloc_contig(NULL, 0,
2056 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2057 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2058 if ((m_pt->flags & PG_ZERO) == 0)
2059 pmap_zero_page(m_pt);
2060 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2063 * Map m_code 1:1, it appears below 4G in KVA due to physical
2064 * address being below 4G. Since kernel KVA is in upper half,
2065 * the pml4e should be zero and free for temporary use.
2067 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2068 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2070 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2071 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2073 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2074 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2076 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2077 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2081 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2082 * entering all existing kernel mappings into level 5 table.
2084 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2085 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2088 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2090 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2091 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2093 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2094 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2098 * Copy and call the 48->57 trampoline, hope we return there, alive.
2100 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2101 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2102 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2103 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2104 la57_tramp(KPML5phys);
2107 * gdt was necessary reset, switch back to our gdt.
2110 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2114 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2115 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2116 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2119 * Now unmap the trampoline, and free the pages.
2120 * Clear pml5 entry used for 1:1 trampoline mapping.
2122 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2123 invlpg((vm_offset_t)v_code);
2124 vm_page_free(m_code);
2125 vm_page_free(m_pdp);
2130 * Recursively map PML5 to itself in order to get PTmap and
2133 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2135 kernel_pmap->pm_cr3 = KPML5phys;
2136 kernel_pmap->pm_pmltop = v_pml5;
2138 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2141 * Initialize a vm_page's machine-dependent fields.
2144 pmap_page_init(vm_page_t m)
2147 TAILQ_INIT(&m->md.pv_list);
2148 m->md.pat_mode = PAT_WRITE_BACK;
2151 static int pmap_allow_2m_x_ept;
2152 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2153 &pmap_allow_2m_x_ept, 0,
2154 "Allow executable superpage mappings in EPT");
2157 pmap_allow_2m_x_ept_recalculate(void)
2160 * SKL002, SKL012S. Since the EPT format is only used by
2161 * Intel CPUs, the vendor check is merely a formality.
2163 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2164 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2165 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2166 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2167 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2168 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2169 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2170 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2171 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2172 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2173 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2174 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2175 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2176 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2177 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2178 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2179 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2180 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2181 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2182 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2183 CPUID_TO_MODEL(cpu_id) == 0x85))))
2184 pmap_allow_2m_x_ept = 1;
2185 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2189 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2192 return (pmap->pm_type != PT_EPT || !executable ||
2193 !pmap_allow_2m_x_ept);
2198 pmap_init_pv_table(void)
2200 struct pmap_large_md_page *pvd;
2202 long start, end, highest, pv_npg;
2203 int domain, i, j, pages;
2206 * We strongly depend on the size being a power of two, so the assert
2207 * is overzealous. However, should the struct be resized to a
2208 * different power of two, the code below needs to be revisited.
2210 CTASSERT((sizeof(*pvd) == 64));
2213 * Calculate the size of the array.
2215 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2216 pv_npg = howmany(pmap_last_pa, NBPDR);
2217 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2219 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2220 if (pv_table == NULL)
2221 panic("%s: kva_alloc failed\n", __func__);
2224 * Iterate physical segments to allocate space for respective pages.
2228 for (i = 0; i < vm_phys_nsegs; i++) {
2229 end = vm_phys_segs[i].end / NBPDR;
2230 domain = vm_phys_segs[i].domain;
2235 start = highest + 1;
2236 pvd = &pv_table[start];
2238 pages = end - start + 1;
2239 s = round_page(pages * sizeof(*pvd));
2240 highest = start + (s / sizeof(*pvd)) - 1;
2242 for (j = 0; j < s; j += PAGE_SIZE) {
2243 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2244 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2246 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2247 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2250 for (j = 0; j < s / sizeof(*pvd); j++) {
2251 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2252 TAILQ_INIT(&pvd->pv_page.pv_list);
2253 pvd->pv_page.pv_gen = 0;
2254 pvd->pv_page.pat_mode = 0;
2255 pvd->pv_invl_gen = 0;
2259 pvd = &pv_dummy_large;
2260 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2261 TAILQ_INIT(&pvd->pv_page.pv_list);
2262 pvd->pv_page.pv_gen = 0;
2263 pvd->pv_page.pat_mode = 0;
2264 pvd->pv_invl_gen = 0;
2268 pmap_init_pv_table(void)
2274 * Initialize the pool of pv list locks.
2276 for (i = 0; i < NPV_LIST_LOCKS; i++)
2277 rw_init(&pv_list_locks[i], "pmap pv list");
2280 * Calculate the size of the pv head table for superpages.
2282 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2285 * Allocate memory for the pv head table for superpages.
2287 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2289 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2290 for (i = 0; i < pv_npg; i++)
2291 TAILQ_INIT(&pv_table[i].pv_list);
2292 TAILQ_INIT(&pv_dummy.pv_list);
2297 * Initialize the pmap module.
2298 * Called by vm_init, to initialize any structures that the pmap
2299 * system needs to map virtual memory.
2304 struct pmap_preinit_mapping *ppim;
2306 int error, i, ret, skz63;
2308 /* L1TF, reserve page @0 unconditionally */
2309 vm_page_blacklist_add(0, bootverbose);
2311 /* Detect bare-metal Skylake Server and Skylake-X. */
2312 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2313 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2315 * Skylake-X errata SKZ63. Processor May Hang When
2316 * Executing Code In an HLE Transaction Region between
2317 * 40000000H and 403FFFFFH.
2319 * Mark the pages in the range as preallocated. It
2320 * seems to be impossible to distinguish between
2321 * Skylake Server and Skylake X.
2324 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2327 printf("SKZ63: skipping 4M RAM starting "
2328 "at physical 1G\n");
2329 for (i = 0; i < atop(0x400000); i++) {
2330 ret = vm_page_blacklist_add(0x40000000 +
2332 if (!ret && bootverbose)
2333 printf("page at %#lx already used\n",
2334 0x40000000 + ptoa(i));
2340 pmap_allow_2m_x_ept_recalculate();
2343 * Initialize the vm page array entries for the kernel pmap's
2346 PMAP_LOCK(kernel_pmap);
2347 for (i = 0; i < nkpt; i++) {
2348 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2349 KASSERT(mpte >= vm_page_array &&
2350 mpte < &vm_page_array[vm_page_array_size],
2351 ("pmap_init: page table page is out of range"));
2352 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2353 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2354 mpte->ref_count = 1;
2357 * Collect the page table pages that were replaced by a 2MB
2358 * page in create_pagetables(). They are zero filled.
2360 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2361 pmap_insert_pt_page(kernel_pmap, mpte, false))
2362 panic("pmap_init: pmap_insert_pt_page failed");
2364 PMAP_UNLOCK(kernel_pmap);
2368 * If the kernel is running on a virtual machine, then it must assume
2369 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2370 * be prepared for the hypervisor changing the vendor and family that
2371 * are reported by CPUID. Consequently, the workaround for AMD Family
2372 * 10h Erratum 383 is enabled if the processor's feature set does not
2373 * include at least one feature that is only supported by older Intel
2374 * or newer AMD processors.
2376 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2377 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2378 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2380 workaround_erratum383 = 1;
2383 * Are large page mappings enabled?
2385 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2386 if (pg_ps_enabled) {
2387 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2388 ("pmap_init: can't assign to pagesizes[1]"));
2389 pagesizes[1] = NBPDR;
2390 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2391 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2392 ("pmap_init: can't assign to pagesizes[2]"));
2393 pagesizes[2] = NBPDP;
2398 * Initialize pv chunk lists.
2400 for (i = 0; i < PMAP_MEMDOM; i++) {
2401 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2402 TAILQ_INIT(&pv_chunks[i].pvc_list);
2404 pmap_init_pv_table();
2406 pmap_initialized = 1;
2407 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2408 ppim = pmap_preinit_mapping + i;
2411 /* Make the direct map consistent */
2412 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2413 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2414 ppim->sz, ppim->mode);
2418 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2419 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2422 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2423 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2424 (vmem_addr_t *)&qframe);
2426 panic("qframe allocation failed");
2429 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2430 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2431 lm_ents = LMEPML4I - LMSPML4I + 1;
2433 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2434 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2436 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2437 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2438 if (large_vmem == NULL) {
2439 printf("pmap: cannot create large map\n");
2442 for (i = 0; i < lm_ents; i++) {
2443 m = pmap_large_map_getptp_unlocked();
2445 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2446 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2452 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2453 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2454 "Maximum number of PML4 entries for use by large map (tunable). "
2455 "Each entry corresponds to 512GB of address space.");
2457 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2458 "2MB page mapping counters");
2460 static u_long pmap_pde_demotions;
2461 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2462 &pmap_pde_demotions, 0, "2MB page demotions");
2464 static u_long pmap_pde_mappings;
2465 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2466 &pmap_pde_mappings, 0, "2MB page mappings");
2468 static u_long pmap_pde_p_failures;
2469 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2470 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2472 static u_long pmap_pde_promotions;
2473 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2474 &pmap_pde_promotions, 0, "2MB page promotions");
2476 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2477 "1GB page mapping counters");
2479 static u_long pmap_pdpe_demotions;
2480 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2481 &pmap_pdpe_demotions, 0, "1GB page demotions");
2483 /***************************************************
2484 * Low level helper routines.....
2485 ***************************************************/
2488 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2490 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2492 switch (pmap->pm_type) {
2495 /* Verify that both PAT bits are not set at the same time */
2496 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2497 ("Invalid PAT bits in entry %#lx", entry));
2499 /* Swap the PAT bits if one of them is set */
2500 if ((entry & x86_pat_bits) != 0)
2501 entry ^= x86_pat_bits;
2505 * Nothing to do - the memory attributes are represented
2506 * the same way for regular pages and superpages.
2510 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2517 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2520 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2521 pat_index[(int)mode] >= 0);
2525 * Determine the appropriate bits to set in a PTE or PDE for a specified
2529 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2531 int cache_bits, pat_flag, pat_idx;
2533 if (!pmap_is_valid_memattr(pmap, mode))
2534 panic("Unknown caching mode %d\n", mode);
2536 switch (pmap->pm_type) {
2539 /* The PAT bit is different for PTE's and PDE's. */
2540 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2542 /* Map the caching mode to a PAT index. */
2543 pat_idx = pat_index[mode];
2545 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2548 cache_bits |= pat_flag;
2550 cache_bits |= PG_NC_PCD;
2552 cache_bits |= PG_NC_PWT;
2556 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2560 panic("unsupported pmap type %d", pmap->pm_type);
2563 return (cache_bits);
2567 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2571 switch (pmap->pm_type) {
2574 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2577 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2580 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2587 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2589 int pat_flag, pat_idx;
2592 switch (pmap->pm_type) {
2595 /* The PAT bit is different for PTE's and PDE's. */
2596 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2598 if ((pte & pat_flag) != 0)
2600 if ((pte & PG_NC_PCD) != 0)
2602 if ((pte & PG_NC_PWT) != 0)
2606 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2607 panic("EPT PTE %#lx has no PAT memory type", pte);
2608 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2612 /* See pmap_init_pat(). */
2622 pmap_ps_enabled(pmap_t pmap)
2625 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2629 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2632 switch (pmap->pm_type) {
2639 * This is a little bogus since the generation number is
2640 * supposed to be bumped up when a region of the address
2641 * space is invalidated in the page tables.
2643 * In this case the old PDE entry is valid but yet we want
2644 * to make sure that any mappings using the old entry are
2645 * invalidated in the TLB.
2647 * The reason this works as expected is because we rendezvous
2648 * "all" host cpus and force any vcpu context to exit as a
2651 atomic_add_long(&pmap->pm_eptgen, 1);
2654 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2656 pde_store(pde, newpde);
2660 * After changing the page size for the specified virtual address in the page
2661 * table, flush the corresponding entries from the processor's TLB. Only the
2662 * calling processor's TLB is affected.
2664 * The calling thread must be pinned to a processor.
2667 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2671 if (pmap_type_guest(pmap))
2674 KASSERT(pmap->pm_type == PT_X86,
2675 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2677 PG_G = pmap_global_bit(pmap);
2679 if ((newpde & PG_PS) == 0)
2680 /* Demotion: flush a specific 2MB page mapping. */
2682 else if ((newpde & PG_G) == 0)
2684 * Promotion: flush every 4KB page mapping from the TLB
2685 * because there are too many to flush individually.
2690 * Promotion: flush every 4KB page mapping from the TLB,
2691 * including any global (PG_G) mappings.
2699 * For SMP, these functions have to use the IPI mechanism for coherence.
2701 * N.B.: Before calling any of the following TLB invalidation functions,
2702 * the calling processor must ensure that all stores updating a non-
2703 * kernel page table are globally performed. Otherwise, another
2704 * processor could cache an old, pre-update entry without being
2705 * invalidated. This can happen one of two ways: (1) The pmap becomes
2706 * active on another processor after its pm_active field is checked by
2707 * one of the following functions but before a store updating the page
2708 * table is globally performed. (2) The pmap becomes active on another
2709 * processor before its pm_active field is checked but due to
2710 * speculative loads one of the following functions stills reads the
2711 * pmap as inactive on the other processor.
2713 * The kernel page table is exempt because its pm_active field is
2714 * immutable. The kernel page table is always active on every
2719 * Interrupt the cpus that are executing in the guest context.
2720 * This will force the vcpu to exit and the cached EPT mappings
2721 * will be invalidated by the host before the next vmresume.
2723 static __inline void
2724 pmap_invalidate_ept(pmap_t pmap)
2730 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2731 ("pmap_invalidate_ept: absurd pm_active"));
2734 * The TLB mappings associated with a vcpu context are not
2735 * flushed each time a different vcpu is chosen to execute.
2737 * This is in contrast with a process's vtop mappings that
2738 * are flushed from the TLB on each context switch.
2740 * Therefore we need to do more than just a TLB shootdown on
2741 * the active cpus in 'pmap->pm_active'. To do this we keep
2742 * track of the number of invalidations performed on this pmap.
2744 * Each vcpu keeps a cache of this counter and compares it
2745 * just before a vmresume. If the counter is out-of-date an
2746 * invept will be done to flush stale mappings from the TLB.
2748 * To ensure that all vCPU threads have observed the new counter
2749 * value before returning, we use SMR. Ordering is important here:
2750 * the VMM enters an SMR read section before loading the counter
2751 * and after updating the pm_active bit set. Thus, pm_active is
2752 * a superset of active readers, and any reader that has observed
2753 * the goal has observed the new counter value.
2755 atomic_add_long(&pmap->pm_eptgen, 1);
2757 goal = smr_advance(pmap->pm_eptsmr);
2760 * Force the vcpu to exit and trap back into the hypervisor.
2762 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2763 ipi_selected(pmap->pm_active, ipinum);
2767 * Ensure that all active vCPUs will observe the new generation counter
2768 * value before executing any more guest instructions.
2770 smr_wait(pmap->pm_eptsmr, goal);
2774 pmap_invalidate_cpu_mask(pmap_t pmap)
2777 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2781 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2782 const bool invpcid_works1)
2784 struct invpcid_descr d;
2785 uint64_t kcr3, ucr3;
2789 cpuid = PCPU_GET(cpuid);
2790 if (pmap == PCPU_GET(curpmap)) {
2791 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2793 * If we context-switched right after
2794 * PCPU_GET(ucr3_load_mask), we could read the
2795 * ~CR3_PCID_SAVE mask, which causes us to skip
2796 * the code below to invalidate user pages. This
2797 * is handled in pmap_activate_sw_pcid_pti() by
2798 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2800 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2802 * Because pm_pcid is recalculated on a
2803 * context switch, we must disable switching.
2804 * Otherwise, we might use a stale value
2808 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2809 if (invpcid_works1) {
2810 d.pcid = pcid | PMAP_PCID_USER_PT;
2813 invpcid(&d, INVPCID_ADDR);
2815 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2816 ucr3 = pmap->pm_ucr3 | pcid |
2817 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2818 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2823 pmap->pm_pcids[cpuid].pm_gen = 0;
2827 pmap->pm_pcids[i].pm_gen = 0;
2831 * The fence is between stores to pm_gen and the read of the
2832 * pm_active mask. We need to ensure that it is impossible
2833 * for us to miss the bit update in pm_active and
2834 * simultaneously observe a non-zero pm_gen in
2835 * pmap_activate_sw(), otherwise TLB update is missed.
2836 * Without the fence, IA32 allows such an outcome. Note that
2837 * pm_active is updated by a locked operation, which provides
2838 * the reciprocal fence.
2840 atomic_thread_fence_seq_cst();
2844 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2847 pmap_invalidate_page_pcid(pmap, va, true);
2851 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2854 pmap_invalidate_page_pcid(pmap, va, false);
2858 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2862 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2865 if (pmap_pcid_enabled)
2866 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2867 pmap_invalidate_page_pcid_noinvpcid);
2868 return (pmap_invalidate_page_nopcid);
2872 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2873 vm_offset_t addr2 __unused)
2876 if (pmap == kernel_pmap) {
2879 if (pmap == PCPU_GET(curpmap))
2881 pmap_invalidate_page_mode(pmap, va);
2886 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2889 if (pmap_type_guest(pmap)) {
2890 pmap_invalidate_ept(pmap);
2894 KASSERT(pmap->pm_type == PT_X86,
2895 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2897 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2898 pmap_invalidate_page_curcpu_cb);
2901 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2902 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2905 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2906 const bool invpcid_works1)
2908 struct invpcid_descr d;
2909 uint64_t kcr3, ucr3;
2913 cpuid = PCPU_GET(cpuid);
2914 if (pmap == PCPU_GET(curpmap)) {
2915 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2916 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2918 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2919 if (invpcid_works1) {
2920 d.pcid = pcid | PMAP_PCID_USER_PT;
2923 for (; d.addr < eva; d.addr += PAGE_SIZE)
2924 invpcid(&d, INVPCID_ADDR);
2926 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2927 ucr3 = pmap->pm_ucr3 | pcid |
2928 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2929 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2934 pmap->pm_pcids[cpuid].pm_gen = 0;
2938 pmap->pm_pcids[i].pm_gen = 0;
2940 /* See the comment in pmap_invalidate_page_pcid(). */
2941 atomic_thread_fence_seq_cst();
2945 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2949 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2953 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2957 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2961 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2965 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2969 if (pmap_pcid_enabled)
2970 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2971 pmap_invalidate_range_pcid_noinvpcid);
2972 return (pmap_invalidate_range_nopcid);
2976 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2980 if (pmap == kernel_pmap) {
2981 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2984 if (pmap == PCPU_GET(curpmap)) {
2985 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2988 pmap_invalidate_range_mode(pmap, sva, eva);
2993 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2996 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2997 pmap_invalidate_all(pmap);
3001 if (pmap_type_guest(pmap)) {
3002 pmap_invalidate_ept(pmap);
3006 KASSERT(pmap->pm_type == PT_X86,
3007 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
3009 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
3010 pmap_invalidate_range_curcpu_cb);
3014 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
3016 struct invpcid_descr d;
3021 if (pmap == kernel_pmap) {
3022 if (invpcid_works1) {
3023 bzero(&d, sizeof(d));
3024 invpcid(&d, INVPCID_CTXGLOB);
3029 cpuid = PCPU_GET(cpuid);
3030 if (pmap == PCPU_GET(curpmap)) {
3032 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3033 if (invpcid_works1) {
3037 invpcid(&d, INVPCID_CTX);
3039 kcr3 = pmap->pm_cr3 | pcid;
3042 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3043 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3046 pmap->pm_pcids[cpuid].pm_gen = 0;
3049 pmap->pm_pcids[i].pm_gen = 0;
3052 /* See the comment in pmap_invalidate_page_pcid(). */
3053 atomic_thread_fence_seq_cst();
3057 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3060 pmap_invalidate_all_pcid(pmap, true);
3064 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3067 pmap_invalidate_all_pcid(pmap, false);
3071 pmap_invalidate_all_nopcid(pmap_t pmap)
3074 if (pmap == kernel_pmap)
3076 else if (pmap == PCPU_GET(curpmap))
3080 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3083 if (pmap_pcid_enabled)
3084 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3085 pmap_invalidate_all_pcid_noinvpcid);
3086 return (pmap_invalidate_all_nopcid);
3090 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3091 vm_offset_t addr2 __unused)
3094 pmap_invalidate_all_mode(pmap);
3098 pmap_invalidate_all(pmap_t pmap)
3101 if (pmap_type_guest(pmap)) {
3102 pmap_invalidate_ept(pmap);
3106 KASSERT(pmap->pm_type == PT_X86,
3107 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3109 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3110 pmap_invalidate_all_curcpu_cb);
3114 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3115 vm_offset_t addr2 __unused)
3122 pmap_invalidate_cache(void)
3125 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3129 cpuset_t invalidate; /* processors that invalidate their TLB */
3134 u_int store; /* processor that updates the PDE */
3138 pmap_update_pde_action(void *arg)
3140 struct pde_action *act = arg;
3142 if (act->store == PCPU_GET(cpuid))
3143 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3147 pmap_update_pde_teardown(void *arg)
3149 struct pde_action *act = arg;
3151 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3152 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3156 * Change the page size for the specified virtual address in a way that
3157 * prevents any possibility of the TLB ever having two entries that map the
3158 * same virtual address using different page sizes. This is the recommended
3159 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3160 * machine check exception for a TLB state that is improperly diagnosed as a
3164 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3166 struct pde_action act;
3167 cpuset_t active, other_cpus;
3171 cpuid = PCPU_GET(cpuid);
3172 other_cpus = all_cpus;
3173 CPU_CLR(cpuid, &other_cpus);
3174 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3177 active = pmap->pm_active;
3179 if (CPU_OVERLAP(&active, &other_cpus)) {
3181 act.invalidate = active;
3185 act.newpde = newpde;
3186 CPU_SET(cpuid, &active);
3187 smp_rendezvous_cpus(active,
3188 smp_no_rendezvous_barrier, pmap_update_pde_action,
3189 pmap_update_pde_teardown, &act);
3191 pmap_update_pde_store(pmap, pde, newpde);
3192 if (CPU_ISSET(cpuid, &active))
3193 pmap_update_pde_invalidate(pmap, va, newpde);
3199 * Normal, non-SMP, invalidation functions.
3202 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3204 struct invpcid_descr d;
3205 uint64_t kcr3, ucr3;
3208 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3212 KASSERT(pmap->pm_type == PT_X86,
3213 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3215 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3217 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3218 pmap->pm_ucr3 != PMAP_NO_CR3) {
3220 pcid = pmap->pm_pcids[0].pm_pcid;
3221 if (invpcid_works) {
3222 d.pcid = pcid | PMAP_PCID_USER_PT;
3225 invpcid(&d, INVPCID_ADDR);
3227 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3228 ucr3 = pmap->pm_ucr3 | pcid |
3229 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3230 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3234 } else if (pmap_pcid_enabled)
3235 pmap->pm_pcids[0].pm_gen = 0;
3239 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3241 struct invpcid_descr d;
3243 uint64_t kcr3, ucr3;
3245 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3249 KASSERT(pmap->pm_type == PT_X86,
3250 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3252 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3253 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3255 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3256 pmap->pm_ucr3 != PMAP_NO_CR3) {
3258 if (invpcid_works) {
3259 d.pcid = pmap->pm_pcids[0].pm_pcid |
3263 for (; d.addr < eva; d.addr += PAGE_SIZE)
3264 invpcid(&d, INVPCID_ADDR);
3266 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3267 pm_pcid | CR3_PCID_SAVE;
3268 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3269 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3270 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3274 } else if (pmap_pcid_enabled) {
3275 pmap->pm_pcids[0].pm_gen = 0;
3280 pmap_invalidate_all(pmap_t pmap)
3282 struct invpcid_descr d;
3283 uint64_t kcr3, ucr3;
3285 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3289 KASSERT(pmap->pm_type == PT_X86,
3290 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3292 if (pmap == kernel_pmap) {
3293 if (pmap_pcid_enabled && invpcid_works) {
3294 bzero(&d, sizeof(d));
3295 invpcid(&d, INVPCID_CTXGLOB);
3299 } else if (pmap == PCPU_GET(curpmap)) {
3300 if (pmap_pcid_enabled) {
3302 if (invpcid_works) {
3303 d.pcid = pmap->pm_pcids[0].pm_pcid;
3306 invpcid(&d, INVPCID_CTX);
3307 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3308 d.pcid |= PMAP_PCID_USER_PT;
3309 invpcid(&d, INVPCID_CTX);
3312 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3313 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3314 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3315 0].pm_pcid | PMAP_PCID_USER_PT;
3316 pmap_pti_pcid_invalidate(ucr3, kcr3);
3324 } else if (pmap_pcid_enabled) {
3325 pmap->pm_pcids[0].pm_gen = 0;
3330 pmap_invalidate_cache(void)
3337 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3340 pmap_update_pde_store(pmap, pde, newpde);
3341 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3342 pmap_update_pde_invalidate(pmap, va, newpde);
3344 pmap->pm_pcids[0].pm_gen = 0;
3349 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3353 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3354 * by a promotion that did not invalidate the 512 4KB page mappings
3355 * that might exist in the TLB. Consequently, at this point, the TLB
3356 * may hold both 4KB and 2MB page mappings for the address range [va,
3357 * va + NBPDR). Therefore, the entire range must be invalidated here.
3358 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3359 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3360 * single INVLPG suffices to invalidate the 2MB page mapping from the
3363 if ((pde & PG_PROMOTED) != 0)
3364 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3366 pmap_invalidate_page(pmap, va);
3369 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3370 (vm_offset_t sva, vm_offset_t eva))
3373 if ((cpu_feature & CPUID_SS) != 0)
3374 return (pmap_invalidate_cache_range_selfsnoop);
3375 if ((cpu_feature & CPUID_CLFSH) != 0)
3376 return (pmap_force_invalidate_cache_range);
3377 return (pmap_invalidate_cache_range_all);
3380 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3383 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3386 KASSERT((sva & PAGE_MASK) == 0,
3387 ("pmap_invalidate_cache_range: sva not page-aligned"));
3388 KASSERT((eva & PAGE_MASK) == 0,
3389 ("pmap_invalidate_cache_range: eva not page-aligned"));
3393 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3396 pmap_invalidate_cache_range_check_align(sva, eva);
3400 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3403 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3406 * XXX: Some CPUs fault, hang, or trash the local APIC
3407 * registers if we use CLFLUSH on the local APIC range. The
3408 * local APIC is always uncached, so we don't need to flush
3409 * for that range anyway.
3411 if (pmap_kextract(sva) == lapic_paddr)
3414 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3416 * Do per-cache line flush. Use a locked
3417 * instruction to insure that previous stores are
3418 * included in the write-back. The processor
3419 * propagates flush to other processors in the cache
3422 atomic_thread_fence_seq_cst();
3423 for (; sva < eva; sva += cpu_clflush_line_size)
3425 atomic_thread_fence_seq_cst();
3428 * Writes are ordered by CLFLUSH on Intel CPUs.
3430 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3432 for (; sva < eva; sva += cpu_clflush_line_size)
3434 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3440 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3443 pmap_invalidate_cache_range_check_align(sva, eva);
3444 pmap_invalidate_cache();
3448 * Remove the specified set of pages from the data and instruction caches.
3450 * In contrast to pmap_invalidate_cache_range(), this function does not
3451 * rely on the CPU's self-snoop feature, because it is intended for use
3452 * when moving pages into a different cache domain.
3455 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3457 vm_offset_t daddr, eva;
3461 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3462 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3463 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3464 pmap_invalidate_cache();
3467 atomic_thread_fence_seq_cst();
3468 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3470 for (i = 0; i < count; i++) {
3471 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3472 eva = daddr + PAGE_SIZE;
3473 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3481 atomic_thread_fence_seq_cst();
3482 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3488 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3491 pmap_invalidate_cache_range_check_align(sva, eva);
3493 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3494 pmap_force_invalidate_cache_range(sva, eva);
3498 /* See comment in pmap_force_invalidate_cache_range(). */
3499 if (pmap_kextract(sva) == lapic_paddr)
3502 atomic_thread_fence_seq_cst();
3503 for (; sva < eva; sva += cpu_clflush_line_size)
3505 atomic_thread_fence_seq_cst();
3509 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3513 int error, pte_bits;
3515 KASSERT((spa & PAGE_MASK) == 0,
3516 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3517 KASSERT((epa & PAGE_MASK) == 0,
3518 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3520 if (spa < dmaplimit) {
3521 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3523 if (dmaplimit >= epa)
3528 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3530 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3532 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3533 pte = vtopte(vaddr);
3534 for (; spa < epa; spa += PAGE_SIZE) {
3536 pte_store(pte, spa | pte_bits);
3538 /* XXXKIB atomic inside flush_cache_range are excessive */
3539 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3542 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3546 * Routine: pmap_extract
3548 * Extract the physical page address associated
3549 * with the given map/virtual_address pair.
3552 pmap_extract(pmap_t pmap, vm_offset_t va)
3556 pt_entry_t *pte, PG_V;
3560 PG_V = pmap_valid_bit(pmap);
3562 pdpe = pmap_pdpe(pmap, va);
3563 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3564 if ((*pdpe & PG_PS) != 0)
3565 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3567 pde = pmap_pdpe_to_pde(pdpe, va);
3568 if ((*pde & PG_V) != 0) {
3569 if ((*pde & PG_PS) != 0) {
3570 pa = (*pde & PG_PS_FRAME) |
3573 pte = pmap_pde_to_pte(pde, va);
3574 pa = (*pte & PG_FRAME) |
3585 * Routine: pmap_extract_and_hold
3587 * Atomically extract and hold the physical page
3588 * with the given pmap and virtual address pair
3589 * if that mapping permits the given protection.
3592 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3594 pdp_entry_t pdpe, *pdpep;
3595 pd_entry_t pde, *pdep;
3596 pt_entry_t pte, PG_RW, PG_V;
3600 PG_RW = pmap_rw_bit(pmap);
3601 PG_V = pmap_valid_bit(pmap);
3604 pdpep = pmap_pdpe(pmap, va);
3605 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3607 if ((pdpe & PG_PS) != 0) {
3608 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3610 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3614 pdep = pmap_pdpe_to_pde(pdpep, va);
3615 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3617 if ((pde & PG_PS) != 0) {
3618 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3620 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3624 pte = *pmap_pde_to_pte(pdep, va);
3625 if ((pte & PG_V) == 0 ||
3626 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3628 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3631 if (m != NULL && !vm_page_wire_mapped(m))
3639 pmap_kextract(vm_offset_t va)
3644 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3645 pa = DMAP_TO_PHYS(va);
3646 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3647 pa = pmap_large_map_kextract(va);
3651 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3654 * Beware of a concurrent promotion that changes the
3655 * PDE at this point! For example, vtopte() must not
3656 * be used to access the PTE because it would use the
3657 * new PDE. It is, however, safe to use the old PDE
3658 * because the page table page is preserved by the
3661 pa = *pmap_pde_to_pte(&pde, va);
3662 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3668 /***************************************************
3669 * Low level mapping routines.....
3670 ***************************************************/
3673 * Add a wired page to the kva.
3674 * Note: not SMP coherent.
3677 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3682 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3685 static __inline void
3686 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3692 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3693 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3697 * Remove a page from the kernel pagetables.
3698 * Note: not SMP coherent.
3701 pmap_kremove(vm_offset_t va)
3710 * Used to map a range of physical addresses into kernel
3711 * virtual address space.
3713 * The value passed in '*virt' is a suggested virtual address for
3714 * the mapping. Architectures which can support a direct-mapped
3715 * physical to virtual region can return the appropriate address
3716 * within that region, leaving '*virt' unchanged. Other
3717 * architectures should map the pages starting at '*virt' and
3718 * update '*virt' with the first usable address after the mapped
3722 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3724 return PHYS_TO_DMAP(start);
3728 * Add a list of wired pages to the kva
3729 * this routine is only used for temporary
3730 * kernel mappings that do not need to have
3731 * page modification or references recorded.
3732 * Note that old mappings are simply written
3733 * over. The page *must* be wired.
3734 * Note: SMP coherent. Uses a ranged shootdown IPI.
3737 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3739 pt_entry_t *endpte, oldpte, pa, *pte;
3745 endpte = pte + count;
3746 while (pte < endpte) {
3748 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3749 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3750 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3752 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3756 if (__predict_false((oldpte & X86_PG_V) != 0))
3757 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3762 * This routine tears out page mappings from the
3763 * kernel -- it is meant only for temporary mappings.
3764 * Note: SMP coherent. Uses a ranged shootdown IPI.
3767 pmap_qremove(vm_offset_t sva, int count)
3772 while (count-- > 0) {
3773 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3777 pmap_invalidate_range(kernel_pmap, sva, va);
3780 /***************************************************
3781 * Page table page management routines.....
3782 ***************************************************/
3784 * Schedule the specified unused page table page to be freed. Specifically,
3785 * add the page to the specified list of pages that will be released to the
3786 * physical memory manager after the TLB has been updated.
3788 static __inline void
3789 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3790 boolean_t set_PG_ZERO)
3794 m->flags |= PG_ZERO;
3796 m->flags &= ~PG_ZERO;
3797 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3801 * Inserts the specified page table page into the specified pmap's collection
3802 * of idle page table pages. Each of a pmap's page table pages is responsible
3803 * for mapping a distinct range of virtual addresses. The pmap's collection is
3804 * ordered by this virtual address range.
3806 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3809 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3813 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3814 return (vm_radix_insert(&pmap->pm_root, mpte));
3818 * Removes the page table page mapping the specified virtual address from the
3819 * specified pmap's collection of idle page table pages, and returns it.
3820 * Otherwise, returns NULL if there is no page table page corresponding to the
3821 * specified virtual address.
3823 static __inline vm_page_t
3824 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3827 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3828 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3832 * Decrements a page table page's reference count, which is used to record the
3833 * number of valid page table entries within the page. If the reference count
3834 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3835 * page table page was unmapped and FALSE otherwise.
3837 static inline boolean_t
3838 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3842 if (m->ref_count == 0) {
3843 _pmap_unwire_ptp(pmap, va, m, free);
3850 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3856 vm_page_t pdpg, pdppg, pml4pg;
3858 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3861 * unmap the page table page
3863 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3865 MPASS(pmap_is_la57(pmap));
3866 pml5 = pmap_pml5e(pmap, va);
3868 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3869 pml5 = pmap_pml5e_u(pmap, va);
3872 } else if (m->pindex >= NUPDE + NUPDPE) {
3874 pml4 = pmap_pml4e(pmap, va);
3876 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3877 va <= VM_MAXUSER_ADDRESS) {
3878 pml4 = pmap_pml4e_u(pmap, va);
3881 } else if (m->pindex >= NUPDE) {
3883 pdp = pmap_pdpe(pmap, va);
3887 pd = pmap_pde(pmap, va);
3890 pmap_resident_count_dec(pmap, 1);
3891 if (m->pindex < NUPDE) {
3892 /* We just released a PT, unhold the matching PD */
3893 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3894 pmap_unwire_ptp(pmap, va, pdpg, free);
3895 } else if (m->pindex < NUPDE + NUPDPE) {
3896 /* We just released a PD, unhold the matching PDP */
3897 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3898 pmap_unwire_ptp(pmap, va, pdppg, free);
3899 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3900 /* We just released a PDP, unhold the matching PML4 */
3901 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3902 pmap_unwire_ptp(pmap, va, pml4pg, free);
3906 * Put page on a list so that it is released after
3907 * *ALL* TLB shootdown is done
3909 pmap_add_delayed_free_list(m, free, TRUE);
3913 * After removing a page table entry, this routine is used to
3914 * conditionally free the page, and manage the reference count.
3917 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3918 struct spglist *free)
3922 if (va >= VM_MAXUSER_ADDRESS)
3924 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3925 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3926 return (pmap_unwire_ptp(pmap, va, mpte, free));
3930 * Release a page table page reference after a failed attempt to create a
3934 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3936 struct spglist free;
3939 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3941 * Although "va" was never mapped, paging-structure caches
3942 * could nonetheless have entries that refer to the freed
3943 * page table pages. Invalidate those entries.
3945 pmap_invalidate_page(pmap, va);
3946 vm_page_free_pages_toq(&free, true);
3951 pmap_pinit0(pmap_t pmap)
3957 PMAP_LOCK_INIT(pmap);
3958 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3959 pmap->pm_pmltopu = NULL;
3960 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3961 /* hack to keep pmap_pti_pcid_invalidate() alive */
3962 pmap->pm_ucr3 = PMAP_NO_CR3;
3963 pmap->pm_root.rt_root = 0;
3964 CPU_ZERO(&pmap->pm_active);
3965 TAILQ_INIT(&pmap->pm_pvchunk);
3966 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3967 pmap->pm_flags = pmap_flags;
3969 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3970 pmap->pm_pcids[i].pm_gen = 1;
3972 pmap_activate_boot(pmap);
3977 p->p_md.md_flags |= P_MD_KPTI;
3980 pmap_thread_init_invl_gen(td);
3982 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3983 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3984 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3990 pmap_pinit_pml4(vm_page_t pml4pg)
3992 pml4_entry_t *pm_pml4;
3995 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3997 /* Wire in kernel global address entries. */
3998 for (i = 0; i < NKPML4E; i++) {
3999 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
4002 for (i = 0; i < ndmpdpphys; i++) {
4003 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
4007 /* install self-referential address mapping entry(s) */
4008 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
4009 X86_PG_A | X86_PG_M;
4011 /* install large map entries if configured */
4012 for (i = 0; i < lm_ents; i++)
4013 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
4017 pmap_pinit_pml5(vm_page_t pml5pg)
4019 pml5_entry_t *pm_pml5;
4021 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4024 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4025 * entering all existing kernel mappings into level 5 table.
4027 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4028 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4029 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4032 * Install self-referential address mapping entry.
4034 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4035 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4036 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4040 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4042 pml4_entry_t *pm_pml4u;
4045 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4046 for (i = 0; i < NPML4EPG; i++)
4047 pm_pml4u[i] = pti_pml4[i];
4051 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4053 pml5_entry_t *pm_pml5u;
4055 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4058 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4059 * table, entering all kernel mappings needed for usermode
4060 * into level 5 table.
4062 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4063 pmap_kextract((vm_offset_t)pti_pml4) |
4064 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4065 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4069 * Initialize a preallocated and zeroed pmap structure,
4070 * such as one in a vmspace structure.
4073 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4075 vm_page_t pmltop_pg, pmltop_pgu;
4076 vm_paddr_t pmltop_phys;
4080 * allocate the page directory page
4082 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4083 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4085 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4086 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4089 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4090 pmap->pm_pcids[i].pm_gen = 0;
4092 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4093 pmap->pm_ucr3 = PMAP_NO_CR3;
4094 pmap->pm_pmltopu = NULL;
4096 pmap->pm_type = pm_type;
4097 if ((pmltop_pg->flags & PG_ZERO) == 0)
4098 pagezero(pmap->pm_pmltop);
4101 * Do not install the host kernel mappings in the nested page
4102 * tables. These mappings are meaningless in the guest physical
4104 * Install minimal kernel mappings in PTI case.
4108 pmap->pm_cr3 = pmltop_phys;
4109 if (pmap_is_la57(pmap))
4110 pmap_pinit_pml5(pmltop_pg);
4112 pmap_pinit_pml4(pmltop_pg);
4113 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4114 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4115 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4116 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4117 VM_PAGE_TO_PHYS(pmltop_pgu));
4118 if (pmap_is_la57(pmap))
4119 pmap_pinit_pml5_pti(pmltop_pgu);
4121 pmap_pinit_pml4_pti(pmltop_pgu);
4122 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4124 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4125 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4126 pkru_free_range, pmap, M_NOWAIT);
4131 pmap->pm_eptsmr = smr_create("pmap", 0, 0);
4135 pmap->pm_root.rt_root = 0;
4136 CPU_ZERO(&pmap->pm_active);
4137 TAILQ_INIT(&pmap->pm_pvchunk);
4138 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4139 pmap->pm_flags = flags;
4140 pmap->pm_eptgen = 0;
4146 pmap_pinit(pmap_t pmap)
4149 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4153 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4156 struct spglist free;
4158 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4159 if (mpg->ref_count != 0)
4162 _pmap_unwire_ptp(pmap, va, mpg, &free);
4163 pmap_invalidate_page(pmap, va);
4164 vm_page_free_pages_toq(&free, true);
4167 static pml4_entry_t *
4168 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4171 vm_pindex_t pml5index;
4178 if (!pmap_is_la57(pmap))
4179 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4181 PG_V = pmap_valid_bit(pmap);
4182 pml5index = pmap_pml5e_index(va);
4183 pml5 = &pmap->pm_pmltop[pml5index];
4184 if ((*pml5 & PG_V) == 0) {
4185 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4192 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4193 pml4 = &pml4[pmap_pml4e_index(va)];
4194 if ((*pml4 & PG_V) == 0) {
4195 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4196 if (allocated && !addref)
4197 pml4pg->ref_count--;
4198 else if (!allocated && addref)
4199 pml4pg->ref_count++;
4204 static pdp_entry_t *
4205 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4214 PG_V = pmap_valid_bit(pmap);
4216 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4220 if ((*pml4 & PG_V) == 0) {
4221 /* Have to allocate a new pdp, recurse */
4222 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4224 if (pmap_is_la57(pmap))
4225 pmap_allocpte_free_unref(pmap, va,
4226 pmap_pml5e(pmap, va));
4233 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4234 pdp = &pdp[pmap_pdpe_index(va)];
4235 if ((*pdp & PG_V) == 0) {
4236 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4237 if (allocated && !addref)
4239 else if (!allocated && addref)
4246 * This routine is called if the desired page table page does not exist.
4248 * If page table page allocation fails, this routine may sleep before
4249 * returning NULL. It sleeps only if a lock pointer was given.
4251 * Note: If a page allocation fails at page table level two, three, or four,
4252 * up to three pages may be held during the wait, only to be released
4253 * afterwards. This conservative approach is easily argued to avoid
4256 * The ptepindexes, i.e. page indices, of the page table pages encountered
4257 * while translating virtual address va are defined as follows:
4258 * - for the page table page (last level),
4259 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4260 * in other words, it is just the index of the PDE that maps the page
4262 * - for the page directory page,
4263 * ptepindex = NUPDE (number of userland PD entries) +
4264 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4265 * i.e. index of PDPE is put after the last index of PDE,
4266 * - for the page directory pointer page,
4267 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4269 * i.e. index of pml4e is put after the last index of PDPE,
4270 * - for the PML4 page (if LA57 mode is enabled),
4271 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4272 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4273 * i.e. index of pml5e is put after the last index of PML4E.
4275 * Define an order on the paging entries, where all entries of the
4276 * same height are put together, then heights are put from deepest to
4277 * root. Then ptexpindex is the sequential number of the
4278 * corresponding paging entry in this order.
4280 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4281 * LA57 paging structures even in LA48 paging mode. Moreover, the
4282 * ptepindexes are calculated as if the paging structures were 5-level
4283 * regardless of the actual mode of operation.
4285 * The root page at PML4/PML5 does not participate in this indexing scheme,
4286 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4289 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4290 vm_offset_t va __unused)
4292 vm_pindex_t pml5index, pml4index;
4293 pml5_entry_t *pml5, *pml5u;
4294 pml4_entry_t *pml4, *pml4u;
4298 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4300 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4302 PG_A = pmap_accessed_bit(pmap);
4303 PG_M = pmap_modified_bit(pmap);
4304 PG_V = pmap_valid_bit(pmap);
4305 PG_RW = pmap_rw_bit(pmap);
4308 * Allocate a page table page.
4310 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4311 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4312 if (lockp != NULL) {
4313 RELEASE_PV_LIST_LOCK(lockp);
4315 PMAP_ASSERT_NOT_IN_DI();
4321 * Indicate the need to retry. While waiting, the page table
4322 * page may have been allocated.
4326 if ((m->flags & PG_ZERO) == 0)
4330 * Map the pagetable page into the process address space, if
4331 * it isn't already there.
4333 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4334 MPASS(pmap_is_la57(pmap));
4336 pml5index = pmap_pml5e_index(va);
4337 pml5 = &pmap->pm_pmltop[pml5index];
4338 KASSERT((*pml5 & PG_V) == 0,
4339 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4340 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4342 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4343 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4346 pml5u = &pmap->pm_pmltopu[pml5index];
4347 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4350 } else if (ptepindex >= NUPDE + NUPDPE) {
4351 pml4index = pmap_pml4e_index(va);
4352 /* Wire up a new PDPE page */
4353 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4355 vm_page_unwire_noq(m);
4356 vm_page_free_zero(m);
4359 KASSERT((*pml4 & PG_V) == 0,
4360 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4361 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4363 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4364 pml4index < NUPML4E) {
4366 * PTI: Make all user-space mappings in the
4367 * kernel-mode page table no-execute so that
4368 * we detect any programming errors that leave
4369 * the kernel-mode page table active on return
4372 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4375 pml4u = &pmap->pm_pmltopu[pml4index];
4376 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4379 } else if (ptepindex >= NUPDE) {
4380 /* Wire up a new PDE page */
4381 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4383 vm_page_unwire_noq(m);
4384 vm_page_free_zero(m);
4387 KASSERT((*pdp & PG_V) == 0,
4388 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4389 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4391 /* Wire up a new PTE page */
4392 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4394 vm_page_unwire_noq(m);
4395 vm_page_free_zero(m);
4398 if ((*pdp & PG_V) == 0) {
4399 /* Have to allocate a new pd, recurse */
4400 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4401 lockp, va) == NULL) {
4402 pmap_allocpte_free_unref(pmap, va,
4403 pmap_pml4e(pmap, va));
4404 vm_page_unwire_noq(m);
4405 vm_page_free_zero(m);
4409 /* Add reference to the pd page */
4410 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4413 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4415 /* Now we know where the page directory page is */
4416 pd = &pd[pmap_pde_index(va)];
4417 KASSERT((*pd & PG_V) == 0,
4418 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4419 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4422 pmap_resident_count_inc(pmap, 1);
4428 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4429 struct rwlock **lockp)
4431 pdp_entry_t *pdpe, PG_V;
4434 vm_pindex_t pdpindex;
4436 PG_V = pmap_valid_bit(pmap);
4439 pdpe = pmap_pdpe(pmap, va);
4440 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4441 pde = pmap_pdpe_to_pde(pdpe, va);
4442 if (va < VM_MAXUSER_ADDRESS) {
4443 /* Add a reference to the pd page. */
4444 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4448 } else if (va < VM_MAXUSER_ADDRESS) {
4449 /* Allocate a pd page. */
4450 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4451 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4458 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4459 pde = &pde[pmap_pde_index(va)];
4461 panic("pmap_alloc_pde: missing page table page for va %#lx",
4468 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4470 vm_pindex_t ptepindex;
4471 pd_entry_t *pd, PG_V;
4474 PG_V = pmap_valid_bit(pmap);
4477 * Calculate pagetable page index
4479 ptepindex = pmap_pde_pindex(va);
4482 * Get the page directory entry
4484 pd = pmap_pde(pmap, va);
4487 * This supports switching from a 2MB page to a
4490 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4491 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4493 * Invalidation of the 2MB page mapping may have caused
4494 * the deallocation of the underlying PD page.
4501 * If the page table page is mapped, we just increment the
4502 * hold count, and activate it.
4504 if (pd != NULL && (*pd & PG_V) != 0) {
4505 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4509 * Here if the pte page isn't mapped, or if it has been
4512 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4513 if (m == NULL && lockp != NULL)
4519 /***************************************************
4520 * Pmap allocation/deallocation routines.
4521 ***************************************************/
4524 * Release any resources held by the given physical map.
4525 * Called when a pmap initialized by pmap_pinit is being released.
4526 * Should only be called if the map contains no valid mappings.
4529 pmap_release(pmap_t pmap)
4534 KASSERT(pmap->pm_stats.resident_count == 0,
4535 ("pmap_release: pmap %p resident count %ld != 0",
4536 pmap, pmap->pm_stats.resident_count));
4537 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4538 ("pmap_release: pmap %p has reserved page table page(s)",
4540 KASSERT(CPU_EMPTY(&pmap->pm_active),
4541 ("releasing active pmap %p", pmap));
4543 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4545 if (pmap_is_la57(pmap)) {
4546 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4547 pmap->pm_pmltop[PML5PML5I] = 0;
4549 for (i = 0; i < NKPML4E; i++) /* KVA */
4550 pmap->pm_pmltop[KPML4BASE + i] = 0;
4551 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4552 pmap->pm_pmltop[DMPML4I + i] = 0;
4553 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4554 for (i = 0; i < lm_ents; i++) /* Large Map */
4555 pmap->pm_pmltop[LMSPML4I + i] = 0;
4558 vm_page_unwire_noq(m);
4559 vm_page_free_zero(m);
4561 if (pmap->pm_pmltopu != NULL) {
4562 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4564 vm_page_unwire_noq(m);
4567 if (pmap->pm_type == PT_X86 &&
4568 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4569 rangeset_fini(&pmap->pm_pkru);
4573 kvm_size(SYSCTL_HANDLER_ARGS)
4575 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4577 return sysctl_handle_long(oidp, &ksize, 0, req);
4579 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4580 0, 0, kvm_size, "LU",
4584 kvm_free(SYSCTL_HANDLER_ARGS)
4586 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4588 return sysctl_handle_long(oidp, &kfree, 0, req);
4590 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4591 0, 0, kvm_free, "LU",
4592 "Amount of KVM free");
4595 * Allocate physical memory for the vm_page array and map it into KVA,
4596 * attempting to back the vm_pages with domain-local memory.
4599 pmap_page_array_startup(long pages)
4602 pd_entry_t *pde, newpdir;
4603 vm_offset_t va, start, end;
4608 vm_page_array_size = pages;
4610 start = VM_MIN_KERNEL_ADDRESS;
4611 end = start + pages * sizeof(struct vm_page);
4612 for (va = start; va < end; va += NBPDR) {
4613 pfn = first_page + (va - start) / sizeof(struct vm_page);
4614 domain = vm_phys_domain(ptoa(pfn));
4615 pdpe = pmap_pdpe(kernel_pmap, va);
4616 if ((*pdpe & X86_PG_V) == 0) {
4617 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4619 pagezero((void *)PHYS_TO_DMAP(pa));
4620 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4621 X86_PG_A | X86_PG_M);
4623 pde = pmap_pdpe_to_pde(pdpe, va);
4624 if ((*pde & X86_PG_V) != 0)
4625 panic("Unexpected pde");
4626 pa = vm_phys_early_alloc(domain, NBPDR);
4627 for (i = 0; i < NPDEPG; i++)
4628 dump_add_page(pa + i * PAGE_SIZE);
4629 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4630 X86_PG_M | PG_PS | pg_g | pg_nx);
4631 pde_store(pde, newpdir);
4633 vm_page_array = (vm_page_t)start;
4637 * grow the number of kernel page table entries, if needed
4640 pmap_growkernel(vm_offset_t addr)
4644 pd_entry_t *pde, newpdir;
4647 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4650 * Return if "addr" is within the range of kernel page table pages
4651 * that were preallocated during pmap bootstrap. Moreover, leave
4652 * "kernel_vm_end" and the kernel page table as they were.
4654 * The correctness of this action is based on the following
4655 * argument: vm_map_insert() allocates contiguous ranges of the
4656 * kernel virtual address space. It calls this function if a range
4657 * ends after "kernel_vm_end". If the kernel is mapped between
4658 * "kernel_vm_end" and "addr", then the range cannot begin at
4659 * "kernel_vm_end". In fact, its beginning address cannot be less
4660 * than the kernel. Thus, there is no immediate need to allocate
4661 * any new kernel page table pages between "kernel_vm_end" and
4664 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4667 addr = roundup2(addr, NBPDR);
4668 if (addr - 1 >= vm_map_max(kernel_map))
4669 addr = vm_map_max(kernel_map);
4670 while (kernel_vm_end < addr) {
4671 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4672 if ((*pdpe & X86_PG_V) == 0) {
4673 /* We need a new PDP entry */
4674 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4675 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4676 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4678 panic("pmap_growkernel: no memory to grow kernel");
4679 if ((nkpg->flags & PG_ZERO) == 0)
4680 pmap_zero_page(nkpg);
4681 paddr = VM_PAGE_TO_PHYS(nkpg);
4682 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4683 X86_PG_A | X86_PG_M);
4684 continue; /* try again */
4686 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4687 if ((*pde & X86_PG_V) != 0) {
4688 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4689 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4690 kernel_vm_end = vm_map_max(kernel_map);
4696 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4697 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4700 panic("pmap_growkernel: no memory to grow kernel");
4701 if ((nkpg->flags & PG_ZERO) == 0)
4702 pmap_zero_page(nkpg);
4703 paddr = VM_PAGE_TO_PHYS(nkpg);
4704 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4705 pde_store(pde, newpdir);
4707 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4708 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4709 kernel_vm_end = vm_map_max(kernel_map);
4715 /***************************************************
4716 * page management routines.
4717 ***************************************************/
4719 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4720 CTASSERT(_NPCM == 3);
4721 CTASSERT(_NPCPV == 168);
4723 static __inline struct pv_chunk *
4724 pv_to_chunk(pv_entry_t pv)
4727 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4730 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4732 #define PC_FREE0 0xfffffffffffffffful
4733 #define PC_FREE1 0xfffffffffffffffful
4734 #define PC_FREE2 0x000000fffffffffful
4736 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4739 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4741 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4742 "Current number of pv entry chunks");
4743 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4744 "Current number of pv entry chunks allocated");
4745 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4746 "Current number of pv entry chunks frees");
4747 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4748 "Number of times tried to get a chunk page but failed.");
4750 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4751 static int pv_entry_spare;
4753 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4754 "Current number of pv entry frees");
4755 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4756 "Current number of pv entry allocs");
4757 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4758 "Current number of pv entries");
4759 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4760 "Current number of spare pv entries");
4764 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4769 pmap_invalidate_all(pmap);
4770 if (pmap != locked_pmap)
4773 pmap_delayed_invl_finish();
4777 * We are in a serious low memory condition. Resort to
4778 * drastic measures to free some pages so we can allocate
4779 * another pv entry chunk.
4781 * Returns NULL if PV entries were reclaimed from the specified pmap.
4783 * We do not, however, unmap 2mpages because subsequent accesses will
4784 * allocate per-page pv entries until repromotion occurs, thereby
4785 * exacerbating the shortage of free pv entries.
4788 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4790 struct pv_chunks_list *pvc;
4791 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4792 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4793 struct md_page *pvh;
4795 pmap_t next_pmap, pmap;
4796 pt_entry_t *pte, tpte;
4797 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4801 struct spglist free;
4803 int bit, field, freed;
4804 bool start_di, restart;
4806 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4807 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4810 PG_G = PG_A = PG_M = PG_RW = 0;
4812 bzero(&pc_marker_b, sizeof(pc_marker_b));
4813 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4814 pc_marker = (struct pv_chunk *)&pc_marker_b;
4815 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4818 * A delayed invalidation block should already be active if
4819 * pmap_advise() or pmap_remove() called this function by way
4820 * of pmap_demote_pde_locked().
4822 start_di = pmap_not_in_di();
4824 pvc = &pv_chunks[domain];
4825 mtx_lock(&pvc->pvc_lock);
4826 pvc->active_reclaims++;
4827 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4828 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4829 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4830 SLIST_EMPTY(&free)) {
4831 next_pmap = pc->pc_pmap;
4832 if (next_pmap == NULL) {
4834 * The next chunk is a marker. However, it is
4835 * not our marker, so active_reclaims must be
4836 * > 1. Consequently, the next_chunk code
4837 * will not rotate the pv_chunks list.
4841 mtx_unlock(&pvc->pvc_lock);
4844 * A pv_chunk can only be removed from the pc_lru list
4845 * when both pc_chunks_mutex is owned and the
4846 * corresponding pmap is locked.
4848 if (pmap != next_pmap) {
4850 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4853 /* Avoid deadlock and lock recursion. */
4854 if (pmap > locked_pmap) {
4855 RELEASE_PV_LIST_LOCK(lockp);
4858 pmap_delayed_invl_start();
4859 mtx_lock(&pvc->pvc_lock);
4861 } else if (pmap != locked_pmap) {
4862 if (PMAP_TRYLOCK(pmap)) {
4864 pmap_delayed_invl_start();
4865 mtx_lock(&pvc->pvc_lock);
4868 pmap = NULL; /* pmap is not locked */
4869 mtx_lock(&pvc->pvc_lock);
4870 pc = TAILQ_NEXT(pc_marker, pc_lru);
4872 pc->pc_pmap != next_pmap)
4876 } else if (start_di)
4877 pmap_delayed_invl_start();
4878 PG_G = pmap_global_bit(pmap);
4879 PG_A = pmap_accessed_bit(pmap);
4880 PG_M = pmap_modified_bit(pmap);
4881 PG_RW = pmap_rw_bit(pmap);
4887 * Destroy every non-wired, 4 KB page mapping in the chunk.
4890 for (field = 0; field < _NPCM; field++) {
4891 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4892 inuse != 0; inuse &= ~(1UL << bit)) {
4894 pv = &pc->pc_pventry[field * 64 + bit];
4896 pde = pmap_pde(pmap, va);
4897 if ((*pde & PG_PS) != 0)
4899 pte = pmap_pde_to_pte(pde, va);
4900 if ((*pte & PG_W) != 0)
4902 tpte = pte_load_clear(pte);
4903 if ((tpte & PG_G) != 0)
4904 pmap_invalidate_page(pmap, va);
4905 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4906 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4908 if ((tpte & PG_A) != 0)
4909 vm_page_aflag_set(m, PGA_REFERENCED);
4910 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4911 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4913 if (TAILQ_EMPTY(&m->md.pv_list) &&
4914 (m->flags & PG_FICTITIOUS) == 0) {
4915 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4916 if (TAILQ_EMPTY(&pvh->pv_list)) {
4917 vm_page_aflag_clear(m,
4921 pmap_delayed_invl_page(m);
4922 pc->pc_map[field] |= 1UL << bit;
4923 pmap_unuse_pt(pmap, va, *pde, &free);
4928 mtx_lock(&pvc->pvc_lock);
4931 /* Every freed mapping is for a 4 KB page. */
4932 pmap_resident_count_dec(pmap, freed);
4933 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4934 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4935 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4936 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4937 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4938 pc->pc_map[2] == PC_FREE2) {
4939 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4940 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4941 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4942 /* Entire chunk is free; return it. */
4943 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4944 dump_drop_page(m_pc->phys_addr);
4945 mtx_lock(&pvc->pvc_lock);
4946 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4949 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4950 mtx_lock(&pvc->pvc_lock);
4951 /* One freed pv entry in locked_pmap is sufficient. */
4952 if (pmap == locked_pmap)
4955 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4956 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4957 if (pvc->active_reclaims == 1 && pmap != NULL) {
4959 * Rotate the pv chunks list so that we do not
4960 * scan the same pv chunks that could not be
4961 * freed (because they contained a wired
4962 * and/or superpage mapping) on every
4963 * invocation of reclaim_pv_chunk().
4965 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4966 MPASS(pc->pc_pmap != NULL);
4967 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4968 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4972 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4973 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4974 pvc->active_reclaims--;
4975 mtx_unlock(&pvc->pvc_lock);
4976 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4977 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4978 m_pc = SLIST_FIRST(&free);
4979 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4980 /* Recycle a freed page table page. */
4981 m_pc->ref_count = 1;
4983 vm_page_free_pages_toq(&free, true);
4988 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4993 domain = PCPU_GET(domain);
4994 for (i = 0; i < vm_ndomains; i++) {
4995 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4998 domain = (domain + 1) % vm_ndomains;
5005 * free the pv_entry back to the free list
5008 free_pv_entry(pmap_t pmap, pv_entry_t pv)
5010 struct pv_chunk *pc;
5011 int idx, field, bit;
5013 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5014 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
5015 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
5016 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
5017 pc = pv_to_chunk(pv);
5018 idx = pv - &pc->pc_pventry[0];
5021 pc->pc_map[field] |= 1ul << bit;
5022 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
5023 pc->pc_map[2] != PC_FREE2) {
5024 /* 98% of the time, pc is already at the head of the list. */
5025 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5026 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5027 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5031 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5036 free_pv_chunk_dequeued(struct pv_chunk *pc)
5040 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
5041 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
5042 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
5043 /* entire chunk is free, return it */
5044 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5045 dump_drop_page(m->phys_addr);
5046 vm_page_unwire_noq(m);
5051 free_pv_chunk(struct pv_chunk *pc)
5053 struct pv_chunks_list *pvc;
5055 pvc = &pv_chunks[pc_to_domain(pc)];
5056 mtx_lock(&pvc->pvc_lock);
5057 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5058 mtx_unlock(&pvc->pvc_lock);
5059 free_pv_chunk_dequeued(pc);
5063 free_pv_chunk_batch(struct pv_chunklist *batch)
5065 struct pv_chunks_list *pvc;
5066 struct pv_chunk *pc, *npc;
5069 for (i = 0; i < vm_ndomains; i++) {
5070 if (TAILQ_EMPTY(&batch[i]))
5072 pvc = &pv_chunks[i];
5073 mtx_lock(&pvc->pvc_lock);
5074 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5075 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5077 mtx_unlock(&pvc->pvc_lock);
5080 for (i = 0; i < vm_ndomains; i++) {
5081 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5082 free_pv_chunk_dequeued(pc);
5088 * Returns a new PV entry, allocating a new PV chunk from the system when
5089 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5090 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5093 * The given PV list lock may be released.
5096 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5098 struct pv_chunks_list *pvc;
5101 struct pv_chunk *pc;
5104 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5105 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5107 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5109 for (field = 0; field < _NPCM; field++) {
5110 if (pc->pc_map[field]) {
5111 bit = bsfq(pc->pc_map[field]);
5115 if (field < _NPCM) {
5116 pv = &pc->pc_pventry[field * 64 + bit];
5117 pc->pc_map[field] &= ~(1ul << bit);
5118 /* If this was the last item, move it to tail */
5119 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5120 pc->pc_map[2] == 0) {
5121 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5122 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5125 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5126 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5130 /* No free items, allocate another chunk */
5131 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5134 if (lockp == NULL) {
5135 PV_STAT(pc_chunk_tryfail++);
5138 m = reclaim_pv_chunk(pmap, lockp);
5142 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5143 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5144 dump_add_page(m->phys_addr);
5145 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5147 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5148 pc->pc_map[1] = PC_FREE1;
5149 pc->pc_map[2] = PC_FREE2;
5150 pvc = &pv_chunks[vm_phys_domain(m->phys_addr)];
5151 mtx_lock(&pvc->pvc_lock);
5152 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5153 mtx_unlock(&pvc->pvc_lock);
5154 pv = &pc->pc_pventry[0];
5155 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5156 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5157 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5162 * Returns the number of one bits within the given PV chunk map.
5164 * The erratas for Intel processors state that "POPCNT Instruction May
5165 * Take Longer to Execute Than Expected". It is believed that the
5166 * issue is the spurious dependency on the destination register.
5167 * Provide a hint to the register rename logic that the destination
5168 * value is overwritten, by clearing it, as suggested in the
5169 * optimization manual. It should be cheap for unaffected processors
5172 * Reference numbers for erratas are
5173 * 4th Gen Core: HSD146
5174 * 5th Gen Core: BDM85
5175 * 6th Gen Core: SKL029
5178 popcnt_pc_map_pq(uint64_t *map)
5182 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5183 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5184 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5185 : "=&r" (result), "=&r" (tmp)
5186 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5191 * Ensure that the number of spare PV entries in the specified pmap meets or
5192 * exceeds the given count, "needed".
5194 * The given PV list lock may be released.
5197 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5199 struct pv_chunks_list *pvc;
5200 struct pch new_tail[PMAP_MEMDOM];
5201 struct pv_chunk *pc;
5206 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5207 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5210 * Newly allocated PV chunks must be stored in a private list until
5211 * the required number of PV chunks have been allocated. Otherwise,
5212 * reclaim_pv_chunk() could recycle one of these chunks. In
5213 * contrast, these chunks must be added to the pmap upon allocation.
5215 for (i = 0; i < PMAP_MEMDOM; i++)
5216 TAILQ_INIT(&new_tail[i]);
5219 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5221 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5222 bit_count((bitstr_t *)pc->pc_map, 0,
5223 sizeof(pc->pc_map) * NBBY, &free);
5226 free = popcnt_pc_map_pq(pc->pc_map);
5230 if (avail >= needed)
5233 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5234 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5237 m = reclaim_pv_chunk(pmap, lockp);
5242 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5243 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5244 dump_add_page(m->phys_addr);
5245 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5247 pc->pc_map[0] = PC_FREE0;
5248 pc->pc_map[1] = PC_FREE1;
5249 pc->pc_map[2] = PC_FREE2;
5250 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5251 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5252 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5255 * The reclaim might have freed a chunk from the current pmap.
5256 * If that chunk contained available entries, we need to
5257 * re-count the number of available entries.
5262 for (i = 0; i < vm_ndomains; i++) {
5263 if (TAILQ_EMPTY(&new_tail[i]))
5265 pvc = &pv_chunks[i];
5266 mtx_lock(&pvc->pvc_lock);
5267 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5268 mtx_unlock(&pvc->pvc_lock);
5273 * First find and then remove the pv entry for the specified pmap and virtual
5274 * address from the specified pv list. Returns the pv entry if found and NULL
5275 * otherwise. This operation can be performed on pv lists for either 4KB or
5276 * 2MB page mappings.
5278 static __inline pv_entry_t
5279 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5283 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5284 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5285 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5294 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5295 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5296 * entries for each of the 4KB page mappings.
5299 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5300 struct rwlock **lockp)
5302 struct md_page *pvh;
5303 struct pv_chunk *pc;
5305 vm_offset_t va_last;
5309 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5310 KASSERT((pa & PDRMASK) == 0,
5311 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5312 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5315 * Transfer the 2mpage's pv entry for this mapping to the first
5316 * page's pv list. Once this transfer begins, the pv list lock
5317 * must not be released until the last pv entry is reinstantiated.
5319 pvh = pa_to_pvh(pa);
5320 va = trunc_2mpage(va);
5321 pv = pmap_pvh_remove(pvh, pmap, va);
5322 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5323 m = PHYS_TO_VM_PAGE(pa);
5324 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5326 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5327 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5328 va_last = va + NBPDR - PAGE_SIZE;
5330 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5331 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5332 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5333 for (field = 0; field < _NPCM; field++) {
5334 while (pc->pc_map[field]) {
5335 bit = bsfq(pc->pc_map[field]);
5336 pc->pc_map[field] &= ~(1ul << bit);
5337 pv = &pc->pc_pventry[field * 64 + bit];
5341 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5342 ("pmap_pv_demote_pde: page %p is not managed", m));
5343 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5349 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5350 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5353 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5354 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5355 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5357 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5358 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5361 #if VM_NRESERVLEVEL > 0
5363 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5364 * replace the many pv entries for the 4KB page mappings by a single pv entry
5365 * for the 2MB page mapping.
5368 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5369 struct rwlock **lockp)
5371 struct md_page *pvh;
5373 vm_offset_t va_last;
5376 KASSERT((pa & PDRMASK) == 0,
5377 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5378 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5381 * Transfer the first page's pv entry for this mapping to the 2mpage's
5382 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5383 * a transfer avoids the possibility that get_pv_entry() calls
5384 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5385 * mappings that is being promoted.
5387 m = PHYS_TO_VM_PAGE(pa);
5388 va = trunc_2mpage(va);
5389 pv = pmap_pvh_remove(&m->md, pmap, va);
5390 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5391 pvh = pa_to_pvh(pa);
5392 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5394 /* Free the remaining NPTEPG - 1 pv entries. */
5395 va_last = va + NBPDR - PAGE_SIZE;
5399 pmap_pvh_free(&m->md, pmap, va);
5400 } while (va < va_last);
5402 #endif /* VM_NRESERVLEVEL > 0 */
5405 * First find and then destroy the pv entry for the specified pmap and virtual
5406 * address. This operation can be performed on pv lists for either 4KB or 2MB
5410 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5414 pv = pmap_pvh_remove(pvh, pmap, va);
5415 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5416 free_pv_entry(pmap, pv);
5420 * Conditionally create the PV entry for a 4KB page mapping if the required
5421 * memory can be allocated without resorting to reclamation.
5424 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5425 struct rwlock **lockp)
5429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5430 /* Pass NULL instead of the lock pointer to disable reclamation. */
5431 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5433 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5434 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5442 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5443 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5444 * false if the PV entry cannot be allocated without resorting to reclamation.
5447 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5448 struct rwlock **lockp)
5450 struct md_page *pvh;
5454 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5455 /* Pass NULL instead of the lock pointer to disable reclamation. */
5456 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5457 NULL : lockp)) == NULL)
5460 pa = pde & PG_PS_FRAME;
5461 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5462 pvh = pa_to_pvh(pa);
5463 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5469 * Fills a page table page with mappings to consecutive physical pages.
5472 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5476 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5478 newpte += PAGE_SIZE;
5483 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5484 * mapping is invalidated.
5487 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5489 struct rwlock *lock;
5493 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5500 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5504 pt_entry_t *xpte, *ypte;
5506 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5507 xpte++, newpte += PAGE_SIZE) {
5508 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5509 printf("pmap_demote_pde: xpte %zd and newpte map "
5510 "different pages: found %#lx, expected %#lx\n",
5511 xpte - firstpte, *xpte, newpte);
5512 printf("page table dump\n");
5513 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5514 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5519 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5520 ("pmap_demote_pde: firstpte and newpte map different physical"
5527 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5528 pd_entry_t oldpde, struct rwlock **lockp)
5530 struct spglist free;
5534 sva = trunc_2mpage(va);
5535 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5536 if ((oldpde & pmap_global_bit(pmap)) == 0)
5537 pmap_invalidate_pde_page(pmap, sva, oldpde);
5538 vm_page_free_pages_toq(&free, true);
5539 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5544 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5545 struct rwlock **lockp)
5547 pd_entry_t newpde, oldpde;
5548 pt_entry_t *firstpte, newpte;
5549 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5555 PG_A = pmap_accessed_bit(pmap);
5556 PG_G = pmap_global_bit(pmap);
5557 PG_M = pmap_modified_bit(pmap);
5558 PG_RW = pmap_rw_bit(pmap);
5559 PG_V = pmap_valid_bit(pmap);
5560 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5561 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5563 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5564 in_kernel = va >= VM_MAXUSER_ADDRESS;
5566 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5567 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5570 * Invalidate the 2MB page mapping and return "failure" if the
5571 * mapping was never accessed.
5573 if ((oldpde & PG_A) == 0) {
5574 KASSERT((oldpde & PG_W) == 0,
5575 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5576 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5580 mpte = pmap_remove_pt_page(pmap, va);
5582 KASSERT((oldpde & PG_W) == 0,
5583 ("pmap_demote_pde: page table page for a wired mapping"
5587 * If the page table page is missing and the mapping
5588 * is for a kernel address, the mapping must belong to
5589 * the direct map. Page table pages are preallocated
5590 * for every other part of the kernel address space,
5591 * so the direct map region is the only part of the
5592 * kernel address space that must be handled here.
5594 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5595 va < DMAP_MAX_ADDRESS),
5596 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5599 * If the 2MB page mapping belongs to the direct map
5600 * region of the kernel's address space, then the page
5601 * allocation request specifies the highest possible
5602 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5603 * priority is normal.
5605 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5606 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5607 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5610 * If the allocation of the new page table page fails,
5611 * invalidate the 2MB page mapping and return "failure".
5614 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5619 mpte->ref_count = NPTEPG;
5620 pmap_resident_count_inc(pmap, 1);
5623 mptepa = VM_PAGE_TO_PHYS(mpte);
5624 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5625 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5626 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5627 ("pmap_demote_pde: oldpde is missing PG_M"));
5628 newpte = oldpde & ~PG_PS;
5629 newpte = pmap_swap_pat(pmap, newpte);
5632 * If the page table page is not leftover from an earlier promotion,
5635 if (mpte->valid == 0)
5636 pmap_fill_ptp(firstpte, newpte);
5638 pmap_demote_pde_check(firstpte, newpte);
5641 * If the mapping has changed attributes, update the page table
5644 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5645 pmap_fill_ptp(firstpte, newpte);
5648 * The spare PV entries must be reserved prior to demoting the
5649 * mapping, that is, prior to changing the PDE. Otherwise, the state
5650 * of the PDE and the PV lists will be inconsistent, which can result
5651 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5652 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5653 * PV entry for the 2MB page mapping that is being demoted.
5655 if ((oldpde & PG_MANAGED) != 0)
5656 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5659 * Demote the mapping. This pmap is locked. The old PDE has
5660 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5661 * set. Thus, there is no danger of a race with another
5662 * processor changing the setting of PG_A and/or PG_M between
5663 * the read above and the store below.
5665 if (workaround_erratum383)
5666 pmap_update_pde(pmap, va, pde, newpde);
5668 pde_store(pde, newpde);
5671 * Invalidate a stale recursive mapping of the page table page.
5674 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5677 * Demote the PV entry.
5679 if ((oldpde & PG_MANAGED) != 0)
5680 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5682 atomic_add_long(&pmap_pde_demotions, 1);
5683 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5689 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5692 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5698 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5700 mpte = pmap_remove_pt_page(pmap, va);
5702 panic("pmap_remove_kernel_pde: Missing pt page.");
5704 mptepa = VM_PAGE_TO_PHYS(mpte);
5705 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5708 * If this page table page was unmapped by a promotion, then it
5709 * contains valid mappings. Zero it to invalidate those mappings.
5711 if (mpte->valid != 0)
5712 pagezero((void *)PHYS_TO_DMAP(mptepa));
5715 * Demote the mapping.
5717 if (workaround_erratum383)
5718 pmap_update_pde(pmap, va, pde, newpde);
5720 pde_store(pde, newpde);
5723 * Invalidate a stale recursive mapping of the page table page.
5725 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5729 * pmap_remove_pde: do the things to unmap a superpage in a process
5732 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5733 struct spglist *free, struct rwlock **lockp)
5735 struct md_page *pvh;
5737 vm_offset_t eva, va;
5739 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5741 PG_G = pmap_global_bit(pmap);
5742 PG_A = pmap_accessed_bit(pmap);
5743 PG_M = pmap_modified_bit(pmap);
5744 PG_RW = pmap_rw_bit(pmap);
5746 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5747 KASSERT((sva & PDRMASK) == 0,
5748 ("pmap_remove_pde: sva is not 2mpage aligned"));
5749 oldpde = pte_load_clear(pdq);
5751 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5752 if ((oldpde & PG_G) != 0)
5753 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5754 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5755 if (oldpde & PG_MANAGED) {
5756 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5757 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5758 pmap_pvh_free(pvh, pmap, sva);
5760 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5761 va < eva; va += PAGE_SIZE, m++) {
5762 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5765 vm_page_aflag_set(m, PGA_REFERENCED);
5766 if (TAILQ_EMPTY(&m->md.pv_list) &&
5767 TAILQ_EMPTY(&pvh->pv_list))
5768 vm_page_aflag_clear(m, PGA_WRITEABLE);
5769 pmap_delayed_invl_page(m);
5772 if (pmap == kernel_pmap) {
5773 pmap_remove_kernel_pde(pmap, pdq, sva);
5775 mpte = pmap_remove_pt_page(pmap, sva);
5777 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5778 ("pmap_remove_pde: pte page not promoted"));
5779 pmap_resident_count_dec(pmap, 1);
5780 KASSERT(mpte->ref_count == NPTEPG,
5781 ("pmap_remove_pde: pte page ref count error"));
5782 mpte->ref_count = 0;
5783 pmap_add_delayed_free_list(mpte, free, FALSE);
5786 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5790 * pmap_remove_pte: do the things to unmap a page in a process
5793 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5794 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5796 struct md_page *pvh;
5797 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5800 PG_A = pmap_accessed_bit(pmap);
5801 PG_M = pmap_modified_bit(pmap);
5802 PG_RW = pmap_rw_bit(pmap);
5804 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5805 oldpte = pte_load_clear(ptq);
5807 pmap->pm_stats.wired_count -= 1;
5808 pmap_resident_count_dec(pmap, 1);
5809 if (oldpte & PG_MANAGED) {
5810 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5811 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5814 vm_page_aflag_set(m, PGA_REFERENCED);
5815 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5816 pmap_pvh_free(&m->md, pmap, va);
5817 if (TAILQ_EMPTY(&m->md.pv_list) &&
5818 (m->flags & PG_FICTITIOUS) == 0) {
5819 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5820 if (TAILQ_EMPTY(&pvh->pv_list))
5821 vm_page_aflag_clear(m, PGA_WRITEABLE);
5823 pmap_delayed_invl_page(m);
5825 return (pmap_unuse_pt(pmap, va, ptepde, free));
5829 * Remove a single page from a process address space
5832 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5833 struct spglist *free)
5835 struct rwlock *lock;
5836 pt_entry_t *pte, PG_V;
5838 PG_V = pmap_valid_bit(pmap);
5839 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5840 if ((*pde & PG_V) == 0)
5842 pte = pmap_pde_to_pte(pde, va);
5843 if ((*pte & PG_V) == 0)
5846 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5849 pmap_invalidate_page(pmap, va);
5853 * Removes the specified range of addresses from the page table page.
5856 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5857 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5859 pt_entry_t PG_G, *pte;
5863 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5864 PG_G = pmap_global_bit(pmap);
5867 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5871 pmap_invalidate_range(pmap, va, sva);
5876 if ((*pte & PG_G) == 0)
5880 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5886 pmap_invalidate_range(pmap, va, sva);
5891 * Remove the given range of addresses from the specified map.
5893 * It is assumed that the start and end are properly
5894 * rounded to the page size.
5897 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5899 struct rwlock *lock;
5901 vm_offset_t va_next;
5902 pml5_entry_t *pml5e;
5903 pml4_entry_t *pml4e;
5905 pd_entry_t ptpaddr, *pde;
5906 pt_entry_t PG_G, PG_V;
5907 struct spglist free;
5910 PG_G = pmap_global_bit(pmap);
5911 PG_V = pmap_valid_bit(pmap);
5914 * Perform an unsynchronized read. This is, however, safe.
5916 if (pmap->pm_stats.resident_count == 0)
5922 pmap_delayed_invl_start();
5924 pmap_pkru_on_remove(pmap, sva, eva);
5927 * special handling of removing one page. a very
5928 * common operation and easy to short circuit some
5931 if (sva + PAGE_SIZE == eva) {
5932 pde = pmap_pde(pmap, sva);
5933 if (pde && (*pde & PG_PS) == 0) {
5934 pmap_remove_page(pmap, sva, pde, &free);
5940 for (; sva < eva; sva = va_next) {
5941 if (pmap->pm_stats.resident_count == 0)
5944 if (pmap_is_la57(pmap)) {
5945 pml5e = pmap_pml5e(pmap, sva);
5946 if ((*pml5e & PG_V) == 0) {
5947 va_next = (sva + NBPML5) & ~PML5MASK;
5952 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5954 pml4e = pmap_pml4e(pmap, sva);
5956 if ((*pml4e & PG_V) == 0) {
5957 va_next = (sva + NBPML4) & ~PML4MASK;
5963 va_next = (sva + NBPDP) & ~PDPMASK;
5966 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5967 if ((*pdpe & PG_V) == 0)
5969 if ((*pdpe & PG_PS) != 0) {
5970 KASSERT(va_next <= eva,
5971 ("partial update of non-transparent 1G mapping "
5972 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
5973 *pdpe, sva, eva, va_next));
5974 MPASS(pmap != kernel_pmap); /* XXXKIB */
5975 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
5978 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
5979 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
5980 pmap_unwire_ptp(pmap, sva, mt, &free);
5985 * Calculate index for next page table.
5987 va_next = (sva + NBPDR) & ~PDRMASK;
5991 pde = pmap_pdpe_to_pde(pdpe, sva);
5995 * Weed out invalid mappings.
6001 * Check for large page.
6003 if ((ptpaddr & PG_PS) != 0) {
6005 * Are we removing the entire large page? If not,
6006 * demote the mapping and fall through.
6008 if (sva + NBPDR == va_next && eva >= va_next) {
6010 * The TLB entry for a PG_G mapping is
6011 * invalidated by pmap_remove_pde().
6013 if ((ptpaddr & PG_G) == 0)
6015 pmap_remove_pde(pmap, pde, sva, &free, &lock);
6017 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
6019 /* The large page mapping was destroyed. */
6026 * Limit our scan to either the end of the va represented
6027 * by the current page table page, or to the end of the
6028 * range being removed.
6033 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6040 pmap_invalidate_all(pmap);
6042 pmap_delayed_invl_finish();
6043 vm_page_free_pages_toq(&free, true);
6047 * Routine: pmap_remove_all
6049 * Removes this physical page from
6050 * all physical maps in which it resides.
6051 * Reflects back modify bits to the pager.
6054 * Original versions of this routine were very
6055 * inefficient because they iteratively called
6056 * pmap_remove (slow...)
6060 pmap_remove_all(vm_page_t m)
6062 struct md_page *pvh;
6065 struct rwlock *lock;
6066 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6069 struct spglist free;
6070 int pvh_gen, md_gen;
6072 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6073 ("pmap_remove_all: page %p is not managed", m));
6075 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6076 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6077 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6080 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6082 if (!PMAP_TRYLOCK(pmap)) {
6083 pvh_gen = pvh->pv_gen;
6087 if (pvh_gen != pvh->pv_gen) {
6094 pde = pmap_pde(pmap, va);
6095 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6098 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6100 if (!PMAP_TRYLOCK(pmap)) {
6101 pvh_gen = pvh->pv_gen;
6102 md_gen = m->md.pv_gen;
6106 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6112 PG_A = pmap_accessed_bit(pmap);
6113 PG_M = pmap_modified_bit(pmap);
6114 PG_RW = pmap_rw_bit(pmap);
6115 pmap_resident_count_dec(pmap, 1);
6116 pde = pmap_pde(pmap, pv->pv_va);
6117 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6118 " a 2mpage in page %p's pv list", m));
6119 pte = pmap_pde_to_pte(pde, pv->pv_va);
6120 tpte = pte_load_clear(pte);
6122 pmap->pm_stats.wired_count--;
6124 vm_page_aflag_set(m, PGA_REFERENCED);
6127 * Update the vm_page_t clean and reference bits.
6129 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6131 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6132 pmap_invalidate_page(pmap, pv->pv_va);
6133 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6135 free_pv_entry(pmap, pv);
6138 vm_page_aflag_clear(m, PGA_WRITEABLE);
6140 pmap_delayed_invl_wait(m);
6141 vm_page_free_pages_toq(&free, true);
6145 * pmap_protect_pde: do the things to protect a 2mpage in a process
6148 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6150 pd_entry_t newpde, oldpde;
6152 boolean_t anychanged;
6153 pt_entry_t PG_G, PG_M, PG_RW;
6155 PG_G = pmap_global_bit(pmap);
6156 PG_M = pmap_modified_bit(pmap);
6157 PG_RW = pmap_rw_bit(pmap);
6159 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6160 KASSERT((sva & PDRMASK) == 0,
6161 ("pmap_protect_pde: sva is not 2mpage aligned"));
6164 oldpde = newpde = *pde;
6165 if ((prot & VM_PROT_WRITE) == 0) {
6166 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6167 (PG_MANAGED | PG_M | PG_RW)) {
6168 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6169 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6172 newpde &= ~(PG_RW | PG_M);
6174 if ((prot & VM_PROT_EXECUTE) == 0)
6176 if (newpde != oldpde) {
6178 * As an optimization to future operations on this PDE, clear
6179 * PG_PROMOTED. The impending invalidation will remove any
6180 * lingering 4KB page mappings from the TLB.
6182 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6184 if ((oldpde & PG_G) != 0)
6185 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6189 return (anychanged);
6193 * Set the physical protection on the
6194 * specified range of this map as requested.
6197 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6200 vm_offset_t va_next;
6201 pml4_entry_t *pml4e;
6203 pd_entry_t ptpaddr, *pde;
6204 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6205 pt_entry_t obits, pbits;
6206 boolean_t anychanged;
6208 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6209 if (prot == VM_PROT_NONE) {
6210 pmap_remove(pmap, sva, eva);
6214 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6215 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6218 PG_G = pmap_global_bit(pmap);
6219 PG_M = pmap_modified_bit(pmap);
6220 PG_V = pmap_valid_bit(pmap);
6221 PG_RW = pmap_rw_bit(pmap);
6225 * Although this function delays and batches the invalidation
6226 * of stale TLB entries, it does not need to call
6227 * pmap_delayed_invl_start() and
6228 * pmap_delayed_invl_finish(), because it does not
6229 * ordinarily destroy mappings. Stale TLB entries from
6230 * protection-only changes need only be invalidated before the
6231 * pmap lock is released, because protection-only changes do
6232 * not destroy PV entries. Even operations that iterate over
6233 * a physical page's PV list of mappings, like
6234 * pmap_remove_write(), acquire the pmap lock for each
6235 * mapping. Consequently, for protection-only changes, the
6236 * pmap lock suffices to synchronize both page table and TLB
6239 * This function only destroys a mapping if pmap_demote_pde()
6240 * fails. In that case, stale TLB entries are immediately
6245 for (; sva < eva; sva = va_next) {
6246 pml4e = pmap_pml4e(pmap, sva);
6247 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6248 va_next = (sva + NBPML4) & ~PML4MASK;
6254 va_next = (sva + NBPDP) & ~PDPMASK;
6257 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6258 if ((*pdpe & PG_V) == 0)
6260 if ((*pdpe & PG_PS) != 0) {
6261 KASSERT(va_next <= eva,
6262 ("partial update of non-transparent 1G mapping "
6263 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6264 *pdpe, sva, eva, va_next));
6266 obits = pbits = *pdpe;
6267 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6268 MPASS(pmap != kernel_pmap); /* XXXKIB */
6269 if ((prot & VM_PROT_WRITE) == 0)
6270 pbits &= ~(PG_RW | PG_M);
6271 if ((prot & VM_PROT_EXECUTE) == 0)
6274 if (pbits != obits) {
6275 if (!atomic_cmpset_long(pdpe, obits, pbits))
6276 /* PG_PS cannot be cleared under us, */
6283 va_next = (sva + NBPDR) & ~PDRMASK;
6287 pde = pmap_pdpe_to_pde(pdpe, sva);
6291 * Weed out invalid mappings.
6297 * Check for large page.
6299 if ((ptpaddr & PG_PS) != 0) {
6301 * Are we protecting the entire large page? If not,
6302 * demote the mapping and fall through.
6304 if (sva + NBPDR == va_next && eva >= va_next) {
6306 * The TLB entry for a PG_G mapping is
6307 * invalidated by pmap_protect_pde().
6309 if (pmap_protect_pde(pmap, pde, sva, prot))
6312 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6314 * The large page mapping was destroyed.
6323 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6326 obits = pbits = *pte;
6327 if ((pbits & PG_V) == 0)
6330 if ((prot & VM_PROT_WRITE) == 0) {
6331 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6332 (PG_MANAGED | PG_M | PG_RW)) {
6333 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6336 pbits &= ~(PG_RW | PG_M);
6338 if ((prot & VM_PROT_EXECUTE) == 0)
6341 if (pbits != obits) {
6342 if (!atomic_cmpset_long(pte, obits, pbits))
6345 pmap_invalidate_page(pmap, sva);
6352 pmap_invalidate_all(pmap);
6356 #if VM_NRESERVLEVEL > 0
6358 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6361 if (pmap->pm_type != PT_EPT)
6363 return ((pde & EPT_PG_EXECUTE) != 0);
6367 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6368 * single page table page (PTP) to a single 2MB page mapping. For promotion
6369 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6370 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6371 * identical characteristics.
6374 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6375 struct rwlock **lockp)
6378 pt_entry_t *firstpte, oldpte, pa, *pte;
6379 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6383 PG_A = pmap_accessed_bit(pmap);
6384 PG_G = pmap_global_bit(pmap);
6385 PG_M = pmap_modified_bit(pmap);
6386 PG_V = pmap_valid_bit(pmap);
6387 PG_RW = pmap_rw_bit(pmap);
6388 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6389 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6391 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6394 * Examine the first PTE in the specified PTP. Abort if this PTE is
6395 * either invalid, unused, or does not map the first 4KB physical page
6396 * within a 2MB page.
6398 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6401 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6402 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6404 atomic_add_long(&pmap_pde_p_failures, 1);
6405 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6406 " in pmap %p", va, pmap);
6409 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6411 * When PG_M is already clear, PG_RW can be cleared without
6412 * a TLB invalidation.
6414 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6420 * Examine each of the other PTEs in the specified PTP. Abort if this
6421 * PTE maps an unexpected 4KB physical page or does not have identical
6422 * characteristics to the first PTE.
6424 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6425 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6428 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6429 atomic_add_long(&pmap_pde_p_failures, 1);
6430 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6431 " in pmap %p", va, pmap);
6434 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6436 * When PG_M is already clear, PG_RW can be cleared
6437 * without a TLB invalidation.
6439 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6442 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6443 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6444 (va & ~PDRMASK), pmap);
6446 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6447 atomic_add_long(&pmap_pde_p_failures, 1);
6448 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6449 " in pmap %p", va, pmap);
6456 * Save the page table page in its current state until the PDE
6457 * mapping the superpage is demoted by pmap_demote_pde() or
6458 * destroyed by pmap_remove_pde().
6460 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6461 KASSERT(mpte >= vm_page_array &&
6462 mpte < &vm_page_array[vm_page_array_size],
6463 ("pmap_promote_pde: page table page is out of range"));
6464 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6465 ("pmap_promote_pde: page table page's pindex is wrong"));
6466 if (pmap_insert_pt_page(pmap, mpte, true)) {
6467 atomic_add_long(&pmap_pde_p_failures, 1);
6469 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6475 * Promote the pv entries.
6477 if ((newpde & PG_MANAGED) != 0)
6478 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6481 * Propagate the PAT index to its proper position.
6483 newpde = pmap_swap_pat(pmap, newpde);
6486 * Map the superpage.
6488 if (workaround_erratum383)
6489 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6491 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6493 atomic_add_long(&pmap_pde_promotions, 1);
6494 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6495 " in pmap %p", va, pmap);
6497 #endif /* VM_NRESERVLEVEL > 0 */
6500 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6504 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6506 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6507 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6508 ("psind %d unexpected", psind));
6509 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6510 ("unaligned phys address %#lx newpte %#lx psind %d",
6511 newpte & PG_FRAME, newpte, psind));
6512 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6513 ("unaligned va %#lx psind %d", va, psind));
6514 KASSERT(va < VM_MAXUSER_ADDRESS,
6515 ("kernel mode non-transparent superpage")); /* XXXKIB */
6516 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6517 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6519 PG_V = pmap_valid_bit(pmap);
6522 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6523 return (KERN_PROTECTION_FAILURE);
6525 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6526 pten |= pmap_pkru_get(pmap, va);
6528 if (psind == 2) { /* 1G */
6529 pml4e = pmap_pml4e(pmap, va);
6530 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6531 mp = _pmap_allocpte(pmap, pmap_pml4e_pindex(va),
6535 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6536 pdpe = &pdpe[pmap_pdpe_index(va)];
6538 MPASS(origpte == 0);
6540 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6541 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6543 if ((origpte & PG_V) == 0) {
6544 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6549 } else /* (psind == 1) */ { /* 2M */
6550 pde = pmap_pde(pmap, va);
6552 mp = _pmap_allocpte(pmap, pmap_pdpe_pindex(va),
6556 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6557 pde = &pde[pmap_pde_index(va)];
6559 MPASS(origpte == 0);
6562 if ((origpte & PG_V) == 0) {
6563 pdpe = pmap_pdpe(pmap, va);
6564 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6565 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6571 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6572 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6573 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6574 va, psind == 2 ? "1G" : "2M", origpte, pten));
6575 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6576 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6577 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6578 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6579 if ((origpte & PG_V) == 0)
6580 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6582 return (KERN_SUCCESS);
6585 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6586 return (KERN_RESOURCE_SHORTAGE);
6594 * Insert the given physical page (p) at
6595 * the specified virtual address (v) in the
6596 * target physical map with the protection requested.
6598 * If specified, the page will be wired down, meaning
6599 * that the related pte can not be reclaimed.
6601 * NB: This is the only routine which MAY NOT lazy-evaluate
6602 * or lose information. That is, this routine must actually
6603 * insert this page into the given map NOW.
6605 * When destroying both a page table and PV entry, this function
6606 * performs the TLB invalidation before releasing the PV list
6607 * lock, so we do not need pmap_delayed_invl_page() calls here.
6610 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6611 u_int flags, int8_t psind)
6613 struct rwlock *lock;
6615 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6616 pt_entry_t newpte, origpte;
6623 PG_A = pmap_accessed_bit(pmap);
6624 PG_G = pmap_global_bit(pmap);
6625 PG_M = pmap_modified_bit(pmap);
6626 PG_V = pmap_valid_bit(pmap);
6627 PG_RW = pmap_rw_bit(pmap);
6629 va = trunc_page(va);
6630 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6631 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6632 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6634 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6635 va >= kmi.clean_eva,
6636 ("pmap_enter: managed mapping within the clean submap"));
6637 if ((m->oflags & VPO_UNMANAGED) == 0)
6638 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6639 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6640 ("pmap_enter: flags %u has reserved bits set", flags));
6641 pa = VM_PAGE_TO_PHYS(m);
6642 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6643 if ((flags & VM_PROT_WRITE) != 0)
6645 if ((prot & VM_PROT_WRITE) != 0)
6647 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6648 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6649 if ((prot & VM_PROT_EXECUTE) == 0)
6651 if ((flags & PMAP_ENTER_WIRED) != 0)
6653 if (va < VM_MAXUSER_ADDRESS)
6655 if (pmap == kernel_pmap)
6657 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6660 * Set modified bit gratuitously for writeable mappings if
6661 * the page is unmanaged. We do not want to take a fault
6662 * to do the dirty bit accounting for these mappings.
6664 if ((m->oflags & VPO_UNMANAGED) != 0) {
6665 if ((newpte & PG_RW) != 0)
6668 newpte |= PG_MANAGED;
6672 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6673 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6674 ("managed largepage va %#lx flags %#x", va, flags));
6675 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6680 /* Assert the required virtual and physical alignment. */
6681 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6682 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6683 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6689 * In the case that a page table page is not
6690 * resident, we are creating it here.
6693 pde = pmap_pde(pmap, va);
6694 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6695 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6696 pte = pmap_pde_to_pte(pde, va);
6697 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6698 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6701 } else if (va < VM_MAXUSER_ADDRESS) {
6703 * Here if the pte page isn't mapped, or if it has been
6706 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6707 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6708 nosleep ? NULL : &lock, va);
6709 if (mpte == NULL && nosleep) {
6710 rv = KERN_RESOURCE_SHORTAGE;
6715 panic("pmap_enter: invalid page directory va=%#lx", va);
6719 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6720 newpte |= pmap_pkru_get(pmap, va);
6723 * Is the specified virtual address already mapped?
6725 if ((origpte & PG_V) != 0) {
6727 * Wiring change, just update stats. We don't worry about
6728 * wiring PT pages as they remain resident as long as there
6729 * are valid mappings in them. Hence, if a user page is wired,
6730 * the PT page will be also.
6732 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6733 pmap->pm_stats.wired_count++;
6734 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6735 pmap->pm_stats.wired_count--;
6738 * Remove the extra PT page reference.
6742 KASSERT(mpte->ref_count > 0,
6743 ("pmap_enter: missing reference to page table page,"
6748 * Has the physical page changed?
6750 opa = origpte & PG_FRAME;
6753 * No, might be a protection or wiring change.
6755 if ((origpte & PG_MANAGED) != 0 &&
6756 (newpte & PG_RW) != 0)
6757 vm_page_aflag_set(m, PGA_WRITEABLE);
6758 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6764 * The physical page has changed. Temporarily invalidate
6765 * the mapping. This ensures that all threads sharing the
6766 * pmap keep a consistent view of the mapping, which is
6767 * necessary for the correct handling of COW faults. It
6768 * also permits reuse of the old mapping's PV entry,
6769 * avoiding an allocation.
6771 * For consistency, handle unmanaged mappings the same way.
6773 origpte = pte_load_clear(pte);
6774 KASSERT((origpte & PG_FRAME) == opa,
6775 ("pmap_enter: unexpected pa update for %#lx", va));
6776 if ((origpte & PG_MANAGED) != 0) {
6777 om = PHYS_TO_VM_PAGE(opa);
6780 * The pmap lock is sufficient to synchronize with
6781 * concurrent calls to pmap_page_test_mappings() and
6782 * pmap_ts_referenced().
6784 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6786 if ((origpte & PG_A) != 0) {
6787 pmap_invalidate_page(pmap, va);
6788 vm_page_aflag_set(om, PGA_REFERENCED);
6790 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6791 pv = pmap_pvh_remove(&om->md, pmap, va);
6793 ("pmap_enter: no PV entry for %#lx", va));
6794 if ((newpte & PG_MANAGED) == 0)
6795 free_pv_entry(pmap, pv);
6796 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6797 TAILQ_EMPTY(&om->md.pv_list) &&
6798 ((om->flags & PG_FICTITIOUS) != 0 ||
6799 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6800 vm_page_aflag_clear(om, PGA_WRITEABLE);
6803 * Since this mapping is unmanaged, assume that PG_A
6806 pmap_invalidate_page(pmap, va);
6811 * Increment the counters.
6813 if ((newpte & PG_W) != 0)
6814 pmap->pm_stats.wired_count++;
6815 pmap_resident_count_inc(pmap, 1);
6819 * Enter on the PV list if part of our managed memory.
6821 if ((newpte & PG_MANAGED) != 0) {
6823 pv = get_pv_entry(pmap, &lock);
6826 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6827 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6829 if ((newpte & PG_RW) != 0)
6830 vm_page_aflag_set(m, PGA_WRITEABLE);
6836 if ((origpte & PG_V) != 0) {
6838 origpte = pte_load_store(pte, newpte);
6839 KASSERT((origpte & PG_FRAME) == pa,
6840 ("pmap_enter: unexpected pa update for %#lx", va));
6841 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6843 if ((origpte & PG_MANAGED) != 0)
6847 * Although the PTE may still have PG_RW set, TLB
6848 * invalidation may nonetheless be required because
6849 * the PTE no longer has PG_M set.
6851 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6853 * This PTE change does not require TLB invalidation.
6857 if ((origpte & PG_A) != 0)
6858 pmap_invalidate_page(pmap, va);
6860 pte_store(pte, newpte);
6864 #if VM_NRESERVLEVEL > 0
6866 * If both the page table page and the reservation are fully
6867 * populated, then attempt promotion.
6869 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6870 pmap_ps_enabled(pmap) &&
6871 (m->flags & PG_FICTITIOUS) == 0 &&
6872 vm_reserv_level_iffullpop(m) == 0)
6873 pmap_promote_pde(pmap, pde, va, &lock);
6885 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6886 * if successful. Returns false if (1) a page table page cannot be allocated
6887 * without sleeping, (2) a mapping already exists at the specified virtual
6888 * address, or (3) a PV entry cannot be allocated without reclaiming another
6892 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6893 struct rwlock **lockp)
6898 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6899 PG_V = pmap_valid_bit(pmap);
6900 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6902 if ((m->oflags & VPO_UNMANAGED) == 0)
6903 newpde |= PG_MANAGED;
6904 if ((prot & VM_PROT_EXECUTE) == 0)
6906 if (va < VM_MAXUSER_ADDRESS)
6908 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6909 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6914 * Returns true if every page table entry in the specified page table page is
6918 pmap_every_pte_zero(vm_paddr_t pa)
6920 pt_entry_t *pt_end, *pte;
6922 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6923 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6924 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6932 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6933 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6934 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6935 * a mapping already exists at the specified virtual address. Returns
6936 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6937 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6938 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6940 * The parameter "m" is only used when creating a managed, writeable mapping.
6943 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6944 vm_page_t m, struct rwlock **lockp)
6946 struct spglist free;
6947 pd_entry_t oldpde, *pde;
6948 pt_entry_t PG_G, PG_RW, PG_V;
6951 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6952 ("pmap_enter_pde: cannot create wired user mapping"));
6953 PG_G = pmap_global_bit(pmap);
6954 PG_RW = pmap_rw_bit(pmap);
6955 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6956 ("pmap_enter_pde: newpde is missing PG_M"));
6957 PG_V = pmap_valid_bit(pmap);
6958 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6960 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6962 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6963 " in pmap %p", va, pmap);
6964 return (KERN_FAILURE);
6966 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6967 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6968 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6969 " in pmap %p", va, pmap);
6970 return (KERN_RESOURCE_SHORTAGE);
6974 * If pkru is not same for the whole pde range, return failure
6975 * and let vm_fault() cope. Check after pde allocation, since
6978 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6979 pmap_abort_ptp(pmap, va, pdpg);
6980 return (KERN_FAILURE);
6982 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6983 newpde &= ~X86_PG_PKU_MASK;
6984 newpde |= pmap_pkru_get(pmap, va);
6988 * If there are existing mappings, either abort or remove them.
6991 if ((oldpde & PG_V) != 0) {
6992 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6993 ("pmap_enter_pde: pdpg's reference count is too low"));
6994 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6995 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6996 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6999 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7000 " in pmap %p", va, pmap);
7001 return (KERN_FAILURE);
7003 /* Break the existing mapping(s). */
7005 if ((oldpde & PG_PS) != 0) {
7007 * The reference to the PD page that was acquired by
7008 * pmap_alloc_pde() ensures that it won't be freed.
7009 * However, if the PDE resulted from a promotion, then
7010 * a reserved PT page could be freed.
7012 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
7013 if ((oldpde & PG_G) == 0)
7014 pmap_invalidate_pde_page(pmap, va, oldpde);
7016 pmap_delayed_invl_start();
7017 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
7019 pmap_invalidate_all(pmap);
7020 pmap_delayed_invl_finish();
7022 if (va < VM_MAXUSER_ADDRESS) {
7023 vm_page_free_pages_toq(&free, true);
7024 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7027 KASSERT(SLIST_EMPTY(&free),
7028 ("pmap_enter_pde: freed kernel page table page"));
7031 * Both pmap_remove_pde() and pmap_remove_ptes() will
7032 * leave the kernel page table page zero filled.
7034 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7035 if (pmap_insert_pt_page(pmap, mt, false))
7036 panic("pmap_enter_pde: trie insert failed");
7040 if ((newpde & PG_MANAGED) != 0) {
7042 * Abort this mapping if its PV entry could not be created.
7044 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7046 pmap_abort_ptp(pmap, va, pdpg);
7047 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7048 " in pmap %p", va, pmap);
7049 return (KERN_RESOURCE_SHORTAGE);
7051 if ((newpde & PG_RW) != 0) {
7052 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7053 vm_page_aflag_set(mt, PGA_WRITEABLE);
7058 * Increment counters.
7060 if ((newpde & PG_W) != 0)
7061 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7062 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7065 * Map the superpage. (This is not a promoted mapping; there will not
7066 * be any lingering 4KB page mappings in the TLB.)
7068 pde_store(pde, newpde);
7070 atomic_add_long(&pmap_pde_mappings, 1);
7071 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7073 return (KERN_SUCCESS);
7077 * Maps a sequence of resident pages belonging to the same object.
7078 * The sequence begins with the given page m_start. This page is
7079 * mapped at the given virtual address start. Each subsequent page is
7080 * mapped at a virtual address that is offset from start by the same
7081 * amount as the page is offset from m_start within the object. The
7082 * last page in the sequence is the page with the largest offset from
7083 * m_start that can be mapped at a virtual address less than the given
7084 * virtual address end. Not every virtual page between start and end
7085 * is mapped; only those for which a resident page exists with the
7086 * corresponding offset from m_start are mapped.
7089 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7090 vm_page_t m_start, vm_prot_t prot)
7092 struct rwlock *lock;
7095 vm_pindex_t diff, psize;
7097 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7099 psize = atop(end - start);
7104 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7105 va = start + ptoa(diff);
7106 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7107 m->psind == 1 && pmap_ps_enabled(pmap) &&
7108 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7109 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7110 m = &m[NBPDR / PAGE_SIZE - 1];
7112 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7114 m = TAILQ_NEXT(m, listq);
7122 * this code makes some *MAJOR* assumptions:
7123 * 1. Current pmap & pmap exists.
7126 * 4. No page table pages.
7127 * but is *MUCH* faster than pmap_enter...
7131 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7133 struct rwlock *lock;
7137 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7144 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7145 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7147 pt_entry_t newpte, *pte, PG_V;
7149 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7150 (m->oflags & VPO_UNMANAGED) != 0,
7151 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7152 PG_V = pmap_valid_bit(pmap);
7153 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7156 * In the case that a page table page is not
7157 * resident, we are creating it here.
7159 if (va < VM_MAXUSER_ADDRESS) {
7160 vm_pindex_t ptepindex;
7164 * Calculate pagetable page index
7166 ptepindex = pmap_pde_pindex(va);
7167 if (mpte && (mpte->pindex == ptepindex)) {
7171 * Get the page directory entry
7173 ptepa = pmap_pde(pmap, va);
7176 * If the page table page is mapped, we just increment
7177 * the hold count, and activate it. Otherwise, we
7178 * attempt to allocate a page table page. If this
7179 * attempt fails, we don't retry. Instead, we give up.
7181 if (ptepa && (*ptepa & PG_V) != 0) {
7184 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7188 * Pass NULL instead of the PV list lock
7189 * pointer, because we don't intend to sleep.
7191 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7197 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7198 pte = &pte[pmap_pte_index(va)];
7210 * Enter on the PV list if part of our managed memory.
7212 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7213 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7215 pmap_abort_ptp(pmap, va, mpte);
7220 * Increment counters
7222 pmap_resident_count_inc(pmap, 1);
7224 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7225 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7226 if ((m->oflags & VPO_UNMANAGED) == 0)
7227 newpte |= PG_MANAGED;
7228 if ((prot & VM_PROT_EXECUTE) == 0)
7230 if (va < VM_MAXUSER_ADDRESS)
7231 newpte |= PG_U | pmap_pkru_get(pmap, va);
7232 pte_store(pte, newpte);
7237 * Make a temporary mapping for a physical address. This is only intended
7238 * to be used for panic dumps.
7241 pmap_kenter_temporary(vm_paddr_t pa, int i)
7245 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7246 pmap_kenter(va, pa);
7248 return ((void *)crashdumpmap);
7252 * This code maps large physical mmap regions into the
7253 * processor address space. Note that some shortcuts
7254 * are taken, but the code works.
7257 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7258 vm_pindex_t pindex, vm_size_t size)
7261 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7262 vm_paddr_t pa, ptepa;
7266 PG_A = pmap_accessed_bit(pmap);
7267 PG_M = pmap_modified_bit(pmap);
7268 PG_V = pmap_valid_bit(pmap);
7269 PG_RW = pmap_rw_bit(pmap);
7271 VM_OBJECT_ASSERT_WLOCKED(object);
7272 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7273 ("pmap_object_init_pt: non-device object"));
7274 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7275 if (!pmap_ps_enabled(pmap))
7277 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7279 p = vm_page_lookup(object, pindex);
7280 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7281 ("pmap_object_init_pt: invalid page %p", p));
7282 pat_mode = p->md.pat_mode;
7285 * Abort the mapping if the first page is not physically
7286 * aligned to a 2MB page boundary.
7288 ptepa = VM_PAGE_TO_PHYS(p);
7289 if (ptepa & (NBPDR - 1))
7293 * Skip the first page. Abort the mapping if the rest of
7294 * the pages are not physically contiguous or have differing
7295 * memory attributes.
7297 p = TAILQ_NEXT(p, listq);
7298 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7300 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7301 ("pmap_object_init_pt: invalid page %p", p));
7302 if (pa != VM_PAGE_TO_PHYS(p) ||
7303 pat_mode != p->md.pat_mode)
7305 p = TAILQ_NEXT(p, listq);
7309 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7310 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7311 * will not affect the termination of this loop.
7314 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7315 pa < ptepa + size; pa += NBPDR) {
7316 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7319 * The creation of mappings below is only an
7320 * optimization. If a page directory page
7321 * cannot be allocated without blocking,
7322 * continue on to the next mapping rather than
7328 if ((*pde & PG_V) == 0) {
7329 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7330 PG_U | PG_RW | PG_V);
7331 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7332 atomic_add_long(&pmap_pde_mappings, 1);
7334 /* Continue on if the PDE is already valid. */
7336 KASSERT(pdpg->ref_count > 0,
7337 ("pmap_object_init_pt: missing reference "
7338 "to page directory page, va: 0x%lx", addr));
7347 * Clear the wired attribute from the mappings for the specified range of
7348 * addresses in the given pmap. Every valid mapping within that range
7349 * must have the wired attribute set. In contrast, invalid mappings
7350 * cannot have the wired attribute set, so they are ignored.
7352 * The wired attribute of the page table entry is not a hardware
7353 * feature, so there is no need to invalidate any TLB entries.
7354 * Since pmap_demote_pde() for the wired entry must never fail,
7355 * pmap_delayed_invl_start()/finish() calls around the
7356 * function are not needed.
7359 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7361 vm_offset_t va_next;
7362 pml4_entry_t *pml4e;
7365 pt_entry_t *pte, PG_V, PG_G;
7367 PG_V = pmap_valid_bit(pmap);
7368 PG_G = pmap_global_bit(pmap);
7370 for (; sva < eva; sva = va_next) {
7371 pml4e = pmap_pml4e(pmap, sva);
7372 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7373 va_next = (sva + NBPML4) & ~PML4MASK;
7379 va_next = (sva + NBPDP) & ~PDPMASK;
7382 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7383 if ((*pdpe & PG_V) == 0)
7385 if ((*pdpe & PG_PS) != 0) {
7386 KASSERT(va_next <= eva,
7387 ("partial update of non-transparent 1G mapping "
7388 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7389 *pdpe, sva, eva, va_next));
7390 MPASS(pmap != kernel_pmap); /* XXXKIB */
7391 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7392 atomic_clear_long(pdpe, PG_W);
7393 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7397 va_next = (sva + NBPDR) & ~PDRMASK;
7400 pde = pmap_pdpe_to_pde(pdpe, sva);
7401 if ((*pde & PG_V) == 0)
7403 if ((*pde & PG_PS) != 0) {
7404 if ((*pde & PG_W) == 0)
7405 panic("pmap_unwire: pde %#jx is missing PG_W",
7409 * Are we unwiring the entire large page? If not,
7410 * demote the mapping and fall through.
7412 if (sva + NBPDR == va_next && eva >= va_next) {
7413 atomic_clear_long(pde, PG_W);
7414 pmap->pm_stats.wired_count -= NBPDR /
7417 } else if (!pmap_demote_pde(pmap, pde, sva))
7418 panic("pmap_unwire: demotion failed");
7422 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7424 if ((*pte & PG_V) == 0)
7426 if ((*pte & PG_W) == 0)
7427 panic("pmap_unwire: pte %#jx is missing PG_W",
7431 * PG_W must be cleared atomically. Although the pmap
7432 * lock synchronizes access to PG_W, another processor
7433 * could be setting PG_M and/or PG_A concurrently.
7435 atomic_clear_long(pte, PG_W);
7436 pmap->pm_stats.wired_count--;
7443 * Copy the range specified by src_addr/len
7444 * from the source map to the range dst_addr/len
7445 * in the destination map.
7447 * This routine is only advisory and need not do anything.
7450 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7451 vm_offset_t src_addr)
7453 struct rwlock *lock;
7454 pml4_entry_t *pml4e;
7456 pd_entry_t *pde, srcptepaddr;
7457 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7458 vm_offset_t addr, end_addr, va_next;
7459 vm_page_t dst_pdpg, dstmpte, srcmpte;
7461 if (dst_addr != src_addr)
7464 if (dst_pmap->pm_type != src_pmap->pm_type)
7468 * EPT page table entries that require emulation of A/D bits are
7469 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7470 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7471 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7472 * implementations flag an EPT misconfiguration for exec-only
7473 * mappings we skip this function entirely for emulated pmaps.
7475 if (pmap_emulate_ad_bits(dst_pmap))
7478 end_addr = src_addr + len;
7480 if (dst_pmap < src_pmap) {
7481 PMAP_LOCK(dst_pmap);
7482 PMAP_LOCK(src_pmap);
7484 PMAP_LOCK(src_pmap);
7485 PMAP_LOCK(dst_pmap);
7488 PG_A = pmap_accessed_bit(dst_pmap);
7489 PG_M = pmap_modified_bit(dst_pmap);
7490 PG_V = pmap_valid_bit(dst_pmap);
7492 for (addr = src_addr; addr < end_addr; addr = va_next) {
7493 KASSERT(addr < UPT_MIN_ADDRESS,
7494 ("pmap_copy: invalid to pmap_copy page tables"));
7496 pml4e = pmap_pml4e(src_pmap, addr);
7497 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7498 va_next = (addr + NBPML4) & ~PML4MASK;
7504 va_next = (addr + NBPDP) & ~PDPMASK;
7507 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7508 if ((*pdpe & PG_V) == 0)
7510 if ((*pdpe & PG_PS) != 0) {
7511 KASSERT(va_next <= end_addr,
7512 ("partial update of non-transparent 1G mapping "
7513 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7514 *pdpe, addr, end_addr, va_next));
7515 MPASS((addr & PDPMASK) == 0);
7516 MPASS((*pdpe & PG_MANAGED) == 0);
7517 srcptepaddr = *pdpe;
7518 pdpe = pmap_pdpe(dst_pmap, addr);
7520 if (_pmap_allocpte(dst_pmap,
7521 pmap_pml4e_pindex(addr), NULL, addr) ==
7524 pdpe = pmap_pdpe(dst_pmap, addr);
7526 pml4e = pmap_pml4e(dst_pmap, addr);
7527 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7528 dst_pdpg->ref_count++;
7531 ("1G mapping present in dst pmap "
7532 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7533 *pdpe, addr, end_addr, va_next));
7534 *pdpe = srcptepaddr & ~PG_W;
7535 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7539 va_next = (addr + NBPDR) & ~PDRMASK;
7543 pde = pmap_pdpe_to_pde(pdpe, addr);
7545 if (srcptepaddr == 0)
7548 if (srcptepaddr & PG_PS) {
7549 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7551 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7554 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7555 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7556 PMAP_ENTER_NORECLAIM, &lock))) {
7557 *pde = srcptepaddr & ~PG_W;
7558 pmap_resident_count_inc(dst_pmap, NBPDR /
7560 atomic_add_long(&pmap_pde_mappings, 1);
7562 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7566 srcptepaddr &= PG_FRAME;
7567 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7568 KASSERT(srcmpte->ref_count > 0,
7569 ("pmap_copy: source page table page is unused"));
7571 if (va_next > end_addr)
7574 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7575 src_pte = &src_pte[pmap_pte_index(addr)];
7577 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7581 * We only virtual copy managed pages.
7583 if ((ptetemp & PG_MANAGED) == 0)
7586 if (dstmpte != NULL) {
7587 KASSERT(dstmpte->pindex ==
7588 pmap_pde_pindex(addr),
7589 ("dstmpte pindex/addr mismatch"));
7590 dstmpte->ref_count++;
7591 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7594 dst_pte = (pt_entry_t *)
7595 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7596 dst_pte = &dst_pte[pmap_pte_index(addr)];
7597 if (*dst_pte == 0 &&
7598 pmap_try_insert_pv_entry(dst_pmap, addr,
7599 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7601 * Clear the wired, modified, and accessed
7602 * (referenced) bits during the copy.
7604 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7605 pmap_resident_count_inc(dst_pmap, 1);
7607 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7610 /* Have we copied all of the valid mappings? */
7611 if (dstmpte->ref_count >= srcmpte->ref_count)
7618 PMAP_UNLOCK(src_pmap);
7619 PMAP_UNLOCK(dst_pmap);
7623 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7627 if (dst_pmap->pm_type != src_pmap->pm_type ||
7628 dst_pmap->pm_type != PT_X86 ||
7629 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7632 if (dst_pmap < src_pmap) {
7633 PMAP_LOCK(dst_pmap);
7634 PMAP_LOCK(src_pmap);
7636 PMAP_LOCK(src_pmap);
7637 PMAP_LOCK(dst_pmap);
7639 error = pmap_pkru_copy(dst_pmap, src_pmap);
7640 /* Clean up partial copy on failure due to no memory. */
7641 if (error == ENOMEM)
7642 pmap_pkru_deassign_all(dst_pmap);
7643 PMAP_UNLOCK(src_pmap);
7644 PMAP_UNLOCK(dst_pmap);
7645 if (error != ENOMEM)
7653 * Zero the specified hardware page.
7656 pmap_zero_page(vm_page_t m)
7658 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7660 pagezero((void *)va);
7664 * Zero an an area within a single hardware page. off and size must not
7665 * cover an area beyond a single hardware page.
7668 pmap_zero_page_area(vm_page_t m, int off, int size)
7670 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7672 if (off == 0 && size == PAGE_SIZE)
7673 pagezero((void *)va);
7675 bzero((char *)va + off, size);
7679 * Copy 1 specified hardware page to another.
7682 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7684 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7685 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7687 pagecopy((void *)src, (void *)dst);
7690 int unmapped_buf_allowed = 1;
7693 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7694 vm_offset_t b_offset, int xfersize)
7698 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7702 while (xfersize > 0) {
7703 a_pg_offset = a_offset & PAGE_MASK;
7704 pages[0] = ma[a_offset >> PAGE_SHIFT];
7705 b_pg_offset = b_offset & PAGE_MASK;
7706 pages[1] = mb[b_offset >> PAGE_SHIFT];
7707 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7708 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7709 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7710 a_cp = (char *)vaddr[0] + a_pg_offset;
7711 b_cp = (char *)vaddr[1] + b_pg_offset;
7712 bcopy(a_cp, b_cp, cnt);
7713 if (__predict_false(mapped))
7714 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7722 * Returns true if the pmap's pv is one of the first
7723 * 16 pvs linked to from this page. This count may
7724 * be changed upwards or downwards in the future; it
7725 * is only necessary that true be returned for a small
7726 * subset of pmaps for proper page aging.
7729 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7731 struct md_page *pvh;
7732 struct rwlock *lock;
7737 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7738 ("pmap_page_exists_quick: page %p is not managed", m));
7740 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7742 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7743 if (PV_PMAP(pv) == pmap) {
7751 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7752 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7753 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7754 if (PV_PMAP(pv) == pmap) {
7768 * pmap_page_wired_mappings:
7770 * Return the number of managed mappings to the given physical page
7774 pmap_page_wired_mappings(vm_page_t m)
7776 struct rwlock *lock;
7777 struct md_page *pvh;
7781 int count, md_gen, pvh_gen;
7783 if ((m->oflags & VPO_UNMANAGED) != 0)
7785 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7789 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7791 if (!PMAP_TRYLOCK(pmap)) {
7792 md_gen = m->md.pv_gen;
7796 if (md_gen != m->md.pv_gen) {
7801 pte = pmap_pte(pmap, pv->pv_va);
7802 if ((*pte & PG_W) != 0)
7806 if ((m->flags & PG_FICTITIOUS) == 0) {
7807 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7808 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7810 if (!PMAP_TRYLOCK(pmap)) {
7811 md_gen = m->md.pv_gen;
7812 pvh_gen = pvh->pv_gen;
7816 if (md_gen != m->md.pv_gen ||
7817 pvh_gen != pvh->pv_gen) {
7822 pte = pmap_pde(pmap, pv->pv_va);
7823 if ((*pte & PG_W) != 0)
7833 * Returns TRUE if the given page is mapped individually or as part of
7834 * a 2mpage. Otherwise, returns FALSE.
7837 pmap_page_is_mapped(vm_page_t m)
7839 struct rwlock *lock;
7842 if ((m->oflags & VPO_UNMANAGED) != 0)
7844 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7846 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7847 ((m->flags & PG_FICTITIOUS) == 0 &&
7848 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7854 * Destroy all managed, non-wired mappings in the given user-space
7855 * pmap. This pmap cannot be active on any processor besides the
7858 * This function cannot be applied to the kernel pmap. Moreover, it
7859 * is not intended for general use. It is only to be used during
7860 * process termination. Consequently, it can be implemented in ways
7861 * that make it faster than pmap_remove(). First, it can more quickly
7862 * destroy mappings by iterating over the pmap's collection of PV
7863 * entries, rather than searching the page table. Second, it doesn't
7864 * have to test and clear the page table entries atomically, because
7865 * no processor is currently accessing the user address space. In
7866 * particular, a page table entry's dirty bit won't change state once
7867 * this function starts.
7869 * Although this function destroys all of the pmap's managed,
7870 * non-wired mappings, it can delay and batch the invalidation of TLB
7871 * entries without calling pmap_delayed_invl_start() and
7872 * pmap_delayed_invl_finish(). Because the pmap is not active on
7873 * any other processor, none of these TLB entries will ever be used
7874 * before their eventual invalidation. Consequently, there is no need
7875 * for either pmap_remove_all() or pmap_remove_write() to wait for
7876 * that eventual TLB invalidation.
7879 pmap_remove_pages(pmap_t pmap)
7882 pt_entry_t *pte, tpte;
7883 pt_entry_t PG_M, PG_RW, PG_V;
7884 struct spglist free;
7885 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7886 vm_page_t m, mpte, mt;
7888 struct md_page *pvh;
7889 struct pv_chunk *pc, *npc;
7890 struct rwlock *lock;
7892 uint64_t inuse, bitmask;
7893 int allfree, field, freed, i, idx;
7894 boolean_t superpage;
7898 * Assert that the given pmap is only active on the current
7899 * CPU. Unfortunately, we cannot block another CPU from
7900 * activating the pmap while this function is executing.
7902 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7905 cpuset_t other_cpus;
7907 other_cpus = all_cpus;
7909 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7910 CPU_AND(&other_cpus, &pmap->pm_active);
7912 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7917 PG_M = pmap_modified_bit(pmap);
7918 PG_V = pmap_valid_bit(pmap);
7919 PG_RW = pmap_rw_bit(pmap);
7921 for (i = 0; i < PMAP_MEMDOM; i++)
7922 TAILQ_INIT(&free_chunks[i]);
7925 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7928 for (field = 0; field < _NPCM; field++) {
7929 inuse = ~pc->pc_map[field] & pc_freemask[field];
7930 while (inuse != 0) {
7932 bitmask = 1UL << bit;
7933 idx = field * 64 + bit;
7934 pv = &pc->pc_pventry[idx];
7937 pte = pmap_pdpe(pmap, pv->pv_va);
7939 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7941 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7944 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7946 pte = &pte[pmap_pte_index(pv->pv_va)];
7950 * Keep track whether 'tpte' is a
7951 * superpage explicitly instead of
7952 * relying on PG_PS being set.
7954 * This is because PG_PS is numerically
7955 * identical to PG_PTE_PAT and thus a
7956 * regular page could be mistaken for
7962 if ((tpte & PG_V) == 0) {
7963 panic("bad pte va %lx pte %lx",
7968 * We cannot remove wired pages from a process' mapping at this time
7976 pa = tpte & PG_PS_FRAME;
7978 pa = tpte & PG_FRAME;
7980 m = PHYS_TO_VM_PAGE(pa);
7981 KASSERT(m->phys_addr == pa,
7982 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7983 m, (uintmax_t)m->phys_addr,
7986 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7987 m < &vm_page_array[vm_page_array_size],
7988 ("pmap_remove_pages: bad tpte %#jx",
7994 * Update the vm_page_t clean/reference bits.
7996 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7998 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8004 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
8007 pc->pc_map[field] |= bitmask;
8009 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
8010 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
8011 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8013 if (TAILQ_EMPTY(&pvh->pv_list)) {
8014 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
8015 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
8016 TAILQ_EMPTY(&mt->md.pv_list))
8017 vm_page_aflag_clear(mt, PGA_WRITEABLE);
8019 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
8021 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
8022 ("pmap_remove_pages: pte page not promoted"));
8023 pmap_resident_count_dec(pmap, 1);
8024 KASSERT(mpte->ref_count == NPTEPG,
8025 ("pmap_remove_pages: pte page reference count error"));
8026 mpte->ref_count = 0;
8027 pmap_add_delayed_free_list(mpte, &free, FALSE);
8030 pmap_resident_count_dec(pmap, 1);
8031 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8033 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8034 TAILQ_EMPTY(&m->md.pv_list) &&
8035 (m->flags & PG_FICTITIOUS) == 0) {
8036 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8037 if (TAILQ_EMPTY(&pvh->pv_list))
8038 vm_page_aflag_clear(m, PGA_WRITEABLE);
8041 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8045 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
8046 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
8047 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
8049 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8050 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8055 pmap_invalidate_all(pmap);
8056 pmap_pkru_deassign_all(pmap);
8057 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8059 vm_page_free_pages_toq(&free, true);
8063 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8065 struct rwlock *lock;
8067 struct md_page *pvh;
8068 pt_entry_t *pte, mask;
8069 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8071 int md_gen, pvh_gen;
8075 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8078 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8080 if (!PMAP_TRYLOCK(pmap)) {
8081 md_gen = m->md.pv_gen;
8085 if (md_gen != m->md.pv_gen) {
8090 pte = pmap_pte(pmap, pv->pv_va);
8093 PG_M = pmap_modified_bit(pmap);
8094 PG_RW = pmap_rw_bit(pmap);
8095 mask |= PG_RW | PG_M;
8098 PG_A = pmap_accessed_bit(pmap);
8099 PG_V = pmap_valid_bit(pmap);
8100 mask |= PG_V | PG_A;
8102 rv = (*pte & mask) == mask;
8107 if ((m->flags & PG_FICTITIOUS) == 0) {
8108 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8109 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8111 if (!PMAP_TRYLOCK(pmap)) {
8112 md_gen = m->md.pv_gen;
8113 pvh_gen = pvh->pv_gen;
8117 if (md_gen != m->md.pv_gen ||
8118 pvh_gen != pvh->pv_gen) {
8123 pte = pmap_pde(pmap, pv->pv_va);
8126 PG_M = pmap_modified_bit(pmap);
8127 PG_RW = pmap_rw_bit(pmap);
8128 mask |= PG_RW | PG_M;
8131 PG_A = pmap_accessed_bit(pmap);
8132 PG_V = pmap_valid_bit(pmap);
8133 mask |= PG_V | PG_A;
8135 rv = (*pte & mask) == mask;
8149 * Return whether or not the specified physical page was modified
8150 * in any physical maps.
8153 pmap_is_modified(vm_page_t m)
8156 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8157 ("pmap_is_modified: page %p is not managed", m));
8160 * If the page is not busied then this check is racy.
8162 if (!pmap_page_is_write_mapped(m))
8164 return (pmap_page_test_mappings(m, FALSE, TRUE));
8168 * pmap_is_prefaultable:
8170 * Return whether or not the specified virtual address is eligible
8174 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8177 pt_entry_t *pte, PG_V;
8180 PG_V = pmap_valid_bit(pmap);
8183 pde = pmap_pde(pmap, addr);
8184 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8185 pte = pmap_pde_to_pte(pde, addr);
8186 rv = (*pte & PG_V) == 0;
8193 * pmap_is_referenced:
8195 * Return whether or not the specified physical page was referenced
8196 * in any physical maps.
8199 pmap_is_referenced(vm_page_t m)
8202 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8203 ("pmap_is_referenced: page %p is not managed", m));
8204 return (pmap_page_test_mappings(m, TRUE, FALSE));
8208 * Clear the write and modified bits in each of the given page's mappings.
8211 pmap_remove_write(vm_page_t m)
8213 struct md_page *pvh;
8215 struct rwlock *lock;
8216 pv_entry_t next_pv, pv;
8218 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8220 int pvh_gen, md_gen;
8222 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8223 ("pmap_remove_write: page %p is not managed", m));
8225 vm_page_assert_busied(m);
8226 if (!pmap_page_is_write_mapped(m))
8229 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8230 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8231 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8234 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8236 if (!PMAP_TRYLOCK(pmap)) {
8237 pvh_gen = pvh->pv_gen;
8241 if (pvh_gen != pvh->pv_gen) {
8247 PG_RW = pmap_rw_bit(pmap);
8249 pde = pmap_pde(pmap, va);
8250 if ((*pde & PG_RW) != 0)
8251 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8252 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8253 ("inconsistent pv lock %p %p for page %p",
8254 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8257 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8259 if (!PMAP_TRYLOCK(pmap)) {
8260 pvh_gen = pvh->pv_gen;
8261 md_gen = m->md.pv_gen;
8265 if (pvh_gen != pvh->pv_gen ||
8266 md_gen != m->md.pv_gen) {
8272 PG_M = pmap_modified_bit(pmap);
8273 PG_RW = pmap_rw_bit(pmap);
8274 pde = pmap_pde(pmap, pv->pv_va);
8275 KASSERT((*pde & PG_PS) == 0,
8276 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8278 pte = pmap_pde_to_pte(pde, pv->pv_va);
8281 if (oldpte & PG_RW) {
8282 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8285 if ((oldpte & PG_M) != 0)
8287 pmap_invalidate_page(pmap, pv->pv_va);
8292 vm_page_aflag_clear(m, PGA_WRITEABLE);
8293 pmap_delayed_invl_wait(m);
8296 static __inline boolean_t
8297 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8300 if (!pmap_emulate_ad_bits(pmap))
8303 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8306 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8307 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8308 * if the EPT_PG_WRITE bit is set.
8310 if ((pte & EPT_PG_WRITE) != 0)
8314 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8316 if ((pte & EPT_PG_EXECUTE) == 0 ||
8317 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8324 * pmap_ts_referenced:
8326 * Return a count of reference bits for a page, clearing those bits.
8327 * It is not necessary for every reference bit to be cleared, but it
8328 * is necessary that 0 only be returned when there are truly no
8329 * reference bits set.
8331 * As an optimization, update the page's dirty field if a modified bit is
8332 * found while counting reference bits. This opportunistic update can be
8333 * performed at low cost and can eliminate the need for some future calls
8334 * to pmap_is_modified(). However, since this function stops after
8335 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8336 * dirty pages. Those dirty pages will only be detected by a future call
8337 * to pmap_is_modified().
8339 * A DI block is not needed within this function, because
8340 * invalidations are performed before the PV list lock is
8344 pmap_ts_referenced(vm_page_t m)
8346 struct md_page *pvh;
8349 struct rwlock *lock;
8350 pd_entry_t oldpde, *pde;
8351 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8354 int cleared, md_gen, not_cleared, pvh_gen;
8355 struct spglist free;
8358 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8359 ("pmap_ts_referenced: page %p is not managed", m));
8362 pa = VM_PAGE_TO_PHYS(m);
8363 lock = PHYS_TO_PV_LIST_LOCK(pa);
8364 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8368 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8369 goto small_mappings;
8375 if (!PMAP_TRYLOCK(pmap)) {
8376 pvh_gen = pvh->pv_gen;
8380 if (pvh_gen != pvh->pv_gen) {
8385 PG_A = pmap_accessed_bit(pmap);
8386 PG_M = pmap_modified_bit(pmap);
8387 PG_RW = pmap_rw_bit(pmap);
8389 pde = pmap_pde(pmap, pv->pv_va);
8391 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8393 * Although "oldpde" is mapping a 2MB page, because
8394 * this function is called at a 4KB page granularity,
8395 * we only update the 4KB page under test.
8399 if ((oldpde & PG_A) != 0) {
8401 * Since this reference bit is shared by 512 4KB
8402 * pages, it should not be cleared every time it is
8403 * tested. Apply a simple "hash" function on the
8404 * physical page number, the virtual superpage number,
8405 * and the pmap address to select one 4KB page out of
8406 * the 512 on which testing the reference bit will
8407 * result in clearing that reference bit. This
8408 * function is designed to avoid the selection of the
8409 * same 4KB page for every 2MB page mapping.
8411 * On demotion, a mapping that hasn't been referenced
8412 * is simply destroyed. To avoid the possibility of a
8413 * subsequent page fault on a demoted wired mapping,
8414 * always leave its reference bit set. Moreover,
8415 * since the superpage is wired, the current state of
8416 * its reference bit won't affect page replacement.
8418 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8419 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8420 (oldpde & PG_W) == 0) {
8421 if (safe_to_clear_referenced(pmap, oldpde)) {
8422 atomic_clear_long(pde, PG_A);
8423 pmap_invalidate_page(pmap, pv->pv_va);
8425 } else if (pmap_demote_pde_locked(pmap, pde,
8426 pv->pv_va, &lock)) {
8428 * Remove the mapping to a single page
8429 * so that a subsequent access may
8430 * repromote. Since the underlying
8431 * page table page is fully populated,
8432 * this removal never frees a page
8436 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8438 pte = pmap_pde_to_pte(pde, va);
8439 pmap_remove_pte(pmap, pte, va, *pde,
8441 pmap_invalidate_page(pmap, va);
8447 * The superpage mapping was removed
8448 * entirely and therefore 'pv' is no
8456 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8457 ("inconsistent pv lock %p %p for page %p",
8458 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8463 /* Rotate the PV list if it has more than one entry. */
8464 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8465 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8466 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8469 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8471 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8473 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8480 if (!PMAP_TRYLOCK(pmap)) {
8481 pvh_gen = pvh->pv_gen;
8482 md_gen = m->md.pv_gen;
8486 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8491 PG_A = pmap_accessed_bit(pmap);
8492 PG_M = pmap_modified_bit(pmap);
8493 PG_RW = pmap_rw_bit(pmap);
8494 pde = pmap_pde(pmap, pv->pv_va);
8495 KASSERT((*pde & PG_PS) == 0,
8496 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8498 pte = pmap_pde_to_pte(pde, pv->pv_va);
8499 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8501 if ((*pte & PG_A) != 0) {
8502 if (safe_to_clear_referenced(pmap, *pte)) {
8503 atomic_clear_long(pte, PG_A);
8504 pmap_invalidate_page(pmap, pv->pv_va);
8506 } else if ((*pte & PG_W) == 0) {
8508 * Wired pages cannot be paged out so
8509 * doing accessed bit emulation for
8510 * them is wasted effort. We do the
8511 * hard work for unwired pages only.
8513 pmap_remove_pte(pmap, pte, pv->pv_va,
8514 *pde, &free, &lock);
8515 pmap_invalidate_page(pmap, pv->pv_va);
8520 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8521 ("inconsistent pv lock %p %p for page %p",
8522 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8527 /* Rotate the PV list if it has more than one entry. */
8528 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8529 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8530 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8533 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8534 not_cleared < PMAP_TS_REFERENCED_MAX);
8537 vm_page_free_pages_toq(&free, true);
8538 return (cleared + not_cleared);
8542 * Apply the given advice to the specified range of addresses within the
8543 * given pmap. Depending on the advice, clear the referenced and/or
8544 * modified flags in each mapping and set the mapped page's dirty field.
8547 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8549 struct rwlock *lock;
8550 pml4_entry_t *pml4e;
8552 pd_entry_t oldpde, *pde;
8553 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8554 vm_offset_t va, va_next;
8558 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8562 * A/D bit emulation requires an alternate code path when clearing
8563 * the modified and accessed bits below. Since this function is
8564 * advisory in nature we skip it entirely for pmaps that require
8565 * A/D bit emulation.
8567 if (pmap_emulate_ad_bits(pmap))
8570 PG_A = pmap_accessed_bit(pmap);
8571 PG_G = pmap_global_bit(pmap);
8572 PG_M = pmap_modified_bit(pmap);
8573 PG_V = pmap_valid_bit(pmap);
8574 PG_RW = pmap_rw_bit(pmap);
8576 pmap_delayed_invl_start();
8578 for (; sva < eva; sva = va_next) {
8579 pml4e = pmap_pml4e(pmap, sva);
8580 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8581 va_next = (sva + NBPML4) & ~PML4MASK;
8587 va_next = (sva + NBPDP) & ~PDPMASK;
8590 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8591 if ((*pdpe & PG_V) == 0)
8593 if ((*pdpe & PG_PS) != 0) {
8594 KASSERT(va_next <= eva,
8595 ("partial update of non-transparent 1G mapping "
8596 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8597 *pdpe, sva, eva, va_next));
8601 va_next = (sva + NBPDR) & ~PDRMASK;
8604 pde = pmap_pdpe_to_pde(pdpe, sva);
8606 if ((oldpde & PG_V) == 0)
8608 else if ((oldpde & PG_PS) != 0) {
8609 if ((oldpde & PG_MANAGED) == 0)
8612 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8617 * The large page mapping was destroyed.
8623 * Unless the page mappings are wired, remove the
8624 * mapping to a single page so that a subsequent
8625 * access may repromote. Choosing the last page
8626 * within the address range [sva, min(va_next, eva))
8627 * generally results in more repromotions. Since the
8628 * underlying page table page is fully populated, this
8629 * removal never frees a page table page.
8631 if ((oldpde & PG_W) == 0) {
8637 ("pmap_advise: no address gap"));
8638 pte = pmap_pde_to_pte(pde, va);
8639 KASSERT((*pte & PG_V) != 0,
8640 ("pmap_advise: invalid PTE"));
8641 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8651 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8653 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8655 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8656 if (advice == MADV_DONTNEED) {
8658 * Future calls to pmap_is_modified()
8659 * can be avoided by making the page
8662 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8665 atomic_clear_long(pte, PG_M | PG_A);
8666 } else if ((*pte & PG_A) != 0)
8667 atomic_clear_long(pte, PG_A);
8671 if ((*pte & PG_G) != 0) {
8678 if (va != va_next) {
8679 pmap_invalidate_range(pmap, va, sva);
8684 pmap_invalidate_range(pmap, va, sva);
8687 pmap_invalidate_all(pmap);
8689 pmap_delayed_invl_finish();
8693 * Clear the modify bits on the specified physical page.
8696 pmap_clear_modify(vm_page_t m)
8698 struct md_page *pvh;
8700 pv_entry_t next_pv, pv;
8701 pd_entry_t oldpde, *pde;
8702 pt_entry_t *pte, PG_M, PG_RW;
8703 struct rwlock *lock;
8705 int md_gen, pvh_gen;
8707 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8708 ("pmap_clear_modify: page %p is not managed", m));
8709 vm_page_assert_busied(m);
8711 if (!pmap_page_is_write_mapped(m))
8713 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8714 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8715 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8718 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8720 if (!PMAP_TRYLOCK(pmap)) {
8721 pvh_gen = pvh->pv_gen;
8725 if (pvh_gen != pvh->pv_gen) {
8730 PG_M = pmap_modified_bit(pmap);
8731 PG_RW = pmap_rw_bit(pmap);
8733 pde = pmap_pde(pmap, va);
8735 /* If oldpde has PG_RW set, then it also has PG_M set. */
8736 if ((oldpde & PG_RW) != 0 &&
8737 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8738 (oldpde & PG_W) == 0) {
8740 * Write protect the mapping to a single page so that
8741 * a subsequent write access may repromote.
8743 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8744 pte = pmap_pde_to_pte(pde, va);
8745 atomic_clear_long(pte, PG_M | PG_RW);
8747 pmap_invalidate_page(pmap, va);
8751 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8753 if (!PMAP_TRYLOCK(pmap)) {
8754 md_gen = m->md.pv_gen;
8755 pvh_gen = pvh->pv_gen;
8759 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8764 PG_M = pmap_modified_bit(pmap);
8765 PG_RW = pmap_rw_bit(pmap);
8766 pde = pmap_pde(pmap, pv->pv_va);
8767 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8768 " a 2mpage in page %p's pv list", m));
8769 pte = pmap_pde_to_pte(pde, pv->pv_va);
8770 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8771 atomic_clear_long(pte, PG_M);
8772 pmap_invalidate_page(pmap, pv->pv_va);
8780 * Miscellaneous support routines follow
8783 /* Adjust the properties for a leaf page table entry. */
8784 static __inline void
8785 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8789 opte = *(u_long *)pte;
8791 npte = opte & ~mask;
8793 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8798 * Map a set of physical memory pages into the kernel virtual
8799 * address space. Return a pointer to where it is mapped. This
8800 * routine is intended to be used for mapping device memory,
8804 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8806 struct pmap_preinit_mapping *ppim;
8807 vm_offset_t va, offset;
8811 offset = pa & PAGE_MASK;
8812 size = round_page(offset + size);
8813 pa = trunc_page(pa);
8815 if (!pmap_initialized) {
8817 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8818 ppim = pmap_preinit_mapping + i;
8819 if (ppim->va == 0) {
8823 ppim->va = virtual_avail;
8824 virtual_avail += size;
8830 panic("%s: too many preinit mappings", __func__);
8833 * If we have a preinit mapping, re-use it.
8835 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8836 ppim = pmap_preinit_mapping + i;
8837 if (ppim->pa == pa && ppim->sz == size &&
8838 (ppim->mode == mode ||
8839 (flags & MAPDEV_SETATTR) == 0))
8840 return ((void *)(ppim->va + offset));
8843 * If the specified range of physical addresses fits within
8844 * the direct map window, use the direct map.
8846 if (pa < dmaplimit && pa + size <= dmaplimit) {
8847 va = PHYS_TO_DMAP(pa);
8848 if ((flags & MAPDEV_SETATTR) != 0) {
8849 PMAP_LOCK(kernel_pmap);
8850 i = pmap_change_props_locked(va, size,
8851 PROT_NONE, mode, flags);
8852 PMAP_UNLOCK(kernel_pmap);
8856 return ((void *)(va + offset));
8858 va = kva_alloc(size);
8860 panic("%s: Couldn't allocate KVA", __func__);
8862 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8863 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8864 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8865 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8866 pmap_invalidate_cache_range(va, va + tmpsize);
8867 return ((void *)(va + offset));
8871 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8874 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8879 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8882 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8886 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8889 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8894 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8897 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8898 MAPDEV_FLUSHCACHE));
8902 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8904 struct pmap_preinit_mapping *ppim;
8908 /* If we gave a direct map region in pmap_mapdev, do nothing */
8909 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8911 offset = va & PAGE_MASK;
8912 size = round_page(offset + size);
8913 va = trunc_page(va);
8914 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8915 ppim = pmap_preinit_mapping + i;
8916 if (ppim->va == va && ppim->sz == size) {
8917 if (pmap_initialized)
8923 if (va + size == virtual_avail)
8928 if (pmap_initialized) {
8929 pmap_qremove(va, atop(size));
8935 * Tries to demote a 1GB page mapping.
8938 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8940 pdp_entry_t newpdpe, oldpdpe;
8941 pd_entry_t *firstpde, newpde, *pde;
8942 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8946 PG_A = pmap_accessed_bit(pmap);
8947 PG_M = pmap_modified_bit(pmap);
8948 PG_V = pmap_valid_bit(pmap);
8949 PG_RW = pmap_rw_bit(pmap);
8951 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8953 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8954 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8955 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8956 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8957 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8958 " in pmap %p", va, pmap);
8961 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8962 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8963 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8964 KASSERT((oldpdpe & PG_A) != 0,
8965 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8966 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8967 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8971 * Initialize the page directory page.
8973 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8979 * Demote the mapping.
8984 * Invalidate a stale recursive mapping of the page directory page.
8986 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8988 pmap_pdpe_demotions++;
8989 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8990 " in pmap %p", va, pmap);
8995 * Sets the memory attribute for the specified page.
8998 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
9001 m->md.pat_mode = ma;
9004 * If "m" is a normal page, update its direct mapping. This update
9005 * can be relied upon to perform any cache operations that are
9006 * required for data coherence.
9008 if ((m->flags & PG_FICTITIOUS) == 0 &&
9009 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
9011 panic("memory attribute change on the direct map failed");
9015 * Changes the specified virtual address range's memory type to that given by
9016 * the parameter "mode". The specified virtual address range must be
9017 * completely contained within either the direct map or the kernel map. If
9018 * the virtual address range is contained within the kernel map, then the
9019 * memory type for each of the corresponding ranges of the direct map is also
9020 * changed. (The corresponding ranges of the direct map are those ranges that
9021 * map the same physical pages as the specified virtual address range.) These
9022 * changes to the direct map are necessary because Intel describes the
9023 * behavior of their processors as "undefined" if two or more mappings to the
9024 * same physical page have different memory types.
9026 * Returns zero if the change completed successfully, and either EINVAL or
9027 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9028 * of the virtual address range was not mapped, and ENOMEM is returned if
9029 * there was insufficient memory available to complete the change. In the
9030 * latter case, the memory type may have been changed on some part of the
9031 * virtual address range or the direct map.
9034 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9038 PMAP_LOCK(kernel_pmap);
9039 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9041 PMAP_UNLOCK(kernel_pmap);
9046 * Changes the specified virtual address range's protections to those
9047 * specified by "prot". Like pmap_change_attr(), protections for aliases
9048 * in the direct map are updated as well. Protections on aliasing mappings may
9049 * be a subset of the requested protections; for example, mappings in the direct
9050 * map are never executable.
9053 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9057 /* Only supported within the kernel map. */
9058 if (va < VM_MIN_KERNEL_ADDRESS)
9061 PMAP_LOCK(kernel_pmap);
9062 error = pmap_change_props_locked(va, size, prot, -1,
9063 MAPDEV_ASSERTVALID);
9064 PMAP_UNLOCK(kernel_pmap);
9069 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9070 int mode, int flags)
9072 vm_offset_t base, offset, tmpva;
9073 vm_paddr_t pa_start, pa_end, pa_end1;
9075 pd_entry_t *pde, pde_bits, pde_mask;
9076 pt_entry_t *pte, pte_bits, pte_mask;
9080 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9081 base = trunc_page(va);
9082 offset = va & PAGE_MASK;
9083 size = round_page(offset + size);
9086 * Only supported on kernel virtual addresses, including the direct
9087 * map but excluding the recursive map.
9089 if (base < DMAP_MIN_ADDRESS)
9093 * Construct our flag sets and masks. "bits" is the subset of
9094 * "mask" that will be set in each modified PTE.
9096 * Mappings in the direct map are never allowed to be executable.
9098 pde_bits = pte_bits = 0;
9099 pde_mask = pte_mask = 0;
9101 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9102 pde_mask |= X86_PG_PDE_CACHE;
9103 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9104 pte_mask |= X86_PG_PTE_CACHE;
9106 if (prot != VM_PROT_NONE) {
9107 if ((prot & VM_PROT_WRITE) != 0) {
9108 pde_bits |= X86_PG_RW;
9109 pte_bits |= X86_PG_RW;
9111 if ((prot & VM_PROT_EXECUTE) == 0 ||
9112 va < VM_MIN_KERNEL_ADDRESS) {
9116 pde_mask |= X86_PG_RW | pg_nx;
9117 pte_mask |= X86_PG_RW | pg_nx;
9121 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9122 * into 4KB pages if required.
9124 for (tmpva = base; tmpva < base + size; ) {
9125 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9126 if (pdpe == NULL || *pdpe == 0) {
9127 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9128 ("%s: addr %#lx is not mapped", __func__, tmpva));
9131 if (*pdpe & PG_PS) {
9133 * If the current 1GB page already has the required
9134 * properties, then we need not demote this page. Just
9135 * increment tmpva to the next 1GB page frame.
9137 if ((*pdpe & pde_mask) == pde_bits) {
9138 tmpva = trunc_1gpage(tmpva) + NBPDP;
9143 * If the current offset aligns with a 1GB page frame
9144 * and there is at least 1GB left within the range, then
9145 * we need not break down this page into 2MB pages.
9147 if ((tmpva & PDPMASK) == 0 &&
9148 tmpva + PDPMASK < base + size) {
9152 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9155 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9157 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9158 ("%s: addr %#lx is not mapped", __func__, tmpva));
9163 * If the current 2MB page already has the required
9164 * properties, then we need not demote this page. Just
9165 * increment tmpva to the next 2MB page frame.
9167 if ((*pde & pde_mask) == pde_bits) {
9168 tmpva = trunc_2mpage(tmpva) + NBPDR;
9173 * If the current offset aligns with a 2MB page frame
9174 * and there is at least 2MB left within the range, then
9175 * we need not break down this page into 4KB pages.
9177 if ((tmpva & PDRMASK) == 0 &&
9178 tmpva + PDRMASK < base + size) {
9182 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9185 pte = pmap_pde_to_pte(pde, tmpva);
9187 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9188 ("%s: addr %#lx is not mapped", __func__, tmpva));
9196 * Ok, all the pages exist, so run through them updating their
9197 * properties if required.
9200 pa_start = pa_end = 0;
9201 for (tmpva = base; tmpva < base + size; ) {
9202 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9203 if (*pdpe & PG_PS) {
9204 if ((*pdpe & pde_mask) != pde_bits) {
9205 pmap_pte_props(pdpe, pde_bits, pde_mask);
9208 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9209 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9210 if (pa_start == pa_end) {
9211 /* Start physical address run. */
9212 pa_start = *pdpe & PG_PS_FRAME;
9213 pa_end = pa_start + NBPDP;
9214 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9217 /* Run ended, update direct map. */
9218 error = pmap_change_props_locked(
9219 PHYS_TO_DMAP(pa_start),
9220 pa_end - pa_start, prot, mode,
9224 /* Start physical address run. */
9225 pa_start = *pdpe & PG_PS_FRAME;
9226 pa_end = pa_start + NBPDP;
9229 tmpva = trunc_1gpage(tmpva) + NBPDP;
9232 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9234 if ((*pde & pde_mask) != pde_bits) {
9235 pmap_pte_props(pde, pde_bits, pde_mask);
9238 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9239 (*pde & PG_PS_FRAME) < dmaplimit) {
9240 if (pa_start == pa_end) {
9241 /* Start physical address run. */
9242 pa_start = *pde & PG_PS_FRAME;
9243 pa_end = pa_start + NBPDR;
9244 } else if (pa_end == (*pde & PG_PS_FRAME))
9247 /* Run ended, update direct map. */
9248 error = pmap_change_props_locked(
9249 PHYS_TO_DMAP(pa_start),
9250 pa_end - pa_start, prot, mode,
9254 /* Start physical address run. */
9255 pa_start = *pde & PG_PS_FRAME;
9256 pa_end = pa_start + NBPDR;
9259 tmpva = trunc_2mpage(tmpva) + NBPDR;
9261 pte = pmap_pde_to_pte(pde, tmpva);
9262 if ((*pte & pte_mask) != pte_bits) {
9263 pmap_pte_props(pte, pte_bits, pte_mask);
9266 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9267 (*pte & PG_FRAME) < dmaplimit) {
9268 if (pa_start == pa_end) {
9269 /* Start physical address run. */
9270 pa_start = *pte & PG_FRAME;
9271 pa_end = pa_start + PAGE_SIZE;
9272 } else if (pa_end == (*pte & PG_FRAME))
9273 pa_end += PAGE_SIZE;
9275 /* Run ended, update direct map. */
9276 error = pmap_change_props_locked(
9277 PHYS_TO_DMAP(pa_start),
9278 pa_end - pa_start, prot, mode,
9282 /* Start physical address run. */
9283 pa_start = *pte & PG_FRAME;
9284 pa_end = pa_start + PAGE_SIZE;
9290 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9291 pa_end1 = MIN(pa_end, dmaplimit);
9292 if (pa_start != pa_end1)
9293 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9294 pa_end1 - pa_start, prot, mode, flags);
9298 * Flush CPU caches if required to make sure any data isn't cached that
9299 * shouldn't be, etc.
9302 pmap_invalidate_range(kernel_pmap, base, tmpva);
9303 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9304 pmap_invalidate_cache_range(base, tmpva);
9310 * Demotes any mapping within the direct map region that covers more than the
9311 * specified range of physical addresses. This range's size must be a power
9312 * of two and its starting address must be a multiple of its size. Since the
9313 * demotion does not change any attributes of the mapping, a TLB invalidation
9314 * is not mandatory. The caller may, however, request a TLB invalidation.
9317 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9326 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9327 KASSERT((base & (len - 1)) == 0,
9328 ("pmap_demote_DMAP: base is not a multiple of len"));
9329 if (len < NBPDP && base < dmaplimit) {
9330 va = PHYS_TO_DMAP(base);
9332 PMAP_LOCK(kernel_pmap);
9333 pdpe = pmap_pdpe(kernel_pmap, va);
9334 if ((*pdpe & X86_PG_V) == 0)
9335 panic("pmap_demote_DMAP: invalid PDPE");
9336 if ((*pdpe & PG_PS) != 0) {
9337 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9338 panic("pmap_demote_DMAP: PDPE failed");
9342 pde = pmap_pdpe_to_pde(pdpe, va);
9343 if ((*pde & X86_PG_V) == 0)
9344 panic("pmap_demote_DMAP: invalid PDE");
9345 if ((*pde & PG_PS) != 0) {
9346 if (!pmap_demote_pde(kernel_pmap, pde, va))
9347 panic("pmap_demote_DMAP: PDE failed");
9351 if (changed && invalidate)
9352 pmap_invalidate_page(kernel_pmap, va);
9353 PMAP_UNLOCK(kernel_pmap);
9358 * Perform the pmap work for mincore(2). If the page is not both referenced and
9359 * modified by this pmap, returns its physical address so that the caller can
9360 * find other mappings.
9363 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9367 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9371 PG_A = pmap_accessed_bit(pmap);
9372 PG_M = pmap_modified_bit(pmap);
9373 PG_V = pmap_valid_bit(pmap);
9374 PG_RW = pmap_rw_bit(pmap);
9380 pdpe = pmap_pdpe(pmap, addr);
9381 if ((*pdpe & PG_V) != 0) {
9382 if ((*pdpe & PG_PS) != 0) {
9384 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9386 val = MINCORE_PSIND(2);
9388 pdep = pmap_pde(pmap, addr);
9389 if (pdep != NULL && (*pdep & PG_V) != 0) {
9390 if ((*pdep & PG_PS) != 0) {
9392 /* Compute the physical address of the 4KB page. */
9393 pa = ((pte & PG_PS_FRAME) | (addr &
9394 PDRMASK)) & PG_FRAME;
9395 val = MINCORE_PSIND(1);
9397 pte = *pmap_pde_to_pte(pdep, addr);
9398 pa = pte & PG_FRAME;
9404 if ((pte & PG_V) != 0) {
9405 val |= MINCORE_INCORE;
9406 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9407 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9408 if ((pte & PG_A) != 0)
9409 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9411 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9412 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9413 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9421 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9423 uint32_t gen, new_gen, pcid_next;
9425 CRITICAL_ASSERT(curthread);
9426 gen = PCPU_GET(pcid_gen);
9427 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9428 return (pti ? 0 : CR3_PCID_SAVE);
9429 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9430 return (CR3_PCID_SAVE);
9431 pcid_next = PCPU_GET(pcid_next);
9432 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9433 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9434 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9435 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9436 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9440 PCPU_SET(pcid_gen, new_gen);
9441 pcid_next = PMAP_PCID_KERN + 1;
9445 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9446 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9447 PCPU_SET(pcid_next, pcid_next + 1);
9452 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9456 cached = pmap_pcid_alloc(pmap, cpuid);
9457 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9458 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9459 pmap->pm_pcids[cpuid].pm_pcid));
9460 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9461 pmap == kernel_pmap,
9462 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9463 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9468 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9471 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9472 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9476 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9479 uint64_t cached, cr3, kcr3, ucr3;
9481 KASSERT((read_rflags() & PSL_I) == 0,
9482 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9484 /* See the comment in pmap_invalidate_page_pcid(). */
9485 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9486 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9487 old_pmap = PCPU_GET(curpmap);
9488 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9489 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9492 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9494 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9495 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9496 PCPU_SET(curpmap, pmap);
9497 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9498 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9501 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9502 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9504 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9505 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9507 PCPU_INC(pm_save_cnt);
9509 pmap_activate_sw_pti_post(td, pmap);
9513 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9516 uint64_t cached, cr3;
9518 KASSERT((read_rflags() & PSL_I) == 0,
9519 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9521 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9523 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9524 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9526 PCPU_SET(curpmap, pmap);
9528 PCPU_INC(pm_save_cnt);
9532 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9533 u_int cpuid __unused)
9536 load_cr3(pmap->pm_cr3);
9537 PCPU_SET(curpmap, pmap);
9541 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9542 u_int cpuid __unused)
9545 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9546 PCPU_SET(kcr3, pmap->pm_cr3);
9547 PCPU_SET(ucr3, pmap->pm_ucr3);
9548 pmap_activate_sw_pti_post(td, pmap);
9551 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9555 if (pmap_pcid_enabled && pti)
9556 return (pmap_activate_sw_pcid_pti);
9557 else if (pmap_pcid_enabled && !pti)
9558 return (pmap_activate_sw_pcid_nopti);
9559 else if (!pmap_pcid_enabled && pti)
9560 return (pmap_activate_sw_nopcid_pti);
9561 else /* if (!pmap_pcid_enabled && !pti) */
9562 return (pmap_activate_sw_nopcid_nopti);
9566 pmap_activate_sw(struct thread *td)
9568 pmap_t oldpmap, pmap;
9571 oldpmap = PCPU_GET(curpmap);
9572 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9573 if (oldpmap == pmap) {
9574 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9578 cpuid = PCPU_GET(cpuid);
9580 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9582 CPU_SET(cpuid, &pmap->pm_active);
9584 pmap_activate_sw_mode(td, pmap, cpuid);
9586 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9588 CPU_CLR(cpuid, &oldpmap->pm_active);
9593 pmap_activate(struct thread *td)
9596 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9597 * invalidate_all IPI, which checks for curpmap ==
9598 * smp_tlb_pmap. The below sequence of operations has a
9599 * window where %CR3 is loaded with the new pmap's PML4
9600 * address, but the curpmap value has not yet been updated.
9601 * This causes the invltlb IPI handler, which is called
9602 * between the updates, to execute as a NOP, which leaves
9603 * stale TLB entries.
9605 * Note that the most common use of pmap_activate_sw(), from
9606 * a context switch, is immune to this race, because
9607 * interrupts are disabled (while the thread lock is owned),
9608 * so the IPI is delayed until after curpmap is updated. Protect
9609 * other callers in a similar way, by disabling interrupts
9610 * around the %cr3 register reload and curpmap assignment.
9613 pmap_activate_sw(td);
9618 pmap_activate_boot(pmap_t pmap)
9624 * kernel_pmap must be never deactivated, and we ensure that
9625 * by never activating it at all.
9627 MPASS(pmap != kernel_pmap);
9629 cpuid = PCPU_GET(cpuid);
9631 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9633 CPU_SET(cpuid, &pmap->pm_active);
9635 PCPU_SET(curpmap, pmap);
9637 kcr3 = pmap->pm_cr3;
9638 if (pmap_pcid_enabled)
9639 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9643 PCPU_SET(kcr3, kcr3);
9644 PCPU_SET(ucr3, PMAP_NO_CR3);
9648 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9653 * Increase the starting virtual address of the given mapping if a
9654 * different alignment might result in more superpage mappings.
9657 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9658 vm_offset_t *addr, vm_size_t size)
9660 vm_offset_t superpage_offset;
9664 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9665 offset += ptoa(object->pg_color);
9666 superpage_offset = offset & PDRMASK;
9667 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9668 (*addr & PDRMASK) == superpage_offset)
9670 if ((*addr & PDRMASK) < superpage_offset)
9671 *addr = (*addr & ~PDRMASK) + superpage_offset;
9673 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9677 static unsigned long num_dirty_emulations;
9678 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9679 &num_dirty_emulations, 0, NULL);
9681 static unsigned long num_accessed_emulations;
9682 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9683 &num_accessed_emulations, 0, NULL);
9685 static unsigned long num_superpage_accessed_emulations;
9686 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9687 &num_superpage_accessed_emulations, 0, NULL);
9689 static unsigned long ad_emulation_superpage_promotions;
9690 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9691 &ad_emulation_superpage_promotions, 0, NULL);
9692 #endif /* INVARIANTS */
9695 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9698 struct rwlock *lock;
9699 #if VM_NRESERVLEVEL > 0
9703 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9705 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9706 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9708 if (!pmap_emulate_ad_bits(pmap))
9711 PG_A = pmap_accessed_bit(pmap);
9712 PG_M = pmap_modified_bit(pmap);
9713 PG_V = pmap_valid_bit(pmap);
9714 PG_RW = pmap_rw_bit(pmap);
9720 pde = pmap_pde(pmap, va);
9721 if (pde == NULL || (*pde & PG_V) == 0)
9724 if ((*pde & PG_PS) != 0) {
9725 if (ftype == VM_PROT_READ) {
9727 atomic_add_long(&num_superpage_accessed_emulations, 1);
9735 pte = pmap_pde_to_pte(pde, va);
9736 if ((*pte & PG_V) == 0)
9739 if (ftype == VM_PROT_WRITE) {
9740 if ((*pte & PG_RW) == 0)
9743 * Set the modified and accessed bits simultaneously.
9745 * Intel EPT PTEs that do software emulation of A/D bits map
9746 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9747 * An EPT misconfiguration is triggered if the PTE is writable
9748 * but not readable (WR=10). This is avoided by setting PG_A
9749 * and PG_M simultaneously.
9751 *pte |= PG_M | PG_A;
9756 #if VM_NRESERVLEVEL > 0
9757 /* try to promote the mapping */
9758 if (va < VM_MAXUSER_ADDRESS)
9759 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9763 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9765 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9766 pmap_ps_enabled(pmap) &&
9767 (m->flags & PG_FICTITIOUS) == 0 &&
9768 vm_reserv_level_iffullpop(m) == 0) {
9769 pmap_promote_pde(pmap, pde, va, &lock);
9771 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9777 if (ftype == VM_PROT_WRITE)
9778 atomic_add_long(&num_dirty_emulations, 1);
9780 atomic_add_long(&num_accessed_emulations, 1);
9782 rv = 0; /* success */
9791 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9796 pt_entry_t *pte, PG_V;
9800 PG_V = pmap_valid_bit(pmap);
9803 pml4 = pmap_pml4e(pmap, va);
9807 if ((*pml4 & PG_V) == 0)
9810 pdp = pmap_pml4e_to_pdpe(pml4, va);
9812 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9815 pde = pmap_pdpe_to_pde(pdp, va);
9817 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9820 pte = pmap_pde_to_pte(pde, va);
9829 * Get the kernel virtual address of a set of physical pages. If there are
9830 * physical addresses not covered by the DMAP perform a transient mapping
9831 * that will be removed when calling pmap_unmap_io_transient.
9833 * \param page The pages the caller wishes to obtain the virtual
9834 * address on the kernel memory map.
9835 * \param vaddr On return contains the kernel virtual memory address
9836 * of the pages passed in the page parameter.
9837 * \param count Number of pages passed in.
9838 * \param can_fault TRUE if the thread using the mapped pages can take
9839 * page faults, FALSE otherwise.
9841 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9842 * finished or FALSE otherwise.
9846 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9847 boolean_t can_fault)
9850 boolean_t needs_mapping;
9852 int cache_bits, error __unused, i;
9855 * Allocate any KVA space that we need, this is done in a separate
9856 * loop to prevent calling vmem_alloc while pinned.
9858 needs_mapping = FALSE;
9859 for (i = 0; i < count; i++) {
9860 paddr = VM_PAGE_TO_PHYS(page[i]);
9861 if (__predict_false(paddr >= dmaplimit)) {
9862 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9863 M_BESTFIT | M_WAITOK, &vaddr[i]);
9864 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9865 needs_mapping = TRUE;
9867 vaddr[i] = PHYS_TO_DMAP(paddr);
9871 /* Exit early if everything is covered by the DMAP */
9876 * NB: The sequence of updating a page table followed by accesses
9877 * to the corresponding pages used in the !DMAP case is subject to
9878 * the situation described in the "AMD64 Architecture Programmer's
9879 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9880 * Coherency Considerations". Therefore, issuing the INVLPG right
9881 * after modifying the PTE bits is crucial.
9885 for (i = 0; i < count; i++) {
9886 paddr = VM_PAGE_TO_PHYS(page[i]);
9887 if (paddr >= dmaplimit) {
9890 * Slow path, since we can get page faults
9891 * while mappings are active don't pin the
9892 * thread to the CPU and instead add a global
9893 * mapping visible to all CPUs.
9895 pmap_qenter(vaddr[i], &page[i], 1);
9897 pte = vtopte(vaddr[i]);
9898 cache_bits = pmap_cache_bits(kernel_pmap,
9899 page[i]->md.pat_mode, 0);
9900 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9907 return (needs_mapping);
9911 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9912 boolean_t can_fault)
9919 for (i = 0; i < count; i++) {
9920 paddr = VM_PAGE_TO_PHYS(page[i]);
9921 if (paddr >= dmaplimit) {
9923 pmap_qremove(vaddr[i], 1);
9924 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9930 pmap_quick_enter_page(vm_page_t m)
9934 paddr = VM_PAGE_TO_PHYS(m);
9935 if (paddr < dmaplimit)
9936 return (PHYS_TO_DMAP(paddr));
9937 mtx_lock_spin(&qframe_mtx);
9938 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9939 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9940 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9945 pmap_quick_remove_page(vm_offset_t addr)
9950 pte_store(vtopte(qframe), 0);
9952 mtx_unlock_spin(&qframe_mtx);
9956 * Pdp pages from the large map are managed differently from either
9957 * kernel or user page table pages. They are permanently allocated at
9958 * initialization time, and their reference count is permanently set to
9959 * zero. The pml4 entries pointing to those pages are copied into
9960 * each allocated pmap.
9962 * In contrast, pd and pt pages are managed like user page table
9963 * pages. They are dynamically allocated, and their reference count
9964 * represents the number of valid entries within the page.
9967 pmap_large_map_getptp_unlocked(void)
9971 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9973 if (m != NULL && (m->flags & PG_ZERO) == 0)
9979 pmap_large_map_getptp(void)
9983 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9984 m = pmap_large_map_getptp_unlocked();
9986 PMAP_UNLOCK(kernel_pmap);
9988 PMAP_LOCK(kernel_pmap);
9989 /* Callers retry. */
9994 static pdp_entry_t *
9995 pmap_large_map_pdpe(vm_offset_t va)
9997 vm_pindex_t pml4_idx;
10000 pml4_idx = pmap_pml4e_index(va);
10001 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
10002 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
10004 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10005 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
10006 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
10007 "LMSPML4I %#jx lm_ents %d",
10008 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
10009 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
10010 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
10013 static pd_entry_t *
10014 pmap_large_map_pde(vm_offset_t va)
10021 pdpe = pmap_large_map_pdpe(va);
10023 m = pmap_large_map_getptp();
10026 mphys = VM_PAGE_TO_PHYS(m);
10027 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10029 MPASS((*pdpe & X86_PG_PS) == 0);
10030 mphys = *pdpe & PG_FRAME;
10032 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10035 static pt_entry_t *
10036 pmap_large_map_pte(vm_offset_t va)
10043 pde = pmap_large_map_pde(va);
10045 m = pmap_large_map_getptp();
10048 mphys = VM_PAGE_TO_PHYS(m);
10049 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10050 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10052 MPASS((*pde & X86_PG_PS) == 0);
10053 mphys = *pde & PG_FRAME;
10055 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10059 pmap_large_map_kextract(vm_offset_t va)
10061 pdp_entry_t *pdpe, pdp;
10062 pd_entry_t *pde, pd;
10063 pt_entry_t *pte, pt;
10065 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10066 ("not largemap range %#lx", (u_long)va));
10067 pdpe = pmap_large_map_pdpe(va);
10069 KASSERT((pdp & X86_PG_V) != 0,
10070 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10071 (u_long)pdpe, pdp));
10072 if ((pdp & X86_PG_PS) != 0) {
10073 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10074 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10075 (u_long)pdpe, pdp));
10076 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10078 pde = pmap_pdpe_to_pde(pdpe, va);
10080 KASSERT((pd & X86_PG_V) != 0,
10081 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10082 if ((pd & X86_PG_PS) != 0)
10083 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10084 pte = pmap_pde_to_pte(pde, va);
10086 KASSERT((pt & X86_PG_V) != 0,
10087 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10088 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10092 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10093 vmem_addr_t *vmem_res)
10097 * Large mappings are all but static. Consequently, there
10098 * is no point in waiting for an earlier allocation to be
10101 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10102 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10106 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10107 vm_memattr_t mattr)
10112 vm_offset_t va, inc;
10113 vmem_addr_t vmem_res;
10117 if (len == 0 || spa + len < spa)
10120 /* See if DMAP can serve. */
10121 if (spa + len <= dmaplimit) {
10122 va = PHYS_TO_DMAP(spa);
10123 *addr = (void *)va;
10124 return (pmap_change_attr(va, len, mattr));
10128 * No, allocate KVA. Fit the address with best possible
10129 * alignment for superpages. Fall back to worse align if
10133 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10134 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10135 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10137 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10139 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10142 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10147 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10148 * in the pagetable to minimize flushing. No need to
10149 * invalidate TLB, since we only update invalid entries.
10151 PMAP_LOCK(kernel_pmap);
10152 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10154 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10155 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10156 pdpe = pmap_large_map_pdpe(va);
10158 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10159 X86_PG_V | X86_PG_A | pg_nx |
10160 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10162 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10163 (va & PDRMASK) == 0) {
10164 pde = pmap_large_map_pde(va);
10166 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10167 X86_PG_V | X86_PG_A | pg_nx |
10168 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10169 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10173 pte = pmap_large_map_pte(va);
10175 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10176 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10178 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10183 PMAP_UNLOCK(kernel_pmap);
10186 *addr = (void *)vmem_res;
10191 pmap_large_unmap(void *svaa, vm_size_t len)
10193 vm_offset_t sva, va;
10195 pdp_entry_t *pdpe, pdp;
10196 pd_entry_t *pde, pd;
10199 struct spglist spgf;
10201 sva = (vm_offset_t)svaa;
10202 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10203 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10207 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10208 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10209 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10210 PMAP_LOCK(kernel_pmap);
10211 for (va = sva; va < sva + len; va += inc) {
10212 pdpe = pmap_large_map_pdpe(va);
10214 KASSERT((pdp & X86_PG_V) != 0,
10215 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10216 (u_long)pdpe, pdp));
10217 if ((pdp & X86_PG_PS) != 0) {
10218 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10219 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10220 (u_long)pdpe, pdp));
10221 KASSERT((va & PDPMASK) == 0,
10222 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10223 (u_long)pdpe, pdp));
10224 KASSERT(va + NBPDP <= sva + len,
10225 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10226 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10227 (u_long)pdpe, pdp, len));
10232 pde = pmap_pdpe_to_pde(pdpe, va);
10234 KASSERT((pd & X86_PG_V) != 0,
10235 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10237 if ((pd & X86_PG_PS) != 0) {
10238 KASSERT((va & PDRMASK) == 0,
10239 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10241 KASSERT(va + NBPDR <= sva + len,
10242 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10243 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10247 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10249 if (m->ref_count == 0) {
10251 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10255 pte = pmap_pde_to_pte(pde, va);
10256 KASSERT((*pte & X86_PG_V) != 0,
10257 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10258 (u_long)pte, *pte));
10261 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10263 if (m->ref_count == 0) {
10265 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10266 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10268 if (m->ref_count == 0) {
10270 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10274 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10275 PMAP_UNLOCK(kernel_pmap);
10276 vm_page_free_pages_toq(&spgf, false);
10277 vmem_free(large_vmem, sva, len);
10281 pmap_large_map_wb_fence_mfence(void)
10288 pmap_large_map_wb_fence_atomic(void)
10291 atomic_thread_fence_seq_cst();
10295 pmap_large_map_wb_fence_nop(void)
10299 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10302 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10303 return (pmap_large_map_wb_fence_mfence);
10304 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10305 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10306 return (pmap_large_map_wb_fence_atomic);
10308 /* clflush is strongly enough ordered */
10309 return (pmap_large_map_wb_fence_nop);
10313 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10316 for (; len > 0; len -= cpu_clflush_line_size,
10317 va += cpu_clflush_line_size)
10322 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10325 for (; len > 0; len -= cpu_clflush_line_size,
10326 va += cpu_clflush_line_size)
10331 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10334 for (; len > 0; len -= cpu_clflush_line_size,
10335 va += cpu_clflush_line_size)
10340 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10344 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10347 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10348 return (pmap_large_map_flush_range_clwb);
10349 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10350 return (pmap_large_map_flush_range_clflushopt);
10351 else if ((cpu_feature & CPUID_CLFSH) != 0)
10352 return (pmap_large_map_flush_range_clflush);
10354 return (pmap_large_map_flush_range_nop);
10358 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10360 volatile u_long *pe;
10366 for (va = sva; va < eva; va += inc) {
10368 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10369 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10371 if ((p & X86_PG_PS) != 0)
10375 pe = (volatile u_long *)pmap_large_map_pde(va);
10377 if ((p & X86_PG_PS) != 0)
10381 pe = (volatile u_long *)pmap_large_map_pte(va);
10385 seen_other = false;
10387 if ((p & X86_PG_AVAIL1) != 0) {
10389 * Spin-wait for the end of a parallel
10396 * If we saw other write-back
10397 * occuring, we cannot rely on PG_M to
10398 * indicate state of the cache. The
10399 * PG_M bit is cleared before the
10400 * flush to avoid ignoring new writes,
10401 * and writes which are relevant for
10402 * us might happen after.
10408 if ((p & X86_PG_M) != 0 || seen_other) {
10409 if (!atomic_fcmpset_long(pe, &p,
10410 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10412 * If we saw PG_M without
10413 * PG_AVAIL1, and then on the
10414 * next attempt we do not
10415 * observe either PG_M or
10416 * PG_AVAIL1, the other
10417 * write-back started after us
10418 * and finished before us. We
10419 * can rely on it doing our
10423 pmap_large_map_flush_range(va, inc);
10424 atomic_clear_long(pe, X86_PG_AVAIL1);
10433 * Write-back cache lines for the given address range.
10435 * Must be called only on the range or sub-range returned from
10436 * pmap_large_map(). Must not be called on the coalesced ranges.
10438 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10439 * instructions support.
10442 pmap_large_map_wb(void *svap, vm_size_t len)
10444 vm_offset_t eva, sva;
10446 sva = (vm_offset_t)svap;
10448 pmap_large_map_wb_fence();
10449 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10450 pmap_large_map_flush_range(sva, len);
10452 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10453 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10454 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10455 pmap_large_map_wb_large(sva, eva);
10457 pmap_large_map_wb_fence();
10461 pmap_pti_alloc_page(void)
10465 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10466 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10467 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10472 pmap_pti_free_page(vm_page_t m)
10475 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10476 if (!vm_page_unwire_noq(m))
10478 vm_page_free_zero(m);
10483 pmap_pti_init(void)
10492 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10493 VM_OBJECT_WLOCK(pti_obj);
10494 pml4_pg = pmap_pti_alloc_page();
10495 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10496 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10497 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10498 pdpe = pmap_pti_pdpe(va);
10499 pmap_pti_wire_pte(pdpe);
10501 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10502 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10503 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10504 sizeof(struct gate_descriptor) * NIDT, false);
10506 /* Doublefault stack IST 1 */
10507 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10508 pmap_pti_add_kva_locked(va - DBLFAULT_STACK_SIZE, va, false);
10509 /* NMI stack IST 2 */
10510 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10511 pmap_pti_add_kva_locked(va - NMI_STACK_SIZE, va, false);
10512 /* MC# stack IST 3 */
10513 va = __pcpu[i].pc_common_tss.tss_ist3 +
10514 sizeof(struct nmi_pcpu);
10515 pmap_pti_add_kva_locked(va - MCE_STACK_SIZE, va, false);
10516 /* DB# stack IST 4 */
10517 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10518 pmap_pti_add_kva_locked(va - DBG_STACK_SIZE, va, false);
10520 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10521 (vm_offset_t)etext, true);
10522 pti_finalized = true;
10523 VM_OBJECT_WUNLOCK(pti_obj);
10525 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10527 static pdp_entry_t *
10528 pmap_pti_pdpe(vm_offset_t va)
10530 pml4_entry_t *pml4e;
10533 vm_pindex_t pml4_idx;
10536 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10538 pml4_idx = pmap_pml4e_index(va);
10539 pml4e = &pti_pml4[pml4_idx];
10543 panic("pml4 alloc after finalization\n");
10544 m = pmap_pti_alloc_page();
10546 pmap_pti_free_page(m);
10547 mphys = *pml4e & ~PAGE_MASK;
10549 mphys = VM_PAGE_TO_PHYS(m);
10550 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10553 mphys = *pml4e & ~PAGE_MASK;
10555 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10560 pmap_pti_wire_pte(void *pte)
10564 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10565 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10570 pmap_pti_unwire_pde(void *pde, bool only_ref)
10574 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10575 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10576 MPASS(m->ref_count > 0);
10577 MPASS(only_ref || m->ref_count > 1);
10578 pmap_pti_free_page(m);
10582 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10587 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10588 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10589 MPASS(m->ref_count > 0);
10590 if (pmap_pti_free_page(m)) {
10591 pde = pmap_pti_pde(va);
10592 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10594 pmap_pti_unwire_pde(pde, false);
10598 static pd_entry_t *
10599 pmap_pti_pde(vm_offset_t va)
10604 vm_pindex_t pd_idx;
10607 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10609 pdpe = pmap_pti_pdpe(va);
10611 m = pmap_pti_alloc_page();
10613 pmap_pti_free_page(m);
10614 MPASS((*pdpe & X86_PG_PS) == 0);
10615 mphys = *pdpe & ~PAGE_MASK;
10617 mphys = VM_PAGE_TO_PHYS(m);
10618 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10621 MPASS((*pdpe & X86_PG_PS) == 0);
10622 mphys = *pdpe & ~PAGE_MASK;
10625 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10626 pd_idx = pmap_pde_index(va);
10631 static pt_entry_t *
10632 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10639 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10641 pde = pmap_pti_pde(va);
10642 if (unwire_pde != NULL) {
10643 *unwire_pde = true;
10644 pmap_pti_wire_pte(pde);
10647 m = pmap_pti_alloc_page();
10649 pmap_pti_free_page(m);
10650 MPASS((*pde & X86_PG_PS) == 0);
10651 mphys = *pde & ~(PAGE_MASK | pg_nx);
10653 mphys = VM_PAGE_TO_PHYS(m);
10654 *pde = mphys | X86_PG_RW | X86_PG_V;
10655 if (unwire_pde != NULL)
10656 *unwire_pde = false;
10659 MPASS((*pde & X86_PG_PS) == 0);
10660 mphys = *pde & ~(PAGE_MASK | pg_nx);
10663 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10664 pte += pmap_pte_index(va);
10670 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10674 pt_entry_t *pte, ptev;
10677 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10679 sva = trunc_page(sva);
10680 MPASS(sva > VM_MAXUSER_ADDRESS);
10681 eva = round_page(eva);
10683 for (; sva < eva; sva += PAGE_SIZE) {
10684 pte = pmap_pti_pte(sva, &unwire_pde);
10685 pa = pmap_kextract(sva);
10686 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10687 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10688 VM_MEMATTR_DEFAULT, FALSE);
10690 pte_store(pte, ptev);
10691 pmap_pti_wire_pte(pte);
10693 KASSERT(!pti_finalized,
10694 ("pti overlap after fin %#lx %#lx %#lx",
10696 KASSERT(*pte == ptev,
10697 ("pti non-identical pte after fin %#lx %#lx %#lx",
10701 pde = pmap_pti_pde(sva);
10702 pmap_pti_unwire_pde(pde, true);
10708 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10713 VM_OBJECT_WLOCK(pti_obj);
10714 pmap_pti_add_kva_locked(sva, eva, exec);
10715 VM_OBJECT_WUNLOCK(pti_obj);
10719 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10726 sva = rounddown2(sva, PAGE_SIZE);
10727 MPASS(sva > VM_MAXUSER_ADDRESS);
10728 eva = roundup2(eva, PAGE_SIZE);
10730 VM_OBJECT_WLOCK(pti_obj);
10731 for (va = sva; va < eva; va += PAGE_SIZE) {
10732 pte = pmap_pti_pte(va, NULL);
10733 KASSERT((*pte & X86_PG_V) != 0,
10734 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10735 (u_long)pte, *pte));
10737 pmap_pti_unwire_pte(pte, va);
10739 pmap_invalidate_range(kernel_pmap, sva, eva);
10740 VM_OBJECT_WUNLOCK(pti_obj);
10744 pkru_dup_range(void *ctx __unused, void *data)
10746 struct pmap_pkru_range *node, *new_node;
10748 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10749 if (new_node == NULL)
10752 memcpy(new_node, node, sizeof(*node));
10757 pkru_free_range(void *ctx __unused, void *node)
10760 uma_zfree(pmap_pkru_ranges_zone, node);
10764 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10767 struct pmap_pkru_range *ppr;
10770 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10771 MPASS(pmap->pm_type == PT_X86);
10772 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10773 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10774 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10776 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10779 ppr->pkru_keyidx = keyidx;
10780 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10781 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10783 uma_zfree(pmap_pkru_ranges_zone, ppr);
10788 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10791 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10792 MPASS(pmap->pm_type == PT_X86);
10793 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10794 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10798 pmap_pkru_deassign_all(pmap_t pmap)
10801 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10802 if (pmap->pm_type == PT_X86 &&
10803 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10804 rangeset_remove_all(&pmap->pm_pkru);
10808 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10810 struct pmap_pkru_range *ppr, *prev_ppr;
10813 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10814 if (pmap->pm_type != PT_X86 ||
10815 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10816 sva >= VM_MAXUSER_ADDRESS)
10818 MPASS(eva <= VM_MAXUSER_ADDRESS);
10819 for (va = sva; va < eva; prev_ppr = ppr) {
10820 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10823 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10829 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10831 va = ppr->pkru_rs_el.re_end;
10837 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10839 struct pmap_pkru_range *ppr;
10841 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10842 if (pmap->pm_type != PT_X86 ||
10843 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10844 va >= VM_MAXUSER_ADDRESS)
10846 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10848 return (X86_PG_PKU(ppr->pkru_keyidx));
10853 pred_pkru_on_remove(void *ctx __unused, void *r)
10855 struct pmap_pkru_range *ppr;
10858 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10862 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10865 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10866 if (pmap->pm_type == PT_X86 &&
10867 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10868 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10869 pred_pkru_on_remove);
10874 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10877 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10878 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10879 MPASS(dst_pmap->pm_type == PT_X86);
10880 MPASS(src_pmap->pm_type == PT_X86);
10881 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10882 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10884 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10888 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10891 pml4_entry_t *pml4e;
10893 pd_entry_t newpde, ptpaddr, *pde;
10894 pt_entry_t newpte, *ptep, pte;
10895 vm_offset_t va, va_next;
10898 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10899 MPASS(pmap->pm_type == PT_X86);
10900 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10902 for (changed = false, va = sva; va < eva; va = va_next) {
10903 pml4e = pmap_pml4e(pmap, va);
10904 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
10905 va_next = (va + NBPML4) & ~PML4MASK;
10911 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10912 if ((*pdpe & X86_PG_V) == 0) {
10913 va_next = (va + NBPDP) & ~PDPMASK;
10919 va_next = (va + NBPDR) & ~PDRMASK;
10923 pde = pmap_pdpe_to_pde(pdpe, va);
10928 MPASS((ptpaddr & X86_PG_V) != 0);
10929 if ((ptpaddr & PG_PS) != 0) {
10930 if (va + NBPDR == va_next && eva >= va_next) {
10931 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10932 X86_PG_PKU(keyidx);
10933 if (newpde != ptpaddr) {
10938 } else if (!pmap_demote_pde(pmap, pde, va)) {
10946 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10947 ptep++, va += PAGE_SIZE) {
10949 if ((pte & X86_PG_V) == 0)
10951 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10952 if (newpte != pte) {
10959 pmap_invalidate_range(pmap, sva, eva);
10963 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10964 u_int keyidx, int flags)
10967 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10968 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10970 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10972 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10978 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10983 sva = trunc_page(sva);
10984 eva = round_page(eva);
10985 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10990 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10992 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10994 if (error != ENOMEM)
11002 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
11006 sva = trunc_page(sva);
11007 eva = round_page(eva);
11008 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
11013 error = pmap_pkru_deassign(pmap, sva, eva);
11015 pmap_pkru_update_range(pmap, sva, eva, 0);
11017 if (error != ENOMEM)
11025 * Track a range of the kernel's virtual address space that is contiguous
11026 * in various mapping attributes.
11028 struct pmap_kernel_map_range {
11037 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11043 if (eva <= range->sva)
11046 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11047 for (i = 0; i < PAT_INDEX_SIZE; i++)
11048 if (pat_index[i] == pat_idx)
11052 case PAT_WRITE_BACK:
11055 case PAT_WRITE_THROUGH:
11058 case PAT_UNCACHEABLE:
11064 case PAT_WRITE_PROTECTED:
11067 case PAT_WRITE_COMBINING:
11071 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11072 __func__, pat_idx, range->sva, eva);
11077 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11079 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11080 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11081 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11082 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11083 mode, range->pdpes, range->pdes, range->ptes);
11085 /* Reset to sentinel value. */
11086 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11087 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11088 NPDEPG - 1, NPTEPG - 1);
11092 * Determine whether the attributes specified by a page table entry match those
11093 * being tracked by the current range. This is not quite as simple as a direct
11094 * flag comparison since some PAT modes have multiple representations.
11097 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11099 pt_entry_t diff, mask;
11101 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11102 diff = (range->attrs ^ attrs) & mask;
11105 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11106 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11107 pmap_pat_index(kernel_pmap, attrs, true))
11113 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11117 memset(range, 0, sizeof(*range));
11119 range->attrs = attrs;
11123 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11124 * those of the current run, dump the address range and its attributes, and
11128 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11129 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11134 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11136 attrs |= pdpe & pg_nx;
11137 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11138 if ((pdpe & PG_PS) != 0) {
11139 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11140 } else if (pde != 0) {
11141 attrs |= pde & pg_nx;
11142 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11144 if ((pde & PG_PS) != 0) {
11145 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11146 } else if (pte != 0) {
11147 attrs |= pte & pg_nx;
11148 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11149 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11151 /* Canonicalize by always using the PDE PAT bit. */
11152 if ((attrs & X86_PG_PTE_PAT) != 0)
11153 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11156 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11157 sysctl_kmaps_dump(sb, range, va);
11158 sysctl_kmaps_reinit(range, va, attrs);
11163 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11165 struct pmap_kernel_map_range range;
11166 struct sbuf sbuf, *sb;
11167 pml4_entry_t pml4e;
11168 pdp_entry_t *pdp, pdpe;
11169 pd_entry_t *pd, pde;
11170 pt_entry_t *pt, pte;
11173 int error, i, j, k, l;
11175 error = sysctl_wire_old_buffer(req, 0);
11179 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11181 /* Sentinel value. */
11182 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11183 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11184 NPDEPG - 1, NPTEPG - 1);
11187 * Iterate over the kernel page tables without holding the kernel pmap
11188 * lock. Outside of the large map, kernel page table pages are never
11189 * freed, so at worst we will observe inconsistencies in the output.
11190 * Within the large map, ensure that PDP and PD page addresses are
11191 * valid before descending.
11193 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11196 sbuf_printf(sb, "\nRecursive map:\n");
11199 sbuf_printf(sb, "\nDirect map:\n");
11202 sbuf_printf(sb, "\nKernel map:\n");
11205 sbuf_printf(sb, "\nLarge map:\n");
11209 /* Convert to canonical form. */
11210 if (sva == 1ul << 47)
11214 pml4e = kernel_pml4[i];
11215 if ((pml4e & X86_PG_V) == 0) {
11216 sva = rounddown2(sva, NBPML4);
11217 sysctl_kmaps_dump(sb, &range, sva);
11221 pa = pml4e & PG_FRAME;
11222 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11224 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11226 if ((pdpe & X86_PG_V) == 0) {
11227 sva = rounddown2(sva, NBPDP);
11228 sysctl_kmaps_dump(sb, &range, sva);
11232 pa = pdpe & PG_FRAME;
11233 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11234 vm_phys_paddr_to_vm_page(pa) == NULL)
11236 if ((pdpe & PG_PS) != 0) {
11237 sva = rounddown2(sva, NBPDP);
11238 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11244 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11246 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11248 if ((pde & X86_PG_V) == 0) {
11249 sva = rounddown2(sva, NBPDR);
11250 sysctl_kmaps_dump(sb, &range, sva);
11254 pa = pde & PG_FRAME;
11255 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11256 vm_phys_paddr_to_vm_page(pa) == NULL)
11258 if ((pde & PG_PS) != 0) {
11259 sva = rounddown2(sva, NBPDR);
11260 sysctl_kmaps_check(sb, &range, sva,
11261 pml4e, pdpe, pde, 0);
11266 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11268 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11269 sva += PAGE_SIZE) {
11271 if ((pte & X86_PG_V) == 0) {
11272 sysctl_kmaps_dump(sb, &range,
11276 sysctl_kmaps_check(sb, &range, sva,
11277 pml4e, pdpe, pde, pte);
11284 error = sbuf_finish(sb);
11288 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11289 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11290 NULL, 0, sysctl_kmaps, "A",
11291 "Dump kernel address layout");
11294 DB_SHOW_COMMAND(pte, pmap_print_pte)
11297 pml5_entry_t *pml5;
11298 pml4_entry_t *pml4;
11301 pt_entry_t *pte, PG_V;
11305 db_printf("show pte addr\n");
11308 va = (vm_offset_t)addr;
11310 if (kdb_thread != NULL)
11311 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11313 pmap = PCPU_GET(curpmap);
11315 PG_V = pmap_valid_bit(pmap);
11316 db_printf("VA 0x%016lx", va);
11318 if (pmap_is_la57(pmap)) {
11319 pml5 = pmap_pml5e(pmap, va);
11320 db_printf(" pml5e 0x%016lx", *pml5);
11321 if ((*pml5 & PG_V) == 0) {
11325 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11327 pml4 = pmap_pml4e(pmap, va);
11329 db_printf(" pml4e 0x%016lx", *pml4);
11330 if ((*pml4 & PG_V) == 0) {
11334 pdp = pmap_pml4e_to_pdpe(pml4, va);
11335 db_printf(" pdpe 0x%016lx", *pdp);
11336 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11340 pde = pmap_pdpe_to_pde(pdp, va);
11341 db_printf(" pde 0x%016lx", *pde);
11342 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11346 pte = pmap_pde_to_pte(pde, va);
11347 db_printf(" pte 0x%016lx\n", *pte);
11350 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11355 a = (vm_paddr_t)addr;
11356 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11358 db_printf("show phys2dmap addr\n");
11363 ptpages_show_page(int level, int idx, vm_page_t pg)
11365 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11366 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11370 ptpages_show_complain(int level, int idx, uint64_t pte)
11372 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11376 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11378 vm_page_t pg3, pg2, pg1;
11379 pml4_entry_t *pml4;
11384 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11385 for (i4 = 0; i4 < num_entries; i4++) {
11386 if ((pml4[i4] & PG_V) == 0)
11388 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11390 ptpages_show_complain(3, i4, pml4[i4]);
11393 ptpages_show_page(3, i4, pg3);
11394 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11395 for (i3 = 0; i3 < NPDPEPG; i3++) {
11396 if ((pdp[i3] & PG_V) == 0)
11398 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11400 ptpages_show_complain(2, i3, pdp[i3]);
11403 ptpages_show_page(2, i3, pg2);
11404 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11405 for (i2 = 0; i2 < NPDEPG; i2++) {
11406 if ((pd[i2] & PG_V) == 0)
11408 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11410 ptpages_show_complain(1, i2, pd[i2]);
11413 ptpages_show_page(1, i2, pg1);
11419 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11423 pml5_entry_t *pml5;
11428 pmap = (pmap_t)addr;
11430 pmap = PCPU_GET(curpmap);
11432 PG_V = pmap_valid_bit(pmap);
11434 if (pmap_is_la57(pmap)) {
11435 pml5 = pmap->pm_pmltop;
11436 for (i5 = 0; i5 < NUPML5E; i5++) {
11437 if ((pml5[i5] & PG_V) == 0)
11439 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11441 ptpages_show_complain(4, i5, pml5[i5]);
11444 ptpages_show_page(4, i5, pg);
11445 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11448 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11449 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);