2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
326 #define pa_index(pa) ({ \
327 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
328 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
345 #define NPV_LIST_LOCKS MAXCPU
347 #define PHYS_TO_PV_LIST_LOCK(pa) \
348 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
351 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
352 struct rwlock **_lockp = (lockp); \
353 struct rwlock *_new_lock; \
355 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
356 if (_new_lock != *_lockp) { \
357 if (*_lockp != NULL) \
358 rw_wunlock(*_lockp); \
359 *_lockp = _new_lock; \
364 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
365 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
367 #define RELEASE_PV_LIST_LOCK(lockp) do { \
368 struct rwlock **_lockp = (lockp); \
370 if (*_lockp != NULL) { \
371 rw_wunlock(*_lockp); \
376 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
377 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
379 struct pmap kernel_pmap_store;
381 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
382 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
385 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
386 "Number of kernel page table pages allocated on bootup");
389 vm_paddr_t dmaplimit;
390 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
393 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
395 static int pg_ps_enabled = 1;
396 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
397 &pg_ps_enabled, 0, "Are large page mappings enabled?");
399 #define PAT_INDEX_SIZE 8
400 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
402 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
403 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
404 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
405 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
407 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
408 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
409 static int ndmpdpphys; /* number of DMPDPphys pages */
411 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
414 * pmap_mapdev support pre initialization (i.e. console)
416 #define PMAP_PREINIT_MAPPING_COUNT 8
417 static struct pmap_preinit_mapping {
422 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
423 static int pmap_initialized;
426 * Data for the pv entry allocation mechanism.
427 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
431 pc_to_domain(struct pv_chunk *pc)
434 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
438 pc_to_domain(struct pv_chunk *pc __unused)
445 struct pv_chunks_list {
447 TAILQ_HEAD(pch, pv_chunk) pvc_list;
449 } __aligned(CACHE_LINE_SIZE);
451 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
454 struct pmap_large_md_page {
455 struct rwlock pv_lock;
456 struct md_page pv_page;
459 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
460 #define pv_dummy pv_dummy_large.pv_page
461 __read_mostly static struct pmap_large_md_page *pv_table;
462 __read_mostly vm_paddr_t pmap_last_pa;
464 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
465 static u_long pv_invl_gen[NPV_LIST_LOCKS];
466 static struct md_page *pv_table;
467 static struct md_page pv_dummy;
471 * All those kernel PT submaps that BSD is so fond of
473 pt_entry_t *CMAP1 = NULL;
475 static vm_offset_t qframe = 0;
476 static struct mtx qframe_mtx;
478 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
480 static vmem_t *large_vmem;
481 static u_int lm_ents;
482 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
483 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
485 int pmap_pcid_enabled = 1;
486 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
487 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
488 int invpcid_works = 0;
489 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
490 "Is the invpcid instruction available ?");
492 int __read_frequently pti = 0;
493 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
495 "Page Table Isolation enabled");
496 static vm_object_t pti_obj;
497 static pml4_entry_t *pti_pml4;
498 static vm_pindex_t pti_pg_idx;
499 static bool pti_finalized;
501 struct pmap_pkru_range {
502 struct rs_el pkru_rs_el;
507 static uma_zone_t pmap_pkru_ranges_zone;
508 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
509 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
510 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
511 static void *pkru_dup_range(void *ctx, void *data);
512 static void pkru_free_range(void *ctx, void *node);
513 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
514 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
515 static void pmap_pkru_deassign_all(pmap_t pmap);
518 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
525 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
527 return (sysctl_handle_64(oidp, &res, 0, req));
529 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
530 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
531 "Count of saved TLB context on switch");
533 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
534 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
535 static struct mtx invl_gen_mtx;
536 /* Fake lock object to satisfy turnstiles interface. */
537 static struct lock_object invl_gen_ts = {
540 static struct pmap_invl_gen pmap_invl_gen_head = {
544 static u_long pmap_invl_gen = 1;
545 static int pmap_invl_waiters;
546 static struct callout pmap_invl_callout;
547 static bool pmap_invl_callout_inited;
549 #define PMAP_ASSERT_NOT_IN_DI() \
550 KASSERT(pmap_not_in_di(), ("DI already started"))
557 if ((cpu_feature2 & CPUID2_CX16) == 0)
560 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
565 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
569 locked = pmap_di_locked();
570 return (sysctl_handle_int(oidp, &locked, 0, req));
572 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
573 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
574 "Locked delayed invalidation");
576 static bool pmap_not_in_di_l(void);
577 static bool pmap_not_in_di_u(void);
578 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
581 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
585 pmap_not_in_di_l(void)
587 struct pmap_invl_gen *invl_gen;
589 invl_gen = &curthread->td_md.md_invl_gen;
590 return (invl_gen->gen == 0);
594 pmap_thread_init_invl_gen_l(struct thread *td)
596 struct pmap_invl_gen *invl_gen;
598 invl_gen = &td->td_md.md_invl_gen;
603 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
605 struct turnstile *ts;
607 ts = turnstile_trywait(&invl_gen_ts);
608 if (*m_gen > atomic_load_long(invl_gen))
609 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
611 turnstile_cancel(ts);
615 pmap_delayed_invl_finish_unblock(u_long new_gen)
617 struct turnstile *ts;
619 turnstile_chain_lock(&invl_gen_ts);
620 ts = turnstile_lookup(&invl_gen_ts);
622 pmap_invl_gen = new_gen;
624 turnstile_broadcast(ts, TS_SHARED_QUEUE);
625 turnstile_unpend(ts);
627 turnstile_chain_unlock(&invl_gen_ts);
631 * Start a new Delayed Invalidation (DI) block of code, executed by
632 * the current thread. Within a DI block, the current thread may
633 * destroy both the page table and PV list entries for a mapping and
634 * then release the corresponding PV list lock before ensuring that
635 * the mapping is flushed from the TLBs of any processors with the
639 pmap_delayed_invl_start_l(void)
641 struct pmap_invl_gen *invl_gen;
644 invl_gen = &curthread->td_md.md_invl_gen;
645 PMAP_ASSERT_NOT_IN_DI();
646 mtx_lock(&invl_gen_mtx);
647 if (LIST_EMPTY(&pmap_invl_gen_tracker))
648 currgen = pmap_invl_gen;
650 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
651 invl_gen->gen = currgen + 1;
652 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
653 mtx_unlock(&invl_gen_mtx);
657 * Finish the DI block, previously started by the current thread. All
658 * required TLB flushes for the pages marked by
659 * pmap_delayed_invl_page() must be finished before this function is
662 * This function works by bumping the global DI generation number to
663 * the generation number of the current thread's DI, unless there is a
664 * pending DI that started earlier. In the latter case, bumping the
665 * global DI generation number would incorrectly signal that the
666 * earlier DI had finished. Instead, this function bumps the earlier
667 * DI's generation number to match the generation number of the
668 * current thread's DI.
671 pmap_delayed_invl_finish_l(void)
673 struct pmap_invl_gen *invl_gen, *next;
675 invl_gen = &curthread->td_md.md_invl_gen;
676 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
677 mtx_lock(&invl_gen_mtx);
678 next = LIST_NEXT(invl_gen, link);
680 pmap_delayed_invl_finish_unblock(invl_gen->gen);
682 next->gen = invl_gen->gen;
683 LIST_REMOVE(invl_gen, link);
684 mtx_unlock(&invl_gen_mtx);
689 pmap_not_in_di_u(void)
691 struct pmap_invl_gen *invl_gen;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
698 pmap_thread_init_invl_gen_u(struct thread *td)
700 struct pmap_invl_gen *invl_gen;
702 invl_gen = &td->td_md.md_invl_gen;
704 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
708 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
710 uint64_t new_high, new_low, old_high, old_low;
713 old_low = new_low = 0;
714 old_high = new_high = (uintptr_t)0;
716 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
717 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
718 : "b"(new_low), "c" (new_high)
721 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
724 out->next = (void *)old_high;
727 out->next = (void *)new_high;
733 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
734 struct pmap_invl_gen *new_val)
736 uint64_t new_high, new_low, old_high, old_low;
739 new_low = new_val->gen;
740 new_high = (uintptr_t)new_val->next;
741 old_low = old_val->gen;
742 old_high = (uintptr_t)old_val->next;
744 __asm volatile("lock;cmpxchg16b\t%1;sete\t%0"
745 : "=r" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
746 : "b"(new_low), "c" (new_high)
752 static long invl_start_restart;
753 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
754 &invl_start_restart, 0,
756 static long invl_finish_restart;
757 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
758 &invl_finish_restart, 0,
760 static int invl_max_qlen;
761 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
766 #define di_delay locks_delay
769 pmap_delayed_invl_start_u(void)
771 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
773 struct lock_delay_arg lda;
781 invl_gen = &td->td_md.md_invl_gen;
782 PMAP_ASSERT_NOT_IN_DI();
783 lock_delay_arg_init(&lda, &di_delay);
784 invl_gen->saved_pri = 0;
785 pri = td->td_base_pri;
788 pri = td->td_base_pri;
790 invl_gen->saved_pri = pri;
797 for (p = &pmap_invl_gen_head;; p = prev.next) {
799 prevl = (uintptr_t)atomic_load_ptr(&p->next);
800 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
801 PV_STAT(atomic_add_long(&invl_start_restart, 1));
807 prev.next = (void *)prevl;
810 if ((ii = invl_max_qlen) < i)
811 atomic_cmpset_int(&invl_max_qlen, ii, i);
814 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
815 PV_STAT(atomic_add_long(&invl_start_restart, 1));
820 new_prev.gen = prev.gen;
821 new_prev.next = invl_gen;
822 invl_gen->gen = prev.gen + 1;
824 /* Formal fence between store to invl->gen and updating *p. */
825 atomic_thread_fence_rel();
828 * After inserting an invl_gen element with invalid bit set,
829 * this thread blocks any other thread trying to enter the
830 * delayed invalidation block. Do not allow to remove us from
831 * the CPU, because it causes starvation for other threads.
836 * ABA for *p is not possible there, since p->gen can only
837 * increase. So if the *p thread finished its di, then
838 * started a new one and got inserted into the list at the
839 * same place, its gen will appear greater than the previously
842 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
844 PV_STAT(atomic_add_long(&invl_start_restart, 1));
850 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
851 * invl_gen->next, allowing other threads to iterate past us.
852 * pmap_di_store_invl() provides fence between the generation
853 * write and the update of next.
855 invl_gen->next = NULL;
860 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
861 struct pmap_invl_gen *p)
863 struct pmap_invl_gen prev, new_prev;
867 * Load invl_gen->gen after setting invl_gen->next
868 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
869 * generations to propagate to our invl_gen->gen. Lock prefix
870 * in atomic_set_ptr() worked as seq_cst fence.
872 mygen = atomic_load_long(&invl_gen->gen);
874 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
877 KASSERT(prev.gen < mygen,
878 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
879 new_prev.gen = mygen;
880 new_prev.next = (void *)((uintptr_t)invl_gen->next &
881 ~PMAP_INVL_GEN_NEXT_INVALID);
883 /* Formal fence between load of prev and storing update to it. */
884 atomic_thread_fence_rel();
886 return (pmap_di_store_invl(p, &prev, &new_prev));
890 pmap_delayed_invl_finish_u(void)
892 struct pmap_invl_gen *invl_gen, *p;
894 struct lock_delay_arg lda;
898 invl_gen = &td->td_md.md_invl_gen;
899 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
900 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
901 ("missed invl_start: INVALID"));
902 lock_delay_arg_init(&lda, &di_delay);
905 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
906 prevl = (uintptr_t)atomic_load_ptr(&p->next);
907 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
908 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
912 if ((void *)prevl == invl_gen)
917 * It is legitimate to not find ourself on the list if a
918 * thread before us finished its DI and started it again.
920 if (__predict_false(p == NULL)) {
921 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
927 atomic_set_ptr((uintptr_t *)&invl_gen->next,
928 PMAP_INVL_GEN_NEXT_INVALID);
929 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
930 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
931 PMAP_INVL_GEN_NEXT_INVALID);
933 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
938 if (atomic_load_int(&pmap_invl_waiters) > 0)
939 pmap_delayed_invl_finish_unblock(0);
940 if (invl_gen->saved_pri != 0) {
942 sched_prio(td, invl_gen->saved_pri);
948 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
950 struct pmap_invl_gen *p, *pn;
955 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
957 nextl = (uintptr_t)atomic_load_ptr(&p->next);
958 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
959 td = first ? NULL : __containerof(p, struct thread,
961 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
962 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
963 td != NULL ? td->td_tid : -1);
969 static long invl_wait;
970 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
971 "Number of times DI invalidation blocked pmap_remove_all/write");
972 static long invl_wait_slow;
973 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
974 "Number of slow invalidation waits for lockless DI");
979 pmap_delayed_invl_genp(vm_page_t m)
984 pa = VM_PAGE_TO_PHYS(m);
985 if (__predict_false((pa) > pmap_last_pa))
986 gen = &pv_dummy_large.pv_invl_gen;
988 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
994 pmap_delayed_invl_genp(vm_page_t m)
997 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1002 pmap_delayed_invl_callout_func(void *arg __unused)
1005 if (atomic_load_int(&pmap_invl_waiters) == 0)
1007 pmap_delayed_invl_finish_unblock(0);
1011 pmap_delayed_invl_callout_init(void *arg __unused)
1014 if (pmap_di_locked())
1016 callout_init(&pmap_invl_callout, 1);
1017 pmap_invl_callout_inited = true;
1019 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1020 pmap_delayed_invl_callout_init, NULL);
1023 * Ensure that all currently executing DI blocks, that need to flush
1024 * TLB for the given page m, actually flushed the TLB at the time the
1025 * function returned. If the page m has an empty PV list and we call
1026 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1027 * valid mapping for the page m in either its page table or TLB.
1029 * This function works by blocking until the global DI generation
1030 * number catches up with the generation number associated with the
1031 * given page m and its PV list. Since this function's callers
1032 * typically own an object lock and sometimes own a page lock, it
1033 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1037 pmap_delayed_invl_wait_l(vm_page_t m)
1041 bool accounted = false;
1044 m_gen = pmap_delayed_invl_genp(m);
1045 while (*m_gen > pmap_invl_gen) {
1048 atomic_add_long(&invl_wait, 1);
1052 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1057 pmap_delayed_invl_wait_u(vm_page_t m)
1060 struct lock_delay_arg lda;
1064 m_gen = pmap_delayed_invl_genp(m);
1065 lock_delay_arg_init(&lda, &di_delay);
1066 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1067 if (fast || !pmap_invl_callout_inited) {
1068 PV_STAT(atomic_add_long(&invl_wait, 1));
1073 * The page's invalidation generation number
1074 * is still below the current thread's number.
1075 * Prepare to block so that we do not waste
1076 * CPU cycles or worse, suffer livelock.
1078 * Since it is impossible to block without
1079 * racing with pmap_delayed_invl_finish_u(),
1080 * prepare for the race by incrementing
1081 * pmap_invl_waiters and arming a 1-tick
1082 * callout which will unblock us if we lose
1085 atomic_add_int(&pmap_invl_waiters, 1);
1088 * Re-check the current thread's invalidation
1089 * generation after incrementing
1090 * pmap_invl_waiters, so that there is no race
1091 * with pmap_delayed_invl_finish_u() setting
1092 * the page generation and checking
1093 * pmap_invl_waiters. The only race allowed
1094 * is for a missed unblock, which is handled
1098 atomic_load_long(&pmap_invl_gen_head.gen)) {
1099 callout_reset(&pmap_invl_callout, 1,
1100 pmap_delayed_invl_callout_func, NULL);
1101 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1102 pmap_delayed_invl_wait_block(m_gen,
1103 &pmap_invl_gen_head.gen);
1105 atomic_add_int(&pmap_invl_waiters, -1);
1110 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1113 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1114 pmap_thread_init_invl_gen_u);
1117 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1120 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1121 pmap_delayed_invl_start_u);
1124 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1127 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1128 pmap_delayed_invl_finish_u);
1131 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1134 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1135 pmap_delayed_invl_wait_u);
1139 * Mark the page m's PV list as participating in the current thread's
1140 * DI block. Any threads concurrently using m's PV list to remove or
1141 * restrict all mappings to m will wait for the current thread's DI
1142 * block to complete before proceeding.
1144 * The function works by setting the DI generation number for m's PV
1145 * list to at least the DI generation number of the current thread.
1146 * This forces a caller of pmap_delayed_invl_wait() to block until
1147 * current thread calls pmap_delayed_invl_finish().
1150 pmap_delayed_invl_page(vm_page_t m)
1154 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1155 gen = curthread->td_md.md_invl_gen.gen;
1158 m_gen = pmap_delayed_invl_genp(m);
1166 static caddr_t crashdumpmap;
1169 * Internal flags for pmap_enter()'s helper functions.
1171 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1172 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1175 * Internal flags for pmap_mapdev_internal() and
1176 * pmap_change_props_locked().
1178 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1179 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1180 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1182 TAILQ_HEAD(pv_chunklist, pv_chunk);
1184 static void free_pv_chunk(struct pv_chunk *pc);
1185 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1186 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1187 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1188 static int popcnt_pc_map_pq(uint64_t *map);
1189 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1190 static void reserve_pv_entries(pmap_t pmap, int needed,
1191 struct rwlock **lockp);
1192 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1193 struct rwlock **lockp);
1194 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1195 u_int flags, struct rwlock **lockp);
1196 #if VM_NRESERVLEVEL > 0
1197 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1198 struct rwlock **lockp);
1200 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1201 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1204 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1205 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1206 vm_prot_t prot, int mode, int flags);
1207 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1208 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1209 vm_offset_t va, struct rwlock **lockp);
1210 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1212 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1213 vm_prot_t prot, struct rwlock **lockp);
1214 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1215 u_int flags, vm_page_t m, struct rwlock **lockp);
1216 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1217 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1218 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1219 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1220 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1222 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1224 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1226 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1227 static vm_page_t pmap_large_map_getptp_unlocked(void);
1228 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1229 #if VM_NRESERVLEVEL > 0
1230 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1231 struct rwlock **lockp);
1233 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1235 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1236 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1238 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1239 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1240 static void pmap_pti_wire_pte(void *pte);
1241 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1242 struct spglist *free, struct rwlock **lockp);
1243 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1244 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1245 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1246 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1247 struct spglist *free);
1248 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1249 pd_entry_t *pde, struct spglist *free,
1250 struct rwlock **lockp);
1251 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1252 vm_page_t m, struct rwlock **lockp);
1253 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1255 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1257 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1258 struct rwlock **lockp);
1259 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1260 struct rwlock **lockp);
1261 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1262 struct rwlock **lockp);
1264 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1265 struct spglist *free);
1266 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1268 /********************/
1269 /* Inline functions */
1270 /********************/
1272 /* Return a non-clipped PD index for a given VA */
1273 static __inline vm_pindex_t
1274 pmap_pde_pindex(vm_offset_t va)
1276 return (va >> PDRSHIFT);
1280 /* Return a pointer to the PML4 slot that corresponds to a VA */
1281 static __inline pml4_entry_t *
1282 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1285 return (&pmap->pm_pml4[pmap_pml4e_index(va)]);
1288 /* Return a pointer to the PDP slot that corresponds to a VA */
1289 static __inline pdp_entry_t *
1290 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1294 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1295 return (&pdpe[pmap_pdpe_index(va)]);
1298 /* Return a pointer to the PDP slot that corresponds to a VA */
1299 static __inline pdp_entry_t *
1300 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1302 pml4_entry_t *pml4e;
1305 PG_V = pmap_valid_bit(pmap);
1306 pml4e = pmap_pml4e(pmap, va);
1307 if ((*pml4e & PG_V) == 0)
1309 return (pmap_pml4e_to_pdpe(pml4e, va));
1312 /* Return a pointer to the PD slot that corresponds to a VA */
1313 static __inline pd_entry_t *
1314 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1318 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1319 return (&pde[pmap_pde_index(va)]);
1322 /* Return a pointer to the PD slot that corresponds to a VA */
1323 static __inline pd_entry_t *
1324 pmap_pde(pmap_t pmap, vm_offset_t va)
1329 PG_V = pmap_valid_bit(pmap);
1330 pdpe = pmap_pdpe(pmap, va);
1331 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1333 return (pmap_pdpe_to_pde(pdpe, va));
1336 /* Return a pointer to the PT slot that corresponds to a VA */
1337 static __inline pt_entry_t *
1338 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1342 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1343 return (&pte[pmap_pte_index(va)]);
1346 /* Return a pointer to the PT slot that corresponds to a VA */
1347 static __inline pt_entry_t *
1348 pmap_pte(pmap_t pmap, vm_offset_t va)
1353 PG_V = pmap_valid_bit(pmap);
1354 pde = pmap_pde(pmap, va);
1355 if (pde == NULL || (*pde & PG_V) == 0)
1357 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1358 return ((pt_entry_t *)pde);
1359 return (pmap_pde_to_pte(pde, va));
1362 static __inline void
1363 pmap_resident_count_inc(pmap_t pmap, int count)
1366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1367 pmap->pm_stats.resident_count += count;
1370 static __inline void
1371 pmap_resident_count_dec(pmap_t pmap, int count)
1374 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1375 KASSERT(pmap->pm_stats.resident_count >= count,
1376 ("pmap %p resident count underflow %ld %d", pmap,
1377 pmap->pm_stats.resident_count, count));
1378 pmap->pm_stats.resident_count -= count;
1381 PMAP_INLINE pt_entry_t *
1382 vtopte(vm_offset_t va)
1384 u_int64_t mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1386 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1388 return (PTmap + ((va >> PAGE_SHIFT) & mask));
1391 static __inline pd_entry_t *
1392 vtopde(vm_offset_t va)
1394 u_int64_t mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT + NPML4EPGSHIFT)) - 1);
1396 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1398 return (PDmap + ((va >> PDRSHIFT) & mask));
1402 allocpages(vm_paddr_t *firstaddr, int n)
1407 bzero((void *)ret, n * PAGE_SIZE);
1408 *firstaddr += n * PAGE_SIZE;
1412 CTASSERT(powerof2(NDMPML4E));
1414 /* number of kernel PDP slots */
1415 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1418 nkpt_init(vm_paddr_t addr)
1425 pt_pages = howmany(addr, 1 << PDRSHIFT);
1426 pt_pages += NKPDPE(pt_pages);
1429 * Add some slop beyond the bare minimum required for bootstrapping
1432 * This is quite important when allocating KVA for kernel modules.
1433 * The modules are required to be linked in the negative 2GB of
1434 * the address space. If we run out of KVA in this region then
1435 * pmap_growkernel() will need to allocate page table pages to map
1436 * the entire 512GB of KVA space which is an unnecessary tax on
1439 * Secondly, device memory mapped as part of setting up the low-
1440 * level console(s) is taken from KVA, starting at virtual_avail.
1441 * This is because cninit() is called after pmap_bootstrap() but
1442 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1445 pt_pages += 32; /* 64MB additional slop. */
1451 * Returns the proper write/execute permission for a physical page that is
1452 * part of the initial boot allocations.
1454 * If the page has kernel text, it is marked as read-only. If the page has
1455 * kernel read-only data, it is marked as read-only/not-executable. If the
1456 * page has only read-write data, it is marked as read-write/not-executable.
1457 * If the page is below/above the kernel range, it is marked as read-write.
1459 * This function operates on 2M pages, since we map the kernel space that
1462 static inline pt_entry_t
1463 bootaddr_rwx(vm_paddr_t pa)
1467 * The kernel is loaded at a 2MB-aligned address, and memory below that
1468 * need not be executable. The .bss section is padded to a 2MB
1469 * boundary, so memory following the kernel need not be executable
1470 * either. Preloaded kernel modules have their mapping permissions
1471 * fixed up by the linker.
1473 if (pa < trunc_2mpage(btext - KERNBASE) ||
1474 pa >= trunc_2mpage(_end - KERNBASE))
1475 return (X86_PG_RW | pg_nx);
1478 * The linker should ensure that the read-only and read-write
1479 * portions don't share the same 2M page, so this shouldn't
1480 * impact read-only data. However, in any case, any page with
1481 * read-write data needs to be read-write.
1483 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1484 return (X86_PG_RW | pg_nx);
1487 * Mark any 2M page containing kernel text as read-only. Mark
1488 * other pages with read-only data as read-only and not executable.
1489 * (It is likely a small portion of the read-only data section will
1490 * be marked as read-only, but executable. This should be acceptable
1491 * since the read-only protection will keep the data from changing.)
1492 * Note that fixups to the .text section will still work until we
1495 if (pa < round_2mpage(etext - KERNBASE))
1501 create_pagetables(vm_paddr_t *firstaddr)
1503 int i, j, ndm1g, nkpdpe, nkdmpde;
1507 uint64_t DMPDkernphys;
1509 /* Allocate page table pages for the direct map */
1510 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1511 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1513 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1514 if (ndmpdpphys > NDMPML4E) {
1516 * Each NDMPML4E allows 512 GB, so limit to that,
1517 * and then readjust ndmpdp and ndmpdpphys.
1519 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1520 Maxmem = atop(NDMPML4E * NBPML4);
1521 ndmpdpphys = NDMPML4E;
1522 ndmpdp = NDMPML4E * NPDEPG;
1524 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1526 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1528 * Calculate the number of 1G pages that will fully fit in
1531 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1534 * Allocate 2M pages for the kernel. These will be used in
1535 * place of the first one or more 1G pages from ndm1g.
1537 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1538 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1541 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1542 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1544 /* Allocate pages */
1545 KPML4phys = allocpages(firstaddr, 1);
1546 KPDPphys = allocpages(firstaddr, NKPML4E);
1549 * Allocate the initial number of kernel page table pages required to
1550 * bootstrap. We defer this until after all memory-size dependent
1551 * allocations are done (e.g. direct map), so that we don't have to
1552 * build in too much slop in our estimate.
1554 * Note that when NKPML4E > 1, we have an empty page underneath
1555 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1556 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1558 nkpt_init(*firstaddr);
1559 nkpdpe = NKPDPE(nkpt);
1561 KPTphys = allocpages(firstaddr, nkpt);
1562 KPDphys = allocpages(firstaddr, nkpdpe);
1565 * Connect the zero-filled PT pages to their PD entries. This
1566 * implicitly maps the PT pages at their correct locations within
1569 pd_p = (pd_entry_t *)KPDphys;
1570 for (i = 0; i < nkpt; i++)
1571 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1574 * Map from physical address zero to the end of loader preallocated
1575 * memory using 2MB pages. This replaces some of the PD entries
1578 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1579 /* Preset PG_M and PG_A because demotion expects it. */
1580 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1581 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1584 * Because we map the physical blocks in 2M pages, adjust firstaddr
1585 * to record the physical blocks we've actually mapped into kernel
1586 * virtual address space.
1588 if (*firstaddr < round_2mpage(KERNend))
1589 *firstaddr = round_2mpage(KERNend);
1591 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1592 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1593 for (i = 0; i < nkpdpe; i++)
1594 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1597 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1598 * the end of physical memory is not aligned to a 1GB page boundary,
1599 * then the residual physical memory is mapped with 2MB pages. Later,
1600 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1601 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1602 * that are partially used.
1604 pd_p = (pd_entry_t *)DMPDphys;
1605 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1606 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1607 /* Preset PG_M and PG_A because demotion expects it. */
1608 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1609 X86_PG_M | X86_PG_A | pg_nx;
1611 pdp_p = (pdp_entry_t *)DMPDPphys;
1612 for (i = 0; i < ndm1g; i++) {
1613 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1614 /* Preset PG_M and PG_A because demotion expects it. */
1615 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1616 X86_PG_M | X86_PG_A | pg_nx;
1618 for (j = 0; i < ndmpdp; i++, j++) {
1619 pdp_p[i] = DMPDphys + ptoa(j);
1620 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1624 * Instead of using a 1G page for the memory containing the kernel,
1625 * use 2M pages with read-only and no-execute permissions. (If using 1G
1626 * pages, this will partially overwrite the PDPEs above.)
1629 pd_p = (pd_entry_t *)DMPDkernphys;
1630 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1631 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1632 X86_PG_M | X86_PG_A | pg_nx |
1633 bootaddr_rwx(i << PDRSHIFT);
1634 for (i = 0; i < nkdmpde; i++)
1635 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1639 /* And recursively map PML4 to itself in order to get PTmap */
1640 p4_p = (pml4_entry_t *)KPML4phys;
1641 p4_p[PML4PML4I] = KPML4phys;
1642 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1644 /* Connect the Direct Map slot(s) up to the PML4. */
1645 for (i = 0; i < ndmpdpphys; i++) {
1646 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1647 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1650 /* Connect the KVA slots up to the PML4 */
1651 for (i = 0; i < NKPML4E; i++) {
1652 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1653 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1658 * Bootstrap the system enough to run with virtual memory.
1660 * On amd64 this is called after mapping has already been enabled
1661 * and just syncs the pmap module with what has already been done.
1662 * [We can't call it easily with mapping off since the kernel is not
1663 * mapped with PA == VA, hence we would have to relocate every address
1664 * from the linked base (virtual) address "KERNBASE" to the actual
1665 * (physical) address starting relative to 0]
1668 pmap_bootstrap(vm_paddr_t *firstaddr)
1671 pt_entry_t *pte, *pcpu_pte;
1672 struct region_descriptor r_gdt;
1673 uint64_t cr4, pcpu_phys;
1677 KERNend = *firstaddr;
1678 res = atop(KERNend - (vm_paddr_t)kernphys);
1684 * Create an initial set of page tables to run the kernel in.
1686 create_pagetables(firstaddr);
1688 pcpu_phys = allocpages(firstaddr, MAXCPU);
1691 * Add a physical memory segment (vm_phys_seg) corresponding to the
1692 * preallocated kernel page table pages so that vm_page structures
1693 * representing these pages will be created. The vm_page structures
1694 * are required for promotion of the corresponding kernel virtual
1695 * addresses to superpage mappings.
1697 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1700 * Account for the virtual addresses mapped by create_pagetables().
1702 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1703 virtual_end = VM_MAX_KERNEL_ADDRESS;
1706 * Enable PG_G global pages, then switch to the kernel page
1707 * table from the bootstrap page table. After the switch, it
1708 * is possible to enable SMEP and SMAP since PG_U bits are
1714 load_cr3(KPML4phys);
1715 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1717 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1722 * Initialize the kernel pmap (which is statically allocated).
1723 * Count bootstrap data as being resident in case any of this data is
1724 * later unmapped (using pmap_remove()) and freed.
1726 PMAP_LOCK_INIT(kernel_pmap);
1727 kernel_pmap->pm_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(KPML4phys);
1728 kernel_pmap->pm_cr3 = KPML4phys;
1729 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1730 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1731 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1732 kernel_pmap->pm_stats.resident_count = res;
1733 kernel_pmap->pm_flags = pmap_flags;
1736 * Initialize the TLB invalidations generation number lock.
1738 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1741 * Reserve some special page table entries/VA space for temporary
1744 #define SYSMAP(c, p, v, n) \
1745 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1751 * Crashdump maps. The first page is reused as CMAP1 for the
1754 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1755 CADDR1 = crashdumpmap;
1757 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1760 for (i = 0; i < MAXCPU; i++) {
1761 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1762 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1766 * Re-initialize PCPU area for BSP after switching.
1767 * Make hardware use gdt and common_tss from the new PCPU.
1769 STAILQ_INIT(&cpuhead);
1770 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1771 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1772 amd64_bsp_pcpu_init1(&__pcpu[0]);
1773 amd64_bsp_ist_init(&__pcpu[0]);
1774 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1776 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1777 sizeof(struct user_segment_descriptor));
1778 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1779 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1780 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1781 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1782 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1784 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1785 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1786 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1787 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1790 * Initialize the PAT MSR.
1791 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1792 * side-effect, invalidates stale PG_G TLB entries that might
1793 * have been created in our pre-boot environment.
1797 /* Initialize TLB Context Id. */
1798 if (pmap_pcid_enabled) {
1799 for (i = 0; i < MAXCPU; i++) {
1800 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1801 kernel_pmap->pm_pcids[i].pm_gen = 1;
1805 * PMAP_PCID_KERN + 1 is used for initialization of
1806 * proc0 pmap. The pmap' pcid state might be used by
1807 * EFIRT entry before first context switch, so it
1808 * needs to be valid.
1810 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1811 PCPU_SET(pcid_gen, 1);
1814 * pcpu area for APs is zeroed during AP startup.
1815 * pc_pcid_next and pc_pcid_gen are initialized by AP
1816 * during pcpu setup.
1818 load_cr4(rcr4() | CR4_PCIDE);
1823 * Setup the PAT MSR.
1832 /* Bail if this CPU doesn't implement PAT. */
1833 if ((cpu_feature & CPUID_PAT) == 0)
1836 /* Set default PAT index table. */
1837 for (i = 0; i < PAT_INDEX_SIZE; i++)
1839 pat_index[PAT_WRITE_BACK] = 0;
1840 pat_index[PAT_WRITE_THROUGH] = 1;
1841 pat_index[PAT_UNCACHEABLE] = 3;
1842 pat_index[PAT_WRITE_COMBINING] = 6;
1843 pat_index[PAT_WRITE_PROTECTED] = 5;
1844 pat_index[PAT_UNCACHED] = 2;
1847 * Initialize default PAT entries.
1848 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1849 * Program 5 and 6 as WP and WC.
1851 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1852 * mapping for a 2M page uses a PAT value with the bit 3 set due
1853 * to its overload with PG_PS.
1855 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1856 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1857 PAT_VALUE(2, PAT_UNCACHED) |
1858 PAT_VALUE(3, PAT_UNCACHEABLE) |
1859 PAT_VALUE(4, PAT_WRITE_BACK) |
1860 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1861 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1862 PAT_VALUE(7, PAT_UNCACHEABLE);
1866 load_cr4(cr4 & ~CR4_PGE);
1868 /* Disable caches (CD = 1, NW = 0). */
1870 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1872 /* Flushes caches and TLBs. */
1876 /* Update PAT and index table. */
1877 wrmsr(MSR_PAT, pat_msr);
1879 /* Flush caches and TLBs again. */
1883 /* Restore caches and PGE. */
1889 * Initialize a vm_page's machine-dependent fields.
1892 pmap_page_init(vm_page_t m)
1895 TAILQ_INIT(&m->md.pv_list);
1896 m->md.pat_mode = PAT_WRITE_BACK;
1899 static int pmap_allow_2m_x_ept;
1900 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
1901 &pmap_allow_2m_x_ept, 0,
1902 "Allow executable superpage mappings in EPT");
1905 pmap_allow_2m_x_ept_recalculate(void)
1908 * SKL002, SKL012S. Since the EPT format is only used by
1909 * Intel CPUs, the vendor check is merely a formality.
1911 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
1912 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
1913 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
1914 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
1915 CPUID_TO_MODEL(cpu_id) == 0x27 ||
1916 CPUID_TO_MODEL(cpu_id) == 0x35 ||
1917 CPUID_TO_MODEL(cpu_id) == 0x36 ||
1918 CPUID_TO_MODEL(cpu_id) == 0x37 ||
1919 CPUID_TO_MODEL(cpu_id) == 0x86 ||
1920 CPUID_TO_MODEL(cpu_id) == 0x1c ||
1921 CPUID_TO_MODEL(cpu_id) == 0x4a ||
1922 CPUID_TO_MODEL(cpu_id) == 0x4c ||
1923 CPUID_TO_MODEL(cpu_id) == 0x4d ||
1924 CPUID_TO_MODEL(cpu_id) == 0x5a ||
1925 CPUID_TO_MODEL(cpu_id) == 0x5c ||
1926 CPUID_TO_MODEL(cpu_id) == 0x5d ||
1927 CPUID_TO_MODEL(cpu_id) == 0x5f ||
1928 CPUID_TO_MODEL(cpu_id) == 0x6e ||
1929 CPUID_TO_MODEL(cpu_id) == 0x7a ||
1930 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
1931 CPUID_TO_MODEL(cpu_id) == 0x85))))
1932 pmap_allow_2m_x_ept = 1;
1933 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
1937 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
1940 return (pmap->pm_type != PT_EPT || !executable ||
1941 !pmap_allow_2m_x_ept);
1946 pmap_init_pv_table(void)
1948 struct pmap_large_md_page *pvd;
1950 long start, end, highest, pv_npg;
1951 int domain, i, j, pages;
1954 * We strongly depend on the size being a power of two, so the assert
1955 * is overzealous. However, should the struct be resized to a
1956 * different power of two, the code below needs to be revisited.
1958 CTASSERT((sizeof(*pvd) == 64));
1961 * Calculate the size of the array.
1963 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
1964 pv_npg = howmany(pmap_last_pa, NBPDR);
1965 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
1967 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
1968 if (pv_table == NULL)
1969 panic("%s: kva_alloc failed\n", __func__);
1972 * Iterate physical segments to allocate space for respective pages.
1976 for (i = 0; i < vm_phys_nsegs; i++) {
1977 end = vm_phys_segs[i].end / NBPDR;
1978 domain = vm_phys_segs[i].domain;
1983 start = highest + 1;
1984 pvd = &pv_table[start];
1986 pages = end - start + 1;
1987 s = round_page(pages * sizeof(*pvd));
1988 highest = start + (s / sizeof(*pvd)) - 1;
1990 for (j = 0; j < s; j += PAGE_SIZE) {
1991 vm_page_t m = vm_page_alloc_domain(NULL, 0,
1992 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
1994 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
1995 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
1998 for (j = 0; j < s / sizeof(*pvd); j++) {
1999 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2000 TAILQ_INIT(&pvd->pv_page.pv_list);
2001 pvd->pv_page.pv_gen = 0;
2002 pvd->pv_page.pat_mode = 0;
2003 pvd->pv_invl_gen = 0;
2007 pvd = &pv_dummy_large;
2008 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2009 TAILQ_INIT(&pvd->pv_page.pv_list);
2010 pvd->pv_page.pv_gen = 0;
2011 pvd->pv_page.pat_mode = 0;
2012 pvd->pv_invl_gen = 0;
2016 pmap_init_pv_table(void)
2022 * Initialize the pool of pv list locks.
2024 for (i = 0; i < NPV_LIST_LOCKS; i++)
2025 rw_init(&pv_list_locks[i], "pmap pv list");
2028 * Calculate the size of the pv head table for superpages.
2030 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2033 * Allocate memory for the pv head table for superpages.
2035 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2037 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2038 for (i = 0; i < pv_npg; i++)
2039 TAILQ_INIT(&pv_table[i].pv_list);
2040 TAILQ_INIT(&pv_dummy.pv_list);
2045 * Initialize the pmap module.
2046 * Called by vm_init, to initialize any structures that the pmap
2047 * system needs to map virtual memory.
2052 struct pmap_preinit_mapping *ppim;
2054 int error, i, ret, skz63;
2056 /* L1TF, reserve page @0 unconditionally */
2057 vm_page_blacklist_add(0, bootverbose);
2059 /* Detect bare-metal Skylake Server and Skylake-X. */
2060 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2061 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2063 * Skylake-X errata SKZ63. Processor May Hang When
2064 * Executing Code In an HLE Transaction Region between
2065 * 40000000H and 403FFFFFH.
2067 * Mark the pages in the range as preallocated. It
2068 * seems to be impossible to distinguish between
2069 * Skylake Server and Skylake X.
2072 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2075 printf("SKZ63: skipping 4M RAM starting "
2076 "at physical 1G\n");
2077 for (i = 0; i < atop(0x400000); i++) {
2078 ret = vm_page_blacklist_add(0x40000000 +
2080 if (!ret && bootverbose)
2081 printf("page at %#lx already used\n",
2082 0x40000000 + ptoa(i));
2088 pmap_allow_2m_x_ept_recalculate();
2091 * Initialize the vm page array entries for the kernel pmap's
2094 PMAP_LOCK(kernel_pmap);
2095 for (i = 0; i < nkpt; i++) {
2096 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2097 KASSERT(mpte >= vm_page_array &&
2098 mpte < &vm_page_array[vm_page_array_size],
2099 ("pmap_init: page table page is out of range"));
2100 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2101 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2102 mpte->ref_count = 1;
2105 * Collect the page table pages that were replaced by a 2MB
2106 * page in create_pagetables(). They are zero filled.
2108 if (i << PDRSHIFT < KERNend &&
2109 pmap_insert_pt_page(kernel_pmap, mpte, false))
2110 panic("pmap_init: pmap_insert_pt_page failed");
2112 PMAP_UNLOCK(kernel_pmap);
2116 * If the kernel is running on a virtual machine, then it must assume
2117 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2118 * be prepared for the hypervisor changing the vendor and family that
2119 * are reported by CPUID. Consequently, the workaround for AMD Family
2120 * 10h Erratum 383 is enabled if the processor's feature set does not
2121 * include at least one feature that is only supported by older Intel
2122 * or newer AMD processors.
2124 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2125 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2126 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2128 workaround_erratum383 = 1;
2131 * Are large page mappings enabled?
2133 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2134 if (pg_ps_enabled) {
2135 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2136 ("pmap_init: can't assign to pagesizes[1]"));
2137 pagesizes[1] = NBPDR;
2141 * Initialize pv chunk lists.
2143 for (i = 0; i < PMAP_MEMDOM; i++) {
2144 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2145 TAILQ_INIT(&pv_chunks[i].pvc_list);
2147 pmap_init_pv_table();
2149 pmap_initialized = 1;
2150 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2151 ppim = pmap_preinit_mapping + i;
2154 /* Make the direct map consistent */
2155 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2156 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2157 ppim->sz, ppim->mode);
2161 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2162 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2165 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2166 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2167 (vmem_addr_t *)&qframe);
2169 panic("qframe allocation failed");
2172 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2173 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2174 lm_ents = LMEPML4I - LMSPML4I + 1;
2176 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2177 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2179 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2180 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2181 if (large_vmem == NULL) {
2182 printf("pmap: cannot create large map\n");
2185 for (i = 0; i < lm_ents; i++) {
2186 m = pmap_large_map_getptp_unlocked();
2187 kernel_pmap->pm_pml4[LMSPML4I + i] = X86_PG_V |
2188 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2194 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2195 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2196 "Maximum number of PML4 entries for use by large map (tunable). "
2197 "Each entry corresponds to 512GB of address space.");
2199 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
2200 "2MB page mapping counters");
2202 static u_long pmap_pde_demotions;
2203 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2204 &pmap_pde_demotions, 0, "2MB page demotions");
2206 static u_long pmap_pde_mappings;
2207 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2208 &pmap_pde_mappings, 0, "2MB page mappings");
2210 static u_long pmap_pde_p_failures;
2211 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2212 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2214 static u_long pmap_pde_promotions;
2215 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2216 &pmap_pde_promotions, 0, "2MB page promotions");
2218 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD, 0,
2219 "1GB page mapping counters");
2221 static u_long pmap_pdpe_demotions;
2222 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2223 &pmap_pdpe_demotions, 0, "1GB page demotions");
2225 /***************************************************
2226 * Low level helper routines.....
2227 ***************************************************/
2230 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2232 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2234 switch (pmap->pm_type) {
2237 /* Verify that both PAT bits are not set at the same time */
2238 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2239 ("Invalid PAT bits in entry %#lx", entry));
2241 /* Swap the PAT bits if one of them is set */
2242 if ((entry & x86_pat_bits) != 0)
2243 entry ^= x86_pat_bits;
2247 * Nothing to do - the memory attributes are represented
2248 * the same way for regular pages and superpages.
2252 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2259 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2262 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2263 pat_index[(int)mode] >= 0);
2267 * Determine the appropriate bits to set in a PTE or PDE for a specified
2271 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2273 int cache_bits, pat_flag, pat_idx;
2275 if (!pmap_is_valid_memattr(pmap, mode))
2276 panic("Unknown caching mode %d\n", mode);
2278 switch (pmap->pm_type) {
2281 /* The PAT bit is different for PTE's and PDE's. */
2282 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2284 /* Map the caching mode to a PAT index. */
2285 pat_idx = pat_index[mode];
2287 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2290 cache_bits |= pat_flag;
2292 cache_bits |= PG_NC_PCD;
2294 cache_bits |= PG_NC_PWT;
2298 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2302 panic("unsupported pmap type %d", pmap->pm_type);
2305 return (cache_bits);
2309 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2313 switch (pmap->pm_type) {
2316 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2319 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2322 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2329 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2331 int pat_flag, pat_idx;
2334 switch (pmap->pm_type) {
2337 /* The PAT bit is different for PTE's and PDE's. */
2338 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2340 if ((pte & pat_flag) != 0)
2342 if ((pte & PG_NC_PCD) != 0)
2344 if ((pte & PG_NC_PWT) != 0)
2348 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2349 panic("EPT PTE %#lx has no PAT memory type", pte);
2350 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2354 /* See pmap_init_pat(). */
2364 pmap_ps_enabled(pmap_t pmap)
2367 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2371 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2374 switch (pmap->pm_type) {
2381 * This is a little bogus since the generation number is
2382 * supposed to be bumped up when a region of the address
2383 * space is invalidated in the page tables.
2385 * In this case the old PDE entry is valid but yet we want
2386 * to make sure that any mappings using the old entry are
2387 * invalidated in the TLB.
2389 * The reason this works as expected is because we rendezvous
2390 * "all" host cpus and force any vcpu context to exit as a
2393 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2396 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2398 pde_store(pde, newpde);
2402 * After changing the page size for the specified virtual address in the page
2403 * table, flush the corresponding entries from the processor's TLB. Only the
2404 * calling processor's TLB is affected.
2406 * The calling thread must be pinned to a processor.
2409 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2413 if (pmap_type_guest(pmap))
2416 KASSERT(pmap->pm_type == PT_X86,
2417 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2419 PG_G = pmap_global_bit(pmap);
2421 if ((newpde & PG_PS) == 0)
2422 /* Demotion: flush a specific 2MB page mapping. */
2424 else if ((newpde & PG_G) == 0)
2426 * Promotion: flush every 4KB page mapping from the TLB
2427 * because there are too many to flush individually.
2432 * Promotion: flush every 4KB page mapping from the TLB,
2433 * including any global (PG_G) mappings.
2441 * For SMP, these functions have to use the IPI mechanism for coherence.
2443 * N.B.: Before calling any of the following TLB invalidation functions,
2444 * the calling processor must ensure that all stores updating a non-
2445 * kernel page table are globally performed. Otherwise, another
2446 * processor could cache an old, pre-update entry without being
2447 * invalidated. This can happen one of two ways: (1) The pmap becomes
2448 * active on another processor after its pm_active field is checked by
2449 * one of the following functions but before a store updating the page
2450 * table is globally performed. (2) The pmap becomes active on another
2451 * processor before its pm_active field is checked but due to
2452 * speculative loads one of the following functions stills reads the
2453 * pmap as inactive on the other processor.
2455 * The kernel page table is exempt because its pm_active field is
2456 * immutable. The kernel page table is always active on every
2461 * Interrupt the cpus that are executing in the guest context.
2462 * This will force the vcpu to exit and the cached EPT mappings
2463 * will be invalidated by the host before the next vmresume.
2465 static __inline void
2466 pmap_invalidate_ept(pmap_t pmap)
2471 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2472 ("pmap_invalidate_ept: absurd pm_active"));
2475 * The TLB mappings associated with a vcpu context are not
2476 * flushed each time a different vcpu is chosen to execute.
2478 * This is in contrast with a process's vtop mappings that
2479 * are flushed from the TLB on each context switch.
2481 * Therefore we need to do more than just a TLB shootdown on
2482 * the active cpus in 'pmap->pm_active'. To do this we keep
2483 * track of the number of invalidations performed on this pmap.
2485 * Each vcpu keeps a cache of this counter and compares it
2486 * just before a vmresume. If the counter is out-of-date an
2487 * invept will be done to flush stale mappings from the TLB.
2489 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2492 * Force the vcpu to exit and trap back into the hypervisor.
2494 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2495 ipi_selected(pmap->pm_active, ipinum);
2500 pmap_invalidate_cpu_mask(pmap_t pmap)
2503 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2507 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2508 const bool invpcid_works1)
2510 struct invpcid_descr d;
2511 uint64_t kcr3, ucr3;
2515 cpuid = PCPU_GET(cpuid);
2516 if (pmap == PCPU_GET(curpmap)) {
2517 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2519 * Because pm_pcid is recalculated on a
2520 * context switch, we must disable switching.
2521 * Otherwise, we might use a stale value
2525 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2526 if (invpcid_works1) {
2527 d.pcid = pcid | PMAP_PCID_USER_PT;
2530 invpcid(&d, INVPCID_ADDR);
2532 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2533 ucr3 = pmap->pm_ucr3 | pcid |
2534 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2535 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2540 pmap->pm_pcids[cpuid].pm_gen = 0;
2544 pmap->pm_pcids[i].pm_gen = 0;
2548 * The fence is between stores to pm_gen and the read of the
2549 * pm_active mask. We need to ensure that it is impossible
2550 * for us to miss the bit update in pm_active and
2551 * simultaneously observe a non-zero pm_gen in
2552 * pmap_activate_sw(), otherwise TLB update is missed.
2553 * Without the fence, IA32 allows such an outcome. Note that
2554 * pm_active is updated by a locked operation, which provides
2555 * the reciprocal fence.
2557 atomic_thread_fence_seq_cst();
2561 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2564 pmap_invalidate_page_pcid(pmap, va, true);
2568 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2571 pmap_invalidate_page_pcid(pmap, va, false);
2575 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2579 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2582 if (pmap_pcid_enabled)
2583 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2584 pmap_invalidate_page_pcid_noinvpcid);
2585 return (pmap_invalidate_page_nopcid);
2589 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2592 if (pmap_type_guest(pmap)) {
2593 pmap_invalidate_ept(pmap);
2597 KASSERT(pmap->pm_type == PT_X86,
2598 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2601 if (pmap == kernel_pmap) {
2604 if (pmap == PCPU_GET(curpmap))
2606 pmap_invalidate_page_mode(pmap, va);
2608 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap);
2612 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2613 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2616 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2617 const bool invpcid_works1)
2619 struct invpcid_descr d;
2620 uint64_t kcr3, ucr3;
2624 cpuid = PCPU_GET(cpuid);
2625 if (pmap == PCPU_GET(curpmap)) {
2626 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2628 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2629 if (invpcid_works1) {
2630 d.pcid = pcid | PMAP_PCID_USER_PT;
2633 for (; d.addr < eva; d.addr += PAGE_SIZE)
2634 invpcid(&d, INVPCID_ADDR);
2636 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2637 ucr3 = pmap->pm_ucr3 | pcid |
2638 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2639 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2644 pmap->pm_pcids[cpuid].pm_gen = 0;
2648 pmap->pm_pcids[i].pm_gen = 0;
2650 /* See the comment in pmap_invalidate_page_pcid(). */
2651 atomic_thread_fence_seq_cst();
2655 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2659 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2663 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2667 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2671 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2675 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2679 if (pmap_pcid_enabled)
2680 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2681 pmap_invalidate_range_pcid_noinvpcid);
2682 return (pmap_invalidate_range_nopcid);
2686 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2690 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2691 pmap_invalidate_all(pmap);
2695 if (pmap_type_guest(pmap)) {
2696 pmap_invalidate_ept(pmap);
2700 KASSERT(pmap->pm_type == PT_X86,
2701 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2704 if (pmap == kernel_pmap) {
2705 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2708 if (pmap == PCPU_GET(curpmap)) {
2709 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2712 pmap_invalidate_range_mode(pmap, sva, eva);
2714 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap);
2719 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2721 struct invpcid_descr d;
2722 uint64_t kcr3, ucr3;
2726 if (pmap == kernel_pmap) {
2727 if (invpcid_works1) {
2728 bzero(&d, sizeof(d));
2729 invpcid(&d, INVPCID_CTXGLOB);
2734 cpuid = PCPU_GET(cpuid);
2735 if (pmap == PCPU_GET(curpmap)) {
2737 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2738 if (invpcid_works1) {
2742 invpcid(&d, INVPCID_CTX);
2743 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
2744 d.pcid |= PMAP_PCID_USER_PT;
2745 invpcid(&d, INVPCID_CTX);
2748 kcr3 = pmap->pm_cr3 | pcid;
2749 ucr3 = pmap->pm_ucr3;
2750 if (ucr3 != PMAP_NO_CR3) {
2751 ucr3 |= pcid | PMAP_PCID_USER_PT;
2752 pmap_pti_pcid_invalidate(ucr3, kcr3);
2759 pmap->pm_pcids[cpuid].pm_gen = 0;
2762 pmap->pm_pcids[i].pm_gen = 0;
2765 /* See the comment in pmap_invalidate_page_pcid(). */
2766 atomic_thread_fence_seq_cst();
2770 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
2773 pmap_invalidate_all_pcid(pmap, true);
2777 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
2780 pmap_invalidate_all_pcid(pmap, false);
2784 pmap_invalidate_all_nopcid(pmap_t pmap)
2787 if (pmap == kernel_pmap)
2789 else if (pmap == PCPU_GET(curpmap))
2793 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
2796 if (pmap_pcid_enabled)
2797 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
2798 pmap_invalidate_all_pcid_noinvpcid);
2799 return (pmap_invalidate_all_nopcid);
2803 pmap_invalidate_all(pmap_t pmap)
2806 if (pmap_type_guest(pmap)) {
2807 pmap_invalidate_ept(pmap);
2811 KASSERT(pmap->pm_type == PT_X86,
2812 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
2815 pmap_invalidate_all_mode(pmap);
2816 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap);
2821 pmap_invalidate_cache(void)
2831 cpuset_t invalidate; /* processors that invalidate their TLB */
2836 u_int store; /* processor that updates the PDE */
2840 pmap_update_pde_action(void *arg)
2842 struct pde_action *act = arg;
2844 if (act->store == PCPU_GET(cpuid))
2845 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
2849 pmap_update_pde_teardown(void *arg)
2851 struct pde_action *act = arg;
2853 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
2854 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
2858 * Change the page size for the specified virtual address in a way that
2859 * prevents any possibility of the TLB ever having two entries that map the
2860 * same virtual address using different page sizes. This is the recommended
2861 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
2862 * machine check exception for a TLB state that is improperly diagnosed as a
2866 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
2868 struct pde_action act;
2869 cpuset_t active, other_cpus;
2873 cpuid = PCPU_GET(cpuid);
2874 other_cpus = all_cpus;
2875 CPU_CLR(cpuid, &other_cpus);
2876 if (pmap == kernel_pmap || pmap_type_guest(pmap))
2879 active = pmap->pm_active;
2881 if (CPU_OVERLAP(&active, &other_cpus)) {
2883 act.invalidate = active;
2887 act.newpde = newpde;
2888 CPU_SET(cpuid, &active);
2889 smp_rendezvous_cpus(active,
2890 smp_no_rendezvous_barrier, pmap_update_pde_action,
2891 pmap_update_pde_teardown, &act);
2893 pmap_update_pde_store(pmap, pde, newpde);
2894 if (CPU_ISSET(cpuid, &active))
2895 pmap_update_pde_invalidate(pmap, va, newpde);
2901 * Normal, non-SMP, invalidation functions.
2904 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2906 struct invpcid_descr d;
2907 uint64_t kcr3, ucr3;
2910 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2914 KASSERT(pmap->pm_type == PT_X86,
2915 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2917 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2919 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2920 pmap->pm_ucr3 != PMAP_NO_CR3) {
2922 pcid = pmap->pm_pcids[0].pm_pcid;
2923 if (invpcid_works) {
2924 d.pcid = pcid | PMAP_PCID_USER_PT;
2927 invpcid(&d, INVPCID_ADDR);
2929 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2930 ucr3 = pmap->pm_ucr3 | pcid |
2931 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2932 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2936 } else if (pmap_pcid_enabled)
2937 pmap->pm_pcids[0].pm_gen = 0;
2941 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2943 struct invpcid_descr d;
2945 uint64_t kcr3, ucr3;
2947 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2951 KASSERT(pmap->pm_type == PT_X86,
2952 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
2954 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
2955 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2957 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
2958 pmap->pm_ucr3 != PMAP_NO_CR3) {
2960 if (invpcid_works) {
2961 d.pcid = pmap->pm_pcids[0].pm_pcid |
2965 for (; d.addr < eva; d.addr += PAGE_SIZE)
2966 invpcid(&d, INVPCID_ADDR);
2968 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
2969 pm_pcid | CR3_PCID_SAVE;
2970 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
2971 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2972 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2976 } else if (pmap_pcid_enabled) {
2977 pmap->pm_pcids[0].pm_gen = 0;
2982 pmap_invalidate_all(pmap_t pmap)
2984 struct invpcid_descr d;
2985 uint64_t kcr3, ucr3;
2987 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
2991 KASSERT(pmap->pm_type == PT_X86,
2992 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
2994 if (pmap == kernel_pmap) {
2995 if (pmap_pcid_enabled && invpcid_works) {
2996 bzero(&d, sizeof(d));
2997 invpcid(&d, INVPCID_CTXGLOB);
3001 } else if (pmap == PCPU_GET(curpmap)) {
3002 if (pmap_pcid_enabled) {
3004 if (invpcid_works) {
3005 d.pcid = pmap->pm_pcids[0].pm_pcid;
3008 invpcid(&d, INVPCID_CTX);
3009 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3010 d.pcid |= PMAP_PCID_USER_PT;
3011 invpcid(&d, INVPCID_CTX);
3014 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3015 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3016 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3017 0].pm_pcid | PMAP_PCID_USER_PT;
3018 pmap_pti_pcid_invalidate(ucr3, kcr3);
3026 } else if (pmap_pcid_enabled) {
3027 pmap->pm_pcids[0].pm_gen = 0;
3032 pmap_invalidate_cache(void)
3039 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3042 pmap_update_pde_store(pmap, pde, newpde);
3043 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3044 pmap_update_pde_invalidate(pmap, va, newpde);
3046 pmap->pm_pcids[0].pm_gen = 0;
3051 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3055 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3056 * by a promotion that did not invalidate the 512 4KB page mappings
3057 * that might exist in the TLB. Consequently, at this point, the TLB
3058 * may hold both 4KB and 2MB page mappings for the address range [va,
3059 * va + NBPDR). Therefore, the entire range must be invalidated here.
3060 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3061 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3062 * single INVLPG suffices to invalidate the 2MB page mapping from the
3065 if ((pde & PG_PROMOTED) != 0)
3066 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3068 pmap_invalidate_page(pmap, va);
3071 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3072 (vm_offset_t sva, vm_offset_t eva))
3075 if ((cpu_feature & CPUID_SS) != 0)
3076 return (pmap_invalidate_cache_range_selfsnoop);
3077 if ((cpu_feature & CPUID_CLFSH) != 0)
3078 return (pmap_force_invalidate_cache_range);
3079 return (pmap_invalidate_cache_range_all);
3082 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3085 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3088 KASSERT((sva & PAGE_MASK) == 0,
3089 ("pmap_invalidate_cache_range: sva not page-aligned"));
3090 KASSERT((eva & PAGE_MASK) == 0,
3091 ("pmap_invalidate_cache_range: eva not page-aligned"));
3095 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3098 pmap_invalidate_cache_range_check_align(sva, eva);
3102 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3105 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3108 * XXX: Some CPUs fault, hang, or trash the local APIC
3109 * registers if we use CLFLUSH on the local APIC range. The
3110 * local APIC is always uncached, so we don't need to flush
3111 * for that range anyway.
3113 if (pmap_kextract(sva) == lapic_paddr)
3116 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3118 * Do per-cache line flush. Use a locked
3119 * instruction to insure that previous stores are
3120 * included in the write-back. The processor
3121 * propagates flush to other processors in the cache
3124 atomic_thread_fence_seq_cst();
3125 for (; sva < eva; sva += cpu_clflush_line_size)
3127 atomic_thread_fence_seq_cst();
3130 * Writes are ordered by CLFLUSH on Intel CPUs.
3132 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3134 for (; sva < eva; sva += cpu_clflush_line_size)
3136 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3142 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3145 pmap_invalidate_cache_range_check_align(sva, eva);
3146 pmap_invalidate_cache();
3150 * Remove the specified set of pages from the data and instruction caches.
3152 * In contrast to pmap_invalidate_cache_range(), this function does not
3153 * rely on the CPU's self-snoop feature, because it is intended for use
3154 * when moving pages into a different cache domain.
3157 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3159 vm_offset_t daddr, eva;
3163 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3164 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3165 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3166 pmap_invalidate_cache();
3169 atomic_thread_fence_seq_cst();
3170 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3172 for (i = 0; i < count; i++) {
3173 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3174 eva = daddr + PAGE_SIZE;
3175 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3183 atomic_thread_fence_seq_cst();
3184 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3190 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3193 pmap_invalidate_cache_range_check_align(sva, eva);
3195 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3196 pmap_force_invalidate_cache_range(sva, eva);
3200 /* See comment in pmap_force_invalidate_cache_range(). */
3201 if (pmap_kextract(sva) == lapic_paddr)
3204 atomic_thread_fence_seq_cst();
3205 for (; sva < eva; sva += cpu_clflush_line_size)
3207 atomic_thread_fence_seq_cst();
3211 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3215 int error, pte_bits;
3217 KASSERT((spa & PAGE_MASK) == 0,
3218 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3219 KASSERT((epa & PAGE_MASK) == 0,
3220 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3222 if (spa < dmaplimit) {
3223 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3225 if (dmaplimit >= epa)
3230 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3232 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3234 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3235 pte = vtopte(vaddr);
3236 for (; spa < epa; spa += PAGE_SIZE) {
3238 pte_store(pte, spa | pte_bits);
3240 /* XXXKIB atomic inside flush_cache_range are excessive */
3241 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3244 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3248 * Routine: pmap_extract
3250 * Extract the physical page address associated
3251 * with the given map/virtual_address pair.
3254 pmap_extract(pmap_t pmap, vm_offset_t va)
3258 pt_entry_t *pte, PG_V;
3262 PG_V = pmap_valid_bit(pmap);
3264 pdpe = pmap_pdpe(pmap, va);
3265 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3266 if ((*pdpe & PG_PS) != 0)
3267 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3269 pde = pmap_pdpe_to_pde(pdpe, va);
3270 if ((*pde & PG_V) != 0) {
3271 if ((*pde & PG_PS) != 0) {
3272 pa = (*pde & PG_PS_FRAME) |
3275 pte = pmap_pde_to_pte(pde, va);
3276 pa = (*pte & PG_FRAME) |
3287 * Routine: pmap_extract_and_hold
3289 * Atomically extract and hold the physical page
3290 * with the given pmap and virtual address pair
3291 * if that mapping permits the given protection.
3294 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3296 pd_entry_t pde, *pdep;
3297 pt_entry_t pte, PG_RW, PG_V;
3301 PG_RW = pmap_rw_bit(pmap);
3302 PG_V = pmap_valid_bit(pmap);
3305 pdep = pmap_pde(pmap, va);
3306 if (pdep != NULL && (pde = *pdep)) {
3308 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3309 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3312 pte = *pmap_pde_to_pte(pdep, va);
3313 if ((pte & PG_V) != 0 &&
3314 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3315 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3317 if (m != NULL && !vm_page_wire_mapped(m))
3325 pmap_kextract(vm_offset_t va)
3330 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3331 pa = DMAP_TO_PHYS(va);
3332 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3333 pa = pmap_large_map_kextract(va);
3337 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3340 * Beware of a concurrent promotion that changes the
3341 * PDE at this point! For example, vtopte() must not
3342 * be used to access the PTE because it would use the
3343 * new PDE. It is, however, safe to use the old PDE
3344 * because the page table page is preserved by the
3347 pa = *pmap_pde_to_pte(&pde, va);
3348 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3354 /***************************************************
3355 * Low level mapping routines.....
3356 ***************************************************/
3359 * Add a wired page to the kva.
3360 * Note: not SMP coherent.
3363 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3368 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3371 static __inline void
3372 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3378 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3379 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3383 * Remove a page from the kernel pagetables.
3384 * Note: not SMP coherent.
3387 pmap_kremove(vm_offset_t va)
3396 * Used to map a range of physical addresses into kernel
3397 * virtual address space.
3399 * The value passed in '*virt' is a suggested virtual address for
3400 * the mapping. Architectures which can support a direct-mapped
3401 * physical to virtual region can return the appropriate address
3402 * within that region, leaving '*virt' unchanged. Other
3403 * architectures should map the pages starting at '*virt' and
3404 * update '*virt' with the first usable address after the mapped
3408 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3410 return PHYS_TO_DMAP(start);
3415 * Add a list of wired pages to the kva
3416 * this routine is only used for temporary
3417 * kernel mappings that do not need to have
3418 * page modification or references recorded.
3419 * Note that old mappings are simply written
3420 * over. The page *must* be wired.
3421 * Note: SMP coherent. Uses a ranged shootdown IPI.
3424 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3426 pt_entry_t *endpte, oldpte, pa, *pte;
3432 endpte = pte + count;
3433 while (pte < endpte) {
3435 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3436 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3437 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3439 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3443 if (__predict_false((oldpte & X86_PG_V) != 0))
3444 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3449 * This routine tears out page mappings from the
3450 * kernel -- it is meant only for temporary mappings.
3451 * Note: SMP coherent. Uses a ranged shootdown IPI.
3454 pmap_qremove(vm_offset_t sva, int count)
3459 while (count-- > 0) {
3460 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3464 pmap_invalidate_range(kernel_pmap, sva, va);
3467 /***************************************************
3468 * Page table page management routines.....
3469 ***************************************************/
3471 * Schedule the specified unused page table page to be freed. Specifically,
3472 * add the page to the specified list of pages that will be released to the
3473 * physical memory manager after the TLB has been updated.
3475 static __inline void
3476 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3477 boolean_t set_PG_ZERO)
3481 m->flags |= PG_ZERO;
3483 m->flags &= ~PG_ZERO;
3484 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3488 * Inserts the specified page table page into the specified pmap's collection
3489 * of idle page table pages. Each of a pmap's page table pages is responsible
3490 * for mapping a distinct range of virtual addresses. The pmap's collection is
3491 * ordered by this virtual address range.
3493 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3496 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3499 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3500 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3501 return (vm_radix_insert(&pmap->pm_root, mpte));
3505 * Removes the page table page mapping the specified virtual address from the
3506 * specified pmap's collection of idle page table pages, and returns it.
3507 * Otherwise, returns NULL if there is no page table page corresponding to the
3508 * specified virtual address.
3510 static __inline vm_page_t
3511 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3514 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3515 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3519 * Decrements a page table page's reference count, which is used to record the
3520 * number of valid page table entries within the page. If the reference count
3521 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3522 * page table page was unmapped and FALSE otherwise.
3524 static inline boolean_t
3525 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3529 if (m->ref_count == 0) {
3530 _pmap_unwire_ptp(pmap, va, m, free);
3537 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3540 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3542 * unmap the page table page
3544 if (m->pindex >= NUPDE + NUPDPE) {
3547 pml4 = pmap_pml4e(pmap, va);
3549 if (pmap->pm_pml4u != NULL && va <= VM_MAXUSER_ADDRESS) {
3550 pml4 = &pmap->pm_pml4u[pmap_pml4e_index(va)];
3553 } else if (m->pindex >= NUPDE) {
3556 pdp = pmap_pdpe(pmap, va);
3561 pd = pmap_pde(pmap, va);
3564 pmap_resident_count_dec(pmap, 1);
3565 if (m->pindex < NUPDE) {
3566 /* We just released a PT, unhold the matching PD */
3569 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3570 pmap_unwire_ptp(pmap, va, pdpg, free);
3571 } else if (m->pindex < NUPDE + NUPDPE) {
3572 /* We just released a PD, unhold the matching PDP */
3575 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3576 pmap_unwire_ptp(pmap, va, pdppg, free);
3580 * Put page on a list so that it is released after
3581 * *ALL* TLB shootdown is done
3583 pmap_add_delayed_free_list(m, free, TRUE);
3587 * After removing a page table entry, this routine is used to
3588 * conditionally free the page, and manage the reference count.
3591 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3592 struct spglist *free)
3596 if (va >= VM_MAXUSER_ADDRESS)
3598 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3599 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3600 return (pmap_unwire_ptp(pmap, va, mpte, free));
3604 * Release a page table page reference after a failed attempt to create a
3608 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3610 struct spglist free;
3613 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3615 * Although "va" was never mapped, paging-structure caches
3616 * could nonetheless have entries that refer to the freed
3617 * page table pages. Invalidate those entries.
3619 pmap_invalidate_page(pmap, va);
3620 vm_page_free_pages_toq(&free, true);
3625 pmap_pinit0(pmap_t pmap)
3631 PMAP_LOCK_INIT(pmap);
3632 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
3633 pmap->pm_pml4u = NULL;
3634 pmap->pm_cr3 = KPML4phys;
3635 /* hack to keep pmap_pti_pcid_invalidate() alive */
3636 pmap->pm_ucr3 = PMAP_NO_CR3;
3637 pmap->pm_root.rt_root = 0;
3638 CPU_ZERO(&pmap->pm_active);
3639 TAILQ_INIT(&pmap->pm_pvchunk);
3640 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3641 pmap->pm_flags = pmap_flags;
3643 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3644 pmap->pm_pcids[i].pm_gen = 1;
3646 pmap_activate_boot(pmap);
3651 p->p_md.md_flags |= P_MD_KPTI;
3654 pmap_thread_init_invl_gen(td);
3656 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3657 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3658 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3664 pmap_pinit_pml4(vm_page_t pml4pg)
3666 pml4_entry_t *pm_pml4;
3669 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3671 /* Wire in kernel global address entries. */
3672 for (i = 0; i < NKPML4E; i++) {
3673 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3676 for (i = 0; i < ndmpdpphys; i++) {
3677 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3681 /* install self-referential address mapping entry(s) */
3682 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3683 X86_PG_A | X86_PG_M;
3685 /* install large map entries if configured */
3686 for (i = 0; i < lm_ents; i++)
3687 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pml4[LMSPML4I + i];
3691 pmap_pinit_pml4_pti(vm_page_t pml4pg)
3693 pml4_entry_t *pm_pml4;
3696 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3697 for (i = 0; i < NPML4EPG; i++)
3698 pm_pml4[i] = pti_pml4[i];
3702 * Initialize a preallocated and zeroed pmap structure,
3703 * such as one in a vmspace structure.
3706 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
3708 vm_page_t pml4pg, pml4pgu;
3709 vm_paddr_t pml4phys;
3713 * allocate the page directory page
3715 pml4pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
3716 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
3718 pml4phys = VM_PAGE_TO_PHYS(pml4pg);
3719 pmap->pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(pml4phys);
3721 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
3722 pmap->pm_pcids[i].pm_gen = 0;
3724 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
3725 pmap->pm_ucr3 = PMAP_NO_CR3;
3726 pmap->pm_pml4u = NULL;
3728 pmap->pm_type = pm_type;
3729 if ((pml4pg->flags & PG_ZERO) == 0)
3730 pagezero(pmap->pm_pml4);
3733 * Do not install the host kernel mappings in the nested page
3734 * tables. These mappings are meaningless in the guest physical
3736 * Install minimal kernel mappings in PTI case.
3738 if (pm_type == PT_X86) {
3739 pmap->pm_cr3 = pml4phys;
3740 pmap_pinit_pml4(pml4pg);
3741 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
3742 pml4pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
3743 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
3744 pmap->pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(
3745 VM_PAGE_TO_PHYS(pml4pgu));
3746 pmap_pinit_pml4_pti(pml4pgu);
3747 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pml4pgu);
3749 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3750 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
3751 pkru_free_range, pmap, M_NOWAIT);
3755 pmap->pm_root.rt_root = 0;
3756 CPU_ZERO(&pmap->pm_active);
3757 TAILQ_INIT(&pmap->pm_pvchunk);
3758 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3759 pmap->pm_flags = flags;
3760 pmap->pm_eptgen = 0;
3766 pmap_pinit(pmap_t pmap)
3769 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
3773 * This routine is called if the desired page table page does not exist.
3775 * If page table page allocation fails, this routine may sleep before
3776 * returning NULL. It sleeps only if a lock pointer was given.
3778 * Note: If a page allocation fails at page table level two or three,
3779 * one or two pages may be held during the wait, only to be released
3780 * afterwards. This conservative approach is easily argued to avoid
3784 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp)
3786 vm_page_t m, pdppg, pdpg;
3787 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
3789 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3791 PG_A = pmap_accessed_bit(pmap);
3792 PG_M = pmap_modified_bit(pmap);
3793 PG_V = pmap_valid_bit(pmap);
3794 PG_RW = pmap_rw_bit(pmap);
3797 * Allocate a page table page.
3799 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
3800 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
3801 if (lockp != NULL) {
3802 RELEASE_PV_LIST_LOCK(lockp);
3804 PMAP_ASSERT_NOT_IN_DI();
3810 * Indicate the need to retry. While waiting, the page table
3811 * page may have been allocated.
3815 if ((m->flags & PG_ZERO) == 0)
3819 * Map the pagetable page into the process address space, if
3820 * it isn't already there.
3823 if (ptepindex >= (NUPDE + NUPDPE)) {
3824 pml4_entry_t *pml4, *pml4u;
3825 vm_pindex_t pml4index;
3827 /* Wire up a new PDPE page */
3828 pml4index = ptepindex - (NUPDE + NUPDPE);
3829 pml4 = &pmap->pm_pml4[pml4index];
3830 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3831 if (pmap->pm_pml4u != NULL && pml4index < NUPML4E) {
3833 * PTI: Make all user-space mappings in the
3834 * kernel-mode page table no-execute so that
3835 * we detect any programming errors that leave
3836 * the kernel-mode page table active on return
3839 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3842 pml4u = &pmap->pm_pml4u[pml4index];
3843 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
3847 } else if (ptepindex >= NUPDE) {
3848 vm_pindex_t pml4index;
3849 vm_pindex_t pdpindex;
3853 /* Wire up a new PDE page */
3854 pdpindex = ptepindex - NUPDE;
3855 pml4index = pdpindex >> NPML4EPGSHIFT;
3857 pml4 = &pmap->pm_pml4[pml4index];
3858 if ((*pml4 & PG_V) == 0) {
3859 /* Have to allocate a new pdp, recurse */
3860 if (_pmap_allocpte(pmap, NUPDE + NUPDPE + pml4index,
3862 vm_page_unwire_noq(m);
3863 vm_page_free_zero(m);
3867 /* Add reference to pdp page */
3868 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
3871 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3873 /* Now find the pdp page */
3874 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3875 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3878 vm_pindex_t pml4index;
3879 vm_pindex_t pdpindex;
3884 /* Wire up a new PTE page */
3885 pdpindex = ptepindex >> NPDPEPGSHIFT;
3886 pml4index = pdpindex >> NPML4EPGSHIFT;
3888 /* First, find the pdp and check that its valid. */
3889 pml4 = &pmap->pm_pml4[pml4index];
3890 if ((*pml4 & PG_V) == 0) {
3891 /* Have to allocate a new pd, recurse */
3892 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3894 vm_page_unwire_noq(m);
3895 vm_page_free_zero(m);
3898 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3899 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3901 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
3902 pdp = &pdp[pdpindex & ((1ul << NPDPEPGSHIFT) - 1)];
3903 if ((*pdp & PG_V) == 0) {
3904 /* Have to allocate a new pd, recurse */
3905 if (_pmap_allocpte(pmap, NUPDE + pdpindex,
3907 vm_page_unwire_noq(m);
3908 vm_page_free_zero(m);
3912 /* Add reference to the pd page */
3913 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
3917 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
3919 /* Now we know where the page directory page is */
3920 pd = &pd[ptepindex & ((1ul << NPDEPGSHIFT) - 1)];
3921 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
3924 pmap_resident_count_inc(pmap, 1);
3930 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
3931 struct rwlock **lockp)
3933 pdp_entry_t *pdpe, PG_V;
3936 vm_pindex_t pdpindex;
3938 PG_V = pmap_valid_bit(pmap);
3941 pdpe = pmap_pdpe(pmap, va);
3942 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3943 pde = pmap_pdpe_to_pde(pdpe, va);
3944 if (va < VM_MAXUSER_ADDRESS) {
3945 /* Add a reference to the pd page. */
3946 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
3950 } else if (va < VM_MAXUSER_ADDRESS) {
3951 /* Allocate a pd page. */
3952 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
3953 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp);
3960 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
3961 pde = &pde[pmap_pde_index(va)];
3963 panic("pmap_alloc_pde: missing page table page for va %#lx",
3970 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
3972 vm_pindex_t ptepindex;
3973 pd_entry_t *pd, PG_V;
3976 PG_V = pmap_valid_bit(pmap);
3979 * Calculate pagetable page index
3981 ptepindex = pmap_pde_pindex(va);
3984 * Get the page directory entry
3986 pd = pmap_pde(pmap, va);
3989 * This supports switching from a 2MB page to a
3992 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
3993 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
3995 * Invalidation of the 2MB page mapping may have caused
3996 * the deallocation of the underlying PD page.
4003 * If the page table page is mapped, we just increment the
4004 * hold count, and activate it.
4006 if (pd != NULL && (*pd & PG_V) != 0) {
4007 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4011 * Here if the pte page isn't mapped, or if it has been
4014 m = _pmap_allocpte(pmap, ptepindex, lockp);
4015 if (m == NULL && lockp != NULL)
4022 /***************************************************
4023 * Pmap allocation/deallocation routines.
4024 ***************************************************/
4027 * Release any resources held by the given physical map.
4028 * Called when a pmap initialized by pmap_pinit is being released.
4029 * Should only be called if the map contains no valid mappings.
4032 pmap_release(pmap_t pmap)
4037 KASSERT(pmap->pm_stats.resident_count == 0,
4038 ("pmap_release: pmap resident count %ld != 0",
4039 pmap->pm_stats.resident_count));
4040 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4041 ("pmap_release: pmap has reserved page table page(s)"));
4042 KASSERT(CPU_EMPTY(&pmap->pm_active),
4043 ("releasing active pmap %p", pmap));
4045 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4));
4047 for (i = 0; i < NKPML4E; i++) /* KVA */
4048 pmap->pm_pml4[KPML4BASE + i] = 0;
4049 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4050 pmap->pm_pml4[DMPML4I + i] = 0;
4051 pmap->pm_pml4[PML4PML4I] = 0; /* Recursive Mapping */
4052 for (i = 0; i < lm_ents; i++) /* Large Map */
4053 pmap->pm_pml4[LMSPML4I + i] = 0;
4055 vm_page_unwire_noq(m);
4056 vm_page_free_zero(m);
4058 if (pmap->pm_pml4u != NULL) {
4059 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pml4u));
4060 vm_page_unwire_noq(m);
4063 if (pmap->pm_type == PT_X86 &&
4064 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4065 rangeset_fini(&pmap->pm_pkru);
4069 kvm_size(SYSCTL_HANDLER_ARGS)
4071 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4073 return sysctl_handle_long(oidp, &ksize, 0, req);
4075 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4076 0, 0, kvm_size, "LU",
4080 kvm_free(SYSCTL_HANDLER_ARGS)
4082 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4084 return sysctl_handle_long(oidp, &kfree, 0, req);
4086 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4087 0, 0, kvm_free, "LU",
4088 "Amount of KVM free");
4091 * Allocate physical memory for the vm_page array and map it into KVA,
4092 * attempting to back the vm_pages with domain-local memory.
4095 pmap_page_array_startup(long pages)
4098 pd_entry_t *pde, newpdir;
4099 vm_offset_t va, start, end;
4104 vm_page_array_size = pages;
4106 start = VM_MIN_KERNEL_ADDRESS;
4107 end = start + pages * sizeof(struct vm_page);
4108 for (va = start; va < end; va += NBPDR) {
4109 pfn = first_page + (va - start) / sizeof(struct vm_page);
4110 domain = _vm_phys_domain(ptoa(pfn));
4111 pdpe = pmap_pdpe(kernel_pmap, va);
4112 if ((*pdpe & X86_PG_V) == 0) {
4113 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4115 pagezero((void *)PHYS_TO_DMAP(pa));
4116 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4117 X86_PG_A | X86_PG_M);
4119 pde = pmap_pdpe_to_pde(pdpe, va);
4120 if ((*pde & X86_PG_V) != 0)
4121 panic("Unexpected pde");
4122 pa = vm_phys_early_alloc(domain, NBPDR);
4123 for (i = 0; i < NPDEPG; i++)
4124 dump_add_page(pa + i * PAGE_SIZE);
4125 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4126 X86_PG_M | PG_PS | pg_g | pg_nx);
4127 pde_store(pde, newpdir);
4129 vm_page_array = (vm_page_t)start;
4133 * grow the number of kernel page table entries, if needed
4136 pmap_growkernel(vm_offset_t addr)
4140 pd_entry_t *pde, newpdir;
4143 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4146 * Return if "addr" is within the range of kernel page table pages
4147 * that were preallocated during pmap bootstrap. Moreover, leave
4148 * "kernel_vm_end" and the kernel page table as they were.
4150 * The correctness of this action is based on the following
4151 * argument: vm_map_insert() allocates contiguous ranges of the
4152 * kernel virtual address space. It calls this function if a range
4153 * ends after "kernel_vm_end". If the kernel is mapped between
4154 * "kernel_vm_end" and "addr", then the range cannot begin at
4155 * "kernel_vm_end". In fact, its beginning address cannot be less
4156 * than the kernel. Thus, there is no immediate need to allocate
4157 * any new kernel page table pages between "kernel_vm_end" and
4160 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4163 addr = roundup2(addr, NBPDR);
4164 if (addr - 1 >= vm_map_max(kernel_map))
4165 addr = vm_map_max(kernel_map);
4166 while (kernel_vm_end < addr) {
4167 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4168 if ((*pdpe & X86_PG_V) == 0) {
4169 /* We need a new PDP entry */
4170 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4171 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4172 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4174 panic("pmap_growkernel: no memory to grow kernel");
4175 if ((nkpg->flags & PG_ZERO) == 0)
4176 pmap_zero_page(nkpg);
4177 paddr = VM_PAGE_TO_PHYS(nkpg);
4178 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4179 X86_PG_A | X86_PG_M);
4180 continue; /* try again */
4182 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4183 if ((*pde & X86_PG_V) != 0) {
4184 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4185 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4186 kernel_vm_end = vm_map_max(kernel_map);
4192 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4193 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4196 panic("pmap_growkernel: no memory to grow kernel");
4197 if ((nkpg->flags & PG_ZERO) == 0)
4198 pmap_zero_page(nkpg);
4199 paddr = VM_PAGE_TO_PHYS(nkpg);
4200 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4201 pde_store(pde, newpdir);
4203 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4204 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4205 kernel_vm_end = vm_map_max(kernel_map);
4212 /***************************************************
4213 * page management routines.
4214 ***************************************************/
4216 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4217 CTASSERT(_NPCM == 3);
4218 CTASSERT(_NPCPV == 168);
4220 static __inline struct pv_chunk *
4221 pv_to_chunk(pv_entry_t pv)
4224 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4227 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4229 #define PC_FREE0 0xfffffffffffffffful
4230 #define PC_FREE1 0xfffffffffffffffful
4231 #define PC_FREE2 0x000000fffffffffful
4233 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4236 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4238 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4239 "Current number of pv entry chunks");
4240 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4241 "Current number of pv entry chunks allocated");
4242 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4243 "Current number of pv entry chunks frees");
4244 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4245 "Number of times tried to get a chunk page but failed.");
4247 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4248 static int pv_entry_spare;
4250 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4251 "Current number of pv entry frees");
4252 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4253 "Current number of pv entry allocs");
4254 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4255 "Current number of pv entries");
4256 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4257 "Current number of spare pv entries");
4261 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4266 pmap_invalidate_all(pmap);
4267 if (pmap != locked_pmap)
4270 pmap_delayed_invl_finish();
4274 * We are in a serious low memory condition. Resort to
4275 * drastic measures to free some pages so we can allocate
4276 * another pv entry chunk.
4278 * Returns NULL if PV entries were reclaimed from the specified pmap.
4280 * We do not, however, unmap 2mpages because subsequent accesses will
4281 * allocate per-page pv entries until repromotion occurs, thereby
4282 * exacerbating the shortage of free pv entries.
4285 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4287 struct pv_chunks_list *pvc;
4288 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4289 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4290 struct md_page *pvh;
4292 pmap_t next_pmap, pmap;
4293 pt_entry_t *pte, tpte;
4294 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4298 struct spglist free;
4300 int bit, field, freed;
4303 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4304 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4307 PG_G = PG_A = PG_M = PG_RW = 0;
4309 bzero(&pc_marker_b, sizeof(pc_marker_b));
4310 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4311 pc_marker = (struct pv_chunk *)&pc_marker_b;
4312 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4315 * A delayed invalidation block should already be active if
4316 * pmap_advise() or pmap_remove() called this function by way
4317 * of pmap_demote_pde_locked().
4319 start_di = pmap_not_in_di();
4321 pvc = &pv_chunks[domain];
4322 mtx_lock(&pvc->pvc_lock);
4323 pvc->active_reclaims++;
4324 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4325 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4326 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4327 SLIST_EMPTY(&free)) {
4328 next_pmap = pc->pc_pmap;
4329 if (next_pmap == NULL) {
4331 * The next chunk is a marker. However, it is
4332 * not our marker, so active_reclaims must be
4333 * > 1. Consequently, the next_chunk code
4334 * will not rotate the pv_chunks list.
4338 mtx_unlock(&pvc->pvc_lock);
4341 * A pv_chunk can only be removed from the pc_lru list
4342 * when both pc_chunks_mutex is owned and the
4343 * corresponding pmap is locked.
4345 if (pmap != next_pmap) {
4346 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4349 /* Avoid deadlock and lock recursion. */
4350 if (pmap > locked_pmap) {
4351 RELEASE_PV_LIST_LOCK(lockp);
4354 pmap_delayed_invl_start();
4355 mtx_lock(&pvc->pvc_lock);
4357 } else if (pmap != locked_pmap) {
4358 if (PMAP_TRYLOCK(pmap)) {
4360 pmap_delayed_invl_start();
4361 mtx_lock(&pvc->pvc_lock);
4364 pmap = NULL; /* pmap is not locked */
4365 mtx_lock(&pvc->pvc_lock);
4366 pc = TAILQ_NEXT(pc_marker, pc_lru);
4368 pc->pc_pmap != next_pmap)
4372 } else if (start_di)
4373 pmap_delayed_invl_start();
4374 PG_G = pmap_global_bit(pmap);
4375 PG_A = pmap_accessed_bit(pmap);
4376 PG_M = pmap_modified_bit(pmap);
4377 PG_RW = pmap_rw_bit(pmap);
4381 * Destroy every non-wired, 4 KB page mapping in the chunk.
4384 for (field = 0; field < _NPCM; field++) {
4385 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4386 inuse != 0; inuse &= ~(1UL << bit)) {
4388 pv = &pc->pc_pventry[field * 64 + bit];
4390 pde = pmap_pde(pmap, va);
4391 if ((*pde & PG_PS) != 0)
4393 pte = pmap_pde_to_pte(pde, va);
4394 if ((*pte & PG_W) != 0)
4396 tpte = pte_load_clear(pte);
4397 if ((tpte & PG_G) != 0)
4398 pmap_invalidate_page(pmap, va);
4399 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4400 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4402 if ((tpte & PG_A) != 0)
4403 vm_page_aflag_set(m, PGA_REFERENCED);
4404 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4405 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4407 if (TAILQ_EMPTY(&m->md.pv_list) &&
4408 (m->flags & PG_FICTITIOUS) == 0) {
4409 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4410 if (TAILQ_EMPTY(&pvh->pv_list)) {
4411 vm_page_aflag_clear(m,
4415 pmap_delayed_invl_page(m);
4416 pc->pc_map[field] |= 1UL << bit;
4417 pmap_unuse_pt(pmap, va, *pde, &free);
4422 mtx_lock(&pvc->pvc_lock);
4425 /* Every freed mapping is for a 4 KB page. */
4426 pmap_resident_count_dec(pmap, freed);
4427 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4428 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4429 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4430 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4431 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4432 pc->pc_map[2] == PC_FREE2) {
4433 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4434 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4435 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4436 /* Entire chunk is free; return it. */
4437 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4438 dump_drop_page(m_pc->phys_addr);
4439 mtx_lock(&pvc->pvc_lock);
4440 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4443 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4444 mtx_lock(&pvc->pvc_lock);
4445 /* One freed pv entry in locked_pmap is sufficient. */
4446 if (pmap == locked_pmap)
4449 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4450 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4451 if (pvc->active_reclaims == 1 && pmap != NULL) {
4453 * Rotate the pv chunks list so that we do not
4454 * scan the same pv chunks that could not be
4455 * freed (because they contained a wired
4456 * and/or superpage mapping) on every
4457 * invocation of reclaim_pv_chunk().
4459 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4460 MPASS(pc->pc_pmap != NULL);
4461 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4462 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4466 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4467 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4468 pvc->active_reclaims--;
4469 mtx_unlock(&pvc->pvc_lock);
4470 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4471 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4472 m_pc = SLIST_FIRST(&free);
4473 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4474 /* Recycle a freed page table page. */
4475 m_pc->ref_count = 1;
4477 vm_page_free_pages_toq(&free, true);
4482 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4487 domain = PCPU_GET(domain);
4488 for (i = 0; i < vm_ndomains; i++) {
4489 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4492 domain = (domain + 1) % vm_ndomains;
4499 * free the pv_entry back to the free list
4502 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4504 struct pv_chunk *pc;
4505 int idx, field, bit;
4507 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4508 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4509 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4510 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4511 pc = pv_to_chunk(pv);
4512 idx = pv - &pc->pc_pventry[0];
4515 pc->pc_map[field] |= 1ul << bit;
4516 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4517 pc->pc_map[2] != PC_FREE2) {
4518 /* 98% of the time, pc is already at the head of the list. */
4519 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4520 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4521 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4525 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4530 free_pv_chunk_dequeued(struct pv_chunk *pc)
4534 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4535 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4536 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4537 /* entire chunk is free, return it */
4538 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4539 dump_drop_page(m->phys_addr);
4540 vm_page_unwire_noq(m);
4545 free_pv_chunk(struct pv_chunk *pc)
4547 struct pv_chunks_list *pvc;
4549 pvc = &pv_chunks[pc_to_domain(pc)];
4550 mtx_lock(&pvc->pvc_lock);
4551 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4552 mtx_unlock(&pvc->pvc_lock);
4553 free_pv_chunk_dequeued(pc);
4557 free_pv_chunk_batch(struct pv_chunklist *batch)
4559 struct pv_chunks_list *pvc;
4560 struct pv_chunk *pc, *npc;
4563 for (i = 0; i < vm_ndomains; i++) {
4564 if (TAILQ_EMPTY(&batch[i]))
4566 pvc = &pv_chunks[i];
4567 mtx_lock(&pvc->pvc_lock);
4568 TAILQ_FOREACH(pc, &batch[i], pc_list) {
4569 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4571 mtx_unlock(&pvc->pvc_lock);
4574 for (i = 0; i < vm_ndomains; i++) {
4575 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
4576 free_pv_chunk_dequeued(pc);
4582 * Returns a new PV entry, allocating a new PV chunk from the system when
4583 * needed. If this PV chunk allocation fails and a PV list lock pointer was
4584 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
4587 * The given PV list lock may be released.
4590 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
4592 struct pv_chunks_list *pvc;
4595 struct pv_chunk *pc;
4598 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4599 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
4601 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4603 for (field = 0; field < _NPCM; field++) {
4604 if (pc->pc_map[field]) {
4605 bit = bsfq(pc->pc_map[field]);
4609 if (field < _NPCM) {
4610 pv = &pc->pc_pventry[field * 64 + bit];
4611 pc->pc_map[field] &= ~(1ul << bit);
4612 /* If this was the last item, move it to tail */
4613 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
4614 pc->pc_map[2] == 0) {
4615 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4616 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
4619 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4620 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
4624 /* No free items, allocate another chunk */
4625 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4628 if (lockp == NULL) {
4629 PV_STAT(pc_chunk_tryfail++);
4632 m = reclaim_pv_chunk(pmap, lockp);
4636 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4637 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4638 dump_add_page(m->phys_addr);
4639 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4641 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
4642 pc->pc_map[1] = PC_FREE1;
4643 pc->pc_map[2] = PC_FREE2;
4644 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
4645 mtx_lock(&pvc->pvc_lock);
4646 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4647 mtx_unlock(&pvc->pvc_lock);
4648 pv = &pc->pc_pventry[0];
4649 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4650 PV_STAT(atomic_add_long(&pv_entry_count, 1));
4651 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
4656 * Returns the number of one bits within the given PV chunk map.
4658 * The erratas for Intel processors state that "POPCNT Instruction May
4659 * Take Longer to Execute Than Expected". It is believed that the
4660 * issue is the spurious dependency on the destination register.
4661 * Provide a hint to the register rename logic that the destination
4662 * value is overwritten, by clearing it, as suggested in the
4663 * optimization manual. It should be cheap for unaffected processors
4666 * Reference numbers for erratas are
4667 * 4th Gen Core: HSD146
4668 * 5th Gen Core: BDM85
4669 * 6th Gen Core: SKL029
4672 popcnt_pc_map_pq(uint64_t *map)
4676 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
4677 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
4678 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
4679 : "=&r" (result), "=&r" (tmp)
4680 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
4685 * Ensure that the number of spare PV entries in the specified pmap meets or
4686 * exceeds the given count, "needed".
4688 * The given PV list lock may be released.
4691 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
4693 struct pv_chunks_list *pvc;
4694 struct pch new_tail[PMAP_MEMDOM];
4695 struct pv_chunk *pc;
4700 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4701 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
4704 * Newly allocated PV chunks must be stored in a private list until
4705 * the required number of PV chunks have been allocated. Otherwise,
4706 * reclaim_pv_chunk() could recycle one of these chunks. In
4707 * contrast, these chunks must be added to the pmap upon allocation.
4709 for (i = 0; i < PMAP_MEMDOM; i++)
4710 TAILQ_INIT(&new_tail[i]);
4713 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
4715 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
4716 bit_count((bitstr_t *)pc->pc_map, 0,
4717 sizeof(pc->pc_map) * NBBY, &free);
4720 free = popcnt_pc_map_pq(pc->pc_map);
4724 if (avail >= needed)
4727 for (reclaimed = false; avail < needed; avail += _NPCPV) {
4728 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4731 m = reclaim_pv_chunk(pmap, lockp);
4736 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
4737 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
4738 dump_add_page(m->phys_addr);
4739 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
4741 pc->pc_map[0] = PC_FREE0;
4742 pc->pc_map[1] = PC_FREE1;
4743 pc->pc_map[2] = PC_FREE2;
4744 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4745 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
4746 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
4749 * The reclaim might have freed a chunk from the current pmap.
4750 * If that chunk contained available entries, we need to
4751 * re-count the number of available entries.
4756 for (i = 0; i < vm_ndomains; i++) {
4757 if (TAILQ_EMPTY(&new_tail[i]))
4759 pvc = &pv_chunks[i];
4760 mtx_lock(&pvc->pvc_lock);
4761 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
4762 mtx_unlock(&pvc->pvc_lock);
4767 * First find and then remove the pv entry for the specified pmap and virtual
4768 * address from the specified pv list. Returns the pv entry if found and NULL
4769 * otherwise. This operation can be performed on pv lists for either 4KB or
4770 * 2MB page mappings.
4772 static __inline pv_entry_t
4773 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4777 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4778 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
4779 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4788 * After demotion from a 2MB page mapping to 512 4KB page mappings,
4789 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
4790 * entries for each of the 4KB page mappings.
4793 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4794 struct rwlock **lockp)
4796 struct md_page *pvh;
4797 struct pv_chunk *pc;
4799 vm_offset_t va_last;
4803 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4804 KASSERT((pa & PDRMASK) == 0,
4805 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
4806 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4809 * Transfer the 2mpage's pv entry for this mapping to the first
4810 * page's pv list. Once this transfer begins, the pv list lock
4811 * must not be released until the last pv entry is reinstantiated.
4813 pvh = pa_to_pvh(pa);
4814 va = trunc_2mpage(va);
4815 pv = pmap_pvh_remove(pvh, pmap, va);
4816 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
4817 m = PHYS_TO_VM_PAGE(pa);
4818 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4820 /* Instantiate the remaining NPTEPG - 1 pv entries. */
4821 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
4822 va_last = va + NBPDR - PAGE_SIZE;
4824 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
4825 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
4826 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
4827 for (field = 0; field < _NPCM; field++) {
4828 while (pc->pc_map[field]) {
4829 bit = bsfq(pc->pc_map[field]);
4830 pc->pc_map[field] &= ~(1ul << bit);
4831 pv = &pc->pc_pventry[field * 64 + bit];
4835 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4836 ("pmap_pv_demote_pde: page %p is not managed", m));
4837 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4843 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4844 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4847 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
4848 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4849 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
4851 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
4852 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
4855 #if VM_NRESERVLEVEL > 0
4857 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
4858 * replace the many pv entries for the 4KB page mappings by a single pv entry
4859 * for the 2MB page mapping.
4862 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
4863 struct rwlock **lockp)
4865 struct md_page *pvh;
4867 vm_offset_t va_last;
4870 KASSERT((pa & PDRMASK) == 0,
4871 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
4872 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4875 * Transfer the first page's pv entry for this mapping to the 2mpage's
4876 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
4877 * a transfer avoids the possibility that get_pv_entry() calls
4878 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
4879 * mappings that is being promoted.
4881 m = PHYS_TO_VM_PAGE(pa);
4882 va = trunc_2mpage(va);
4883 pv = pmap_pvh_remove(&m->md, pmap, va);
4884 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
4885 pvh = pa_to_pvh(pa);
4886 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4888 /* Free the remaining NPTEPG - 1 pv entries. */
4889 va_last = va + NBPDR - PAGE_SIZE;
4893 pmap_pvh_free(&m->md, pmap, va);
4894 } while (va < va_last);
4896 #endif /* VM_NRESERVLEVEL > 0 */
4899 * First find and then destroy the pv entry for the specified pmap and virtual
4900 * address. This operation can be performed on pv lists for either 4KB or 2MB
4904 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
4908 pv = pmap_pvh_remove(pvh, pmap, va);
4909 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
4910 free_pv_entry(pmap, pv);
4914 * Conditionally create the PV entry for a 4KB page mapping if the required
4915 * memory can be allocated without resorting to reclamation.
4918 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
4919 struct rwlock **lockp)
4923 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4924 /* Pass NULL instead of the lock pointer to disable reclamation. */
4925 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
4927 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4928 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4936 * Create the PV entry for a 2MB page mapping. Always returns true unless the
4937 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
4938 * false if the PV entry cannot be allocated without resorting to reclamation.
4941 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
4942 struct rwlock **lockp)
4944 struct md_page *pvh;
4948 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4949 /* Pass NULL instead of the lock pointer to disable reclamation. */
4950 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
4951 NULL : lockp)) == NULL)
4954 pa = pde & PG_PS_FRAME;
4955 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
4956 pvh = pa_to_pvh(pa);
4957 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4963 * Fills a page table page with mappings to consecutive physical pages.
4966 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
4970 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
4972 newpte += PAGE_SIZE;
4977 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
4978 * mapping is invalidated.
4981 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
4983 struct rwlock *lock;
4987 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
4994 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
4998 pt_entry_t *xpte, *ypte;
5000 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5001 xpte++, newpte += PAGE_SIZE) {
5002 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5003 printf("pmap_demote_pde: xpte %zd and newpte map "
5004 "different pages: found %#lx, expected %#lx\n",
5005 xpte - firstpte, *xpte, newpte);
5006 printf("page table dump\n");
5007 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5008 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5013 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5014 ("pmap_demote_pde: firstpte and newpte map different physical"
5021 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5022 pd_entry_t oldpde, struct rwlock **lockp)
5024 struct spglist free;
5028 sva = trunc_2mpage(va);
5029 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5030 if ((oldpde & pmap_global_bit(pmap)) == 0)
5031 pmap_invalidate_pde_page(pmap, sva, oldpde);
5032 vm_page_free_pages_toq(&free, true);
5033 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5038 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5039 struct rwlock **lockp)
5041 pd_entry_t newpde, oldpde;
5042 pt_entry_t *firstpte, newpte;
5043 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5049 PG_A = pmap_accessed_bit(pmap);
5050 PG_G = pmap_global_bit(pmap);
5051 PG_M = pmap_modified_bit(pmap);
5052 PG_RW = pmap_rw_bit(pmap);
5053 PG_V = pmap_valid_bit(pmap);
5054 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5055 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5057 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5058 in_kernel = va >= VM_MAXUSER_ADDRESS;
5060 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5061 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5064 * Invalidate the 2MB page mapping and return "failure" if the
5065 * mapping was never accessed.
5067 if ((oldpde & PG_A) == 0) {
5068 KASSERT((oldpde & PG_W) == 0,
5069 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5070 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5074 mpte = pmap_remove_pt_page(pmap, va);
5076 KASSERT((oldpde & PG_W) == 0,
5077 ("pmap_demote_pde: page table page for a wired mapping"
5081 * If the page table page is missing and the mapping
5082 * is for a kernel address, the mapping must belong to
5083 * the direct map. Page table pages are preallocated
5084 * for every other part of the kernel address space,
5085 * so the direct map region is the only part of the
5086 * kernel address space that must be handled here.
5088 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5089 va < DMAP_MAX_ADDRESS),
5090 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5093 * If the 2MB page mapping belongs to the direct map
5094 * region of the kernel's address space, then the page
5095 * allocation request specifies the highest possible
5096 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5097 * priority is normal.
5099 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5100 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5101 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5104 * If the allocation of the new page table page fails,
5105 * invalidate the 2MB page mapping and return "failure".
5108 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5113 mpte->ref_count = NPTEPG;
5114 pmap_resident_count_inc(pmap, 1);
5117 mptepa = VM_PAGE_TO_PHYS(mpte);
5118 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5119 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5120 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5121 ("pmap_demote_pde: oldpde is missing PG_M"));
5122 newpte = oldpde & ~PG_PS;
5123 newpte = pmap_swap_pat(pmap, newpte);
5126 * If the page table page is not leftover from an earlier promotion,
5129 if (mpte->valid == 0)
5130 pmap_fill_ptp(firstpte, newpte);
5132 pmap_demote_pde_check(firstpte, newpte);
5135 * If the mapping has changed attributes, update the page table
5138 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5139 pmap_fill_ptp(firstpte, newpte);
5142 * The spare PV entries must be reserved prior to demoting the
5143 * mapping, that is, prior to changing the PDE. Otherwise, the state
5144 * of the PDE and the PV lists will be inconsistent, which can result
5145 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5146 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5147 * PV entry for the 2MB page mapping that is being demoted.
5149 if ((oldpde & PG_MANAGED) != 0)
5150 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5153 * Demote the mapping. This pmap is locked. The old PDE has
5154 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5155 * set. Thus, there is no danger of a race with another
5156 * processor changing the setting of PG_A and/or PG_M between
5157 * the read above and the store below.
5159 if (workaround_erratum383)
5160 pmap_update_pde(pmap, va, pde, newpde);
5162 pde_store(pde, newpde);
5165 * Invalidate a stale recursive mapping of the page table page.
5168 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5171 * Demote the PV entry.
5173 if ((oldpde & PG_MANAGED) != 0)
5174 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5176 atomic_add_long(&pmap_pde_demotions, 1);
5177 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5183 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5186 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5192 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5193 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5194 mpte = pmap_remove_pt_page(pmap, va);
5196 panic("pmap_remove_kernel_pde: Missing pt page.");
5198 mptepa = VM_PAGE_TO_PHYS(mpte);
5199 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5202 * If this page table page was unmapped by a promotion, then it
5203 * contains valid mappings. Zero it to invalidate those mappings.
5205 if (mpte->valid != 0)
5206 pagezero((void *)PHYS_TO_DMAP(mptepa));
5209 * Demote the mapping.
5211 if (workaround_erratum383)
5212 pmap_update_pde(pmap, va, pde, newpde);
5214 pde_store(pde, newpde);
5217 * Invalidate a stale recursive mapping of the page table page.
5219 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5223 * pmap_remove_pde: do the things to unmap a superpage in a process
5226 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5227 struct spglist *free, struct rwlock **lockp)
5229 struct md_page *pvh;
5231 vm_offset_t eva, va;
5233 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5235 PG_G = pmap_global_bit(pmap);
5236 PG_A = pmap_accessed_bit(pmap);
5237 PG_M = pmap_modified_bit(pmap);
5238 PG_RW = pmap_rw_bit(pmap);
5240 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5241 KASSERT((sva & PDRMASK) == 0,
5242 ("pmap_remove_pde: sva is not 2mpage aligned"));
5243 oldpde = pte_load_clear(pdq);
5245 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5246 if ((oldpde & PG_G) != 0)
5247 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5248 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5249 if (oldpde & PG_MANAGED) {
5250 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5251 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5252 pmap_pvh_free(pvh, pmap, sva);
5254 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5255 va < eva; va += PAGE_SIZE, m++) {
5256 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5259 vm_page_aflag_set(m, PGA_REFERENCED);
5260 if (TAILQ_EMPTY(&m->md.pv_list) &&
5261 TAILQ_EMPTY(&pvh->pv_list))
5262 vm_page_aflag_clear(m, PGA_WRITEABLE);
5263 pmap_delayed_invl_page(m);
5266 if (pmap == kernel_pmap) {
5267 pmap_remove_kernel_pde(pmap, pdq, sva);
5269 mpte = pmap_remove_pt_page(pmap, sva);
5271 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5272 ("pmap_remove_pde: pte page not promoted"));
5273 pmap_resident_count_dec(pmap, 1);
5274 KASSERT(mpte->ref_count == NPTEPG,
5275 ("pmap_remove_pde: pte page ref count error"));
5276 mpte->ref_count = 0;
5277 pmap_add_delayed_free_list(mpte, free, FALSE);
5280 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5284 * pmap_remove_pte: do the things to unmap a page in a process
5287 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5288 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5290 struct md_page *pvh;
5291 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5294 PG_A = pmap_accessed_bit(pmap);
5295 PG_M = pmap_modified_bit(pmap);
5296 PG_RW = pmap_rw_bit(pmap);
5298 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5299 oldpte = pte_load_clear(ptq);
5301 pmap->pm_stats.wired_count -= 1;
5302 pmap_resident_count_dec(pmap, 1);
5303 if (oldpte & PG_MANAGED) {
5304 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5305 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5308 vm_page_aflag_set(m, PGA_REFERENCED);
5309 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5310 pmap_pvh_free(&m->md, pmap, va);
5311 if (TAILQ_EMPTY(&m->md.pv_list) &&
5312 (m->flags & PG_FICTITIOUS) == 0) {
5313 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5314 if (TAILQ_EMPTY(&pvh->pv_list))
5315 vm_page_aflag_clear(m, PGA_WRITEABLE);
5317 pmap_delayed_invl_page(m);
5319 return (pmap_unuse_pt(pmap, va, ptepde, free));
5323 * Remove a single page from a process address space
5326 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5327 struct spglist *free)
5329 struct rwlock *lock;
5330 pt_entry_t *pte, PG_V;
5332 PG_V = pmap_valid_bit(pmap);
5333 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5334 if ((*pde & PG_V) == 0)
5336 pte = pmap_pde_to_pte(pde, va);
5337 if ((*pte & PG_V) == 0)
5340 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5343 pmap_invalidate_page(pmap, va);
5347 * Removes the specified range of addresses from the page table page.
5350 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5351 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5353 pt_entry_t PG_G, *pte;
5357 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5358 PG_G = pmap_global_bit(pmap);
5361 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5365 pmap_invalidate_range(pmap, va, sva);
5370 if ((*pte & PG_G) == 0)
5374 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5380 pmap_invalidate_range(pmap, va, sva);
5385 * Remove the given range of addresses from the specified map.
5387 * It is assumed that the start and end are properly
5388 * rounded to the page size.
5391 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5393 struct rwlock *lock;
5394 vm_offset_t va_next;
5395 pml4_entry_t *pml4e;
5397 pd_entry_t ptpaddr, *pde;
5398 pt_entry_t PG_G, PG_V;
5399 struct spglist free;
5402 PG_G = pmap_global_bit(pmap);
5403 PG_V = pmap_valid_bit(pmap);
5406 * Perform an unsynchronized read. This is, however, safe.
5408 if (pmap->pm_stats.resident_count == 0)
5414 pmap_delayed_invl_start();
5416 pmap_pkru_on_remove(pmap, sva, eva);
5419 * special handling of removing one page. a very
5420 * common operation and easy to short circuit some
5423 if (sva + PAGE_SIZE == eva) {
5424 pde = pmap_pde(pmap, sva);
5425 if (pde && (*pde & PG_PS) == 0) {
5426 pmap_remove_page(pmap, sva, pde, &free);
5432 for (; sva < eva; sva = va_next) {
5434 if (pmap->pm_stats.resident_count == 0)
5437 pml4e = pmap_pml4e(pmap, sva);
5438 if ((*pml4e & PG_V) == 0) {
5439 va_next = (sva + NBPML4) & ~PML4MASK;
5445 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5446 if ((*pdpe & PG_V) == 0) {
5447 va_next = (sva + NBPDP) & ~PDPMASK;
5454 * Calculate index for next page table.
5456 va_next = (sva + NBPDR) & ~PDRMASK;
5460 pde = pmap_pdpe_to_pde(pdpe, sva);
5464 * Weed out invalid mappings.
5470 * Check for large page.
5472 if ((ptpaddr & PG_PS) != 0) {
5474 * Are we removing the entire large page? If not,
5475 * demote the mapping and fall through.
5477 if (sva + NBPDR == va_next && eva >= va_next) {
5479 * The TLB entry for a PG_G mapping is
5480 * invalidated by pmap_remove_pde().
5482 if ((ptpaddr & PG_G) == 0)
5484 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5486 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5488 /* The large page mapping was destroyed. */
5495 * Limit our scan to either the end of the va represented
5496 * by the current page table page, or to the end of the
5497 * range being removed.
5502 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5509 pmap_invalidate_all(pmap);
5511 pmap_delayed_invl_finish();
5512 vm_page_free_pages_toq(&free, true);
5516 * Routine: pmap_remove_all
5518 * Removes this physical page from
5519 * all physical maps in which it resides.
5520 * Reflects back modify bits to the pager.
5523 * Original versions of this routine were very
5524 * inefficient because they iteratively called
5525 * pmap_remove (slow...)
5529 pmap_remove_all(vm_page_t m)
5531 struct md_page *pvh;
5534 struct rwlock *lock;
5535 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5538 struct spglist free;
5539 int pvh_gen, md_gen;
5541 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5542 ("pmap_remove_all: page %p is not managed", m));
5544 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5545 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5546 pa_to_pvh(VM_PAGE_TO_PHYS(m));
5549 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
5551 if (!PMAP_TRYLOCK(pmap)) {
5552 pvh_gen = pvh->pv_gen;
5556 if (pvh_gen != pvh->pv_gen) {
5563 pde = pmap_pde(pmap, va);
5564 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
5567 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
5569 if (!PMAP_TRYLOCK(pmap)) {
5570 pvh_gen = pvh->pv_gen;
5571 md_gen = m->md.pv_gen;
5575 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
5581 PG_A = pmap_accessed_bit(pmap);
5582 PG_M = pmap_modified_bit(pmap);
5583 PG_RW = pmap_rw_bit(pmap);
5584 pmap_resident_count_dec(pmap, 1);
5585 pde = pmap_pde(pmap, pv->pv_va);
5586 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
5587 " a 2mpage in page %p's pv list", m));
5588 pte = pmap_pde_to_pte(pde, pv->pv_va);
5589 tpte = pte_load_clear(pte);
5591 pmap->pm_stats.wired_count--;
5593 vm_page_aflag_set(m, PGA_REFERENCED);
5596 * Update the vm_page_t clean and reference bits.
5598 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5600 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
5601 pmap_invalidate_page(pmap, pv->pv_va);
5602 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5604 free_pv_entry(pmap, pv);
5607 vm_page_aflag_clear(m, PGA_WRITEABLE);
5609 pmap_delayed_invl_wait(m);
5610 vm_page_free_pages_toq(&free, true);
5614 * pmap_protect_pde: do the things to protect a 2mpage in a process
5617 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
5619 pd_entry_t newpde, oldpde;
5621 boolean_t anychanged;
5622 pt_entry_t PG_G, PG_M, PG_RW;
5624 PG_G = pmap_global_bit(pmap);
5625 PG_M = pmap_modified_bit(pmap);
5626 PG_RW = pmap_rw_bit(pmap);
5628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5629 KASSERT((sva & PDRMASK) == 0,
5630 ("pmap_protect_pde: sva is not 2mpage aligned"));
5633 oldpde = newpde = *pde;
5634 if ((prot & VM_PROT_WRITE) == 0) {
5635 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
5636 (PG_MANAGED | PG_M | PG_RW)) {
5637 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5638 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
5641 newpde &= ~(PG_RW | PG_M);
5643 if ((prot & VM_PROT_EXECUTE) == 0)
5645 if (newpde != oldpde) {
5647 * As an optimization to future operations on this PDE, clear
5648 * PG_PROMOTED. The impending invalidation will remove any
5649 * lingering 4KB page mappings from the TLB.
5651 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
5653 if ((oldpde & PG_G) != 0)
5654 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5658 return (anychanged);
5662 * Set the physical protection on the
5663 * specified range of this map as requested.
5666 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
5668 vm_offset_t va_next;
5669 pml4_entry_t *pml4e;
5671 pd_entry_t ptpaddr, *pde;
5672 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
5673 boolean_t anychanged;
5675 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
5676 if (prot == VM_PROT_NONE) {
5677 pmap_remove(pmap, sva, eva);
5681 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
5682 (VM_PROT_WRITE|VM_PROT_EXECUTE))
5685 PG_G = pmap_global_bit(pmap);
5686 PG_M = pmap_modified_bit(pmap);
5687 PG_V = pmap_valid_bit(pmap);
5688 PG_RW = pmap_rw_bit(pmap);
5692 * Although this function delays and batches the invalidation
5693 * of stale TLB entries, it does not need to call
5694 * pmap_delayed_invl_start() and
5695 * pmap_delayed_invl_finish(), because it does not
5696 * ordinarily destroy mappings. Stale TLB entries from
5697 * protection-only changes need only be invalidated before the
5698 * pmap lock is released, because protection-only changes do
5699 * not destroy PV entries. Even operations that iterate over
5700 * a physical page's PV list of mappings, like
5701 * pmap_remove_write(), acquire the pmap lock for each
5702 * mapping. Consequently, for protection-only changes, the
5703 * pmap lock suffices to synchronize both page table and TLB
5706 * This function only destroys a mapping if pmap_demote_pde()
5707 * fails. In that case, stale TLB entries are immediately
5712 for (; sva < eva; sva = va_next) {
5714 pml4e = pmap_pml4e(pmap, sva);
5715 if ((*pml4e & PG_V) == 0) {
5716 va_next = (sva + NBPML4) & ~PML4MASK;
5722 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5723 if ((*pdpe & PG_V) == 0) {
5724 va_next = (sva + NBPDP) & ~PDPMASK;
5730 va_next = (sva + NBPDR) & ~PDRMASK;
5734 pde = pmap_pdpe_to_pde(pdpe, sva);
5738 * Weed out invalid mappings.
5744 * Check for large page.
5746 if ((ptpaddr & PG_PS) != 0) {
5748 * Are we protecting the entire large page? If not,
5749 * demote the mapping and fall through.
5751 if (sva + NBPDR == va_next && eva >= va_next) {
5753 * The TLB entry for a PG_G mapping is
5754 * invalidated by pmap_protect_pde().
5756 if (pmap_protect_pde(pmap, pde, sva, prot))
5759 } else if (!pmap_demote_pde(pmap, pde, sva)) {
5761 * The large page mapping was destroyed.
5770 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
5772 pt_entry_t obits, pbits;
5776 obits = pbits = *pte;
5777 if ((pbits & PG_V) == 0)
5780 if ((prot & VM_PROT_WRITE) == 0) {
5781 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
5782 (PG_MANAGED | PG_M | PG_RW)) {
5783 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
5786 pbits &= ~(PG_RW | PG_M);
5788 if ((prot & VM_PROT_EXECUTE) == 0)
5791 if (pbits != obits) {
5792 if (!atomic_cmpset_long(pte, obits, pbits))
5795 pmap_invalidate_page(pmap, sva);
5802 pmap_invalidate_all(pmap);
5806 #if VM_NRESERVLEVEL > 0
5808 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
5811 if (pmap->pm_type != PT_EPT)
5813 return ((pde & EPT_PG_EXECUTE) != 0);
5817 * Tries to promote the 512, contiguous 4KB page mappings that are within a
5818 * single page table page (PTP) to a single 2MB page mapping. For promotion
5819 * to occur, two conditions must be met: (1) the 4KB page mappings must map
5820 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
5821 * identical characteristics.
5824 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5825 struct rwlock **lockp)
5828 pt_entry_t *firstpte, oldpte, pa, *pte;
5829 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
5833 PG_A = pmap_accessed_bit(pmap);
5834 PG_G = pmap_global_bit(pmap);
5835 PG_M = pmap_modified_bit(pmap);
5836 PG_V = pmap_valid_bit(pmap);
5837 PG_RW = pmap_rw_bit(pmap);
5838 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5839 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5841 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5844 * Examine the first PTE in the specified PTP. Abort if this PTE is
5845 * either invalid, unused, or does not map the first 4KB physical page
5846 * within a 2MB page.
5848 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
5851 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
5852 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
5854 atomic_add_long(&pmap_pde_p_failures, 1);
5855 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5856 " in pmap %p", va, pmap);
5859 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
5861 * When PG_M is already clear, PG_RW can be cleared without
5862 * a TLB invalidation.
5864 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
5870 * Examine each of the other PTEs in the specified PTP. Abort if this
5871 * PTE maps an unexpected 4KB physical page or does not have identical
5872 * characteristics to the first PTE.
5874 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
5875 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
5878 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
5879 atomic_add_long(&pmap_pde_p_failures, 1);
5880 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5881 " in pmap %p", va, pmap);
5884 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
5886 * When PG_M is already clear, PG_RW can be cleared
5887 * without a TLB invalidation.
5889 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
5892 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
5893 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
5894 (va & ~PDRMASK), pmap);
5896 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
5897 atomic_add_long(&pmap_pde_p_failures, 1);
5898 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
5899 " in pmap %p", va, pmap);
5906 * Save the page table page in its current state until the PDE
5907 * mapping the superpage is demoted by pmap_demote_pde() or
5908 * destroyed by pmap_remove_pde().
5910 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
5911 KASSERT(mpte >= vm_page_array &&
5912 mpte < &vm_page_array[vm_page_array_size],
5913 ("pmap_promote_pde: page table page is out of range"));
5914 KASSERT(mpte->pindex == pmap_pde_pindex(va),
5915 ("pmap_promote_pde: page table page's pindex is wrong"));
5916 if (pmap_insert_pt_page(pmap, mpte, true)) {
5917 atomic_add_long(&pmap_pde_p_failures, 1);
5919 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
5925 * Promote the pv entries.
5927 if ((newpde & PG_MANAGED) != 0)
5928 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
5931 * Propagate the PAT index to its proper position.
5933 newpde = pmap_swap_pat(pmap, newpde);
5936 * Map the superpage.
5938 if (workaround_erratum383)
5939 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
5941 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
5943 atomic_add_long(&pmap_pde_promotions, 1);
5944 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
5945 " in pmap %p", va, pmap);
5947 #endif /* VM_NRESERVLEVEL > 0 */
5950 * Insert the given physical page (p) at
5951 * the specified virtual address (v) in the
5952 * target physical map with the protection requested.
5954 * If specified, the page will be wired down, meaning
5955 * that the related pte can not be reclaimed.
5957 * NB: This is the only routine which MAY NOT lazy-evaluate
5958 * or lose information. That is, this routine must actually
5959 * insert this page into the given map NOW.
5961 * When destroying both a page table and PV entry, this function
5962 * performs the TLB invalidation before releasing the PV list
5963 * lock, so we do not need pmap_delayed_invl_page() calls here.
5966 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
5967 u_int flags, int8_t psind)
5969 struct rwlock *lock;
5971 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
5972 pt_entry_t newpte, origpte;
5979 PG_A = pmap_accessed_bit(pmap);
5980 PG_G = pmap_global_bit(pmap);
5981 PG_M = pmap_modified_bit(pmap);
5982 PG_V = pmap_valid_bit(pmap);
5983 PG_RW = pmap_rw_bit(pmap);
5985 va = trunc_page(va);
5986 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
5987 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
5988 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
5990 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
5991 va >= kmi.clean_eva,
5992 ("pmap_enter: managed mapping within the clean submap"));
5993 if ((m->oflags & VPO_UNMANAGED) == 0)
5994 VM_PAGE_OBJECT_BUSY_ASSERT(m);
5995 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
5996 ("pmap_enter: flags %u has reserved bits set", flags));
5997 pa = VM_PAGE_TO_PHYS(m);
5998 newpte = (pt_entry_t)(pa | PG_A | PG_V);
5999 if ((flags & VM_PROT_WRITE) != 0)
6001 if ((prot & VM_PROT_WRITE) != 0)
6003 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6004 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6005 if ((prot & VM_PROT_EXECUTE) == 0)
6007 if ((flags & PMAP_ENTER_WIRED) != 0)
6009 if (va < VM_MAXUSER_ADDRESS)
6011 if (pmap == kernel_pmap)
6013 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6016 * Set modified bit gratuitously for writeable mappings if
6017 * the page is unmanaged. We do not want to take a fault
6018 * to do the dirty bit accounting for these mappings.
6020 if ((m->oflags & VPO_UNMANAGED) != 0) {
6021 if ((newpte & PG_RW) != 0)
6024 newpte |= PG_MANAGED;
6029 /* Assert the required virtual and physical alignment. */
6030 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6031 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6032 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6038 * In the case that a page table page is not
6039 * resident, we are creating it here.
6042 pde = pmap_pde(pmap, va);
6043 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6044 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6045 pte = pmap_pde_to_pte(pde, va);
6046 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6047 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6050 } else if (va < VM_MAXUSER_ADDRESS) {
6052 * Here if the pte page isn't mapped, or if it has been
6055 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6056 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6057 nosleep ? NULL : &lock);
6058 if (mpte == NULL && nosleep) {
6059 rv = KERN_RESOURCE_SHORTAGE;
6064 panic("pmap_enter: invalid page directory va=%#lx", va);
6068 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6069 newpte |= pmap_pkru_get(pmap, va);
6072 * Is the specified virtual address already mapped?
6074 if ((origpte & PG_V) != 0) {
6076 * Wiring change, just update stats. We don't worry about
6077 * wiring PT pages as they remain resident as long as there
6078 * are valid mappings in them. Hence, if a user page is wired,
6079 * the PT page will be also.
6081 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6082 pmap->pm_stats.wired_count++;
6083 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6084 pmap->pm_stats.wired_count--;
6087 * Remove the extra PT page reference.
6091 KASSERT(mpte->ref_count > 0,
6092 ("pmap_enter: missing reference to page table page,"
6097 * Has the physical page changed?
6099 opa = origpte & PG_FRAME;
6102 * No, might be a protection or wiring change.
6104 if ((origpte & PG_MANAGED) != 0 &&
6105 (newpte & PG_RW) != 0)
6106 vm_page_aflag_set(m, PGA_WRITEABLE);
6107 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6113 * The physical page has changed. Temporarily invalidate
6114 * the mapping. This ensures that all threads sharing the
6115 * pmap keep a consistent view of the mapping, which is
6116 * necessary for the correct handling of COW faults. It
6117 * also permits reuse of the old mapping's PV entry,
6118 * avoiding an allocation.
6120 * For consistency, handle unmanaged mappings the same way.
6122 origpte = pte_load_clear(pte);
6123 KASSERT((origpte & PG_FRAME) == opa,
6124 ("pmap_enter: unexpected pa update for %#lx", va));
6125 if ((origpte & PG_MANAGED) != 0) {
6126 om = PHYS_TO_VM_PAGE(opa);
6129 * The pmap lock is sufficient to synchronize with
6130 * concurrent calls to pmap_page_test_mappings() and
6131 * pmap_ts_referenced().
6133 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6135 if ((origpte & PG_A) != 0) {
6136 pmap_invalidate_page(pmap, va);
6137 vm_page_aflag_set(om, PGA_REFERENCED);
6139 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6140 pv = pmap_pvh_remove(&om->md, pmap, va);
6142 ("pmap_enter: no PV entry for %#lx", va));
6143 if ((newpte & PG_MANAGED) == 0)
6144 free_pv_entry(pmap, pv);
6145 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6146 TAILQ_EMPTY(&om->md.pv_list) &&
6147 ((om->flags & PG_FICTITIOUS) != 0 ||
6148 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6149 vm_page_aflag_clear(om, PGA_WRITEABLE);
6152 * Since this mapping is unmanaged, assume that PG_A
6155 pmap_invalidate_page(pmap, va);
6160 * Increment the counters.
6162 if ((newpte & PG_W) != 0)
6163 pmap->pm_stats.wired_count++;
6164 pmap_resident_count_inc(pmap, 1);
6168 * Enter on the PV list if part of our managed memory.
6170 if ((newpte & PG_MANAGED) != 0) {
6172 pv = get_pv_entry(pmap, &lock);
6175 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6176 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6178 if ((newpte & PG_RW) != 0)
6179 vm_page_aflag_set(m, PGA_WRITEABLE);
6185 if ((origpte & PG_V) != 0) {
6187 origpte = pte_load_store(pte, newpte);
6188 KASSERT((origpte & PG_FRAME) == pa,
6189 ("pmap_enter: unexpected pa update for %#lx", va));
6190 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6192 if ((origpte & PG_MANAGED) != 0)
6196 * Although the PTE may still have PG_RW set, TLB
6197 * invalidation may nonetheless be required because
6198 * the PTE no longer has PG_M set.
6200 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6202 * This PTE change does not require TLB invalidation.
6206 if ((origpte & PG_A) != 0)
6207 pmap_invalidate_page(pmap, va);
6209 pte_store(pte, newpte);
6213 #if VM_NRESERVLEVEL > 0
6215 * If both the page table page and the reservation are fully
6216 * populated, then attempt promotion.
6218 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6219 pmap_ps_enabled(pmap) &&
6220 (m->flags & PG_FICTITIOUS) == 0 &&
6221 vm_reserv_level_iffullpop(m) == 0)
6222 pmap_promote_pde(pmap, pde, va, &lock);
6234 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6235 * if successful. Returns false if (1) a page table page cannot be allocated
6236 * without sleeping, (2) a mapping already exists at the specified virtual
6237 * address, or (3) a PV entry cannot be allocated without reclaiming another
6241 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6242 struct rwlock **lockp)
6247 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6248 PG_V = pmap_valid_bit(pmap);
6249 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6251 if ((m->oflags & VPO_UNMANAGED) == 0)
6252 newpde |= PG_MANAGED;
6253 if ((prot & VM_PROT_EXECUTE) == 0)
6255 if (va < VM_MAXUSER_ADDRESS)
6257 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6258 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6263 * Returns true if every page table entry in the specified page table page is
6267 pmap_every_pte_zero(vm_paddr_t pa)
6269 pt_entry_t *pt_end, *pte;
6271 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6272 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6273 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6281 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6282 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6283 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6284 * a mapping already exists at the specified virtual address. Returns
6285 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6286 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6287 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6289 * The parameter "m" is only used when creating a managed, writeable mapping.
6292 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6293 vm_page_t m, struct rwlock **lockp)
6295 struct spglist free;
6296 pd_entry_t oldpde, *pde;
6297 pt_entry_t PG_G, PG_RW, PG_V;
6300 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6301 ("pmap_enter_pde: cannot create wired user mapping"));
6302 PG_G = pmap_global_bit(pmap);
6303 PG_RW = pmap_rw_bit(pmap);
6304 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6305 ("pmap_enter_pde: newpde is missing PG_M"));
6306 PG_V = pmap_valid_bit(pmap);
6307 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6309 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6311 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6312 " in pmap %p", va, pmap);
6313 return (KERN_FAILURE);
6315 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6316 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6317 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6318 " in pmap %p", va, pmap);
6319 return (KERN_RESOURCE_SHORTAGE);
6323 * If pkru is not same for the whole pde range, return failure
6324 * and let vm_fault() cope. Check after pde allocation, since
6327 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6328 pmap_abort_ptp(pmap, va, pdpg);
6329 return (KERN_FAILURE);
6331 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6332 newpde &= ~X86_PG_PKU_MASK;
6333 newpde |= pmap_pkru_get(pmap, va);
6337 * If there are existing mappings, either abort or remove them.
6340 if ((oldpde & PG_V) != 0) {
6341 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6342 ("pmap_enter_pde: pdpg's reference count is too low"));
6343 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6344 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6345 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6348 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6349 " in pmap %p", va, pmap);
6350 return (KERN_FAILURE);
6352 /* Break the existing mapping(s). */
6354 if ((oldpde & PG_PS) != 0) {
6356 * The reference to the PD page that was acquired by
6357 * pmap_alloc_pde() ensures that it won't be freed.
6358 * However, if the PDE resulted from a promotion, then
6359 * a reserved PT page could be freed.
6361 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6362 if ((oldpde & PG_G) == 0)
6363 pmap_invalidate_pde_page(pmap, va, oldpde);
6365 pmap_delayed_invl_start();
6366 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6368 pmap_invalidate_all(pmap);
6369 pmap_delayed_invl_finish();
6371 if (va < VM_MAXUSER_ADDRESS) {
6372 vm_page_free_pages_toq(&free, true);
6373 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6376 KASSERT(SLIST_EMPTY(&free),
6377 ("pmap_enter_pde: freed kernel page table page"));
6380 * Both pmap_remove_pde() and pmap_remove_ptes() will
6381 * leave the kernel page table page zero filled.
6383 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6384 if (pmap_insert_pt_page(pmap, mt, false))
6385 panic("pmap_enter_pde: trie insert failed");
6389 if ((newpde & PG_MANAGED) != 0) {
6391 * Abort this mapping if its PV entry could not be created.
6393 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6395 pmap_abort_ptp(pmap, va, pdpg);
6396 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6397 " in pmap %p", va, pmap);
6398 return (KERN_RESOURCE_SHORTAGE);
6400 if ((newpde & PG_RW) != 0) {
6401 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6402 vm_page_aflag_set(mt, PGA_WRITEABLE);
6407 * Increment counters.
6409 if ((newpde & PG_W) != 0)
6410 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6411 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6414 * Map the superpage. (This is not a promoted mapping; there will not
6415 * be any lingering 4KB page mappings in the TLB.)
6417 pde_store(pde, newpde);
6419 atomic_add_long(&pmap_pde_mappings, 1);
6420 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
6422 return (KERN_SUCCESS);
6426 * Maps a sequence of resident pages belonging to the same object.
6427 * The sequence begins with the given page m_start. This page is
6428 * mapped at the given virtual address start. Each subsequent page is
6429 * mapped at a virtual address that is offset from start by the same
6430 * amount as the page is offset from m_start within the object. The
6431 * last page in the sequence is the page with the largest offset from
6432 * m_start that can be mapped at a virtual address less than the given
6433 * virtual address end. Not every virtual page between start and end
6434 * is mapped; only those for which a resident page exists with the
6435 * corresponding offset from m_start are mapped.
6438 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6439 vm_page_t m_start, vm_prot_t prot)
6441 struct rwlock *lock;
6444 vm_pindex_t diff, psize;
6446 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6448 psize = atop(end - start);
6453 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6454 va = start + ptoa(diff);
6455 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6456 m->psind == 1 && pmap_ps_enabled(pmap) &&
6457 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6458 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6459 m = &m[NBPDR / PAGE_SIZE - 1];
6461 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6463 m = TAILQ_NEXT(m, listq);
6471 * this code makes some *MAJOR* assumptions:
6472 * 1. Current pmap & pmap exists.
6475 * 4. No page table pages.
6476 * but is *MUCH* faster than pmap_enter...
6480 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6482 struct rwlock *lock;
6486 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6493 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6494 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6496 pt_entry_t newpte, *pte, PG_V;
6498 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6499 (m->oflags & VPO_UNMANAGED) != 0,
6500 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6501 PG_V = pmap_valid_bit(pmap);
6502 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6505 * In the case that a page table page is not
6506 * resident, we are creating it here.
6508 if (va < VM_MAXUSER_ADDRESS) {
6509 vm_pindex_t ptepindex;
6513 * Calculate pagetable page index
6515 ptepindex = pmap_pde_pindex(va);
6516 if (mpte && (mpte->pindex == ptepindex)) {
6520 * Get the page directory entry
6522 ptepa = pmap_pde(pmap, va);
6525 * If the page table page is mapped, we just increment
6526 * the hold count, and activate it. Otherwise, we
6527 * attempt to allocate a page table page. If this
6528 * attempt fails, we don't retry. Instead, we give up.
6530 if (ptepa && (*ptepa & PG_V) != 0) {
6533 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6537 * Pass NULL instead of the PV list lock
6538 * pointer, because we don't intend to sleep.
6540 mpte = _pmap_allocpte(pmap, ptepindex, NULL);
6545 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6546 pte = &pte[pmap_pte_index(va)];
6558 * Enter on the PV list if part of our managed memory.
6560 if ((m->oflags & VPO_UNMANAGED) == 0 &&
6561 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
6563 pmap_abort_ptp(pmap, va, mpte);
6568 * Increment counters
6570 pmap_resident_count_inc(pmap, 1);
6572 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
6573 pmap_cache_bits(pmap, m->md.pat_mode, 0);
6574 if ((m->oflags & VPO_UNMANAGED) == 0)
6575 newpte |= PG_MANAGED;
6576 if ((prot & VM_PROT_EXECUTE) == 0)
6578 if (va < VM_MAXUSER_ADDRESS)
6579 newpte |= PG_U | pmap_pkru_get(pmap, va);
6580 pte_store(pte, newpte);
6585 * Make a temporary mapping for a physical address. This is only intended
6586 * to be used for panic dumps.
6589 pmap_kenter_temporary(vm_paddr_t pa, int i)
6593 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
6594 pmap_kenter(va, pa);
6596 return ((void *)crashdumpmap);
6600 * This code maps large physical mmap regions into the
6601 * processor address space. Note that some shortcuts
6602 * are taken, but the code works.
6605 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
6606 vm_pindex_t pindex, vm_size_t size)
6609 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
6610 vm_paddr_t pa, ptepa;
6614 PG_A = pmap_accessed_bit(pmap);
6615 PG_M = pmap_modified_bit(pmap);
6616 PG_V = pmap_valid_bit(pmap);
6617 PG_RW = pmap_rw_bit(pmap);
6619 VM_OBJECT_ASSERT_WLOCKED(object);
6620 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
6621 ("pmap_object_init_pt: non-device object"));
6622 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
6623 if (!pmap_ps_enabled(pmap))
6625 if (!vm_object_populate(object, pindex, pindex + atop(size)))
6627 p = vm_page_lookup(object, pindex);
6628 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6629 ("pmap_object_init_pt: invalid page %p", p));
6630 pat_mode = p->md.pat_mode;
6633 * Abort the mapping if the first page is not physically
6634 * aligned to a 2MB page boundary.
6636 ptepa = VM_PAGE_TO_PHYS(p);
6637 if (ptepa & (NBPDR - 1))
6641 * Skip the first page. Abort the mapping if the rest of
6642 * the pages are not physically contiguous or have differing
6643 * memory attributes.
6645 p = TAILQ_NEXT(p, listq);
6646 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
6648 KASSERT(p->valid == VM_PAGE_BITS_ALL,
6649 ("pmap_object_init_pt: invalid page %p", p));
6650 if (pa != VM_PAGE_TO_PHYS(p) ||
6651 pat_mode != p->md.pat_mode)
6653 p = TAILQ_NEXT(p, listq);
6657 * Map using 2MB pages. Since "ptepa" is 2M aligned and
6658 * "size" is a multiple of 2M, adding the PAT setting to "pa"
6659 * will not affect the termination of this loop.
6662 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
6663 pa < ptepa + size; pa += NBPDR) {
6664 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
6667 * The creation of mappings below is only an
6668 * optimization. If a page directory page
6669 * cannot be allocated without blocking,
6670 * continue on to the next mapping rather than
6676 if ((*pde & PG_V) == 0) {
6677 pde_store(pde, pa | PG_PS | PG_M | PG_A |
6678 PG_U | PG_RW | PG_V);
6679 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6680 atomic_add_long(&pmap_pde_mappings, 1);
6682 /* Continue on if the PDE is already valid. */
6684 KASSERT(pdpg->ref_count > 0,
6685 ("pmap_object_init_pt: missing reference "
6686 "to page directory page, va: 0x%lx", addr));
6695 * Clear the wired attribute from the mappings for the specified range of
6696 * addresses in the given pmap. Every valid mapping within that range
6697 * must have the wired attribute set. In contrast, invalid mappings
6698 * cannot have the wired attribute set, so they are ignored.
6700 * The wired attribute of the page table entry is not a hardware
6701 * feature, so there is no need to invalidate any TLB entries.
6702 * Since pmap_demote_pde() for the wired entry must never fail,
6703 * pmap_delayed_invl_start()/finish() calls around the
6704 * function are not needed.
6707 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
6709 vm_offset_t va_next;
6710 pml4_entry_t *pml4e;
6713 pt_entry_t *pte, PG_V;
6715 PG_V = pmap_valid_bit(pmap);
6717 for (; sva < eva; sva = va_next) {
6718 pml4e = pmap_pml4e(pmap, sva);
6719 if ((*pml4e & PG_V) == 0) {
6720 va_next = (sva + NBPML4) & ~PML4MASK;
6725 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6726 if ((*pdpe & PG_V) == 0) {
6727 va_next = (sva + NBPDP) & ~PDPMASK;
6732 va_next = (sva + NBPDR) & ~PDRMASK;
6735 pde = pmap_pdpe_to_pde(pdpe, sva);
6736 if ((*pde & PG_V) == 0)
6738 if ((*pde & PG_PS) != 0) {
6739 if ((*pde & PG_W) == 0)
6740 panic("pmap_unwire: pde %#jx is missing PG_W",
6744 * Are we unwiring the entire large page? If not,
6745 * demote the mapping and fall through.
6747 if (sva + NBPDR == va_next && eva >= va_next) {
6748 atomic_clear_long(pde, PG_W);
6749 pmap->pm_stats.wired_count -= NBPDR /
6752 } else if (!pmap_demote_pde(pmap, pde, sva))
6753 panic("pmap_unwire: demotion failed");
6757 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6759 if ((*pte & PG_V) == 0)
6761 if ((*pte & PG_W) == 0)
6762 panic("pmap_unwire: pte %#jx is missing PG_W",
6766 * PG_W must be cleared atomically. Although the pmap
6767 * lock synchronizes access to PG_W, another processor
6768 * could be setting PG_M and/or PG_A concurrently.
6770 atomic_clear_long(pte, PG_W);
6771 pmap->pm_stats.wired_count--;
6778 * Copy the range specified by src_addr/len
6779 * from the source map to the range dst_addr/len
6780 * in the destination map.
6782 * This routine is only advisory and need not do anything.
6785 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
6786 vm_offset_t src_addr)
6788 struct rwlock *lock;
6789 pml4_entry_t *pml4e;
6791 pd_entry_t *pde, srcptepaddr;
6792 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
6793 vm_offset_t addr, end_addr, va_next;
6794 vm_page_t dst_pdpg, dstmpte, srcmpte;
6796 if (dst_addr != src_addr)
6799 if (dst_pmap->pm_type != src_pmap->pm_type)
6803 * EPT page table entries that require emulation of A/D bits are
6804 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
6805 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
6806 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
6807 * implementations flag an EPT misconfiguration for exec-only
6808 * mappings we skip this function entirely for emulated pmaps.
6810 if (pmap_emulate_ad_bits(dst_pmap))
6813 end_addr = src_addr + len;
6815 if (dst_pmap < src_pmap) {
6816 PMAP_LOCK(dst_pmap);
6817 PMAP_LOCK(src_pmap);
6819 PMAP_LOCK(src_pmap);
6820 PMAP_LOCK(dst_pmap);
6823 PG_A = pmap_accessed_bit(dst_pmap);
6824 PG_M = pmap_modified_bit(dst_pmap);
6825 PG_V = pmap_valid_bit(dst_pmap);
6827 for (addr = src_addr; addr < end_addr; addr = va_next) {
6828 KASSERT(addr < UPT_MIN_ADDRESS,
6829 ("pmap_copy: invalid to pmap_copy page tables"));
6831 pml4e = pmap_pml4e(src_pmap, addr);
6832 if ((*pml4e & PG_V) == 0) {
6833 va_next = (addr + NBPML4) & ~PML4MASK;
6839 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
6840 if ((*pdpe & PG_V) == 0) {
6841 va_next = (addr + NBPDP) & ~PDPMASK;
6847 va_next = (addr + NBPDR) & ~PDRMASK;
6851 pde = pmap_pdpe_to_pde(pdpe, addr);
6853 if (srcptepaddr == 0)
6856 if (srcptepaddr & PG_PS) {
6857 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
6859 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
6862 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
6863 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
6864 PMAP_ENTER_NORECLAIM, &lock))) {
6865 *pde = srcptepaddr & ~PG_W;
6866 pmap_resident_count_inc(dst_pmap, NBPDR /
6868 atomic_add_long(&pmap_pde_mappings, 1);
6870 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
6874 srcptepaddr &= PG_FRAME;
6875 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
6876 KASSERT(srcmpte->ref_count > 0,
6877 ("pmap_copy: source page table page is unused"));
6879 if (va_next > end_addr)
6882 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
6883 src_pte = &src_pte[pmap_pte_index(addr)];
6885 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
6889 * We only virtual copy managed pages.
6891 if ((ptetemp & PG_MANAGED) == 0)
6894 if (dstmpte != NULL) {
6895 KASSERT(dstmpte->pindex ==
6896 pmap_pde_pindex(addr),
6897 ("dstmpte pindex/addr mismatch"));
6898 dstmpte->ref_count++;
6899 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
6902 dst_pte = (pt_entry_t *)
6903 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
6904 dst_pte = &dst_pte[pmap_pte_index(addr)];
6905 if (*dst_pte == 0 &&
6906 pmap_try_insert_pv_entry(dst_pmap, addr,
6907 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
6909 * Clear the wired, modified, and accessed
6910 * (referenced) bits during the copy.
6912 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
6913 pmap_resident_count_inc(dst_pmap, 1);
6915 pmap_abort_ptp(dst_pmap, addr, dstmpte);
6918 /* Have we copied all of the valid mappings? */
6919 if (dstmpte->ref_count >= srcmpte->ref_count)
6926 PMAP_UNLOCK(src_pmap);
6927 PMAP_UNLOCK(dst_pmap);
6931 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
6935 if (dst_pmap->pm_type != src_pmap->pm_type ||
6936 dst_pmap->pm_type != PT_X86 ||
6937 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
6940 if (dst_pmap < src_pmap) {
6941 PMAP_LOCK(dst_pmap);
6942 PMAP_LOCK(src_pmap);
6944 PMAP_LOCK(src_pmap);
6945 PMAP_LOCK(dst_pmap);
6947 error = pmap_pkru_copy(dst_pmap, src_pmap);
6948 /* Clean up partial copy on failure due to no memory. */
6949 if (error == ENOMEM)
6950 pmap_pkru_deassign_all(dst_pmap);
6951 PMAP_UNLOCK(src_pmap);
6952 PMAP_UNLOCK(dst_pmap);
6953 if (error != ENOMEM)
6961 * Zero the specified hardware page.
6964 pmap_zero_page(vm_page_t m)
6966 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6968 pagezero((void *)va);
6972 * Zero an an area within a single hardware page. off and size must not
6973 * cover an area beyond a single hardware page.
6976 pmap_zero_page_area(vm_page_t m, int off, int size)
6978 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
6980 if (off == 0 && size == PAGE_SIZE)
6981 pagezero((void *)va);
6983 bzero((char *)va + off, size);
6987 * Copy 1 specified hardware page to another.
6990 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
6992 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
6993 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
6995 pagecopy((void *)src, (void *)dst);
6998 int unmapped_buf_allowed = 1;
7001 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7002 vm_offset_t b_offset, int xfersize)
7006 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7010 while (xfersize > 0) {
7011 a_pg_offset = a_offset & PAGE_MASK;
7012 pages[0] = ma[a_offset >> PAGE_SHIFT];
7013 b_pg_offset = b_offset & PAGE_MASK;
7014 pages[1] = mb[b_offset >> PAGE_SHIFT];
7015 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7016 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7017 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7018 a_cp = (char *)vaddr[0] + a_pg_offset;
7019 b_cp = (char *)vaddr[1] + b_pg_offset;
7020 bcopy(a_cp, b_cp, cnt);
7021 if (__predict_false(mapped))
7022 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7030 * Returns true if the pmap's pv is one of the first
7031 * 16 pvs linked to from this page. This count may
7032 * be changed upwards or downwards in the future; it
7033 * is only necessary that true be returned for a small
7034 * subset of pmaps for proper page aging.
7037 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7039 struct md_page *pvh;
7040 struct rwlock *lock;
7045 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7046 ("pmap_page_exists_quick: page %p is not managed", m));
7048 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7050 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7051 if (PV_PMAP(pv) == pmap) {
7059 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7060 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7061 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7062 if (PV_PMAP(pv) == pmap) {
7076 * pmap_page_wired_mappings:
7078 * Return the number of managed mappings to the given physical page
7082 pmap_page_wired_mappings(vm_page_t m)
7084 struct rwlock *lock;
7085 struct md_page *pvh;
7089 int count, md_gen, pvh_gen;
7091 if ((m->oflags & VPO_UNMANAGED) != 0)
7093 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7097 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7099 if (!PMAP_TRYLOCK(pmap)) {
7100 md_gen = m->md.pv_gen;
7104 if (md_gen != m->md.pv_gen) {
7109 pte = pmap_pte(pmap, pv->pv_va);
7110 if ((*pte & PG_W) != 0)
7114 if ((m->flags & PG_FICTITIOUS) == 0) {
7115 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7116 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7118 if (!PMAP_TRYLOCK(pmap)) {
7119 md_gen = m->md.pv_gen;
7120 pvh_gen = pvh->pv_gen;
7124 if (md_gen != m->md.pv_gen ||
7125 pvh_gen != pvh->pv_gen) {
7130 pte = pmap_pde(pmap, pv->pv_va);
7131 if ((*pte & PG_W) != 0)
7141 * Returns TRUE if the given page is mapped individually or as part of
7142 * a 2mpage. Otherwise, returns FALSE.
7145 pmap_page_is_mapped(vm_page_t m)
7147 struct rwlock *lock;
7150 if ((m->oflags & VPO_UNMANAGED) != 0)
7152 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7154 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7155 ((m->flags & PG_FICTITIOUS) == 0 &&
7156 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7162 * Destroy all managed, non-wired mappings in the given user-space
7163 * pmap. This pmap cannot be active on any processor besides the
7166 * This function cannot be applied to the kernel pmap. Moreover, it
7167 * is not intended for general use. It is only to be used during
7168 * process termination. Consequently, it can be implemented in ways
7169 * that make it faster than pmap_remove(). First, it can more quickly
7170 * destroy mappings by iterating over the pmap's collection of PV
7171 * entries, rather than searching the page table. Second, it doesn't
7172 * have to test and clear the page table entries atomically, because
7173 * no processor is currently accessing the user address space. In
7174 * particular, a page table entry's dirty bit won't change state once
7175 * this function starts.
7177 * Although this function destroys all of the pmap's managed,
7178 * non-wired mappings, it can delay and batch the invalidation of TLB
7179 * entries without calling pmap_delayed_invl_start() and
7180 * pmap_delayed_invl_finish(). Because the pmap is not active on
7181 * any other processor, none of these TLB entries will ever be used
7182 * before their eventual invalidation. Consequently, there is no need
7183 * for either pmap_remove_all() or pmap_remove_write() to wait for
7184 * that eventual TLB invalidation.
7187 pmap_remove_pages(pmap_t pmap)
7190 pt_entry_t *pte, tpte;
7191 pt_entry_t PG_M, PG_RW, PG_V;
7192 struct spglist free;
7193 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7194 vm_page_t m, mpte, mt;
7196 struct md_page *pvh;
7197 struct pv_chunk *pc, *npc;
7198 struct rwlock *lock;
7200 uint64_t inuse, bitmask;
7201 int allfree, field, freed, i, idx;
7202 boolean_t superpage;
7206 * Assert that the given pmap is only active on the current
7207 * CPU. Unfortunately, we cannot block another CPU from
7208 * activating the pmap while this function is executing.
7210 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7213 cpuset_t other_cpus;
7215 other_cpus = all_cpus;
7217 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7218 CPU_AND(&other_cpus, &pmap->pm_active);
7220 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7225 PG_M = pmap_modified_bit(pmap);
7226 PG_V = pmap_valid_bit(pmap);
7227 PG_RW = pmap_rw_bit(pmap);
7229 for (i = 0; i < PMAP_MEMDOM; i++)
7230 TAILQ_INIT(&free_chunks[i]);
7233 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7236 for (field = 0; field < _NPCM; field++) {
7237 inuse = ~pc->pc_map[field] & pc_freemask[field];
7238 while (inuse != 0) {
7240 bitmask = 1UL << bit;
7241 idx = field * 64 + bit;
7242 pv = &pc->pc_pventry[idx];
7245 pte = pmap_pdpe(pmap, pv->pv_va);
7247 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7249 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7252 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7254 pte = &pte[pmap_pte_index(pv->pv_va)];
7258 * Keep track whether 'tpte' is a
7259 * superpage explicitly instead of
7260 * relying on PG_PS being set.
7262 * This is because PG_PS is numerically
7263 * identical to PG_PTE_PAT and thus a
7264 * regular page could be mistaken for
7270 if ((tpte & PG_V) == 0) {
7271 panic("bad pte va %lx pte %lx",
7276 * We cannot remove wired pages from a process' mapping at this time
7284 pa = tpte & PG_PS_FRAME;
7286 pa = tpte & PG_FRAME;
7288 m = PHYS_TO_VM_PAGE(pa);
7289 KASSERT(m->phys_addr == pa,
7290 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7291 m, (uintmax_t)m->phys_addr,
7294 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7295 m < &vm_page_array[vm_page_array_size],
7296 ("pmap_remove_pages: bad tpte %#jx",
7302 * Update the vm_page_t clean/reference bits.
7304 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7306 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7312 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7315 pc->pc_map[field] |= bitmask;
7317 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7318 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7319 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7321 if (TAILQ_EMPTY(&pvh->pv_list)) {
7322 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7323 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7324 TAILQ_EMPTY(&mt->md.pv_list))
7325 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7327 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7329 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7330 ("pmap_remove_pages: pte page not promoted"));
7331 pmap_resident_count_dec(pmap, 1);
7332 KASSERT(mpte->ref_count == NPTEPG,
7333 ("pmap_remove_pages: pte page reference count error"));
7334 mpte->ref_count = 0;
7335 pmap_add_delayed_free_list(mpte, &free, FALSE);
7338 pmap_resident_count_dec(pmap, 1);
7339 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7341 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7342 TAILQ_EMPTY(&m->md.pv_list) &&
7343 (m->flags & PG_FICTITIOUS) == 0) {
7344 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7345 if (TAILQ_EMPTY(&pvh->pv_list))
7346 vm_page_aflag_clear(m, PGA_WRITEABLE);
7349 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7353 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7354 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7355 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7357 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7358 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7363 pmap_invalidate_all(pmap);
7364 pmap_pkru_deassign_all(pmap);
7365 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7367 vm_page_free_pages_toq(&free, true);
7371 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7373 struct rwlock *lock;
7375 struct md_page *pvh;
7376 pt_entry_t *pte, mask;
7377 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7379 int md_gen, pvh_gen;
7383 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7386 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7388 if (!PMAP_TRYLOCK(pmap)) {
7389 md_gen = m->md.pv_gen;
7393 if (md_gen != m->md.pv_gen) {
7398 pte = pmap_pte(pmap, pv->pv_va);
7401 PG_M = pmap_modified_bit(pmap);
7402 PG_RW = pmap_rw_bit(pmap);
7403 mask |= PG_RW | PG_M;
7406 PG_A = pmap_accessed_bit(pmap);
7407 PG_V = pmap_valid_bit(pmap);
7408 mask |= PG_V | PG_A;
7410 rv = (*pte & mask) == mask;
7415 if ((m->flags & PG_FICTITIOUS) == 0) {
7416 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7417 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7419 if (!PMAP_TRYLOCK(pmap)) {
7420 md_gen = m->md.pv_gen;
7421 pvh_gen = pvh->pv_gen;
7425 if (md_gen != m->md.pv_gen ||
7426 pvh_gen != pvh->pv_gen) {
7431 pte = pmap_pde(pmap, pv->pv_va);
7434 PG_M = pmap_modified_bit(pmap);
7435 PG_RW = pmap_rw_bit(pmap);
7436 mask |= PG_RW | PG_M;
7439 PG_A = pmap_accessed_bit(pmap);
7440 PG_V = pmap_valid_bit(pmap);
7441 mask |= PG_V | PG_A;
7443 rv = (*pte & mask) == mask;
7457 * Return whether or not the specified physical page was modified
7458 * in any physical maps.
7461 pmap_is_modified(vm_page_t m)
7464 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7465 ("pmap_is_modified: page %p is not managed", m));
7468 * If the page is not busied then this check is racy.
7470 if (!pmap_page_is_write_mapped(m))
7472 return (pmap_page_test_mappings(m, FALSE, TRUE));
7476 * pmap_is_prefaultable:
7478 * Return whether or not the specified virtual address is eligible
7482 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7485 pt_entry_t *pte, PG_V;
7488 PG_V = pmap_valid_bit(pmap);
7491 pde = pmap_pde(pmap, addr);
7492 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7493 pte = pmap_pde_to_pte(pde, addr);
7494 rv = (*pte & PG_V) == 0;
7501 * pmap_is_referenced:
7503 * Return whether or not the specified physical page was referenced
7504 * in any physical maps.
7507 pmap_is_referenced(vm_page_t m)
7510 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7511 ("pmap_is_referenced: page %p is not managed", m));
7512 return (pmap_page_test_mappings(m, TRUE, FALSE));
7516 * Clear the write and modified bits in each of the given page's mappings.
7519 pmap_remove_write(vm_page_t m)
7521 struct md_page *pvh;
7523 struct rwlock *lock;
7524 pv_entry_t next_pv, pv;
7526 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7528 int pvh_gen, md_gen;
7530 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7531 ("pmap_remove_write: page %p is not managed", m));
7533 vm_page_assert_busied(m);
7534 if (!pmap_page_is_write_mapped(m))
7537 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7538 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7539 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7542 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7544 if (!PMAP_TRYLOCK(pmap)) {
7545 pvh_gen = pvh->pv_gen;
7549 if (pvh_gen != pvh->pv_gen) {
7555 PG_RW = pmap_rw_bit(pmap);
7557 pde = pmap_pde(pmap, va);
7558 if ((*pde & PG_RW) != 0)
7559 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
7560 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7561 ("inconsistent pv lock %p %p for page %p",
7562 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7565 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7567 if (!PMAP_TRYLOCK(pmap)) {
7568 pvh_gen = pvh->pv_gen;
7569 md_gen = m->md.pv_gen;
7573 if (pvh_gen != pvh->pv_gen ||
7574 md_gen != m->md.pv_gen) {
7580 PG_M = pmap_modified_bit(pmap);
7581 PG_RW = pmap_rw_bit(pmap);
7582 pde = pmap_pde(pmap, pv->pv_va);
7583 KASSERT((*pde & PG_PS) == 0,
7584 ("pmap_remove_write: found a 2mpage in page %p's pv list",
7586 pte = pmap_pde_to_pte(pde, pv->pv_va);
7589 if (oldpte & PG_RW) {
7590 if (!atomic_cmpset_long(pte, oldpte, oldpte &
7593 if ((oldpte & PG_M) != 0)
7595 pmap_invalidate_page(pmap, pv->pv_va);
7600 vm_page_aflag_clear(m, PGA_WRITEABLE);
7601 pmap_delayed_invl_wait(m);
7604 static __inline boolean_t
7605 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
7608 if (!pmap_emulate_ad_bits(pmap))
7611 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
7614 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
7615 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
7616 * if the EPT_PG_WRITE bit is set.
7618 if ((pte & EPT_PG_WRITE) != 0)
7622 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
7624 if ((pte & EPT_PG_EXECUTE) == 0 ||
7625 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
7632 * pmap_ts_referenced:
7634 * Return a count of reference bits for a page, clearing those bits.
7635 * It is not necessary for every reference bit to be cleared, but it
7636 * is necessary that 0 only be returned when there are truly no
7637 * reference bits set.
7639 * As an optimization, update the page's dirty field if a modified bit is
7640 * found while counting reference bits. This opportunistic update can be
7641 * performed at low cost and can eliminate the need for some future calls
7642 * to pmap_is_modified(). However, since this function stops after
7643 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
7644 * dirty pages. Those dirty pages will only be detected by a future call
7645 * to pmap_is_modified().
7647 * A DI block is not needed within this function, because
7648 * invalidations are performed before the PV list lock is
7652 pmap_ts_referenced(vm_page_t m)
7654 struct md_page *pvh;
7657 struct rwlock *lock;
7658 pd_entry_t oldpde, *pde;
7659 pt_entry_t *pte, PG_A, PG_M, PG_RW;
7662 int cleared, md_gen, not_cleared, pvh_gen;
7663 struct spglist free;
7666 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7667 ("pmap_ts_referenced: page %p is not managed", m));
7670 pa = VM_PAGE_TO_PHYS(m);
7671 lock = PHYS_TO_PV_LIST_LOCK(pa);
7672 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
7676 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
7677 goto small_mappings;
7683 if (!PMAP_TRYLOCK(pmap)) {
7684 pvh_gen = pvh->pv_gen;
7688 if (pvh_gen != pvh->pv_gen) {
7693 PG_A = pmap_accessed_bit(pmap);
7694 PG_M = pmap_modified_bit(pmap);
7695 PG_RW = pmap_rw_bit(pmap);
7697 pde = pmap_pde(pmap, pv->pv_va);
7699 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7701 * Although "oldpde" is mapping a 2MB page, because
7702 * this function is called at a 4KB page granularity,
7703 * we only update the 4KB page under test.
7707 if ((oldpde & PG_A) != 0) {
7709 * Since this reference bit is shared by 512 4KB
7710 * pages, it should not be cleared every time it is
7711 * tested. Apply a simple "hash" function on the
7712 * physical page number, the virtual superpage number,
7713 * and the pmap address to select one 4KB page out of
7714 * the 512 on which testing the reference bit will
7715 * result in clearing that reference bit. This
7716 * function is designed to avoid the selection of the
7717 * same 4KB page for every 2MB page mapping.
7719 * On demotion, a mapping that hasn't been referenced
7720 * is simply destroyed. To avoid the possibility of a
7721 * subsequent page fault on a demoted wired mapping,
7722 * always leave its reference bit set. Moreover,
7723 * since the superpage is wired, the current state of
7724 * its reference bit won't affect page replacement.
7726 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
7727 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
7728 (oldpde & PG_W) == 0) {
7729 if (safe_to_clear_referenced(pmap, oldpde)) {
7730 atomic_clear_long(pde, PG_A);
7731 pmap_invalidate_page(pmap, pv->pv_va);
7733 } else if (pmap_demote_pde_locked(pmap, pde,
7734 pv->pv_va, &lock)) {
7736 * Remove the mapping to a single page
7737 * so that a subsequent access may
7738 * repromote. Since the underlying
7739 * page table page is fully populated,
7740 * this removal never frees a page
7744 va += VM_PAGE_TO_PHYS(m) - (oldpde &
7746 pte = pmap_pde_to_pte(pde, va);
7747 pmap_remove_pte(pmap, pte, va, *pde,
7749 pmap_invalidate_page(pmap, va);
7755 * The superpage mapping was removed
7756 * entirely and therefore 'pv' is no
7764 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7765 ("inconsistent pv lock %p %p for page %p",
7766 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7771 /* Rotate the PV list if it has more than one entry. */
7772 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7773 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7774 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
7777 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
7779 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
7781 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
7788 if (!PMAP_TRYLOCK(pmap)) {
7789 pvh_gen = pvh->pv_gen;
7790 md_gen = m->md.pv_gen;
7794 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
7799 PG_A = pmap_accessed_bit(pmap);
7800 PG_M = pmap_modified_bit(pmap);
7801 PG_RW = pmap_rw_bit(pmap);
7802 pde = pmap_pde(pmap, pv->pv_va);
7803 KASSERT((*pde & PG_PS) == 0,
7804 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
7806 pte = pmap_pde_to_pte(pde, pv->pv_va);
7807 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
7809 if ((*pte & PG_A) != 0) {
7810 if (safe_to_clear_referenced(pmap, *pte)) {
7811 atomic_clear_long(pte, PG_A);
7812 pmap_invalidate_page(pmap, pv->pv_va);
7814 } else if ((*pte & PG_W) == 0) {
7816 * Wired pages cannot be paged out so
7817 * doing accessed bit emulation for
7818 * them is wasted effort. We do the
7819 * hard work for unwired pages only.
7821 pmap_remove_pte(pmap, pte, pv->pv_va,
7822 *pde, &free, &lock);
7823 pmap_invalidate_page(pmap, pv->pv_va);
7828 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
7829 ("inconsistent pv lock %p %p for page %p",
7830 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
7835 /* Rotate the PV list if it has more than one entry. */
7836 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
7837 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7838 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
7841 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
7842 not_cleared < PMAP_TS_REFERENCED_MAX);
7845 vm_page_free_pages_toq(&free, true);
7846 return (cleared + not_cleared);
7850 * Apply the given advice to the specified range of addresses within the
7851 * given pmap. Depending on the advice, clear the referenced and/or
7852 * modified flags in each mapping and set the mapped page's dirty field.
7855 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
7857 struct rwlock *lock;
7858 pml4_entry_t *pml4e;
7860 pd_entry_t oldpde, *pde;
7861 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
7862 vm_offset_t va, va_next;
7866 if (advice != MADV_DONTNEED && advice != MADV_FREE)
7870 * A/D bit emulation requires an alternate code path when clearing
7871 * the modified and accessed bits below. Since this function is
7872 * advisory in nature we skip it entirely for pmaps that require
7873 * A/D bit emulation.
7875 if (pmap_emulate_ad_bits(pmap))
7878 PG_A = pmap_accessed_bit(pmap);
7879 PG_G = pmap_global_bit(pmap);
7880 PG_M = pmap_modified_bit(pmap);
7881 PG_V = pmap_valid_bit(pmap);
7882 PG_RW = pmap_rw_bit(pmap);
7884 pmap_delayed_invl_start();
7886 for (; sva < eva; sva = va_next) {
7887 pml4e = pmap_pml4e(pmap, sva);
7888 if ((*pml4e & PG_V) == 0) {
7889 va_next = (sva + NBPML4) & ~PML4MASK;
7894 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7895 if ((*pdpe & PG_V) == 0) {
7896 va_next = (sva + NBPDP) & ~PDPMASK;
7901 va_next = (sva + NBPDR) & ~PDRMASK;
7904 pde = pmap_pdpe_to_pde(pdpe, sva);
7906 if ((oldpde & PG_V) == 0)
7908 else if ((oldpde & PG_PS) != 0) {
7909 if ((oldpde & PG_MANAGED) == 0)
7912 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
7917 * The large page mapping was destroyed.
7923 * Unless the page mappings are wired, remove the
7924 * mapping to a single page so that a subsequent
7925 * access may repromote. Choosing the last page
7926 * within the address range [sva, min(va_next, eva))
7927 * generally results in more repromotions. Since the
7928 * underlying page table page is fully populated, this
7929 * removal never frees a page table page.
7931 if ((oldpde & PG_W) == 0) {
7937 ("pmap_advise: no address gap"));
7938 pte = pmap_pde_to_pte(pde, va);
7939 KASSERT((*pte & PG_V) != 0,
7940 ("pmap_advise: invalid PTE"));
7941 pmap_remove_pte(pmap, pte, va, *pde, NULL,
7951 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7953 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
7955 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7956 if (advice == MADV_DONTNEED) {
7958 * Future calls to pmap_is_modified()
7959 * can be avoided by making the page
7962 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
7965 atomic_clear_long(pte, PG_M | PG_A);
7966 } else if ((*pte & PG_A) != 0)
7967 atomic_clear_long(pte, PG_A);
7971 if ((*pte & PG_G) != 0) {
7978 if (va != va_next) {
7979 pmap_invalidate_range(pmap, va, sva);
7984 pmap_invalidate_range(pmap, va, sva);
7987 pmap_invalidate_all(pmap);
7989 pmap_delayed_invl_finish();
7993 * Clear the modify bits on the specified physical page.
7996 pmap_clear_modify(vm_page_t m)
7998 struct md_page *pvh;
8000 pv_entry_t next_pv, pv;
8001 pd_entry_t oldpde, *pde;
8002 pt_entry_t *pte, PG_M, PG_RW;
8003 struct rwlock *lock;
8005 int md_gen, pvh_gen;
8007 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8008 ("pmap_clear_modify: page %p is not managed", m));
8009 vm_page_assert_busied(m);
8011 if (!pmap_page_is_write_mapped(m))
8013 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8014 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8015 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8018 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8020 if (!PMAP_TRYLOCK(pmap)) {
8021 pvh_gen = pvh->pv_gen;
8025 if (pvh_gen != pvh->pv_gen) {
8030 PG_M = pmap_modified_bit(pmap);
8031 PG_RW = pmap_rw_bit(pmap);
8033 pde = pmap_pde(pmap, va);
8035 /* If oldpde has PG_RW set, then it also has PG_M set. */
8036 if ((oldpde & PG_RW) != 0 &&
8037 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8038 (oldpde & PG_W) == 0) {
8040 * Write protect the mapping to a single page so that
8041 * a subsequent write access may repromote.
8043 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8044 pte = pmap_pde_to_pte(pde, va);
8045 atomic_clear_long(pte, PG_M | PG_RW);
8047 pmap_invalidate_page(pmap, va);
8051 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8053 if (!PMAP_TRYLOCK(pmap)) {
8054 md_gen = m->md.pv_gen;
8055 pvh_gen = pvh->pv_gen;
8059 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8064 PG_M = pmap_modified_bit(pmap);
8065 PG_RW = pmap_rw_bit(pmap);
8066 pde = pmap_pde(pmap, pv->pv_va);
8067 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8068 " a 2mpage in page %p's pv list", m));
8069 pte = pmap_pde_to_pte(pde, pv->pv_va);
8070 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8071 atomic_clear_long(pte, PG_M);
8072 pmap_invalidate_page(pmap, pv->pv_va);
8080 * Miscellaneous support routines follow
8083 /* Adjust the properties for a leaf page table entry. */
8084 static __inline void
8085 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8089 opte = *(u_long *)pte;
8091 npte = opte & ~mask;
8093 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8098 * Map a set of physical memory pages into the kernel virtual
8099 * address space. Return a pointer to where it is mapped. This
8100 * routine is intended to be used for mapping device memory,
8104 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8106 struct pmap_preinit_mapping *ppim;
8107 vm_offset_t va, offset;
8111 offset = pa & PAGE_MASK;
8112 size = round_page(offset + size);
8113 pa = trunc_page(pa);
8115 if (!pmap_initialized) {
8117 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8118 ppim = pmap_preinit_mapping + i;
8119 if (ppim->va == 0) {
8123 ppim->va = virtual_avail;
8124 virtual_avail += size;
8130 panic("%s: too many preinit mappings", __func__);
8133 * If we have a preinit mapping, re-use it.
8135 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8136 ppim = pmap_preinit_mapping + i;
8137 if (ppim->pa == pa && ppim->sz == size &&
8138 (ppim->mode == mode ||
8139 (flags & MAPDEV_SETATTR) == 0))
8140 return ((void *)(ppim->va + offset));
8143 * If the specified range of physical addresses fits within
8144 * the direct map window, use the direct map.
8146 if (pa < dmaplimit && pa + size <= dmaplimit) {
8147 va = PHYS_TO_DMAP(pa);
8148 if ((flags & MAPDEV_SETATTR) != 0) {
8149 PMAP_LOCK(kernel_pmap);
8150 i = pmap_change_props_locked(va, size,
8151 PROT_NONE, mode, flags);
8152 PMAP_UNLOCK(kernel_pmap);
8156 return ((void *)(va + offset));
8158 va = kva_alloc(size);
8160 panic("%s: Couldn't allocate KVA", __func__);
8162 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8163 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8164 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8165 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8166 pmap_invalidate_cache_range(va, va + tmpsize);
8167 return ((void *)(va + offset));
8171 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8174 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8179 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8182 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8186 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8189 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8194 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8197 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8198 MAPDEV_FLUSHCACHE));
8202 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8204 struct pmap_preinit_mapping *ppim;
8208 /* If we gave a direct map region in pmap_mapdev, do nothing */
8209 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8211 offset = va & PAGE_MASK;
8212 size = round_page(offset + size);
8213 va = trunc_page(va);
8214 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8215 ppim = pmap_preinit_mapping + i;
8216 if (ppim->va == va && ppim->sz == size) {
8217 if (pmap_initialized)
8223 if (va + size == virtual_avail)
8228 if (pmap_initialized)
8233 * Tries to demote a 1GB page mapping.
8236 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8238 pdp_entry_t newpdpe, oldpdpe;
8239 pd_entry_t *firstpde, newpde, *pde;
8240 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8244 PG_A = pmap_accessed_bit(pmap);
8245 PG_M = pmap_modified_bit(pmap);
8246 PG_V = pmap_valid_bit(pmap);
8247 PG_RW = pmap_rw_bit(pmap);
8249 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8251 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8252 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8253 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8254 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8255 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8256 " in pmap %p", va, pmap);
8259 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8260 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8261 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8262 KASSERT((oldpdpe & PG_A) != 0,
8263 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8264 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8265 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8269 * Initialize the page directory page.
8271 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8277 * Demote the mapping.
8282 * Invalidate a stale recursive mapping of the page directory page.
8284 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8286 pmap_pdpe_demotions++;
8287 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8288 " in pmap %p", va, pmap);
8293 * Sets the memory attribute for the specified page.
8296 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8299 m->md.pat_mode = ma;
8302 * If "m" is a normal page, update its direct mapping. This update
8303 * can be relied upon to perform any cache operations that are
8304 * required for data coherence.
8306 if ((m->flags & PG_FICTITIOUS) == 0 &&
8307 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8309 panic("memory attribute change on the direct map failed");
8313 * Changes the specified virtual address range's memory type to that given by
8314 * the parameter "mode". The specified virtual address range must be
8315 * completely contained within either the direct map or the kernel map. If
8316 * the virtual address range is contained within the kernel map, then the
8317 * memory type for each of the corresponding ranges of the direct map is also
8318 * changed. (The corresponding ranges of the direct map are those ranges that
8319 * map the same physical pages as the specified virtual address range.) These
8320 * changes to the direct map are necessary because Intel describes the
8321 * behavior of their processors as "undefined" if two or more mappings to the
8322 * same physical page have different memory types.
8324 * Returns zero if the change completed successfully, and either EINVAL or
8325 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8326 * of the virtual address range was not mapped, and ENOMEM is returned if
8327 * there was insufficient memory available to complete the change. In the
8328 * latter case, the memory type may have been changed on some part of the
8329 * virtual address range or the direct map.
8332 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8336 PMAP_LOCK(kernel_pmap);
8337 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8339 PMAP_UNLOCK(kernel_pmap);
8344 * Changes the specified virtual address range's protections to those
8345 * specified by "prot". Like pmap_change_attr(), protections for aliases
8346 * in the direct map are updated as well. Protections on aliasing mappings may
8347 * be a subset of the requested protections; for example, mappings in the direct
8348 * map are never executable.
8351 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8355 /* Only supported within the kernel map. */
8356 if (va < VM_MIN_KERNEL_ADDRESS)
8359 PMAP_LOCK(kernel_pmap);
8360 error = pmap_change_props_locked(va, size, prot, -1,
8361 MAPDEV_ASSERTVALID);
8362 PMAP_UNLOCK(kernel_pmap);
8367 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8368 int mode, int flags)
8370 vm_offset_t base, offset, tmpva;
8371 vm_paddr_t pa_start, pa_end, pa_end1;
8373 pd_entry_t *pde, pde_bits, pde_mask;
8374 pt_entry_t *pte, pte_bits, pte_mask;
8378 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8379 base = trunc_page(va);
8380 offset = va & PAGE_MASK;
8381 size = round_page(offset + size);
8384 * Only supported on kernel virtual addresses, including the direct
8385 * map but excluding the recursive map.
8387 if (base < DMAP_MIN_ADDRESS)
8391 * Construct our flag sets and masks. "bits" is the subset of
8392 * "mask" that will be set in each modified PTE.
8394 * Mappings in the direct map are never allowed to be executable.
8396 pde_bits = pte_bits = 0;
8397 pde_mask = pte_mask = 0;
8399 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8400 pde_mask |= X86_PG_PDE_CACHE;
8401 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8402 pte_mask |= X86_PG_PTE_CACHE;
8404 if (prot != VM_PROT_NONE) {
8405 if ((prot & VM_PROT_WRITE) != 0) {
8406 pde_bits |= X86_PG_RW;
8407 pte_bits |= X86_PG_RW;
8409 if ((prot & VM_PROT_EXECUTE) == 0 ||
8410 va < VM_MIN_KERNEL_ADDRESS) {
8414 pde_mask |= X86_PG_RW | pg_nx;
8415 pte_mask |= X86_PG_RW | pg_nx;
8419 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8420 * into 4KB pages if required.
8422 for (tmpva = base; tmpva < base + size; ) {
8423 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8424 if (pdpe == NULL || *pdpe == 0) {
8425 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8426 ("%s: addr %#lx is not mapped", __func__, tmpva));
8429 if (*pdpe & PG_PS) {
8431 * If the current 1GB page already has the required
8432 * properties, then we need not demote this page. Just
8433 * increment tmpva to the next 1GB page frame.
8435 if ((*pdpe & pde_mask) == pde_bits) {
8436 tmpva = trunc_1gpage(tmpva) + NBPDP;
8441 * If the current offset aligns with a 1GB page frame
8442 * and there is at least 1GB left within the range, then
8443 * we need not break down this page into 2MB pages.
8445 if ((tmpva & PDPMASK) == 0 &&
8446 tmpva + PDPMASK < base + size) {
8450 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8453 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8455 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8456 ("%s: addr %#lx is not mapped", __func__, tmpva));
8461 * If the current 2MB page already has the required
8462 * properties, then we need not demote this page. Just
8463 * increment tmpva to the next 2MB page frame.
8465 if ((*pde & pde_mask) == pde_bits) {
8466 tmpva = trunc_2mpage(tmpva) + NBPDR;
8471 * If the current offset aligns with a 2MB page frame
8472 * and there is at least 2MB left within the range, then
8473 * we need not break down this page into 4KB pages.
8475 if ((tmpva & PDRMASK) == 0 &&
8476 tmpva + PDRMASK < base + size) {
8480 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8483 pte = pmap_pde_to_pte(pde, tmpva);
8485 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8486 ("%s: addr %#lx is not mapped", __func__, tmpva));
8494 * Ok, all the pages exist, so run through them updating their
8495 * properties if required.
8498 pa_start = pa_end = 0;
8499 for (tmpva = base; tmpva < base + size; ) {
8500 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8501 if (*pdpe & PG_PS) {
8502 if ((*pdpe & pde_mask) != pde_bits) {
8503 pmap_pte_props(pdpe, pde_bits, pde_mask);
8506 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8507 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8508 if (pa_start == pa_end) {
8509 /* Start physical address run. */
8510 pa_start = *pdpe & PG_PS_FRAME;
8511 pa_end = pa_start + NBPDP;
8512 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8515 /* Run ended, update direct map. */
8516 error = pmap_change_props_locked(
8517 PHYS_TO_DMAP(pa_start),
8518 pa_end - pa_start, prot, mode,
8522 /* Start physical address run. */
8523 pa_start = *pdpe & PG_PS_FRAME;
8524 pa_end = pa_start + NBPDP;
8527 tmpva = trunc_1gpage(tmpva) + NBPDP;
8530 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8532 if ((*pde & pde_mask) != pde_bits) {
8533 pmap_pte_props(pde, pde_bits, pde_mask);
8536 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8537 (*pde & PG_PS_FRAME) < dmaplimit) {
8538 if (pa_start == pa_end) {
8539 /* Start physical address run. */
8540 pa_start = *pde & PG_PS_FRAME;
8541 pa_end = pa_start + NBPDR;
8542 } else if (pa_end == (*pde & PG_PS_FRAME))
8545 /* Run ended, update direct map. */
8546 error = pmap_change_props_locked(
8547 PHYS_TO_DMAP(pa_start),
8548 pa_end - pa_start, prot, mode,
8552 /* Start physical address run. */
8553 pa_start = *pde & PG_PS_FRAME;
8554 pa_end = pa_start + NBPDR;
8557 tmpva = trunc_2mpage(tmpva) + NBPDR;
8559 pte = pmap_pde_to_pte(pde, tmpva);
8560 if ((*pte & pte_mask) != pte_bits) {
8561 pmap_pte_props(pte, pte_bits, pte_mask);
8564 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8565 (*pte & PG_FRAME) < dmaplimit) {
8566 if (pa_start == pa_end) {
8567 /* Start physical address run. */
8568 pa_start = *pte & PG_FRAME;
8569 pa_end = pa_start + PAGE_SIZE;
8570 } else if (pa_end == (*pte & PG_FRAME))
8571 pa_end += PAGE_SIZE;
8573 /* Run ended, update direct map. */
8574 error = pmap_change_props_locked(
8575 PHYS_TO_DMAP(pa_start),
8576 pa_end - pa_start, prot, mode,
8580 /* Start physical address run. */
8581 pa_start = *pte & PG_FRAME;
8582 pa_end = pa_start + PAGE_SIZE;
8588 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
8589 pa_end1 = MIN(pa_end, dmaplimit);
8590 if (pa_start != pa_end1)
8591 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
8592 pa_end1 - pa_start, prot, mode, flags);
8596 * Flush CPU caches if required to make sure any data isn't cached that
8597 * shouldn't be, etc.
8600 pmap_invalidate_range(kernel_pmap, base, tmpva);
8601 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8602 pmap_invalidate_cache_range(base, tmpva);
8608 * Demotes any mapping within the direct map region that covers more than the
8609 * specified range of physical addresses. This range's size must be a power
8610 * of two and its starting address must be a multiple of its size. Since the
8611 * demotion does not change any attributes of the mapping, a TLB invalidation
8612 * is not mandatory. The caller may, however, request a TLB invalidation.
8615 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
8624 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
8625 KASSERT((base & (len - 1)) == 0,
8626 ("pmap_demote_DMAP: base is not a multiple of len"));
8627 if (len < NBPDP && base < dmaplimit) {
8628 va = PHYS_TO_DMAP(base);
8630 PMAP_LOCK(kernel_pmap);
8631 pdpe = pmap_pdpe(kernel_pmap, va);
8632 if ((*pdpe & X86_PG_V) == 0)
8633 panic("pmap_demote_DMAP: invalid PDPE");
8634 if ((*pdpe & PG_PS) != 0) {
8635 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
8636 panic("pmap_demote_DMAP: PDPE failed");
8640 pde = pmap_pdpe_to_pde(pdpe, va);
8641 if ((*pde & X86_PG_V) == 0)
8642 panic("pmap_demote_DMAP: invalid PDE");
8643 if ((*pde & PG_PS) != 0) {
8644 if (!pmap_demote_pde(kernel_pmap, pde, va))
8645 panic("pmap_demote_DMAP: PDE failed");
8649 if (changed && invalidate)
8650 pmap_invalidate_page(kernel_pmap, va);
8651 PMAP_UNLOCK(kernel_pmap);
8656 * Perform the pmap work for mincore(2). If the page is not both referenced and
8657 * modified by this pmap, returns its physical address so that the caller can
8658 * find other mappings.
8661 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
8664 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
8668 PG_A = pmap_accessed_bit(pmap);
8669 PG_M = pmap_modified_bit(pmap);
8670 PG_V = pmap_valid_bit(pmap);
8671 PG_RW = pmap_rw_bit(pmap);
8674 pdep = pmap_pde(pmap, addr);
8675 if (pdep != NULL && (*pdep & PG_V)) {
8676 if (*pdep & PG_PS) {
8678 /* Compute the physical address of the 4KB page. */
8679 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
8681 val = MINCORE_SUPER;
8683 pte = *pmap_pde_to_pte(pdep, addr);
8684 pa = pte & PG_FRAME;
8692 if ((pte & PG_V) != 0) {
8693 val |= MINCORE_INCORE;
8694 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8695 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
8696 if ((pte & PG_A) != 0)
8697 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
8699 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
8700 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
8701 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
8709 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
8711 uint32_t gen, new_gen, pcid_next;
8713 CRITICAL_ASSERT(curthread);
8714 gen = PCPU_GET(pcid_gen);
8715 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
8716 return (pti ? 0 : CR3_PCID_SAVE);
8717 if (pmap->pm_pcids[cpuid].pm_gen == gen)
8718 return (CR3_PCID_SAVE);
8719 pcid_next = PCPU_GET(pcid_next);
8720 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
8721 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
8722 ("cpu %d pcid_next %#x", cpuid, pcid_next));
8723 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
8724 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
8728 PCPU_SET(pcid_gen, new_gen);
8729 pcid_next = PMAP_PCID_KERN + 1;
8733 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
8734 pmap->pm_pcids[cpuid].pm_gen = new_gen;
8735 PCPU_SET(pcid_next, pcid_next + 1);
8740 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
8744 cached = pmap_pcid_alloc(pmap, cpuid);
8745 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
8746 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
8747 pmap->pm_pcids[cpuid].pm_pcid));
8748 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
8749 pmap == kernel_pmap,
8750 ("non-kernel pmap pmap %p cpu %d pcid %#x",
8751 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
8756 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
8759 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
8760 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
8764 pmap_activate_sw_pcid_pti(pmap_t pmap, u_int cpuid, const bool invpcid_works1)
8766 struct invpcid_descr d;
8767 uint64_t cached, cr3, kcr3, ucr3;
8769 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8771 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8772 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
8773 PCPU_SET(curpmap, pmap);
8774 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
8775 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
8778 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3) {
8780 * Explicitly invalidate translations cached from the
8781 * user page table. They are not automatically
8782 * flushed by reload of cr3 with the kernel page table
8785 * Note that the if() condition is resolved statically
8786 * by using the function argument instead of
8787 * runtime-evaluated invpcid_works value.
8789 if (invpcid_works1) {
8790 d.pcid = PMAP_PCID_USER_PT |
8791 pmap->pm_pcids[cpuid].pm_pcid;
8794 invpcid(&d, INVPCID_CTX);
8796 pmap_pti_pcid_invalidate(ucr3, kcr3);
8800 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
8801 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
8803 PCPU_INC(pm_save_cnt);
8807 pmap_activate_sw_pcid_invpcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
8810 pmap_activate_sw_pcid_pti(pmap, cpuid, true);
8811 pmap_activate_sw_pti_post(td, pmap);
8815 pmap_activate_sw_pcid_noinvpcid_pti(struct thread *td, pmap_t pmap,
8821 * If the INVPCID instruction is not available,
8822 * invltlb_pcid_handler() is used to handle an invalidate_all
8823 * IPI, which checks for curpmap == smp_tlb_pmap. The below
8824 * sequence of operations has a window where %CR3 is loaded
8825 * with the new pmap's PML4 address, but the curpmap value has
8826 * not yet been updated. This causes the invltlb IPI handler,
8827 * which is called between the updates, to execute as a NOP,
8828 * which leaves stale TLB entries.
8830 * Note that the most typical use of pmap_activate_sw(), from
8831 * the context switch, is immune to this race, because
8832 * interrupts are disabled (while the thread lock is owned),
8833 * and the IPI happens after curpmap is updated. Protect
8834 * other callers in a similar way, by disabling interrupts
8835 * around the %cr3 register reload and curpmap assignment.
8837 rflags = intr_disable();
8838 pmap_activate_sw_pcid_pti(pmap, cpuid, false);
8839 intr_restore(rflags);
8840 pmap_activate_sw_pti_post(td, pmap);
8844 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
8847 uint64_t cached, cr3;
8849 cached = pmap_pcid_alloc_checked(pmap, cpuid);
8851 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
8852 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
8854 PCPU_SET(curpmap, pmap);
8856 PCPU_INC(pm_save_cnt);
8860 pmap_activate_sw_pcid_noinvpcid_nopti(struct thread *td __unused, pmap_t pmap,
8865 rflags = intr_disable();
8866 pmap_activate_sw_pcid_nopti(td, pmap, cpuid);
8867 intr_restore(rflags);
8871 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
8872 u_int cpuid __unused)
8875 load_cr3(pmap->pm_cr3);
8876 PCPU_SET(curpmap, pmap);
8880 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
8881 u_int cpuid __unused)
8884 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
8885 PCPU_SET(kcr3, pmap->pm_cr3);
8886 PCPU_SET(ucr3, pmap->pm_ucr3);
8887 pmap_activate_sw_pti_post(td, pmap);
8890 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
8894 if (pmap_pcid_enabled && pti && invpcid_works)
8895 return (pmap_activate_sw_pcid_invpcid_pti);
8896 else if (pmap_pcid_enabled && pti && !invpcid_works)
8897 return (pmap_activate_sw_pcid_noinvpcid_pti);
8898 else if (pmap_pcid_enabled && !pti && invpcid_works)
8899 return (pmap_activate_sw_pcid_nopti);
8900 else if (pmap_pcid_enabled && !pti && !invpcid_works)
8901 return (pmap_activate_sw_pcid_noinvpcid_nopti);
8902 else if (!pmap_pcid_enabled && pti)
8903 return (pmap_activate_sw_nopcid_pti);
8904 else /* if (!pmap_pcid_enabled && !pti) */
8905 return (pmap_activate_sw_nopcid_nopti);
8909 pmap_activate_sw(struct thread *td)
8911 pmap_t oldpmap, pmap;
8914 oldpmap = PCPU_GET(curpmap);
8915 pmap = vmspace_pmap(td->td_proc->p_vmspace);
8916 if (oldpmap == pmap) {
8917 if (cpu_vendor_id != CPU_VENDOR_INTEL)
8921 cpuid = PCPU_GET(cpuid);
8923 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8925 CPU_SET(cpuid, &pmap->pm_active);
8927 pmap_activate_sw_mode(td, pmap, cpuid);
8929 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
8931 CPU_CLR(cpuid, &oldpmap->pm_active);
8936 pmap_activate(struct thread *td)
8940 pmap_activate_sw(td);
8945 pmap_activate_boot(pmap_t pmap)
8951 * kernel_pmap must be never deactivated, and we ensure that
8952 * by never activating it at all.
8954 MPASS(pmap != kernel_pmap);
8956 cpuid = PCPU_GET(cpuid);
8958 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
8960 CPU_SET(cpuid, &pmap->pm_active);
8962 PCPU_SET(curpmap, pmap);
8964 kcr3 = pmap->pm_cr3;
8965 if (pmap_pcid_enabled)
8966 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
8970 PCPU_SET(kcr3, kcr3);
8971 PCPU_SET(ucr3, PMAP_NO_CR3);
8975 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
8980 * Increase the starting virtual address of the given mapping if a
8981 * different alignment might result in more superpage mappings.
8984 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
8985 vm_offset_t *addr, vm_size_t size)
8987 vm_offset_t superpage_offset;
8991 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
8992 offset += ptoa(object->pg_color);
8993 superpage_offset = offset & PDRMASK;
8994 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
8995 (*addr & PDRMASK) == superpage_offset)
8997 if ((*addr & PDRMASK) < superpage_offset)
8998 *addr = (*addr & ~PDRMASK) + superpage_offset;
9000 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9004 static unsigned long num_dirty_emulations;
9005 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9006 &num_dirty_emulations, 0, NULL);
9008 static unsigned long num_accessed_emulations;
9009 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9010 &num_accessed_emulations, 0, NULL);
9012 static unsigned long num_superpage_accessed_emulations;
9013 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9014 &num_superpage_accessed_emulations, 0, NULL);
9016 static unsigned long ad_emulation_superpage_promotions;
9017 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9018 &ad_emulation_superpage_promotions, 0, NULL);
9019 #endif /* INVARIANTS */
9022 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9025 struct rwlock *lock;
9026 #if VM_NRESERVLEVEL > 0
9030 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9032 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9033 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9035 if (!pmap_emulate_ad_bits(pmap))
9038 PG_A = pmap_accessed_bit(pmap);
9039 PG_M = pmap_modified_bit(pmap);
9040 PG_V = pmap_valid_bit(pmap);
9041 PG_RW = pmap_rw_bit(pmap);
9047 pde = pmap_pde(pmap, va);
9048 if (pde == NULL || (*pde & PG_V) == 0)
9051 if ((*pde & PG_PS) != 0) {
9052 if (ftype == VM_PROT_READ) {
9054 atomic_add_long(&num_superpage_accessed_emulations, 1);
9062 pte = pmap_pde_to_pte(pde, va);
9063 if ((*pte & PG_V) == 0)
9066 if (ftype == VM_PROT_WRITE) {
9067 if ((*pte & PG_RW) == 0)
9070 * Set the modified and accessed bits simultaneously.
9072 * Intel EPT PTEs that do software emulation of A/D bits map
9073 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9074 * An EPT misconfiguration is triggered if the PTE is writable
9075 * but not readable (WR=10). This is avoided by setting PG_A
9076 * and PG_M simultaneously.
9078 *pte |= PG_M | PG_A;
9083 #if VM_NRESERVLEVEL > 0
9084 /* try to promote the mapping */
9085 if (va < VM_MAXUSER_ADDRESS)
9086 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9090 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9092 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9093 pmap_ps_enabled(pmap) &&
9094 (m->flags & PG_FICTITIOUS) == 0 &&
9095 vm_reserv_level_iffullpop(m) == 0) {
9096 pmap_promote_pde(pmap, pde, va, &lock);
9098 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9104 if (ftype == VM_PROT_WRITE)
9105 atomic_add_long(&num_dirty_emulations, 1);
9107 atomic_add_long(&num_accessed_emulations, 1);
9109 rv = 0; /* success */
9118 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9123 pt_entry_t *pte, PG_V;
9127 PG_V = pmap_valid_bit(pmap);
9130 pml4 = pmap_pml4e(pmap, va);
9132 if ((*pml4 & PG_V) == 0)
9135 pdp = pmap_pml4e_to_pdpe(pml4, va);
9137 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9140 pde = pmap_pdpe_to_pde(pdp, va);
9142 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9145 pte = pmap_pde_to_pte(pde, va);
9154 * Get the kernel virtual address of a set of physical pages. If there are
9155 * physical addresses not covered by the DMAP perform a transient mapping
9156 * that will be removed when calling pmap_unmap_io_transient.
9158 * \param page The pages the caller wishes to obtain the virtual
9159 * address on the kernel memory map.
9160 * \param vaddr On return contains the kernel virtual memory address
9161 * of the pages passed in the page parameter.
9162 * \param count Number of pages passed in.
9163 * \param can_fault TRUE if the thread using the mapped pages can take
9164 * page faults, FALSE otherwise.
9166 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9167 * finished or FALSE otherwise.
9171 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9172 boolean_t can_fault)
9175 boolean_t needs_mapping;
9177 int cache_bits, error __unused, i;
9180 * Allocate any KVA space that we need, this is done in a separate
9181 * loop to prevent calling vmem_alloc while pinned.
9183 needs_mapping = FALSE;
9184 for (i = 0; i < count; i++) {
9185 paddr = VM_PAGE_TO_PHYS(page[i]);
9186 if (__predict_false(paddr >= dmaplimit)) {
9187 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9188 M_BESTFIT | M_WAITOK, &vaddr[i]);
9189 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9190 needs_mapping = TRUE;
9192 vaddr[i] = PHYS_TO_DMAP(paddr);
9196 /* Exit early if everything is covered by the DMAP */
9201 * NB: The sequence of updating a page table followed by accesses
9202 * to the corresponding pages used in the !DMAP case is subject to
9203 * the situation described in the "AMD64 Architecture Programmer's
9204 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9205 * Coherency Considerations". Therefore, issuing the INVLPG right
9206 * after modifying the PTE bits is crucial.
9210 for (i = 0; i < count; i++) {
9211 paddr = VM_PAGE_TO_PHYS(page[i]);
9212 if (paddr >= dmaplimit) {
9215 * Slow path, since we can get page faults
9216 * while mappings are active don't pin the
9217 * thread to the CPU and instead add a global
9218 * mapping visible to all CPUs.
9220 pmap_qenter(vaddr[i], &page[i], 1);
9222 pte = vtopte(vaddr[i]);
9223 cache_bits = pmap_cache_bits(kernel_pmap,
9224 page[i]->md.pat_mode, 0);
9225 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9232 return (needs_mapping);
9236 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9237 boolean_t can_fault)
9244 for (i = 0; i < count; i++) {
9245 paddr = VM_PAGE_TO_PHYS(page[i]);
9246 if (paddr >= dmaplimit) {
9248 pmap_qremove(vaddr[i], 1);
9249 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9255 pmap_quick_enter_page(vm_page_t m)
9259 paddr = VM_PAGE_TO_PHYS(m);
9260 if (paddr < dmaplimit)
9261 return (PHYS_TO_DMAP(paddr));
9262 mtx_lock_spin(&qframe_mtx);
9263 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9264 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9265 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9270 pmap_quick_remove_page(vm_offset_t addr)
9275 pte_store(vtopte(qframe), 0);
9277 mtx_unlock_spin(&qframe_mtx);
9281 * Pdp pages from the large map are managed differently from either
9282 * kernel or user page table pages. They are permanently allocated at
9283 * initialization time, and their reference count is permanently set to
9284 * zero. The pml4 entries pointing to those pages are copied into
9285 * each allocated pmap.
9287 * In contrast, pd and pt pages are managed like user page table
9288 * pages. They are dynamically allocated, and their reference count
9289 * represents the number of valid entries within the page.
9292 pmap_large_map_getptp_unlocked(void)
9296 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9298 if (m != NULL && (m->flags & PG_ZERO) == 0)
9304 pmap_large_map_getptp(void)
9308 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9309 m = pmap_large_map_getptp_unlocked();
9311 PMAP_UNLOCK(kernel_pmap);
9313 PMAP_LOCK(kernel_pmap);
9314 /* Callers retry. */
9319 static pdp_entry_t *
9320 pmap_large_map_pdpe(vm_offset_t va)
9322 vm_pindex_t pml4_idx;
9325 pml4_idx = pmap_pml4e_index(va);
9326 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9327 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9329 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9330 KASSERT((kernel_pmap->pm_pml4[pml4_idx] & X86_PG_V) != 0,
9331 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9332 "LMSPML4I %#jx lm_ents %d",
9333 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9334 mphys = kernel_pmap->pm_pml4[pml4_idx] & PG_FRAME;
9335 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9339 pmap_large_map_pde(vm_offset_t va)
9346 pdpe = pmap_large_map_pdpe(va);
9348 m = pmap_large_map_getptp();
9351 mphys = VM_PAGE_TO_PHYS(m);
9352 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9354 MPASS((*pdpe & X86_PG_PS) == 0);
9355 mphys = *pdpe & PG_FRAME;
9357 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9361 pmap_large_map_pte(vm_offset_t va)
9368 pde = pmap_large_map_pde(va);
9370 m = pmap_large_map_getptp();
9373 mphys = VM_PAGE_TO_PHYS(m);
9374 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9375 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9377 MPASS((*pde & X86_PG_PS) == 0);
9378 mphys = *pde & PG_FRAME;
9380 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9384 pmap_large_map_kextract(vm_offset_t va)
9386 pdp_entry_t *pdpe, pdp;
9387 pd_entry_t *pde, pd;
9388 pt_entry_t *pte, pt;
9390 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9391 ("not largemap range %#lx", (u_long)va));
9392 pdpe = pmap_large_map_pdpe(va);
9394 KASSERT((pdp & X86_PG_V) != 0,
9395 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9396 (u_long)pdpe, pdp));
9397 if ((pdp & X86_PG_PS) != 0) {
9398 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9399 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9400 (u_long)pdpe, pdp));
9401 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9403 pde = pmap_pdpe_to_pde(pdpe, va);
9405 KASSERT((pd & X86_PG_V) != 0,
9406 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9407 if ((pd & X86_PG_PS) != 0)
9408 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9409 pte = pmap_pde_to_pte(pde, va);
9411 KASSERT((pt & X86_PG_V) != 0,
9412 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9413 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9417 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9418 vmem_addr_t *vmem_res)
9422 * Large mappings are all but static. Consequently, there
9423 * is no point in waiting for an earlier allocation to be
9426 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9427 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9431 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9437 vm_offset_t va, inc;
9438 vmem_addr_t vmem_res;
9442 if (len == 0 || spa + len < spa)
9445 /* See if DMAP can serve. */
9446 if (spa + len <= dmaplimit) {
9447 va = PHYS_TO_DMAP(spa);
9449 return (pmap_change_attr(va, len, mattr));
9453 * No, allocate KVA. Fit the address with best possible
9454 * alignment for superpages. Fall back to worse align if
9458 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9459 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9460 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9462 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9464 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9467 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9472 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9473 * in the pagetable to minimize flushing. No need to
9474 * invalidate TLB, since we only update invalid entries.
9476 PMAP_LOCK(kernel_pmap);
9477 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9479 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9480 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9481 pdpe = pmap_large_map_pdpe(va);
9483 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9484 X86_PG_V | X86_PG_A | pg_nx |
9485 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9487 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9488 (va & PDRMASK) == 0) {
9489 pde = pmap_large_map_pde(va);
9491 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9492 X86_PG_V | X86_PG_A | pg_nx |
9493 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9494 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9498 pte = pmap_large_map_pte(va);
9500 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9501 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9503 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9508 PMAP_UNLOCK(kernel_pmap);
9511 *addr = (void *)vmem_res;
9516 pmap_large_unmap(void *svaa, vm_size_t len)
9518 vm_offset_t sva, va;
9520 pdp_entry_t *pdpe, pdp;
9521 pd_entry_t *pde, pd;
9524 struct spglist spgf;
9526 sva = (vm_offset_t)svaa;
9527 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9528 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9532 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9533 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9534 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9535 PMAP_LOCK(kernel_pmap);
9536 for (va = sva; va < sva + len; va += inc) {
9537 pdpe = pmap_large_map_pdpe(va);
9539 KASSERT((pdp & X86_PG_V) != 0,
9540 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9541 (u_long)pdpe, pdp));
9542 if ((pdp & X86_PG_PS) != 0) {
9543 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9544 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9545 (u_long)pdpe, pdp));
9546 KASSERT((va & PDPMASK) == 0,
9547 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9548 (u_long)pdpe, pdp));
9549 KASSERT(va + NBPDP <= sva + len,
9550 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9551 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9552 (u_long)pdpe, pdp, len));
9557 pde = pmap_pdpe_to_pde(pdpe, va);
9559 KASSERT((pd & X86_PG_V) != 0,
9560 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9562 if ((pd & X86_PG_PS) != 0) {
9563 KASSERT((va & PDRMASK) == 0,
9564 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9566 KASSERT(va + NBPDR <= sva + len,
9567 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9568 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9572 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9574 if (m->ref_count == 0) {
9576 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9580 pte = pmap_pde_to_pte(pde, va);
9581 KASSERT((*pte & X86_PG_V) != 0,
9582 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9583 (u_long)pte, *pte));
9586 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
9588 if (m->ref_count == 0) {
9590 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9591 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9593 if (m->ref_count == 0) {
9595 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9599 pmap_invalidate_range(kernel_pmap, sva, sva + len);
9600 PMAP_UNLOCK(kernel_pmap);
9601 vm_page_free_pages_toq(&spgf, false);
9602 vmem_free(large_vmem, sva, len);
9606 pmap_large_map_wb_fence_mfence(void)
9613 pmap_large_map_wb_fence_atomic(void)
9616 atomic_thread_fence_seq_cst();
9620 pmap_large_map_wb_fence_nop(void)
9624 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
9627 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9628 return (pmap_large_map_wb_fence_mfence);
9629 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
9630 CPUID_STDEXT_CLFLUSHOPT)) == 0)
9631 return (pmap_large_map_wb_fence_atomic);
9633 /* clflush is strongly enough ordered */
9634 return (pmap_large_map_wb_fence_nop);
9638 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
9641 for (; len > 0; len -= cpu_clflush_line_size,
9642 va += cpu_clflush_line_size)
9647 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
9650 for (; len > 0; len -= cpu_clflush_line_size,
9651 va += cpu_clflush_line_size)
9656 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
9659 for (; len > 0; len -= cpu_clflush_line_size,
9660 va += cpu_clflush_line_size)
9665 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
9669 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
9672 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
9673 return (pmap_large_map_flush_range_clwb);
9674 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
9675 return (pmap_large_map_flush_range_clflushopt);
9676 else if ((cpu_feature & CPUID_CLFSH) != 0)
9677 return (pmap_large_map_flush_range_clflush);
9679 return (pmap_large_map_flush_range_nop);
9683 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
9685 volatile u_long *pe;
9691 for (va = sva; va < eva; va += inc) {
9693 if ((amd_feature & AMDID_PAGE1GB) != 0) {
9694 pe = (volatile u_long *)pmap_large_map_pdpe(va);
9696 if ((p & X86_PG_PS) != 0)
9700 pe = (volatile u_long *)pmap_large_map_pde(va);
9702 if ((p & X86_PG_PS) != 0)
9706 pe = (volatile u_long *)pmap_large_map_pte(va);
9712 if ((p & X86_PG_AVAIL1) != 0) {
9714 * Spin-wait for the end of a parallel
9721 * If we saw other write-back
9722 * occuring, we cannot rely on PG_M to
9723 * indicate state of the cache. The
9724 * PG_M bit is cleared before the
9725 * flush to avoid ignoring new writes,
9726 * and writes which are relevant for
9727 * us might happen after.
9733 if ((p & X86_PG_M) != 0 || seen_other) {
9734 if (!atomic_fcmpset_long(pe, &p,
9735 (p & ~X86_PG_M) | X86_PG_AVAIL1))
9737 * If we saw PG_M without
9738 * PG_AVAIL1, and then on the
9739 * next attempt we do not
9740 * observe either PG_M or
9741 * PG_AVAIL1, the other
9742 * write-back started after us
9743 * and finished before us. We
9744 * can rely on it doing our
9748 pmap_large_map_flush_range(va, inc);
9749 atomic_clear_long(pe, X86_PG_AVAIL1);
9758 * Write-back cache lines for the given address range.
9760 * Must be called only on the range or sub-range returned from
9761 * pmap_large_map(). Must not be called on the coalesced ranges.
9763 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
9764 * instructions support.
9767 pmap_large_map_wb(void *svap, vm_size_t len)
9769 vm_offset_t eva, sva;
9771 sva = (vm_offset_t)svap;
9773 pmap_large_map_wb_fence();
9774 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
9775 pmap_large_map_flush_range(sva, len);
9777 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
9778 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
9779 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
9780 pmap_large_map_wb_large(sva, eva);
9782 pmap_large_map_wb_fence();
9786 pmap_pti_alloc_page(void)
9790 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9791 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
9792 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
9797 pmap_pti_free_page(vm_page_t m)
9800 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
9801 if (!vm_page_unwire_noq(m))
9803 vm_page_free_zero(m);
9817 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
9818 VM_OBJECT_WLOCK(pti_obj);
9819 pml4_pg = pmap_pti_alloc_page();
9820 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
9821 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
9822 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
9823 pdpe = pmap_pti_pdpe(va);
9824 pmap_pti_wire_pte(pdpe);
9826 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
9827 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
9828 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
9829 sizeof(struct gate_descriptor) * NIDT, false);
9831 /* Doublefault stack IST 1 */
9832 va = __pcpu[i].pc_common_tss.tss_ist1;
9833 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9834 /* NMI stack IST 2 */
9835 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
9836 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9837 /* MC# stack IST 3 */
9838 va = __pcpu[i].pc_common_tss.tss_ist3 +
9839 sizeof(struct nmi_pcpu);
9840 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9841 /* DB# stack IST 4 */
9842 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
9843 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
9845 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
9846 (vm_offset_t)etext, true);
9847 pti_finalized = true;
9848 VM_OBJECT_WUNLOCK(pti_obj);
9850 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
9852 static pdp_entry_t *
9853 pmap_pti_pdpe(vm_offset_t va)
9855 pml4_entry_t *pml4e;
9858 vm_pindex_t pml4_idx;
9861 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9863 pml4_idx = pmap_pml4e_index(va);
9864 pml4e = &pti_pml4[pml4_idx];
9868 panic("pml4 alloc after finalization\n");
9869 m = pmap_pti_alloc_page();
9871 pmap_pti_free_page(m);
9872 mphys = *pml4e & ~PAGE_MASK;
9874 mphys = VM_PAGE_TO_PHYS(m);
9875 *pml4e = mphys | X86_PG_RW | X86_PG_V;
9878 mphys = *pml4e & ~PAGE_MASK;
9880 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
9885 pmap_pti_wire_pte(void *pte)
9889 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9890 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9895 pmap_pti_unwire_pde(void *pde, bool only_ref)
9899 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9900 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
9901 MPASS(m->ref_count > 0);
9902 MPASS(only_ref || m->ref_count > 1);
9903 pmap_pti_free_page(m);
9907 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
9912 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9913 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
9914 MPASS(m->ref_count > 0);
9915 if (pmap_pti_free_page(m)) {
9916 pde = pmap_pti_pde(va);
9917 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
9919 pmap_pti_unwire_pde(pde, false);
9924 pmap_pti_pde(vm_offset_t va)
9932 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9934 pdpe = pmap_pti_pdpe(va);
9936 m = pmap_pti_alloc_page();
9938 pmap_pti_free_page(m);
9939 MPASS((*pdpe & X86_PG_PS) == 0);
9940 mphys = *pdpe & ~PAGE_MASK;
9942 mphys = VM_PAGE_TO_PHYS(m);
9943 *pdpe = mphys | X86_PG_RW | X86_PG_V;
9946 MPASS((*pdpe & X86_PG_PS) == 0);
9947 mphys = *pdpe & ~PAGE_MASK;
9950 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
9951 pd_idx = pmap_pde_index(va);
9957 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
9964 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
9966 pde = pmap_pti_pde(va);
9967 if (unwire_pde != NULL) {
9969 pmap_pti_wire_pte(pde);
9972 m = pmap_pti_alloc_page();
9974 pmap_pti_free_page(m);
9975 MPASS((*pde & X86_PG_PS) == 0);
9976 mphys = *pde & ~(PAGE_MASK | pg_nx);
9978 mphys = VM_PAGE_TO_PHYS(m);
9979 *pde = mphys | X86_PG_RW | X86_PG_V;
9980 if (unwire_pde != NULL)
9981 *unwire_pde = false;
9984 MPASS((*pde & X86_PG_PS) == 0);
9985 mphys = *pde & ~(PAGE_MASK | pg_nx);
9988 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
9989 pte += pmap_pte_index(va);
9995 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
9999 pt_entry_t *pte, ptev;
10002 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10004 sva = trunc_page(sva);
10005 MPASS(sva > VM_MAXUSER_ADDRESS);
10006 eva = round_page(eva);
10008 for (; sva < eva; sva += PAGE_SIZE) {
10009 pte = pmap_pti_pte(sva, &unwire_pde);
10010 pa = pmap_kextract(sva);
10011 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10012 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10013 VM_MEMATTR_DEFAULT, FALSE);
10015 pte_store(pte, ptev);
10016 pmap_pti_wire_pte(pte);
10018 KASSERT(!pti_finalized,
10019 ("pti overlap after fin %#lx %#lx %#lx",
10021 KASSERT(*pte == ptev,
10022 ("pti non-identical pte after fin %#lx %#lx %#lx",
10026 pde = pmap_pti_pde(sva);
10027 pmap_pti_unwire_pde(pde, true);
10033 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10038 VM_OBJECT_WLOCK(pti_obj);
10039 pmap_pti_add_kva_locked(sva, eva, exec);
10040 VM_OBJECT_WUNLOCK(pti_obj);
10044 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10051 sva = rounddown2(sva, PAGE_SIZE);
10052 MPASS(sva > VM_MAXUSER_ADDRESS);
10053 eva = roundup2(eva, PAGE_SIZE);
10055 VM_OBJECT_WLOCK(pti_obj);
10056 for (va = sva; va < eva; va += PAGE_SIZE) {
10057 pte = pmap_pti_pte(va, NULL);
10058 KASSERT((*pte & X86_PG_V) != 0,
10059 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10060 (u_long)pte, *pte));
10062 pmap_pti_unwire_pte(pte, va);
10064 pmap_invalidate_range(kernel_pmap, sva, eva);
10065 VM_OBJECT_WUNLOCK(pti_obj);
10069 pkru_dup_range(void *ctx __unused, void *data)
10071 struct pmap_pkru_range *node, *new_node;
10073 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10074 if (new_node == NULL)
10077 memcpy(new_node, node, sizeof(*node));
10082 pkru_free_range(void *ctx __unused, void *node)
10085 uma_zfree(pmap_pkru_ranges_zone, node);
10089 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10092 struct pmap_pkru_range *ppr;
10095 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10096 MPASS(pmap->pm_type == PT_X86);
10097 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10098 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10099 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10101 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10104 ppr->pkru_keyidx = keyidx;
10105 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10106 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10108 uma_zfree(pmap_pkru_ranges_zone, ppr);
10113 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10116 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10117 MPASS(pmap->pm_type == PT_X86);
10118 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10119 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10123 pmap_pkru_deassign_all(pmap_t pmap)
10126 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10127 if (pmap->pm_type == PT_X86 &&
10128 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10129 rangeset_remove_all(&pmap->pm_pkru);
10133 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10135 struct pmap_pkru_range *ppr, *prev_ppr;
10138 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10139 if (pmap->pm_type != PT_X86 ||
10140 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10141 sva >= VM_MAXUSER_ADDRESS)
10143 MPASS(eva <= VM_MAXUSER_ADDRESS);
10144 for (va = sva, prev_ppr = NULL; va < eva;) {
10145 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10146 if ((ppr == NULL) ^ (prev_ppr == NULL))
10152 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10154 va = ppr->pkru_rs_el.re_end;
10160 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10162 struct pmap_pkru_range *ppr;
10164 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10165 if (pmap->pm_type != PT_X86 ||
10166 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10167 va >= VM_MAXUSER_ADDRESS)
10169 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10171 return (X86_PG_PKU(ppr->pkru_keyidx));
10176 pred_pkru_on_remove(void *ctx __unused, void *r)
10178 struct pmap_pkru_range *ppr;
10181 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10185 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10188 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10189 if (pmap->pm_type == PT_X86 &&
10190 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10191 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10192 pred_pkru_on_remove);
10197 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10200 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10201 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10202 MPASS(dst_pmap->pm_type == PT_X86);
10203 MPASS(src_pmap->pm_type == PT_X86);
10204 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10205 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10207 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10211 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10214 pml4_entry_t *pml4e;
10216 pd_entry_t newpde, ptpaddr, *pde;
10217 pt_entry_t newpte, *ptep, pte;
10218 vm_offset_t va, va_next;
10221 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10222 MPASS(pmap->pm_type == PT_X86);
10223 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10225 for (changed = false, va = sva; va < eva; va = va_next) {
10226 pml4e = pmap_pml4e(pmap, va);
10227 if ((*pml4e & X86_PG_V) == 0) {
10228 va_next = (va + NBPML4) & ~PML4MASK;
10234 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10235 if ((*pdpe & X86_PG_V) == 0) {
10236 va_next = (va + NBPDP) & ~PDPMASK;
10242 va_next = (va + NBPDR) & ~PDRMASK;
10246 pde = pmap_pdpe_to_pde(pdpe, va);
10251 MPASS((ptpaddr & X86_PG_V) != 0);
10252 if ((ptpaddr & PG_PS) != 0) {
10253 if (va + NBPDR == va_next && eva >= va_next) {
10254 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10255 X86_PG_PKU(keyidx);
10256 if (newpde != ptpaddr) {
10261 } else if (!pmap_demote_pde(pmap, pde, va)) {
10269 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10270 ptep++, va += PAGE_SIZE) {
10272 if ((pte & X86_PG_V) == 0)
10274 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10275 if (newpte != pte) {
10282 pmap_invalidate_range(pmap, sva, eva);
10286 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10287 u_int keyidx, int flags)
10290 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10291 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10293 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10295 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10301 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10306 sva = trunc_page(sva);
10307 eva = round_page(eva);
10308 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10313 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10315 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10317 if (error != ENOMEM)
10325 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10329 sva = trunc_page(sva);
10330 eva = round_page(eva);
10331 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10336 error = pmap_pkru_deassign(pmap, sva, eva);
10338 pmap_pkru_update_range(pmap, sva, eva, 0);
10340 if (error != ENOMEM)
10348 * Track a range of the kernel's virtual address space that is contiguous
10349 * in various mapping attributes.
10351 struct pmap_kernel_map_range {
10360 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10366 if (eva <= range->sva)
10369 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10370 for (i = 0; i < PAT_INDEX_SIZE; i++)
10371 if (pat_index[i] == pat_idx)
10375 case PAT_WRITE_BACK:
10378 case PAT_WRITE_THROUGH:
10381 case PAT_UNCACHEABLE:
10387 case PAT_WRITE_PROTECTED:
10390 case PAT_WRITE_COMBINING:
10394 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10395 __func__, pat_idx, range->sva, eva);
10400 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10402 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10403 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10404 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10405 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10406 mode, range->pdpes, range->pdes, range->ptes);
10408 /* Reset to sentinel value. */
10409 range->sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10413 * Determine whether the attributes specified by a page table entry match those
10414 * being tracked by the current range. This is not quite as simple as a direct
10415 * flag comparison since some PAT modes have multiple representations.
10418 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10420 pt_entry_t diff, mask;
10422 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10423 diff = (range->attrs ^ attrs) & mask;
10426 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10427 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10428 pmap_pat_index(kernel_pmap, attrs, true))
10434 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10438 memset(range, 0, sizeof(*range));
10440 range->attrs = attrs;
10444 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10445 * those of the current run, dump the address range and its attributes, and
10449 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10450 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10455 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10457 attrs |= pdpe & pg_nx;
10458 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10459 if ((pdpe & PG_PS) != 0) {
10460 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10461 } else if (pde != 0) {
10462 attrs |= pde & pg_nx;
10463 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10465 if ((pde & PG_PS) != 0) {
10466 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10467 } else if (pte != 0) {
10468 attrs |= pte & pg_nx;
10469 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10470 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10472 /* Canonicalize by always using the PDE PAT bit. */
10473 if ((attrs & X86_PG_PTE_PAT) != 0)
10474 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10477 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10478 sysctl_kmaps_dump(sb, range, va);
10479 sysctl_kmaps_reinit(range, va, attrs);
10484 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10486 struct pmap_kernel_map_range range;
10487 struct sbuf sbuf, *sb;
10488 pml4_entry_t pml4e;
10489 pdp_entry_t *pdp, pdpe;
10490 pd_entry_t *pd, pde;
10491 pt_entry_t *pt, pte;
10494 int error, i, j, k, l;
10496 error = sysctl_wire_old_buffer(req, 0);
10500 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10502 /* Sentinel value. */
10503 range.sva = KVADDR(NPML4EPG - 1, NPDPEPG - 1, NPDEPG - 1, NPTEPG - 1);
10506 * Iterate over the kernel page tables without holding the kernel pmap
10507 * lock. Outside of the large map, kernel page table pages are never
10508 * freed, so at worst we will observe inconsistencies in the output.
10509 * Within the large map, ensure that PDP and PD page addresses are
10510 * valid before descending.
10512 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10515 sbuf_printf(sb, "\nRecursive map:\n");
10518 sbuf_printf(sb, "\nDirect map:\n");
10521 sbuf_printf(sb, "\nKernel map:\n");
10524 sbuf_printf(sb, "\nLarge map:\n");
10528 /* Convert to canonical form. */
10529 if (sva == 1ul << 47)
10533 pml4e = kernel_pmap->pm_pml4[i];
10534 if ((pml4e & X86_PG_V) == 0) {
10535 sva = rounddown2(sva, NBPML4);
10536 sysctl_kmaps_dump(sb, &range, sva);
10540 pa = pml4e & PG_FRAME;
10541 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10543 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10545 if ((pdpe & X86_PG_V) == 0) {
10546 sva = rounddown2(sva, NBPDP);
10547 sysctl_kmaps_dump(sb, &range, sva);
10551 pa = pdpe & PG_FRAME;
10552 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10553 vm_phys_paddr_to_vm_page(pa) == NULL)
10555 if ((pdpe & PG_PS) != 0) {
10556 sva = rounddown2(sva, NBPDP);
10557 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10563 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10565 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10567 if ((pde & X86_PG_V) == 0) {
10568 sva = rounddown2(sva, NBPDR);
10569 sysctl_kmaps_dump(sb, &range, sva);
10573 pa = pde & PG_FRAME;
10574 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10575 vm_phys_paddr_to_vm_page(pa) == NULL)
10577 if ((pde & PG_PS) != 0) {
10578 sva = rounddown2(sva, NBPDR);
10579 sysctl_kmaps_check(sb, &range, sva,
10580 pml4e, pdpe, pde, 0);
10585 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
10587 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
10588 sva += PAGE_SIZE) {
10590 if ((pte & X86_PG_V) == 0) {
10591 sysctl_kmaps_dump(sb, &range,
10595 sysctl_kmaps_check(sb, &range, sva,
10596 pml4e, pdpe, pde, pte);
10603 error = sbuf_finish(sb);
10607 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
10608 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
10609 NULL, 0, sysctl_kmaps, "A",
10610 "Dump kernel address layout");
10613 DB_SHOW_COMMAND(pte, pmap_print_pte)
10616 pml4_entry_t *pml4;
10619 pt_entry_t *pte, PG_V;
10623 db_printf("show pte addr\n");
10626 va = (vm_offset_t)addr;
10628 if (kdb_thread != NULL)
10629 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
10631 pmap = PCPU_GET(curpmap);
10633 PG_V = pmap_valid_bit(pmap);
10634 pml4 = pmap_pml4e(pmap, va);
10635 db_printf("VA 0x%016lx pml4e 0x%016lx", va, *pml4);
10636 if ((*pml4 & PG_V) == 0) {
10640 pdp = pmap_pml4e_to_pdpe(pml4, va);
10641 db_printf(" pdpe 0x%016lx", *pdp);
10642 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
10646 pde = pmap_pdpe_to_pde(pdp, va);
10647 db_printf(" pde 0x%016lx", *pde);
10648 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
10652 pte = pmap_pde_to_pte(pde, va);
10653 db_printf(" pte 0x%016lx\n", *pte);
10656 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
10661 a = (vm_paddr_t)addr;
10662 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
10664 db_printf("show phys2dmap addr\n");