2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2019 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
327 #define pa_index(pa) ({ \
328 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
329 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_index(pa) ((pa) >> PDRSHIFT)
344 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
346 #define NPV_LIST_LOCKS MAXCPU
348 #define PHYS_TO_PV_LIST_LOCK(pa) \
349 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
352 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
353 struct rwlock **_lockp = (lockp); \
354 struct rwlock *_new_lock; \
356 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
357 if (_new_lock != *_lockp) { \
358 if (*_lockp != NULL) \
359 rw_wunlock(*_lockp); \
360 *_lockp = _new_lock; \
365 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
366 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
368 #define RELEASE_PV_LIST_LOCK(lockp) do { \
369 struct rwlock **_lockp = (lockp); \
371 if (*_lockp != NULL) { \
372 rw_wunlock(*_lockp); \
377 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
378 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
380 struct pmap kernel_pmap_store;
382 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
383 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
386 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
387 "Number of kernel page table pages allocated on bootup");
390 vm_paddr_t dmaplimit;
391 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
394 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
395 "VM/pmap parameters");
397 static int pg_ps_enabled = 1;
398 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
399 &pg_ps_enabled, 0, "Are large page mappings enabled?");
401 int __read_frequently la57 = 0;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
404 "5-level paging for host is enabled");
407 pmap_is_la57(pmap_t pmap)
409 if (pmap->pm_type == PT_X86)
411 return (false); /* XXXKIB handle EPT */
414 #define PAT_INDEX_SIZE 8
415 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
417 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
418 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
419 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
420 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
421 u_int64_t KPML5phys; /* phys addr of kernel level 5,
424 static pml4_entry_t *kernel_pml4;
425 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
426 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
427 static int ndmpdpphys; /* number of DMPDPphys pages */
429 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
432 * pmap_mapdev support pre initialization (i.e. console)
434 #define PMAP_PREINIT_MAPPING_COUNT 8
435 static struct pmap_preinit_mapping {
440 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
441 static int pmap_initialized;
444 * Data for the pv entry allocation mechanism.
445 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
449 pc_to_domain(struct pv_chunk *pc)
452 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
456 pc_to_domain(struct pv_chunk *pc __unused)
463 struct pv_chunks_list {
465 TAILQ_HEAD(pch, pv_chunk) pvc_list;
467 } __aligned(CACHE_LINE_SIZE);
469 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
472 struct pmap_large_md_page {
473 struct rwlock pv_lock;
474 struct md_page pv_page;
477 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
478 #define pv_dummy pv_dummy_large.pv_page
479 __read_mostly static struct pmap_large_md_page *pv_table;
480 __read_mostly vm_paddr_t pmap_last_pa;
482 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
483 static u_long pv_invl_gen[NPV_LIST_LOCKS];
484 static struct md_page *pv_table;
485 static struct md_page pv_dummy;
489 * All those kernel PT submaps that BSD is so fond of
491 pt_entry_t *CMAP1 = NULL;
493 static vm_offset_t qframe = 0;
494 static struct mtx qframe_mtx;
496 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
498 static vmem_t *large_vmem;
499 static u_int lm_ents;
500 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
501 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
503 int pmap_pcid_enabled = 1;
504 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
505 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
506 int invpcid_works = 0;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
508 "Is the invpcid instruction available ?");
510 int __read_frequently pti = 0;
511 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
513 "Page Table Isolation enabled");
514 static vm_object_t pti_obj;
515 static pml4_entry_t *pti_pml4;
516 static vm_pindex_t pti_pg_idx;
517 static bool pti_finalized;
519 struct pmap_pkru_range {
520 struct rs_el pkru_rs_el;
525 static uma_zone_t pmap_pkru_ranges_zone;
526 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
527 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
528 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
529 static void *pkru_dup_range(void *ctx, void *data);
530 static void pkru_free_range(void *ctx, void *node);
531 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
532 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
533 static void pmap_pkru_deassign_all(pmap_t pmap);
536 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
543 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
545 return (sysctl_handle_64(oidp, &res, 0, req));
547 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
548 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
549 "Count of saved TLB context on switch");
551 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
552 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
553 static struct mtx invl_gen_mtx;
554 /* Fake lock object to satisfy turnstiles interface. */
555 static struct lock_object invl_gen_ts = {
558 static struct pmap_invl_gen pmap_invl_gen_head = {
562 static u_long pmap_invl_gen = 1;
563 static int pmap_invl_waiters;
564 static struct callout pmap_invl_callout;
565 static bool pmap_invl_callout_inited;
567 #define PMAP_ASSERT_NOT_IN_DI() \
568 KASSERT(pmap_not_in_di(), ("DI already started"))
575 if ((cpu_feature2 & CPUID2_CX16) == 0)
578 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
583 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
587 locked = pmap_di_locked();
588 return (sysctl_handle_int(oidp, &locked, 0, req));
590 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
591 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
592 "Locked delayed invalidation");
594 static bool pmap_not_in_di_l(void);
595 static bool pmap_not_in_di_u(void);
596 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
599 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
603 pmap_not_in_di_l(void)
605 struct pmap_invl_gen *invl_gen;
607 invl_gen = &curthread->td_md.md_invl_gen;
608 return (invl_gen->gen == 0);
612 pmap_thread_init_invl_gen_l(struct thread *td)
614 struct pmap_invl_gen *invl_gen;
616 invl_gen = &td->td_md.md_invl_gen;
621 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
623 struct turnstile *ts;
625 ts = turnstile_trywait(&invl_gen_ts);
626 if (*m_gen > atomic_load_long(invl_gen))
627 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
629 turnstile_cancel(ts);
633 pmap_delayed_invl_finish_unblock(u_long new_gen)
635 struct turnstile *ts;
637 turnstile_chain_lock(&invl_gen_ts);
638 ts = turnstile_lookup(&invl_gen_ts);
640 pmap_invl_gen = new_gen;
642 turnstile_broadcast(ts, TS_SHARED_QUEUE);
643 turnstile_unpend(ts);
645 turnstile_chain_unlock(&invl_gen_ts);
649 * Start a new Delayed Invalidation (DI) block of code, executed by
650 * the current thread. Within a DI block, the current thread may
651 * destroy both the page table and PV list entries for a mapping and
652 * then release the corresponding PV list lock before ensuring that
653 * the mapping is flushed from the TLBs of any processors with the
657 pmap_delayed_invl_start_l(void)
659 struct pmap_invl_gen *invl_gen;
662 invl_gen = &curthread->td_md.md_invl_gen;
663 PMAP_ASSERT_NOT_IN_DI();
664 mtx_lock(&invl_gen_mtx);
665 if (LIST_EMPTY(&pmap_invl_gen_tracker))
666 currgen = pmap_invl_gen;
668 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
669 invl_gen->gen = currgen + 1;
670 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
671 mtx_unlock(&invl_gen_mtx);
675 * Finish the DI block, previously started by the current thread. All
676 * required TLB flushes for the pages marked by
677 * pmap_delayed_invl_page() must be finished before this function is
680 * This function works by bumping the global DI generation number to
681 * the generation number of the current thread's DI, unless there is a
682 * pending DI that started earlier. In the latter case, bumping the
683 * global DI generation number would incorrectly signal that the
684 * earlier DI had finished. Instead, this function bumps the earlier
685 * DI's generation number to match the generation number of the
686 * current thread's DI.
689 pmap_delayed_invl_finish_l(void)
691 struct pmap_invl_gen *invl_gen, *next;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
695 mtx_lock(&invl_gen_mtx);
696 next = LIST_NEXT(invl_gen, link);
698 pmap_delayed_invl_finish_unblock(invl_gen->gen);
700 next->gen = invl_gen->gen;
701 LIST_REMOVE(invl_gen, link);
702 mtx_unlock(&invl_gen_mtx);
707 pmap_not_in_di_u(void)
709 struct pmap_invl_gen *invl_gen;
711 invl_gen = &curthread->td_md.md_invl_gen;
712 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
716 pmap_thread_init_invl_gen_u(struct thread *td)
718 struct pmap_invl_gen *invl_gen;
720 invl_gen = &td->td_md.md_invl_gen;
722 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
726 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
728 uint64_t new_high, new_low, old_high, old_low;
731 old_low = new_low = 0;
732 old_high = new_high = (uintptr_t)0;
734 __asm volatile("lock;cmpxchg16b\t%1"
735 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
736 : "b"(new_low), "c" (new_high)
739 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
742 out->next = (void *)old_high;
745 out->next = (void *)new_high;
751 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
752 struct pmap_invl_gen *new_val)
754 uint64_t new_high, new_low, old_high, old_low;
757 new_low = new_val->gen;
758 new_high = (uintptr_t)new_val->next;
759 old_low = old_val->gen;
760 old_high = (uintptr_t)old_val->next;
762 __asm volatile("lock;cmpxchg16b\t%1"
763 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
764 : "b"(new_low), "c" (new_high)
770 static long invl_start_restart;
771 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
772 &invl_start_restart, 0,
774 static long invl_finish_restart;
775 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
776 &invl_finish_restart, 0,
778 static int invl_max_qlen;
779 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
784 #define di_delay locks_delay
787 pmap_delayed_invl_start_u(void)
789 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
791 struct lock_delay_arg lda;
799 invl_gen = &td->td_md.md_invl_gen;
800 PMAP_ASSERT_NOT_IN_DI();
801 lock_delay_arg_init(&lda, &di_delay);
802 invl_gen->saved_pri = 0;
803 pri = td->td_base_pri;
806 pri = td->td_base_pri;
808 invl_gen->saved_pri = pri;
815 for (p = &pmap_invl_gen_head;; p = prev.next) {
817 prevl = (uintptr_t)atomic_load_ptr(&p->next);
818 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
819 PV_STAT(atomic_add_long(&invl_start_restart, 1));
825 prev.next = (void *)prevl;
828 if ((ii = invl_max_qlen) < i)
829 atomic_cmpset_int(&invl_max_qlen, ii, i);
832 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
833 PV_STAT(atomic_add_long(&invl_start_restart, 1));
838 new_prev.gen = prev.gen;
839 new_prev.next = invl_gen;
840 invl_gen->gen = prev.gen + 1;
842 /* Formal fence between store to invl->gen and updating *p. */
843 atomic_thread_fence_rel();
846 * After inserting an invl_gen element with invalid bit set,
847 * this thread blocks any other thread trying to enter the
848 * delayed invalidation block. Do not allow to remove us from
849 * the CPU, because it causes starvation for other threads.
854 * ABA for *p is not possible there, since p->gen can only
855 * increase. So if the *p thread finished its di, then
856 * started a new one and got inserted into the list at the
857 * same place, its gen will appear greater than the previously
860 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
862 PV_STAT(atomic_add_long(&invl_start_restart, 1));
868 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
869 * invl_gen->next, allowing other threads to iterate past us.
870 * pmap_di_store_invl() provides fence between the generation
871 * write and the update of next.
873 invl_gen->next = NULL;
878 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
879 struct pmap_invl_gen *p)
881 struct pmap_invl_gen prev, new_prev;
885 * Load invl_gen->gen after setting invl_gen->next
886 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
887 * generations to propagate to our invl_gen->gen. Lock prefix
888 * in atomic_set_ptr() worked as seq_cst fence.
890 mygen = atomic_load_long(&invl_gen->gen);
892 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
895 KASSERT(prev.gen < mygen,
896 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
897 new_prev.gen = mygen;
898 new_prev.next = (void *)((uintptr_t)invl_gen->next &
899 ~PMAP_INVL_GEN_NEXT_INVALID);
901 /* Formal fence between load of prev and storing update to it. */
902 atomic_thread_fence_rel();
904 return (pmap_di_store_invl(p, &prev, &new_prev));
908 pmap_delayed_invl_finish_u(void)
910 struct pmap_invl_gen *invl_gen, *p;
912 struct lock_delay_arg lda;
916 invl_gen = &td->td_md.md_invl_gen;
917 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
918 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
919 ("missed invl_start: INVALID"));
920 lock_delay_arg_init(&lda, &di_delay);
923 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
924 prevl = (uintptr_t)atomic_load_ptr(&p->next);
925 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
926 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
930 if ((void *)prevl == invl_gen)
935 * It is legitimate to not find ourself on the list if a
936 * thread before us finished its DI and started it again.
938 if (__predict_false(p == NULL)) {
939 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
945 atomic_set_ptr((uintptr_t *)&invl_gen->next,
946 PMAP_INVL_GEN_NEXT_INVALID);
947 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
948 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
949 PMAP_INVL_GEN_NEXT_INVALID);
951 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
956 if (atomic_load_int(&pmap_invl_waiters) > 0)
957 pmap_delayed_invl_finish_unblock(0);
958 if (invl_gen->saved_pri != 0) {
960 sched_prio(td, invl_gen->saved_pri);
966 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
968 struct pmap_invl_gen *p, *pn;
973 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
975 nextl = (uintptr_t)atomic_load_ptr(&p->next);
976 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
977 td = first ? NULL : __containerof(p, struct thread,
979 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
980 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
981 td != NULL ? td->td_tid : -1);
987 static long invl_wait;
988 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
989 "Number of times DI invalidation blocked pmap_remove_all/write");
990 static long invl_wait_slow;
991 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
992 "Number of slow invalidation waits for lockless DI");
997 pmap_delayed_invl_genp(vm_page_t m)
1002 pa = VM_PAGE_TO_PHYS(m);
1003 if (__predict_false((pa) > pmap_last_pa))
1004 gen = &pv_dummy_large.pv_invl_gen;
1006 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1012 pmap_delayed_invl_genp(vm_page_t m)
1015 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1020 pmap_delayed_invl_callout_func(void *arg __unused)
1023 if (atomic_load_int(&pmap_invl_waiters) == 0)
1025 pmap_delayed_invl_finish_unblock(0);
1029 pmap_delayed_invl_callout_init(void *arg __unused)
1032 if (pmap_di_locked())
1034 callout_init(&pmap_invl_callout, 1);
1035 pmap_invl_callout_inited = true;
1037 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1038 pmap_delayed_invl_callout_init, NULL);
1041 * Ensure that all currently executing DI blocks, that need to flush
1042 * TLB for the given page m, actually flushed the TLB at the time the
1043 * function returned. If the page m has an empty PV list and we call
1044 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1045 * valid mapping for the page m in either its page table or TLB.
1047 * This function works by blocking until the global DI generation
1048 * number catches up with the generation number associated with the
1049 * given page m and its PV list. Since this function's callers
1050 * typically own an object lock and sometimes own a page lock, it
1051 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1055 pmap_delayed_invl_wait_l(vm_page_t m)
1059 bool accounted = false;
1062 m_gen = pmap_delayed_invl_genp(m);
1063 while (*m_gen > pmap_invl_gen) {
1066 atomic_add_long(&invl_wait, 1);
1070 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1075 pmap_delayed_invl_wait_u(vm_page_t m)
1078 struct lock_delay_arg lda;
1082 m_gen = pmap_delayed_invl_genp(m);
1083 lock_delay_arg_init(&lda, &di_delay);
1084 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1085 if (fast || !pmap_invl_callout_inited) {
1086 PV_STAT(atomic_add_long(&invl_wait, 1));
1091 * The page's invalidation generation number
1092 * is still below the current thread's number.
1093 * Prepare to block so that we do not waste
1094 * CPU cycles or worse, suffer livelock.
1096 * Since it is impossible to block without
1097 * racing with pmap_delayed_invl_finish_u(),
1098 * prepare for the race by incrementing
1099 * pmap_invl_waiters and arming a 1-tick
1100 * callout which will unblock us if we lose
1103 atomic_add_int(&pmap_invl_waiters, 1);
1106 * Re-check the current thread's invalidation
1107 * generation after incrementing
1108 * pmap_invl_waiters, so that there is no race
1109 * with pmap_delayed_invl_finish_u() setting
1110 * the page generation and checking
1111 * pmap_invl_waiters. The only race allowed
1112 * is for a missed unblock, which is handled
1116 atomic_load_long(&pmap_invl_gen_head.gen)) {
1117 callout_reset(&pmap_invl_callout, 1,
1118 pmap_delayed_invl_callout_func, NULL);
1119 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1120 pmap_delayed_invl_wait_block(m_gen,
1121 &pmap_invl_gen_head.gen);
1123 atomic_add_int(&pmap_invl_waiters, -1);
1128 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1131 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1132 pmap_thread_init_invl_gen_u);
1135 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1138 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1139 pmap_delayed_invl_start_u);
1142 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1145 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1146 pmap_delayed_invl_finish_u);
1149 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1152 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1153 pmap_delayed_invl_wait_u);
1157 * Mark the page m's PV list as participating in the current thread's
1158 * DI block. Any threads concurrently using m's PV list to remove or
1159 * restrict all mappings to m will wait for the current thread's DI
1160 * block to complete before proceeding.
1162 * The function works by setting the DI generation number for m's PV
1163 * list to at least the DI generation number of the current thread.
1164 * This forces a caller of pmap_delayed_invl_wait() to block until
1165 * current thread calls pmap_delayed_invl_finish().
1168 pmap_delayed_invl_page(vm_page_t m)
1172 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1173 gen = curthread->td_md.md_invl_gen.gen;
1176 m_gen = pmap_delayed_invl_genp(m);
1184 static caddr_t crashdumpmap;
1187 * Internal flags for pmap_enter()'s helper functions.
1189 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1190 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1193 * Internal flags for pmap_mapdev_internal() and
1194 * pmap_change_props_locked().
1196 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1197 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1198 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1200 TAILQ_HEAD(pv_chunklist, pv_chunk);
1202 static void free_pv_chunk(struct pv_chunk *pc);
1203 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1204 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1205 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1206 static int popcnt_pc_map_pq(uint64_t *map);
1207 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1208 static void reserve_pv_entries(pmap_t pmap, int needed,
1209 struct rwlock **lockp);
1210 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1211 struct rwlock **lockp);
1212 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1213 u_int flags, struct rwlock **lockp);
1214 #if VM_NRESERVLEVEL > 0
1215 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1216 struct rwlock **lockp);
1218 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1219 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1222 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1223 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1224 vm_prot_t prot, int mode, int flags);
1225 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1226 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1227 vm_offset_t va, struct rwlock **lockp);
1228 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1230 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1231 vm_prot_t prot, struct rwlock **lockp);
1232 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1233 u_int flags, vm_page_t m, struct rwlock **lockp);
1234 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1235 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1236 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1237 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1238 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1240 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1242 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1244 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1245 static vm_page_t pmap_large_map_getptp_unlocked(void);
1246 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1247 #if VM_NRESERVLEVEL > 0
1248 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1249 struct rwlock **lockp);
1251 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1253 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1254 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1256 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1257 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1258 static void pmap_pti_wire_pte(void *pte);
1259 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1260 struct spglist *free, struct rwlock **lockp);
1261 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1262 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1263 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1264 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1265 struct spglist *free);
1266 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1267 pd_entry_t *pde, struct spglist *free,
1268 struct rwlock **lockp);
1269 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1270 vm_page_t m, struct rwlock **lockp);
1271 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1273 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1275 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1276 struct rwlock **lockp, vm_offset_t va);
1277 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1278 struct rwlock **lockp);
1279 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1280 struct rwlock **lockp);
1282 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1283 struct spglist *free);
1284 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1286 /********************/
1287 /* Inline functions */
1288 /********************/
1291 * Return a non-clipped indexes for a given VA, which are page table
1292 * pages indexes at the corresponding level.
1294 static __inline vm_pindex_t
1295 pmap_pde_pindex(vm_offset_t va)
1297 return (va >> PDRSHIFT);
1300 static __inline vm_pindex_t
1301 pmap_pdpe_pindex(vm_offset_t va)
1303 return (NUPDE + (va >> PDPSHIFT));
1306 static __inline vm_pindex_t
1307 pmap_pml4e_pindex(vm_offset_t va)
1309 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1312 static __inline vm_pindex_t
1313 pmap_pml5e_pindex(vm_offset_t va)
1315 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1318 static __inline pml4_entry_t *
1319 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1322 MPASS(pmap_is_la57(pmap));
1323 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1326 static __inline pml4_entry_t *
1327 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1330 MPASS(pmap_is_la57(pmap));
1331 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1334 static __inline pml4_entry_t *
1335 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1337 pml4_entry_t *pml4e;
1339 /* XXX MPASS(pmap_is_la57(pmap); */
1340 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1341 return (&pml4e[pmap_pml4e_index(va)]);
1344 /* Return a pointer to the PML4 slot that corresponds to a VA */
1345 static __inline pml4_entry_t *
1346 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1348 pml5_entry_t *pml5e;
1349 pml4_entry_t *pml4e;
1352 if (pmap_is_la57(pmap)) {
1353 pml5e = pmap_pml5e(pmap, va);
1354 PG_V = pmap_valid_bit(pmap);
1355 if ((*pml5e & PG_V) == 0)
1357 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1359 pml4e = pmap->pm_pmltop;
1361 return (&pml4e[pmap_pml4e_index(va)]);
1364 static __inline pml4_entry_t *
1365 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1367 MPASS(!pmap_is_la57(pmap));
1368 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1371 /* Return a pointer to the PDP slot that corresponds to a VA */
1372 static __inline pdp_entry_t *
1373 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1377 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1378 return (&pdpe[pmap_pdpe_index(va)]);
1381 /* Return a pointer to the PDP slot that corresponds to a VA */
1382 static __inline pdp_entry_t *
1383 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1385 pml4_entry_t *pml4e;
1388 PG_V = pmap_valid_bit(pmap);
1389 pml4e = pmap_pml4e(pmap, va);
1390 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1392 return (pmap_pml4e_to_pdpe(pml4e, va));
1395 /* Return a pointer to the PD slot that corresponds to a VA */
1396 static __inline pd_entry_t *
1397 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1401 KASSERT((*pdpe & PG_PS) == 0,
1402 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1403 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1404 return (&pde[pmap_pde_index(va)]);
1407 /* Return a pointer to the PD slot that corresponds to a VA */
1408 static __inline pd_entry_t *
1409 pmap_pde(pmap_t pmap, vm_offset_t va)
1414 PG_V = pmap_valid_bit(pmap);
1415 pdpe = pmap_pdpe(pmap, va);
1416 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1418 return (pmap_pdpe_to_pde(pdpe, va));
1421 /* Return a pointer to the PT slot that corresponds to a VA */
1422 static __inline pt_entry_t *
1423 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1427 KASSERT((*pde & PG_PS) == 0,
1428 ("%s: pde %#lx is a leaf", __func__, *pde));
1429 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1430 return (&pte[pmap_pte_index(va)]);
1433 /* Return a pointer to the PT slot that corresponds to a VA */
1434 static __inline pt_entry_t *
1435 pmap_pte(pmap_t pmap, vm_offset_t va)
1440 PG_V = pmap_valid_bit(pmap);
1441 pde = pmap_pde(pmap, va);
1442 if (pde == NULL || (*pde & PG_V) == 0)
1444 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1445 return ((pt_entry_t *)pde);
1446 return (pmap_pde_to_pte(pde, va));
1449 static __inline void
1450 pmap_resident_count_inc(pmap_t pmap, int count)
1453 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1454 pmap->pm_stats.resident_count += count;
1457 static __inline void
1458 pmap_resident_count_dec(pmap_t pmap, int count)
1461 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1462 KASSERT(pmap->pm_stats.resident_count >= count,
1463 ("pmap %p resident count underflow %ld %d", pmap,
1464 pmap->pm_stats.resident_count, count));
1465 pmap->pm_stats.resident_count -= count;
1468 PMAP_INLINE pt_entry_t *
1469 vtopte(vm_offset_t va)
1473 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1476 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1477 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1478 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1480 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1481 NPML4EPGSHIFT)) - 1);
1482 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1486 static __inline pd_entry_t *
1487 vtopde(vm_offset_t va)
1491 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1494 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1495 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1496 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1498 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1499 NPML4EPGSHIFT)) - 1);
1500 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1505 allocpages(vm_paddr_t *firstaddr, int n)
1510 bzero((void *)ret, n * PAGE_SIZE);
1511 *firstaddr += n * PAGE_SIZE;
1515 CTASSERT(powerof2(NDMPML4E));
1517 /* number of kernel PDP slots */
1518 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1521 nkpt_init(vm_paddr_t addr)
1528 pt_pages = howmany(addr, 1 << PDRSHIFT);
1529 pt_pages += NKPDPE(pt_pages);
1532 * Add some slop beyond the bare minimum required for bootstrapping
1535 * This is quite important when allocating KVA for kernel modules.
1536 * The modules are required to be linked in the negative 2GB of
1537 * the address space. If we run out of KVA in this region then
1538 * pmap_growkernel() will need to allocate page table pages to map
1539 * the entire 512GB of KVA space which is an unnecessary tax on
1542 * Secondly, device memory mapped as part of setting up the low-
1543 * level console(s) is taken from KVA, starting at virtual_avail.
1544 * This is because cninit() is called after pmap_bootstrap() but
1545 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1548 pt_pages += 32; /* 64MB additional slop. */
1554 * Returns the proper write/execute permission for a physical page that is
1555 * part of the initial boot allocations.
1557 * If the page has kernel text, it is marked as read-only. If the page has
1558 * kernel read-only data, it is marked as read-only/not-executable. If the
1559 * page has only read-write data, it is marked as read-write/not-executable.
1560 * If the page is below/above the kernel range, it is marked as read-write.
1562 * This function operates on 2M pages, since we map the kernel space that
1565 static inline pt_entry_t
1566 bootaddr_rwx(vm_paddr_t pa)
1570 * The kernel is loaded at a 2MB-aligned address, and memory below that
1571 * need not be executable. The .bss section is padded to a 2MB
1572 * boundary, so memory following the kernel need not be executable
1573 * either. Preloaded kernel modules have their mapping permissions
1574 * fixed up by the linker.
1576 if (pa < trunc_2mpage(btext - KERNBASE) ||
1577 pa >= trunc_2mpage(_end - KERNBASE))
1578 return (X86_PG_RW | pg_nx);
1581 * The linker should ensure that the read-only and read-write
1582 * portions don't share the same 2M page, so this shouldn't
1583 * impact read-only data. However, in any case, any page with
1584 * read-write data needs to be read-write.
1586 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1587 return (X86_PG_RW | pg_nx);
1590 * Mark any 2M page containing kernel text as read-only. Mark
1591 * other pages with read-only data as read-only and not executable.
1592 * (It is likely a small portion of the read-only data section will
1593 * be marked as read-only, but executable. This should be acceptable
1594 * since the read-only protection will keep the data from changing.)
1595 * Note that fixups to the .text section will still work until we
1598 if (pa < round_2mpage(etext - KERNBASE))
1604 create_pagetables(vm_paddr_t *firstaddr)
1606 int i, j, ndm1g, nkpdpe, nkdmpde;
1610 uint64_t DMPDkernphys;
1612 /* Allocate page table pages for the direct map */
1613 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1614 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1616 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1617 if (ndmpdpphys > NDMPML4E) {
1619 * Each NDMPML4E allows 512 GB, so limit to that,
1620 * and then readjust ndmpdp and ndmpdpphys.
1622 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1623 Maxmem = atop(NDMPML4E * NBPML4);
1624 ndmpdpphys = NDMPML4E;
1625 ndmpdp = NDMPML4E * NPDEPG;
1627 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1629 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1631 * Calculate the number of 1G pages that will fully fit in
1634 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1637 * Allocate 2M pages for the kernel. These will be used in
1638 * place of the first one or more 1G pages from ndm1g.
1640 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1641 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1644 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1645 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1647 /* Allocate pages */
1648 KPML4phys = allocpages(firstaddr, 1);
1649 KPDPphys = allocpages(firstaddr, NKPML4E);
1652 * Allocate the initial number of kernel page table pages required to
1653 * bootstrap. We defer this until after all memory-size dependent
1654 * allocations are done (e.g. direct map), so that we don't have to
1655 * build in too much slop in our estimate.
1657 * Note that when NKPML4E > 1, we have an empty page underneath
1658 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1659 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1661 nkpt_init(*firstaddr);
1662 nkpdpe = NKPDPE(nkpt);
1664 KPTphys = allocpages(firstaddr, nkpt);
1665 KPDphys = allocpages(firstaddr, nkpdpe);
1668 * Connect the zero-filled PT pages to their PD entries. This
1669 * implicitly maps the PT pages at their correct locations within
1672 pd_p = (pd_entry_t *)KPDphys;
1673 for (i = 0; i < nkpt; i++)
1674 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1677 * Map from physical address zero to the end of loader preallocated
1678 * memory using 2MB pages. This replaces some of the PD entries
1681 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1682 /* Preset PG_M and PG_A because demotion expects it. */
1683 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1684 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1687 * Because we map the physical blocks in 2M pages, adjust firstaddr
1688 * to record the physical blocks we've actually mapped into kernel
1689 * virtual address space.
1691 if (*firstaddr < round_2mpage(KERNend))
1692 *firstaddr = round_2mpage(KERNend);
1694 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1695 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1696 for (i = 0; i < nkpdpe; i++)
1697 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1700 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1701 * the end of physical memory is not aligned to a 1GB page boundary,
1702 * then the residual physical memory is mapped with 2MB pages. Later,
1703 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1704 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1705 * that are partially used.
1707 pd_p = (pd_entry_t *)DMPDphys;
1708 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1709 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1710 /* Preset PG_M and PG_A because demotion expects it. */
1711 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1712 X86_PG_M | X86_PG_A | pg_nx;
1714 pdp_p = (pdp_entry_t *)DMPDPphys;
1715 for (i = 0; i < ndm1g; i++) {
1716 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1717 /* Preset PG_M and PG_A because demotion expects it. */
1718 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1719 X86_PG_M | X86_PG_A | pg_nx;
1721 for (j = 0; i < ndmpdp; i++, j++) {
1722 pdp_p[i] = DMPDphys + ptoa(j);
1723 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1727 * Instead of using a 1G page for the memory containing the kernel,
1728 * use 2M pages with read-only and no-execute permissions. (If using 1G
1729 * pages, this will partially overwrite the PDPEs above.)
1732 pd_p = (pd_entry_t *)DMPDkernphys;
1733 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1734 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1735 X86_PG_M | X86_PG_A | pg_nx |
1736 bootaddr_rwx(i << PDRSHIFT);
1737 for (i = 0; i < nkdmpde; i++)
1738 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1742 /* And recursively map PML4 to itself in order to get PTmap */
1743 p4_p = (pml4_entry_t *)KPML4phys;
1744 p4_p[PML4PML4I] = KPML4phys;
1745 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1747 /* Connect the Direct Map slot(s) up to the PML4. */
1748 for (i = 0; i < ndmpdpphys; i++) {
1749 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1750 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1753 /* Connect the KVA slots up to the PML4 */
1754 for (i = 0; i < NKPML4E; i++) {
1755 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1756 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1759 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1763 * Bootstrap the system enough to run with virtual memory.
1765 * On amd64 this is called after mapping has already been enabled
1766 * and just syncs the pmap module with what has already been done.
1767 * [We can't call it easily with mapping off since the kernel is not
1768 * mapped with PA == VA, hence we would have to relocate every address
1769 * from the linked base (virtual) address "KERNBASE" to the actual
1770 * (physical) address starting relative to 0]
1773 pmap_bootstrap(vm_paddr_t *firstaddr)
1776 pt_entry_t *pte, *pcpu_pte;
1777 struct region_descriptor r_gdt;
1778 uint64_t cr4, pcpu_phys;
1782 KERNend = *firstaddr;
1783 res = atop(KERNend - (vm_paddr_t)kernphys);
1789 * Create an initial set of page tables to run the kernel in.
1791 create_pagetables(firstaddr);
1793 pcpu_phys = allocpages(firstaddr, MAXCPU);
1796 * Add a physical memory segment (vm_phys_seg) corresponding to the
1797 * preallocated kernel page table pages so that vm_page structures
1798 * representing these pages will be created. The vm_page structures
1799 * are required for promotion of the corresponding kernel virtual
1800 * addresses to superpage mappings.
1802 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1805 * Account for the virtual addresses mapped by create_pagetables().
1807 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1808 virtual_end = VM_MAX_KERNEL_ADDRESS;
1811 * Enable PG_G global pages, then switch to the kernel page
1812 * table from the bootstrap page table. After the switch, it
1813 * is possible to enable SMEP and SMAP since PG_U bits are
1819 load_cr3(KPML4phys);
1820 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1822 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1827 * Initialize the kernel pmap (which is statically allocated).
1828 * Count bootstrap data as being resident in case any of this data is
1829 * later unmapped (using pmap_remove()) and freed.
1831 PMAP_LOCK_INIT(kernel_pmap);
1832 kernel_pmap->pm_pmltop = kernel_pml4;
1833 kernel_pmap->pm_cr3 = KPML4phys;
1834 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1835 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1836 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1837 kernel_pmap->pm_stats.resident_count = res;
1838 kernel_pmap->pm_flags = pmap_flags;
1841 * Initialize the TLB invalidations generation number lock.
1843 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1846 * Reserve some special page table entries/VA space for temporary
1849 #define SYSMAP(c, p, v, n) \
1850 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1856 * Crashdump maps. The first page is reused as CMAP1 for the
1859 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1860 CADDR1 = crashdumpmap;
1862 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1865 for (i = 0; i < MAXCPU; i++) {
1866 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1867 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1871 * Re-initialize PCPU area for BSP after switching.
1872 * Make hardware use gdt and common_tss from the new PCPU.
1874 STAILQ_INIT(&cpuhead);
1875 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1876 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1877 amd64_bsp_pcpu_init1(&__pcpu[0]);
1878 amd64_bsp_ist_init(&__pcpu[0]);
1879 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1881 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1882 sizeof(struct user_segment_descriptor));
1883 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1884 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1885 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1886 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1887 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1889 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1890 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1891 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1892 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1895 * Initialize the PAT MSR.
1896 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1897 * side-effect, invalidates stale PG_G TLB entries that might
1898 * have been created in our pre-boot environment.
1902 /* Initialize TLB Context Id. */
1903 if (pmap_pcid_enabled) {
1904 for (i = 0; i < MAXCPU; i++) {
1905 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1906 kernel_pmap->pm_pcids[i].pm_gen = 1;
1910 * PMAP_PCID_KERN + 1 is used for initialization of
1911 * proc0 pmap. The pmap' pcid state might be used by
1912 * EFIRT entry before first context switch, so it
1913 * needs to be valid.
1915 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1916 PCPU_SET(pcid_gen, 1);
1919 * pcpu area for APs is zeroed during AP startup.
1920 * pc_pcid_next and pc_pcid_gen are initialized by AP
1921 * during pcpu setup.
1923 load_cr4(rcr4() | CR4_PCIDE);
1928 * Setup the PAT MSR.
1937 /* Bail if this CPU doesn't implement PAT. */
1938 if ((cpu_feature & CPUID_PAT) == 0)
1941 /* Set default PAT index table. */
1942 for (i = 0; i < PAT_INDEX_SIZE; i++)
1944 pat_index[PAT_WRITE_BACK] = 0;
1945 pat_index[PAT_WRITE_THROUGH] = 1;
1946 pat_index[PAT_UNCACHEABLE] = 3;
1947 pat_index[PAT_WRITE_COMBINING] = 6;
1948 pat_index[PAT_WRITE_PROTECTED] = 5;
1949 pat_index[PAT_UNCACHED] = 2;
1952 * Initialize default PAT entries.
1953 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1954 * Program 5 and 6 as WP and WC.
1956 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1957 * mapping for a 2M page uses a PAT value with the bit 3 set due
1958 * to its overload with PG_PS.
1960 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1961 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1962 PAT_VALUE(2, PAT_UNCACHED) |
1963 PAT_VALUE(3, PAT_UNCACHEABLE) |
1964 PAT_VALUE(4, PAT_WRITE_BACK) |
1965 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1966 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1967 PAT_VALUE(7, PAT_UNCACHEABLE);
1971 load_cr4(cr4 & ~CR4_PGE);
1973 /* Disable caches (CD = 1, NW = 0). */
1975 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1977 /* Flushes caches and TLBs. */
1981 /* Update PAT and index table. */
1982 wrmsr(MSR_PAT, pat_msr);
1984 /* Flush caches and TLBs again. */
1988 /* Restore caches and PGE. */
1993 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1994 la57_trampoline_gdt[], la57_trampoline_end[];
1997 pmap_bootstrap_la57(void *arg __unused)
2000 pml5_entry_t *v_pml5;
2001 pml4_entry_t *v_pml4;
2005 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2006 void (*la57_tramp)(uint64_t pml5);
2007 struct region_descriptor r_gdt;
2009 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2011 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2016 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2017 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2019 m_code = vm_page_alloc_contig(NULL, 0,
2020 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2021 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2022 if ((m_code->flags & PG_ZERO) == 0)
2023 pmap_zero_page(m_code);
2024 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2025 m_pml5 = vm_page_alloc_contig(NULL, 0,
2026 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2027 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2028 if ((m_pml5->flags & PG_ZERO) == 0)
2029 pmap_zero_page(m_pml5);
2030 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2031 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2032 m_pml4 = vm_page_alloc_contig(NULL, 0,
2033 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2034 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2035 if ((m_pml4->flags & PG_ZERO) == 0)
2036 pmap_zero_page(m_pml4);
2037 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2038 m_pdp = vm_page_alloc_contig(NULL, 0,
2039 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2040 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2041 if ((m_pdp->flags & PG_ZERO) == 0)
2042 pmap_zero_page(m_pdp);
2043 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2044 m_pd = vm_page_alloc_contig(NULL, 0,
2045 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2046 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2047 if ((m_pd->flags & PG_ZERO) == 0)
2048 pmap_zero_page(m_pd);
2049 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2050 m_pt = vm_page_alloc_contig(NULL, 0,
2051 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2052 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2053 if ((m_pt->flags & PG_ZERO) == 0)
2054 pmap_zero_page(m_pt);
2055 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2058 * Map m_code 1:1, it appears below 4G in KVA due to physical
2059 * address being below 4G. Since kernel KVA is in upper half,
2060 * the pml4e should be zero and free for temporary use.
2062 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2063 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2065 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2066 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2068 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2069 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2071 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2072 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2076 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2077 * entering all existing kernel mappings into level 5 table.
2079 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2080 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2083 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2085 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2086 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2088 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2089 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2093 * Copy and call the 48->57 trampoline, hope we return there, alive.
2095 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2096 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2097 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2098 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2099 la57_tramp(KPML5phys);
2102 * gdt was necessary reset, switch back to our gdt.
2105 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2109 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2110 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2111 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2114 * Now unmap the trampoline, and free the pages.
2115 * Clear pml5 entry used for 1:1 trampoline mapping.
2117 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2118 invlpg((vm_offset_t)v_code);
2119 vm_page_free(m_code);
2120 vm_page_free(m_pdp);
2125 * Recursively map PML5 to itself in order to get PTmap and
2128 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2130 kernel_pmap->pm_cr3 = KPML5phys;
2131 kernel_pmap->pm_pmltop = v_pml5;
2133 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2136 * Initialize a vm_page's machine-dependent fields.
2139 pmap_page_init(vm_page_t m)
2142 TAILQ_INIT(&m->md.pv_list);
2143 m->md.pat_mode = PAT_WRITE_BACK;
2146 static int pmap_allow_2m_x_ept;
2147 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2148 &pmap_allow_2m_x_ept, 0,
2149 "Allow executable superpage mappings in EPT");
2152 pmap_allow_2m_x_ept_recalculate(void)
2155 * SKL002, SKL012S. Since the EPT format is only used by
2156 * Intel CPUs, the vendor check is merely a formality.
2158 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2159 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2160 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2161 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2162 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2163 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2164 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2165 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2166 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2167 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2168 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2169 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2170 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2171 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2172 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2173 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2174 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2175 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2176 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2177 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2178 CPUID_TO_MODEL(cpu_id) == 0x85))))
2179 pmap_allow_2m_x_ept = 1;
2180 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2184 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2187 return (pmap->pm_type != PT_EPT || !executable ||
2188 !pmap_allow_2m_x_ept);
2193 pmap_init_pv_table(void)
2195 struct pmap_large_md_page *pvd;
2197 long start, end, highest, pv_npg;
2198 int domain, i, j, pages;
2201 * We strongly depend on the size being a power of two, so the assert
2202 * is overzealous. However, should the struct be resized to a
2203 * different power of two, the code below needs to be revisited.
2205 CTASSERT((sizeof(*pvd) == 64));
2208 * Calculate the size of the array.
2210 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2211 pv_npg = howmany(pmap_last_pa, NBPDR);
2212 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2214 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2215 if (pv_table == NULL)
2216 panic("%s: kva_alloc failed\n", __func__);
2219 * Iterate physical segments to allocate space for respective pages.
2223 for (i = 0; i < vm_phys_nsegs; i++) {
2224 end = vm_phys_segs[i].end / NBPDR;
2225 domain = vm_phys_segs[i].domain;
2230 start = highest + 1;
2231 pvd = &pv_table[start];
2233 pages = end - start + 1;
2234 s = round_page(pages * sizeof(*pvd));
2235 highest = start + (s / sizeof(*pvd)) - 1;
2237 for (j = 0; j < s; j += PAGE_SIZE) {
2238 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2239 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2241 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2242 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2245 for (j = 0; j < s / sizeof(*pvd); j++) {
2246 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2247 TAILQ_INIT(&pvd->pv_page.pv_list);
2248 pvd->pv_page.pv_gen = 0;
2249 pvd->pv_page.pat_mode = 0;
2250 pvd->pv_invl_gen = 0;
2254 pvd = &pv_dummy_large;
2255 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2256 TAILQ_INIT(&pvd->pv_page.pv_list);
2257 pvd->pv_page.pv_gen = 0;
2258 pvd->pv_page.pat_mode = 0;
2259 pvd->pv_invl_gen = 0;
2263 pmap_init_pv_table(void)
2269 * Initialize the pool of pv list locks.
2271 for (i = 0; i < NPV_LIST_LOCKS; i++)
2272 rw_init(&pv_list_locks[i], "pmap pv list");
2275 * Calculate the size of the pv head table for superpages.
2277 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2280 * Allocate memory for the pv head table for superpages.
2282 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2284 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2285 for (i = 0; i < pv_npg; i++)
2286 TAILQ_INIT(&pv_table[i].pv_list);
2287 TAILQ_INIT(&pv_dummy.pv_list);
2292 * Initialize the pmap module.
2293 * Called by vm_init, to initialize any structures that the pmap
2294 * system needs to map virtual memory.
2299 struct pmap_preinit_mapping *ppim;
2301 int error, i, ret, skz63;
2303 /* L1TF, reserve page @0 unconditionally */
2304 vm_page_blacklist_add(0, bootverbose);
2306 /* Detect bare-metal Skylake Server and Skylake-X. */
2307 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2308 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2310 * Skylake-X errata SKZ63. Processor May Hang When
2311 * Executing Code In an HLE Transaction Region between
2312 * 40000000H and 403FFFFFH.
2314 * Mark the pages in the range as preallocated. It
2315 * seems to be impossible to distinguish between
2316 * Skylake Server and Skylake X.
2319 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2322 printf("SKZ63: skipping 4M RAM starting "
2323 "at physical 1G\n");
2324 for (i = 0; i < atop(0x400000); i++) {
2325 ret = vm_page_blacklist_add(0x40000000 +
2327 if (!ret && bootverbose)
2328 printf("page at %#lx already used\n",
2329 0x40000000 + ptoa(i));
2335 pmap_allow_2m_x_ept_recalculate();
2338 * Initialize the vm page array entries for the kernel pmap's
2341 PMAP_LOCK(kernel_pmap);
2342 for (i = 0; i < nkpt; i++) {
2343 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2344 KASSERT(mpte >= vm_page_array &&
2345 mpte < &vm_page_array[vm_page_array_size],
2346 ("pmap_init: page table page is out of range"));
2347 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2348 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2349 mpte->ref_count = 1;
2352 * Collect the page table pages that were replaced by a 2MB
2353 * page in create_pagetables(). They are zero filled.
2355 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2356 pmap_insert_pt_page(kernel_pmap, mpte, false))
2357 panic("pmap_init: pmap_insert_pt_page failed");
2359 PMAP_UNLOCK(kernel_pmap);
2363 * If the kernel is running on a virtual machine, then it must assume
2364 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2365 * be prepared for the hypervisor changing the vendor and family that
2366 * are reported by CPUID. Consequently, the workaround for AMD Family
2367 * 10h Erratum 383 is enabled if the processor's feature set does not
2368 * include at least one feature that is only supported by older Intel
2369 * or newer AMD processors.
2371 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2372 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2373 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2375 workaround_erratum383 = 1;
2378 * Are large page mappings enabled?
2380 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2381 if (pg_ps_enabled) {
2382 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2383 ("pmap_init: can't assign to pagesizes[1]"));
2384 pagesizes[1] = NBPDR;
2388 * Initialize pv chunk lists.
2390 for (i = 0; i < PMAP_MEMDOM; i++) {
2391 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2392 TAILQ_INIT(&pv_chunks[i].pvc_list);
2394 pmap_init_pv_table();
2396 pmap_initialized = 1;
2397 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2398 ppim = pmap_preinit_mapping + i;
2401 /* Make the direct map consistent */
2402 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2403 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2404 ppim->sz, ppim->mode);
2408 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2409 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2412 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2413 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2414 (vmem_addr_t *)&qframe);
2416 panic("qframe allocation failed");
2419 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2420 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2421 lm_ents = LMEPML4I - LMSPML4I + 1;
2423 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2424 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2426 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2427 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2428 if (large_vmem == NULL) {
2429 printf("pmap: cannot create large map\n");
2432 for (i = 0; i < lm_ents; i++) {
2433 m = pmap_large_map_getptp_unlocked();
2435 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2436 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2442 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2443 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2444 "Maximum number of PML4 entries for use by large map (tunable). "
2445 "Each entry corresponds to 512GB of address space.");
2447 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2448 "2MB page mapping counters");
2450 static u_long pmap_pde_demotions;
2451 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2452 &pmap_pde_demotions, 0, "2MB page demotions");
2454 static u_long pmap_pde_mappings;
2455 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2456 &pmap_pde_mappings, 0, "2MB page mappings");
2458 static u_long pmap_pde_p_failures;
2459 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2460 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2462 static u_long pmap_pde_promotions;
2463 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2464 &pmap_pde_promotions, 0, "2MB page promotions");
2466 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2467 "1GB page mapping counters");
2469 static u_long pmap_pdpe_demotions;
2470 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2471 &pmap_pdpe_demotions, 0, "1GB page demotions");
2473 /***************************************************
2474 * Low level helper routines.....
2475 ***************************************************/
2478 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2480 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2482 switch (pmap->pm_type) {
2485 /* Verify that both PAT bits are not set at the same time */
2486 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2487 ("Invalid PAT bits in entry %#lx", entry));
2489 /* Swap the PAT bits if one of them is set */
2490 if ((entry & x86_pat_bits) != 0)
2491 entry ^= x86_pat_bits;
2495 * Nothing to do - the memory attributes are represented
2496 * the same way for regular pages and superpages.
2500 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2507 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2510 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2511 pat_index[(int)mode] >= 0);
2515 * Determine the appropriate bits to set in a PTE or PDE for a specified
2519 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2521 int cache_bits, pat_flag, pat_idx;
2523 if (!pmap_is_valid_memattr(pmap, mode))
2524 panic("Unknown caching mode %d\n", mode);
2526 switch (pmap->pm_type) {
2529 /* The PAT bit is different for PTE's and PDE's. */
2530 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2532 /* Map the caching mode to a PAT index. */
2533 pat_idx = pat_index[mode];
2535 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2538 cache_bits |= pat_flag;
2540 cache_bits |= PG_NC_PCD;
2542 cache_bits |= PG_NC_PWT;
2546 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2550 panic("unsupported pmap type %d", pmap->pm_type);
2553 return (cache_bits);
2557 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2561 switch (pmap->pm_type) {
2564 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2567 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2570 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2577 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2579 int pat_flag, pat_idx;
2582 switch (pmap->pm_type) {
2585 /* The PAT bit is different for PTE's and PDE's. */
2586 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2588 if ((pte & pat_flag) != 0)
2590 if ((pte & PG_NC_PCD) != 0)
2592 if ((pte & PG_NC_PWT) != 0)
2596 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2597 panic("EPT PTE %#lx has no PAT memory type", pte);
2598 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2602 /* See pmap_init_pat(). */
2612 pmap_ps_enabled(pmap_t pmap)
2615 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2619 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2622 switch (pmap->pm_type) {
2629 * This is a little bogus since the generation number is
2630 * supposed to be bumped up when a region of the address
2631 * space is invalidated in the page tables.
2633 * In this case the old PDE entry is valid but yet we want
2634 * to make sure that any mappings using the old entry are
2635 * invalidated in the TLB.
2637 * The reason this works as expected is because we rendezvous
2638 * "all" host cpus and force any vcpu context to exit as a
2641 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2644 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2646 pde_store(pde, newpde);
2650 * After changing the page size for the specified virtual address in the page
2651 * table, flush the corresponding entries from the processor's TLB. Only the
2652 * calling processor's TLB is affected.
2654 * The calling thread must be pinned to a processor.
2657 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2661 if (pmap_type_guest(pmap))
2664 KASSERT(pmap->pm_type == PT_X86,
2665 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2667 PG_G = pmap_global_bit(pmap);
2669 if ((newpde & PG_PS) == 0)
2670 /* Demotion: flush a specific 2MB page mapping. */
2672 else if ((newpde & PG_G) == 0)
2674 * Promotion: flush every 4KB page mapping from the TLB
2675 * because there are too many to flush individually.
2680 * Promotion: flush every 4KB page mapping from the TLB,
2681 * including any global (PG_G) mappings.
2689 * For SMP, these functions have to use the IPI mechanism for coherence.
2691 * N.B.: Before calling any of the following TLB invalidation functions,
2692 * the calling processor must ensure that all stores updating a non-
2693 * kernel page table are globally performed. Otherwise, another
2694 * processor could cache an old, pre-update entry without being
2695 * invalidated. This can happen one of two ways: (1) The pmap becomes
2696 * active on another processor after its pm_active field is checked by
2697 * one of the following functions but before a store updating the page
2698 * table is globally performed. (2) The pmap becomes active on another
2699 * processor before its pm_active field is checked but due to
2700 * speculative loads one of the following functions stills reads the
2701 * pmap as inactive on the other processor.
2703 * The kernel page table is exempt because its pm_active field is
2704 * immutable. The kernel page table is always active on every
2709 * Interrupt the cpus that are executing in the guest context.
2710 * This will force the vcpu to exit and the cached EPT mappings
2711 * will be invalidated by the host before the next vmresume.
2713 static __inline void
2714 pmap_invalidate_ept(pmap_t pmap)
2719 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2720 ("pmap_invalidate_ept: absurd pm_active"));
2723 * The TLB mappings associated with a vcpu context are not
2724 * flushed each time a different vcpu is chosen to execute.
2726 * This is in contrast with a process's vtop mappings that
2727 * are flushed from the TLB on each context switch.
2729 * Therefore we need to do more than just a TLB shootdown on
2730 * the active cpus in 'pmap->pm_active'. To do this we keep
2731 * track of the number of invalidations performed on this pmap.
2733 * Each vcpu keeps a cache of this counter and compares it
2734 * just before a vmresume. If the counter is out-of-date an
2735 * invept will be done to flush stale mappings from the TLB.
2737 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2740 * Force the vcpu to exit and trap back into the hypervisor.
2742 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2743 ipi_selected(pmap->pm_active, ipinum);
2748 pmap_invalidate_cpu_mask(pmap_t pmap)
2751 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2755 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2756 const bool invpcid_works1)
2758 struct invpcid_descr d;
2759 uint64_t kcr3, ucr3;
2763 cpuid = PCPU_GET(cpuid);
2764 if (pmap == PCPU_GET(curpmap)) {
2765 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2767 * If we context-switched right after
2768 * PCPU_GET(ucr3_load_mask), we could read the
2769 * ~CR3_PCID_SAVE mask, which causes us to skip
2770 * the code below to invalidate user pages. This
2771 * is handled in pmap_activate_sw_pcid_pti() by
2772 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2774 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2776 * Because pm_pcid is recalculated on a
2777 * context switch, we must disable switching.
2778 * Otherwise, we might use a stale value
2782 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2783 if (invpcid_works1) {
2784 d.pcid = pcid | PMAP_PCID_USER_PT;
2787 invpcid(&d, INVPCID_ADDR);
2789 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2790 ucr3 = pmap->pm_ucr3 | pcid |
2791 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2792 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2797 pmap->pm_pcids[cpuid].pm_gen = 0;
2801 pmap->pm_pcids[i].pm_gen = 0;
2805 * The fence is between stores to pm_gen and the read of the
2806 * pm_active mask. We need to ensure that it is impossible
2807 * for us to miss the bit update in pm_active and
2808 * simultaneously observe a non-zero pm_gen in
2809 * pmap_activate_sw(), otherwise TLB update is missed.
2810 * Without the fence, IA32 allows such an outcome. Note that
2811 * pm_active is updated by a locked operation, which provides
2812 * the reciprocal fence.
2814 atomic_thread_fence_seq_cst();
2818 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2821 pmap_invalidate_page_pcid(pmap, va, true);
2825 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2828 pmap_invalidate_page_pcid(pmap, va, false);
2832 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2836 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2839 if (pmap_pcid_enabled)
2840 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2841 pmap_invalidate_page_pcid_noinvpcid);
2842 return (pmap_invalidate_page_nopcid);
2846 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2847 vm_offset_t addr2 __unused)
2850 if (pmap == kernel_pmap) {
2853 if (pmap == PCPU_GET(curpmap))
2855 pmap_invalidate_page_mode(pmap, va);
2860 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2863 if (pmap_type_guest(pmap)) {
2864 pmap_invalidate_ept(pmap);
2868 KASSERT(pmap->pm_type == PT_X86,
2869 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2871 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2872 pmap_invalidate_page_curcpu_cb);
2875 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2876 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2879 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2880 const bool invpcid_works1)
2882 struct invpcid_descr d;
2883 uint64_t kcr3, ucr3;
2887 cpuid = PCPU_GET(cpuid);
2888 if (pmap == PCPU_GET(curpmap)) {
2889 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2890 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2892 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2893 if (invpcid_works1) {
2894 d.pcid = pcid | PMAP_PCID_USER_PT;
2897 for (; d.addr < eva; d.addr += PAGE_SIZE)
2898 invpcid(&d, INVPCID_ADDR);
2900 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2901 ucr3 = pmap->pm_ucr3 | pcid |
2902 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2903 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2908 pmap->pm_pcids[cpuid].pm_gen = 0;
2912 pmap->pm_pcids[i].pm_gen = 0;
2914 /* See the comment in pmap_invalidate_page_pcid(). */
2915 atomic_thread_fence_seq_cst();
2919 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2923 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2927 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2931 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2935 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2939 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2943 if (pmap_pcid_enabled)
2944 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2945 pmap_invalidate_range_pcid_noinvpcid);
2946 return (pmap_invalidate_range_nopcid);
2950 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2954 if (pmap == kernel_pmap) {
2955 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2958 if (pmap == PCPU_GET(curpmap)) {
2959 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2962 pmap_invalidate_range_mode(pmap, sva, eva);
2967 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2970 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2971 pmap_invalidate_all(pmap);
2975 if (pmap_type_guest(pmap)) {
2976 pmap_invalidate_ept(pmap);
2980 KASSERT(pmap->pm_type == PT_X86,
2981 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2983 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2984 pmap_invalidate_range_curcpu_cb);
2988 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2990 struct invpcid_descr d;
2995 if (pmap == kernel_pmap) {
2996 if (invpcid_works1) {
2997 bzero(&d, sizeof(d));
2998 invpcid(&d, INVPCID_CTXGLOB);
3003 cpuid = PCPU_GET(cpuid);
3004 if (pmap == PCPU_GET(curpmap)) {
3006 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3007 if (invpcid_works1) {
3011 invpcid(&d, INVPCID_CTX);
3013 kcr3 = pmap->pm_cr3 | pcid;
3016 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3017 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3020 pmap->pm_pcids[cpuid].pm_gen = 0;
3023 pmap->pm_pcids[i].pm_gen = 0;
3026 /* See the comment in pmap_invalidate_page_pcid(). */
3027 atomic_thread_fence_seq_cst();
3031 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3034 pmap_invalidate_all_pcid(pmap, true);
3038 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3041 pmap_invalidate_all_pcid(pmap, false);
3045 pmap_invalidate_all_nopcid(pmap_t pmap)
3048 if (pmap == kernel_pmap)
3050 else if (pmap == PCPU_GET(curpmap))
3054 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3057 if (pmap_pcid_enabled)
3058 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3059 pmap_invalidate_all_pcid_noinvpcid);
3060 return (pmap_invalidate_all_nopcid);
3064 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3065 vm_offset_t addr2 __unused)
3068 pmap_invalidate_all_mode(pmap);
3072 pmap_invalidate_all(pmap_t pmap)
3075 if (pmap_type_guest(pmap)) {
3076 pmap_invalidate_ept(pmap);
3080 KASSERT(pmap->pm_type == PT_X86,
3081 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3083 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3084 pmap_invalidate_all_curcpu_cb);
3088 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3089 vm_offset_t addr2 __unused)
3096 pmap_invalidate_cache(void)
3099 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3103 cpuset_t invalidate; /* processors that invalidate their TLB */
3108 u_int store; /* processor that updates the PDE */
3112 pmap_update_pde_action(void *arg)
3114 struct pde_action *act = arg;
3116 if (act->store == PCPU_GET(cpuid))
3117 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3121 pmap_update_pde_teardown(void *arg)
3123 struct pde_action *act = arg;
3125 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3126 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3130 * Change the page size for the specified virtual address in a way that
3131 * prevents any possibility of the TLB ever having two entries that map the
3132 * same virtual address using different page sizes. This is the recommended
3133 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3134 * machine check exception for a TLB state that is improperly diagnosed as a
3138 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3140 struct pde_action act;
3141 cpuset_t active, other_cpus;
3145 cpuid = PCPU_GET(cpuid);
3146 other_cpus = all_cpus;
3147 CPU_CLR(cpuid, &other_cpus);
3148 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3151 active = pmap->pm_active;
3153 if (CPU_OVERLAP(&active, &other_cpus)) {
3155 act.invalidate = active;
3159 act.newpde = newpde;
3160 CPU_SET(cpuid, &active);
3161 smp_rendezvous_cpus(active,
3162 smp_no_rendezvous_barrier, pmap_update_pde_action,
3163 pmap_update_pde_teardown, &act);
3165 pmap_update_pde_store(pmap, pde, newpde);
3166 if (CPU_ISSET(cpuid, &active))
3167 pmap_update_pde_invalidate(pmap, va, newpde);
3173 * Normal, non-SMP, invalidation functions.
3176 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3178 struct invpcid_descr d;
3179 uint64_t kcr3, ucr3;
3182 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3186 KASSERT(pmap->pm_type == PT_X86,
3187 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3189 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3191 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3192 pmap->pm_ucr3 != PMAP_NO_CR3) {
3194 pcid = pmap->pm_pcids[0].pm_pcid;
3195 if (invpcid_works) {
3196 d.pcid = pcid | PMAP_PCID_USER_PT;
3199 invpcid(&d, INVPCID_ADDR);
3201 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3202 ucr3 = pmap->pm_ucr3 | pcid |
3203 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3204 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3208 } else if (pmap_pcid_enabled)
3209 pmap->pm_pcids[0].pm_gen = 0;
3213 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3215 struct invpcid_descr d;
3217 uint64_t kcr3, ucr3;
3219 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3223 KASSERT(pmap->pm_type == PT_X86,
3224 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3226 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3227 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3229 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3230 pmap->pm_ucr3 != PMAP_NO_CR3) {
3232 if (invpcid_works) {
3233 d.pcid = pmap->pm_pcids[0].pm_pcid |
3237 for (; d.addr < eva; d.addr += PAGE_SIZE)
3238 invpcid(&d, INVPCID_ADDR);
3240 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3241 pm_pcid | CR3_PCID_SAVE;
3242 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3243 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3244 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3248 } else if (pmap_pcid_enabled) {
3249 pmap->pm_pcids[0].pm_gen = 0;
3254 pmap_invalidate_all(pmap_t pmap)
3256 struct invpcid_descr d;
3257 uint64_t kcr3, ucr3;
3259 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3263 KASSERT(pmap->pm_type == PT_X86,
3264 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3266 if (pmap == kernel_pmap) {
3267 if (pmap_pcid_enabled && invpcid_works) {
3268 bzero(&d, sizeof(d));
3269 invpcid(&d, INVPCID_CTXGLOB);
3273 } else if (pmap == PCPU_GET(curpmap)) {
3274 if (pmap_pcid_enabled) {
3276 if (invpcid_works) {
3277 d.pcid = pmap->pm_pcids[0].pm_pcid;
3280 invpcid(&d, INVPCID_CTX);
3281 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3282 d.pcid |= PMAP_PCID_USER_PT;
3283 invpcid(&d, INVPCID_CTX);
3286 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3287 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3288 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3289 0].pm_pcid | PMAP_PCID_USER_PT;
3290 pmap_pti_pcid_invalidate(ucr3, kcr3);
3298 } else if (pmap_pcid_enabled) {
3299 pmap->pm_pcids[0].pm_gen = 0;
3304 pmap_invalidate_cache(void)
3311 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3314 pmap_update_pde_store(pmap, pde, newpde);
3315 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3316 pmap_update_pde_invalidate(pmap, va, newpde);
3318 pmap->pm_pcids[0].pm_gen = 0;
3323 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3327 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3328 * by a promotion that did not invalidate the 512 4KB page mappings
3329 * that might exist in the TLB. Consequently, at this point, the TLB
3330 * may hold both 4KB and 2MB page mappings for the address range [va,
3331 * va + NBPDR). Therefore, the entire range must be invalidated here.
3332 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3333 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3334 * single INVLPG suffices to invalidate the 2MB page mapping from the
3337 if ((pde & PG_PROMOTED) != 0)
3338 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3340 pmap_invalidate_page(pmap, va);
3343 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3344 (vm_offset_t sva, vm_offset_t eva))
3347 if ((cpu_feature & CPUID_SS) != 0)
3348 return (pmap_invalidate_cache_range_selfsnoop);
3349 if ((cpu_feature & CPUID_CLFSH) != 0)
3350 return (pmap_force_invalidate_cache_range);
3351 return (pmap_invalidate_cache_range_all);
3354 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3357 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3360 KASSERT((sva & PAGE_MASK) == 0,
3361 ("pmap_invalidate_cache_range: sva not page-aligned"));
3362 KASSERT((eva & PAGE_MASK) == 0,
3363 ("pmap_invalidate_cache_range: eva not page-aligned"));
3367 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3370 pmap_invalidate_cache_range_check_align(sva, eva);
3374 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3377 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3380 * XXX: Some CPUs fault, hang, or trash the local APIC
3381 * registers if we use CLFLUSH on the local APIC range. The
3382 * local APIC is always uncached, so we don't need to flush
3383 * for that range anyway.
3385 if (pmap_kextract(sva) == lapic_paddr)
3388 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3390 * Do per-cache line flush. Use a locked
3391 * instruction to insure that previous stores are
3392 * included in the write-back. The processor
3393 * propagates flush to other processors in the cache
3396 atomic_thread_fence_seq_cst();
3397 for (; sva < eva; sva += cpu_clflush_line_size)
3399 atomic_thread_fence_seq_cst();
3402 * Writes are ordered by CLFLUSH on Intel CPUs.
3404 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3406 for (; sva < eva; sva += cpu_clflush_line_size)
3408 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3414 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3417 pmap_invalidate_cache_range_check_align(sva, eva);
3418 pmap_invalidate_cache();
3422 * Remove the specified set of pages from the data and instruction caches.
3424 * In contrast to pmap_invalidate_cache_range(), this function does not
3425 * rely on the CPU's self-snoop feature, because it is intended for use
3426 * when moving pages into a different cache domain.
3429 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3431 vm_offset_t daddr, eva;
3435 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3436 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3437 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3438 pmap_invalidate_cache();
3441 atomic_thread_fence_seq_cst();
3442 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3444 for (i = 0; i < count; i++) {
3445 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3446 eva = daddr + PAGE_SIZE;
3447 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3455 atomic_thread_fence_seq_cst();
3456 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3462 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3465 pmap_invalidate_cache_range_check_align(sva, eva);
3467 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3468 pmap_force_invalidate_cache_range(sva, eva);
3472 /* See comment in pmap_force_invalidate_cache_range(). */
3473 if (pmap_kextract(sva) == lapic_paddr)
3476 atomic_thread_fence_seq_cst();
3477 for (; sva < eva; sva += cpu_clflush_line_size)
3479 atomic_thread_fence_seq_cst();
3483 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3487 int error, pte_bits;
3489 KASSERT((spa & PAGE_MASK) == 0,
3490 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3491 KASSERT((epa & PAGE_MASK) == 0,
3492 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3494 if (spa < dmaplimit) {
3495 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3497 if (dmaplimit >= epa)
3502 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3504 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3506 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3507 pte = vtopte(vaddr);
3508 for (; spa < epa; spa += PAGE_SIZE) {
3510 pte_store(pte, spa | pte_bits);
3512 /* XXXKIB atomic inside flush_cache_range are excessive */
3513 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3516 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3520 * Routine: pmap_extract
3522 * Extract the physical page address associated
3523 * with the given map/virtual_address pair.
3526 pmap_extract(pmap_t pmap, vm_offset_t va)
3530 pt_entry_t *pte, PG_V;
3534 PG_V = pmap_valid_bit(pmap);
3536 pdpe = pmap_pdpe(pmap, va);
3537 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3538 if ((*pdpe & PG_PS) != 0)
3539 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3541 pde = pmap_pdpe_to_pde(pdpe, va);
3542 if ((*pde & PG_V) != 0) {
3543 if ((*pde & PG_PS) != 0) {
3544 pa = (*pde & PG_PS_FRAME) |
3547 pte = pmap_pde_to_pte(pde, va);
3548 pa = (*pte & PG_FRAME) |
3559 * Routine: pmap_extract_and_hold
3561 * Atomically extract and hold the physical page
3562 * with the given pmap and virtual address pair
3563 * if that mapping permits the given protection.
3566 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3568 pd_entry_t pde, *pdep;
3569 pt_entry_t pte, PG_RW, PG_V;
3573 PG_RW = pmap_rw_bit(pmap);
3574 PG_V = pmap_valid_bit(pmap);
3577 pdep = pmap_pde(pmap, va);
3578 if (pdep != NULL && (pde = *pdep)) {
3580 if ((pde & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0)
3581 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
3584 pte = *pmap_pde_to_pte(pdep, va);
3585 if ((pte & PG_V) != 0 &&
3586 ((pte & PG_RW) != 0 || (prot & VM_PROT_WRITE) == 0))
3587 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3589 if (m != NULL && !vm_page_wire_mapped(m))
3597 pmap_kextract(vm_offset_t va)
3602 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3603 pa = DMAP_TO_PHYS(va);
3604 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3605 pa = pmap_large_map_kextract(va);
3609 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3612 * Beware of a concurrent promotion that changes the
3613 * PDE at this point! For example, vtopte() must not
3614 * be used to access the PTE because it would use the
3615 * new PDE. It is, however, safe to use the old PDE
3616 * because the page table page is preserved by the
3619 pa = *pmap_pde_to_pte(&pde, va);
3620 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3626 /***************************************************
3627 * Low level mapping routines.....
3628 ***************************************************/
3631 * Add a wired page to the kva.
3632 * Note: not SMP coherent.
3635 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3640 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3643 static __inline void
3644 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3650 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3651 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3655 * Remove a page from the kernel pagetables.
3656 * Note: not SMP coherent.
3659 pmap_kremove(vm_offset_t va)
3668 * Used to map a range of physical addresses into kernel
3669 * virtual address space.
3671 * The value passed in '*virt' is a suggested virtual address for
3672 * the mapping. Architectures which can support a direct-mapped
3673 * physical to virtual region can return the appropriate address
3674 * within that region, leaving '*virt' unchanged. Other
3675 * architectures should map the pages starting at '*virt' and
3676 * update '*virt' with the first usable address after the mapped
3680 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3682 return PHYS_TO_DMAP(start);
3687 * Add a list of wired pages to the kva
3688 * this routine is only used for temporary
3689 * kernel mappings that do not need to have
3690 * page modification or references recorded.
3691 * Note that old mappings are simply written
3692 * over. The page *must* be wired.
3693 * Note: SMP coherent. Uses a ranged shootdown IPI.
3696 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3698 pt_entry_t *endpte, oldpte, pa, *pte;
3704 endpte = pte + count;
3705 while (pte < endpte) {
3707 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3708 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3709 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3711 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3715 if (__predict_false((oldpte & X86_PG_V) != 0))
3716 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3721 * This routine tears out page mappings from the
3722 * kernel -- it is meant only for temporary mappings.
3723 * Note: SMP coherent. Uses a ranged shootdown IPI.
3726 pmap_qremove(vm_offset_t sva, int count)
3731 while (count-- > 0) {
3732 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3736 pmap_invalidate_range(kernel_pmap, sva, va);
3739 /***************************************************
3740 * Page table page management routines.....
3741 ***************************************************/
3743 * Schedule the specified unused page table page to be freed. Specifically,
3744 * add the page to the specified list of pages that will be released to the
3745 * physical memory manager after the TLB has been updated.
3747 static __inline void
3748 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3749 boolean_t set_PG_ZERO)
3753 m->flags |= PG_ZERO;
3755 m->flags &= ~PG_ZERO;
3756 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3760 * Inserts the specified page table page into the specified pmap's collection
3761 * of idle page table pages. Each of a pmap's page table pages is responsible
3762 * for mapping a distinct range of virtual addresses. The pmap's collection is
3763 * ordered by this virtual address range.
3765 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3768 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3771 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3772 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3773 return (vm_radix_insert(&pmap->pm_root, mpte));
3777 * Removes the page table page mapping the specified virtual address from the
3778 * specified pmap's collection of idle page table pages, and returns it.
3779 * Otherwise, returns NULL if there is no page table page corresponding to the
3780 * specified virtual address.
3782 static __inline vm_page_t
3783 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3786 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3787 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3791 * Decrements a page table page's reference count, which is used to record the
3792 * number of valid page table entries within the page. If the reference count
3793 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3794 * page table page was unmapped and FALSE otherwise.
3796 static inline boolean_t
3797 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3801 if (m->ref_count == 0) {
3802 _pmap_unwire_ptp(pmap, va, m, free);
3809 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3815 vm_page_t pdpg, pdppg, pml4pg;
3817 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3820 * unmap the page table page
3822 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3824 MPASS(pmap_is_la57(pmap));
3825 pml5 = pmap_pml5e(pmap, va);
3827 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3828 pml5 = pmap_pml5e_u(pmap, va);
3831 } else if (m->pindex >= NUPDE + NUPDPE) {
3833 pml4 = pmap_pml4e(pmap, va);
3835 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3836 va <= VM_MAXUSER_ADDRESS) {
3837 pml4 = pmap_pml4e_u(pmap, va);
3840 } else if (m->pindex >= NUPDE) {
3842 pdp = pmap_pdpe(pmap, va);
3846 pd = pmap_pde(pmap, va);
3849 pmap_resident_count_dec(pmap, 1);
3850 if (m->pindex < NUPDE) {
3851 /* We just released a PT, unhold the matching PD */
3852 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3853 pmap_unwire_ptp(pmap, va, pdpg, free);
3854 } else if (m->pindex < NUPDE + NUPDPE) {
3855 /* We just released a PD, unhold the matching PDP */
3856 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3857 pmap_unwire_ptp(pmap, va, pdppg, free);
3858 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3859 /* We just released a PDP, unhold the matching PML4 */
3860 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3861 pmap_unwire_ptp(pmap, va, pml4pg, free);
3865 * Put page on a list so that it is released after
3866 * *ALL* TLB shootdown is done
3868 pmap_add_delayed_free_list(m, free, TRUE);
3872 * After removing a page table entry, this routine is used to
3873 * conditionally free the page, and manage the reference count.
3876 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3877 struct spglist *free)
3881 if (va >= VM_MAXUSER_ADDRESS)
3883 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3884 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3885 return (pmap_unwire_ptp(pmap, va, mpte, free));
3889 * Release a page table page reference after a failed attempt to create a
3893 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3895 struct spglist free;
3898 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3900 * Although "va" was never mapped, paging-structure caches
3901 * could nonetheless have entries that refer to the freed
3902 * page table pages. Invalidate those entries.
3904 pmap_invalidate_page(pmap, va);
3905 vm_page_free_pages_toq(&free, true);
3910 pmap_pinit0(pmap_t pmap)
3916 PMAP_LOCK_INIT(pmap);
3917 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3918 pmap->pm_pmltopu = NULL;
3919 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3920 /* hack to keep pmap_pti_pcid_invalidate() alive */
3921 pmap->pm_ucr3 = PMAP_NO_CR3;
3922 pmap->pm_root.rt_root = 0;
3923 CPU_ZERO(&pmap->pm_active);
3924 TAILQ_INIT(&pmap->pm_pvchunk);
3925 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3926 pmap->pm_flags = pmap_flags;
3928 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3929 pmap->pm_pcids[i].pm_gen = 1;
3931 pmap_activate_boot(pmap);
3936 p->p_md.md_flags |= P_MD_KPTI;
3939 pmap_thread_init_invl_gen(td);
3941 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3942 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3943 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3949 pmap_pinit_pml4(vm_page_t pml4pg)
3951 pml4_entry_t *pm_pml4;
3954 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3956 /* Wire in kernel global address entries. */
3957 for (i = 0; i < NKPML4E; i++) {
3958 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3961 for (i = 0; i < ndmpdpphys; i++) {
3962 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3966 /* install self-referential address mapping entry(s) */
3967 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3968 X86_PG_A | X86_PG_M;
3970 /* install large map entries if configured */
3971 for (i = 0; i < lm_ents; i++)
3972 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
3976 pmap_pinit_pml5(vm_page_t pml5pg)
3978 pml5_entry_t *pm_pml5;
3980 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
3983 * Add pml5 entry at top of KVA pointing to existing pml4 table,
3984 * entering all existing kernel mappings into level 5 table.
3986 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
3987 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
3988 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
3991 * Install self-referential address mapping entry.
3993 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
3994 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
3995 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
3999 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4001 pml4_entry_t *pm_pml4u;
4004 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4005 for (i = 0; i < NPML4EPG; i++)
4006 pm_pml4u[i] = pti_pml4[i];
4010 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4012 pml5_entry_t *pm_pml5u;
4014 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4017 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4018 * table, entering all kernel mappings needed for usermode
4019 * into level 5 table.
4021 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4022 pmap_kextract((vm_offset_t)pti_pml4) |
4023 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4024 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4028 * Initialize a preallocated and zeroed pmap structure,
4029 * such as one in a vmspace structure.
4032 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4034 vm_page_t pmltop_pg, pmltop_pgu;
4035 vm_paddr_t pmltop_phys;
4039 * allocate the page directory page
4041 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4042 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4044 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4045 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4048 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4049 pmap->pm_pcids[i].pm_gen = 0;
4051 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4052 pmap->pm_ucr3 = PMAP_NO_CR3;
4053 pmap->pm_pmltopu = NULL;
4055 pmap->pm_type = pm_type;
4056 if ((pmltop_pg->flags & PG_ZERO) == 0)
4057 pagezero(pmap->pm_pmltop);
4060 * Do not install the host kernel mappings in the nested page
4061 * tables. These mappings are meaningless in the guest physical
4063 * Install minimal kernel mappings in PTI case.
4065 if (pm_type == PT_X86) {
4066 pmap->pm_cr3 = pmltop_phys;
4067 if (pmap_is_la57(pmap))
4068 pmap_pinit_pml5(pmltop_pg);
4070 pmap_pinit_pml4(pmltop_pg);
4071 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4072 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4073 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4074 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4075 VM_PAGE_TO_PHYS(pmltop_pgu));
4076 if (pmap_is_la57(pmap))
4077 pmap_pinit_pml5_pti(pmltop_pgu);
4079 pmap_pinit_pml4_pti(pmltop_pgu);
4080 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4082 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4083 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4084 pkru_free_range, pmap, M_NOWAIT);
4088 pmap->pm_root.rt_root = 0;
4089 CPU_ZERO(&pmap->pm_active);
4090 TAILQ_INIT(&pmap->pm_pvchunk);
4091 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4092 pmap->pm_flags = flags;
4093 pmap->pm_eptgen = 0;
4099 pmap_pinit(pmap_t pmap)
4102 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4105 static pml4_entry_t *
4106 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4109 vm_pindex_t pml5index;
4116 if (!pmap_is_la57(pmap))
4117 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4119 PG_V = pmap_valid_bit(pmap);
4120 pml5index = pmap_pml5e_index(va);
4121 pml5 = &pmap->pm_pmltop[pml5index];
4122 if ((*pml5 & PG_V) == 0) {
4123 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4130 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4131 pml4 = &pml4[pmap_pml4e_index(va)];
4132 if ((*pml4 & PG_V) == 0) {
4133 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4134 if (allocated && !addref)
4135 pml4pg->ref_count--;
4136 else if (!allocated && addref)
4137 pml4pg->ref_count++;
4142 static pdp_entry_t *
4143 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4152 PG_V = pmap_valid_bit(pmap);
4154 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4158 if ((*pml4 & PG_V) == 0) {
4159 /* Have to allocate a new pdp, recurse */
4160 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4167 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4168 pdp = &pdp[pmap_pdpe_index(va)];
4169 if ((*pdp & PG_V) == 0) {
4170 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4171 if (allocated && !addref)
4173 else if (!allocated && addref)
4180 * This routine is called if the desired page table page does not exist.
4182 * If page table page allocation fails, this routine may sleep before
4183 * returning NULL. It sleeps only if a lock pointer was given.
4185 * Note: If a page allocation fails at page table level two, three, or four,
4186 * up to three pages may be held during the wait, only to be released
4187 * afterwards. This conservative approach is easily argued to avoid
4190 * The ptepindexes, i.e. page indices, of the page table pages encountered
4191 * while translating virtual address va are defined as follows:
4192 * - for the page table page (last level),
4193 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4194 * in other words, it is just the index of the PDE that maps the page
4196 * - for the page directory page,
4197 * ptepindex = NUPDE (number of userland PD entries) +
4198 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4199 * i.e. index of PDPE is put after the last index of PDE,
4200 * - for the page directory pointer page,
4201 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4203 * i.e. index of pml4e is put after the last index of PDPE,
4204 * - for the PML4 page (if LA57 mode is enabled),
4205 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4206 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4207 * i.e. index of pml5e is put after the last index of PML4E.
4209 * Define an order on the paging entries, where all entries of the
4210 * same height are put together, then heights are put from deepest to
4211 * root. Then ptexpindex is the sequential number of the
4212 * corresponding paging entry in this order.
4214 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4215 * LA57 paging structures even in LA48 paging mode. Moreover, the
4216 * ptepindexes are calculated as if the paging structures were 5-level
4217 * regardless of the actual mode of operation.
4219 * The root page at PML4/PML5 does not participate in this indexing scheme,
4220 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4223 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4224 vm_offset_t va __unused)
4226 vm_pindex_t pml5index, pml4index;
4227 pml5_entry_t *pml5, *pml5u;
4228 pml4_entry_t *pml4, *pml4u;
4232 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4234 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4236 PG_A = pmap_accessed_bit(pmap);
4237 PG_M = pmap_modified_bit(pmap);
4238 PG_V = pmap_valid_bit(pmap);
4239 PG_RW = pmap_rw_bit(pmap);
4242 * Allocate a page table page.
4244 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4245 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4246 if (lockp != NULL) {
4247 RELEASE_PV_LIST_LOCK(lockp);
4249 PMAP_ASSERT_NOT_IN_DI();
4255 * Indicate the need to retry. While waiting, the page table
4256 * page may have been allocated.
4260 if ((m->flags & PG_ZERO) == 0)
4264 * Map the pagetable page into the process address space, if
4265 * it isn't already there.
4267 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4268 MPASS(pmap_is_la57(pmap));
4270 pml5index = pmap_pml5e_index(va);
4271 pml5 = &pmap->pm_pmltop[pml5index];
4272 KASSERT((*pml5 & PG_V) == 0,
4273 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4274 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4276 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4277 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4280 pml5u = &pmap->pm_pmltopu[pml5index];
4281 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4284 } else if (ptepindex >= NUPDE + NUPDPE) {
4285 pml4index = pmap_pml4e_index(va);
4286 /* Wire up a new PDPE page */
4287 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4289 vm_page_unwire_noq(m);
4290 vm_page_free_zero(m);
4293 KASSERT((*pml4 & PG_V) == 0,
4294 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4295 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4297 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4298 pml4index < NUPML4E) {
4300 * PTI: Make all user-space mappings in the
4301 * kernel-mode page table no-execute so that
4302 * we detect any programming errors that leave
4303 * the kernel-mode page table active on return
4306 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4309 pml4u = &pmap->pm_pmltopu[pml4index];
4310 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4313 } else if (ptepindex >= NUPDE) {
4314 /* Wire up a new PDE page */
4315 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4317 vm_page_unwire_noq(m);
4318 vm_page_free_zero(m);
4321 KASSERT((*pdp & PG_V) == 0,
4322 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4323 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4325 /* Wire up a new PTE page */
4326 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4328 vm_page_unwire_noq(m);
4329 vm_page_free_zero(m);
4332 if ((*pdp & PG_V) == 0) {
4333 /* Have to allocate a new pd, recurse */
4334 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4335 lockp, va) == NULL) {
4336 vm_page_unwire_noq(m);
4337 vm_page_free_zero(m);
4341 /* Add reference to the pd page */
4342 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4345 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4347 /* Now we know where the page directory page is */
4348 pd = &pd[pmap_pde_index(va)];
4349 KASSERT((*pd & PG_V) == 0,
4350 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4351 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4354 pmap_resident_count_inc(pmap, 1);
4360 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4361 struct rwlock **lockp)
4363 pdp_entry_t *pdpe, PG_V;
4366 vm_pindex_t pdpindex;
4368 PG_V = pmap_valid_bit(pmap);
4371 pdpe = pmap_pdpe(pmap, va);
4372 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4373 pde = pmap_pdpe_to_pde(pdpe, va);
4374 if (va < VM_MAXUSER_ADDRESS) {
4375 /* Add a reference to the pd page. */
4376 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4380 } else if (va < VM_MAXUSER_ADDRESS) {
4381 /* Allocate a pd page. */
4382 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4383 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4390 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4391 pde = &pde[pmap_pde_index(va)];
4393 panic("pmap_alloc_pde: missing page table page for va %#lx",
4400 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4402 vm_pindex_t ptepindex;
4403 pd_entry_t *pd, PG_V;
4406 PG_V = pmap_valid_bit(pmap);
4409 * Calculate pagetable page index
4411 ptepindex = pmap_pde_pindex(va);
4414 * Get the page directory entry
4416 pd = pmap_pde(pmap, va);
4419 * This supports switching from a 2MB page to a
4422 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4423 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4425 * Invalidation of the 2MB page mapping may have caused
4426 * the deallocation of the underlying PD page.
4433 * If the page table page is mapped, we just increment the
4434 * hold count, and activate it.
4436 if (pd != NULL && (*pd & PG_V) != 0) {
4437 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4441 * Here if the pte page isn't mapped, or if it has been
4444 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4445 if (m == NULL && lockp != NULL)
4452 /***************************************************
4453 * Pmap allocation/deallocation routines.
4454 ***************************************************/
4457 * Release any resources held by the given physical map.
4458 * Called when a pmap initialized by pmap_pinit is being released.
4459 * Should only be called if the map contains no valid mappings.
4462 pmap_release(pmap_t pmap)
4467 KASSERT(pmap->pm_stats.resident_count == 0,
4468 ("pmap_release: pmap %p resident count %ld != 0",
4469 pmap, pmap->pm_stats.resident_count));
4470 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4471 ("pmap_release: pmap %p has reserved page table page(s)",
4473 KASSERT(CPU_EMPTY(&pmap->pm_active),
4474 ("releasing active pmap %p", pmap));
4476 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4478 if (pmap_is_la57(pmap)) {
4479 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4480 pmap->pm_pmltop[PML5PML5I] = 0;
4482 for (i = 0; i < NKPML4E; i++) /* KVA */
4483 pmap->pm_pmltop[KPML4BASE + i] = 0;
4484 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4485 pmap->pm_pmltop[DMPML4I + i] = 0;
4486 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4487 for (i = 0; i < lm_ents; i++) /* Large Map */
4488 pmap->pm_pmltop[LMSPML4I + i] = 0;
4491 vm_page_unwire_noq(m);
4492 vm_page_free_zero(m);
4494 if (pmap->pm_pmltopu != NULL) {
4495 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4497 vm_page_unwire_noq(m);
4500 if (pmap->pm_type == PT_X86 &&
4501 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4502 rangeset_fini(&pmap->pm_pkru);
4506 kvm_size(SYSCTL_HANDLER_ARGS)
4508 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4510 return sysctl_handle_long(oidp, &ksize, 0, req);
4512 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4513 0, 0, kvm_size, "LU",
4517 kvm_free(SYSCTL_HANDLER_ARGS)
4519 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4521 return sysctl_handle_long(oidp, &kfree, 0, req);
4523 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4524 0, 0, kvm_free, "LU",
4525 "Amount of KVM free");
4528 * Allocate physical memory for the vm_page array and map it into KVA,
4529 * attempting to back the vm_pages with domain-local memory.
4532 pmap_page_array_startup(long pages)
4535 pd_entry_t *pde, newpdir;
4536 vm_offset_t va, start, end;
4541 vm_page_array_size = pages;
4543 start = VM_MIN_KERNEL_ADDRESS;
4544 end = start + pages * sizeof(struct vm_page);
4545 for (va = start; va < end; va += NBPDR) {
4546 pfn = first_page + (va - start) / sizeof(struct vm_page);
4547 domain = _vm_phys_domain(ptoa(pfn));
4548 pdpe = pmap_pdpe(kernel_pmap, va);
4549 if ((*pdpe & X86_PG_V) == 0) {
4550 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4552 pagezero((void *)PHYS_TO_DMAP(pa));
4553 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4554 X86_PG_A | X86_PG_M);
4556 pde = pmap_pdpe_to_pde(pdpe, va);
4557 if ((*pde & X86_PG_V) != 0)
4558 panic("Unexpected pde");
4559 pa = vm_phys_early_alloc(domain, NBPDR);
4560 for (i = 0; i < NPDEPG; i++)
4561 dump_add_page(pa + i * PAGE_SIZE);
4562 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4563 X86_PG_M | PG_PS | pg_g | pg_nx);
4564 pde_store(pde, newpdir);
4566 vm_page_array = (vm_page_t)start;
4570 * grow the number of kernel page table entries, if needed
4573 pmap_growkernel(vm_offset_t addr)
4577 pd_entry_t *pde, newpdir;
4580 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4583 * Return if "addr" is within the range of kernel page table pages
4584 * that were preallocated during pmap bootstrap. Moreover, leave
4585 * "kernel_vm_end" and the kernel page table as they were.
4587 * The correctness of this action is based on the following
4588 * argument: vm_map_insert() allocates contiguous ranges of the
4589 * kernel virtual address space. It calls this function if a range
4590 * ends after "kernel_vm_end". If the kernel is mapped between
4591 * "kernel_vm_end" and "addr", then the range cannot begin at
4592 * "kernel_vm_end". In fact, its beginning address cannot be less
4593 * than the kernel. Thus, there is no immediate need to allocate
4594 * any new kernel page table pages between "kernel_vm_end" and
4597 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4600 addr = roundup2(addr, NBPDR);
4601 if (addr - 1 >= vm_map_max(kernel_map))
4602 addr = vm_map_max(kernel_map);
4603 while (kernel_vm_end < addr) {
4604 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4605 if ((*pdpe & X86_PG_V) == 0) {
4606 /* We need a new PDP entry */
4607 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4608 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4609 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4611 panic("pmap_growkernel: no memory to grow kernel");
4612 if ((nkpg->flags & PG_ZERO) == 0)
4613 pmap_zero_page(nkpg);
4614 paddr = VM_PAGE_TO_PHYS(nkpg);
4615 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4616 X86_PG_A | X86_PG_M);
4617 continue; /* try again */
4619 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4620 if ((*pde & X86_PG_V) != 0) {
4621 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4622 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4623 kernel_vm_end = vm_map_max(kernel_map);
4629 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4630 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4633 panic("pmap_growkernel: no memory to grow kernel");
4634 if ((nkpg->flags & PG_ZERO) == 0)
4635 pmap_zero_page(nkpg);
4636 paddr = VM_PAGE_TO_PHYS(nkpg);
4637 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4638 pde_store(pde, newpdir);
4640 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4641 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4642 kernel_vm_end = vm_map_max(kernel_map);
4649 /***************************************************
4650 * page management routines.
4651 ***************************************************/
4653 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4654 CTASSERT(_NPCM == 3);
4655 CTASSERT(_NPCPV == 168);
4657 static __inline struct pv_chunk *
4658 pv_to_chunk(pv_entry_t pv)
4661 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4664 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4666 #define PC_FREE0 0xfffffffffffffffful
4667 #define PC_FREE1 0xfffffffffffffffful
4668 #define PC_FREE2 0x000000fffffffffful
4670 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4673 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4675 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4676 "Current number of pv entry chunks");
4677 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4678 "Current number of pv entry chunks allocated");
4679 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4680 "Current number of pv entry chunks frees");
4681 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4682 "Number of times tried to get a chunk page but failed.");
4684 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4685 static int pv_entry_spare;
4687 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4688 "Current number of pv entry frees");
4689 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4690 "Current number of pv entry allocs");
4691 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4692 "Current number of pv entries");
4693 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4694 "Current number of spare pv entries");
4698 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4703 pmap_invalidate_all(pmap);
4704 if (pmap != locked_pmap)
4707 pmap_delayed_invl_finish();
4711 * We are in a serious low memory condition. Resort to
4712 * drastic measures to free some pages so we can allocate
4713 * another pv entry chunk.
4715 * Returns NULL if PV entries were reclaimed from the specified pmap.
4717 * We do not, however, unmap 2mpages because subsequent accesses will
4718 * allocate per-page pv entries until repromotion occurs, thereby
4719 * exacerbating the shortage of free pv entries.
4722 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4724 struct pv_chunks_list *pvc;
4725 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4726 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4727 struct md_page *pvh;
4729 pmap_t next_pmap, pmap;
4730 pt_entry_t *pte, tpte;
4731 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4735 struct spglist free;
4737 int bit, field, freed;
4738 bool start_di, restart;
4740 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4741 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4744 PG_G = PG_A = PG_M = PG_RW = 0;
4746 bzero(&pc_marker_b, sizeof(pc_marker_b));
4747 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4748 pc_marker = (struct pv_chunk *)&pc_marker_b;
4749 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4752 * A delayed invalidation block should already be active if
4753 * pmap_advise() or pmap_remove() called this function by way
4754 * of pmap_demote_pde_locked().
4756 start_di = pmap_not_in_di();
4758 pvc = &pv_chunks[domain];
4759 mtx_lock(&pvc->pvc_lock);
4760 pvc->active_reclaims++;
4761 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4762 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4763 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4764 SLIST_EMPTY(&free)) {
4765 next_pmap = pc->pc_pmap;
4766 if (next_pmap == NULL) {
4768 * The next chunk is a marker. However, it is
4769 * not our marker, so active_reclaims must be
4770 * > 1. Consequently, the next_chunk code
4771 * will not rotate the pv_chunks list.
4775 mtx_unlock(&pvc->pvc_lock);
4778 * A pv_chunk can only be removed from the pc_lru list
4779 * when both pc_chunks_mutex is owned and the
4780 * corresponding pmap is locked.
4782 if (pmap != next_pmap) {
4784 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4787 /* Avoid deadlock and lock recursion. */
4788 if (pmap > locked_pmap) {
4789 RELEASE_PV_LIST_LOCK(lockp);
4792 pmap_delayed_invl_start();
4793 mtx_lock(&pvc->pvc_lock);
4795 } else if (pmap != locked_pmap) {
4796 if (PMAP_TRYLOCK(pmap)) {
4798 pmap_delayed_invl_start();
4799 mtx_lock(&pvc->pvc_lock);
4802 pmap = NULL; /* pmap is not locked */
4803 mtx_lock(&pvc->pvc_lock);
4804 pc = TAILQ_NEXT(pc_marker, pc_lru);
4806 pc->pc_pmap != next_pmap)
4810 } else if (start_di)
4811 pmap_delayed_invl_start();
4812 PG_G = pmap_global_bit(pmap);
4813 PG_A = pmap_accessed_bit(pmap);
4814 PG_M = pmap_modified_bit(pmap);
4815 PG_RW = pmap_rw_bit(pmap);
4821 * Destroy every non-wired, 4 KB page mapping in the chunk.
4824 for (field = 0; field < _NPCM; field++) {
4825 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4826 inuse != 0; inuse &= ~(1UL << bit)) {
4828 pv = &pc->pc_pventry[field * 64 + bit];
4830 pde = pmap_pde(pmap, va);
4831 if ((*pde & PG_PS) != 0)
4833 pte = pmap_pde_to_pte(pde, va);
4834 if ((*pte & PG_W) != 0)
4836 tpte = pte_load_clear(pte);
4837 if ((tpte & PG_G) != 0)
4838 pmap_invalidate_page(pmap, va);
4839 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4840 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4842 if ((tpte & PG_A) != 0)
4843 vm_page_aflag_set(m, PGA_REFERENCED);
4844 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4845 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4847 if (TAILQ_EMPTY(&m->md.pv_list) &&
4848 (m->flags & PG_FICTITIOUS) == 0) {
4849 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4850 if (TAILQ_EMPTY(&pvh->pv_list)) {
4851 vm_page_aflag_clear(m,
4855 pmap_delayed_invl_page(m);
4856 pc->pc_map[field] |= 1UL << bit;
4857 pmap_unuse_pt(pmap, va, *pde, &free);
4862 mtx_lock(&pvc->pvc_lock);
4865 /* Every freed mapping is for a 4 KB page. */
4866 pmap_resident_count_dec(pmap, freed);
4867 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4868 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4869 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4870 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4871 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4872 pc->pc_map[2] == PC_FREE2) {
4873 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4874 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4875 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4876 /* Entire chunk is free; return it. */
4877 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4878 dump_drop_page(m_pc->phys_addr);
4879 mtx_lock(&pvc->pvc_lock);
4880 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4883 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4884 mtx_lock(&pvc->pvc_lock);
4885 /* One freed pv entry in locked_pmap is sufficient. */
4886 if (pmap == locked_pmap)
4889 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4890 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4891 if (pvc->active_reclaims == 1 && pmap != NULL) {
4893 * Rotate the pv chunks list so that we do not
4894 * scan the same pv chunks that could not be
4895 * freed (because they contained a wired
4896 * and/or superpage mapping) on every
4897 * invocation of reclaim_pv_chunk().
4899 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4900 MPASS(pc->pc_pmap != NULL);
4901 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4902 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4906 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4907 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4908 pvc->active_reclaims--;
4909 mtx_unlock(&pvc->pvc_lock);
4910 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4911 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4912 m_pc = SLIST_FIRST(&free);
4913 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4914 /* Recycle a freed page table page. */
4915 m_pc->ref_count = 1;
4917 vm_page_free_pages_toq(&free, true);
4922 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4927 domain = PCPU_GET(domain);
4928 for (i = 0; i < vm_ndomains; i++) {
4929 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4932 domain = (domain + 1) % vm_ndomains;
4939 * free the pv_entry back to the free list
4942 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4944 struct pv_chunk *pc;
4945 int idx, field, bit;
4947 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4948 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4949 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4950 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4951 pc = pv_to_chunk(pv);
4952 idx = pv - &pc->pc_pventry[0];
4955 pc->pc_map[field] |= 1ul << bit;
4956 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4957 pc->pc_map[2] != PC_FREE2) {
4958 /* 98% of the time, pc is already at the head of the list. */
4959 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
4960 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4961 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4965 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4970 free_pv_chunk_dequeued(struct pv_chunk *pc)
4974 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4975 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4976 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4977 /* entire chunk is free, return it */
4978 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4979 dump_drop_page(m->phys_addr);
4980 vm_page_unwire_noq(m);
4985 free_pv_chunk(struct pv_chunk *pc)
4987 struct pv_chunks_list *pvc;
4989 pvc = &pv_chunks[pc_to_domain(pc)];
4990 mtx_lock(&pvc->pvc_lock);
4991 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4992 mtx_unlock(&pvc->pvc_lock);
4993 free_pv_chunk_dequeued(pc);
4997 free_pv_chunk_batch(struct pv_chunklist *batch)
4999 struct pv_chunks_list *pvc;
5000 struct pv_chunk *pc, *npc;
5003 for (i = 0; i < vm_ndomains; i++) {
5004 if (TAILQ_EMPTY(&batch[i]))
5006 pvc = &pv_chunks[i];
5007 mtx_lock(&pvc->pvc_lock);
5008 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5009 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5011 mtx_unlock(&pvc->pvc_lock);
5014 for (i = 0; i < vm_ndomains; i++) {
5015 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5016 free_pv_chunk_dequeued(pc);
5022 * Returns a new PV entry, allocating a new PV chunk from the system when
5023 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5024 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5027 * The given PV list lock may be released.
5030 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5032 struct pv_chunks_list *pvc;
5035 struct pv_chunk *pc;
5038 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5039 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5041 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5043 for (field = 0; field < _NPCM; field++) {
5044 if (pc->pc_map[field]) {
5045 bit = bsfq(pc->pc_map[field]);
5049 if (field < _NPCM) {
5050 pv = &pc->pc_pventry[field * 64 + bit];
5051 pc->pc_map[field] &= ~(1ul << bit);
5052 /* If this was the last item, move it to tail */
5053 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5054 pc->pc_map[2] == 0) {
5055 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5056 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5059 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5060 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5064 /* No free items, allocate another chunk */
5065 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5068 if (lockp == NULL) {
5069 PV_STAT(pc_chunk_tryfail++);
5072 m = reclaim_pv_chunk(pmap, lockp);
5076 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5077 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5078 dump_add_page(m->phys_addr);
5079 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5081 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5082 pc->pc_map[1] = PC_FREE1;
5083 pc->pc_map[2] = PC_FREE2;
5084 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
5085 mtx_lock(&pvc->pvc_lock);
5086 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5087 mtx_unlock(&pvc->pvc_lock);
5088 pv = &pc->pc_pventry[0];
5089 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5090 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5091 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5096 * Returns the number of one bits within the given PV chunk map.
5098 * The erratas for Intel processors state that "POPCNT Instruction May
5099 * Take Longer to Execute Than Expected". It is believed that the
5100 * issue is the spurious dependency on the destination register.
5101 * Provide a hint to the register rename logic that the destination
5102 * value is overwritten, by clearing it, as suggested in the
5103 * optimization manual. It should be cheap for unaffected processors
5106 * Reference numbers for erratas are
5107 * 4th Gen Core: HSD146
5108 * 5th Gen Core: BDM85
5109 * 6th Gen Core: SKL029
5112 popcnt_pc_map_pq(uint64_t *map)
5116 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5117 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5118 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5119 : "=&r" (result), "=&r" (tmp)
5120 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5125 * Ensure that the number of spare PV entries in the specified pmap meets or
5126 * exceeds the given count, "needed".
5128 * The given PV list lock may be released.
5131 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5133 struct pv_chunks_list *pvc;
5134 struct pch new_tail[PMAP_MEMDOM];
5135 struct pv_chunk *pc;
5140 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5141 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5144 * Newly allocated PV chunks must be stored in a private list until
5145 * the required number of PV chunks have been allocated. Otherwise,
5146 * reclaim_pv_chunk() could recycle one of these chunks. In
5147 * contrast, these chunks must be added to the pmap upon allocation.
5149 for (i = 0; i < PMAP_MEMDOM; i++)
5150 TAILQ_INIT(&new_tail[i]);
5153 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5155 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5156 bit_count((bitstr_t *)pc->pc_map, 0,
5157 sizeof(pc->pc_map) * NBBY, &free);
5160 free = popcnt_pc_map_pq(pc->pc_map);
5164 if (avail >= needed)
5167 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5168 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5171 m = reclaim_pv_chunk(pmap, lockp);
5176 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5177 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5178 dump_add_page(m->phys_addr);
5179 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5181 pc->pc_map[0] = PC_FREE0;
5182 pc->pc_map[1] = PC_FREE1;
5183 pc->pc_map[2] = PC_FREE2;
5184 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5185 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5186 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5189 * The reclaim might have freed a chunk from the current pmap.
5190 * If that chunk contained available entries, we need to
5191 * re-count the number of available entries.
5196 for (i = 0; i < vm_ndomains; i++) {
5197 if (TAILQ_EMPTY(&new_tail[i]))
5199 pvc = &pv_chunks[i];
5200 mtx_lock(&pvc->pvc_lock);
5201 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5202 mtx_unlock(&pvc->pvc_lock);
5207 * First find and then remove the pv entry for the specified pmap and virtual
5208 * address from the specified pv list. Returns the pv entry if found and NULL
5209 * otherwise. This operation can be performed on pv lists for either 4KB or
5210 * 2MB page mappings.
5212 static __inline pv_entry_t
5213 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5217 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5218 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5219 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5228 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5229 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5230 * entries for each of the 4KB page mappings.
5233 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5234 struct rwlock **lockp)
5236 struct md_page *pvh;
5237 struct pv_chunk *pc;
5239 vm_offset_t va_last;
5243 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5244 KASSERT((pa & PDRMASK) == 0,
5245 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5246 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5249 * Transfer the 2mpage's pv entry for this mapping to the first
5250 * page's pv list. Once this transfer begins, the pv list lock
5251 * must not be released until the last pv entry is reinstantiated.
5253 pvh = pa_to_pvh(pa);
5254 va = trunc_2mpage(va);
5255 pv = pmap_pvh_remove(pvh, pmap, va);
5256 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5257 m = PHYS_TO_VM_PAGE(pa);
5258 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5260 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5261 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5262 va_last = va + NBPDR - PAGE_SIZE;
5264 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5265 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5266 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5267 for (field = 0; field < _NPCM; field++) {
5268 while (pc->pc_map[field]) {
5269 bit = bsfq(pc->pc_map[field]);
5270 pc->pc_map[field] &= ~(1ul << bit);
5271 pv = &pc->pc_pventry[field * 64 + bit];
5275 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5276 ("pmap_pv_demote_pde: page %p is not managed", m));
5277 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5283 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5284 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5287 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5288 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5289 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5291 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5292 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5295 #if VM_NRESERVLEVEL > 0
5297 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5298 * replace the many pv entries for the 4KB page mappings by a single pv entry
5299 * for the 2MB page mapping.
5302 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5303 struct rwlock **lockp)
5305 struct md_page *pvh;
5307 vm_offset_t va_last;
5310 KASSERT((pa & PDRMASK) == 0,
5311 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5312 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5315 * Transfer the first page's pv entry for this mapping to the 2mpage's
5316 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5317 * a transfer avoids the possibility that get_pv_entry() calls
5318 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5319 * mappings that is being promoted.
5321 m = PHYS_TO_VM_PAGE(pa);
5322 va = trunc_2mpage(va);
5323 pv = pmap_pvh_remove(&m->md, pmap, va);
5324 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5325 pvh = pa_to_pvh(pa);
5326 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5328 /* Free the remaining NPTEPG - 1 pv entries. */
5329 va_last = va + NBPDR - PAGE_SIZE;
5333 pmap_pvh_free(&m->md, pmap, va);
5334 } while (va < va_last);
5336 #endif /* VM_NRESERVLEVEL > 0 */
5339 * First find and then destroy the pv entry for the specified pmap and virtual
5340 * address. This operation can be performed on pv lists for either 4KB or 2MB
5344 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5348 pv = pmap_pvh_remove(pvh, pmap, va);
5349 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5350 free_pv_entry(pmap, pv);
5354 * Conditionally create the PV entry for a 4KB page mapping if the required
5355 * memory can be allocated without resorting to reclamation.
5358 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5359 struct rwlock **lockp)
5363 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5364 /* Pass NULL instead of the lock pointer to disable reclamation. */
5365 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5367 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5368 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5376 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5377 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5378 * false if the PV entry cannot be allocated without resorting to reclamation.
5381 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5382 struct rwlock **lockp)
5384 struct md_page *pvh;
5388 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5389 /* Pass NULL instead of the lock pointer to disable reclamation. */
5390 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5391 NULL : lockp)) == NULL)
5394 pa = pde & PG_PS_FRAME;
5395 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5396 pvh = pa_to_pvh(pa);
5397 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5403 * Fills a page table page with mappings to consecutive physical pages.
5406 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5410 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5412 newpte += PAGE_SIZE;
5417 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5418 * mapping is invalidated.
5421 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5423 struct rwlock *lock;
5427 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5434 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5438 pt_entry_t *xpte, *ypte;
5440 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5441 xpte++, newpte += PAGE_SIZE) {
5442 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5443 printf("pmap_demote_pde: xpte %zd and newpte map "
5444 "different pages: found %#lx, expected %#lx\n",
5445 xpte - firstpte, *xpte, newpte);
5446 printf("page table dump\n");
5447 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5448 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5453 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5454 ("pmap_demote_pde: firstpte and newpte map different physical"
5461 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5462 pd_entry_t oldpde, struct rwlock **lockp)
5464 struct spglist free;
5468 sva = trunc_2mpage(va);
5469 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5470 if ((oldpde & pmap_global_bit(pmap)) == 0)
5471 pmap_invalidate_pde_page(pmap, sva, oldpde);
5472 vm_page_free_pages_toq(&free, true);
5473 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5478 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5479 struct rwlock **lockp)
5481 pd_entry_t newpde, oldpde;
5482 pt_entry_t *firstpte, newpte;
5483 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5489 PG_A = pmap_accessed_bit(pmap);
5490 PG_G = pmap_global_bit(pmap);
5491 PG_M = pmap_modified_bit(pmap);
5492 PG_RW = pmap_rw_bit(pmap);
5493 PG_V = pmap_valid_bit(pmap);
5494 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5495 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5497 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5498 in_kernel = va >= VM_MAXUSER_ADDRESS;
5500 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5501 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5504 * Invalidate the 2MB page mapping and return "failure" if the
5505 * mapping was never accessed.
5507 if ((oldpde & PG_A) == 0) {
5508 KASSERT((oldpde & PG_W) == 0,
5509 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5510 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5514 mpte = pmap_remove_pt_page(pmap, va);
5516 KASSERT((oldpde & PG_W) == 0,
5517 ("pmap_demote_pde: page table page for a wired mapping"
5521 * If the page table page is missing and the mapping
5522 * is for a kernel address, the mapping must belong to
5523 * the direct map. Page table pages are preallocated
5524 * for every other part of the kernel address space,
5525 * so the direct map region is the only part of the
5526 * kernel address space that must be handled here.
5528 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5529 va < DMAP_MAX_ADDRESS),
5530 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5533 * If the 2MB page mapping belongs to the direct map
5534 * region of the kernel's address space, then the page
5535 * allocation request specifies the highest possible
5536 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5537 * priority is normal.
5539 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5540 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5541 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5544 * If the allocation of the new page table page fails,
5545 * invalidate the 2MB page mapping and return "failure".
5548 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5553 mpte->ref_count = NPTEPG;
5554 pmap_resident_count_inc(pmap, 1);
5557 mptepa = VM_PAGE_TO_PHYS(mpte);
5558 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5559 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5560 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5561 ("pmap_demote_pde: oldpde is missing PG_M"));
5562 newpte = oldpde & ~PG_PS;
5563 newpte = pmap_swap_pat(pmap, newpte);
5566 * If the page table page is not leftover from an earlier promotion,
5569 if (mpte->valid == 0)
5570 pmap_fill_ptp(firstpte, newpte);
5572 pmap_demote_pde_check(firstpte, newpte);
5575 * If the mapping has changed attributes, update the page table
5578 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5579 pmap_fill_ptp(firstpte, newpte);
5582 * The spare PV entries must be reserved prior to demoting the
5583 * mapping, that is, prior to changing the PDE. Otherwise, the state
5584 * of the PDE and the PV lists will be inconsistent, which can result
5585 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5586 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5587 * PV entry for the 2MB page mapping that is being demoted.
5589 if ((oldpde & PG_MANAGED) != 0)
5590 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5593 * Demote the mapping. This pmap is locked. The old PDE has
5594 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5595 * set. Thus, there is no danger of a race with another
5596 * processor changing the setting of PG_A and/or PG_M between
5597 * the read above and the store below.
5599 if (workaround_erratum383)
5600 pmap_update_pde(pmap, va, pde, newpde);
5602 pde_store(pde, newpde);
5605 * Invalidate a stale recursive mapping of the page table page.
5608 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5611 * Demote the PV entry.
5613 if ((oldpde & PG_MANAGED) != 0)
5614 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5616 atomic_add_long(&pmap_pde_demotions, 1);
5617 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5623 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5626 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5632 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5633 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5634 mpte = pmap_remove_pt_page(pmap, va);
5636 panic("pmap_remove_kernel_pde: Missing pt page.");
5638 mptepa = VM_PAGE_TO_PHYS(mpte);
5639 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5642 * If this page table page was unmapped by a promotion, then it
5643 * contains valid mappings. Zero it to invalidate those mappings.
5645 if (mpte->valid != 0)
5646 pagezero((void *)PHYS_TO_DMAP(mptepa));
5649 * Demote the mapping.
5651 if (workaround_erratum383)
5652 pmap_update_pde(pmap, va, pde, newpde);
5654 pde_store(pde, newpde);
5657 * Invalidate a stale recursive mapping of the page table page.
5659 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5663 * pmap_remove_pde: do the things to unmap a superpage in a process
5666 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5667 struct spglist *free, struct rwlock **lockp)
5669 struct md_page *pvh;
5671 vm_offset_t eva, va;
5673 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5675 PG_G = pmap_global_bit(pmap);
5676 PG_A = pmap_accessed_bit(pmap);
5677 PG_M = pmap_modified_bit(pmap);
5678 PG_RW = pmap_rw_bit(pmap);
5680 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5681 KASSERT((sva & PDRMASK) == 0,
5682 ("pmap_remove_pde: sva is not 2mpage aligned"));
5683 oldpde = pte_load_clear(pdq);
5685 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5686 if ((oldpde & PG_G) != 0)
5687 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5688 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5689 if (oldpde & PG_MANAGED) {
5690 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5691 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5692 pmap_pvh_free(pvh, pmap, sva);
5694 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5695 va < eva; va += PAGE_SIZE, m++) {
5696 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5699 vm_page_aflag_set(m, PGA_REFERENCED);
5700 if (TAILQ_EMPTY(&m->md.pv_list) &&
5701 TAILQ_EMPTY(&pvh->pv_list))
5702 vm_page_aflag_clear(m, PGA_WRITEABLE);
5703 pmap_delayed_invl_page(m);
5706 if (pmap == kernel_pmap) {
5707 pmap_remove_kernel_pde(pmap, pdq, sva);
5709 mpte = pmap_remove_pt_page(pmap, sva);
5711 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5712 ("pmap_remove_pde: pte page not promoted"));
5713 pmap_resident_count_dec(pmap, 1);
5714 KASSERT(mpte->ref_count == NPTEPG,
5715 ("pmap_remove_pde: pte page ref count error"));
5716 mpte->ref_count = 0;
5717 pmap_add_delayed_free_list(mpte, free, FALSE);
5720 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5724 * pmap_remove_pte: do the things to unmap a page in a process
5727 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5728 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5730 struct md_page *pvh;
5731 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5734 PG_A = pmap_accessed_bit(pmap);
5735 PG_M = pmap_modified_bit(pmap);
5736 PG_RW = pmap_rw_bit(pmap);
5738 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5739 oldpte = pte_load_clear(ptq);
5741 pmap->pm_stats.wired_count -= 1;
5742 pmap_resident_count_dec(pmap, 1);
5743 if (oldpte & PG_MANAGED) {
5744 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5745 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5748 vm_page_aflag_set(m, PGA_REFERENCED);
5749 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5750 pmap_pvh_free(&m->md, pmap, va);
5751 if (TAILQ_EMPTY(&m->md.pv_list) &&
5752 (m->flags & PG_FICTITIOUS) == 0) {
5753 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5754 if (TAILQ_EMPTY(&pvh->pv_list))
5755 vm_page_aflag_clear(m, PGA_WRITEABLE);
5757 pmap_delayed_invl_page(m);
5759 return (pmap_unuse_pt(pmap, va, ptepde, free));
5763 * Remove a single page from a process address space
5766 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5767 struct spglist *free)
5769 struct rwlock *lock;
5770 pt_entry_t *pte, PG_V;
5772 PG_V = pmap_valid_bit(pmap);
5773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5774 if ((*pde & PG_V) == 0)
5776 pte = pmap_pde_to_pte(pde, va);
5777 if ((*pte & PG_V) == 0)
5780 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5783 pmap_invalidate_page(pmap, va);
5787 * Removes the specified range of addresses from the page table page.
5790 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5791 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5793 pt_entry_t PG_G, *pte;
5797 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5798 PG_G = pmap_global_bit(pmap);
5801 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5805 pmap_invalidate_range(pmap, va, sva);
5810 if ((*pte & PG_G) == 0)
5814 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5820 pmap_invalidate_range(pmap, va, sva);
5825 * Remove the given range of addresses from the specified map.
5827 * It is assumed that the start and end are properly
5828 * rounded to the page size.
5831 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5833 struct rwlock *lock;
5834 vm_offset_t va_next;
5835 pml5_entry_t *pml5e;
5836 pml4_entry_t *pml4e;
5838 pd_entry_t ptpaddr, *pde;
5839 pt_entry_t PG_G, PG_V;
5840 struct spglist free;
5843 PG_G = pmap_global_bit(pmap);
5844 PG_V = pmap_valid_bit(pmap);
5847 * Perform an unsynchronized read. This is, however, safe.
5849 if (pmap->pm_stats.resident_count == 0)
5855 pmap_delayed_invl_start();
5857 pmap_pkru_on_remove(pmap, sva, eva);
5860 * special handling of removing one page. a very
5861 * common operation and easy to short circuit some
5864 if (sva + PAGE_SIZE == eva) {
5865 pde = pmap_pde(pmap, sva);
5866 if (pde && (*pde & PG_PS) == 0) {
5867 pmap_remove_page(pmap, sva, pde, &free);
5873 for (; sva < eva; sva = va_next) {
5875 if (pmap->pm_stats.resident_count == 0)
5878 if (pmap_is_la57(pmap)) {
5879 pml5e = pmap_pml5e(pmap, sva);
5880 if ((*pml5e & PG_V) == 0) {
5881 va_next = (sva + NBPML5) & ~PML5MASK;
5886 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5888 pml4e = pmap_pml4e(pmap, sva);
5890 if ((*pml4e & PG_V) == 0) {
5891 va_next = (sva + NBPML4) & ~PML4MASK;
5897 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5898 if ((*pdpe & PG_V) == 0) {
5899 va_next = (sva + NBPDP) & ~PDPMASK;
5906 * Calculate index for next page table.
5908 va_next = (sva + NBPDR) & ~PDRMASK;
5912 pde = pmap_pdpe_to_pde(pdpe, sva);
5916 * Weed out invalid mappings.
5922 * Check for large page.
5924 if ((ptpaddr & PG_PS) != 0) {
5926 * Are we removing the entire large page? If not,
5927 * demote the mapping and fall through.
5929 if (sva + NBPDR == va_next && eva >= va_next) {
5931 * The TLB entry for a PG_G mapping is
5932 * invalidated by pmap_remove_pde().
5934 if ((ptpaddr & PG_G) == 0)
5936 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5938 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5940 /* The large page mapping was destroyed. */
5947 * Limit our scan to either the end of the va represented
5948 * by the current page table page, or to the end of the
5949 * range being removed.
5954 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
5961 pmap_invalidate_all(pmap);
5963 pmap_delayed_invl_finish();
5964 vm_page_free_pages_toq(&free, true);
5968 * Routine: pmap_remove_all
5970 * Removes this physical page from
5971 * all physical maps in which it resides.
5972 * Reflects back modify bits to the pager.
5975 * Original versions of this routine were very
5976 * inefficient because they iteratively called
5977 * pmap_remove (slow...)
5981 pmap_remove_all(vm_page_t m)
5983 struct md_page *pvh;
5986 struct rwlock *lock;
5987 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
5990 struct spglist free;
5991 int pvh_gen, md_gen;
5993 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5994 ("pmap_remove_all: page %p is not managed", m));
5996 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
5997 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
5998 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6001 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6003 if (!PMAP_TRYLOCK(pmap)) {
6004 pvh_gen = pvh->pv_gen;
6008 if (pvh_gen != pvh->pv_gen) {
6015 pde = pmap_pde(pmap, va);
6016 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6019 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6021 if (!PMAP_TRYLOCK(pmap)) {
6022 pvh_gen = pvh->pv_gen;
6023 md_gen = m->md.pv_gen;
6027 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6033 PG_A = pmap_accessed_bit(pmap);
6034 PG_M = pmap_modified_bit(pmap);
6035 PG_RW = pmap_rw_bit(pmap);
6036 pmap_resident_count_dec(pmap, 1);
6037 pde = pmap_pde(pmap, pv->pv_va);
6038 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6039 " a 2mpage in page %p's pv list", m));
6040 pte = pmap_pde_to_pte(pde, pv->pv_va);
6041 tpte = pte_load_clear(pte);
6043 pmap->pm_stats.wired_count--;
6045 vm_page_aflag_set(m, PGA_REFERENCED);
6048 * Update the vm_page_t clean and reference bits.
6050 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6052 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6053 pmap_invalidate_page(pmap, pv->pv_va);
6054 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6056 free_pv_entry(pmap, pv);
6059 vm_page_aflag_clear(m, PGA_WRITEABLE);
6061 pmap_delayed_invl_wait(m);
6062 vm_page_free_pages_toq(&free, true);
6066 * pmap_protect_pde: do the things to protect a 2mpage in a process
6069 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6071 pd_entry_t newpde, oldpde;
6073 boolean_t anychanged;
6074 pt_entry_t PG_G, PG_M, PG_RW;
6076 PG_G = pmap_global_bit(pmap);
6077 PG_M = pmap_modified_bit(pmap);
6078 PG_RW = pmap_rw_bit(pmap);
6080 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6081 KASSERT((sva & PDRMASK) == 0,
6082 ("pmap_protect_pde: sva is not 2mpage aligned"));
6085 oldpde = newpde = *pde;
6086 if ((prot & VM_PROT_WRITE) == 0) {
6087 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6088 (PG_MANAGED | PG_M | PG_RW)) {
6089 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6090 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6093 newpde &= ~(PG_RW | PG_M);
6095 if ((prot & VM_PROT_EXECUTE) == 0)
6097 if (newpde != oldpde) {
6099 * As an optimization to future operations on this PDE, clear
6100 * PG_PROMOTED. The impending invalidation will remove any
6101 * lingering 4KB page mappings from the TLB.
6103 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6105 if ((oldpde & PG_G) != 0)
6106 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6110 return (anychanged);
6114 * Set the physical protection on the
6115 * specified range of this map as requested.
6118 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6120 vm_offset_t va_next;
6121 pml4_entry_t *pml4e;
6123 pd_entry_t ptpaddr, *pde;
6124 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6125 boolean_t anychanged;
6127 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6128 if (prot == VM_PROT_NONE) {
6129 pmap_remove(pmap, sva, eva);
6133 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6134 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6137 PG_G = pmap_global_bit(pmap);
6138 PG_M = pmap_modified_bit(pmap);
6139 PG_V = pmap_valid_bit(pmap);
6140 PG_RW = pmap_rw_bit(pmap);
6144 * Although this function delays and batches the invalidation
6145 * of stale TLB entries, it does not need to call
6146 * pmap_delayed_invl_start() and
6147 * pmap_delayed_invl_finish(), because it does not
6148 * ordinarily destroy mappings. Stale TLB entries from
6149 * protection-only changes need only be invalidated before the
6150 * pmap lock is released, because protection-only changes do
6151 * not destroy PV entries. Even operations that iterate over
6152 * a physical page's PV list of mappings, like
6153 * pmap_remove_write(), acquire the pmap lock for each
6154 * mapping. Consequently, for protection-only changes, the
6155 * pmap lock suffices to synchronize both page table and TLB
6158 * This function only destroys a mapping if pmap_demote_pde()
6159 * fails. In that case, stale TLB entries are immediately
6164 for (; sva < eva; sva = va_next) {
6166 pml4e = pmap_pml4e(pmap, sva);
6167 if ((*pml4e & PG_V) == 0) {
6168 va_next = (sva + NBPML4) & ~PML4MASK;
6174 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6175 if ((*pdpe & PG_V) == 0) {
6176 va_next = (sva + NBPDP) & ~PDPMASK;
6182 va_next = (sva + NBPDR) & ~PDRMASK;
6186 pde = pmap_pdpe_to_pde(pdpe, sva);
6190 * Weed out invalid mappings.
6196 * Check for large page.
6198 if ((ptpaddr & PG_PS) != 0) {
6200 * Are we protecting the entire large page? If not,
6201 * demote the mapping and fall through.
6203 if (sva + NBPDR == va_next && eva >= va_next) {
6205 * The TLB entry for a PG_G mapping is
6206 * invalidated by pmap_protect_pde().
6208 if (pmap_protect_pde(pmap, pde, sva, prot))
6211 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6213 * The large page mapping was destroyed.
6222 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6224 pt_entry_t obits, pbits;
6228 obits = pbits = *pte;
6229 if ((pbits & PG_V) == 0)
6232 if ((prot & VM_PROT_WRITE) == 0) {
6233 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6234 (PG_MANAGED | PG_M | PG_RW)) {
6235 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6238 pbits &= ~(PG_RW | PG_M);
6240 if ((prot & VM_PROT_EXECUTE) == 0)
6243 if (pbits != obits) {
6244 if (!atomic_cmpset_long(pte, obits, pbits))
6247 pmap_invalidate_page(pmap, sva);
6254 pmap_invalidate_all(pmap);
6258 #if VM_NRESERVLEVEL > 0
6260 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6263 if (pmap->pm_type != PT_EPT)
6265 return ((pde & EPT_PG_EXECUTE) != 0);
6269 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6270 * single page table page (PTP) to a single 2MB page mapping. For promotion
6271 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6272 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6273 * identical characteristics.
6276 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6277 struct rwlock **lockp)
6280 pt_entry_t *firstpte, oldpte, pa, *pte;
6281 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6285 PG_A = pmap_accessed_bit(pmap);
6286 PG_G = pmap_global_bit(pmap);
6287 PG_M = pmap_modified_bit(pmap);
6288 PG_V = pmap_valid_bit(pmap);
6289 PG_RW = pmap_rw_bit(pmap);
6290 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6291 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6293 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6296 * Examine the first PTE in the specified PTP. Abort if this PTE is
6297 * either invalid, unused, or does not map the first 4KB physical page
6298 * within a 2MB page.
6300 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6303 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6304 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6306 atomic_add_long(&pmap_pde_p_failures, 1);
6307 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6308 " in pmap %p", va, pmap);
6311 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6313 * When PG_M is already clear, PG_RW can be cleared without
6314 * a TLB invalidation.
6316 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6322 * Examine each of the other PTEs in the specified PTP. Abort if this
6323 * PTE maps an unexpected 4KB physical page or does not have identical
6324 * characteristics to the first PTE.
6326 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6327 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6330 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6331 atomic_add_long(&pmap_pde_p_failures, 1);
6332 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6333 " in pmap %p", va, pmap);
6336 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6338 * When PG_M is already clear, PG_RW can be cleared
6339 * without a TLB invalidation.
6341 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6344 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6345 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6346 (va & ~PDRMASK), pmap);
6348 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6349 atomic_add_long(&pmap_pde_p_failures, 1);
6350 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6351 " in pmap %p", va, pmap);
6358 * Save the page table page in its current state until the PDE
6359 * mapping the superpage is demoted by pmap_demote_pde() or
6360 * destroyed by pmap_remove_pde().
6362 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6363 KASSERT(mpte >= vm_page_array &&
6364 mpte < &vm_page_array[vm_page_array_size],
6365 ("pmap_promote_pde: page table page is out of range"));
6366 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6367 ("pmap_promote_pde: page table page's pindex is wrong"));
6368 if (pmap_insert_pt_page(pmap, mpte, true)) {
6369 atomic_add_long(&pmap_pde_p_failures, 1);
6371 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6377 * Promote the pv entries.
6379 if ((newpde & PG_MANAGED) != 0)
6380 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6383 * Propagate the PAT index to its proper position.
6385 newpde = pmap_swap_pat(pmap, newpde);
6388 * Map the superpage.
6390 if (workaround_erratum383)
6391 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6393 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6395 atomic_add_long(&pmap_pde_promotions, 1);
6396 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6397 " in pmap %p", va, pmap);
6399 #endif /* VM_NRESERVLEVEL > 0 */
6402 * Insert the given physical page (p) at
6403 * the specified virtual address (v) in the
6404 * target physical map with the protection requested.
6406 * If specified, the page will be wired down, meaning
6407 * that the related pte can not be reclaimed.
6409 * NB: This is the only routine which MAY NOT lazy-evaluate
6410 * or lose information. That is, this routine must actually
6411 * insert this page into the given map NOW.
6413 * When destroying both a page table and PV entry, this function
6414 * performs the TLB invalidation before releasing the PV list
6415 * lock, so we do not need pmap_delayed_invl_page() calls here.
6418 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6419 u_int flags, int8_t psind)
6421 struct rwlock *lock;
6423 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6424 pt_entry_t newpte, origpte;
6431 PG_A = pmap_accessed_bit(pmap);
6432 PG_G = pmap_global_bit(pmap);
6433 PG_M = pmap_modified_bit(pmap);
6434 PG_V = pmap_valid_bit(pmap);
6435 PG_RW = pmap_rw_bit(pmap);
6437 va = trunc_page(va);
6438 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6439 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6440 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6442 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6443 va >= kmi.clean_eva,
6444 ("pmap_enter: managed mapping within the clean submap"));
6445 if ((m->oflags & VPO_UNMANAGED) == 0)
6446 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6447 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6448 ("pmap_enter: flags %u has reserved bits set", flags));
6449 pa = VM_PAGE_TO_PHYS(m);
6450 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6451 if ((flags & VM_PROT_WRITE) != 0)
6453 if ((prot & VM_PROT_WRITE) != 0)
6455 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6456 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6457 if ((prot & VM_PROT_EXECUTE) == 0)
6459 if ((flags & PMAP_ENTER_WIRED) != 0)
6461 if (va < VM_MAXUSER_ADDRESS)
6463 if (pmap == kernel_pmap)
6465 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6468 * Set modified bit gratuitously for writeable mappings if
6469 * the page is unmanaged. We do not want to take a fault
6470 * to do the dirty bit accounting for these mappings.
6472 if ((m->oflags & VPO_UNMANAGED) != 0) {
6473 if ((newpte & PG_RW) != 0)
6476 newpte |= PG_MANAGED;
6481 /* Assert the required virtual and physical alignment. */
6482 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6483 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6484 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6490 * In the case that a page table page is not
6491 * resident, we are creating it here.
6494 pde = pmap_pde(pmap, va);
6495 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6496 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6497 pte = pmap_pde_to_pte(pde, va);
6498 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6499 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6502 } else if (va < VM_MAXUSER_ADDRESS) {
6504 * Here if the pte page isn't mapped, or if it has been
6507 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6508 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6509 nosleep ? NULL : &lock, va);
6510 if (mpte == NULL && nosleep) {
6511 rv = KERN_RESOURCE_SHORTAGE;
6516 panic("pmap_enter: invalid page directory va=%#lx", va);
6520 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6521 newpte |= pmap_pkru_get(pmap, va);
6524 * Is the specified virtual address already mapped?
6526 if ((origpte & PG_V) != 0) {
6528 * Wiring change, just update stats. We don't worry about
6529 * wiring PT pages as they remain resident as long as there
6530 * are valid mappings in them. Hence, if a user page is wired,
6531 * the PT page will be also.
6533 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6534 pmap->pm_stats.wired_count++;
6535 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6536 pmap->pm_stats.wired_count--;
6539 * Remove the extra PT page reference.
6543 KASSERT(mpte->ref_count > 0,
6544 ("pmap_enter: missing reference to page table page,"
6549 * Has the physical page changed?
6551 opa = origpte & PG_FRAME;
6554 * No, might be a protection or wiring change.
6556 if ((origpte & PG_MANAGED) != 0 &&
6557 (newpte & PG_RW) != 0)
6558 vm_page_aflag_set(m, PGA_WRITEABLE);
6559 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6565 * The physical page has changed. Temporarily invalidate
6566 * the mapping. This ensures that all threads sharing the
6567 * pmap keep a consistent view of the mapping, which is
6568 * necessary for the correct handling of COW faults. It
6569 * also permits reuse of the old mapping's PV entry,
6570 * avoiding an allocation.
6572 * For consistency, handle unmanaged mappings the same way.
6574 origpte = pte_load_clear(pte);
6575 KASSERT((origpte & PG_FRAME) == opa,
6576 ("pmap_enter: unexpected pa update for %#lx", va));
6577 if ((origpte & PG_MANAGED) != 0) {
6578 om = PHYS_TO_VM_PAGE(opa);
6581 * The pmap lock is sufficient to synchronize with
6582 * concurrent calls to pmap_page_test_mappings() and
6583 * pmap_ts_referenced().
6585 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6587 if ((origpte & PG_A) != 0) {
6588 pmap_invalidate_page(pmap, va);
6589 vm_page_aflag_set(om, PGA_REFERENCED);
6591 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6592 pv = pmap_pvh_remove(&om->md, pmap, va);
6594 ("pmap_enter: no PV entry for %#lx", va));
6595 if ((newpte & PG_MANAGED) == 0)
6596 free_pv_entry(pmap, pv);
6597 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6598 TAILQ_EMPTY(&om->md.pv_list) &&
6599 ((om->flags & PG_FICTITIOUS) != 0 ||
6600 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6601 vm_page_aflag_clear(om, PGA_WRITEABLE);
6604 * Since this mapping is unmanaged, assume that PG_A
6607 pmap_invalidate_page(pmap, va);
6612 * Increment the counters.
6614 if ((newpte & PG_W) != 0)
6615 pmap->pm_stats.wired_count++;
6616 pmap_resident_count_inc(pmap, 1);
6620 * Enter on the PV list if part of our managed memory.
6622 if ((newpte & PG_MANAGED) != 0) {
6624 pv = get_pv_entry(pmap, &lock);
6627 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6628 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6630 if ((newpte & PG_RW) != 0)
6631 vm_page_aflag_set(m, PGA_WRITEABLE);
6637 if ((origpte & PG_V) != 0) {
6639 origpte = pte_load_store(pte, newpte);
6640 KASSERT((origpte & PG_FRAME) == pa,
6641 ("pmap_enter: unexpected pa update for %#lx", va));
6642 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6644 if ((origpte & PG_MANAGED) != 0)
6648 * Although the PTE may still have PG_RW set, TLB
6649 * invalidation may nonetheless be required because
6650 * the PTE no longer has PG_M set.
6652 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6654 * This PTE change does not require TLB invalidation.
6658 if ((origpte & PG_A) != 0)
6659 pmap_invalidate_page(pmap, va);
6661 pte_store(pte, newpte);
6665 #if VM_NRESERVLEVEL > 0
6667 * If both the page table page and the reservation are fully
6668 * populated, then attempt promotion.
6670 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6671 pmap_ps_enabled(pmap) &&
6672 (m->flags & PG_FICTITIOUS) == 0 &&
6673 vm_reserv_level_iffullpop(m) == 0)
6674 pmap_promote_pde(pmap, pde, va, &lock);
6686 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6687 * if successful. Returns false if (1) a page table page cannot be allocated
6688 * without sleeping, (2) a mapping already exists at the specified virtual
6689 * address, or (3) a PV entry cannot be allocated without reclaiming another
6693 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6694 struct rwlock **lockp)
6699 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6700 PG_V = pmap_valid_bit(pmap);
6701 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6703 if ((m->oflags & VPO_UNMANAGED) == 0)
6704 newpde |= PG_MANAGED;
6705 if ((prot & VM_PROT_EXECUTE) == 0)
6707 if (va < VM_MAXUSER_ADDRESS)
6709 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6710 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6715 * Returns true if every page table entry in the specified page table page is
6719 pmap_every_pte_zero(vm_paddr_t pa)
6721 pt_entry_t *pt_end, *pte;
6723 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6724 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6725 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6733 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6734 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6735 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6736 * a mapping already exists at the specified virtual address. Returns
6737 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6738 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6739 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6741 * The parameter "m" is only used when creating a managed, writeable mapping.
6744 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6745 vm_page_t m, struct rwlock **lockp)
6747 struct spglist free;
6748 pd_entry_t oldpde, *pde;
6749 pt_entry_t PG_G, PG_RW, PG_V;
6752 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6753 ("pmap_enter_pde: cannot create wired user mapping"));
6754 PG_G = pmap_global_bit(pmap);
6755 PG_RW = pmap_rw_bit(pmap);
6756 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6757 ("pmap_enter_pde: newpde is missing PG_M"));
6758 PG_V = pmap_valid_bit(pmap);
6759 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6761 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6763 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6764 " in pmap %p", va, pmap);
6765 return (KERN_FAILURE);
6767 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6768 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6769 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6770 " in pmap %p", va, pmap);
6771 return (KERN_RESOURCE_SHORTAGE);
6775 * If pkru is not same for the whole pde range, return failure
6776 * and let vm_fault() cope. Check after pde allocation, since
6779 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6780 pmap_abort_ptp(pmap, va, pdpg);
6781 return (KERN_FAILURE);
6783 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6784 newpde &= ~X86_PG_PKU_MASK;
6785 newpde |= pmap_pkru_get(pmap, va);
6789 * If there are existing mappings, either abort or remove them.
6792 if ((oldpde & PG_V) != 0) {
6793 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6794 ("pmap_enter_pde: pdpg's reference count is too low"));
6795 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6796 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6797 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6800 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6801 " in pmap %p", va, pmap);
6802 return (KERN_FAILURE);
6804 /* Break the existing mapping(s). */
6806 if ((oldpde & PG_PS) != 0) {
6808 * The reference to the PD page that was acquired by
6809 * pmap_alloc_pde() ensures that it won't be freed.
6810 * However, if the PDE resulted from a promotion, then
6811 * a reserved PT page could be freed.
6813 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6814 if ((oldpde & PG_G) == 0)
6815 pmap_invalidate_pde_page(pmap, va, oldpde);
6817 pmap_delayed_invl_start();
6818 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6820 pmap_invalidate_all(pmap);
6821 pmap_delayed_invl_finish();
6823 if (va < VM_MAXUSER_ADDRESS) {
6824 vm_page_free_pages_toq(&free, true);
6825 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
6828 KASSERT(SLIST_EMPTY(&free),
6829 ("pmap_enter_pde: freed kernel page table page"));
6832 * Both pmap_remove_pde() and pmap_remove_ptes() will
6833 * leave the kernel page table page zero filled.
6835 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6836 if (pmap_insert_pt_page(pmap, mt, false))
6837 panic("pmap_enter_pde: trie insert failed");
6841 if ((newpde & PG_MANAGED) != 0) {
6843 * Abort this mapping if its PV entry could not be created.
6845 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
6847 pmap_abort_ptp(pmap, va, pdpg);
6848 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6849 " in pmap %p", va, pmap);
6850 return (KERN_RESOURCE_SHORTAGE);
6852 if ((newpde & PG_RW) != 0) {
6853 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6854 vm_page_aflag_set(mt, PGA_WRITEABLE);
6859 * Increment counters.
6861 if ((newpde & PG_W) != 0)
6862 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
6863 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
6866 * Map the superpage. (This is not a promoted mapping; there will not
6867 * be any lingering 4KB page mappings in the TLB.)
6869 pde_store(pde, newpde);
6871 atomic_add_long(&pmap_pde_mappings, 1);
6872 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
6874 return (KERN_SUCCESS);
6878 * Maps a sequence of resident pages belonging to the same object.
6879 * The sequence begins with the given page m_start. This page is
6880 * mapped at the given virtual address start. Each subsequent page is
6881 * mapped at a virtual address that is offset from start by the same
6882 * amount as the page is offset from m_start within the object. The
6883 * last page in the sequence is the page with the largest offset from
6884 * m_start that can be mapped at a virtual address less than the given
6885 * virtual address end. Not every virtual page between start and end
6886 * is mapped; only those for which a resident page exists with the
6887 * corresponding offset from m_start are mapped.
6890 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
6891 vm_page_t m_start, vm_prot_t prot)
6893 struct rwlock *lock;
6896 vm_pindex_t diff, psize;
6898 VM_OBJECT_ASSERT_LOCKED(m_start->object);
6900 psize = atop(end - start);
6905 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
6906 va = start + ptoa(diff);
6907 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
6908 m->psind == 1 && pmap_ps_enabled(pmap) &&
6909 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
6910 pmap_enter_2mpage(pmap, va, m, prot, &lock))
6911 m = &m[NBPDR / PAGE_SIZE - 1];
6913 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
6915 m = TAILQ_NEXT(m, listq);
6923 * this code makes some *MAJOR* assumptions:
6924 * 1. Current pmap & pmap exists.
6927 * 4. No page table pages.
6928 * but is *MUCH* faster than pmap_enter...
6932 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
6934 struct rwlock *lock;
6938 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
6945 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
6946 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
6948 pt_entry_t newpte, *pte, PG_V;
6950 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
6951 (m->oflags & VPO_UNMANAGED) != 0,
6952 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
6953 PG_V = pmap_valid_bit(pmap);
6954 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6957 * In the case that a page table page is not
6958 * resident, we are creating it here.
6960 if (va < VM_MAXUSER_ADDRESS) {
6961 vm_pindex_t ptepindex;
6965 * Calculate pagetable page index
6967 ptepindex = pmap_pde_pindex(va);
6968 if (mpte && (mpte->pindex == ptepindex)) {
6972 * Get the page directory entry
6974 ptepa = pmap_pde(pmap, va);
6977 * If the page table page is mapped, we just increment
6978 * the hold count, and activate it. Otherwise, we
6979 * attempt to allocate a page table page. If this
6980 * attempt fails, we don't retry. Instead, we give up.
6982 if (ptepa && (*ptepa & PG_V) != 0) {
6985 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
6989 * Pass NULL instead of the PV list lock
6990 * pointer, because we don't intend to sleep.
6992 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
6998 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
6999 pte = &pte[pmap_pte_index(va)];
7011 * Enter on the PV list if part of our managed memory.
7013 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7014 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7016 pmap_abort_ptp(pmap, va, mpte);
7021 * Increment counters
7023 pmap_resident_count_inc(pmap, 1);
7025 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7026 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7027 if ((m->oflags & VPO_UNMANAGED) == 0)
7028 newpte |= PG_MANAGED;
7029 if ((prot & VM_PROT_EXECUTE) == 0)
7031 if (va < VM_MAXUSER_ADDRESS)
7032 newpte |= PG_U | pmap_pkru_get(pmap, va);
7033 pte_store(pte, newpte);
7038 * Make a temporary mapping for a physical address. This is only intended
7039 * to be used for panic dumps.
7042 pmap_kenter_temporary(vm_paddr_t pa, int i)
7046 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7047 pmap_kenter(va, pa);
7049 return ((void *)crashdumpmap);
7053 * This code maps large physical mmap regions into the
7054 * processor address space. Note that some shortcuts
7055 * are taken, but the code works.
7058 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7059 vm_pindex_t pindex, vm_size_t size)
7062 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7063 vm_paddr_t pa, ptepa;
7067 PG_A = pmap_accessed_bit(pmap);
7068 PG_M = pmap_modified_bit(pmap);
7069 PG_V = pmap_valid_bit(pmap);
7070 PG_RW = pmap_rw_bit(pmap);
7072 VM_OBJECT_ASSERT_WLOCKED(object);
7073 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7074 ("pmap_object_init_pt: non-device object"));
7075 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7076 if (!pmap_ps_enabled(pmap))
7078 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7080 p = vm_page_lookup(object, pindex);
7081 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7082 ("pmap_object_init_pt: invalid page %p", p));
7083 pat_mode = p->md.pat_mode;
7086 * Abort the mapping if the first page is not physically
7087 * aligned to a 2MB page boundary.
7089 ptepa = VM_PAGE_TO_PHYS(p);
7090 if (ptepa & (NBPDR - 1))
7094 * Skip the first page. Abort the mapping if the rest of
7095 * the pages are not physically contiguous or have differing
7096 * memory attributes.
7098 p = TAILQ_NEXT(p, listq);
7099 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7101 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7102 ("pmap_object_init_pt: invalid page %p", p));
7103 if (pa != VM_PAGE_TO_PHYS(p) ||
7104 pat_mode != p->md.pat_mode)
7106 p = TAILQ_NEXT(p, listq);
7110 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7111 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7112 * will not affect the termination of this loop.
7115 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7116 pa < ptepa + size; pa += NBPDR) {
7117 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7120 * The creation of mappings below is only an
7121 * optimization. If a page directory page
7122 * cannot be allocated without blocking,
7123 * continue on to the next mapping rather than
7129 if ((*pde & PG_V) == 0) {
7130 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7131 PG_U | PG_RW | PG_V);
7132 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7133 atomic_add_long(&pmap_pde_mappings, 1);
7135 /* Continue on if the PDE is already valid. */
7137 KASSERT(pdpg->ref_count > 0,
7138 ("pmap_object_init_pt: missing reference "
7139 "to page directory page, va: 0x%lx", addr));
7148 * Clear the wired attribute from the mappings for the specified range of
7149 * addresses in the given pmap. Every valid mapping within that range
7150 * must have the wired attribute set. In contrast, invalid mappings
7151 * cannot have the wired attribute set, so they are ignored.
7153 * The wired attribute of the page table entry is not a hardware
7154 * feature, so there is no need to invalidate any TLB entries.
7155 * Since pmap_demote_pde() for the wired entry must never fail,
7156 * pmap_delayed_invl_start()/finish() calls around the
7157 * function are not needed.
7160 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7162 vm_offset_t va_next;
7163 pml4_entry_t *pml4e;
7166 pt_entry_t *pte, PG_V;
7168 PG_V = pmap_valid_bit(pmap);
7170 for (; sva < eva; sva = va_next) {
7171 pml4e = pmap_pml4e(pmap, sva);
7172 if ((*pml4e & PG_V) == 0) {
7173 va_next = (sva + NBPML4) & ~PML4MASK;
7178 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7179 if ((*pdpe & PG_V) == 0) {
7180 va_next = (sva + NBPDP) & ~PDPMASK;
7185 va_next = (sva + NBPDR) & ~PDRMASK;
7188 pde = pmap_pdpe_to_pde(pdpe, sva);
7189 if ((*pde & PG_V) == 0)
7191 if ((*pde & PG_PS) != 0) {
7192 if ((*pde & PG_W) == 0)
7193 panic("pmap_unwire: pde %#jx is missing PG_W",
7197 * Are we unwiring the entire large page? If not,
7198 * demote the mapping and fall through.
7200 if (sva + NBPDR == va_next && eva >= va_next) {
7201 atomic_clear_long(pde, PG_W);
7202 pmap->pm_stats.wired_count -= NBPDR /
7205 } else if (!pmap_demote_pde(pmap, pde, sva))
7206 panic("pmap_unwire: demotion failed");
7210 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7212 if ((*pte & PG_V) == 0)
7214 if ((*pte & PG_W) == 0)
7215 panic("pmap_unwire: pte %#jx is missing PG_W",
7219 * PG_W must be cleared atomically. Although the pmap
7220 * lock synchronizes access to PG_W, another processor
7221 * could be setting PG_M and/or PG_A concurrently.
7223 atomic_clear_long(pte, PG_W);
7224 pmap->pm_stats.wired_count--;
7231 * Copy the range specified by src_addr/len
7232 * from the source map to the range dst_addr/len
7233 * in the destination map.
7235 * This routine is only advisory and need not do anything.
7238 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7239 vm_offset_t src_addr)
7241 struct rwlock *lock;
7242 pml4_entry_t *pml4e;
7244 pd_entry_t *pde, srcptepaddr;
7245 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7246 vm_offset_t addr, end_addr, va_next;
7247 vm_page_t dst_pdpg, dstmpte, srcmpte;
7249 if (dst_addr != src_addr)
7252 if (dst_pmap->pm_type != src_pmap->pm_type)
7256 * EPT page table entries that require emulation of A/D bits are
7257 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7258 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7259 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7260 * implementations flag an EPT misconfiguration for exec-only
7261 * mappings we skip this function entirely for emulated pmaps.
7263 if (pmap_emulate_ad_bits(dst_pmap))
7266 end_addr = src_addr + len;
7268 if (dst_pmap < src_pmap) {
7269 PMAP_LOCK(dst_pmap);
7270 PMAP_LOCK(src_pmap);
7272 PMAP_LOCK(src_pmap);
7273 PMAP_LOCK(dst_pmap);
7276 PG_A = pmap_accessed_bit(dst_pmap);
7277 PG_M = pmap_modified_bit(dst_pmap);
7278 PG_V = pmap_valid_bit(dst_pmap);
7280 for (addr = src_addr; addr < end_addr; addr = va_next) {
7281 KASSERT(addr < UPT_MIN_ADDRESS,
7282 ("pmap_copy: invalid to pmap_copy page tables"));
7284 pml4e = pmap_pml4e(src_pmap, addr);
7285 if ((*pml4e & PG_V) == 0) {
7286 va_next = (addr + NBPML4) & ~PML4MASK;
7292 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7293 if ((*pdpe & PG_V) == 0) {
7294 va_next = (addr + NBPDP) & ~PDPMASK;
7300 va_next = (addr + NBPDR) & ~PDRMASK;
7304 pde = pmap_pdpe_to_pde(pdpe, addr);
7306 if (srcptepaddr == 0)
7309 if (srcptepaddr & PG_PS) {
7310 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7312 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7315 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7316 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7317 PMAP_ENTER_NORECLAIM, &lock))) {
7318 *pde = srcptepaddr & ~PG_W;
7319 pmap_resident_count_inc(dst_pmap, NBPDR /
7321 atomic_add_long(&pmap_pde_mappings, 1);
7323 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7327 srcptepaddr &= PG_FRAME;
7328 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7329 KASSERT(srcmpte->ref_count > 0,
7330 ("pmap_copy: source page table page is unused"));
7332 if (va_next > end_addr)
7335 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7336 src_pte = &src_pte[pmap_pte_index(addr)];
7338 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7342 * We only virtual copy managed pages.
7344 if ((ptetemp & PG_MANAGED) == 0)
7347 if (dstmpte != NULL) {
7348 KASSERT(dstmpte->pindex ==
7349 pmap_pde_pindex(addr),
7350 ("dstmpte pindex/addr mismatch"));
7351 dstmpte->ref_count++;
7352 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7355 dst_pte = (pt_entry_t *)
7356 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7357 dst_pte = &dst_pte[pmap_pte_index(addr)];
7358 if (*dst_pte == 0 &&
7359 pmap_try_insert_pv_entry(dst_pmap, addr,
7360 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7362 * Clear the wired, modified, and accessed
7363 * (referenced) bits during the copy.
7365 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7366 pmap_resident_count_inc(dst_pmap, 1);
7368 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7371 /* Have we copied all of the valid mappings? */
7372 if (dstmpte->ref_count >= srcmpte->ref_count)
7379 PMAP_UNLOCK(src_pmap);
7380 PMAP_UNLOCK(dst_pmap);
7384 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7388 if (dst_pmap->pm_type != src_pmap->pm_type ||
7389 dst_pmap->pm_type != PT_X86 ||
7390 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7393 if (dst_pmap < src_pmap) {
7394 PMAP_LOCK(dst_pmap);
7395 PMAP_LOCK(src_pmap);
7397 PMAP_LOCK(src_pmap);
7398 PMAP_LOCK(dst_pmap);
7400 error = pmap_pkru_copy(dst_pmap, src_pmap);
7401 /* Clean up partial copy on failure due to no memory. */
7402 if (error == ENOMEM)
7403 pmap_pkru_deassign_all(dst_pmap);
7404 PMAP_UNLOCK(src_pmap);
7405 PMAP_UNLOCK(dst_pmap);
7406 if (error != ENOMEM)
7414 * Zero the specified hardware page.
7417 pmap_zero_page(vm_page_t m)
7419 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7421 pagezero((void *)va);
7425 * Zero an an area within a single hardware page. off and size must not
7426 * cover an area beyond a single hardware page.
7429 pmap_zero_page_area(vm_page_t m, int off, int size)
7431 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7433 if (off == 0 && size == PAGE_SIZE)
7434 pagezero((void *)va);
7436 bzero((char *)va + off, size);
7440 * Copy 1 specified hardware page to another.
7443 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7445 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7446 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7448 pagecopy((void *)src, (void *)dst);
7451 int unmapped_buf_allowed = 1;
7454 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7455 vm_offset_t b_offset, int xfersize)
7459 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7463 while (xfersize > 0) {
7464 a_pg_offset = a_offset & PAGE_MASK;
7465 pages[0] = ma[a_offset >> PAGE_SHIFT];
7466 b_pg_offset = b_offset & PAGE_MASK;
7467 pages[1] = mb[b_offset >> PAGE_SHIFT];
7468 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7469 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7470 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7471 a_cp = (char *)vaddr[0] + a_pg_offset;
7472 b_cp = (char *)vaddr[1] + b_pg_offset;
7473 bcopy(a_cp, b_cp, cnt);
7474 if (__predict_false(mapped))
7475 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7483 * Returns true if the pmap's pv is one of the first
7484 * 16 pvs linked to from this page. This count may
7485 * be changed upwards or downwards in the future; it
7486 * is only necessary that true be returned for a small
7487 * subset of pmaps for proper page aging.
7490 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7492 struct md_page *pvh;
7493 struct rwlock *lock;
7498 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7499 ("pmap_page_exists_quick: page %p is not managed", m));
7501 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7503 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7504 if (PV_PMAP(pv) == pmap) {
7512 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7513 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7514 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7515 if (PV_PMAP(pv) == pmap) {
7529 * pmap_page_wired_mappings:
7531 * Return the number of managed mappings to the given physical page
7535 pmap_page_wired_mappings(vm_page_t m)
7537 struct rwlock *lock;
7538 struct md_page *pvh;
7542 int count, md_gen, pvh_gen;
7544 if ((m->oflags & VPO_UNMANAGED) != 0)
7546 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7550 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7552 if (!PMAP_TRYLOCK(pmap)) {
7553 md_gen = m->md.pv_gen;
7557 if (md_gen != m->md.pv_gen) {
7562 pte = pmap_pte(pmap, pv->pv_va);
7563 if ((*pte & PG_W) != 0)
7567 if ((m->flags & PG_FICTITIOUS) == 0) {
7568 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7569 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7571 if (!PMAP_TRYLOCK(pmap)) {
7572 md_gen = m->md.pv_gen;
7573 pvh_gen = pvh->pv_gen;
7577 if (md_gen != m->md.pv_gen ||
7578 pvh_gen != pvh->pv_gen) {
7583 pte = pmap_pde(pmap, pv->pv_va);
7584 if ((*pte & PG_W) != 0)
7594 * Returns TRUE if the given page is mapped individually or as part of
7595 * a 2mpage. Otherwise, returns FALSE.
7598 pmap_page_is_mapped(vm_page_t m)
7600 struct rwlock *lock;
7603 if ((m->oflags & VPO_UNMANAGED) != 0)
7605 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7607 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7608 ((m->flags & PG_FICTITIOUS) == 0 &&
7609 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7615 * Destroy all managed, non-wired mappings in the given user-space
7616 * pmap. This pmap cannot be active on any processor besides the
7619 * This function cannot be applied to the kernel pmap. Moreover, it
7620 * is not intended for general use. It is only to be used during
7621 * process termination. Consequently, it can be implemented in ways
7622 * that make it faster than pmap_remove(). First, it can more quickly
7623 * destroy mappings by iterating over the pmap's collection of PV
7624 * entries, rather than searching the page table. Second, it doesn't
7625 * have to test and clear the page table entries atomically, because
7626 * no processor is currently accessing the user address space. In
7627 * particular, a page table entry's dirty bit won't change state once
7628 * this function starts.
7630 * Although this function destroys all of the pmap's managed,
7631 * non-wired mappings, it can delay and batch the invalidation of TLB
7632 * entries without calling pmap_delayed_invl_start() and
7633 * pmap_delayed_invl_finish(). Because the pmap is not active on
7634 * any other processor, none of these TLB entries will ever be used
7635 * before their eventual invalidation. Consequently, there is no need
7636 * for either pmap_remove_all() or pmap_remove_write() to wait for
7637 * that eventual TLB invalidation.
7640 pmap_remove_pages(pmap_t pmap)
7643 pt_entry_t *pte, tpte;
7644 pt_entry_t PG_M, PG_RW, PG_V;
7645 struct spglist free;
7646 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7647 vm_page_t m, mpte, mt;
7649 struct md_page *pvh;
7650 struct pv_chunk *pc, *npc;
7651 struct rwlock *lock;
7653 uint64_t inuse, bitmask;
7654 int allfree, field, freed, i, idx;
7655 boolean_t superpage;
7659 * Assert that the given pmap is only active on the current
7660 * CPU. Unfortunately, we cannot block another CPU from
7661 * activating the pmap while this function is executing.
7663 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7666 cpuset_t other_cpus;
7668 other_cpus = all_cpus;
7670 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7671 CPU_AND(&other_cpus, &pmap->pm_active);
7673 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7678 PG_M = pmap_modified_bit(pmap);
7679 PG_V = pmap_valid_bit(pmap);
7680 PG_RW = pmap_rw_bit(pmap);
7682 for (i = 0; i < PMAP_MEMDOM; i++)
7683 TAILQ_INIT(&free_chunks[i]);
7686 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7689 for (field = 0; field < _NPCM; field++) {
7690 inuse = ~pc->pc_map[field] & pc_freemask[field];
7691 while (inuse != 0) {
7693 bitmask = 1UL << bit;
7694 idx = field * 64 + bit;
7695 pv = &pc->pc_pventry[idx];
7698 pte = pmap_pdpe(pmap, pv->pv_va);
7700 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7702 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7705 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7707 pte = &pte[pmap_pte_index(pv->pv_va)];
7711 * Keep track whether 'tpte' is a
7712 * superpage explicitly instead of
7713 * relying on PG_PS being set.
7715 * This is because PG_PS is numerically
7716 * identical to PG_PTE_PAT and thus a
7717 * regular page could be mistaken for
7723 if ((tpte & PG_V) == 0) {
7724 panic("bad pte va %lx pte %lx",
7729 * We cannot remove wired pages from a process' mapping at this time
7737 pa = tpte & PG_PS_FRAME;
7739 pa = tpte & PG_FRAME;
7741 m = PHYS_TO_VM_PAGE(pa);
7742 KASSERT(m->phys_addr == pa,
7743 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7744 m, (uintmax_t)m->phys_addr,
7747 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7748 m < &vm_page_array[vm_page_array_size],
7749 ("pmap_remove_pages: bad tpte %#jx",
7755 * Update the vm_page_t clean/reference bits.
7757 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7759 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7765 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7768 pc->pc_map[field] |= bitmask;
7770 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7771 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7772 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7774 if (TAILQ_EMPTY(&pvh->pv_list)) {
7775 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7776 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7777 TAILQ_EMPTY(&mt->md.pv_list))
7778 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7780 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7782 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7783 ("pmap_remove_pages: pte page not promoted"));
7784 pmap_resident_count_dec(pmap, 1);
7785 KASSERT(mpte->ref_count == NPTEPG,
7786 ("pmap_remove_pages: pte page reference count error"));
7787 mpte->ref_count = 0;
7788 pmap_add_delayed_free_list(mpte, &free, FALSE);
7791 pmap_resident_count_dec(pmap, 1);
7792 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
7794 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
7795 TAILQ_EMPTY(&m->md.pv_list) &&
7796 (m->flags & PG_FICTITIOUS) == 0) {
7797 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7798 if (TAILQ_EMPTY(&pvh->pv_list))
7799 vm_page_aflag_clear(m, PGA_WRITEABLE);
7802 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
7806 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
7807 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
7808 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
7810 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
7811 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
7816 pmap_invalidate_all(pmap);
7817 pmap_pkru_deassign_all(pmap);
7818 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
7820 vm_page_free_pages_toq(&free, true);
7824 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
7826 struct rwlock *lock;
7828 struct md_page *pvh;
7829 pt_entry_t *pte, mask;
7830 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7832 int md_gen, pvh_gen;
7836 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7839 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7841 if (!PMAP_TRYLOCK(pmap)) {
7842 md_gen = m->md.pv_gen;
7846 if (md_gen != m->md.pv_gen) {
7851 pte = pmap_pte(pmap, pv->pv_va);
7854 PG_M = pmap_modified_bit(pmap);
7855 PG_RW = pmap_rw_bit(pmap);
7856 mask |= PG_RW | PG_M;
7859 PG_A = pmap_accessed_bit(pmap);
7860 PG_V = pmap_valid_bit(pmap);
7861 mask |= PG_V | PG_A;
7863 rv = (*pte & mask) == mask;
7868 if ((m->flags & PG_FICTITIOUS) == 0) {
7869 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7870 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7872 if (!PMAP_TRYLOCK(pmap)) {
7873 md_gen = m->md.pv_gen;
7874 pvh_gen = pvh->pv_gen;
7878 if (md_gen != m->md.pv_gen ||
7879 pvh_gen != pvh->pv_gen) {
7884 pte = pmap_pde(pmap, pv->pv_va);
7887 PG_M = pmap_modified_bit(pmap);
7888 PG_RW = pmap_rw_bit(pmap);
7889 mask |= PG_RW | PG_M;
7892 PG_A = pmap_accessed_bit(pmap);
7893 PG_V = pmap_valid_bit(pmap);
7894 mask |= PG_V | PG_A;
7896 rv = (*pte & mask) == mask;
7910 * Return whether or not the specified physical page was modified
7911 * in any physical maps.
7914 pmap_is_modified(vm_page_t m)
7917 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7918 ("pmap_is_modified: page %p is not managed", m));
7921 * If the page is not busied then this check is racy.
7923 if (!pmap_page_is_write_mapped(m))
7925 return (pmap_page_test_mappings(m, FALSE, TRUE));
7929 * pmap_is_prefaultable:
7931 * Return whether or not the specified virtual address is eligible
7935 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
7938 pt_entry_t *pte, PG_V;
7941 PG_V = pmap_valid_bit(pmap);
7944 pde = pmap_pde(pmap, addr);
7945 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
7946 pte = pmap_pde_to_pte(pde, addr);
7947 rv = (*pte & PG_V) == 0;
7954 * pmap_is_referenced:
7956 * Return whether or not the specified physical page was referenced
7957 * in any physical maps.
7960 pmap_is_referenced(vm_page_t m)
7963 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7964 ("pmap_is_referenced: page %p is not managed", m));
7965 return (pmap_page_test_mappings(m, TRUE, FALSE));
7969 * Clear the write and modified bits in each of the given page's mappings.
7972 pmap_remove_write(vm_page_t m)
7974 struct md_page *pvh;
7976 struct rwlock *lock;
7977 pv_entry_t next_pv, pv;
7979 pt_entry_t oldpte, *pte, PG_M, PG_RW;
7981 int pvh_gen, md_gen;
7983 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7984 ("pmap_remove_write: page %p is not managed", m));
7986 vm_page_assert_busied(m);
7987 if (!pmap_page_is_write_mapped(m))
7990 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7991 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
7992 pa_to_pvh(VM_PAGE_TO_PHYS(m));
7995 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
7997 if (!PMAP_TRYLOCK(pmap)) {
7998 pvh_gen = pvh->pv_gen;
8002 if (pvh_gen != pvh->pv_gen) {
8008 PG_RW = pmap_rw_bit(pmap);
8010 pde = pmap_pde(pmap, va);
8011 if ((*pde & PG_RW) != 0)
8012 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8013 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8014 ("inconsistent pv lock %p %p for page %p",
8015 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8018 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8020 if (!PMAP_TRYLOCK(pmap)) {
8021 pvh_gen = pvh->pv_gen;
8022 md_gen = m->md.pv_gen;
8026 if (pvh_gen != pvh->pv_gen ||
8027 md_gen != m->md.pv_gen) {
8033 PG_M = pmap_modified_bit(pmap);
8034 PG_RW = pmap_rw_bit(pmap);
8035 pde = pmap_pde(pmap, pv->pv_va);
8036 KASSERT((*pde & PG_PS) == 0,
8037 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8039 pte = pmap_pde_to_pte(pde, pv->pv_va);
8042 if (oldpte & PG_RW) {
8043 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8046 if ((oldpte & PG_M) != 0)
8048 pmap_invalidate_page(pmap, pv->pv_va);
8053 vm_page_aflag_clear(m, PGA_WRITEABLE);
8054 pmap_delayed_invl_wait(m);
8057 static __inline boolean_t
8058 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8061 if (!pmap_emulate_ad_bits(pmap))
8064 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8067 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8068 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8069 * if the EPT_PG_WRITE bit is set.
8071 if ((pte & EPT_PG_WRITE) != 0)
8075 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8077 if ((pte & EPT_PG_EXECUTE) == 0 ||
8078 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8085 * pmap_ts_referenced:
8087 * Return a count of reference bits for a page, clearing those bits.
8088 * It is not necessary for every reference bit to be cleared, but it
8089 * is necessary that 0 only be returned when there are truly no
8090 * reference bits set.
8092 * As an optimization, update the page's dirty field if a modified bit is
8093 * found while counting reference bits. This opportunistic update can be
8094 * performed at low cost and can eliminate the need for some future calls
8095 * to pmap_is_modified(). However, since this function stops after
8096 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8097 * dirty pages. Those dirty pages will only be detected by a future call
8098 * to pmap_is_modified().
8100 * A DI block is not needed within this function, because
8101 * invalidations are performed before the PV list lock is
8105 pmap_ts_referenced(vm_page_t m)
8107 struct md_page *pvh;
8110 struct rwlock *lock;
8111 pd_entry_t oldpde, *pde;
8112 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8115 int cleared, md_gen, not_cleared, pvh_gen;
8116 struct spglist free;
8119 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8120 ("pmap_ts_referenced: page %p is not managed", m));
8123 pa = VM_PAGE_TO_PHYS(m);
8124 lock = PHYS_TO_PV_LIST_LOCK(pa);
8125 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8129 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8130 goto small_mappings;
8136 if (!PMAP_TRYLOCK(pmap)) {
8137 pvh_gen = pvh->pv_gen;
8141 if (pvh_gen != pvh->pv_gen) {
8146 PG_A = pmap_accessed_bit(pmap);
8147 PG_M = pmap_modified_bit(pmap);
8148 PG_RW = pmap_rw_bit(pmap);
8150 pde = pmap_pde(pmap, pv->pv_va);
8152 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8154 * Although "oldpde" is mapping a 2MB page, because
8155 * this function is called at a 4KB page granularity,
8156 * we only update the 4KB page under test.
8160 if ((oldpde & PG_A) != 0) {
8162 * Since this reference bit is shared by 512 4KB
8163 * pages, it should not be cleared every time it is
8164 * tested. Apply a simple "hash" function on the
8165 * physical page number, the virtual superpage number,
8166 * and the pmap address to select one 4KB page out of
8167 * the 512 on which testing the reference bit will
8168 * result in clearing that reference bit. This
8169 * function is designed to avoid the selection of the
8170 * same 4KB page for every 2MB page mapping.
8172 * On demotion, a mapping that hasn't been referenced
8173 * is simply destroyed. To avoid the possibility of a
8174 * subsequent page fault on a demoted wired mapping,
8175 * always leave its reference bit set. Moreover,
8176 * since the superpage is wired, the current state of
8177 * its reference bit won't affect page replacement.
8179 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8180 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8181 (oldpde & PG_W) == 0) {
8182 if (safe_to_clear_referenced(pmap, oldpde)) {
8183 atomic_clear_long(pde, PG_A);
8184 pmap_invalidate_page(pmap, pv->pv_va);
8186 } else if (pmap_demote_pde_locked(pmap, pde,
8187 pv->pv_va, &lock)) {
8189 * Remove the mapping to a single page
8190 * so that a subsequent access may
8191 * repromote. Since the underlying
8192 * page table page is fully populated,
8193 * this removal never frees a page
8197 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8199 pte = pmap_pde_to_pte(pde, va);
8200 pmap_remove_pte(pmap, pte, va, *pde,
8202 pmap_invalidate_page(pmap, va);
8208 * The superpage mapping was removed
8209 * entirely and therefore 'pv' is no
8217 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8218 ("inconsistent pv lock %p %p for page %p",
8219 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8224 /* Rotate the PV list if it has more than one entry. */
8225 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8226 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8227 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8230 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8232 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8234 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8241 if (!PMAP_TRYLOCK(pmap)) {
8242 pvh_gen = pvh->pv_gen;
8243 md_gen = m->md.pv_gen;
8247 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8252 PG_A = pmap_accessed_bit(pmap);
8253 PG_M = pmap_modified_bit(pmap);
8254 PG_RW = pmap_rw_bit(pmap);
8255 pde = pmap_pde(pmap, pv->pv_va);
8256 KASSERT((*pde & PG_PS) == 0,
8257 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8259 pte = pmap_pde_to_pte(pde, pv->pv_va);
8260 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8262 if ((*pte & PG_A) != 0) {
8263 if (safe_to_clear_referenced(pmap, *pte)) {
8264 atomic_clear_long(pte, PG_A);
8265 pmap_invalidate_page(pmap, pv->pv_va);
8267 } else if ((*pte & PG_W) == 0) {
8269 * Wired pages cannot be paged out so
8270 * doing accessed bit emulation for
8271 * them is wasted effort. We do the
8272 * hard work for unwired pages only.
8274 pmap_remove_pte(pmap, pte, pv->pv_va,
8275 *pde, &free, &lock);
8276 pmap_invalidate_page(pmap, pv->pv_va);
8281 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8282 ("inconsistent pv lock %p %p for page %p",
8283 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8288 /* Rotate the PV list if it has more than one entry. */
8289 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8290 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8291 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8294 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8295 not_cleared < PMAP_TS_REFERENCED_MAX);
8298 vm_page_free_pages_toq(&free, true);
8299 return (cleared + not_cleared);
8303 * Apply the given advice to the specified range of addresses within the
8304 * given pmap. Depending on the advice, clear the referenced and/or
8305 * modified flags in each mapping and set the mapped page's dirty field.
8308 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8310 struct rwlock *lock;
8311 pml4_entry_t *pml4e;
8313 pd_entry_t oldpde, *pde;
8314 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8315 vm_offset_t va, va_next;
8319 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8323 * A/D bit emulation requires an alternate code path when clearing
8324 * the modified and accessed bits below. Since this function is
8325 * advisory in nature we skip it entirely for pmaps that require
8326 * A/D bit emulation.
8328 if (pmap_emulate_ad_bits(pmap))
8331 PG_A = pmap_accessed_bit(pmap);
8332 PG_G = pmap_global_bit(pmap);
8333 PG_M = pmap_modified_bit(pmap);
8334 PG_V = pmap_valid_bit(pmap);
8335 PG_RW = pmap_rw_bit(pmap);
8337 pmap_delayed_invl_start();
8339 for (; sva < eva; sva = va_next) {
8340 pml4e = pmap_pml4e(pmap, sva);
8341 if ((*pml4e & PG_V) == 0) {
8342 va_next = (sva + NBPML4) & ~PML4MASK;
8347 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8348 if ((*pdpe & PG_V) == 0) {
8349 va_next = (sva + NBPDP) & ~PDPMASK;
8354 va_next = (sva + NBPDR) & ~PDRMASK;
8357 pde = pmap_pdpe_to_pde(pdpe, sva);
8359 if ((oldpde & PG_V) == 0)
8361 else if ((oldpde & PG_PS) != 0) {
8362 if ((oldpde & PG_MANAGED) == 0)
8365 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8370 * The large page mapping was destroyed.
8376 * Unless the page mappings are wired, remove the
8377 * mapping to a single page so that a subsequent
8378 * access may repromote. Choosing the last page
8379 * within the address range [sva, min(va_next, eva))
8380 * generally results in more repromotions. Since the
8381 * underlying page table page is fully populated, this
8382 * removal never frees a page table page.
8384 if ((oldpde & PG_W) == 0) {
8390 ("pmap_advise: no address gap"));
8391 pte = pmap_pde_to_pte(pde, va);
8392 KASSERT((*pte & PG_V) != 0,
8393 ("pmap_advise: invalid PTE"));
8394 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8404 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8406 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8408 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8409 if (advice == MADV_DONTNEED) {
8411 * Future calls to pmap_is_modified()
8412 * can be avoided by making the page
8415 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8418 atomic_clear_long(pte, PG_M | PG_A);
8419 } else if ((*pte & PG_A) != 0)
8420 atomic_clear_long(pte, PG_A);
8424 if ((*pte & PG_G) != 0) {
8431 if (va != va_next) {
8432 pmap_invalidate_range(pmap, va, sva);
8437 pmap_invalidate_range(pmap, va, sva);
8440 pmap_invalidate_all(pmap);
8442 pmap_delayed_invl_finish();
8446 * Clear the modify bits on the specified physical page.
8449 pmap_clear_modify(vm_page_t m)
8451 struct md_page *pvh;
8453 pv_entry_t next_pv, pv;
8454 pd_entry_t oldpde, *pde;
8455 pt_entry_t *pte, PG_M, PG_RW;
8456 struct rwlock *lock;
8458 int md_gen, pvh_gen;
8460 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8461 ("pmap_clear_modify: page %p is not managed", m));
8462 vm_page_assert_busied(m);
8464 if (!pmap_page_is_write_mapped(m))
8466 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8467 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8468 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8471 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8473 if (!PMAP_TRYLOCK(pmap)) {
8474 pvh_gen = pvh->pv_gen;
8478 if (pvh_gen != pvh->pv_gen) {
8483 PG_M = pmap_modified_bit(pmap);
8484 PG_RW = pmap_rw_bit(pmap);
8486 pde = pmap_pde(pmap, va);
8488 /* If oldpde has PG_RW set, then it also has PG_M set. */
8489 if ((oldpde & PG_RW) != 0 &&
8490 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8491 (oldpde & PG_W) == 0) {
8493 * Write protect the mapping to a single page so that
8494 * a subsequent write access may repromote.
8496 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8497 pte = pmap_pde_to_pte(pde, va);
8498 atomic_clear_long(pte, PG_M | PG_RW);
8500 pmap_invalidate_page(pmap, va);
8504 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8506 if (!PMAP_TRYLOCK(pmap)) {
8507 md_gen = m->md.pv_gen;
8508 pvh_gen = pvh->pv_gen;
8512 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8517 PG_M = pmap_modified_bit(pmap);
8518 PG_RW = pmap_rw_bit(pmap);
8519 pde = pmap_pde(pmap, pv->pv_va);
8520 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8521 " a 2mpage in page %p's pv list", m));
8522 pte = pmap_pde_to_pte(pde, pv->pv_va);
8523 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8524 atomic_clear_long(pte, PG_M);
8525 pmap_invalidate_page(pmap, pv->pv_va);
8533 * Miscellaneous support routines follow
8536 /* Adjust the properties for a leaf page table entry. */
8537 static __inline void
8538 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8542 opte = *(u_long *)pte;
8544 npte = opte & ~mask;
8546 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8551 * Map a set of physical memory pages into the kernel virtual
8552 * address space. Return a pointer to where it is mapped. This
8553 * routine is intended to be used for mapping device memory,
8557 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8559 struct pmap_preinit_mapping *ppim;
8560 vm_offset_t va, offset;
8564 offset = pa & PAGE_MASK;
8565 size = round_page(offset + size);
8566 pa = trunc_page(pa);
8568 if (!pmap_initialized) {
8570 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8571 ppim = pmap_preinit_mapping + i;
8572 if (ppim->va == 0) {
8576 ppim->va = virtual_avail;
8577 virtual_avail += size;
8583 panic("%s: too many preinit mappings", __func__);
8586 * If we have a preinit mapping, re-use it.
8588 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8589 ppim = pmap_preinit_mapping + i;
8590 if (ppim->pa == pa && ppim->sz == size &&
8591 (ppim->mode == mode ||
8592 (flags & MAPDEV_SETATTR) == 0))
8593 return ((void *)(ppim->va + offset));
8596 * If the specified range of physical addresses fits within
8597 * the direct map window, use the direct map.
8599 if (pa < dmaplimit && pa + size <= dmaplimit) {
8600 va = PHYS_TO_DMAP(pa);
8601 if ((flags & MAPDEV_SETATTR) != 0) {
8602 PMAP_LOCK(kernel_pmap);
8603 i = pmap_change_props_locked(va, size,
8604 PROT_NONE, mode, flags);
8605 PMAP_UNLOCK(kernel_pmap);
8609 return ((void *)(va + offset));
8611 va = kva_alloc(size);
8613 panic("%s: Couldn't allocate KVA", __func__);
8615 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8616 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8617 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8618 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8619 pmap_invalidate_cache_range(va, va + tmpsize);
8620 return ((void *)(va + offset));
8624 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8627 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8632 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8635 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8639 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8642 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8647 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8650 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8651 MAPDEV_FLUSHCACHE));
8655 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8657 struct pmap_preinit_mapping *ppim;
8661 /* If we gave a direct map region in pmap_mapdev, do nothing */
8662 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8664 offset = va & PAGE_MASK;
8665 size = round_page(offset + size);
8666 va = trunc_page(va);
8667 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8668 ppim = pmap_preinit_mapping + i;
8669 if (ppim->va == va && ppim->sz == size) {
8670 if (pmap_initialized)
8676 if (va + size == virtual_avail)
8681 if (pmap_initialized) {
8682 pmap_qremove(va, atop(size));
8688 * Tries to demote a 1GB page mapping.
8691 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8693 pdp_entry_t newpdpe, oldpdpe;
8694 pd_entry_t *firstpde, newpde, *pde;
8695 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8699 PG_A = pmap_accessed_bit(pmap);
8700 PG_M = pmap_modified_bit(pmap);
8701 PG_V = pmap_valid_bit(pmap);
8702 PG_RW = pmap_rw_bit(pmap);
8704 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8706 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8707 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8708 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8709 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8710 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8711 " in pmap %p", va, pmap);
8714 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8715 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8716 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8717 KASSERT((oldpdpe & PG_A) != 0,
8718 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8719 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8720 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8724 * Initialize the page directory page.
8726 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8732 * Demote the mapping.
8737 * Invalidate a stale recursive mapping of the page directory page.
8739 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8741 pmap_pdpe_demotions++;
8742 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8743 " in pmap %p", va, pmap);
8748 * Sets the memory attribute for the specified page.
8751 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8754 m->md.pat_mode = ma;
8757 * If "m" is a normal page, update its direct mapping. This update
8758 * can be relied upon to perform any cache operations that are
8759 * required for data coherence.
8761 if ((m->flags & PG_FICTITIOUS) == 0 &&
8762 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8764 panic("memory attribute change on the direct map failed");
8768 * Changes the specified virtual address range's memory type to that given by
8769 * the parameter "mode". The specified virtual address range must be
8770 * completely contained within either the direct map or the kernel map. If
8771 * the virtual address range is contained within the kernel map, then the
8772 * memory type for each of the corresponding ranges of the direct map is also
8773 * changed. (The corresponding ranges of the direct map are those ranges that
8774 * map the same physical pages as the specified virtual address range.) These
8775 * changes to the direct map are necessary because Intel describes the
8776 * behavior of their processors as "undefined" if two or more mappings to the
8777 * same physical page have different memory types.
8779 * Returns zero if the change completed successfully, and either EINVAL or
8780 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
8781 * of the virtual address range was not mapped, and ENOMEM is returned if
8782 * there was insufficient memory available to complete the change. In the
8783 * latter case, the memory type may have been changed on some part of the
8784 * virtual address range or the direct map.
8787 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
8791 PMAP_LOCK(kernel_pmap);
8792 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
8794 PMAP_UNLOCK(kernel_pmap);
8799 * Changes the specified virtual address range's protections to those
8800 * specified by "prot". Like pmap_change_attr(), protections for aliases
8801 * in the direct map are updated as well. Protections on aliasing mappings may
8802 * be a subset of the requested protections; for example, mappings in the direct
8803 * map are never executable.
8806 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
8810 /* Only supported within the kernel map. */
8811 if (va < VM_MIN_KERNEL_ADDRESS)
8814 PMAP_LOCK(kernel_pmap);
8815 error = pmap_change_props_locked(va, size, prot, -1,
8816 MAPDEV_ASSERTVALID);
8817 PMAP_UNLOCK(kernel_pmap);
8822 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
8823 int mode, int flags)
8825 vm_offset_t base, offset, tmpva;
8826 vm_paddr_t pa_start, pa_end, pa_end1;
8828 pd_entry_t *pde, pde_bits, pde_mask;
8829 pt_entry_t *pte, pte_bits, pte_mask;
8833 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
8834 base = trunc_page(va);
8835 offset = va & PAGE_MASK;
8836 size = round_page(offset + size);
8839 * Only supported on kernel virtual addresses, including the direct
8840 * map but excluding the recursive map.
8842 if (base < DMAP_MIN_ADDRESS)
8846 * Construct our flag sets and masks. "bits" is the subset of
8847 * "mask" that will be set in each modified PTE.
8849 * Mappings in the direct map are never allowed to be executable.
8851 pde_bits = pte_bits = 0;
8852 pde_mask = pte_mask = 0;
8854 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
8855 pde_mask |= X86_PG_PDE_CACHE;
8856 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
8857 pte_mask |= X86_PG_PTE_CACHE;
8859 if (prot != VM_PROT_NONE) {
8860 if ((prot & VM_PROT_WRITE) != 0) {
8861 pde_bits |= X86_PG_RW;
8862 pte_bits |= X86_PG_RW;
8864 if ((prot & VM_PROT_EXECUTE) == 0 ||
8865 va < VM_MIN_KERNEL_ADDRESS) {
8869 pde_mask |= X86_PG_RW | pg_nx;
8870 pte_mask |= X86_PG_RW | pg_nx;
8874 * Pages that aren't mapped aren't supported. Also break down 2MB pages
8875 * into 4KB pages if required.
8877 for (tmpva = base; tmpva < base + size; ) {
8878 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8879 if (pdpe == NULL || *pdpe == 0) {
8880 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8881 ("%s: addr %#lx is not mapped", __func__, tmpva));
8884 if (*pdpe & PG_PS) {
8886 * If the current 1GB page already has the required
8887 * properties, then we need not demote this page. Just
8888 * increment tmpva to the next 1GB page frame.
8890 if ((*pdpe & pde_mask) == pde_bits) {
8891 tmpva = trunc_1gpage(tmpva) + NBPDP;
8896 * If the current offset aligns with a 1GB page frame
8897 * and there is at least 1GB left within the range, then
8898 * we need not break down this page into 2MB pages.
8900 if ((tmpva & PDPMASK) == 0 &&
8901 tmpva + PDPMASK < base + size) {
8905 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
8908 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8910 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8911 ("%s: addr %#lx is not mapped", __func__, tmpva));
8916 * If the current 2MB page already has the required
8917 * properties, then we need not demote this page. Just
8918 * increment tmpva to the next 2MB page frame.
8920 if ((*pde & pde_mask) == pde_bits) {
8921 tmpva = trunc_2mpage(tmpva) + NBPDR;
8926 * If the current offset aligns with a 2MB page frame
8927 * and there is at least 2MB left within the range, then
8928 * we need not break down this page into 4KB pages.
8930 if ((tmpva & PDRMASK) == 0 &&
8931 tmpva + PDRMASK < base + size) {
8935 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
8938 pte = pmap_pde_to_pte(pde, tmpva);
8940 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
8941 ("%s: addr %#lx is not mapped", __func__, tmpva));
8949 * Ok, all the pages exist, so run through them updating their
8950 * properties if required.
8953 pa_start = pa_end = 0;
8954 for (tmpva = base; tmpva < base + size; ) {
8955 pdpe = pmap_pdpe(kernel_pmap, tmpva);
8956 if (*pdpe & PG_PS) {
8957 if ((*pdpe & pde_mask) != pde_bits) {
8958 pmap_pte_props(pdpe, pde_bits, pde_mask);
8961 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8962 (*pdpe & PG_PS_FRAME) < dmaplimit) {
8963 if (pa_start == pa_end) {
8964 /* Start physical address run. */
8965 pa_start = *pdpe & PG_PS_FRAME;
8966 pa_end = pa_start + NBPDP;
8967 } else if (pa_end == (*pdpe & PG_PS_FRAME))
8970 /* Run ended, update direct map. */
8971 error = pmap_change_props_locked(
8972 PHYS_TO_DMAP(pa_start),
8973 pa_end - pa_start, prot, mode,
8977 /* Start physical address run. */
8978 pa_start = *pdpe & PG_PS_FRAME;
8979 pa_end = pa_start + NBPDP;
8982 tmpva = trunc_1gpage(tmpva) + NBPDP;
8985 pde = pmap_pdpe_to_pde(pdpe, tmpva);
8987 if ((*pde & pde_mask) != pde_bits) {
8988 pmap_pte_props(pde, pde_bits, pde_mask);
8991 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
8992 (*pde & PG_PS_FRAME) < dmaplimit) {
8993 if (pa_start == pa_end) {
8994 /* Start physical address run. */
8995 pa_start = *pde & PG_PS_FRAME;
8996 pa_end = pa_start + NBPDR;
8997 } else if (pa_end == (*pde & PG_PS_FRAME))
9000 /* Run ended, update direct map. */
9001 error = pmap_change_props_locked(
9002 PHYS_TO_DMAP(pa_start),
9003 pa_end - pa_start, prot, mode,
9007 /* Start physical address run. */
9008 pa_start = *pde & PG_PS_FRAME;
9009 pa_end = pa_start + NBPDR;
9012 tmpva = trunc_2mpage(tmpva) + NBPDR;
9014 pte = pmap_pde_to_pte(pde, tmpva);
9015 if ((*pte & pte_mask) != pte_bits) {
9016 pmap_pte_props(pte, pte_bits, pte_mask);
9019 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9020 (*pte & PG_FRAME) < dmaplimit) {
9021 if (pa_start == pa_end) {
9022 /* Start physical address run. */
9023 pa_start = *pte & PG_FRAME;
9024 pa_end = pa_start + PAGE_SIZE;
9025 } else if (pa_end == (*pte & PG_FRAME))
9026 pa_end += PAGE_SIZE;
9028 /* Run ended, update direct map. */
9029 error = pmap_change_props_locked(
9030 PHYS_TO_DMAP(pa_start),
9031 pa_end - pa_start, prot, mode,
9035 /* Start physical address run. */
9036 pa_start = *pte & PG_FRAME;
9037 pa_end = pa_start + PAGE_SIZE;
9043 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9044 pa_end1 = MIN(pa_end, dmaplimit);
9045 if (pa_start != pa_end1)
9046 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9047 pa_end1 - pa_start, prot, mode, flags);
9051 * Flush CPU caches if required to make sure any data isn't cached that
9052 * shouldn't be, etc.
9055 pmap_invalidate_range(kernel_pmap, base, tmpva);
9056 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9057 pmap_invalidate_cache_range(base, tmpva);
9063 * Demotes any mapping within the direct map region that covers more than the
9064 * specified range of physical addresses. This range's size must be a power
9065 * of two and its starting address must be a multiple of its size. Since the
9066 * demotion does not change any attributes of the mapping, a TLB invalidation
9067 * is not mandatory. The caller may, however, request a TLB invalidation.
9070 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9079 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9080 KASSERT((base & (len - 1)) == 0,
9081 ("pmap_demote_DMAP: base is not a multiple of len"));
9082 if (len < NBPDP && base < dmaplimit) {
9083 va = PHYS_TO_DMAP(base);
9085 PMAP_LOCK(kernel_pmap);
9086 pdpe = pmap_pdpe(kernel_pmap, va);
9087 if ((*pdpe & X86_PG_V) == 0)
9088 panic("pmap_demote_DMAP: invalid PDPE");
9089 if ((*pdpe & PG_PS) != 0) {
9090 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9091 panic("pmap_demote_DMAP: PDPE failed");
9095 pde = pmap_pdpe_to_pde(pdpe, va);
9096 if ((*pde & X86_PG_V) == 0)
9097 panic("pmap_demote_DMAP: invalid PDE");
9098 if ((*pde & PG_PS) != 0) {
9099 if (!pmap_demote_pde(kernel_pmap, pde, va))
9100 panic("pmap_demote_DMAP: PDE failed");
9104 if (changed && invalidate)
9105 pmap_invalidate_page(kernel_pmap, va);
9106 PMAP_UNLOCK(kernel_pmap);
9111 * Perform the pmap work for mincore(2). If the page is not both referenced and
9112 * modified by this pmap, returns its physical address so that the caller can
9113 * find other mappings.
9116 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9119 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9123 PG_A = pmap_accessed_bit(pmap);
9124 PG_M = pmap_modified_bit(pmap);
9125 PG_V = pmap_valid_bit(pmap);
9126 PG_RW = pmap_rw_bit(pmap);
9129 pdep = pmap_pde(pmap, addr);
9130 if (pdep != NULL && (*pdep & PG_V)) {
9131 if (*pdep & PG_PS) {
9133 /* Compute the physical address of the 4KB page. */
9134 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
9136 val = MINCORE_SUPER;
9138 pte = *pmap_pde_to_pte(pdep, addr);
9139 pa = pte & PG_FRAME;
9147 if ((pte & PG_V) != 0) {
9148 val |= MINCORE_INCORE;
9149 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9150 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9151 if ((pte & PG_A) != 0)
9152 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9154 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9155 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9156 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9164 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9166 uint32_t gen, new_gen, pcid_next;
9168 CRITICAL_ASSERT(curthread);
9169 gen = PCPU_GET(pcid_gen);
9170 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9171 return (pti ? 0 : CR3_PCID_SAVE);
9172 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9173 return (CR3_PCID_SAVE);
9174 pcid_next = PCPU_GET(pcid_next);
9175 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9176 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9177 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9178 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9179 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9183 PCPU_SET(pcid_gen, new_gen);
9184 pcid_next = PMAP_PCID_KERN + 1;
9188 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9189 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9190 PCPU_SET(pcid_next, pcid_next + 1);
9195 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9199 cached = pmap_pcid_alloc(pmap, cpuid);
9200 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9201 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9202 pmap->pm_pcids[cpuid].pm_pcid));
9203 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9204 pmap == kernel_pmap,
9205 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9206 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9211 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9214 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9215 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9219 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9222 uint64_t cached, cr3, kcr3, ucr3;
9224 KASSERT((read_rflags() & PSL_I) == 0,
9225 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9227 /* See the comment in pmap_invalidate_page_pcid(). */
9228 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9229 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9230 old_pmap = PCPU_GET(curpmap);
9231 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9232 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9235 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9237 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9238 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9239 PCPU_SET(curpmap, pmap);
9240 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9241 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9244 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9245 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9247 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9248 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9250 PCPU_INC(pm_save_cnt);
9252 pmap_activate_sw_pti_post(td, pmap);
9256 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9259 uint64_t cached, cr3;
9261 KASSERT((read_rflags() & PSL_I) == 0,
9262 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9264 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9266 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9267 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9269 PCPU_SET(curpmap, pmap);
9271 PCPU_INC(pm_save_cnt);
9275 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9276 u_int cpuid __unused)
9279 load_cr3(pmap->pm_cr3);
9280 PCPU_SET(curpmap, pmap);
9284 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9285 u_int cpuid __unused)
9288 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9289 PCPU_SET(kcr3, pmap->pm_cr3);
9290 PCPU_SET(ucr3, pmap->pm_ucr3);
9291 pmap_activate_sw_pti_post(td, pmap);
9294 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9298 if (pmap_pcid_enabled && pti)
9299 return (pmap_activate_sw_pcid_pti);
9300 else if (pmap_pcid_enabled && !pti)
9301 return (pmap_activate_sw_pcid_nopti);
9302 else if (!pmap_pcid_enabled && pti)
9303 return (pmap_activate_sw_nopcid_pti);
9304 else /* if (!pmap_pcid_enabled && !pti) */
9305 return (pmap_activate_sw_nopcid_nopti);
9309 pmap_activate_sw(struct thread *td)
9311 pmap_t oldpmap, pmap;
9314 oldpmap = PCPU_GET(curpmap);
9315 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9316 if (oldpmap == pmap) {
9317 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9321 cpuid = PCPU_GET(cpuid);
9323 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9325 CPU_SET(cpuid, &pmap->pm_active);
9327 pmap_activate_sw_mode(td, pmap, cpuid);
9329 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9331 CPU_CLR(cpuid, &oldpmap->pm_active);
9336 pmap_activate(struct thread *td)
9339 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9340 * invalidate_all IPI, which checks for curpmap ==
9341 * smp_tlb_pmap. The below sequence of operations has a
9342 * window where %CR3 is loaded with the new pmap's PML4
9343 * address, but the curpmap value has not yet been updated.
9344 * This causes the invltlb IPI handler, which is called
9345 * between the updates, to execute as a NOP, which leaves
9346 * stale TLB entries.
9348 * Note that the most common use of pmap_activate_sw(), from
9349 * a context switch, is immune to this race, because
9350 * interrupts are disabled (while the thread lock is owned),
9351 * so the IPI is delayed until after curpmap is updated. Protect
9352 * other callers in a similar way, by disabling interrupts
9353 * around the %cr3 register reload and curpmap assignment.
9356 pmap_activate_sw(td);
9361 pmap_activate_boot(pmap_t pmap)
9367 * kernel_pmap must be never deactivated, and we ensure that
9368 * by never activating it at all.
9370 MPASS(pmap != kernel_pmap);
9372 cpuid = PCPU_GET(cpuid);
9374 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9376 CPU_SET(cpuid, &pmap->pm_active);
9378 PCPU_SET(curpmap, pmap);
9380 kcr3 = pmap->pm_cr3;
9381 if (pmap_pcid_enabled)
9382 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9386 PCPU_SET(kcr3, kcr3);
9387 PCPU_SET(ucr3, PMAP_NO_CR3);
9391 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9396 * Increase the starting virtual address of the given mapping if a
9397 * different alignment might result in more superpage mappings.
9400 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9401 vm_offset_t *addr, vm_size_t size)
9403 vm_offset_t superpage_offset;
9407 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9408 offset += ptoa(object->pg_color);
9409 superpage_offset = offset & PDRMASK;
9410 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9411 (*addr & PDRMASK) == superpage_offset)
9413 if ((*addr & PDRMASK) < superpage_offset)
9414 *addr = (*addr & ~PDRMASK) + superpage_offset;
9416 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9420 static unsigned long num_dirty_emulations;
9421 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9422 &num_dirty_emulations, 0, NULL);
9424 static unsigned long num_accessed_emulations;
9425 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9426 &num_accessed_emulations, 0, NULL);
9428 static unsigned long num_superpage_accessed_emulations;
9429 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9430 &num_superpage_accessed_emulations, 0, NULL);
9432 static unsigned long ad_emulation_superpage_promotions;
9433 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9434 &ad_emulation_superpage_promotions, 0, NULL);
9435 #endif /* INVARIANTS */
9438 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9441 struct rwlock *lock;
9442 #if VM_NRESERVLEVEL > 0
9446 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9448 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9449 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9451 if (!pmap_emulate_ad_bits(pmap))
9454 PG_A = pmap_accessed_bit(pmap);
9455 PG_M = pmap_modified_bit(pmap);
9456 PG_V = pmap_valid_bit(pmap);
9457 PG_RW = pmap_rw_bit(pmap);
9463 pde = pmap_pde(pmap, va);
9464 if (pde == NULL || (*pde & PG_V) == 0)
9467 if ((*pde & PG_PS) != 0) {
9468 if (ftype == VM_PROT_READ) {
9470 atomic_add_long(&num_superpage_accessed_emulations, 1);
9478 pte = pmap_pde_to_pte(pde, va);
9479 if ((*pte & PG_V) == 0)
9482 if (ftype == VM_PROT_WRITE) {
9483 if ((*pte & PG_RW) == 0)
9486 * Set the modified and accessed bits simultaneously.
9488 * Intel EPT PTEs that do software emulation of A/D bits map
9489 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9490 * An EPT misconfiguration is triggered if the PTE is writable
9491 * but not readable (WR=10). This is avoided by setting PG_A
9492 * and PG_M simultaneously.
9494 *pte |= PG_M | PG_A;
9499 #if VM_NRESERVLEVEL > 0
9500 /* try to promote the mapping */
9501 if (va < VM_MAXUSER_ADDRESS)
9502 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9506 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9508 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9509 pmap_ps_enabled(pmap) &&
9510 (m->flags & PG_FICTITIOUS) == 0 &&
9511 vm_reserv_level_iffullpop(m) == 0) {
9512 pmap_promote_pde(pmap, pde, va, &lock);
9514 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9520 if (ftype == VM_PROT_WRITE)
9521 atomic_add_long(&num_dirty_emulations, 1);
9523 atomic_add_long(&num_accessed_emulations, 1);
9525 rv = 0; /* success */
9534 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9539 pt_entry_t *pte, PG_V;
9543 PG_V = pmap_valid_bit(pmap);
9546 pml4 = pmap_pml4e(pmap, va);
9548 if ((*pml4 & PG_V) == 0)
9551 pdp = pmap_pml4e_to_pdpe(pml4, va);
9553 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9556 pde = pmap_pdpe_to_pde(pdp, va);
9558 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9561 pte = pmap_pde_to_pte(pde, va);
9570 * Get the kernel virtual address of a set of physical pages. If there are
9571 * physical addresses not covered by the DMAP perform a transient mapping
9572 * that will be removed when calling pmap_unmap_io_transient.
9574 * \param page The pages the caller wishes to obtain the virtual
9575 * address on the kernel memory map.
9576 * \param vaddr On return contains the kernel virtual memory address
9577 * of the pages passed in the page parameter.
9578 * \param count Number of pages passed in.
9579 * \param can_fault TRUE if the thread using the mapped pages can take
9580 * page faults, FALSE otherwise.
9582 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9583 * finished or FALSE otherwise.
9587 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9588 boolean_t can_fault)
9591 boolean_t needs_mapping;
9593 int cache_bits, error __unused, i;
9596 * Allocate any KVA space that we need, this is done in a separate
9597 * loop to prevent calling vmem_alloc while pinned.
9599 needs_mapping = FALSE;
9600 for (i = 0; i < count; i++) {
9601 paddr = VM_PAGE_TO_PHYS(page[i]);
9602 if (__predict_false(paddr >= dmaplimit)) {
9603 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9604 M_BESTFIT | M_WAITOK, &vaddr[i]);
9605 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9606 needs_mapping = TRUE;
9608 vaddr[i] = PHYS_TO_DMAP(paddr);
9612 /* Exit early if everything is covered by the DMAP */
9617 * NB: The sequence of updating a page table followed by accesses
9618 * to the corresponding pages used in the !DMAP case is subject to
9619 * the situation described in the "AMD64 Architecture Programmer's
9620 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9621 * Coherency Considerations". Therefore, issuing the INVLPG right
9622 * after modifying the PTE bits is crucial.
9626 for (i = 0; i < count; i++) {
9627 paddr = VM_PAGE_TO_PHYS(page[i]);
9628 if (paddr >= dmaplimit) {
9631 * Slow path, since we can get page faults
9632 * while mappings are active don't pin the
9633 * thread to the CPU and instead add a global
9634 * mapping visible to all CPUs.
9636 pmap_qenter(vaddr[i], &page[i], 1);
9638 pte = vtopte(vaddr[i]);
9639 cache_bits = pmap_cache_bits(kernel_pmap,
9640 page[i]->md.pat_mode, 0);
9641 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9648 return (needs_mapping);
9652 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9653 boolean_t can_fault)
9660 for (i = 0; i < count; i++) {
9661 paddr = VM_PAGE_TO_PHYS(page[i]);
9662 if (paddr >= dmaplimit) {
9664 pmap_qremove(vaddr[i], 1);
9665 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9671 pmap_quick_enter_page(vm_page_t m)
9675 paddr = VM_PAGE_TO_PHYS(m);
9676 if (paddr < dmaplimit)
9677 return (PHYS_TO_DMAP(paddr));
9678 mtx_lock_spin(&qframe_mtx);
9679 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9680 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9681 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9686 pmap_quick_remove_page(vm_offset_t addr)
9691 pte_store(vtopte(qframe), 0);
9693 mtx_unlock_spin(&qframe_mtx);
9697 * Pdp pages from the large map are managed differently from either
9698 * kernel or user page table pages. They are permanently allocated at
9699 * initialization time, and their reference count is permanently set to
9700 * zero. The pml4 entries pointing to those pages are copied into
9701 * each allocated pmap.
9703 * In contrast, pd and pt pages are managed like user page table
9704 * pages. They are dynamically allocated, and their reference count
9705 * represents the number of valid entries within the page.
9708 pmap_large_map_getptp_unlocked(void)
9712 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9714 if (m != NULL && (m->flags & PG_ZERO) == 0)
9720 pmap_large_map_getptp(void)
9724 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9725 m = pmap_large_map_getptp_unlocked();
9727 PMAP_UNLOCK(kernel_pmap);
9729 PMAP_LOCK(kernel_pmap);
9730 /* Callers retry. */
9735 static pdp_entry_t *
9736 pmap_large_map_pdpe(vm_offset_t va)
9738 vm_pindex_t pml4_idx;
9741 pml4_idx = pmap_pml4e_index(va);
9742 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9743 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9745 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9746 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9747 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9748 "LMSPML4I %#jx lm_ents %d",
9749 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9750 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9751 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9755 pmap_large_map_pde(vm_offset_t va)
9762 pdpe = pmap_large_map_pdpe(va);
9764 m = pmap_large_map_getptp();
9767 mphys = VM_PAGE_TO_PHYS(m);
9768 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9770 MPASS((*pdpe & X86_PG_PS) == 0);
9771 mphys = *pdpe & PG_FRAME;
9773 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
9777 pmap_large_map_pte(vm_offset_t va)
9784 pde = pmap_large_map_pde(va);
9786 m = pmap_large_map_getptp();
9789 mphys = VM_PAGE_TO_PHYS(m);
9790 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
9791 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
9793 MPASS((*pde & X86_PG_PS) == 0);
9794 mphys = *pde & PG_FRAME;
9796 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
9800 pmap_large_map_kextract(vm_offset_t va)
9802 pdp_entry_t *pdpe, pdp;
9803 pd_entry_t *pde, pd;
9804 pt_entry_t *pte, pt;
9806 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
9807 ("not largemap range %#lx", (u_long)va));
9808 pdpe = pmap_large_map_pdpe(va);
9810 KASSERT((pdp & X86_PG_V) != 0,
9811 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9812 (u_long)pdpe, pdp));
9813 if ((pdp & X86_PG_PS) != 0) {
9814 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9815 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9816 (u_long)pdpe, pdp));
9817 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
9819 pde = pmap_pdpe_to_pde(pdpe, va);
9821 KASSERT((pd & X86_PG_V) != 0,
9822 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
9823 if ((pd & X86_PG_PS) != 0)
9824 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
9825 pte = pmap_pde_to_pte(pde, va);
9827 KASSERT((pt & X86_PG_V) != 0,
9828 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
9829 return ((pt & PG_FRAME) | (va & PAGE_MASK));
9833 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
9834 vmem_addr_t *vmem_res)
9838 * Large mappings are all but static. Consequently, there
9839 * is no point in waiting for an earlier allocation to be
9842 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
9843 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
9847 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
9853 vm_offset_t va, inc;
9854 vmem_addr_t vmem_res;
9858 if (len == 0 || spa + len < spa)
9861 /* See if DMAP can serve. */
9862 if (spa + len <= dmaplimit) {
9863 va = PHYS_TO_DMAP(spa);
9865 return (pmap_change_attr(va, len, mattr));
9869 * No, allocate KVA. Fit the address with best possible
9870 * alignment for superpages. Fall back to worse align if
9874 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
9875 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
9876 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
9878 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
9880 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
9883 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
9888 * Fill pagetable. PG_M is not pre-set, we scan modified bits
9889 * in the pagetable to minimize flushing. No need to
9890 * invalidate TLB, since we only update invalid entries.
9892 PMAP_LOCK(kernel_pmap);
9893 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
9895 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
9896 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
9897 pdpe = pmap_large_map_pdpe(va);
9899 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
9900 X86_PG_V | X86_PG_A | pg_nx |
9901 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9903 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
9904 (va & PDRMASK) == 0) {
9905 pde = pmap_large_map_pde(va);
9907 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
9908 X86_PG_V | X86_PG_A | pg_nx |
9909 pmap_cache_bits(kernel_pmap, mattr, TRUE);
9910 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
9914 pte = pmap_large_map_pte(va);
9916 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
9917 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
9919 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
9924 PMAP_UNLOCK(kernel_pmap);
9927 *addr = (void *)vmem_res;
9932 pmap_large_unmap(void *svaa, vm_size_t len)
9934 vm_offset_t sva, va;
9936 pdp_entry_t *pdpe, pdp;
9937 pd_entry_t *pde, pd;
9940 struct spglist spgf;
9942 sva = (vm_offset_t)svaa;
9943 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
9944 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
9948 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
9949 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
9950 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
9951 PMAP_LOCK(kernel_pmap);
9952 for (va = sva; va < sva + len; va += inc) {
9953 pdpe = pmap_large_map_pdpe(va);
9955 KASSERT((pdp & X86_PG_V) != 0,
9956 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
9957 (u_long)pdpe, pdp));
9958 if ((pdp & X86_PG_PS) != 0) {
9959 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
9960 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
9961 (u_long)pdpe, pdp));
9962 KASSERT((va & PDPMASK) == 0,
9963 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
9964 (u_long)pdpe, pdp));
9965 KASSERT(va + NBPDP <= sva + len,
9966 ("unmap covers partial 1GB page, sva %#lx va %#lx "
9967 "pdpe %#lx pdp %#lx len %#lx", sva, va,
9968 (u_long)pdpe, pdp, len));
9973 pde = pmap_pdpe_to_pde(pdpe, va);
9975 KASSERT((pd & X86_PG_V) != 0,
9976 ("invalid pd va %#lx pde %#lx pd %#lx", va,
9978 if ((pd & X86_PG_PS) != 0) {
9979 KASSERT((va & PDRMASK) == 0,
9980 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
9982 KASSERT(va + NBPDR <= sva + len,
9983 ("unmap covers partial 2MB page, sva %#lx va %#lx "
9984 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
9988 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
9990 if (m->ref_count == 0) {
9992 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
9996 pte = pmap_pde_to_pte(pde, va);
9997 KASSERT((*pte & X86_PG_V) != 0,
9998 ("invalid pte va %#lx pte %#lx pt %#lx", va,
9999 (u_long)pte, *pte));
10002 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10004 if (m->ref_count == 0) {
10006 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10007 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10009 if (m->ref_count == 0) {
10011 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10015 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10016 PMAP_UNLOCK(kernel_pmap);
10017 vm_page_free_pages_toq(&spgf, false);
10018 vmem_free(large_vmem, sva, len);
10022 pmap_large_map_wb_fence_mfence(void)
10029 pmap_large_map_wb_fence_atomic(void)
10032 atomic_thread_fence_seq_cst();
10036 pmap_large_map_wb_fence_nop(void)
10040 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10043 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10044 return (pmap_large_map_wb_fence_mfence);
10045 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10046 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10047 return (pmap_large_map_wb_fence_atomic);
10049 /* clflush is strongly enough ordered */
10050 return (pmap_large_map_wb_fence_nop);
10054 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10057 for (; len > 0; len -= cpu_clflush_line_size,
10058 va += cpu_clflush_line_size)
10063 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10066 for (; len > 0; len -= cpu_clflush_line_size,
10067 va += cpu_clflush_line_size)
10072 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10075 for (; len > 0; len -= cpu_clflush_line_size,
10076 va += cpu_clflush_line_size)
10081 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10085 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10088 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10089 return (pmap_large_map_flush_range_clwb);
10090 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10091 return (pmap_large_map_flush_range_clflushopt);
10092 else if ((cpu_feature & CPUID_CLFSH) != 0)
10093 return (pmap_large_map_flush_range_clflush);
10095 return (pmap_large_map_flush_range_nop);
10099 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10101 volatile u_long *pe;
10107 for (va = sva; va < eva; va += inc) {
10109 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10110 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10112 if ((p & X86_PG_PS) != 0)
10116 pe = (volatile u_long *)pmap_large_map_pde(va);
10118 if ((p & X86_PG_PS) != 0)
10122 pe = (volatile u_long *)pmap_large_map_pte(va);
10126 seen_other = false;
10128 if ((p & X86_PG_AVAIL1) != 0) {
10130 * Spin-wait for the end of a parallel
10137 * If we saw other write-back
10138 * occuring, we cannot rely on PG_M to
10139 * indicate state of the cache. The
10140 * PG_M bit is cleared before the
10141 * flush to avoid ignoring new writes,
10142 * and writes which are relevant for
10143 * us might happen after.
10149 if ((p & X86_PG_M) != 0 || seen_other) {
10150 if (!atomic_fcmpset_long(pe, &p,
10151 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10153 * If we saw PG_M without
10154 * PG_AVAIL1, and then on the
10155 * next attempt we do not
10156 * observe either PG_M or
10157 * PG_AVAIL1, the other
10158 * write-back started after us
10159 * and finished before us. We
10160 * can rely on it doing our
10164 pmap_large_map_flush_range(va, inc);
10165 atomic_clear_long(pe, X86_PG_AVAIL1);
10174 * Write-back cache lines for the given address range.
10176 * Must be called only on the range or sub-range returned from
10177 * pmap_large_map(). Must not be called on the coalesced ranges.
10179 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10180 * instructions support.
10183 pmap_large_map_wb(void *svap, vm_size_t len)
10185 vm_offset_t eva, sva;
10187 sva = (vm_offset_t)svap;
10189 pmap_large_map_wb_fence();
10190 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10191 pmap_large_map_flush_range(sva, len);
10193 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10194 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10195 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10196 pmap_large_map_wb_large(sva, eva);
10198 pmap_large_map_wb_fence();
10202 pmap_pti_alloc_page(void)
10206 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10207 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10208 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10213 pmap_pti_free_page(vm_page_t m)
10216 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10217 if (!vm_page_unwire_noq(m))
10219 vm_page_free_zero(m);
10224 pmap_pti_init(void)
10233 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10234 VM_OBJECT_WLOCK(pti_obj);
10235 pml4_pg = pmap_pti_alloc_page();
10236 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10237 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10238 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10239 pdpe = pmap_pti_pdpe(va);
10240 pmap_pti_wire_pte(pdpe);
10242 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10243 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10244 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10245 sizeof(struct gate_descriptor) * NIDT, false);
10247 /* Doublefault stack IST 1 */
10248 va = __pcpu[i].pc_common_tss.tss_ist1;
10249 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10250 /* NMI stack IST 2 */
10251 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10252 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10253 /* MC# stack IST 3 */
10254 va = __pcpu[i].pc_common_tss.tss_ist3 +
10255 sizeof(struct nmi_pcpu);
10256 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10257 /* DB# stack IST 4 */
10258 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10259 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10261 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10262 (vm_offset_t)etext, true);
10263 pti_finalized = true;
10264 VM_OBJECT_WUNLOCK(pti_obj);
10266 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10268 static pdp_entry_t *
10269 pmap_pti_pdpe(vm_offset_t va)
10271 pml4_entry_t *pml4e;
10274 vm_pindex_t pml4_idx;
10277 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10279 pml4_idx = pmap_pml4e_index(va);
10280 pml4e = &pti_pml4[pml4_idx];
10284 panic("pml4 alloc after finalization\n");
10285 m = pmap_pti_alloc_page();
10287 pmap_pti_free_page(m);
10288 mphys = *pml4e & ~PAGE_MASK;
10290 mphys = VM_PAGE_TO_PHYS(m);
10291 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10294 mphys = *pml4e & ~PAGE_MASK;
10296 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10301 pmap_pti_wire_pte(void *pte)
10305 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10306 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10311 pmap_pti_unwire_pde(void *pde, bool only_ref)
10315 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10316 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10317 MPASS(m->ref_count > 0);
10318 MPASS(only_ref || m->ref_count > 1);
10319 pmap_pti_free_page(m);
10323 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10328 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10329 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10330 MPASS(m->ref_count > 0);
10331 if (pmap_pti_free_page(m)) {
10332 pde = pmap_pti_pde(va);
10333 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10335 pmap_pti_unwire_pde(pde, false);
10339 static pd_entry_t *
10340 pmap_pti_pde(vm_offset_t va)
10345 vm_pindex_t pd_idx;
10348 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10350 pdpe = pmap_pti_pdpe(va);
10352 m = pmap_pti_alloc_page();
10354 pmap_pti_free_page(m);
10355 MPASS((*pdpe & X86_PG_PS) == 0);
10356 mphys = *pdpe & ~PAGE_MASK;
10358 mphys = VM_PAGE_TO_PHYS(m);
10359 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10362 MPASS((*pdpe & X86_PG_PS) == 0);
10363 mphys = *pdpe & ~PAGE_MASK;
10366 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10367 pd_idx = pmap_pde_index(va);
10372 static pt_entry_t *
10373 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10380 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10382 pde = pmap_pti_pde(va);
10383 if (unwire_pde != NULL) {
10384 *unwire_pde = true;
10385 pmap_pti_wire_pte(pde);
10388 m = pmap_pti_alloc_page();
10390 pmap_pti_free_page(m);
10391 MPASS((*pde & X86_PG_PS) == 0);
10392 mphys = *pde & ~(PAGE_MASK | pg_nx);
10394 mphys = VM_PAGE_TO_PHYS(m);
10395 *pde = mphys | X86_PG_RW | X86_PG_V;
10396 if (unwire_pde != NULL)
10397 *unwire_pde = false;
10400 MPASS((*pde & X86_PG_PS) == 0);
10401 mphys = *pde & ~(PAGE_MASK | pg_nx);
10404 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10405 pte += pmap_pte_index(va);
10411 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10415 pt_entry_t *pte, ptev;
10418 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10420 sva = trunc_page(sva);
10421 MPASS(sva > VM_MAXUSER_ADDRESS);
10422 eva = round_page(eva);
10424 for (; sva < eva; sva += PAGE_SIZE) {
10425 pte = pmap_pti_pte(sva, &unwire_pde);
10426 pa = pmap_kextract(sva);
10427 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10428 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10429 VM_MEMATTR_DEFAULT, FALSE);
10431 pte_store(pte, ptev);
10432 pmap_pti_wire_pte(pte);
10434 KASSERT(!pti_finalized,
10435 ("pti overlap after fin %#lx %#lx %#lx",
10437 KASSERT(*pte == ptev,
10438 ("pti non-identical pte after fin %#lx %#lx %#lx",
10442 pde = pmap_pti_pde(sva);
10443 pmap_pti_unwire_pde(pde, true);
10449 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10454 VM_OBJECT_WLOCK(pti_obj);
10455 pmap_pti_add_kva_locked(sva, eva, exec);
10456 VM_OBJECT_WUNLOCK(pti_obj);
10460 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10467 sva = rounddown2(sva, PAGE_SIZE);
10468 MPASS(sva > VM_MAXUSER_ADDRESS);
10469 eva = roundup2(eva, PAGE_SIZE);
10471 VM_OBJECT_WLOCK(pti_obj);
10472 for (va = sva; va < eva; va += PAGE_SIZE) {
10473 pte = pmap_pti_pte(va, NULL);
10474 KASSERT((*pte & X86_PG_V) != 0,
10475 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10476 (u_long)pte, *pte));
10478 pmap_pti_unwire_pte(pte, va);
10480 pmap_invalidate_range(kernel_pmap, sva, eva);
10481 VM_OBJECT_WUNLOCK(pti_obj);
10485 pkru_dup_range(void *ctx __unused, void *data)
10487 struct pmap_pkru_range *node, *new_node;
10489 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10490 if (new_node == NULL)
10493 memcpy(new_node, node, sizeof(*node));
10498 pkru_free_range(void *ctx __unused, void *node)
10501 uma_zfree(pmap_pkru_ranges_zone, node);
10505 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10508 struct pmap_pkru_range *ppr;
10511 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10512 MPASS(pmap->pm_type == PT_X86);
10513 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10514 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10515 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10517 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10520 ppr->pkru_keyidx = keyidx;
10521 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10522 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10524 uma_zfree(pmap_pkru_ranges_zone, ppr);
10529 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10532 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10533 MPASS(pmap->pm_type == PT_X86);
10534 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10535 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10539 pmap_pkru_deassign_all(pmap_t pmap)
10542 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10543 if (pmap->pm_type == PT_X86 &&
10544 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10545 rangeset_remove_all(&pmap->pm_pkru);
10549 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10551 struct pmap_pkru_range *ppr, *prev_ppr;
10554 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10555 if (pmap->pm_type != PT_X86 ||
10556 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10557 sva >= VM_MAXUSER_ADDRESS)
10559 MPASS(eva <= VM_MAXUSER_ADDRESS);
10560 for (va = sva, prev_ppr = NULL; va < eva;) {
10561 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10562 if ((ppr == NULL) ^ (prev_ppr == NULL))
10568 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10570 va = ppr->pkru_rs_el.re_end;
10576 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10578 struct pmap_pkru_range *ppr;
10580 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10581 if (pmap->pm_type != PT_X86 ||
10582 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10583 va >= VM_MAXUSER_ADDRESS)
10585 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10587 return (X86_PG_PKU(ppr->pkru_keyidx));
10592 pred_pkru_on_remove(void *ctx __unused, void *r)
10594 struct pmap_pkru_range *ppr;
10597 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10601 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10604 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10605 if (pmap->pm_type == PT_X86 &&
10606 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10607 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10608 pred_pkru_on_remove);
10613 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10616 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10617 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10618 MPASS(dst_pmap->pm_type == PT_X86);
10619 MPASS(src_pmap->pm_type == PT_X86);
10620 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10621 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10623 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10627 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10630 pml4_entry_t *pml4e;
10632 pd_entry_t newpde, ptpaddr, *pde;
10633 pt_entry_t newpte, *ptep, pte;
10634 vm_offset_t va, va_next;
10637 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10638 MPASS(pmap->pm_type == PT_X86);
10639 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10641 for (changed = false, va = sva; va < eva; va = va_next) {
10642 pml4e = pmap_pml4e(pmap, va);
10643 if ((*pml4e & X86_PG_V) == 0) {
10644 va_next = (va + NBPML4) & ~PML4MASK;
10650 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10651 if ((*pdpe & X86_PG_V) == 0) {
10652 va_next = (va + NBPDP) & ~PDPMASK;
10658 va_next = (va + NBPDR) & ~PDRMASK;
10662 pde = pmap_pdpe_to_pde(pdpe, va);
10667 MPASS((ptpaddr & X86_PG_V) != 0);
10668 if ((ptpaddr & PG_PS) != 0) {
10669 if (va + NBPDR == va_next && eva >= va_next) {
10670 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10671 X86_PG_PKU(keyidx);
10672 if (newpde != ptpaddr) {
10677 } else if (!pmap_demote_pde(pmap, pde, va)) {
10685 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10686 ptep++, va += PAGE_SIZE) {
10688 if ((pte & X86_PG_V) == 0)
10690 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10691 if (newpte != pte) {
10698 pmap_invalidate_range(pmap, sva, eva);
10702 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10703 u_int keyidx, int flags)
10706 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10707 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10709 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10711 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10717 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10722 sva = trunc_page(sva);
10723 eva = round_page(eva);
10724 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10729 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10731 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10733 if (error != ENOMEM)
10741 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10745 sva = trunc_page(sva);
10746 eva = round_page(eva);
10747 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10752 error = pmap_pkru_deassign(pmap, sva, eva);
10754 pmap_pkru_update_range(pmap, sva, eva, 0);
10756 if (error != ENOMEM)
10764 * Track a range of the kernel's virtual address space that is contiguous
10765 * in various mapping attributes.
10767 struct pmap_kernel_map_range {
10776 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
10782 if (eva <= range->sva)
10785 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
10786 for (i = 0; i < PAT_INDEX_SIZE; i++)
10787 if (pat_index[i] == pat_idx)
10791 case PAT_WRITE_BACK:
10794 case PAT_WRITE_THROUGH:
10797 case PAT_UNCACHEABLE:
10803 case PAT_WRITE_PROTECTED:
10806 case PAT_WRITE_COMBINING:
10810 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
10811 __func__, pat_idx, range->sva, eva);
10816 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
10818 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
10819 (range->attrs & pg_nx) != 0 ? '-' : 'x',
10820 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
10821 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
10822 mode, range->pdpes, range->pdes, range->ptes);
10824 /* Reset to sentinel value. */
10825 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
10826 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
10827 NPDEPG - 1, NPTEPG - 1);
10831 * Determine whether the attributes specified by a page table entry match those
10832 * being tracked by the current range. This is not quite as simple as a direct
10833 * flag comparison since some PAT modes have multiple representations.
10836 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
10838 pt_entry_t diff, mask;
10840 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
10841 diff = (range->attrs ^ attrs) & mask;
10844 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
10845 pmap_pat_index(kernel_pmap, range->attrs, true) ==
10846 pmap_pat_index(kernel_pmap, attrs, true))
10852 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
10856 memset(range, 0, sizeof(*range));
10858 range->attrs = attrs;
10862 * Given a leaf PTE, derive the mapping's attributes. If they do not match
10863 * those of the current run, dump the address range and its attributes, and
10867 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
10868 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
10873 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
10875 attrs |= pdpe & pg_nx;
10876 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
10877 if ((pdpe & PG_PS) != 0) {
10878 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
10879 } else if (pde != 0) {
10880 attrs |= pde & pg_nx;
10881 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
10883 if ((pde & PG_PS) != 0) {
10884 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
10885 } else if (pte != 0) {
10886 attrs |= pte & pg_nx;
10887 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
10888 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
10890 /* Canonicalize by always using the PDE PAT bit. */
10891 if ((attrs & X86_PG_PTE_PAT) != 0)
10892 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
10895 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
10896 sysctl_kmaps_dump(sb, range, va);
10897 sysctl_kmaps_reinit(range, va, attrs);
10902 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
10904 struct pmap_kernel_map_range range;
10905 struct sbuf sbuf, *sb;
10906 pml4_entry_t pml4e;
10907 pdp_entry_t *pdp, pdpe;
10908 pd_entry_t *pd, pde;
10909 pt_entry_t *pt, pte;
10912 int error, i, j, k, l;
10914 error = sysctl_wire_old_buffer(req, 0);
10918 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
10920 /* Sentinel value. */
10921 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
10922 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
10923 NPDEPG - 1, NPTEPG - 1);
10926 * Iterate over the kernel page tables without holding the kernel pmap
10927 * lock. Outside of the large map, kernel page table pages are never
10928 * freed, so at worst we will observe inconsistencies in the output.
10929 * Within the large map, ensure that PDP and PD page addresses are
10930 * valid before descending.
10932 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
10935 sbuf_printf(sb, "\nRecursive map:\n");
10938 sbuf_printf(sb, "\nDirect map:\n");
10941 sbuf_printf(sb, "\nKernel map:\n");
10944 sbuf_printf(sb, "\nLarge map:\n");
10948 /* Convert to canonical form. */
10949 if (sva == 1ul << 47)
10953 pml4e = kernel_pml4[i];
10954 if ((pml4e & X86_PG_V) == 0) {
10955 sva = rounddown2(sva, NBPML4);
10956 sysctl_kmaps_dump(sb, &range, sva);
10960 pa = pml4e & PG_FRAME;
10961 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
10963 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
10965 if ((pdpe & X86_PG_V) == 0) {
10966 sva = rounddown2(sva, NBPDP);
10967 sysctl_kmaps_dump(sb, &range, sva);
10971 pa = pdpe & PG_FRAME;
10972 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10973 vm_phys_paddr_to_vm_page(pa) == NULL)
10975 if ((pdpe & PG_PS) != 0) {
10976 sva = rounddown2(sva, NBPDP);
10977 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
10983 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
10985 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
10987 if ((pde & X86_PG_V) == 0) {
10988 sva = rounddown2(sva, NBPDR);
10989 sysctl_kmaps_dump(sb, &range, sva);
10993 pa = pde & PG_FRAME;
10994 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10995 vm_phys_paddr_to_vm_page(pa) == NULL)
10997 if ((pde & PG_PS) != 0) {
10998 sva = rounddown2(sva, NBPDR);
10999 sysctl_kmaps_check(sb, &range, sva,
11000 pml4e, pdpe, pde, 0);
11005 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11007 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11008 sva += PAGE_SIZE) {
11010 if ((pte & X86_PG_V) == 0) {
11011 sysctl_kmaps_dump(sb, &range,
11015 sysctl_kmaps_check(sb, &range, sva,
11016 pml4e, pdpe, pde, pte);
11023 error = sbuf_finish(sb);
11027 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11028 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11029 NULL, 0, sysctl_kmaps, "A",
11030 "Dump kernel address layout");
11033 DB_SHOW_COMMAND(pte, pmap_print_pte)
11036 pml5_entry_t *pml5;
11037 pml4_entry_t *pml4;
11040 pt_entry_t *pte, PG_V;
11044 db_printf("show pte addr\n");
11047 va = (vm_offset_t)addr;
11049 if (kdb_thread != NULL)
11050 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11052 pmap = PCPU_GET(curpmap);
11054 PG_V = pmap_valid_bit(pmap);
11055 db_printf("VA 0x%016lx", va);
11057 if (pmap_is_la57(pmap)) {
11058 pml5 = pmap_pml5e(pmap, va);
11059 db_printf(" pml5e 0x%016lx", *pml5);
11060 if ((*pml5 & PG_V) == 0) {
11064 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11066 pml4 = pmap_pml4e(pmap, va);
11068 db_printf(" pml4e 0x%016lx", *pml4);
11069 if ((*pml4 & PG_V) == 0) {
11073 pdp = pmap_pml4e_to_pdpe(pml4, va);
11074 db_printf(" pdpe 0x%016lx", *pdp);
11075 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11079 pde = pmap_pdpe_to_pde(pdp, va);
11080 db_printf(" pde 0x%016lx", *pde);
11081 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11085 pte = pmap_pde_to_pte(pde, va);
11086 db_printf(" pte 0x%016lx\n", *pte);
11089 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11094 a = (vm_paddr_t)addr;
11095 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11097 db_printf("show phys2dmap addr\n");
11102 ptpages_show_page(int level, int idx, vm_page_t pg)
11104 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11105 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11109 ptpages_show_complain(int level, int idx, uint64_t pte)
11111 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11115 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11117 vm_page_t pg3, pg2, pg1;
11118 pml4_entry_t *pml4;
11123 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11124 for (i4 = 0; i4 < num_entries; i4++) {
11125 if ((pml4[i4] & PG_V) == 0)
11127 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11129 ptpages_show_complain(3, i4, pml4[i4]);
11132 ptpages_show_page(3, i4, pg3);
11133 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11134 for (i3 = 0; i3 < NPDPEPG; i3++) {
11135 if ((pdp[i3] & PG_V) == 0)
11137 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11139 ptpages_show_complain(2, i3, pdp[i3]);
11142 ptpages_show_page(2, i3, pg2);
11143 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11144 for (i2 = 0; i2 < NPDEPG; i2++) {
11145 if ((pd[i2] & PG_V) == 0)
11147 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11149 ptpages_show_complain(1, i2, pd[i2]);
11152 ptpages_show_page(1, i2, pg1);
11158 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11162 pml5_entry_t *pml5;
11167 pmap = (pmap_t)addr;
11169 pmap = PCPU_GET(curpmap);
11171 PG_V = pmap_valid_bit(pmap);
11173 if (pmap_is_la57(pmap)) {
11174 pml5 = pmap->pm_pmltop;
11175 for (i5 = 0; i5 < NUPML5E; i5++) {
11176 if ((pml5[i5] & PG_V) == 0)
11178 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11180 ptpages_show_complain(4, i5, pml5[i5]);
11183 ptpages_show_page(4, i5, pg);
11184 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11187 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11188 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);