2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
10 * Copyright (c) 2003 Peter Wemm
11 * All rights reserved.
12 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
13 * All rights reserved.
15 * This code is derived from software contributed to Berkeley by
16 * the Systems Programming Group of the University of Utah Computer
17 * Science Department and William Jolitz of UUNET Technologies Inc.
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
22 * 1. Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * 2. Redistributions in binary form must reproduce the above copyright
25 * notice, this list of conditions and the following disclaimer in the
26 * documentation and/or other materials provided with the distribution.
27 * 3. All advertising materials mentioning features or use of this software
28 * must display the following acknowledgement:
29 * This product includes software developed by the University of
30 * California, Berkeley and its contributors.
31 * 4. Neither the name of the University nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
47 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
50 * Copyright (c) 2003 Networks Associates Technology, Inc.
51 * Copyright (c) 2014-2020 The FreeBSD Foundation
52 * All rights reserved.
54 * This software was developed for the FreeBSD Project by Jake Burkholder,
55 * Safeport Network Services, and Network Associates Laboratories, the
56 * Security Research Division of Network Associates, Inc. under
57 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
58 * CHATS research program.
60 * Portions of this software were developed by
61 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
62 * the FreeBSD Foundation.
64 * Redistribution and use in source and binary forms, with or without
65 * modification, are permitted provided that the following conditions
67 * 1. Redistributions of source code must retain the above copyright
68 * notice, this list of conditions and the following disclaimer.
69 * 2. Redistributions in binary form must reproduce the above copyright
70 * notice, this list of conditions and the following disclaimer in the
71 * documentation and/or other materials provided with the distribution.
73 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
74 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
79 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
80 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
81 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
82 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 #define AMD64_NPT_AWARE
88 #include <sys/cdefs.h>
89 __FBSDID("$FreeBSD$");
92 * Manages physical address maps.
94 * Since the information managed by this module is
95 * also stored by the logical address mapping module,
96 * this module may throw away valid virtual-to-physical
97 * mappings at almost any time. However, invalidations
98 * of virtual-to-physical mappings must be done as
101 * In order to cope with hardware architectures which
102 * make virtual-to-physical map invalidates expensive,
103 * this module may delay invalidate or reduced protection
104 * operations until such time as they are actually
105 * necessary. This module is given full information as
106 * to which processors are currently using which maps,
107 * and to when physical maps must be made correct.
111 #include "opt_pmap.h"
114 #include <sys/param.h>
115 #include <sys/bitstring.h>
117 #include <sys/systm.h>
118 #include <sys/kernel.h>
120 #include <sys/lock.h>
121 #include <sys/malloc.h>
122 #include <sys/mman.h>
123 #include <sys/mutex.h>
124 #include <sys/proc.h>
125 #include <sys/rangeset.h>
126 #include <sys/rwlock.h>
127 #include <sys/sbuf.h>
129 #include <sys/turnstile.h>
130 #include <sys/vmem.h>
131 #include <sys/vmmeter.h>
132 #include <sys/sched.h>
133 #include <sys/sysctl.h>
141 #include <vm/vm_param.h>
142 #include <vm/vm_kern.h>
143 #include <vm/vm_page.h>
144 #include <vm/vm_map.h>
145 #include <vm/vm_object.h>
146 #include <vm/vm_extern.h>
147 #include <vm/vm_pageout.h>
148 #include <vm/vm_pager.h>
149 #include <vm/vm_phys.h>
150 #include <vm/vm_radix.h>
151 #include <vm/vm_reserv.h>
154 #include <machine/intr_machdep.h>
155 #include <x86/apicvar.h>
156 #include <x86/ifunc.h>
157 #include <machine/cpu.h>
158 #include <machine/cputypes.h>
159 #include <machine/md_var.h>
160 #include <machine/pcb.h>
161 #include <machine/specialreg.h>
163 #include <machine/smp.h>
165 #include <machine/sysarch.h>
166 #include <machine/tss.h>
169 #define PMAP_MEMDOM MAXMEMDOM
171 #define PMAP_MEMDOM 1
174 static __inline boolean_t
175 pmap_type_guest(pmap_t pmap)
178 return ((pmap->pm_type == PT_EPT) || (pmap->pm_type == PT_RVI));
181 static __inline boolean_t
182 pmap_emulate_ad_bits(pmap_t pmap)
185 return ((pmap->pm_flags & PMAP_EMULATE_AD_BITS) != 0);
188 static __inline pt_entry_t
189 pmap_valid_bit(pmap_t pmap)
193 switch (pmap->pm_type) {
199 if (pmap_emulate_ad_bits(pmap))
200 mask = EPT_PG_EMUL_V;
205 panic("pmap_valid_bit: invalid pm_type %d", pmap->pm_type);
211 static __inline pt_entry_t
212 pmap_rw_bit(pmap_t pmap)
216 switch (pmap->pm_type) {
222 if (pmap_emulate_ad_bits(pmap))
223 mask = EPT_PG_EMUL_RW;
228 panic("pmap_rw_bit: invalid pm_type %d", pmap->pm_type);
234 static pt_entry_t pg_g;
236 static __inline pt_entry_t
237 pmap_global_bit(pmap_t pmap)
241 switch (pmap->pm_type) {
250 panic("pmap_global_bit: invalid pm_type %d", pmap->pm_type);
256 static __inline pt_entry_t
257 pmap_accessed_bit(pmap_t pmap)
261 switch (pmap->pm_type) {
267 if (pmap_emulate_ad_bits(pmap))
273 panic("pmap_accessed_bit: invalid pm_type %d", pmap->pm_type);
279 static __inline pt_entry_t
280 pmap_modified_bit(pmap_t pmap)
284 switch (pmap->pm_type) {
290 if (pmap_emulate_ad_bits(pmap))
296 panic("pmap_modified_bit: invalid pm_type %d", pmap->pm_type);
302 static __inline pt_entry_t
303 pmap_pku_mask_bit(pmap_t pmap)
306 return (pmap->pm_type == PT_X86 ? X86_PG_PKU_MASK : 0);
309 #if !defined(DIAGNOSTIC)
310 #ifdef __GNUC_GNU_INLINE__
311 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
313 #define PMAP_INLINE extern inline
320 #define PV_STAT(x) do { x ; } while (0)
322 #define PV_STAT(x) do { } while (0)
327 #define pa_index(pa) ({ \
328 KASSERT((pa) <= vm_phys_segs[vm_phys_nsegs - 1].end, \
329 ("address %lx beyond the last segment", (pa))); \
332 #define pa_to_pmdp(pa) (&pv_table[pa_index(pa)])
333 #define pa_to_pvh(pa) (&(pa_to_pmdp(pa)->pv_page))
334 #define PHYS_TO_PV_LIST_LOCK(pa) ({ \
335 struct rwlock *_lock; \
336 if (__predict_false((pa) > pmap_last_pa)) \
337 _lock = &pv_dummy_large.pv_lock; \
339 _lock = &(pa_to_pmdp(pa)->pv_lock); \
343 #define pa_index(pa) ((pa) >> PDRSHIFT)
344 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
346 #define NPV_LIST_LOCKS MAXCPU
348 #define PHYS_TO_PV_LIST_LOCK(pa) \
349 (&pv_list_locks[pa_index(pa) % NPV_LIST_LOCKS])
352 #define CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa) do { \
353 struct rwlock **_lockp = (lockp); \
354 struct rwlock *_new_lock; \
356 _new_lock = PHYS_TO_PV_LIST_LOCK(pa); \
357 if (_new_lock != *_lockp) { \
358 if (*_lockp != NULL) \
359 rw_wunlock(*_lockp); \
360 *_lockp = _new_lock; \
365 #define CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m) \
366 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, VM_PAGE_TO_PHYS(m))
368 #define RELEASE_PV_LIST_LOCK(lockp) do { \
369 struct rwlock **_lockp = (lockp); \
371 if (*_lockp != NULL) { \
372 rw_wunlock(*_lockp); \
377 #define VM_PAGE_TO_PV_LIST_LOCK(m) \
378 PHYS_TO_PV_LIST_LOCK(VM_PAGE_TO_PHYS(m))
380 struct pmap kernel_pmap_store;
382 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
383 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
386 SYSCTL_INT(_machdep, OID_AUTO, nkpt, CTLFLAG_RD, &nkpt, 0,
387 "Number of kernel page table pages allocated on bootup");
390 vm_paddr_t dmaplimit;
391 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
394 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
395 "VM/pmap parameters");
397 static int pg_ps_enabled = 1;
398 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
399 &pg_ps_enabled, 0, "Are large page mappings enabled?");
401 int __read_frequently la57 = 0;
402 SYSCTL_INT(_vm_pmap, OID_AUTO, la57, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
404 "5-level paging for host is enabled");
407 pmap_is_la57(pmap_t pmap)
409 if (pmap->pm_type == PT_X86)
411 return (false); /* XXXKIB handle EPT */
414 #define PAT_INDEX_SIZE 8
415 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
417 static u_int64_t KPTphys; /* phys addr of kernel level 1 */
418 static u_int64_t KPDphys; /* phys addr of kernel level 2 */
419 u_int64_t KPDPphys; /* phys addr of kernel level 3 */
420 u_int64_t KPML4phys; /* phys addr of kernel level 4 */
421 u_int64_t KPML5phys; /* phys addr of kernel level 5,
424 static pml4_entry_t *kernel_pml4;
425 static u_int64_t DMPDphys; /* phys addr of direct mapped level 2 */
426 static u_int64_t DMPDPphys; /* phys addr of direct mapped level 3 */
427 static int ndmpdpphys; /* number of DMPDPphys pages */
429 static vm_paddr_t KERNend; /* phys addr of end of bootstrap data */
432 * pmap_mapdev support pre initialization (i.e. console)
434 #define PMAP_PREINIT_MAPPING_COUNT 8
435 static struct pmap_preinit_mapping {
440 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
441 static int pmap_initialized;
444 * Data for the pv entry allocation mechanism.
445 * Updates to pv_invl_gen are protected by the pv list lock but reads are not.
449 pc_to_domain(struct pv_chunk *pc)
452 return (_vm_phys_domain(DMAP_TO_PHYS((vm_offset_t)pc)));
456 pc_to_domain(struct pv_chunk *pc __unused)
463 struct pv_chunks_list {
465 TAILQ_HEAD(pch, pv_chunk) pvc_list;
467 } __aligned(CACHE_LINE_SIZE);
469 struct pv_chunks_list __exclusive_cache_line pv_chunks[PMAP_MEMDOM];
472 struct pmap_large_md_page {
473 struct rwlock pv_lock;
474 struct md_page pv_page;
477 __exclusive_cache_line static struct pmap_large_md_page pv_dummy_large;
478 #define pv_dummy pv_dummy_large.pv_page
479 __read_mostly static struct pmap_large_md_page *pv_table;
480 __read_mostly vm_paddr_t pmap_last_pa;
482 static struct rwlock __exclusive_cache_line pv_list_locks[NPV_LIST_LOCKS];
483 static u_long pv_invl_gen[NPV_LIST_LOCKS];
484 static struct md_page *pv_table;
485 static struct md_page pv_dummy;
489 * All those kernel PT submaps that BSD is so fond of
491 pt_entry_t *CMAP1 = NULL;
493 static vm_offset_t qframe = 0;
494 static struct mtx qframe_mtx;
496 static int pmap_flags = PMAP_PDE_SUPERPAGE; /* flags for x86 pmaps */
498 static vmem_t *large_vmem;
499 static u_int lm_ents;
500 #define PMAP_ADDRESS_IN_LARGEMAP(va) ((va) >= LARGEMAP_MIN_ADDRESS && \
501 (va) < LARGEMAP_MIN_ADDRESS + NBPML4 * (u_long)lm_ents)
503 int pmap_pcid_enabled = 1;
504 SYSCTL_INT(_vm_pmap, OID_AUTO, pcid_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
505 &pmap_pcid_enabled, 0, "Is TLB Context ID enabled ?");
506 int invpcid_works = 0;
507 SYSCTL_INT(_vm_pmap, OID_AUTO, invpcid_works, CTLFLAG_RD, &invpcid_works, 0,
508 "Is the invpcid instruction available ?");
510 int __read_frequently pti = 0;
511 SYSCTL_INT(_vm_pmap, OID_AUTO, pti, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
513 "Page Table Isolation enabled");
514 static vm_object_t pti_obj;
515 static pml4_entry_t *pti_pml4;
516 static vm_pindex_t pti_pg_idx;
517 static bool pti_finalized;
519 struct pmap_pkru_range {
520 struct rs_el pkru_rs_el;
525 static uma_zone_t pmap_pkru_ranges_zone;
526 static bool pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
527 static pt_entry_t pmap_pkru_get(pmap_t pmap, vm_offset_t va);
528 static void pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
529 static void *pkru_dup_range(void *ctx, void *data);
530 static void pkru_free_range(void *ctx, void *node);
531 static int pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap);
532 static int pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva);
533 static void pmap_pkru_deassign_all(pmap_t pmap);
536 pmap_pcid_save_cnt_proc(SYSCTL_HANDLER_ARGS)
543 res += cpuid_to_pcpu[i]->pc_pm_save_cnt;
545 return (sysctl_handle_64(oidp, &res, 0, req));
547 SYSCTL_PROC(_vm_pmap, OID_AUTO, pcid_save_cnt, CTLTYPE_U64 | CTLFLAG_RD |
548 CTLFLAG_MPSAFE, NULL, 0, pmap_pcid_save_cnt_proc, "QU",
549 "Count of saved TLB context on switch");
551 static LIST_HEAD(, pmap_invl_gen) pmap_invl_gen_tracker =
552 LIST_HEAD_INITIALIZER(&pmap_invl_gen_tracker);
553 static struct mtx invl_gen_mtx;
554 /* Fake lock object to satisfy turnstiles interface. */
555 static struct lock_object invl_gen_ts = {
558 static struct pmap_invl_gen pmap_invl_gen_head = {
562 static u_long pmap_invl_gen = 1;
563 static int pmap_invl_waiters;
564 static struct callout pmap_invl_callout;
565 static bool pmap_invl_callout_inited;
567 #define PMAP_ASSERT_NOT_IN_DI() \
568 KASSERT(pmap_not_in_di(), ("DI already started"))
575 if ((cpu_feature2 & CPUID2_CX16) == 0)
578 TUNABLE_INT_FETCH("vm.pmap.di_locked", &tun);
583 sysctl_pmap_di_locked(SYSCTL_HANDLER_ARGS)
587 locked = pmap_di_locked();
588 return (sysctl_handle_int(oidp, &locked, 0, req));
590 SYSCTL_PROC(_vm_pmap, OID_AUTO, di_locked, CTLTYPE_INT | CTLFLAG_RDTUN |
591 CTLFLAG_MPSAFE, 0, 0, sysctl_pmap_di_locked, "",
592 "Locked delayed invalidation");
594 static bool pmap_not_in_di_l(void);
595 static bool pmap_not_in_di_u(void);
596 DEFINE_IFUNC(, bool, pmap_not_in_di, (void))
599 return (pmap_di_locked() ? pmap_not_in_di_l : pmap_not_in_di_u);
603 pmap_not_in_di_l(void)
605 struct pmap_invl_gen *invl_gen;
607 invl_gen = &curthread->td_md.md_invl_gen;
608 return (invl_gen->gen == 0);
612 pmap_thread_init_invl_gen_l(struct thread *td)
614 struct pmap_invl_gen *invl_gen;
616 invl_gen = &td->td_md.md_invl_gen;
621 pmap_delayed_invl_wait_block(u_long *m_gen, u_long *invl_gen)
623 struct turnstile *ts;
625 ts = turnstile_trywait(&invl_gen_ts);
626 if (*m_gen > atomic_load_long(invl_gen))
627 turnstile_wait(ts, NULL, TS_SHARED_QUEUE);
629 turnstile_cancel(ts);
633 pmap_delayed_invl_finish_unblock(u_long new_gen)
635 struct turnstile *ts;
637 turnstile_chain_lock(&invl_gen_ts);
638 ts = turnstile_lookup(&invl_gen_ts);
640 pmap_invl_gen = new_gen;
642 turnstile_broadcast(ts, TS_SHARED_QUEUE);
643 turnstile_unpend(ts);
645 turnstile_chain_unlock(&invl_gen_ts);
649 * Start a new Delayed Invalidation (DI) block of code, executed by
650 * the current thread. Within a DI block, the current thread may
651 * destroy both the page table and PV list entries for a mapping and
652 * then release the corresponding PV list lock before ensuring that
653 * the mapping is flushed from the TLBs of any processors with the
657 pmap_delayed_invl_start_l(void)
659 struct pmap_invl_gen *invl_gen;
662 invl_gen = &curthread->td_md.md_invl_gen;
663 PMAP_ASSERT_NOT_IN_DI();
664 mtx_lock(&invl_gen_mtx);
665 if (LIST_EMPTY(&pmap_invl_gen_tracker))
666 currgen = pmap_invl_gen;
668 currgen = LIST_FIRST(&pmap_invl_gen_tracker)->gen;
669 invl_gen->gen = currgen + 1;
670 LIST_INSERT_HEAD(&pmap_invl_gen_tracker, invl_gen, link);
671 mtx_unlock(&invl_gen_mtx);
675 * Finish the DI block, previously started by the current thread. All
676 * required TLB flushes for the pages marked by
677 * pmap_delayed_invl_page() must be finished before this function is
680 * This function works by bumping the global DI generation number to
681 * the generation number of the current thread's DI, unless there is a
682 * pending DI that started earlier. In the latter case, bumping the
683 * global DI generation number would incorrectly signal that the
684 * earlier DI had finished. Instead, this function bumps the earlier
685 * DI's generation number to match the generation number of the
686 * current thread's DI.
689 pmap_delayed_invl_finish_l(void)
691 struct pmap_invl_gen *invl_gen, *next;
693 invl_gen = &curthread->td_md.md_invl_gen;
694 KASSERT(invl_gen->gen != 0, ("missed invl_start"));
695 mtx_lock(&invl_gen_mtx);
696 next = LIST_NEXT(invl_gen, link);
698 pmap_delayed_invl_finish_unblock(invl_gen->gen);
700 next->gen = invl_gen->gen;
701 LIST_REMOVE(invl_gen, link);
702 mtx_unlock(&invl_gen_mtx);
707 pmap_not_in_di_u(void)
709 struct pmap_invl_gen *invl_gen;
711 invl_gen = &curthread->td_md.md_invl_gen;
712 return (((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) != 0);
716 pmap_thread_init_invl_gen_u(struct thread *td)
718 struct pmap_invl_gen *invl_gen;
720 invl_gen = &td->td_md.md_invl_gen;
722 invl_gen->next = (void *)PMAP_INVL_GEN_NEXT_INVALID;
726 pmap_di_load_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *out)
728 uint64_t new_high, new_low, old_high, old_low;
731 old_low = new_low = 0;
732 old_high = new_high = (uintptr_t)0;
734 __asm volatile("lock;cmpxchg16b\t%1"
735 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
736 : "b"(new_low), "c" (new_high)
739 if ((old_high & PMAP_INVL_GEN_NEXT_INVALID) != 0)
742 out->next = (void *)old_high;
745 out->next = (void *)new_high;
751 pmap_di_store_invl(struct pmap_invl_gen *ptr, struct pmap_invl_gen *old_val,
752 struct pmap_invl_gen *new_val)
754 uint64_t new_high, new_low, old_high, old_low;
757 new_low = new_val->gen;
758 new_high = (uintptr_t)new_val->next;
759 old_low = old_val->gen;
760 old_high = (uintptr_t)old_val->next;
762 __asm volatile("lock;cmpxchg16b\t%1"
763 : "=@cce" (res), "+m" (*ptr), "+a" (old_low), "+d" (old_high)
764 : "b"(new_low), "c" (new_high)
770 static long invl_start_restart;
771 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_start_restart, CTLFLAG_RD,
772 &invl_start_restart, 0,
774 static long invl_finish_restart;
775 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_finish_restart, CTLFLAG_RD,
776 &invl_finish_restart, 0,
778 static int invl_max_qlen;
779 SYSCTL_INT(_vm_pmap, OID_AUTO, invl_max_qlen, CTLFLAG_RD,
784 #define di_delay locks_delay
787 pmap_delayed_invl_start_u(void)
789 struct pmap_invl_gen *invl_gen, *p, prev, new_prev;
791 struct lock_delay_arg lda;
799 invl_gen = &td->td_md.md_invl_gen;
800 PMAP_ASSERT_NOT_IN_DI();
801 lock_delay_arg_init(&lda, &di_delay);
802 invl_gen->saved_pri = 0;
803 pri = td->td_base_pri;
806 pri = td->td_base_pri;
808 invl_gen->saved_pri = pri;
815 for (p = &pmap_invl_gen_head;; p = prev.next) {
817 prevl = (uintptr_t)atomic_load_ptr(&p->next);
818 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
819 PV_STAT(atomic_add_long(&invl_start_restart, 1));
825 prev.next = (void *)prevl;
828 if ((ii = invl_max_qlen) < i)
829 atomic_cmpset_int(&invl_max_qlen, ii, i);
832 if (!pmap_di_load_invl(p, &prev) || prev.next != NULL) {
833 PV_STAT(atomic_add_long(&invl_start_restart, 1));
838 new_prev.gen = prev.gen;
839 new_prev.next = invl_gen;
840 invl_gen->gen = prev.gen + 1;
842 /* Formal fence between store to invl->gen and updating *p. */
843 atomic_thread_fence_rel();
846 * After inserting an invl_gen element with invalid bit set,
847 * this thread blocks any other thread trying to enter the
848 * delayed invalidation block. Do not allow to remove us from
849 * the CPU, because it causes starvation for other threads.
854 * ABA for *p is not possible there, since p->gen can only
855 * increase. So if the *p thread finished its di, then
856 * started a new one and got inserted into the list at the
857 * same place, its gen will appear greater than the previously
860 if (!pmap_di_store_invl(p, &prev, &new_prev)) {
862 PV_STAT(atomic_add_long(&invl_start_restart, 1));
868 * There we clear PMAP_INVL_GEN_NEXT_INVALID in
869 * invl_gen->next, allowing other threads to iterate past us.
870 * pmap_di_store_invl() provides fence between the generation
871 * write and the update of next.
873 invl_gen->next = NULL;
878 pmap_delayed_invl_finish_u_crit(struct pmap_invl_gen *invl_gen,
879 struct pmap_invl_gen *p)
881 struct pmap_invl_gen prev, new_prev;
885 * Load invl_gen->gen after setting invl_gen->next
886 * PMAP_INVL_GEN_NEXT_INVALID. This prevents larger
887 * generations to propagate to our invl_gen->gen. Lock prefix
888 * in atomic_set_ptr() worked as seq_cst fence.
890 mygen = atomic_load_long(&invl_gen->gen);
892 if (!pmap_di_load_invl(p, &prev) || prev.next != invl_gen)
895 KASSERT(prev.gen < mygen,
896 ("invalid di gen sequence %lu %lu", prev.gen, mygen));
897 new_prev.gen = mygen;
898 new_prev.next = (void *)((uintptr_t)invl_gen->next &
899 ~PMAP_INVL_GEN_NEXT_INVALID);
901 /* Formal fence between load of prev and storing update to it. */
902 atomic_thread_fence_rel();
904 return (pmap_di_store_invl(p, &prev, &new_prev));
908 pmap_delayed_invl_finish_u(void)
910 struct pmap_invl_gen *invl_gen, *p;
912 struct lock_delay_arg lda;
916 invl_gen = &td->td_md.md_invl_gen;
917 KASSERT(invl_gen->gen != 0, ("missed invl_start: gen 0"));
918 KASSERT(((uintptr_t)invl_gen->next & PMAP_INVL_GEN_NEXT_INVALID) == 0,
919 ("missed invl_start: INVALID"));
920 lock_delay_arg_init(&lda, &di_delay);
923 for (p = &pmap_invl_gen_head; p != NULL; p = (void *)prevl) {
924 prevl = (uintptr_t)atomic_load_ptr(&p->next);
925 if ((prevl & PMAP_INVL_GEN_NEXT_INVALID) != 0) {
926 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
930 if ((void *)prevl == invl_gen)
935 * It is legitimate to not find ourself on the list if a
936 * thread before us finished its DI and started it again.
938 if (__predict_false(p == NULL)) {
939 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
945 atomic_set_ptr((uintptr_t *)&invl_gen->next,
946 PMAP_INVL_GEN_NEXT_INVALID);
947 if (!pmap_delayed_invl_finish_u_crit(invl_gen, p)) {
948 atomic_clear_ptr((uintptr_t *)&invl_gen->next,
949 PMAP_INVL_GEN_NEXT_INVALID);
951 PV_STAT(atomic_add_long(&invl_finish_restart, 1));
956 if (atomic_load_int(&pmap_invl_waiters) > 0)
957 pmap_delayed_invl_finish_unblock(0);
958 if (invl_gen->saved_pri != 0) {
960 sched_prio(td, invl_gen->saved_pri);
966 DB_SHOW_COMMAND(di_queue, pmap_di_queue)
968 struct pmap_invl_gen *p, *pn;
973 for (p = &pmap_invl_gen_head, first = true; p != NULL; p = pn,
975 nextl = (uintptr_t)atomic_load_ptr(&p->next);
976 pn = (void *)(nextl & ~PMAP_INVL_GEN_NEXT_INVALID);
977 td = first ? NULL : __containerof(p, struct thread,
979 db_printf("gen %lu inv %d td %p tid %d\n", p->gen,
980 (nextl & PMAP_INVL_GEN_NEXT_INVALID) != 0, td,
981 td != NULL ? td->td_tid : -1);
987 static long invl_wait;
988 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait, CTLFLAG_RD, &invl_wait, 0,
989 "Number of times DI invalidation blocked pmap_remove_all/write");
990 static long invl_wait_slow;
991 SYSCTL_LONG(_vm_pmap, OID_AUTO, invl_wait_slow, CTLFLAG_RD, &invl_wait_slow, 0,
992 "Number of slow invalidation waits for lockless DI");
997 pmap_delayed_invl_genp(vm_page_t m)
1002 pa = VM_PAGE_TO_PHYS(m);
1003 if (__predict_false((pa) > pmap_last_pa))
1004 gen = &pv_dummy_large.pv_invl_gen;
1006 gen = &(pa_to_pmdp(pa)->pv_invl_gen);
1012 pmap_delayed_invl_genp(vm_page_t m)
1015 return (&pv_invl_gen[pa_index(VM_PAGE_TO_PHYS(m)) % NPV_LIST_LOCKS]);
1020 pmap_delayed_invl_callout_func(void *arg __unused)
1023 if (atomic_load_int(&pmap_invl_waiters) == 0)
1025 pmap_delayed_invl_finish_unblock(0);
1029 pmap_delayed_invl_callout_init(void *arg __unused)
1032 if (pmap_di_locked())
1034 callout_init(&pmap_invl_callout, 1);
1035 pmap_invl_callout_inited = true;
1037 SYSINIT(pmap_di_callout, SI_SUB_CPU + 1, SI_ORDER_ANY,
1038 pmap_delayed_invl_callout_init, NULL);
1041 * Ensure that all currently executing DI blocks, that need to flush
1042 * TLB for the given page m, actually flushed the TLB at the time the
1043 * function returned. If the page m has an empty PV list and we call
1044 * pmap_delayed_invl_wait(), upon its return we know that no CPU has a
1045 * valid mapping for the page m in either its page table or TLB.
1047 * This function works by blocking until the global DI generation
1048 * number catches up with the generation number associated with the
1049 * given page m and its PV list. Since this function's callers
1050 * typically own an object lock and sometimes own a page lock, it
1051 * cannot sleep. Instead, it blocks on a turnstile to relinquish the
1055 pmap_delayed_invl_wait_l(vm_page_t m)
1059 bool accounted = false;
1062 m_gen = pmap_delayed_invl_genp(m);
1063 while (*m_gen > pmap_invl_gen) {
1066 atomic_add_long(&invl_wait, 1);
1070 pmap_delayed_invl_wait_block(m_gen, &pmap_invl_gen);
1075 pmap_delayed_invl_wait_u(vm_page_t m)
1078 struct lock_delay_arg lda;
1082 m_gen = pmap_delayed_invl_genp(m);
1083 lock_delay_arg_init(&lda, &di_delay);
1084 while (*m_gen > atomic_load_long(&pmap_invl_gen_head.gen)) {
1085 if (fast || !pmap_invl_callout_inited) {
1086 PV_STAT(atomic_add_long(&invl_wait, 1));
1091 * The page's invalidation generation number
1092 * is still below the current thread's number.
1093 * Prepare to block so that we do not waste
1094 * CPU cycles or worse, suffer livelock.
1096 * Since it is impossible to block without
1097 * racing with pmap_delayed_invl_finish_u(),
1098 * prepare for the race by incrementing
1099 * pmap_invl_waiters and arming a 1-tick
1100 * callout which will unblock us if we lose
1103 atomic_add_int(&pmap_invl_waiters, 1);
1106 * Re-check the current thread's invalidation
1107 * generation after incrementing
1108 * pmap_invl_waiters, so that there is no race
1109 * with pmap_delayed_invl_finish_u() setting
1110 * the page generation and checking
1111 * pmap_invl_waiters. The only race allowed
1112 * is for a missed unblock, which is handled
1116 atomic_load_long(&pmap_invl_gen_head.gen)) {
1117 callout_reset(&pmap_invl_callout, 1,
1118 pmap_delayed_invl_callout_func, NULL);
1119 PV_STAT(atomic_add_long(&invl_wait_slow, 1));
1120 pmap_delayed_invl_wait_block(m_gen,
1121 &pmap_invl_gen_head.gen);
1123 atomic_add_int(&pmap_invl_waiters, -1);
1128 DEFINE_IFUNC(, void, pmap_thread_init_invl_gen, (struct thread *))
1131 return (pmap_di_locked() ? pmap_thread_init_invl_gen_l :
1132 pmap_thread_init_invl_gen_u);
1135 DEFINE_IFUNC(static, void, pmap_delayed_invl_start, (void))
1138 return (pmap_di_locked() ? pmap_delayed_invl_start_l :
1139 pmap_delayed_invl_start_u);
1142 DEFINE_IFUNC(static, void, pmap_delayed_invl_finish, (void))
1145 return (pmap_di_locked() ? pmap_delayed_invl_finish_l :
1146 pmap_delayed_invl_finish_u);
1149 DEFINE_IFUNC(static, void, pmap_delayed_invl_wait, (vm_page_t))
1152 return (pmap_di_locked() ? pmap_delayed_invl_wait_l :
1153 pmap_delayed_invl_wait_u);
1157 * Mark the page m's PV list as participating in the current thread's
1158 * DI block. Any threads concurrently using m's PV list to remove or
1159 * restrict all mappings to m will wait for the current thread's DI
1160 * block to complete before proceeding.
1162 * The function works by setting the DI generation number for m's PV
1163 * list to at least the DI generation number of the current thread.
1164 * This forces a caller of pmap_delayed_invl_wait() to block until
1165 * current thread calls pmap_delayed_invl_finish().
1168 pmap_delayed_invl_page(vm_page_t m)
1172 rw_assert(VM_PAGE_TO_PV_LIST_LOCK(m), RA_WLOCKED);
1173 gen = curthread->td_md.md_invl_gen.gen;
1176 m_gen = pmap_delayed_invl_genp(m);
1184 static caddr_t crashdumpmap;
1187 * Internal flags for pmap_enter()'s helper functions.
1189 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
1190 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
1193 * Internal flags for pmap_mapdev_internal() and
1194 * pmap_change_props_locked().
1196 #define MAPDEV_FLUSHCACHE 0x00000001 /* Flush cache after mapping. */
1197 #define MAPDEV_SETATTR 0x00000002 /* Modify existing attrs. */
1198 #define MAPDEV_ASSERTVALID 0x00000004 /* Assert mapping validity. */
1200 TAILQ_HEAD(pv_chunklist, pv_chunk);
1202 static void free_pv_chunk(struct pv_chunk *pc);
1203 static void free_pv_chunk_batch(struct pv_chunklist *batch);
1204 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
1205 static pv_entry_t get_pv_entry(pmap_t pmap, struct rwlock **lockp);
1206 static int popcnt_pc_map_pq(uint64_t *map);
1207 static vm_page_t reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp);
1208 static void reserve_pv_entries(pmap_t pmap, int needed,
1209 struct rwlock **lockp);
1210 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1211 struct rwlock **lockp);
1212 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
1213 u_int flags, struct rwlock **lockp);
1214 #if VM_NRESERVLEVEL > 0
1215 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
1216 struct rwlock **lockp);
1218 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
1219 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
1222 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
1223 static int pmap_change_props_locked(vm_offset_t va, vm_size_t size,
1224 vm_prot_t prot, int mode, int flags);
1225 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
1226 static boolean_t pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde,
1227 vm_offset_t va, struct rwlock **lockp);
1228 static boolean_t pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe,
1230 static bool pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
1231 vm_prot_t prot, struct rwlock **lockp);
1232 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
1233 u_int flags, vm_page_t m, struct rwlock **lockp);
1234 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
1235 vm_page_t m, vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp);
1236 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
1237 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted);
1238 static void pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva,
1240 static void pmap_invalidate_cache_range_all(vm_offset_t sva,
1242 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
1244 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
1245 static vm_page_t pmap_large_map_getptp_unlocked(void);
1246 static vm_paddr_t pmap_large_map_kextract(vm_offset_t va);
1247 #if VM_NRESERVLEVEL > 0
1248 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
1249 struct rwlock **lockp);
1251 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
1253 static void pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask);
1254 static void pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva,
1256 static pdp_entry_t *pmap_pti_pdpe(vm_offset_t va);
1257 static pd_entry_t *pmap_pti_pde(vm_offset_t va);
1258 static void pmap_pti_wire_pte(void *pte);
1259 static int pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
1260 struct spglist *free, struct rwlock **lockp);
1261 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
1262 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp);
1263 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
1264 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1265 struct spglist *free);
1266 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1267 pd_entry_t *pde, struct spglist *free,
1268 struct rwlock **lockp);
1269 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
1270 vm_page_t m, struct rwlock **lockp);
1271 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
1273 static void pmap_update_pde_invalidate(pmap_t, vm_offset_t va, pd_entry_t pde);
1275 static vm_page_t _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex,
1276 struct rwlock **lockp, vm_offset_t va);
1277 static pd_entry_t *pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
1278 struct rwlock **lockp);
1279 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va,
1280 struct rwlock **lockp);
1282 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m,
1283 struct spglist *free);
1284 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t, struct spglist *);
1286 /********************/
1287 /* Inline functions */
1288 /********************/
1291 * Return a non-clipped indexes for a given VA, which are page table
1292 * pages indexes at the corresponding level.
1294 static __inline vm_pindex_t
1295 pmap_pde_pindex(vm_offset_t va)
1297 return (va >> PDRSHIFT);
1300 static __inline vm_pindex_t
1301 pmap_pdpe_pindex(vm_offset_t va)
1303 return (NUPDE + (va >> PDPSHIFT));
1306 static __inline vm_pindex_t
1307 pmap_pml4e_pindex(vm_offset_t va)
1309 return (NUPDE + NUPDPE + (va >> PML4SHIFT));
1312 static __inline vm_pindex_t
1313 pmap_pml5e_pindex(vm_offset_t va)
1315 return (NUPDE + NUPDPE + NUPML4E + (va >> PML5SHIFT));
1318 static __inline pml4_entry_t *
1319 pmap_pml5e(pmap_t pmap, vm_offset_t va)
1322 MPASS(pmap_is_la57(pmap));
1323 return (&pmap->pm_pmltop[pmap_pml5e_index(va)]);
1326 static __inline pml4_entry_t *
1327 pmap_pml5e_u(pmap_t pmap, vm_offset_t va)
1330 MPASS(pmap_is_la57(pmap));
1331 return (&pmap->pm_pmltopu[pmap_pml5e_index(va)]);
1334 static __inline pml4_entry_t *
1335 pmap_pml5e_to_pml4e(pml5_entry_t *pml5e, vm_offset_t va)
1337 pml4_entry_t *pml4e;
1339 /* XXX MPASS(pmap_is_la57(pmap); */
1340 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1341 return (&pml4e[pmap_pml4e_index(va)]);
1344 /* Return a pointer to the PML4 slot that corresponds to a VA */
1345 static __inline pml4_entry_t *
1346 pmap_pml4e(pmap_t pmap, vm_offset_t va)
1348 pml5_entry_t *pml5e;
1349 pml4_entry_t *pml4e;
1352 if (pmap_is_la57(pmap)) {
1353 pml5e = pmap_pml5e(pmap, va);
1354 PG_V = pmap_valid_bit(pmap);
1355 if ((*pml5e & PG_V) == 0)
1357 pml4e = (pml4_entry_t *)PHYS_TO_DMAP(*pml5e & PG_FRAME);
1359 pml4e = pmap->pm_pmltop;
1361 return (&pml4e[pmap_pml4e_index(va)]);
1364 static __inline pml4_entry_t *
1365 pmap_pml4e_u(pmap_t pmap, vm_offset_t va)
1367 MPASS(!pmap_is_la57(pmap));
1368 return (&pmap->pm_pmltopu[pmap_pml4e_index(va)]);
1371 /* Return a pointer to the PDP slot that corresponds to a VA */
1372 static __inline pdp_entry_t *
1373 pmap_pml4e_to_pdpe(pml4_entry_t *pml4e, vm_offset_t va)
1377 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(*pml4e & PG_FRAME);
1378 return (&pdpe[pmap_pdpe_index(va)]);
1381 /* Return a pointer to the PDP slot that corresponds to a VA */
1382 static __inline pdp_entry_t *
1383 pmap_pdpe(pmap_t pmap, vm_offset_t va)
1385 pml4_entry_t *pml4e;
1388 PG_V = pmap_valid_bit(pmap);
1389 pml4e = pmap_pml4e(pmap, va);
1390 if (pml4e == NULL || (*pml4e & PG_V) == 0)
1392 return (pmap_pml4e_to_pdpe(pml4e, va));
1395 /* Return a pointer to the PD slot that corresponds to a VA */
1396 static __inline pd_entry_t *
1397 pmap_pdpe_to_pde(pdp_entry_t *pdpe, vm_offset_t va)
1401 KASSERT((*pdpe & PG_PS) == 0,
1402 ("%s: pdpe %#lx is a leaf", __func__, *pdpe));
1403 pde = (pd_entry_t *)PHYS_TO_DMAP(*pdpe & PG_FRAME);
1404 return (&pde[pmap_pde_index(va)]);
1407 /* Return a pointer to the PD slot that corresponds to a VA */
1408 static __inline pd_entry_t *
1409 pmap_pde(pmap_t pmap, vm_offset_t va)
1414 PG_V = pmap_valid_bit(pmap);
1415 pdpe = pmap_pdpe(pmap, va);
1416 if (pdpe == NULL || (*pdpe & PG_V) == 0)
1418 KASSERT((*pdpe & PG_PS) == 0,
1419 ("pmap_pde for 1G page, pmap %p va %#lx", pmap, va));
1420 return (pmap_pdpe_to_pde(pdpe, va));
1423 /* Return a pointer to the PT slot that corresponds to a VA */
1424 static __inline pt_entry_t *
1425 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
1429 KASSERT((*pde & PG_PS) == 0,
1430 ("%s: pde %#lx is a leaf", __func__, *pde));
1431 pte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
1432 return (&pte[pmap_pte_index(va)]);
1435 /* Return a pointer to the PT slot that corresponds to a VA */
1436 static __inline pt_entry_t *
1437 pmap_pte(pmap_t pmap, vm_offset_t va)
1442 PG_V = pmap_valid_bit(pmap);
1443 pde = pmap_pde(pmap, va);
1444 if (pde == NULL || (*pde & PG_V) == 0)
1446 if ((*pde & PG_PS) != 0) /* compat with i386 pmap_pte() */
1447 return ((pt_entry_t *)pde);
1448 return (pmap_pde_to_pte(pde, va));
1451 static __inline void
1452 pmap_resident_count_inc(pmap_t pmap, int count)
1455 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1456 pmap->pm_stats.resident_count += count;
1459 static __inline void
1460 pmap_resident_count_dec(pmap_t pmap, int count)
1463 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1464 KASSERT(pmap->pm_stats.resident_count >= count,
1465 ("pmap %p resident count underflow %ld %d", pmap,
1466 pmap->pm_stats.resident_count, count));
1467 pmap->pm_stats.resident_count -= count;
1470 PMAP_INLINE pt_entry_t *
1471 vtopte(vm_offset_t va)
1475 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopte on a uva/gpa 0x%0lx", va));
1478 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1479 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1480 return (P5Tmap + ((va >> PAGE_SHIFT) & mask));
1482 mask = ((1ul << (NPTEPGSHIFT + NPDEPGSHIFT + NPDPEPGSHIFT +
1483 NPML4EPGSHIFT)) - 1);
1484 return (P4Tmap + ((va >> PAGE_SHIFT) & mask));
1488 static __inline pd_entry_t *
1489 vtopde(vm_offset_t va)
1493 KASSERT(va >= VM_MAXUSER_ADDRESS, ("vtopde on a uva/gpa 0x%0lx", va));
1496 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1497 NPML4EPGSHIFT + NPML5EPGSHIFT)) - 1);
1498 return (P5Dmap + ((va >> PDRSHIFT) & mask));
1500 mask = ((1ul << (NPDEPGSHIFT + NPDPEPGSHIFT +
1501 NPML4EPGSHIFT)) - 1);
1502 return (P4Dmap + ((va >> PDRSHIFT) & mask));
1507 allocpages(vm_paddr_t *firstaddr, int n)
1512 bzero((void *)ret, n * PAGE_SIZE);
1513 *firstaddr += n * PAGE_SIZE;
1517 CTASSERT(powerof2(NDMPML4E));
1519 /* number of kernel PDP slots */
1520 #define NKPDPE(ptpgs) howmany(ptpgs, NPDEPG)
1523 nkpt_init(vm_paddr_t addr)
1530 pt_pages = howmany(addr, 1 << PDRSHIFT);
1531 pt_pages += NKPDPE(pt_pages);
1534 * Add some slop beyond the bare minimum required for bootstrapping
1537 * This is quite important when allocating KVA for kernel modules.
1538 * The modules are required to be linked in the negative 2GB of
1539 * the address space. If we run out of KVA in this region then
1540 * pmap_growkernel() will need to allocate page table pages to map
1541 * the entire 512GB of KVA space which is an unnecessary tax on
1544 * Secondly, device memory mapped as part of setting up the low-
1545 * level console(s) is taken from KVA, starting at virtual_avail.
1546 * This is because cninit() is called after pmap_bootstrap() but
1547 * before vm_init() and pmap_init(). 20MB for a frame buffer is
1550 pt_pages += 32; /* 64MB additional slop. */
1556 * Returns the proper write/execute permission for a physical page that is
1557 * part of the initial boot allocations.
1559 * If the page has kernel text, it is marked as read-only. If the page has
1560 * kernel read-only data, it is marked as read-only/not-executable. If the
1561 * page has only read-write data, it is marked as read-write/not-executable.
1562 * If the page is below/above the kernel range, it is marked as read-write.
1564 * This function operates on 2M pages, since we map the kernel space that
1567 static inline pt_entry_t
1568 bootaddr_rwx(vm_paddr_t pa)
1572 * The kernel is loaded at a 2MB-aligned address, and memory below that
1573 * need not be executable. The .bss section is padded to a 2MB
1574 * boundary, so memory following the kernel need not be executable
1575 * either. Preloaded kernel modules have their mapping permissions
1576 * fixed up by the linker.
1578 if (pa < trunc_2mpage(btext - KERNBASE) ||
1579 pa >= trunc_2mpage(_end - KERNBASE))
1580 return (X86_PG_RW | pg_nx);
1583 * The linker should ensure that the read-only and read-write
1584 * portions don't share the same 2M page, so this shouldn't
1585 * impact read-only data. However, in any case, any page with
1586 * read-write data needs to be read-write.
1588 if (pa >= trunc_2mpage(brwsection - KERNBASE))
1589 return (X86_PG_RW | pg_nx);
1592 * Mark any 2M page containing kernel text as read-only. Mark
1593 * other pages with read-only data as read-only and not executable.
1594 * (It is likely a small portion of the read-only data section will
1595 * be marked as read-only, but executable. This should be acceptable
1596 * since the read-only protection will keep the data from changing.)
1597 * Note that fixups to the .text section will still work until we
1600 if (pa < round_2mpage(etext - KERNBASE))
1606 create_pagetables(vm_paddr_t *firstaddr)
1608 int i, j, ndm1g, nkpdpe, nkdmpde;
1612 uint64_t DMPDkernphys;
1614 /* Allocate page table pages for the direct map */
1615 ndmpdp = howmany(ptoa(Maxmem), NBPDP);
1616 if (ndmpdp < 4) /* Minimum 4GB of dirmap */
1618 ndmpdpphys = howmany(ndmpdp, NPDPEPG);
1619 if (ndmpdpphys > NDMPML4E) {
1621 * Each NDMPML4E allows 512 GB, so limit to that,
1622 * and then readjust ndmpdp and ndmpdpphys.
1624 printf("NDMPML4E limits system to %d GB\n", NDMPML4E * 512);
1625 Maxmem = atop(NDMPML4E * NBPML4);
1626 ndmpdpphys = NDMPML4E;
1627 ndmpdp = NDMPML4E * NPDEPG;
1629 DMPDPphys = allocpages(firstaddr, ndmpdpphys);
1631 if ((amd_feature & AMDID_PAGE1GB) != 0) {
1633 * Calculate the number of 1G pages that will fully fit in
1636 ndm1g = ptoa(Maxmem) >> PDPSHIFT;
1639 * Allocate 2M pages for the kernel. These will be used in
1640 * place of the first one or more 1G pages from ndm1g.
1642 nkdmpde = howmany((vm_offset_t)(brwsection - KERNBASE), NBPDP);
1643 DMPDkernphys = allocpages(firstaddr, nkdmpde);
1646 DMPDphys = allocpages(firstaddr, ndmpdp - ndm1g);
1647 dmaplimit = (vm_paddr_t)ndmpdp << PDPSHIFT;
1649 /* Allocate pages */
1650 KPML4phys = allocpages(firstaddr, 1);
1651 KPDPphys = allocpages(firstaddr, NKPML4E);
1654 * Allocate the initial number of kernel page table pages required to
1655 * bootstrap. We defer this until after all memory-size dependent
1656 * allocations are done (e.g. direct map), so that we don't have to
1657 * build in too much slop in our estimate.
1659 * Note that when NKPML4E > 1, we have an empty page underneath
1660 * all but the KPML4I'th one, so we need NKPML4E-1 extra (zeroed)
1661 * pages. (pmap_enter requires a PD page to exist for each KPML4E.)
1663 nkpt_init(*firstaddr);
1664 nkpdpe = NKPDPE(nkpt);
1666 KPTphys = allocpages(firstaddr, nkpt);
1667 KPDphys = allocpages(firstaddr, nkpdpe);
1670 * Connect the zero-filled PT pages to their PD entries. This
1671 * implicitly maps the PT pages at their correct locations within
1674 pd_p = (pd_entry_t *)KPDphys;
1675 for (i = 0; i < nkpt; i++)
1676 pd_p[i] = (KPTphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1679 * Map from physical address zero to the end of loader preallocated
1680 * memory using 2MB pages. This replaces some of the PD entries
1683 for (i = 0; (i << PDRSHIFT) < KERNend; i++)
1684 /* Preset PG_M and PG_A because demotion expects it. */
1685 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1686 X86_PG_M | X86_PG_A | bootaddr_rwx(i << PDRSHIFT);
1689 * Because we map the physical blocks in 2M pages, adjust firstaddr
1690 * to record the physical blocks we've actually mapped into kernel
1691 * virtual address space.
1693 if (*firstaddr < round_2mpage(KERNend))
1694 *firstaddr = round_2mpage(KERNend);
1696 /* And connect up the PD to the PDP (leaving room for L4 pages) */
1697 pdp_p = (pdp_entry_t *)(KPDPphys + ptoa(KPML4I - KPML4BASE));
1698 for (i = 0; i < nkpdpe; i++)
1699 pdp_p[i + KPDPI] = (KPDphys + ptoa(i)) | X86_PG_RW | X86_PG_V;
1702 * Now, set up the direct map region using 2MB and/or 1GB pages. If
1703 * the end of physical memory is not aligned to a 1GB page boundary,
1704 * then the residual physical memory is mapped with 2MB pages. Later,
1705 * if pmap_mapdev{_attr}() uses the direct map for non-write-back
1706 * memory, pmap_change_attr() will demote any 2MB or 1GB page mappings
1707 * that are partially used.
1709 pd_p = (pd_entry_t *)DMPDphys;
1710 for (i = NPDEPG * ndm1g, j = 0; i < NPDEPG * ndmpdp; i++, j++) {
1711 pd_p[j] = (vm_paddr_t)i << PDRSHIFT;
1712 /* Preset PG_M and PG_A because demotion expects it. */
1713 pd_p[j] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1714 X86_PG_M | X86_PG_A | pg_nx;
1716 pdp_p = (pdp_entry_t *)DMPDPphys;
1717 for (i = 0; i < ndm1g; i++) {
1718 pdp_p[i] = (vm_paddr_t)i << PDPSHIFT;
1719 /* Preset PG_M and PG_A because demotion expects it. */
1720 pdp_p[i] |= X86_PG_RW | X86_PG_V | PG_PS | pg_g |
1721 X86_PG_M | X86_PG_A | pg_nx;
1723 for (j = 0; i < ndmpdp; i++, j++) {
1724 pdp_p[i] = DMPDphys + ptoa(j);
1725 pdp_p[i] |= X86_PG_RW | X86_PG_V | pg_nx;
1729 * Instead of using a 1G page for the memory containing the kernel,
1730 * use 2M pages with read-only and no-execute permissions. (If using 1G
1731 * pages, this will partially overwrite the PDPEs above.)
1734 pd_p = (pd_entry_t *)DMPDkernphys;
1735 for (i = 0; i < (NPDEPG * nkdmpde); i++)
1736 pd_p[i] = (i << PDRSHIFT) | X86_PG_V | PG_PS | pg_g |
1737 X86_PG_M | X86_PG_A | pg_nx |
1738 bootaddr_rwx(i << PDRSHIFT);
1739 for (i = 0; i < nkdmpde; i++)
1740 pdp_p[i] = (DMPDkernphys + ptoa(i)) | X86_PG_RW |
1744 /* And recursively map PML4 to itself in order to get PTmap */
1745 p4_p = (pml4_entry_t *)KPML4phys;
1746 p4_p[PML4PML4I] = KPML4phys;
1747 p4_p[PML4PML4I] |= X86_PG_RW | X86_PG_V | pg_nx;
1749 /* Connect the Direct Map slot(s) up to the PML4. */
1750 for (i = 0; i < ndmpdpphys; i++) {
1751 p4_p[DMPML4I + i] = DMPDPphys + ptoa(i);
1752 p4_p[DMPML4I + i] |= X86_PG_RW | X86_PG_V | pg_nx;
1755 /* Connect the KVA slots up to the PML4 */
1756 for (i = 0; i < NKPML4E; i++) {
1757 p4_p[KPML4BASE + i] = KPDPphys + ptoa(i);
1758 p4_p[KPML4BASE + i] |= X86_PG_RW | X86_PG_V;
1761 kernel_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(KPML4phys);
1765 * Bootstrap the system enough to run with virtual memory.
1767 * On amd64 this is called after mapping has already been enabled
1768 * and just syncs the pmap module with what has already been done.
1769 * [We can't call it easily with mapping off since the kernel is not
1770 * mapped with PA == VA, hence we would have to relocate every address
1771 * from the linked base (virtual) address "KERNBASE" to the actual
1772 * (physical) address starting relative to 0]
1775 pmap_bootstrap(vm_paddr_t *firstaddr)
1778 pt_entry_t *pte, *pcpu_pte;
1779 struct region_descriptor r_gdt;
1780 uint64_t cr4, pcpu_phys;
1784 KERNend = *firstaddr;
1785 res = atop(KERNend - (vm_paddr_t)kernphys);
1791 * Create an initial set of page tables to run the kernel in.
1793 create_pagetables(firstaddr);
1795 pcpu_phys = allocpages(firstaddr, MAXCPU);
1798 * Add a physical memory segment (vm_phys_seg) corresponding to the
1799 * preallocated kernel page table pages so that vm_page structures
1800 * representing these pages will be created. The vm_page structures
1801 * are required for promotion of the corresponding kernel virtual
1802 * addresses to superpage mappings.
1804 vm_phys_early_add_seg(KPTphys, KPTphys + ptoa(nkpt));
1807 * Account for the virtual addresses mapped by create_pagetables().
1809 virtual_avail = (vm_offset_t)KERNBASE + round_2mpage(KERNend);
1810 virtual_end = VM_MAX_KERNEL_ADDRESS;
1813 * Enable PG_G global pages, then switch to the kernel page
1814 * table from the bootstrap page table. After the switch, it
1815 * is possible to enable SMEP and SMAP since PG_U bits are
1821 load_cr3(KPML4phys);
1822 if (cpu_stdext_feature & CPUID_STDEXT_SMEP)
1824 if (cpu_stdext_feature & CPUID_STDEXT_SMAP)
1829 * Initialize the kernel pmap (which is statically allocated).
1830 * Count bootstrap data as being resident in case any of this data is
1831 * later unmapped (using pmap_remove()) and freed.
1833 PMAP_LOCK_INIT(kernel_pmap);
1834 kernel_pmap->pm_pmltop = kernel_pml4;
1835 kernel_pmap->pm_cr3 = KPML4phys;
1836 kernel_pmap->pm_ucr3 = PMAP_NO_CR3;
1837 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
1838 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
1839 kernel_pmap->pm_stats.resident_count = res;
1840 kernel_pmap->pm_flags = pmap_flags;
1843 * Initialize the TLB invalidations generation number lock.
1845 mtx_init(&invl_gen_mtx, "invlgn", NULL, MTX_DEF);
1848 * Reserve some special page table entries/VA space for temporary
1851 #define SYSMAP(c, p, v, n) \
1852 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
1858 * Crashdump maps. The first page is reused as CMAP1 for the
1861 SYSMAP(caddr_t, CMAP1, crashdumpmap, MAXDUMPPGS)
1862 CADDR1 = crashdumpmap;
1864 SYSMAP(struct pcpu *, pcpu_pte, __pcpu, MAXCPU);
1867 for (i = 0; i < MAXCPU; i++) {
1868 pcpu_pte[i] = (pcpu_phys + ptoa(i)) | X86_PG_V | X86_PG_RW |
1869 pg_g | pg_nx | X86_PG_M | X86_PG_A;
1873 * Re-initialize PCPU area for BSP after switching.
1874 * Make hardware use gdt and common_tss from the new PCPU.
1876 STAILQ_INIT(&cpuhead);
1877 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1878 pcpu_init(&__pcpu[0], 0, sizeof(struct pcpu));
1879 amd64_bsp_pcpu_init1(&__pcpu[0]);
1880 amd64_bsp_ist_init(&__pcpu[0]);
1881 __pcpu[0].pc_common_tss.tss_iobase = sizeof(struct amd64tss) +
1883 memcpy(__pcpu[0].pc_gdt, temp_bsp_pcpu.pc_gdt, NGDT *
1884 sizeof(struct user_segment_descriptor));
1885 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&__pcpu[0].pc_common_tss;
1886 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1887 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
1888 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
1889 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
1891 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
1892 ltr(GSEL(GPROC0_SEL, SEL_KPL));
1893 __pcpu[0].pc_dynamic = temp_bsp_pcpu.pc_dynamic;
1894 __pcpu[0].pc_acpi_id = temp_bsp_pcpu.pc_acpi_id;
1897 * Initialize the PAT MSR.
1898 * pmap_init_pat() clears and sets CR4_PGE, which, as a
1899 * side-effect, invalidates stale PG_G TLB entries that might
1900 * have been created in our pre-boot environment.
1904 /* Initialize TLB Context Id. */
1905 if (pmap_pcid_enabled) {
1906 for (i = 0; i < MAXCPU; i++) {
1907 kernel_pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN;
1908 kernel_pmap->pm_pcids[i].pm_gen = 1;
1912 * PMAP_PCID_KERN + 1 is used for initialization of
1913 * proc0 pmap. The pmap' pcid state might be used by
1914 * EFIRT entry before first context switch, so it
1915 * needs to be valid.
1917 PCPU_SET(pcid_next, PMAP_PCID_KERN + 2);
1918 PCPU_SET(pcid_gen, 1);
1921 * pcpu area for APs is zeroed during AP startup.
1922 * pc_pcid_next and pc_pcid_gen are initialized by AP
1923 * during pcpu setup.
1925 load_cr4(rcr4() | CR4_PCIDE);
1930 * Setup the PAT MSR.
1939 /* Bail if this CPU doesn't implement PAT. */
1940 if ((cpu_feature & CPUID_PAT) == 0)
1943 /* Set default PAT index table. */
1944 for (i = 0; i < PAT_INDEX_SIZE; i++)
1946 pat_index[PAT_WRITE_BACK] = 0;
1947 pat_index[PAT_WRITE_THROUGH] = 1;
1948 pat_index[PAT_UNCACHEABLE] = 3;
1949 pat_index[PAT_WRITE_COMBINING] = 6;
1950 pat_index[PAT_WRITE_PROTECTED] = 5;
1951 pat_index[PAT_UNCACHED] = 2;
1954 * Initialize default PAT entries.
1955 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
1956 * Program 5 and 6 as WP and WC.
1958 * Leave 4 and 7 as WB and UC. Note that a recursive page table
1959 * mapping for a 2M page uses a PAT value with the bit 3 set due
1960 * to its overload with PG_PS.
1962 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
1963 PAT_VALUE(1, PAT_WRITE_THROUGH) |
1964 PAT_VALUE(2, PAT_UNCACHED) |
1965 PAT_VALUE(3, PAT_UNCACHEABLE) |
1966 PAT_VALUE(4, PAT_WRITE_BACK) |
1967 PAT_VALUE(5, PAT_WRITE_PROTECTED) |
1968 PAT_VALUE(6, PAT_WRITE_COMBINING) |
1969 PAT_VALUE(7, PAT_UNCACHEABLE);
1973 load_cr4(cr4 & ~CR4_PGE);
1975 /* Disable caches (CD = 1, NW = 0). */
1977 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
1979 /* Flushes caches and TLBs. */
1983 /* Update PAT and index table. */
1984 wrmsr(MSR_PAT, pat_msr);
1986 /* Flush caches and TLBs again. */
1990 /* Restore caches and PGE. */
1995 extern const char la57_trampoline[], la57_trampoline_gdt_desc[],
1996 la57_trampoline_gdt[], la57_trampoline_end[];
1999 pmap_bootstrap_la57(void *arg __unused)
2002 pml5_entry_t *v_pml5;
2003 pml4_entry_t *v_pml4;
2007 vm_page_t m_code, m_pml4, m_pdp, m_pd, m_pt, m_pml5;
2008 void (*la57_tramp)(uint64_t pml5);
2009 struct region_descriptor r_gdt;
2011 if ((cpu_stdext_feature2 & CPUID_STDEXT2_LA57) == 0)
2013 if (!TUNABLE_INT_FETCH("vm.pmap.la57", &la57))
2018 r_gdt.rd_limit = NGDT * sizeof(struct user_segment_descriptor) - 1;
2019 r_gdt.rd_base = (long)__pcpu[0].pc_gdt;
2021 m_code = vm_page_alloc_contig(NULL, 0,
2022 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2023 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2024 if ((m_code->flags & PG_ZERO) == 0)
2025 pmap_zero_page(m_code);
2026 v_code = (char *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_code));
2027 m_pml5 = vm_page_alloc_contig(NULL, 0,
2028 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2029 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2030 if ((m_pml5->flags & PG_ZERO) == 0)
2031 pmap_zero_page(m_pml5);
2032 KPML5phys = VM_PAGE_TO_PHYS(m_pml5);
2033 v_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(KPML5phys);
2034 m_pml4 = vm_page_alloc_contig(NULL, 0,
2035 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2036 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2037 if ((m_pml4->flags & PG_ZERO) == 0)
2038 pmap_zero_page(m_pml4);
2039 v_pml4 = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pml4));
2040 m_pdp = vm_page_alloc_contig(NULL, 0,
2041 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2042 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2043 if ((m_pdp->flags & PG_ZERO) == 0)
2044 pmap_zero_page(m_pdp);
2045 v_pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pdp));
2046 m_pd = vm_page_alloc_contig(NULL, 0,
2047 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2048 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2049 if ((m_pd->flags & PG_ZERO) == 0)
2050 pmap_zero_page(m_pd);
2051 v_pd = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pd));
2052 m_pt = vm_page_alloc_contig(NULL, 0,
2053 VM_ALLOC_NORMAL | VM_ALLOC_NOBUSY | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ,
2054 1, 0, (1ULL << 32), PAGE_SIZE, 0, VM_MEMATTR_DEFAULT);
2055 if ((m_pt->flags & PG_ZERO) == 0)
2056 pmap_zero_page(m_pt);
2057 v_pt = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m_pt));
2060 * Map m_code 1:1, it appears below 4G in KVA due to physical
2061 * address being below 4G. Since kernel KVA is in upper half,
2062 * the pml4e should be zero and free for temporary use.
2064 kernel_pmap->pm_pmltop[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2065 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2067 v_pdp[pmap_pdpe_index(VM_PAGE_TO_PHYS(m_code))] =
2068 VM_PAGE_TO_PHYS(m_pd) | X86_PG_V | X86_PG_RW | X86_PG_A |
2070 v_pd[pmap_pde_index(VM_PAGE_TO_PHYS(m_code))] =
2071 VM_PAGE_TO_PHYS(m_pt) | X86_PG_V | X86_PG_RW | X86_PG_A |
2073 v_pt[pmap_pte_index(VM_PAGE_TO_PHYS(m_code))] =
2074 VM_PAGE_TO_PHYS(m_code) | X86_PG_V | X86_PG_RW | X86_PG_A |
2078 * Add pml5 entry at top of KVA pointing to existing pml4 table,
2079 * entering all existing kernel mappings into level 5 table.
2081 v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
2082 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
2085 * Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.
2087 v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))] =
2088 VM_PAGE_TO_PHYS(m_pml4) | X86_PG_V | X86_PG_RW | X86_PG_A |
2090 v_pml4[pmap_pml4e_index(VM_PAGE_TO_PHYS(m_code))] =
2091 VM_PAGE_TO_PHYS(m_pdp) | X86_PG_V | X86_PG_RW | X86_PG_A |
2095 * Copy and call the 48->57 trampoline, hope we return there, alive.
2097 bcopy(la57_trampoline, v_code, la57_trampoline_end - la57_trampoline);
2098 *(u_long *)(v_code + 2 + (la57_trampoline_gdt_desc - la57_trampoline)) =
2099 la57_trampoline_gdt - la57_trampoline + VM_PAGE_TO_PHYS(m_code);
2100 la57_tramp = (void (*)(uint64_t))VM_PAGE_TO_PHYS(m_code);
2101 la57_tramp(KPML5phys);
2104 * gdt was necessary reset, switch back to our gdt.
2107 wrmsr(MSR_GSBASE, (uint64_t)&__pcpu[0]);
2111 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2112 (struct system_segment_descriptor *)&__pcpu[0].pc_gdt[GPROC0_SEL]);
2113 ltr(GSEL(GPROC0_SEL, SEL_KPL));
2116 * Now unmap the trampoline, and free the pages.
2117 * Clear pml5 entry used for 1:1 trampoline mapping.
2119 pte_clear(&v_pml5[pmap_pml5e_index(VM_PAGE_TO_PHYS(m_code))]);
2120 invlpg((vm_offset_t)v_code);
2121 vm_page_free(m_code);
2122 vm_page_free(m_pdp);
2127 * Recursively map PML5 to itself in order to get PTmap and
2130 v_pml5[PML5PML5I] = KPML5phys | X86_PG_RW | X86_PG_V | pg_nx;
2132 kernel_pmap->pm_cr3 = KPML5phys;
2133 kernel_pmap->pm_pmltop = v_pml5;
2135 SYSINIT(la57, SI_SUB_KMEM, SI_ORDER_ANY, pmap_bootstrap_la57, NULL);
2138 * Initialize a vm_page's machine-dependent fields.
2141 pmap_page_init(vm_page_t m)
2144 TAILQ_INIT(&m->md.pv_list);
2145 m->md.pat_mode = PAT_WRITE_BACK;
2148 static int pmap_allow_2m_x_ept;
2149 SYSCTL_INT(_vm_pmap, OID_AUTO, allow_2m_x_ept, CTLFLAG_RWTUN | CTLFLAG_NOFETCH,
2150 &pmap_allow_2m_x_ept, 0,
2151 "Allow executable superpage mappings in EPT");
2154 pmap_allow_2m_x_ept_recalculate(void)
2157 * SKL002, SKL012S. Since the EPT format is only used by
2158 * Intel CPUs, the vendor check is merely a formality.
2160 if (!(cpu_vendor_id != CPU_VENDOR_INTEL ||
2161 (cpu_ia32_arch_caps & IA32_ARCH_CAP_IF_PSCHANGE_MC_NO) != 0 ||
2162 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
2163 (CPUID_TO_MODEL(cpu_id) == 0x26 || /* Atoms */
2164 CPUID_TO_MODEL(cpu_id) == 0x27 ||
2165 CPUID_TO_MODEL(cpu_id) == 0x35 ||
2166 CPUID_TO_MODEL(cpu_id) == 0x36 ||
2167 CPUID_TO_MODEL(cpu_id) == 0x37 ||
2168 CPUID_TO_MODEL(cpu_id) == 0x86 ||
2169 CPUID_TO_MODEL(cpu_id) == 0x1c ||
2170 CPUID_TO_MODEL(cpu_id) == 0x4a ||
2171 CPUID_TO_MODEL(cpu_id) == 0x4c ||
2172 CPUID_TO_MODEL(cpu_id) == 0x4d ||
2173 CPUID_TO_MODEL(cpu_id) == 0x5a ||
2174 CPUID_TO_MODEL(cpu_id) == 0x5c ||
2175 CPUID_TO_MODEL(cpu_id) == 0x5d ||
2176 CPUID_TO_MODEL(cpu_id) == 0x5f ||
2177 CPUID_TO_MODEL(cpu_id) == 0x6e ||
2178 CPUID_TO_MODEL(cpu_id) == 0x7a ||
2179 CPUID_TO_MODEL(cpu_id) == 0x57 || /* Knights */
2180 CPUID_TO_MODEL(cpu_id) == 0x85))))
2181 pmap_allow_2m_x_ept = 1;
2182 TUNABLE_INT_FETCH("hw.allow_2m_x_ept", &pmap_allow_2m_x_ept);
2186 pmap_allow_2m_x_page(pmap_t pmap, bool executable)
2189 return (pmap->pm_type != PT_EPT || !executable ||
2190 !pmap_allow_2m_x_ept);
2195 pmap_init_pv_table(void)
2197 struct pmap_large_md_page *pvd;
2199 long start, end, highest, pv_npg;
2200 int domain, i, j, pages;
2203 * We strongly depend on the size being a power of two, so the assert
2204 * is overzealous. However, should the struct be resized to a
2205 * different power of two, the code below needs to be revisited.
2207 CTASSERT((sizeof(*pvd) == 64));
2210 * Calculate the size of the array.
2212 pmap_last_pa = vm_phys_segs[vm_phys_nsegs - 1].end;
2213 pv_npg = howmany(pmap_last_pa, NBPDR);
2214 s = (vm_size_t)pv_npg * sizeof(struct pmap_large_md_page);
2216 pv_table = (struct pmap_large_md_page *)kva_alloc(s);
2217 if (pv_table == NULL)
2218 panic("%s: kva_alloc failed\n", __func__);
2221 * Iterate physical segments to allocate space for respective pages.
2225 for (i = 0; i < vm_phys_nsegs; i++) {
2226 end = vm_phys_segs[i].end / NBPDR;
2227 domain = vm_phys_segs[i].domain;
2232 start = highest + 1;
2233 pvd = &pv_table[start];
2235 pages = end - start + 1;
2236 s = round_page(pages * sizeof(*pvd));
2237 highest = start + (s / sizeof(*pvd)) - 1;
2239 for (j = 0; j < s; j += PAGE_SIZE) {
2240 vm_page_t m = vm_page_alloc_domain(NULL, 0,
2241 domain, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ);
2243 panic("vm_page_alloc_domain failed for %lx\n", (vm_offset_t)pvd + j);
2244 pmap_qenter((vm_offset_t)pvd + j, &m, 1);
2247 for (j = 0; j < s / sizeof(*pvd); j++) {
2248 rw_init_flags(&pvd->pv_lock, "pmap pv list", RW_NEW);
2249 TAILQ_INIT(&pvd->pv_page.pv_list);
2250 pvd->pv_page.pv_gen = 0;
2251 pvd->pv_page.pat_mode = 0;
2252 pvd->pv_invl_gen = 0;
2256 pvd = &pv_dummy_large;
2257 rw_init_flags(&pvd->pv_lock, "pmap pv list dummy", RW_NEW);
2258 TAILQ_INIT(&pvd->pv_page.pv_list);
2259 pvd->pv_page.pv_gen = 0;
2260 pvd->pv_page.pat_mode = 0;
2261 pvd->pv_invl_gen = 0;
2265 pmap_init_pv_table(void)
2271 * Initialize the pool of pv list locks.
2273 for (i = 0; i < NPV_LIST_LOCKS; i++)
2274 rw_init(&pv_list_locks[i], "pmap pv list");
2277 * Calculate the size of the pv head table for superpages.
2279 pv_npg = howmany(vm_phys_segs[vm_phys_nsegs - 1].end, NBPDR);
2282 * Allocate memory for the pv head table for superpages.
2284 s = (vm_size_t)pv_npg * sizeof(struct md_page);
2286 pv_table = (struct md_page *)kmem_malloc(s, M_WAITOK | M_ZERO);
2287 for (i = 0; i < pv_npg; i++)
2288 TAILQ_INIT(&pv_table[i].pv_list);
2289 TAILQ_INIT(&pv_dummy.pv_list);
2294 * Initialize the pmap module.
2295 * Called by vm_init, to initialize any structures that the pmap
2296 * system needs to map virtual memory.
2301 struct pmap_preinit_mapping *ppim;
2303 int error, i, ret, skz63;
2305 /* L1TF, reserve page @0 unconditionally */
2306 vm_page_blacklist_add(0, bootverbose);
2308 /* Detect bare-metal Skylake Server and Skylake-X. */
2309 if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_INTEL &&
2310 CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) == 0x55) {
2312 * Skylake-X errata SKZ63. Processor May Hang When
2313 * Executing Code In an HLE Transaction Region between
2314 * 40000000H and 403FFFFFH.
2316 * Mark the pages in the range as preallocated. It
2317 * seems to be impossible to distinguish between
2318 * Skylake Server and Skylake X.
2321 TUNABLE_INT_FETCH("hw.skz63_enable", &skz63);
2324 printf("SKZ63: skipping 4M RAM starting "
2325 "at physical 1G\n");
2326 for (i = 0; i < atop(0x400000); i++) {
2327 ret = vm_page_blacklist_add(0x40000000 +
2329 if (!ret && bootverbose)
2330 printf("page at %#lx already used\n",
2331 0x40000000 + ptoa(i));
2337 pmap_allow_2m_x_ept_recalculate();
2340 * Initialize the vm page array entries for the kernel pmap's
2343 PMAP_LOCK(kernel_pmap);
2344 for (i = 0; i < nkpt; i++) {
2345 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
2346 KASSERT(mpte >= vm_page_array &&
2347 mpte < &vm_page_array[vm_page_array_size],
2348 ("pmap_init: page table page is out of range"));
2349 mpte->pindex = pmap_pde_pindex(KERNBASE) + i;
2350 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
2351 mpte->ref_count = 1;
2354 * Collect the page table pages that were replaced by a 2MB
2355 * page in create_pagetables(). They are zero filled.
2357 if ((vm_paddr_t)i << PDRSHIFT < KERNend &&
2358 pmap_insert_pt_page(kernel_pmap, mpte, false))
2359 panic("pmap_init: pmap_insert_pt_page failed");
2361 PMAP_UNLOCK(kernel_pmap);
2365 * If the kernel is running on a virtual machine, then it must assume
2366 * that MCA is enabled by the hypervisor. Moreover, the kernel must
2367 * be prepared for the hypervisor changing the vendor and family that
2368 * are reported by CPUID. Consequently, the workaround for AMD Family
2369 * 10h Erratum 383 is enabled if the processor's feature set does not
2370 * include at least one feature that is only supported by older Intel
2371 * or newer AMD processors.
2373 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
2374 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
2375 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
2377 workaround_erratum383 = 1;
2380 * Are large page mappings enabled?
2382 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
2383 if (pg_ps_enabled) {
2384 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
2385 ("pmap_init: can't assign to pagesizes[1]"));
2386 pagesizes[1] = NBPDR;
2387 if ((amd_feature & AMDID_PAGE1GB) != 0) {
2388 KASSERT(MAXPAGESIZES > 2 && pagesizes[2] == 0,
2389 ("pmap_init: can't assign to pagesizes[2]"));
2390 pagesizes[2] = NBPDP;
2395 * Initialize pv chunk lists.
2397 for (i = 0; i < PMAP_MEMDOM; i++) {
2398 mtx_init(&pv_chunks[i].pvc_lock, "pmap pv chunk list", NULL, MTX_DEF);
2399 TAILQ_INIT(&pv_chunks[i].pvc_list);
2401 pmap_init_pv_table();
2403 pmap_initialized = 1;
2404 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
2405 ppim = pmap_preinit_mapping + i;
2408 /* Make the direct map consistent */
2409 if (ppim->pa < dmaplimit && ppim->pa + ppim->sz <= dmaplimit) {
2410 (void)pmap_change_attr(PHYS_TO_DMAP(ppim->pa),
2411 ppim->sz, ppim->mode);
2415 printf("PPIM %u: PA=%#lx, VA=%#lx, size=%#lx, mode=%#x\n", i,
2416 ppim->pa, ppim->va, ppim->sz, ppim->mode);
2419 mtx_init(&qframe_mtx, "qfrmlk", NULL, MTX_SPIN);
2420 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
2421 (vmem_addr_t *)&qframe);
2423 panic("qframe allocation failed");
2426 TUNABLE_INT_FETCH("vm.pmap.large_map_pml4_entries", &lm_ents);
2427 if (lm_ents > LMEPML4I - LMSPML4I + 1)
2428 lm_ents = LMEPML4I - LMSPML4I + 1;
2430 printf("pmap: large map %u PML4 slots (%lu GB)\n",
2431 lm_ents, (u_long)lm_ents * (NBPML4 / 1024 / 1024 / 1024));
2433 large_vmem = vmem_create("large", LARGEMAP_MIN_ADDRESS,
2434 (vmem_size_t)lm_ents * NBPML4, PAGE_SIZE, 0, M_WAITOK);
2435 if (large_vmem == NULL) {
2436 printf("pmap: cannot create large map\n");
2439 for (i = 0; i < lm_ents; i++) {
2440 m = pmap_large_map_getptp_unlocked();
2442 kernel_pml4[LMSPML4I + i] = X86_PG_V |
2443 X86_PG_RW | X86_PG_A | X86_PG_M | pg_nx |
2449 SYSCTL_UINT(_vm_pmap, OID_AUTO, large_map_pml4_entries,
2450 CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &lm_ents, 0,
2451 "Maximum number of PML4 entries for use by large map (tunable). "
2452 "Each entry corresponds to 512GB of address space.");
2454 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2455 "2MB page mapping counters");
2457 static u_long pmap_pde_demotions;
2458 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
2459 &pmap_pde_demotions, 0, "2MB page demotions");
2461 static u_long pmap_pde_mappings;
2462 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
2463 &pmap_pde_mappings, 0, "2MB page mappings");
2465 static u_long pmap_pde_p_failures;
2466 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
2467 &pmap_pde_p_failures, 0, "2MB page promotion failures");
2469 static u_long pmap_pde_promotions;
2470 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
2471 &pmap_pde_promotions, 0, "2MB page promotions");
2473 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pdpe, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
2474 "1GB page mapping counters");
2476 static u_long pmap_pdpe_demotions;
2477 SYSCTL_ULONG(_vm_pmap_pdpe, OID_AUTO, demotions, CTLFLAG_RD,
2478 &pmap_pdpe_demotions, 0, "1GB page demotions");
2480 /***************************************************
2481 * Low level helper routines.....
2482 ***************************************************/
2485 pmap_swap_pat(pmap_t pmap, pt_entry_t entry)
2487 int x86_pat_bits = X86_PG_PTE_PAT | X86_PG_PDE_PAT;
2489 switch (pmap->pm_type) {
2492 /* Verify that both PAT bits are not set at the same time */
2493 KASSERT((entry & x86_pat_bits) != x86_pat_bits,
2494 ("Invalid PAT bits in entry %#lx", entry));
2496 /* Swap the PAT bits if one of them is set */
2497 if ((entry & x86_pat_bits) != 0)
2498 entry ^= x86_pat_bits;
2502 * Nothing to do - the memory attributes are represented
2503 * the same way for regular pages and superpages.
2507 panic("pmap_switch_pat_bits: bad pm_type %d", pmap->pm_type);
2514 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
2517 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
2518 pat_index[(int)mode] >= 0);
2522 * Determine the appropriate bits to set in a PTE or PDE for a specified
2526 pmap_cache_bits(pmap_t pmap, int mode, boolean_t is_pde)
2528 int cache_bits, pat_flag, pat_idx;
2530 if (!pmap_is_valid_memattr(pmap, mode))
2531 panic("Unknown caching mode %d\n", mode);
2533 switch (pmap->pm_type) {
2536 /* The PAT bit is different for PTE's and PDE's. */
2537 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2539 /* Map the caching mode to a PAT index. */
2540 pat_idx = pat_index[mode];
2542 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
2545 cache_bits |= pat_flag;
2547 cache_bits |= PG_NC_PCD;
2549 cache_bits |= PG_NC_PWT;
2553 cache_bits = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(mode);
2557 panic("unsupported pmap type %d", pmap->pm_type);
2560 return (cache_bits);
2564 pmap_cache_mask(pmap_t pmap, boolean_t is_pde)
2568 switch (pmap->pm_type) {
2571 mask = is_pde ? X86_PG_PDE_CACHE : X86_PG_PTE_CACHE;
2574 mask = EPT_PG_IGNORE_PAT | EPT_PG_MEMORY_TYPE(0x7);
2577 panic("pmap_cache_mask: invalid pm_type %d", pmap->pm_type);
2584 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
2586 int pat_flag, pat_idx;
2589 switch (pmap->pm_type) {
2592 /* The PAT bit is different for PTE's and PDE's. */
2593 pat_flag = is_pde ? X86_PG_PDE_PAT : X86_PG_PTE_PAT;
2595 if ((pte & pat_flag) != 0)
2597 if ((pte & PG_NC_PCD) != 0)
2599 if ((pte & PG_NC_PWT) != 0)
2603 if ((pte & EPT_PG_IGNORE_PAT) != 0)
2604 panic("EPT PTE %#lx has no PAT memory type", pte);
2605 pat_idx = (pte & EPT_PG_MEMORY_TYPE(0x7)) >> 3;
2609 /* See pmap_init_pat(). */
2619 pmap_ps_enabled(pmap_t pmap)
2622 return (pg_ps_enabled && (pmap->pm_flags & PMAP_PDE_SUPERPAGE) != 0);
2626 pmap_update_pde_store(pmap_t pmap, pd_entry_t *pde, pd_entry_t newpde)
2629 switch (pmap->pm_type) {
2636 * This is a little bogus since the generation number is
2637 * supposed to be bumped up when a region of the address
2638 * space is invalidated in the page tables.
2640 * In this case the old PDE entry is valid but yet we want
2641 * to make sure that any mappings using the old entry are
2642 * invalidated in the TLB.
2644 * The reason this works as expected is because we rendezvous
2645 * "all" host cpus and force any vcpu context to exit as a
2648 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2651 panic("pmap_update_pde_store: bad pm_type %d", pmap->pm_type);
2653 pde_store(pde, newpde);
2657 * After changing the page size for the specified virtual address in the page
2658 * table, flush the corresponding entries from the processor's TLB. Only the
2659 * calling processor's TLB is affected.
2661 * The calling thread must be pinned to a processor.
2664 pmap_update_pde_invalidate(pmap_t pmap, vm_offset_t va, pd_entry_t newpde)
2668 if (pmap_type_guest(pmap))
2671 KASSERT(pmap->pm_type == PT_X86,
2672 ("pmap_update_pde_invalidate: invalid type %d", pmap->pm_type));
2674 PG_G = pmap_global_bit(pmap);
2676 if ((newpde & PG_PS) == 0)
2677 /* Demotion: flush a specific 2MB page mapping. */
2679 else if ((newpde & PG_G) == 0)
2681 * Promotion: flush every 4KB page mapping from the TLB
2682 * because there are too many to flush individually.
2687 * Promotion: flush every 4KB page mapping from the TLB,
2688 * including any global (PG_G) mappings.
2696 * For SMP, these functions have to use the IPI mechanism for coherence.
2698 * N.B.: Before calling any of the following TLB invalidation functions,
2699 * the calling processor must ensure that all stores updating a non-
2700 * kernel page table are globally performed. Otherwise, another
2701 * processor could cache an old, pre-update entry without being
2702 * invalidated. This can happen one of two ways: (1) The pmap becomes
2703 * active on another processor after its pm_active field is checked by
2704 * one of the following functions but before a store updating the page
2705 * table is globally performed. (2) The pmap becomes active on another
2706 * processor before its pm_active field is checked but due to
2707 * speculative loads one of the following functions stills reads the
2708 * pmap as inactive on the other processor.
2710 * The kernel page table is exempt because its pm_active field is
2711 * immutable. The kernel page table is always active on every
2716 * Interrupt the cpus that are executing in the guest context.
2717 * This will force the vcpu to exit and the cached EPT mappings
2718 * will be invalidated by the host before the next vmresume.
2720 static __inline void
2721 pmap_invalidate_ept(pmap_t pmap)
2726 KASSERT(!CPU_ISSET(curcpu, &pmap->pm_active),
2727 ("pmap_invalidate_ept: absurd pm_active"));
2730 * The TLB mappings associated with a vcpu context are not
2731 * flushed each time a different vcpu is chosen to execute.
2733 * This is in contrast with a process's vtop mappings that
2734 * are flushed from the TLB on each context switch.
2736 * Therefore we need to do more than just a TLB shootdown on
2737 * the active cpus in 'pmap->pm_active'. To do this we keep
2738 * track of the number of invalidations performed on this pmap.
2740 * Each vcpu keeps a cache of this counter and compares it
2741 * just before a vmresume. If the counter is out-of-date an
2742 * invept will be done to flush stale mappings from the TLB.
2744 atomic_add_acq_long(&pmap->pm_eptgen, 1);
2747 * Force the vcpu to exit and trap back into the hypervisor.
2749 ipinum = pmap->pm_flags & PMAP_NESTED_IPIMASK;
2750 ipi_selected(pmap->pm_active, ipinum);
2755 pmap_invalidate_cpu_mask(pmap_t pmap)
2758 return (pmap == kernel_pmap ? all_cpus : pmap->pm_active);
2762 pmap_invalidate_page_pcid(pmap_t pmap, vm_offset_t va,
2763 const bool invpcid_works1)
2765 struct invpcid_descr d;
2766 uint64_t kcr3, ucr3;
2770 cpuid = PCPU_GET(cpuid);
2771 if (pmap == PCPU_GET(curpmap)) {
2772 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2774 * If we context-switched right after
2775 * PCPU_GET(ucr3_load_mask), we could read the
2776 * ~CR3_PCID_SAVE mask, which causes us to skip
2777 * the code below to invalidate user pages. This
2778 * is handled in pmap_activate_sw_pcid_pti() by
2779 * clearing pm_gen if ucr3_load_mask is ~CR3_PCID_SAVE.
2781 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2783 * Because pm_pcid is recalculated on a
2784 * context switch, we must disable switching.
2785 * Otherwise, we might use a stale value
2789 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2790 if (invpcid_works1) {
2791 d.pcid = pcid | PMAP_PCID_USER_PT;
2794 invpcid(&d, INVPCID_ADDR);
2796 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2797 ucr3 = pmap->pm_ucr3 | pcid |
2798 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2799 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
2804 pmap->pm_pcids[cpuid].pm_gen = 0;
2808 pmap->pm_pcids[i].pm_gen = 0;
2812 * The fence is between stores to pm_gen and the read of the
2813 * pm_active mask. We need to ensure that it is impossible
2814 * for us to miss the bit update in pm_active and
2815 * simultaneously observe a non-zero pm_gen in
2816 * pmap_activate_sw(), otherwise TLB update is missed.
2817 * Without the fence, IA32 allows such an outcome. Note that
2818 * pm_active is updated by a locked operation, which provides
2819 * the reciprocal fence.
2821 atomic_thread_fence_seq_cst();
2825 pmap_invalidate_page_pcid_invpcid(pmap_t pmap, vm_offset_t va)
2828 pmap_invalidate_page_pcid(pmap, va, true);
2832 pmap_invalidate_page_pcid_noinvpcid(pmap_t pmap, vm_offset_t va)
2835 pmap_invalidate_page_pcid(pmap, va, false);
2839 pmap_invalidate_page_nopcid(pmap_t pmap, vm_offset_t va)
2843 DEFINE_IFUNC(static, void, pmap_invalidate_page_mode, (pmap_t, vm_offset_t))
2846 if (pmap_pcid_enabled)
2847 return (invpcid_works ? pmap_invalidate_page_pcid_invpcid :
2848 pmap_invalidate_page_pcid_noinvpcid);
2849 return (pmap_invalidate_page_nopcid);
2853 pmap_invalidate_page_curcpu_cb(pmap_t pmap, vm_offset_t va,
2854 vm_offset_t addr2 __unused)
2857 if (pmap == kernel_pmap) {
2860 if (pmap == PCPU_GET(curpmap))
2862 pmap_invalidate_page_mode(pmap, va);
2867 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
2870 if (pmap_type_guest(pmap)) {
2871 pmap_invalidate_ept(pmap);
2875 KASSERT(pmap->pm_type == PT_X86,
2876 ("pmap_invalidate_page: invalid type %d", pmap->pm_type));
2878 smp_masked_invlpg(pmap_invalidate_cpu_mask(pmap), va, pmap,
2879 pmap_invalidate_page_curcpu_cb);
2882 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
2883 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
2886 pmap_invalidate_range_pcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
2887 const bool invpcid_works1)
2889 struct invpcid_descr d;
2890 uint64_t kcr3, ucr3;
2894 cpuid = PCPU_GET(cpuid);
2895 if (pmap == PCPU_GET(curpmap)) {
2896 if (pmap->pm_ucr3 != PMAP_NO_CR3 &&
2897 PCPU_GET(ucr3_load_mask) == PMAP_UCR3_NOMASK) {
2899 pcid = pmap->pm_pcids[cpuid].pm_pcid;
2900 if (invpcid_works1) {
2901 d.pcid = pcid | PMAP_PCID_USER_PT;
2904 for (; d.addr < eva; d.addr += PAGE_SIZE)
2905 invpcid(&d, INVPCID_ADDR);
2907 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
2908 ucr3 = pmap->pm_ucr3 | pcid |
2909 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
2910 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
2915 pmap->pm_pcids[cpuid].pm_gen = 0;
2919 pmap->pm_pcids[i].pm_gen = 0;
2921 /* See the comment in pmap_invalidate_page_pcid(). */
2922 atomic_thread_fence_seq_cst();
2926 pmap_invalidate_range_pcid_invpcid(pmap_t pmap, vm_offset_t sva,
2930 pmap_invalidate_range_pcid(pmap, sva, eva, true);
2934 pmap_invalidate_range_pcid_noinvpcid(pmap_t pmap, vm_offset_t sva,
2938 pmap_invalidate_range_pcid(pmap, sva, eva, false);
2942 pmap_invalidate_range_nopcid(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2946 DEFINE_IFUNC(static, void, pmap_invalidate_range_mode, (pmap_t, vm_offset_t,
2950 if (pmap_pcid_enabled)
2951 return (invpcid_works ? pmap_invalidate_range_pcid_invpcid :
2952 pmap_invalidate_range_pcid_noinvpcid);
2953 return (pmap_invalidate_range_nopcid);
2957 pmap_invalidate_range_curcpu_cb(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2961 if (pmap == kernel_pmap) {
2962 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2965 if (pmap == PCPU_GET(curpmap)) {
2966 for (addr = sva; addr < eva; addr += PAGE_SIZE)
2969 pmap_invalidate_range_mode(pmap, sva, eva);
2974 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2977 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
2978 pmap_invalidate_all(pmap);
2982 if (pmap_type_guest(pmap)) {
2983 pmap_invalidate_ept(pmap);
2987 KASSERT(pmap->pm_type == PT_X86,
2988 ("pmap_invalidate_range: invalid type %d", pmap->pm_type));
2990 smp_masked_invlpg_range(pmap_invalidate_cpu_mask(pmap), sva, eva, pmap,
2991 pmap_invalidate_range_curcpu_cb);
2995 pmap_invalidate_all_pcid(pmap_t pmap, bool invpcid_works1)
2997 struct invpcid_descr d;
3002 if (pmap == kernel_pmap) {
3003 if (invpcid_works1) {
3004 bzero(&d, sizeof(d));
3005 invpcid(&d, INVPCID_CTXGLOB);
3010 cpuid = PCPU_GET(cpuid);
3011 if (pmap == PCPU_GET(curpmap)) {
3013 pcid = pmap->pm_pcids[cpuid].pm_pcid;
3014 if (invpcid_works1) {
3018 invpcid(&d, INVPCID_CTX);
3020 kcr3 = pmap->pm_cr3 | pcid;
3023 if (pmap->pm_ucr3 != PMAP_NO_CR3)
3024 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
3027 pmap->pm_pcids[cpuid].pm_gen = 0;
3030 pmap->pm_pcids[i].pm_gen = 0;
3033 /* See the comment in pmap_invalidate_page_pcid(). */
3034 atomic_thread_fence_seq_cst();
3038 pmap_invalidate_all_pcid_invpcid(pmap_t pmap)
3041 pmap_invalidate_all_pcid(pmap, true);
3045 pmap_invalidate_all_pcid_noinvpcid(pmap_t pmap)
3048 pmap_invalidate_all_pcid(pmap, false);
3052 pmap_invalidate_all_nopcid(pmap_t pmap)
3055 if (pmap == kernel_pmap)
3057 else if (pmap == PCPU_GET(curpmap))
3061 DEFINE_IFUNC(static, void, pmap_invalidate_all_mode, (pmap_t))
3064 if (pmap_pcid_enabled)
3065 return (invpcid_works ? pmap_invalidate_all_pcid_invpcid :
3066 pmap_invalidate_all_pcid_noinvpcid);
3067 return (pmap_invalidate_all_nopcid);
3071 pmap_invalidate_all_curcpu_cb(pmap_t pmap, vm_offset_t addr1 __unused,
3072 vm_offset_t addr2 __unused)
3075 pmap_invalidate_all_mode(pmap);
3079 pmap_invalidate_all(pmap_t pmap)
3082 if (pmap_type_guest(pmap)) {
3083 pmap_invalidate_ept(pmap);
3087 KASSERT(pmap->pm_type == PT_X86,
3088 ("pmap_invalidate_all: invalid type %d", pmap->pm_type));
3090 smp_masked_invltlb(pmap_invalidate_cpu_mask(pmap), pmap,
3091 pmap_invalidate_all_curcpu_cb);
3095 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused, vm_offset_t va __unused,
3096 vm_offset_t addr2 __unused)
3103 pmap_invalidate_cache(void)
3106 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
3110 cpuset_t invalidate; /* processors that invalidate their TLB */
3115 u_int store; /* processor that updates the PDE */
3119 pmap_update_pde_action(void *arg)
3121 struct pde_action *act = arg;
3123 if (act->store == PCPU_GET(cpuid))
3124 pmap_update_pde_store(act->pmap, act->pde, act->newpde);
3128 pmap_update_pde_teardown(void *arg)
3130 struct pde_action *act = arg;
3132 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
3133 pmap_update_pde_invalidate(act->pmap, act->va, act->newpde);
3137 * Change the page size for the specified virtual address in a way that
3138 * prevents any possibility of the TLB ever having two entries that map the
3139 * same virtual address using different page sizes. This is the recommended
3140 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
3141 * machine check exception for a TLB state that is improperly diagnosed as a
3145 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3147 struct pde_action act;
3148 cpuset_t active, other_cpus;
3152 cpuid = PCPU_GET(cpuid);
3153 other_cpus = all_cpus;
3154 CPU_CLR(cpuid, &other_cpus);
3155 if (pmap == kernel_pmap || pmap_type_guest(pmap))
3158 active = pmap->pm_active;
3160 if (CPU_OVERLAP(&active, &other_cpus)) {
3162 act.invalidate = active;
3166 act.newpde = newpde;
3167 CPU_SET(cpuid, &active);
3168 smp_rendezvous_cpus(active,
3169 smp_no_rendezvous_barrier, pmap_update_pde_action,
3170 pmap_update_pde_teardown, &act);
3172 pmap_update_pde_store(pmap, pde, newpde);
3173 if (CPU_ISSET(cpuid, &active))
3174 pmap_update_pde_invalidate(pmap, va, newpde);
3180 * Normal, non-SMP, invalidation functions.
3183 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
3185 struct invpcid_descr d;
3186 uint64_t kcr3, ucr3;
3189 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3193 KASSERT(pmap->pm_type == PT_X86,
3194 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3196 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3198 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3199 pmap->pm_ucr3 != PMAP_NO_CR3) {
3201 pcid = pmap->pm_pcids[0].pm_pcid;
3202 if (invpcid_works) {
3203 d.pcid = pcid | PMAP_PCID_USER_PT;
3206 invpcid(&d, INVPCID_ADDR);
3208 kcr3 = pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
3209 ucr3 = pmap->pm_ucr3 | pcid |
3210 PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3211 pmap_pti_pcid_invlpg(ucr3, kcr3, va);
3215 } else if (pmap_pcid_enabled)
3216 pmap->pm_pcids[0].pm_gen = 0;
3220 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3222 struct invpcid_descr d;
3224 uint64_t kcr3, ucr3;
3226 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3230 KASSERT(pmap->pm_type == PT_X86,
3231 ("pmap_invalidate_range: unknown type %d", pmap->pm_type));
3233 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap)) {
3234 for (addr = sva; addr < eva; addr += PAGE_SIZE)
3236 if (pmap == PCPU_GET(curpmap) && pmap_pcid_enabled &&
3237 pmap->pm_ucr3 != PMAP_NO_CR3) {
3239 if (invpcid_works) {
3240 d.pcid = pmap->pm_pcids[0].pm_pcid |
3244 for (; d.addr < eva; d.addr += PAGE_SIZE)
3245 invpcid(&d, INVPCID_ADDR);
3247 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].
3248 pm_pcid | CR3_PCID_SAVE;
3249 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[0].
3250 pm_pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
3251 pmap_pti_pcid_invlrng(ucr3, kcr3, sva, eva);
3255 } else if (pmap_pcid_enabled) {
3256 pmap->pm_pcids[0].pm_gen = 0;
3261 pmap_invalidate_all(pmap_t pmap)
3263 struct invpcid_descr d;
3264 uint64_t kcr3, ucr3;
3266 if (pmap->pm_type == PT_RVI || pmap->pm_type == PT_EPT) {
3270 KASSERT(pmap->pm_type == PT_X86,
3271 ("pmap_invalidate_all: unknown type %d", pmap->pm_type));
3273 if (pmap == kernel_pmap) {
3274 if (pmap_pcid_enabled && invpcid_works) {
3275 bzero(&d, sizeof(d));
3276 invpcid(&d, INVPCID_CTXGLOB);
3280 } else if (pmap == PCPU_GET(curpmap)) {
3281 if (pmap_pcid_enabled) {
3283 if (invpcid_works) {
3284 d.pcid = pmap->pm_pcids[0].pm_pcid;
3287 invpcid(&d, INVPCID_CTX);
3288 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3289 d.pcid |= PMAP_PCID_USER_PT;
3290 invpcid(&d, INVPCID_CTX);
3293 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[0].pm_pcid;
3294 if (pmap->pm_ucr3 != PMAP_NO_CR3) {
3295 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[
3296 0].pm_pcid | PMAP_PCID_USER_PT;
3297 pmap_pti_pcid_invalidate(ucr3, kcr3);
3305 } else if (pmap_pcid_enabled) {
3306 pmap->pm_pcids[0].pm_gen = 0;
3311 pmap_invalidate_cache(void)
3318 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
3321 pmap_update_pde_store(pmap, pde, newpde);
3322 if (pmap == kernel_pmap || pmap == PCPU_GET(curpmap))
3323 pmap_update_pde_invalidate(pmap, va, newpde);
3325 pmap->pm_pcids[0].pm_gen = 0;
3330 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
3334 * When the PDE has PG_PROMOTED set, the 2MB page mapping was created
3335 * by a promotion that did not invalidate the 512 4KB page mappings
3336 * that might exist in the TLB. Consequently, at this point, the TLB
3337 * may hold both 4KB and 2MB page mappings for the address range [va,
3338 * va + NBPDR). Therefore, the entire range must be invalidated here.
3339 * In contrast, when PG_PROMOTED is clear, the TLB will not hold any
3340 * 4KB page mappings for the address range [va, va + NBPDR), and so a
3341 * single INVLPG suffices to invalidate the 2MB page mapping from the
3344 if ((pde & PG_PROMOTED) != 0)
3345 pmap_invalidate_range(pmap, va, va + NBPDR - 1);
3347 pmap_invalidate_page(pmap, va);
3350 DEFINE_IFUNC(, void, pmap_invalidate_cache_range,
3351 (vm_offset_t sva, vm_offset_t eva))
3354 if ((cpu_feature & CPUID_SS) != 0)
3355 return (pmap_invalidate_cache_range_selfsnoop);
3356 if ((cpu_feature & CPUID_CLFSH) != 0)
3357 return (pmap_force_invalidate_cache_range);
3358 return (pmap_invalidate_cache_range_all);
3361 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
3364 pmap_invalidate_cache_range_check_align(vm_offset_t sva, vm_offset_t eva)
3367 KASSERT((sva & PAGE_MASK) == 0,
3368 ("pmap_invalidate_cache_range: sva not page-aligned"));
3369 KASSERT((eva & PAGE_MASK) == 0,
3370 ("pmap_invalidate_cache_range: eva not page-aligned"));
3374 pmap_invalidate_cache_range_selfsnoop(vm_offset_t sva, vm_offset_t eva)
3377 pmap_invalidate_cache_range_check_align(sva, eva);
3381 pmap_force_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
3384 sva &= ~(vm_offset_t)(cpu_clflush_line_size - 1);
3387 * XXX: Some CPUs fault, hang, or trash the local APIC
3388 * registers if we use CLFLUSH on the local APIC range. The
3389 * local APIC is always uncached, so we don't need to flush
3390 * for that range anyway.
3392 if (pmap_kextract(sva) == lapic_paddr)
3395 if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0) {
3397 * Do per-cache line flush. Use a locked
3398 * instruction to insure that previous stores are
3399 * included in the write-back. The processor
3400 * propagates flush to other processors in the cache
3403 atomic_thread_fence_seq_cst();
3404 for (; sva < eva; sva += cpu_clflush_line_size)
3406 atomic_thread_fence_seq_cst();
3409 * Writes are ordered by CLFLUSH on Intel CPUs.
3411 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3413 for (; sva < eva; sva += cpu_clflush_line_size)
3415 if (cpu_vendor_id != CPU_VENDOR_INTEL)
3421 pmap_invalidate_cache_range_all(vm_offset_t sva, vm_offset_t eva)
3424 pmap_invalidate_cache_range_check_align(sva, eva);
3425 pmap_invalidate_cache();
3429 * Remove the specified set of pages from the data and instruction caches.
3431 * In contrast to pmap_invalidate_cache_range(), this function does not
3432 * rely on the CPU's self-snoop feature, because it is intended for use
3433 * when moving pages into a different cache domain.
3436 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
3438 vm_offset_t daddr, eva;
3442 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
3443 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
3444 ((cpu_feature & CPUID_CLFSH) == 0 && !useclflushopt))
3445 pmap_invalidate_cache();
3448 atomic_thread_fence_seq_cst();
3449 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3451 for (i = 0; i < count; i++) {
3452 daddr = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pages[i]));
3453 eva = daddr + PAGE_SIZE;
3454 for (; daddr < eva; daddr += cpu_clflush_line_size) {
3462 atomic_thread_fence_seq_cst();
3463 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
3469 pmap_flush_cache_range(vm_offset_t sva, vm_offset_t eva)
3472 pmap_invalidate_cache_range_check_align(sva, eva);
3474 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) == 0) {
3475 pmap_force_invalidate_cache_range(sva, eva);
3479 /* See comment in pmap_force_invalidate_cache_range(). */
3480 if (pmap_kextract(sva) == lapic_paddr)
3483 atomic_thread_fence_seq_cst();
3484 for (; sva < eva; sva += cpu_clflush_line_size)
3486 atomic_thread_fence_seq_cst();
3490 pmap_flush_cache_phys_range(vm_paddr_t spa, vm_paddr_t epa, vm_memattr_t mattr)
3494 int error, pte_bits;
3496 KASSERT((spa & PAGE_MASK) == 0,
3497 ("pmap_flush_cache_phys_range: spa not page-aligned"));
3498 KASSERT((epa & PAGE_MASK) == 0,
3499 ("pmap_flush_cache_phys_range: epa not page-aligned"));
3501 if (spa < dmaplimit) {
3502 pmap_flush_cache_range(PHYS_TO_DMAP(spa), PHYS_TO_DMAP(MIN(
3504 if (dmaplimit >= epa)
3509 pte_bits = pmap_cache_bits(kernel_pmap, mattr, 0) | X86_PG_RW |
3511 error = vmem_alloc(kernel_arena, PAGE_SIZE, M_BESTFIT | M_WAITOK,
3513 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
3514 pte = vtopte(vaddr);
3515 for (; spa < epa; spa += PAGE_SIZE) {
3517 pte_store(pte, spa | pte_bits);
3519 /* XXXKIB atomic inside flush_cache_range are excessive */
3520 pmap_flush_cache_range(vaddr, vaddr + PAGE_SIZE);
3523 vmem_free(kernel_arena, vaddr, PAGE_SIZE);
3527 * Routine: pmap_extract
3529 * Extract the physical page address associated
3530 * with the given map/virtual_address pair.
3533 pmap_extract(pmap_t pmap, vm_offset_t va)
3537 pt_entry_t *pte, PG_V;
3541 PG_V = pmap_valid_bit(pmap);
3543 pdpe = pmap_pdpe(pmap, va);
3544 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
3545 if ((*pdpe & PG_PS) != 0)
3546 pa = (*pdpe & PG_PS_FRAME) | (va & PDPMASK);
3548 pde = pmap_pdpe_to_pde(pdpe, va);
3549 if ((*pde & PG_V) != 0) {
3550 if ((*pde & PG_PS) != 0) {
3551 pa = (*pde & PG_PS_FRAME) |
3554 pte = pmap_pde_to_pte(pde, va);
3555 pa = (*pte & PG_FRAME) |
3566 * Routine: pmap_extract_and_hold
3568 * Atomically extract and hold the physical page
3569 * with the given pmap and virtual address pair
3570 * if that mapping permits the given protection.
3573 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
3575 pdp_entry_t pdpe, *pdpep;
3576 pd_entry_t pde, *pdep;
3577 pt_entry_t pte, PG_RW, PG_V;
3581 PG_RW = pmap_rw_bit(pmap);
3582 PG_V = pmap_valid_bit(pmap);
3585 pdpep = pmap_pdpe(pmap, va);
3586 if (pdpep == NULL || ((pdpe = *pdpep) & PG_V) == 0)
3588 if ((pdpe & PG_PS) != 0) {
3589 if ((pdpe & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3591 m = PHYS_TO_VM_PAGE((pdpe & PG_PS_FRAME) | (va & PDPMASK));
3595 pdep = pmap_pdpe_to_pde(pdpep, va);
3596 if (pdep == NULL || ((pde = *pdep) & PG_V) == 0)
3598 if ((pde & PG_PS) != 0) {
3599 if ((pde & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0)
3601 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | (va & PDRMASK));
3605 pte = *pmap_pde_to_pte(pdep, va);
3606 if ((pte & PG_V) == 0 ||
3607 ((pte & PG_RW) == 0 && (prot & VM_PROT_WRITE) != 0))
3609 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
3612 if (m != NULL && !vm_page_wire_mapped(m))
3620 pmap_kextract(vm_offset_t va)
3625 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS) {
3626 pa = DMAP_TO_PHYS(va);
3627 } else if (PMAP_ADDRESS_IN_LARGEMAP(va)) {
3628 pa = pmap_large_map_kextract(va);
3632 pa = (pde & PG_PS_FRAME) | (va & PDRMASK);
3635 * Beware of a concurrent promotion that changes the
3636 * PDE at this point! For example, vtopte() must not
3637 * be used to access the PTE because it would use the
3638 * new PDE. It is, however, safe to use the old PDE
3639 * because the page table page is preserved by the
3642 pa = *pmap_pde_to_pte(&pde, va);
3643 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
3649 /***************************************************
3650 * Low level mapping routines.....
3651 ***************************************************/
3654 * Add a wired page to the kva.
3655 * Note: not SMP coherent.
3658 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
3663 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx);
3666 static __inline void
3667 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
3673 cache_bits = pmap_cache_bits(kernel_pmap, mode, 0);
3674 pte_store(pte, pa | X86_PG_RW | X86_PG_V | pg_g | pg_nx | cache_bits);
3678 * Remove a page from the kernel pagetables.
3679 * Note: not SMP coherent.
3682 pmap_kremove(vm_offset_t va)
3691 * Used to map a range of physical addresses into kernel
3692 * virtual address space.
3694 * The value passed in '*virt' is a suggested virtual address for
3695 * the mapping. Architectures which can support a direct-mapped
3696 * physical to virtual region can return the appropriate address
3697 * within that region, leaving '*virt' unchanged. Other
3698 * architectures should map the pages starting at '*virt' and
3699 * update '*virt' with the first usable address after the mapped
3703 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
3705 return PHYS_TO_DMAP(start);
3709 * Add a list of wired pages to the kva
3710 * this routine is only used for temporary
3711 * kernel mappings that do not need to have
3712 * page modification or references recorded.
3713 * Note that old mappings are simply written
3714 * over. The page *must* be wired.
3715 * Note: SMP coherent. Uses a ranged shootdown IPI.
3718 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
3720 pt_entry_t *endpte, oldpte, pa, *pte;
3726 endpte = pte + count;
3727 while (pte < endpte) {
3729 cache_bits = pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0);
3730 pa = VM_PAGE_TO_PHYS(m) | cache_bits;
3731 if ((*pte & (PG_FRAME | X86_PG_PTE_CACHE)) != pa) {
3733 pte_store(pte, pa | pg_g | pg_nx | X86_PG_RW | X86_PG_V);
3737 if (__predict_false((oldpte & X86_PG_V) != 0))
3738 pmap_invalidate_range(kernel_pmap, sva, sva + count *
3743 * This routine tears out page mappings from the
3744 * kernel -- it is meant only for temporary mappings.
3745 * Note: SMP coherent. Uses a ranged shootdown IPI.
3748 pmap_qremove(vm_offset_t sva, int count)
3753 while (count-- > 0) {
3754 KASSERT(va >= VM_MIN_KERNEL_ADDRESS, ("usermode va %lx", va));
3758 pmap_invalidate_range(kernel_pmap, sva, va);
3761 /***************************************************
3762 * Page table page management routines.....
3763 ***************************************************/
3765 * Schedule the specified unused page table page to be freed. Specifically,
3766 * add the page to the specified list of pages that will be released to the
3767 * physical memory manager after the TLB has been updated.
3769 static __inline void
3770 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
3771 boolean_t set_PG_ZERO)
3775 m->flags |= PG_ZERO;
3777 m->flags &= ~PG_ZERO;
3778 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
3782 * Inserts the specified page table page into the specified pmap's collection
3783 * of idle page table pages. Each of a pmap's page table pages is responsible
3784 * for mapping a distinct range of virtual addresses. The pmap's collection is
3785 * ordered by this virtual address range.
3787 * If "promoted" is false, then the page table page "mpte" must be zero filled.
3790 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted)
3793 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3794 mpte->valid = promoted ? VM_PAGE_BITS_ALL : 0;
3795 return (vm_radix_insert(&pmap->pm_root, mpte));
3799 * Removes the page table page mapping the specified virtual address from the
3800 * specified pmap's collection of idle page table pages, and returns it.
3801 * Otherwise, returns NULL if there is no page table page corresponding to the
3802 * specified virtual address.
3804 static __inline vm_page_t
3805 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
3808 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3809 return (vm_radix_remove(&pmap->pm_root, pmap_pde_pindex(va)));
3813 * Decrements a page table page's reference count, which is used to record the
3814 * number of valid page table entries within the page. If the reference count
3815 * drops to zero, then the page table page is unmapped. Returns TRUE if the
3816 * page table page was unmapped and FALSE otherwise.
3818 static inline boolean_t
3819 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3823 if (m->ref_count == 0) {
3824 _pmap_unwire_ptp(pmap, va, m, free);
3831 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m, struct spglist *free)
3837 vm_page_t pdpg, pdppg, pml4pg;
3839 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3842 * unmap the page table page
3844 if (m->pindex >= NUPDE + NUPDPE + NUPML4E) {
3846 MPASS(pmap_is_la57(pmap));
3847 pml5 = pmap_pml5e(pmap, va);
3849 if (pmap->pm_pmltopu != NULL && va <= VM_MAXUSER_ADDRESS) {
3850 pml5 = pmap_pml5e_u(pmap, va);
3853 } else if (m->pindex >= NUPDE + NUPDPE) {
3855 pml4 = pmap_pml4e(pmap, va);
3857 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
3858 va <= VM_MAXUSER_ADDRESS) {
3859 pml4 = pmap_pml4e_u(pmap, va);
3862 } else if (m->pindex >= NUPDE) {
3864 pdp = pmap_pdpe(pmap, va);
3868 pd = pmap_pde(pmap, va);
3871 pmap_resident_count_dec(pmap, 1);
3872 if (m->pindex < NUPDE) {
3873 /* We just released a PT, unhold the matching PD */
3874 pdpg = PHYS_TO_VM_PAGE(*pmap_pdpe(pmap, va) & PG_FRAME);
3875 pmap_unwire_ptp(pmap, va, pdpg, free);
3876 } else if (m->pindex < NUPDE + NUPDPE) {
3877 /* We just released a PD, unhold the matching PDP */
3878 pdppg = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, va) & PG_FRAME);
3879 pmap_unwire_ptp(pmap, va, pdppg, free);
3880 } else if (m->pindex < NUPDE + NUPDPE + NUPML4E && pmap_is_la57(pmap)) {
3881 /* We just released a PDP, unhold the matching PML4 */
3882 pml4pg = PHYS_TO_VM_PAGE(*pmap_pml5e(pmap, va) & PG_FRAME);
3883 pmap_unwire_ptp(pmap, va, pml4pg, free);
3887 * Put page on a list so that it is released after
3888 * *ALL* TLB shootdown is done
3890 pmap_add_delayed_free_list(m, free, TRUE);
3894 * After removing a page table entry, this routine is used to
3895 * conditionally free the page, and manage the reference count.
3898 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t ptepde,
3899 struct spglist *free)
3903 if (va >= VM_MAXUSER_ADDRESS)
3905 KASSERT(ptepde != 0, ("pmap_unuse_pt: ptepde != 0"));
3906 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
3907 return (pmap_unwire_ptp(pmap, va, mpte, free));
3911 * Release a page table page reference after a failed attempt to create a
3915 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
3917 struct spglist free;
3920 if (pmap_unwire_ptp(pmap, va, mpte, &free)) {
3922 * Although "va" was never mapped, paging-structure caches
3923 * could nonetheless have entries that refer to the freed
3924 * page table pages. Invalidate those entries.
3926 pmap_invalidate_page(pmap, va);
3927 vm_page_free_pages_toq(&free, true);
3932 pmap_pinit0(pmap_t pmap)
3938 PMAP_LOCK_INIT(pmap);
3939 pmap->pm_pmltop = kernel_pmap->pm_pmltop;
3940 pmap->pm_pmltopu = NULL;
3941 pmap->pm_cr3 = kernel_pmap->pm_cr3;
3942 /* hack to keep pmap_pti_pcid_invalidate() alive */
3943 pmap->pm_ucr3 = PMAP_NO_CR3;
3944 pmap->pm_root.rt_root = 0;
3945 CPU_ZERO(&pmap->pm_active);
3946 TAILQ_INIT(&pmap->pm_pvchunk);
3947 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
3948 pmap->pm_flags = pmap_flags;
3950 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_KERN + 1;
3951 pmap->pm_pcids[i].pm_gen = 1;
3953 pmap_activate_boot(pmap);
3958 p->p_md.md_flags |= P_MD_KPTI;
3961 pmap_thread_init_invl_gen(td);
3963 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
3964 pmap_pkru_ranges_zone = uma_zcreate("pkru ranges",
3965 sizeof(struct pmap_pkru_range), NULL, NULL, NULL, NULL,
3971 pmap_pinit_pml4(vm_page_t pml4pg)
3973 pml4_entry_t *pm_pml4;
3976 pm_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pg));
3978 /* Wire in kernel global address entries. */
3979 for (i = 0; i < NKPML4E; i++) {
3980 pm_pml4[KPML4BASE + i] = (KPDPphys + ptoa(i)) | X86_PG_RW |
3983 for (i = 0; i < ndmpdpphys; i++) {
3984 pm_pml4[DMPML4I + i] = (DMPDPphys + ptoa(i)) | X86_PG_RW |
3988 /* install self-referential address mapping entry(s) */
3989 pm_pml4[PML4PML4I] = VM_PAGE_TO_PHYS(pml4pg) | X86_PG_V | X86_PG_RW |
3990 X86_PG_A | X86_PG_M;
3992 /* install large map entries if configured */
3993 for (i = 0; i < lm_ents; i++)
3994 pm_pml4[LMSPML4I + i] = kernel_pmap->pm_pmltop[LMSPML4I + i];
3998 pmap_pinit_pml5(vm_page_t pml5pg)
4000 pml5_entry_t *pm_pml5;
4002 pm_pml5 = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pg));
4005 * Add pml5 entry at top of KVA pointing to existing pml4 table,
4006 * entering all existing kernel mappings into level 5 table.
4008 pm_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
4009 X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4010 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4013 * Install self-referential address mapping entry.
4015 pm_pml5[PML5PML5I] = VM_PAGE_TO_PHYS(pml5pg) |
4016 X86_PG_RW | X86_PG_V | X86_PG_M | X86_PG_A |
4017 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4021 pmap_pinit_pml4_pti(vm_page_t pml4pgu)
4023 pml4_entry_t *pm_pml4u;
4026 pm_pml4u = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4pgu));
4027 for (i = 0; i < NPML4EPG; i++)
4028 pm_pml4u[i] = pti_pml4[i];
4032 pmap_pinit_pml5_pti(vm_page_t pml5pgu)
4034 pml5_entry_t *pm_pml5u;
4036 pm_pml5u = (pml5_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml5pgu));
4039 * Add pml5 entry at top of KVA pointing to existing pml4 pti
4040 * table, entering all kernel mappings needed for usermode
4041 * into level 5 table.
4043 pm_pml5u[pmap_pml5e_index(UPT_MAX_ADDRESS)] =
4044 pmap_kextract((vm_offset_t)pti_pml4) |
4045 X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M | pg_g |
4046 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, FALSE);
4050 * Initialize a preallocated and zeroed pmap structure,
4051 * such as one in a vmspace structure.
4054 pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags)
4056 vm_page_t pmltop_pg, pmltop_pgu;
4057 vm_paddr_t pmltop_phys;
4061 * allocate the page directory page
4063 pmltop_pg = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
4064 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
4066 pmltop_phys = VM_PAGE_TO_PHYS(pmltop_pg);
4067 pmap->pm_pmltop = (pml5_entry_t *)PHYS_TO_DMAP(pmltop_phys);
4070 pmap->pm_pcids[i].pm_pcid = PMAP_PCID_NONE;
4071 pmap->pm_pcids[i].pm_gen = 0;
4073 pmap->pm_cr3 = PMAP_NO_CR3; /* initialize to an invalid value */
4074 pmap->pm_ucr3 = PMAP_NO_CR3;
4075 pmap->pm_pmltopu = NULL;
4077 pmap->pm_type = pm_type;
4078 if ((pmltop_pg->flags & PG_ZERO) == 0)
4079 pagezero(pmap->pm_pmltop);
4082 * Do not install the host kernel mappings in the nested page
4083 * tables. These mappings are meaningless in the guest physical
4085 * Install minimal kernel mappings in PTI case.
4087 if (pm_type == PT_X86) {
4088 pmap->pm_cr3 = pmltop_phys;
4089 if (pmap_is_la57(pmap))
4090 pmap_pinit_pml5(pmltop_pg);
4092 pmap_pinit_pml4(pmltop_pg);
4093 if ((curproc->p_md.md_flags & P_MD_KPTI) != 0) {
4094 pmltop_pgu = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
4095 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
4096 pmap->pm_pmltopu = (pml4_entry_t *)PHYS_TO_DMAP(
4097 VM_PAGE_TO_PHYS(pmltop_pgu));
4098 if (pmap_is_la57(pmap))
4099 pmap_pinit_pml5_pti(pmltop_pgu);
4101 pmap_pinit_pml4_pti(pmltop_pgu);
4102 pmap->pm_ucr3 = VM_PAGE_TO_PHYS(pmltop_pgu);
4104 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
4105 rangeset_init(&pmap->pm_pkru, pkru_dup_range,
4106 pkru_free_range, pmap, M_NOWAIT);
4110 pmap->pm_root.rt_root = 0;
4111 CPU_ZERO(&pmap->pm_active);
4112 TAILQ_INIT(&pmap->pm_pvchunk);
4113 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
4114 pmap->pm_flags = flags;
4115 pmap->pm_eptgen = 0;
4121 pmap_pinit(pmap_t pmap)
4124 return (pmap_pinit_type(pmap, PT_X86, pmap_flags));
4128 pmap_allocpte_free_unref(pmap_t pmap, vm_offset_t va, pt_entry_t *pte)
4131 struct spglist free;
4133 mpg = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4134 if (mpg->ref_count != 0)
4137 _pmap_unwire_ptp(pmap, va, mpg, &free);
4138 pmap_invalidate_page(pmap, va);
4139 vm_page_free_pages_toq(&free, true);
4142 static pml4_entry_t *
4143 pmap_allocpte_getpml4(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4146 vm_pindex_t pml5index;
4153 if (!pmap_is_la57(pmap))
4154 return (&pmap->pm_pmltop[pmap_pml4e_index(va)]);
4156 PG_V = pmap_valid_bit(pmap);
4157 pml5index = pmap_pml5e_index(va);
4158 pml5 = &pmap->pm_pmltop[pml5index];
4159 if ((*pml5 & PG_V) == 0) {
4160 if (_pmap_allocpte(pmap, pmap_pml5e_pindex(va), lockp, va) ==
4167 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(*pml5 & PG_FRAME);
4168 pml4 = &pml4[pmap_pml4e_index(va)];
4169 if ((*pml4 & PG_V) == 0) {
4170 pml4pg = PHYS_TO_VM_PAGE(*pml5 & PG_FRAME);
4171 if (allocated && !addref)
4172 pml4pg->ref_count--;
4173 else if (!allocated && addref)
4174 pml4pg->ref_count++;
4179 static pdp_entry_t *
4180 pmap_allocpte_getpdp(pmap_t pmap, struct rwlock **lockp, vm_offset_t va,
4189 PG_V = pmap_valid_bit(pmap);
4191 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, false);
4195 if ((*pml4 & PG_V) == 0) {
4196 /* Have to allocate a new pdp, recurse */
4197 if (_pmap_allocpte(pmap, pmap_pml4e_pindex(va), lockp, va) ==
4199 if (pmap_is_la57(pmap))
4200 pmap_allocpte_free_unref(pmap, va,
4201 pmap_pml5e(pmap, va));
4208 pdp = (pdp_entry_t *)PHYS_TO_DMAP(*pml4 & PG_FRAME);
4209 pdp = &pdp[pmap_pdpe_index(va)];
4210 if ((*pdp & PG_V) == 0) {
4211 pdppg = PHYS_TO_VM_PAGE(*pml4 & PG_FRAME);
4212 if (allocated && !addref)
4214 else if (!allocated && addref)
4221 * This routine is called if the desired page table page does not exist.
4223 * If page table page allocation fails, this routine may sleep before
4224 * returning NULL. It sleeps only if a lock pointer was given.
4226 * Note: If a page allocation fails at page table level two, three, or four,
4227 * up to three pages may be held during the wait, only to be released
4228 * afterwards. This conservative approach is easily argued to avoid
4231 * The ptepindexes, i.e. page indices, of the page table pages encountered
4232 * while translating virtual address va are defined as follows:
4233 * - for the page table page (last level),
4234 * ptepindex = pmap_pde_pindex(va) = va >> PDRSHIFT,
4235 * in other words, it is just the index of the PDE that maps the page
4237 * - for the page directory page,
4238 * ptepindex = NUPDE (number of userland PD entries) +
4239 * (pmap_pde_index(va) >> NPDEPGSHIFT)
4240 * i.e. index of PDPE is put after the last index of PDE,
4241 * - for the page directory pointer page,
4242 * ptepindex = NUPDE + NUPDPE + (pmap_pde_index(va) >> (NPDEPGSHIFT +
4244 * i.e. index of pml4e is put after the last index of PDPE,
4245 * - for the PML4 page (if LA57 mode is enabled),
4246 * ptepindex = NUPDE + NUPDPE + NUPML4E + (pmap_pde_index(va) >>
4247 * (NPDEPGSHIFT + NPML4EPGSHIFT + NPML5EPGSHIFT),
4248 * i.e. index of pml5e is put after the last index of PML4E.
4250 * Define an order on the paging entries, where all entries of the
4251 * same height are put together, then heights are put from deepest to
4252 * root. Then ptexpindex is the sequential number of the
4253 * corresponding paging entry in this order.
4255 * The values of NUPDE, NUPDPE, and NUPML4E are determined by the size of
4256 * LA57 paging structures even in LA48 paging mode. Moreover, the
4257 * ptepindexes are calculated as if the paging structures were 5-level
4258 * regardless of the actual mode of operation.
4260 * The root page at PML4/PML5 does not participate in this indexing scheme,
4261 * since it is statically allocated by pmap_pinit() and not by _pmap_allocpte().
4264 _pmap_allocpte(pmap_t pmap, vm_pindex_t ptepindex, struct rwlock **lockp,
4265 vm_offset_t va __unused)
4267 vm_pindex_t pml5index, pml4index;
4268 pml5_entry_t *pml5, *pml5u;
4269 pml4_entry_t *pml4, *pml4u;
4273 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
4275 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4277 PG_A = pmap_accessed_bit(pmap);
4278 PG_M = pmap_modified_bit(pmap);
4279 PG_V = pmap_valid_bit(pmap);
4280 PG_RW = pmap_rw_bit(pmap);
4283 * Allocate a page table page.
4285 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
4286 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
4287 if (lockp != NULL) {
4288 RELEASE_PV_LIST_LOCK(lockp);
4290 PMAP_ASSERT_NOT_IN_DI();
4296 * Indicate the need to retry. While waiting, the page table
4297 * page may have been allocated.
4301 if ((m->flags & PG_ZERO) == 0)
4305 * Map the pagetable page into the process address space, if
4306 * it isn't already there.
4308 if (ptepindex >= NUPDE + NUPDPE + NUPML4E) {
4309 MPASS(pmap_is_la57(pmap));
4311 pml5index = pmap_pml5e_index(va);
4312 pml5 = &pmap->pm_pmltop[pml5index];
4313 KASSERT((*pml5 & PG_V) == 0,
4314 ("pmap %p va %#lx pml5 %#lx", pmap, va, *pml5));
4315 *pml5 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4317 if (pmap->pm_pmltopu != NULL && pml5index < NUPML5E) {
4318 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4321 pml5u = &pmap->pm_pmltopu[pml5index];
4322 *pml5u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4325 } else if (ptepindex >= NUPDE + NUPDPE) {
4326 pml4index = pmap_pml4e_index(va);
4327 /* Wire up a new PDPE page */
4328 pml4 = pmap_allocpte_getpml4(pmap, lockp, va, true);
4330 vm_page_unwire_noq(m);
4331 vm_page_free_zero(m);
4334 KASSERT((*pml4 & PG_V) == 0,
4335 ("pmap %p va %#lx pml4 %#lx", pmap, va, *pml4));
4336 *pml4 = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4338 if (!pmap_is_la57(pmap) && pmap->pm_pmltopu != NULL &&
4339 pml4index < NUPML4E) {
4341 * PTI: Make all user-space mappings in the
4342 * kernel-mode page table no-execute so that
4343 * we detect any programming errors that leave
4344 * the kernel-mode page table active on return
4347 if (pmap->pm_ucr3 != PMAP_NO_CR3)
4350 pml4u = &pmap->pm_pmltopu[pml4index];
4351 *pml4u = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V |
4354 } else if (ptepindex >= NUPDE) {
4355 /* Wire up a new PDE page */
4356 pdp = pmap_allocpte_getpdp(pmap, lockp, va, true);
4358 vm_page_unwire_noq(m);
4359 vm_page_free_zero(m);
4362 KASSERT((*pdp & PG_V) == 0,
4363 ("pmap %p va %#lx pdp %#lx", pmap, va, *pdp));
4364 *pdp = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4366 /* Wire up a new PTE page */
4367 pdp = pmap_allocpte_getpdp(pmap, lockp, va, false);
4369 vm_page_unwire_noq(m);
4370 vm_page_free_zero(m);
4373 if ((*pdp & PG_V) == 0) {
4374 /* Have to allocate a new pd, recurse */
4375 if (_pmap_allocpte(pmap, pmap_pdpe_pindex(va),
4376 lockp, va) == NULL) {
4377 pmap_allocpte_free_unref(pmap, va,
4378 pmap_pml4e(pmap, va));
4379 vm_page_unwire_noq(m);
4380 vm_page_free_zero(m);
4384 /* Add reference to the pd page */
4385 pdpg = PHYS_TO_VM_PAGE(*pdp & PG_FRAME);
4388 pd = (pd_entry_t *)PHYS_TO_DMAP(*pdp & PG_FRAME);
4390 /* Now we know where the page directory page is */
4391 pd = &pd[pmap_pde_index(va)];
4392 KASSERT((*pd & PG_V) == 0,
4393 ("pmap %p va %#lx pd %#lx", pmap, va, *pd));
4394 *pd = VM_PAGE_TO_PHYS(m) | PG_U | PG_RW | PG_V | PG_A | PG_M;
4397 pmap_resident_count_inc(pmap, 1);
4403 pmap_alloc_pde(pmap_t pmap, vm_offset_t va, vm_page_t *pdpgp,
4404 struct rwlock **lockp)
4406 pdp_entry_t *pdpe, PG_V;
4409 vm_pindex_t pdpindex;
4411 PG_V = pmap_valid_bit(pmap);
4414 pdpe = pmap_pdpe(pmap, va);
4415 if (pdpe != NULL && (*pdpe & PG_V) != 0) {
4416 pde = pmap_pdpe_to_pde(pdpe, va);
4417 if (va < VM_MAXUSER_ADDRESS) {
4418 /* Add a reference to the pd page. */
4419 pdpg = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
4423 } else if (va < VM_MAXUSER_ADDRESS) {
4424 /* Allocate a pd page. */
4425 pdpindex = pmap_pde_pindex(va) >> NPDPEPGSHIFT;
4426 pdpg = _pmap_allocpte(pmap, NUPDE + pdpindex, lockp, va);
4433 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pdpg));
4434 pde = &pde[pmap_pde_index(va)];
4436 panic("pmap_alloc_pde: missing page table page for va %#lx",
4443 pmap_allocpte(pmap_t pmap, vm_offset_t va, struct rwlock **lockp)
4445 vm_pindex_t ptepindex;
4446 pd_entry_t *pd, PG_V;
4449 PG_V = pmap_valid_bit(pmap);
4452 * Calculate pagetable page index
4454 ptepindex = pmap_pde_pindex(va);
4457 * Get the page directory entry
4459 pd = pmap_pde(pmap, va);
4462 * This supports switching from a 2MB page to a
4465 if (pd != NULL && (*pd & (PG_PS | PG_V)) == (PG_PS | PG_V)) {
4466 if (!pmap_demote_pde_locked(pmap, pd, va, lockp)) {
4468 * Invalidation of the 2MB page mapping may have caused
4469 * the deallocation of the underlying PD page.
4476 * If the page table page is mapped, we just increment the
4477 * hold count, and activate it.
4479 if (pd != NULL && (*pd & PG_V) != 0) {
4480 m = PHYS_TO_VM_PAGE(*pd & PG_FRAME);
4484 * Here if the pte page isn't mapped, or if it has been
4487 m = _pmap_allocpte(pmap, ptepindex, lockp, va);
4488 if (m == NULL && lockp != NULL)
4494 /***************************************************
4495 * Pmap allocation/deallocation routines.
4496 ***************************************************/
4499 * Release any resources held by the given physical map.
4500 * Called when a pmap initialized by pmap_pinit is being released.
4501 * Should only be called if the map contains no valid mappings.
4504 pmap_release(pmap_t pmap)
4509 KASSERT(pmap->pm_stats.resident_count == 0,
4510 ("pmap_release: pmap %p resident count %ld != 0",
4511 pmap, pmap->pm_stats.resident_count));
4512 KASSERT(vm_radix_is_empty(&pmap->pm_root),
4513 ("pmap_release: pmap %p has reserved page table page(s)",
4515 KASSERT(CPU_EMPTY(&pmap->pm_active),
4516 ("releasing active pmap %p", pmap));
4518 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->pm_pmltop));
4520 if (pmap_is_la57(pmap)) {
4521 pmap->pm_pmltop[pmap_pml5e_index(UPT_MAX_ADDRESS)] = 0;
4522 pmap->pm_pmltop[PML5PML5I] = 0;
4524 for (i = 0; i < NKPML4E; i++) /* KVA */
4525 pmap->pm_pmltop[KPML4BASE + i] = 0;
4526 for (i = 0; i < ndmpdpphys; i++)/* Direct Map */
4527 pmap->pm_pmltop[DMPML4I + i] = 0;
4528 pmap->pm_pmltop[PML4PML4I] = 0; /* Recursive Mapping */
4529 for (i = 0; i < lm_ents; i++) /* Large Map */
4530 pmap->pm_pmltop[LMSPML4I + i] = 0;
4533 vm_page_unwire_noq(m);
4534 vm_page_free_zero(m);
4536 if (pmap->pm_pmltopu != NULL) {
4537 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pmap->
4539 vm_page_unwire_noq(m);
4542 if (pmap->pm_type == PT_X86 &&
4543 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
4544 rangeset_fini(&pmap->pm_pkru);
4548 kvm_size(SYSCTL_HANDLER_ARGS)
4550 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS;
4552 return sysctl_handle_long(oidp, &ksize, 0, req);
4554 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4555 0, 0, kvm_size, "LU",
4559 kvm_free(SYSCTL_HANDLER_ARGS)
4561 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
4563 return sysctl_handle_long(oidp, &kfree, 0, req);
4565 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG | CTLFLAG_RD | CTLFLAG_MPSAFE,
4566 0, 0, kvm_free, "LU",
4567 "Amount of KVM free");
4570 * Allocate physical memory for the vm_page array and map it into KVA,
4571 * attempting to back the vm_pages with domain-local memory.
4574 pmap_page_array_startup(long pages)
4577 pd_entry_t *pde, newpdir;
4578 vm_offset_t va, start, end;
4583 vm_page_array_size = pages;
4585 start = VM_MIN_KERNEL_ADDRESS;
4586 end = start + pages * sizeof(struct vm_page);
4587 for (va = start; va < end; va += NBPDR) {
4588 pfn = first_page + (va - start) / sizeof(struct vm_page);
4589 domain = _vm_phys_domain(ptoa(pfn));
4590 pdpe = pmap_pdpe(kernel_pmap, va);
4591 if ((*pdpe & X86_PG_V) == 0) {
4592 pa = vm_phys_early_alloc(domain, PAGE_SIZE);
4594 pagezero((void *)PHYS_TO_DMAP(pa));
4595 *pdpe = (pdp_entry_t)(pa | X86_PG_V | X86_PG_RW |
4596 X86_PG_A | X86_PG_M);
4598 pde = pmap_pdpe_to_pde(pdpe, va);
4599 if ((*pde & X86_PG_V) != 0)
4600 panic("Unexpected pde");
4601 pa = vm_phys_early_alloc(domain, NBPDR);
4602 for (i = 0; i < NPDEPG; i++)
4603 dump_add_page(pa + i * PAGE_SIZE);
4604 newpdir = (pd_entry_t)(pa | X86_PG_V | X86_PG_RW | X86_PG_A |
4605 X86_PG_M | PG_PS | pg_g | pg_nx);
4606 pde_store(pde, newpdir);
4608 vm_page_array = (vm_page_t)start;
4612 * grow the number of kernel page table entries, if needed
4615 pmap_growkernel(vm_offset_t addr)
4619 pd_entry_t *pde, newpdir;
4622 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
4625 * Return if "addr" is within the range of kernel page table pages
4626 * that were preallocated during pmap bootstrap. Moreover, leave
4627 * "kernel_vm_end" and the kernel page table as they were.
4629 * The correctness of this action is based on the following
4630 * argument: vm_map_insert() allocates contiguous ranges of the
4631 * kernel virtual address space. It calls this function if a range
4632 * ends after "kernel_vm_end". If the kernel is mapped between
4633 * "kernel_vm_end" and "addr", then the range cannot begin at
4634 * "kernel_vm_end". In fact, its beginning address cannot be less
4635 * than the kernel. Thus, there is no immediate need to allocate
4636 * any new kernel page table pages between "kernel_vm_end" and
4639 if (KERNBASE < addr && addr <= KERNBASE + nkpt * NBPDR)
4642 addr = roundup2(addr, NBPDR);
4643 if (addr - 1 >= vm_map_max(kernel_map))
4644 addr = vm_map_max(kernel_map);
4645 while (kernel_vm_end < addr) {
4646 pdpe = pmap_pdpe(kernel_pmap, kernel_vm_end);
4647 if ((*pdpe & X86_PG_V) == 0) {
4648 /* We need a new PDP entry */
4649 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDPSHIFT,
4650 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ |
4651 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
4653 panic("pmap_growkernel: no memory to grow kernel");
4654 if ((nkpg->flags & PG_ZERO) == 0)
4655 pmap_zero_page(nkpg);
4656 paddr = VM_PAGE_TO_PHYS(nkpg);
4657 *pdpe = (pdp_entry_t)(paddr | X86_PG_V | X86_PG_RW |
4658 X86_PG_A | X86_PG_M);
4659 continue; /* try again */
4661 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
4662 if ((*pde & X86_PG_V) != 0) {
4663 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4664 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4665 kernel_vm_end = vm_map_max(kernel_map);
4671 nkpg = vm_page_alloc(NULL, pmap_pde_pindex(kernel_vm_end),
4672 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
4675 panic("pmap_growkernel: no memory to grow kernel");
4676 if ((nkpg->flags & PG_ZERO) == 0)
4677 pmap_zero_page(nkpg);
4678 paddr = VM_PAGE_TO_PHYS(nkpg);
4679 newpdir = paddr | X86_PG_V | X86_PG_RW | X86_PG_A | X86_PG_M;
4680 pde_store(pde, newpdir);
4682 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
4683 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
4684 kernel_vm_end = vm_map_max(kernel_map);
4690 /***************************************************
4691 * page management routines.
4692 ***************************************************/
4694 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
4695 CTASSERT(_NPCM == 3);
4696 CTASSERT(_NPCPV == 168);
4698 static __inline struct pv_chunk *
4699 pv_to_chunk(pv_entry_t pv)
4702 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
4705 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
4707 #define PC_FREE0 0xfffffffffffffffful
4708 #define PC_FREE1 0xfffffffffffffffful
4709 #define PC_FREE2 0x000000fffffffffful
4711 static const uint64_t pc_freemask[_NPCM] = { PC_FREE0, PC_FREE1, PC_FREE2 };
4714 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
4716 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
4717 "Current number of pv entry chunks");
4718 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
4719 "Current number of pv entry chunks allocated");
4720 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
4721 "Current number of pv entry chunks frees");
4722 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
4723 "Number of times tried to get a chunk page but failed.");
4725 static long pv_entry_frees, pv_entry_allocs, pv_entry_count;
4726 static int pv_entry_spare;
4728 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
4729 "Current number of pv entry frees");
4730 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
4731 "Current number of pv entry allocs");
4732 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
4733 "Current number of pv entries");
4734 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
4735 "Current number of spare pv entries");
4739 reclaim_pv_chunk_leave_pmap(pmap_t pmap, pmap_t locked_pmap, bool start_di)
4744 pmap_invalidate_all(pmap);
4745 if (pmap != locked_pmap)
4748 pmap_delayed_invl_finish();
4752 * We are in a serious low memory condition. Resort to
4753 * drastic measures to free some pages so we can allocate
4754 * another pv entry chunk.
4756 * Returns NULL if PV entries were reclaimed from the specified pmap.
4758 * We do not, however, unmap 2mpages because subsequent accesses will
4759 * allocate per-page pv entries until repromotion occurs, thereby
4760 * exacerbating the shortage of free pv entries.
4763 reclaim_pv_chunk_domain(pmap_t locked_pmap, struct rwlock **lockp, int domain)
4765 struct pv_chunks_list *pvc;
4766 struct pv_chunk *pc, *pc_marker, *pc_marker_end;
4767 struct pv_chunk_header pc_marker_b, pc_marker_end_b;
4768 struct md_page *pvh;
4770 pmap_t next_pmap, pmap;
4771 pt_entry_t *pte, tpte;
4772 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
4776 struct spglist free;
4778 int bit, field, freed;
4779 bool start_di, restart;
4781 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
4782 KASSERT(lockp != NULL, ("reclaim_pv_chunk: lockp is NULL"));
4785 PG_G = PG_A = PG_M = PG_RW = 0;
4787 bzero(&pc_marker_b, sizeof(pc_marker_b));
4788 bzero(&pc_marker_end_b, sizeof(pc_marker_end_b));
4789 pc_marker = (struct pv_chunk *)&pc_marker_b;
4790 pc_marker_end = (struct pv_chunk *)&pc_marker_end_b;
4793 * A delayed invalidation block should already be active if
4794 * pmap_advise() or pmap_remove() called this function by way
4795 * of pmap_demote_pde_locked().
4797 start_di = pmap_not_in_di();
4799 pvc = &pv_chunks[domain];
4800 mtx_lock(&pvc->pvc_lock);
4801 pvc->active_reclaims++;
4802 TAILQ_INSERT_HEAD(&pvc->pvc_list, pc_marker, pc_lru);
4803 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc_marker_end, pc_lru);
4804 while ((pc = TAILQ_NEXT(pc_marker, pc_lru)) != pc_marker_end &&
4805 SLIST_EMPTY(&free)) {
4806 next_pmap = pc->pc_pmap;
4807 if (next_pmap == NULL) {
4809 * The next chunk is a marker. However, it is
4810 * not our marker, so active_reclaims must be
4811 * > 1. Consequently, the next_chunk code
4812 * will not rotate the pv_chunks list.
4816 mtx_unlock(&pvc->pvc_lock);
4819 * A pv_chunk can only be removed from the pc_lru list
4820 * when both pc_chunks_mutex is owned and the
4821 * corresponding pmap is locked.
4823 if (pmap != next_pmap) {
4825 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap,
4828 /* Avoid deadlock and lock recursion. */
4829 if (pmap > locked_pmap) {
4830 RELEASE_PV_LIST_LOCK(lockp);
4833 pmap_delayed_invl_start();
4834 mtx_lock(&pvc->pvc_lock);
4836 } else if (pmap != locked_pmap) {
4837 if (PMAP_TRYLOCK(pmap)) {
4839 pmap_delayed_invl_start();
4840 mtx_lock(&pvc->pvc_lock);
4843 pmap = NULL; /* pmap is not locked */
4844 mtx_lock(&pvc->pvc_lock);
4845 pc = TAILQ_NEXT(pc_marker, pc_lru);
4847 pc->pc_pmap != next_pmap)
4851 } else if (start_di)
4852 pmap_delayed_invl_start();
4853 PG_G = pmap_global_bit(pmap);
4854 PG_A = pmap_accessed_bit(pmap);
4855 PG_M = pmap_modified_bit(pmap);
4856 PG_RW = pmap_rw_bit(pmap);
4862 * Destroy every non-wired, 4 KB page mapping in the chunk.
4865 for (field = 0; field < _NPCM; field++) {
4866 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
4867 inuse != 0; inuse &= ~(1UL << bit)) {
4869 pv = &pc->pc_pventry[field * 64 + bit];
4871 pde = pmap_pde(pmap, va);
4872 if ((*pde & PG_PS) != 0)
4874 pte = pmap_pde_to_pte(pde, va);
4875 if ((*pte & PG_W) != 0)
4877 tpte = pte_load_clear(pte);
4878 if ((tpte & PG_G) != 0)
4879 pmap_invalidate_page(pmap, va);
4880 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4881 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
4883 if ((tpte & PG_A) != 0)
4884 vm_page_aflag_set(m, PGA_REFERENCED);
4885 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
4886 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4888 if (TAILQ_EMPTY(&m->md.pv_list) &&
4889 (m->flags & PG_FICTITIOUS) == 0) {
4890 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4891 if (TAILQ_EMPTY(&pvh->pv_list)) {
4892 vm_page_aflag_clear(m,
4896 pmap_delayed_invl_page(m);
4897 pc->pc_map[field] |= 1UL << bit;
4898 pmap_unuse_pt(pmap, va, *pde, &free);
4903 mtx_lock(&pvc->pvc_lock);
4906 /* Every freed mapping is for a 4 KB page. */
4907 pmap_resident_count_dec(pmap, freed);
4908 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
4909 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
4910 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
4911 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4912 if (pc->pc_map[0] == PC_FREE0 && pc->pc_map[1] == PC_FREE1 &&
4913 pc->pc_map[2] == PC_FREE2) {
4914 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
4915 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
4916 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
4917 /* Entire chunk is free; return it. */
4918 m_pc = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
4919 dump_drop_page(m_pc->phys_addr);
4920 mtx_lock(&pvc->pvc_lock);
4921 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4924 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
4925 mtx_lock(&pvc->pvc_lock);
4926 /* One freed pv entry in locked_pmap is sufficient. */
4927 if (pmap == locked_pmap)
4930 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4931 TAILQ_INSERT_AFTER(&pvc->pvc_list, pc, pc_marker, pc_lru);
4932 if (pvc->active_reclaims == 1 && pmap != NULL) {
4934 * Rotate the pv chunks list so that we do not
4935 * scan the same pv chunks that could not be
4936 * freed (because they contained a wired
4937 * and/or superpage mapping) on every
4938 * invocation of reclaim_pv_chunk().
4940 while ((pc = TAILQ_FIRST(&pvc->pvc_list)) != pc_marker) {
4941 MPASS(pc->pc_pmap != NULL);
4942 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
4943 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
4947 TAILQ_REMOVE(&pvc->pvc_list, pc_marker, pc_lru);
4948 TAILQ_REMOVE(&pvc->pvc_list, pc_marker_end, pc_lru);
4949 pvc->active_reclaims--;
4950 mtx_unlock(&pvc->pvc_lock);
4951 reclaim_pv_chunk_leave_pmap(pmap, locked_pmap, start_di);
4952 if (m_pc == NULL && !SLIST_EMPTY(&free)) {
4953 m_pc = SLIST_FIRST(&free);
4954 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
4955 /* Recycle a freed page table page. */
4956 m_pc->ref_count = 1;
4958 vm_page_free_pages_toq(&free, true);
4963 reclaim_pv_chunk(pmap_t locked_pmap, struct rwlock **lockp)
4968 domain = PCPU_GET(domain);
4969 for (i = 0; i < vm_ndomains; i++) {
4970 m = reclaim_pv_chunk_domain(locked_pmap, lockp, domain);
4973 domain = (domain + 1) % vm_ndomains;
4980 * free the pv_entry back to the free list
4983 free_pv_entry(pmap_t pmap, pv_entry_t pv)
4985 struct pv_chunk *pc;
4986 int idx, field, bit;
4988 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4989 PV_STAT(atomic_add_long(&pv_entry_frees, 1));
4990 PV_STAT(atomic_add_int(&pv_entry_spare, 1));
4991 PV_STAT(atomic_subtract_long(&pv_entry_count, 1));
4992 pc = pv_to_chunk(pv);
4993 idx = pv - &pc->pc_pventry[0];
4996 pc->pc_map[field] |= 1ul << bit;
4997 if (pc->pc_map[0] != PC_FREE0 || pc->pc_map[1] != PC_FREE1 ||
4998 pc->pc_map[2] != PC_FREE2) {
4999 /* 98% of the time, pc is already at the head of the list. */
5000 if (__predict_false(pc != TAILQ_FIRST(&pmap->pm_pvchunk))) {
5001 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5002 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5006 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5011 free_pv_chunk_dequeued(struct pv_chunk *pc)
5015 PV_STAT(atomic_subtract_int(&pv_entry_spare, _NPCPV));
5016 PV_STAT(atomic_subtract_int(&pc_chunk_count, 1));
5017 PV_STAT(atomic_add_int(&pc_chunk_frees, 1));
5018 /* entire chunk is free, return it */
5019 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pc));
5020 dump_drop_page(m->phys_addr);
5021 vm_page_unwire_noq(m);
5026 free_pv_chunk(struct pv_chunk *pc)
5028 struct pv_chunks_list *pvc;
5030 pvc = &pv_chunks[pc_to_domain(pc)];
5031 mtx_lock(&pvc->pvc_lock);
5032 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5033 mtx_unlock(&pvc->pvc_lock);
5034 free_pv_chunk_dequeued(pc);
5038 free_pv_chunk_batch(struct pv_chunklist *batch)
5040 struct pv_chunks_list *pvc;
5041 struct pv_chunk *pc, *npc;
5044 for (i = 0; i < vm_ndomains; i++) {
5045 if (TAILQ_EMPTY(&batch[i]))
5047 pvc = &pv_chunks[i];
5048 mtx_lock(&pvc->pvc_lock);
5049 TAILQ_FOREACH(pc, &batch[i], pc_list) {
5050 TAILQ_REMOVE(&pvc->pvc_list, pc, pc_lru);
5052 mtx_unlock(&pvc->pvc_lock);
5055 for (i = 0; i < vm_ndomains; i++) {
5056 TAILQ_FOREACH_SAFE(pc, &batch[i], pc_list, npc) {
5057 free_pv_chunk_dequeued(pc);
5063 * Returns a new PV entry, allocating a new PV chunk from the system when
5064 * needed. If this PV chunk allocation fails and a PV list lock pointer was
5065 * given, a PV chunk is reclaimed from an arbitrary pmap. Otherwise, NULL is
5068 * The given PV list lock may be released.
5071 get_pv_entry(pmap_t pmap, struct rwlock **lockp)
5073 struct pv_chunks_list *pvc;
5076 struct pv_chunk *pc;
5079 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5080 PV_STAT(atomic_add_long(&pv_entry_allocs, 1));
5082 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5084 for (field = 0; field < _NPCM; field++) {
5085 if (pc->pc_map[field]) {
5086 bit = bsfq(pc->pc_map[field]);
5090 if (field < _NPCM) {
5091 pv = &pc->pc_pventry[field * 64 + bit];
5092 pc->pc_map[field] &= ~(1ul << bit);
5093 /* If this was the last item, move it to tail */
5094 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 &&
5095 pc->pc_map[2] == 0) {
5096 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5097 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc,
5100 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5101 PV_STAT(atomic_subtract_int(&pv_entry_spare, 1));
5105 /* No free items, allocate another chunk */
5106 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5109 if (lockp == NULL) {
5110 PV_STAT(pc_chunk_tryfail++);
5113 m = reclaim_pv_chunk(pmap, lockp);
5117 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5118 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5119 dump_add_page(m->phys_addr);
5120 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5122 pc->pc_map[0] = PC_FREE0 & ~1ul; /* preallocated bit 0 */
5123 pc->pc_map[1] = PC_FREE1;
5124 pc->pc_map[2] = PC_FREE2;
5125 pvc = &pv_chunks[_vm_phys_domain(m->phys_addr)];
5126 mtx_lock(&pvc->pvc_lock);
5127 TAILQ_INSERT_TAIL(&pvc->pvc_list, pc, pc_lru);
5128 mtx_unlock(&pvc->pvc_lock);
5129 pv = &pc->pc_pventry[0];
5130 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5131 PV_STAT(atomic_add_long(&pv_entry_count, 1));
5132 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV - 1));
5137 * Returns the number of one bits within the given PV chunk map.
5139 * The erratas for Intel processors state that "POPCNT Instruction May
5140 * Take Longer to Execute Than Expected". It is believed that the
5141 * issue is the spurious dependency on the destination register.
5142 * Provide a hint to the register rename logic that the destination
5143 * value is overwritten, by clearing it, as suggested in the
5144 * optimization manual. It should be cheap for unaffected processors
5147 * Reference numbers for erratas are
5148 * 4th Gen Core: HSD146
5149 * 5th Gen Core: BDM85
5150 * 6th Gen Core: SKL029
5153 popcnt_pc_map_pq(uint64_t *map)
5157 __asm __volatile("xorl %k0,%k0;popcntq %2,%0;"
5158 "xorl %k1,%k1;popcntq %3,%1;addl %k1,%k0;"
5159 "xorl %k1,%k1;popcntq %4,%1;addl %k1,%k0"
5160 : "=&r" (result), "=&r" (tmp)
5161 : "m" (map[0]), "m" (map[1]), "m" (map[2]));
5166 * Ensure that the number of spare PV entries in the specified pmap meets or
5167 * exceeds the given count, "needed".
5169 * The given PV list lock may be released.
5172 reserve_pv_entries(pmap_t pmap, int needed, struct rwlock **lockp)
5174 struct pv_chunks_list *pvc;
5175 struct pch new_tail[PMAP_MEMDOM];
5176 struct pv_chunk *pc;
5181 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5182 KASSERT(lockp != NULL, ("reserve_pv_entries: lockp is NULL"));
5185 * Newly allocated PV chunks must be stored in a private list until
5186 * the required number of PV chunks have been allocated. Otherwise,
5187 * reclaim_pv_chunk() could recycle one of these chunks. In
5188 * contrast, these chunks must be added to the pmap upon allocation.
5190 for (i = 0; i < PMAP_MEMDOM; i++)
5191 TAILQ_INIT(&new_tail[i]);
5194 TAILQ_FOREACH(pc, &pmap->pm_pvchunk, pc_list) {
5196 if ((cpu_feature2 & CPUID2_POPCNT) == 0)
5197 bit_count((bitstr_t *)pc->pc_map, 0,
5198 sizeof(pc->pc_map) * NBBY, &free);
5201 free = popcnt_pc_map_pq(pc->pc_map);
5205 if (avail >= needed)
5208 for (reclaimed = false; avail < needed; avail += _NPCPV) {
5209 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
5212 m = reclaim_pv_chunk(pmap, lockp);
5217 PV_STAT(atomic_add_int(&pc_chunk_count, 1));
5218 PV_STAT(atomic_add_int(&pc_chunk_allocs, 1));
5219 dump_add_page(m->phys_addr);
5220 pc = (void *)PHYS_TO_DMAP(m->phys_addr);
5222 pc->pc_map[0] = PC_FREE0;
5223 pc->pc_map[1] = PC_FREE1;
5224 pc->pc_map[2] = PC_FREE2;
5225 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
5226 TAILQ_INSERT_TAIL(&new_tail[pc_to_domain(pc)], pc, pc_lru);
5227 PV_STAT(atomic_add_int(&pv_entry_spare, _NPCPV));
5230 * The reclaim might have freed a chunk from the current pmap.
5231 * If that chunk contained available entries, we need to
5232 * re-count the number of available entries.
5237 for (i = 0; i < vm_ndomains; i++) {
5238 if (TAILQ_EMPTY(&new_tail[i]))
5240 pvc = &pv_chunks[i];
5241 mtx_lock(&pvc->pvc_lock);
5242 TAILQ_CONCAT(&pvc->pvc_list, &new_tail[i], pc_lru);
5243 mtx_unlock(&pvc->pvc_lock);
5248 * First find and then remove the pv entry for the specified pmap and virtual
5249 * address from the specified pv list. Returns the pv entry if found and NULL
5250 * otherwise. This operation can be performed on pv lists for either 4KB or
5251 * 2MB page mappings.
5253 static __inline pv_entry_t
5254 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5258 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5259 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
5260 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5269 * After demotion from a 2MB page mapping to 512 4KB page mappings,
5270 * destroy the pv entry for the 2MB page mapping and reinstantiate the pv
5271 * entries for each of the 4KB page mappings.
5274 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5275 struct rwlock **lockp)
5277 struct md_page *pvh;
5278 struct pv_chunk *pc;
5280 vm_offset_t va_last;
5284 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5285 KASSERT((pa & PDRMASK) == 0,
5286 ("pmap_pv_demote_pde: pa is not 2mpage aligned"));
5287 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5290 * Transfer the 2mpage's pv entry for this mapping to the first
5291 * page's pv list. Once this transfer begins, the pv list lock
5292 * must not be released until the last pv entry is reinstantiated.
5294 pvh = pa_to_pvh(pa);
5295 va = trunc_2mpage(va);
5296 pv = pmap_pvh_remove(pvh, pmap, va);
5297 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
5298 m = PHYS_TO_VM_PAGE(pa);
5299 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5301 /* Instantiate the remaining NPTEPG - 1 pv entries. */
5302 PV_STAT(atomic_add_long(&pv_entry_allocs, NPTEPG - 1));
5303 va_last = va + NBPDR - PAGE_SIZE;
5305 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
5306 KASSERT(pc->pc_map[0] != 0 || pc->pc_map[1] != 0 ||
5307 pc->pc_map[2] != 0, ("pmap_pv_demote_pde: missing spare"));
5308 for (field = 0; field < _NPCM; field++) {
5309 while (pc->pc_map[field]) {
5310 bit = bsfq(pc->pc_map[field]);
5311 pc->pc_map[field] &= ~(1ul << bit);
5312 pv = &pc->pc_pventry[field * 64 + bit];
5316 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5317 ("pmap_pv_demote_pde: page %p is not managed", m));
5318 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5324 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5325 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5328 if (pc->pc_map[0] == 0 && pc->pc_map[1] == 0 && pc->pc_map[2] == 0) {
5329 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
5330 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
5332 PV_STAT(atomic_add_long(&pv_entry_count, NPTEPG - 1));
5333 PV_STAT(atomic_subtract_int(&pv_entry_spare, NPTEPG - 1));
5336 #if VM_NRESERVLEVEL > 0
5338 * After promotion from 512 4KB page mappings to a single 2MB page mapping,
5339 * replace the many pv entries for the 4KB page mappings by a single pv entry
5340 * for the 2MB page mapping.
5343 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa,
5344 struct rwlock **lockp)
5346 struct md_page *pvh;
5348 vm_offset_t va_last;
5351 KASSERT((pa & PDRMASK) == 0,
5352 ("pmap_pv_promote_pde: pa is not 2mpage aligned"));
5353 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5356 * Transfer the first page's pv entry for this mapping to the 2mpage's
5357 * pv list. Aside from avoiding the cost of a call to get_pv_entry(),
5358 * a transfer avoids the possibility that get_pv_entry() calls
5359 * reclaim_pv_chunk() and that reclaim_pv_chunk() removes one of the
5360 * mappings that is being promoted.
5362 m = PHYS_TO_VM_PAGE(pa);
5363 va = trunc_2mpage(va);
5364 pv = pmap_pvh_remove(&m->md, pmap, va);
5365 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
5366 pvh = pa_to_pvh(pa);
5367 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5369 /* Free the remaining NPTEPG - 1 pv entries. */
5370 va_last = va + NBPDR - PAGE_SIZE;
5374 pmap_pvh_free(&m->md, pmap, va);
5375 } while (va < va_last);
5377 #endif /* VM_NRESERVLEVEL > 0 */
5380 * First find and then destroy the pv entry for the specified pmap and virtual
5381 * address. This operation can be performed on pv lists for either 4KB or 2MB
5385 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
5389 pv = pmap_pvh_remove(pvh, pmap, va);
5390 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
5391 free_pv_entry(pmap, pv);
5395 * Conditionally create the PV entry for a 4KB page mapping if the required
5396 * memory can be allocated without resorting to reclamation.
5399 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m,
5400 struct rwlock **lockp)
5404 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5405 /* Pass NULL instead of the lock pointer to disable reclamation. */
5406 if ((pv = get_pv_entry(pmap, NULL)) != NULL) {
5408 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5409 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5417 * Create the PV entry for a 2MB page mapping. Always returns true unless the
5418 * flag PMAP_ENTER_NORECLAIM is specified. If that flag is specified, returns
5419 * false if the PV entry cannot be allocated without resorting to reclamation.
5422 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags,
5423 struct rwlock **lockp)
5425 struct md_page *pvh;
5429 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5430 /* Pass NULL instead of the lock pointer to disable reclamation. */
5431 if ((pv = get_pv_entry(pmap, (flags & PMAP_ENTER_NORECLAIM) != 0 ?
5432 NULL : lockp)) == NULL)
5435 pa = pde & PG_PS_FRAME;
5436 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, pa);
5437 pvh = pa_to_pvh(pa);
5438 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5444 * Fills a page table page with mappings to consecutive physical pages.
5447 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
5451 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
5453 newpte += PAGE_SIZE;
5458 * Tries to demote a 2MB page mapping. If demotion fails, the 2MB page
5459 * mapping is invalidated.
5462 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5464 struct rwlock *lock;
5468 rv = pmap_demote_pde_locked(pmap, pde, va, &lock);
5475 pmap_demote_pde_check(pt_entry_t *firstpte __unused, pt_entry_t newpte __unused)
5479 pt_entry_t *xpte, *ypte;
5481 for (xpte = firstpte; xpte < firstpte + NPTEPG;
5482 xpte++, newpte += PAGE_SIZE) {
5483 if ((*xpte & PG_FRAME) != (newpte & PG_FRAME)) {
5484 printf("pmap_demote_pde: xpte %zd and newpte map "
5485 "different pages: found %#lx, expected %#lx\n",
5486 xpte - firstpte, *xpte, newpte);
5487 printf("page table dump\n");
5488 for (ypte = firstpte; ypte < firstpte + NPTEPG; ypte++)
5489 printf("%zd %#lx\n", ypte - firstpte, *ypte);
5494 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
5495 ("pmap_demote_pde: firstpte and newpte map different physical"
5502 pmap_demote_pde_abort(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5503 pd_entry_t oldpde, struct rwlock **lockp)
5505 struct spglist free;
5509 sva = trunc_2mpage(va);
5510 pmap_remove_pde(pmap, pde, sva, &free, lockp);
5511 if ((oldpde & pmap_global_bit(pmap)) == 0)
5512 pmap_invalidate_pde_page(pmap, sva, oldpde);
5513 vm_page_free_pages_toq(&free, true);
5514 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#lx in pmap %p",
5519 pmap_demote_pde_locked(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
5520 struct rwlock **lockp)
5522 pd_entry_t newpde, oldpde;
5523 pt_entry_t *firstpte, newpte;
5524 pt_entry_t PG_A, PG_G, PG_M, PG_PKU_MASK, PG_RW, PG_V;
5530 PG_A = pmap_accessed_bit(pmap);
5531 PG_G = pmap_global_bit(pmap);
5532 PG_M = pmap_modified_bit(pmap);
5533 PG_RW = pmap_rw_bit(pmap);
5534 PG_V = pmap_valid_bit(pmap);
5535 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
5536 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
5538 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5539 in_kernel = va >= VM_MAXUSER_ADDRESS;
5541 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
5542 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
5545 * Invalidate the 2MB page mapping and return "failure" if the
5546 * mapping was never accessed.
5548 if ((oldpde & PG_A) == 0) {
5549 KASSERT((oldpde & PG_W) == 0,
5550 ("pmap_demote_pde: a wired mapping is missing PG_A"));
5551 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5555 mpte = pmap_remove_pt_page(pmap, va);
5557 KASSERT((oldpde & PG_W) == 0,
5558 ("pmap_demote_pde: page table page for a wired mapping"
5562 * If the page table page is missing and the mapping
5563 * is for a kernel address, the mapping must belong to
5564 * the direct map. Page table pages are preallocated
5565 * for every other part of the kernel address space,
5566 * so the direct map region is the only part of the
5567 * kernel address space that must be handled here.
5569 KASSERT(!in_kernel || (va >= DMAP_MIN_ADDRESS &&
5570 va < DMAP_MAX_ADDRESS),
5571 ("pmap_demote_pde: No saved mpte for va %#lx", va));
5574 * If the 2MB page mapping belongs to the direct map
5575 * region of the kernel's address space, then the page
5576 * allocation request specifies the highest possible
5577 * priority (VM_ALLOC_INTERRUPT). Otherwise, the
5578 * priority is normal.
5580 mpte = vm_page_alloc(NULL, pmap_pde_pindex(va),
5581 (in_kernel ? VM_ALLOC_INTERRUPT : VM_ALLOC_NORMAL) |
5582 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED);
5585 * If the allocation of the new page table page fails,
5586 * invalidate the 2MB page mapping and return "failure".
5589 pmap_demote_pde_abort(pmap, va, pde, oldpde, lockp);
5594 mpte->ref_count = NPTEPG;
5595 pmap_resident_count_inc(pmap, 1);
5598 mptepa = VM_PAGE_TO_PHYS(mpte);
5599 firstpte = (pt_entry_t *)PHYS_TO_DMAP(mptepa);
5600 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
5601 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
5602 ("pmap_demote_pde: oldpde is missing PG_M"));
5603 newpte = oldpde & ~PG_PS;
5604 newpte = pmap_swap_pat(pmap, newpte);
5607 * If the page table page is not leftover from an earlier promotion,
5610 if (mpte->valid == 0)
5611 pmap_fill_ptp(firstpte, newpte);
5613 pmap_demote_pde_check(firstpte, newpte);
5616 * If the mapping has changed attributes, update the page table
5619 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
5620 pmap_fill_ptp(firstpte, newpte);
5623 * The spare PV entries must be reserved prior to demoting the
5624 * mapping, that is, prior to changing the PDE. Otherwise, the state
5625 * of the PDE and the PV lists will be inconsistent, which can result
5626 * in reclaim_pv_chunk() attempting to remove a PV entry from the
5627 * wrong PV list and pmap_pv_demote_pde() failing to find the expected
5628 * PV entry for the 2MB page mapping that is being demoted.
5630 if ((oldpde & PG_MANAGED) != 0)
5631 reserve_pv_entries(pmap, NPTEPG - 1, lockp);
5634 * Demote the mapping. This pmap is locked. The old PDE has
5635 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
5636 * set. Thus, there is no danger of a race with another
5637 * processor changing the setting of PG_A and/or PG_M between
5638 * the read above and the store below.
5640 if (workaround_erratum383)
5641 pmap_update_pde(pmap, va, pde, newpde);
5643 pde_store(pde, newpde);
5646 * Invalidate a stale recursive mapping of the page table page.
5649 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5652 * Demote the PV entry.
5654 if ((oldpde & PG_MANAGED) != 0)
5655 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME, lockp);
5657 atomic_add_long(&pmap_pde_demotions, 1);
5658 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#lx in pmap %p",
5664 * pmap_remove_kernel_pde: Remove a kernel superpage mapping.
5667 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
5673 KASSERT(pmap == kernel_pmap, ("pmap %p is not kernel_pmap", pmap));
5674 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5675 mpte = pmap_remove_pt_page(pmap, va);
5677 panic("pmap_remove_kernel_pde: Missing pt page.");
5679 mptepa = VM_PAGE_TO_PHYS(mpte);
5680 newpde = mptepa | X86_PG_M | X86_PG_A | X86_PG_RW | X86_PG_V;
5683 * If this page table page was unmapped by a promotion, then it
5684 * contains valid mappings. Zero it to invalidate those mappings.
5686 if (mpte->valid != 0)
5687 pagezero((void *)PHYS_TO_DMAP(mptepa));
5690 * Demote the mapping.
5692 if (workaround_erratum383)
5693 pmap_update_pde(pmap, va, pde, newpde);
5695 pde_store(pde, newpde);
5698 * Invalidate a stale recursive mapping of the page table page.
5700 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
5704 * pmap_remove_pde: do the things to unmap a superpage in a process
5707 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
5708 struct spglist *free, struct rwlock **lockp)
5710 struct md_page *pvh;
5712 vm_offset_t eva, va;
5714 pt_entry_t PG_G, PG_A, PG_M, PG_RW;
5716 PG_G = pmap_global_bit(pmap);
5717 PG_A = pmap_accessed_bit(pmap);
5718 PG_M = pmap_modified_bit(pmap);
5719 PG_RW = pmap_rw_bit(pmap);
5721 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5722 KASSERT((sva & PDRMASK) == 0,
5723 ("pmap_remove_pde: sva is not 2mpage aligned"));
5724 oldpde = pte_load_clear(pdq);
5726 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
5727 if ((oldpde & PG_G) != 0)
5728 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
5729 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
5730 if (oldpde & PG_MANAGED) {
5731 CHANGE_PV_LIST_LOCK_TO_PHYS(lockp, oldpde & PG_PS_FRAME);
5732 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
5733 pmap_pvh_free(pvh, pmap, sva);
5735 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
5736 va < eva; va += PAGE_SIZE, m++) {
5737 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
5740 vm_page_aflag_set(m, PGA_REFERENCED);
5741 if (TAILQ_EMPTY(&m->md.pv_list) &&
5742 TAILQ_EMPTY(&pvh->pv_list))
5743 vm_page_aflag_clear(m, PGA_WRITEABLE);
5744 pmap_delayed_invl_page(m);
5747 if (pmap == kernel_pmap) {
5748 pmap_remove_kernel_pde(pmap, pdq, sva);
5750 mpte = pmap_remove_pt_page(pmap, sva);
5752 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
5753 ("pmap_remove_pde: pte page not promoted"));
5754 pmap_resident_count_dec(pmap, 1);
5755 KASSERT(mpte->ref_count == NPTEPG,
5756 ("pmap_remove_pde: pte page ref count error"));
5757 mpte->ref_count = 0;
5758 pmap_add_delayed_free_list(mpte, free, FALSE);
5761 return (pmap_unuse_pt(pmap, sva, *pmap_pdpe(pmap, sva), free));
5765 * pmap_remove_pte: do the things to unmap a page in a process
5768 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
5769 pd_entry_t ptepde, struct spglist *free, struct rwlock **lockp)
5771 struct md_page *pvh;
5772 pt_entry_t oldpte, PG_A, PG_M, PG_RW;
5775 PG_A = pmap_accessed_bit(pmap);
5776 PG_M = pmap_modified_bit(pmap);
5777 PG_RW = pmap_rw_bit(pmap);
5779 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5780 oldpte = pte_load_clear(ptq);
5782 pmap->pm_stats.wired_count -= 1;
5783 pmap_resident_count_dec(pmap, 1);
5784 if (oldpte & PG_MANAGED) {
5785 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
5786 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5789 vm_page_aflag_set(m, PGA_REFERENCED);
5790 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(lockp, m);
5791 pmap_pvh_free(&m->md, pmap, va);
5792 if (TAILQ_EMPTY(&m->md.pv_list) &&
5793 (m->flags & PG_FICTITIOUS) == 0) {
5794 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5795 if (TAILQ_EMPTY(&pvh->pv_list))
5796 vm_page_aflag_clear(m, PGA_WRITEABLE);
5798 pmap_delayed_invl_page(m);
5800 return (pmap_unuse_pt(pmap, va, ptepde, free));
5804 * Remove a single page from a process address space
5807 pmap_remove_page(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
5808 struct spglist *free)
5810 struct rwlock *lock;
5811 pt_entry_t *pte, PG_V;
5813 PG_V = pmap_valid_bit(pmap);
5814 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5815 if ((*pde & PG_V) == 0)
5817 pte = pmap_pde_to_pte(pde, va);
5818 if ((*pte & PG_V) == 0)
5821 pmap_remove_pte(pmap, pte, va, *pde, free, &lock);
5824 pmap_invalidate_page(pmap, va);
5828 * Removes the specified range of addresses from the page table page.
5831 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5832 pd_entry_t *pde, struct spglist *free, struct rwlock **lockp)
5834 pt_entry_t PG_G, *pte;
5838 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
5839 PG_G = pmap_global_bit(pmap);
5842 for (pte = pmap_pde_to_pte(pde, sva); sva != eva; pte++,
5846 pmap_invalidate_range(pmap, va, sva);
5851 if ((*pte & PG_G) == 0)
5855 if (pmap_remove_pte(pmap, pte, sva, *pde, free, lockp)) {
5861 pmap_invalidate_range(pmap, va, sva);
5866 * Remove the given range of addresses from the specified map.
5868 * It is assumed that the start and end are properly
5869 * rounded to the page size.
5872 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
5874 struct rwlock *lock;
5876 vm_offset_t va_next;
5877 pml5_entry_t *pml5e;
5878 pml4_entry_t *pml4e;
5880 pd_entry_t ptpaddr, *pde;
5881 pt_entry_t PG_G, PG_V;
5882 struct spglist free;
5885 PG_G = pmap_global_bit(pmap);
5886 PG_V = pmap_valid_bit(pmap);
5889 * Perform an unsynchronized read. This is, however, safe.
5891 if (pmap->pm_stats.resident_count == 0)
5897 pmap_delayed_invl_start();
5899 pmap_pkru_on_remove(pmap, sva, eva);
5902 * special handling of removing one page. a very
5903 * common operation and easy to short circuit some
5906 if (sva + PAGE_SIZE == eva) {
5907 pde = pmap_pde(pmap, sva);
5908 if (pde && (*pde & PG_PS) == 0) {
5909 pmap_remove_page(pmap, sva, pde, &free);
5915 for (; sva < eva; sva = va_next) {
5916 if (pmap->pm_stats.resident_count == 0)
5919 if (pmap_is_la57(pmap)) {
5920 pml5e = pmap_pml5e(pmap, sva);
5921 if ((*pml5e & PG_V) == 0) {
5922 va_next = (sva + NBPML5) & ~PML5MASK;
5927 pml4e = pmap_pml5e_to_pml4e(pml5e, sva);
5929 pml4e = pmap_pml4e(pmap, sva);
5931 if ((*pml4e & PG_V) == 0) {
5932 va_next = (sva + NBPML4) & ~PML4MASK;
5938 va_next = (sva + NBPDP) & ~PDPMASK;
5941 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
5942 if ((*pdpe & PG_V) == 0)
5944 if ((*pdpe & PG_PS) != 0) {
5945 KASSERT(va_next <= eva,
5946 ("partial update of non-transparent 1G mapping "
5947 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
5948 *pdpe, sva, eva, va_next));
5949 MPASS(pmap != kernel_pmap); /* XXXKIB */
5950 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
5953 pmap_resident_count_dec(pmap, NBPDP / PAGE_SIZE);
5954 mt = PHYS_TO_VM_PAGE(*pmap_pml4e(pmap, sva) & PG_FRAME);
5955 pmap_unwire_ptp(pmap, sva, mt, &free);
5960 * Calculate index for next page table.
5962 va_next = (sva + NBPDR) & ~PDRMASK;
5966 pde = pmap_pdpe_to_pde(pdpe, sva);
5970 * Weed out invalid mappings.
5976 * Check for large page.
5978 if ((ptpaddr & PG_PS) != 0) {
5980 * Are we removing the entire large page? If not,
5981 * demote the mapping and fall through.
5983 if (sva + NBPDR == va_next && eva >= va_next) {
5985 * The TLB entry for a PG_G mapping is
5986 * invalidated by pmap_remove_pde().
5988 if ((ptpaddr & PG_G) == 0)
5990 pmap_remove_pde(pmap, pde, sva, &free, &lock);
5992 } else if (!pmap_demote_pde_locked(pmap, pde, sva,
5994 /* The large page mapping was destroyed. */
6001 * Limit our scan to either the end of the va represented
6002 * by the current page table page, or to the end of the
6003 * range being removed.
6008 if (pmap_remove_ptes(pmap, sva, va_next, pde, &free, &lock))
6015 pmap_invalidate_all(pmap);
6017 pmap_delayed_invl_finish();
6018 vm_page_free_pages_toq(&free, true);
6022 * Routine: pmap_remove_all
6024 * Removes this physical page from
6025 * all physical maps in which it resides.
6026 * Reflects back modify bits to the pager.
6029 * Original versions of this routine were very
6030 * inefficient because they iteratively called
6031 * pmap_remove (slow...)
6035 pmap_remove_all(vm_page_t m)
6037 struct md_page *pvh;
6040 struct rwlock *lock;
6041 pt_entry_t *pte, tpte, PG_A, PG_M, PG_RW;
6044 struct spglist free;
6045 int pvh_gen, md_gen;
6047 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
6048 ("pmap_remove_all: page %p is not managed", m));
6050 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
6051 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
6052 pa_to_pvh(VM_PAGE_TO_PHYS(m));
6055 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
6057 if (!PMAP_TRYLOCK(pmap)) {
6058 pvh_gen = pvh->pv_gen;
6062 if (pvh_gen != pvh->pv_gen) {
6069 pde = pmap_pde(pmap, va);
6070 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
6073 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
6075 if (!PMAP_TRYLOCK(pmap)) {
6076 pvh_gen = pvh->pv_gen;
6077 md_gen = m->md.pv_gen;
6081 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
6087 PG_A = pmap_accessed_bit(pmap);
6088 PG_M = pmap_modified_bit(pmap);
6089 PG_RW = pmap_rw_bit(pmap);
6090 pmap_resident_count_dec(pmap, 1);
6091 pde = pmap_pde(pmap, pv->pv_va);
6092 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
6093 " a 2mpage in page %p's pv list", m));
6094 pte = pmap_pde_to_pte(pde, pv->pv_va);
6095 tpte = pte_load_clear(pte);
6097 pmap->pm_stats.wired_count--;
6099 vm_page_aflag_set(m, PGA_REFERENCED);
6102 * Update the vm_page_t clean and reference bits.
6104 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6106 pmap_unuse_pt(pmap, pv->pv_va, *pde, &free);
6107 pmap_invalidate_page(pmap, pv->pv_va);
6108 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
6110 free_pv_entry(pmap, pv);
6113 vm_page_aflag_clear(m, PGA_WRITEABLE);
6115 pmap_delayed_invl_wait(m);
6116 vm_page_free_pages_toq(&free, true);
6120 * pmap_protect_pde: do the things to protect a 2mpage in a process
6123 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
6125 pd_entry_t newpde, oldpde;
6127 boolean_t anychanged;
6128 pt_entry_t PG_G, PG_M, PG_RW;
6130 PG_G = pmap_global_bit(pmap);
6131 PG_M = pmap_modified_bit(pmap);
6132 PG_RW = pmap_rw_bit(pmap);
6134 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6135 KASSERT((sva & PDRMASK) == 0,
6136 ("pmap_protect_pde: sva is not 2mpage aligned"));
6139 oldpde = newpde = *pde;
6140 if ((prot & VM_PROT_WRITE) == 0) {
6141 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
6142 (PG_MANAGED | PG_M | PG_RW)) {
6143 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
6144 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
6147 newpde &= ~(PG_RW | PG_M);
6149 if ((prot & VM_PROT_EXECUTE) == 0)
6151 if (newpde != oldpde) {
6153 * As an optimization to future operations on this PDE, clear
6154 * PG_PROMOTED. The impending invalidation will remove any
6155 * lingering 4KB page mappings from the TLB.
6157 if (!atomic_cmpset_long(pde, oldpde, newpde & ~PG_PROMOTED))
6159 if ((oldpde & PG_G) != 0)
6160 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
6164 return (anychanged);
6168 * Set the physical protection on the
6169 * specified range of this map as requested.
6172 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
6175 vm_offset_t va_next;
6176 pml4_entry_t *pml4e;
6178 pd_entry_t ptpaddr, *pde;
6179 pt_entry_t *pte, PG_G, PG_M, PG_RW, PG_V;
6180 pt_entry_t obits, pbits;
6181 boolean_t anychanged;
6183 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
6184 if (prot == VM_PROT_NONE) {
6185 pmap_remove(pmap, sva, eva);
6189 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
6190 (VM_PROT_WRITE|VM_PROT_EXECUTE))
6193 PG_G = pmap_global_bit(pmap);
6194 PG_M = pmap_modified_bit(pmap);
6195 PG_V = pmap_valid_bit(pmap);
6196 PG_RW = pmap_rw_bit(pmap);
6200 * Although this function delays and batches the invalidation
6201 * of stale TLB entries, it does not need to call
6202 * pmap_delayed_invl_start() and
6203 * pmap_delayed_invl_finish(), because it does not
6204 * ordinarily destroy mappings. Stale TLB entries from
6205 * protection-only changes need only be invalidated before the
6206 * pmap lock is released, because protection-only changes do
6207 * not destroy PV entries. Even operations that iterate over
6208 * a physical page's PV list of mappings, like
6209 * pmap_remove_write(), acquire the pmap lock for each
6210 * mapping. Consequently, for protection-only changes, the
6211 * pmap lock suffices to synchronize both page table and TLB
6214 * This function only destroys a mapping if pmap_demote_pde()
6215 * fails. In that case, stale TLB entries are immediately
6220 for (; sva < eva; sva = va_next) {
6221 pml4e = pmap_pml4e(pmap, sva);
6222 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6223 va_next = (sva + NBPML4) & ~PML4MASK;
6229 va_next = (sva + NBPDP) & ~PDPMASK;
6232 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
6233 if ((*pdpe & PG_V) == 0)
6235 if ((*pdpe & PG_PS) != 0) {
6236 KASSERT(va_next <= eva,
6237 ("partial update of non-transparent 1G mapping "
6238 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
6239 *pdpe, sva, eva, va_next));
6241 obits = pbits = *pdpe;
6242 MPASS((pbits & (PG_MANAGED | PG_G)) == 0);
6243 MPASS(pmap != kernel_pmap); /* XXXKIB */
6244 if ((prot & VM_PROT_WRITE) == 0)
6245 pbits &= ~(PG_RW | PG_M);
6246 if ((prot & VM_PROT_EXECUTE) == 0)
6249 if (pbits != obits) {
6250 if (!atomic_cmpset_long(pdpe, obits, pbits))
6251 /* PG_PS cannot be cleared under us, */
6258 va_next = (sva + NBPDR) & ~PDRMASK;
6262 pde = pmap_pdpe_to_pde(pdpe, sva);
6266 * Weed out invalid mappings.
6272 * Check for large page.
6274 if ((ptpaddr & PG_PS) != 0) {
6276 * Are we protecting the entire large page? If not,
6277 * demote the mapping and fall through.
6279 if (sva + NBPDR == va_next && eva >= va_next) {
6281 * The TLB entry for a PG_G mapping is
6282 * invalidated by pmap_protect_pde().
6284 if (pmap_protect_pde(pmap, pde, sva, prot))
6287 } else if (!pmap_demote_pde(pmap, pde, sva)) {
6289 * The large page mapping was destroyed.
6298 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
6301 obits = pbits = *pte;
6302 if ((pbits & PG_V) == 0)
6305 if ((prot & VM_PROT_WRITE) == 0) {
6306 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
6307 (PG_MANAGED | PG_M | PG_RW)) {
6308 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
6311 pbits &= ~(PG_RW | PG_M);
6313 if ((prot & VM_PROT_EXECUTE) == 0)
6316 if (pbits != obits) {
6317 if (!atomic_cmpset_long(pte, obits, pbits))
6320 pmap_invalidate_page(pmap, sva);
6327 pmap_invalidate_all(pmap);
6331 #if VM_NRESERVLEVEL > 0
6333 pmap_pde_ept_executable(pmap_t pmap, pd_entry_t pde)
6336 if (pmap->pm_type != PT_EPT)
6338 return ((pde & EPT_PG_EXECUTE) != 0);
6342 * Tries to promote the 512, contiguous 4KB page mappings that are within a
6343 * single page table page (PTP) to a single 2MB page mapping. For promotion
6344 * to occur, two conditions must be met: (1) the 4KB page mappings must map
6345 * aligned, contiguous physical memory and (2) the 4KB page mappings must have
6346 * identical characteristics.
6349 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
6350 struct rwlock **lockp)
6353 pt_entry_t *firstpte, oldpte, pa, *pte;
6354 pt_entry_t PG_G, PG_A, PG_M, PG_RW, PG_V, PG_PKU_MASK;
6358 PG_A = pmap_accessed_bit(pmap);
6359 PG_G = pmap_global_bit(pmap);
6360 PG_M = pmap_modified_bit(pmap);
6361 PG_V = pmap_valid_bit(pmap);
6362 PG_RW = pmap_rw_bit(pmap);
6363 PG_PKU_MASK = pmap_pku_mask_bit(pmap);
6364 PG_PTE_CACHE = pmap_cache_mask(pmap, 0);
6366 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6369 * Examine the first PTE in the specified PTP. Abort if this PTE is
6370 * either invalid, unused, or does not map the first 4KB physical page
6371 * within a 2MB page.
6373 firstpte = (pt_entry_t *)PHYS_TO_DMAP(*pde & PG_FRAME);
6376 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V) ||
6377 !pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6379 atomic_add_long(&pmap_pde_p_failures, 1);
6380 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6381 " in pmap %p", va, pmap);
6384 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
6386 * When PG_M is already clear, PG_RW can be cleared without
6387 * a TLB invalidation.
6389 if (!atomic_cmpset_long(firstpte, newpde, newpde & ~PG_RW))
6395 * Examine each of the other PTEs in the specified PTP. Abort if this
6396 * PTE maps an unexpected 4KB physical page or does not have identical
6397 * characteristics to the first PTE.
6399 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
6400 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
6403 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
6404 atomic_add_long(&pmap_pde_p_failures, 1);
6405 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6406 " in pmap %p", va, pmap);
6409 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
6411 * When PG_M is already clear, PG_RW can be cleared
6412 * without a TLB invalidation.
6414 if (!atomic_cmpset_long(pte, oldpte, oldpte & ~PG_RW))
6417 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
6418 " in pmap %p", (oldpte & PG_FRAME & PDRMASK) |
6419 (va & ~PDRMASK), pmap);
6421 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
6422 atomic_add_long(&pmap_pde_p_failures, 1);
6423 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#lx"
6424 " in pmap %p", va, pmap);
6431 * Save the page table page in its current state until the PDE
6432 * mapping the superpage is demoted by pmap_demote_pde() or
6433 * destroyed by pmap_remove_pde().
6435 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6436 KASSERT(mpte >= vm_page_array &&
6437 mpte < &vm_page_array[vm_page_array_size],
6438 ("pmap_promote_pde: page table page is out of range"));
6439 KASSERT(mpte->pindex == pmap_pde_pindex(va),
6440 ("pmap_promote_pde: page table page's pindex is wrong"));
6441 if (pmap_insert_pt_page(pmap, mpte, true)) {
6442 atomic_add_long(&pmap_pde_p_failures, 1);
6444 "pmap_promote_pde: failure for va %#lx in pmap %p", va,
6450 * Promote the pv entries.
6452 if ((newpde & PG_MANAGED) != 0)
6453 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME, lockp);
6456 * Propagate the PAT index to its proper position.
6458 newpde = pmap_swap_pat(pmap, newpde);
6461 * Map the superpage.
6463 if (workaround_erratum383)
6464 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
6466 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
6468 atomic_add_long(&pmap_pde_promotions, 1);
6469 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#lx"
6470 " in pmap %p", va, pmap);
6472 #endif /* VM_NRESERVLEVEL > 0 */
6475 pmap_enter_largepage(pmap_t pmap, vm_offset_t va, pt_entry_t newpte, int flags,
6479 pt_entry_t origpte, *pml4e, *pdpe, *pde, pten, PG_V;
6481 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6482 KASSERT(psind > 0 && psind < MAXPAGESIZES && pagesizes[psind] != 0,
6483 ("psind %d unexpected", psind));
6484 KASSERT(((newpte & PG_FRAME) & (pagesizes[psind] - 1)) == 0,
6485 ("unaligned phys address %#lx newpte %#lx psind %d",
6486 newpte & PG_FRAME, newpte, psind));
6487 KASSERT((va & (pagesizes[psind] - 1)) == 0,
6488 ("unaligned va %#lx psind %d", va, psind));
6489 KASSERT(va < VM_MAXUSER_ADDRESS,
6490 ("kernel mode non-transparent superpage")); /* XXXKIB */
6491 KASSERT(va + pagesizes[psind] < VM_MAXUSER_ADDRESS,
6492 ("overflowing user map va %#lx psind %d", va, psind)); /* XXXKIB */
6494 PG_V = pmap_valid_bit(pmap);
6497 if (!pmap_pkru_same(pmap, va, va + pagesizes[psind]))
6498 return (KERN_PROTECTION_FAILURE);
6500 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6501 pten |= pmap_pkru_get(pmap, va);
6503 if (psind == 2) { /* 1G */
6504 pml4e = pmap_pml4e(pmap, va);
6505 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
6506 mp = _pmap_allocpte(pmap, pmap_pml4e_pindex(va),
6510 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6511 pdpe = &pdpe[pmap_pdpe_index(va)];
6513 MPASS(origpte == 0);
6515 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
6516 KASSERT(pdpe != NULL, ("va %#lx lost pdpe", va));
6518 if ((origpte & PG_V) == 0) {
6519 mp = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
6524 } else /* (psind == 1) */ { /* 2M */
6525 pde = pmap_pde(pmap, va);
6527 mp = _pmap_allocpte(pmap, pmap_pdpe_pindex(va),
6531 pde = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mp));
6532 pde = &pde[pmap_pde_index(va)];
6534 MPASS(origpte == 0);
6537 if ((origpte & PG_V) == 0) {
6538 pdpe = pmap_pdpe(pmap, va);
6539 MPASS(pdpe != NULL && (*pdpe & PG_V) != 0);
6540 mp = PHYS_TO_VM_PAGE(*pdpe & PG_FRAME);
6546 KASSERT((origpte & PG_V) == 0 || ((origpte & PG_PS) != 0 &&
6547 (origpte & PG_PS_FRAME) == (pten & PG_PS_FRAME)),
6548 ("va %#lx changing %s phys page origpte %#lx pten %#lx",
6549 va, psind == 2 ? "1G" : "2M", origpte, pten));
6550 if ((pten & PG_W) != 0 && (origpte & PG_W) == 0)
6551 pmap->pm_stats.wired_count += pagesizes[psind] / PAGE_SIZE;
6552 else if ((pten & PG_W) == 0 && (origpte & PG_W) != 0)
6553 pmap->pm_stats.wired_count -= pagesizes[psind] / PAGE_SIZE;
6554 if ((origpte & PG_V) == 0)
6555 pmap_resident_count_inc(pmap, pagesizes[psind] / PAGE_SIZE);
6557 return (KERN_SUCCESS);
6560 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
6561 return (KERN_RESOURCE_SHORTAGE);
6569 * Insert the given physical page (p) at
6570 * the specified virtual address (v) in the
6571 * target physical map with the protection requested.
6573 * If specified, the page will be wired down, meaning
6574 * that the related pte can not be reclaimed.
6576 * NB: This is the only routine which MAY NOT lazy-evaluate
6577 * or lose information. That is, this routine must actually
6578 * insert this page into the given map NOW.
6580 * When destroying both a page table and PV entry, this function
6581 * performs the TLB invalidation before releasing the PV list
6582 * lock, so we do not need pmap_delayed_invl_page() calls here.
6585 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6586 u_int flags, int8_t psind)
6588 struct rwlock *lock;
6590 pt_entry_t *pte, PG_G, PG_A, PG_M, PG_RW, PG_V;
6591 pt_entry_t newpte, origpte;
6598 PG_A = pmap_accessed_bit(pmap);
6599 PG_G = pmap_global_bit(pmap);
6600 PG_M = pmap_modified_bit(pmap);
6601 PG_V = pmap_valid_bit(pmap);
6602 PG_RW = pmap_rw_bit(pmap);
6604 va = trunc_page(va);
6605 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
6606 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
6607 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%lx)",
6609 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
6610 va >= kmi.clean_eva,
6611 ("pmap_enter: managed mapping within the clean submap"));
6612 if ((m->oflags & VPO_UNMANAGED) == 0)
6613 VM_PAGE_OBJECT_BUSY_ASSERT(m);
6614 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
6615 ("pmap_enter: flags %u has reserved bits set", flags));
6616 pa = VM_PAGE_TO_PHYS(m);
6617 newpte = (pt_entry_t)(pa | PG_A | PG_V);
6618 if ((flags & VM_PROT_WRITE) != 0)
6620 if ((prot & VM_PROT_WRITE) != 0)
6622 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
6623 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
6624 if ((prot & VM_PROT_EXECUTE) == 0)
6626 if ((flags & PMAP_ENTER_WIRED) != 0)
6628 if (va < VM_MAXUSER_ADDRESS)
6630 if (pmap == kernel_pmap)
6632 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
6635 * Set modified bit gratuitously for writeable mappings if
6636 * the page is unmanaged. We do not want to take a fault
6637 * to do the dirty bit accounting for these mappings.
6639 if ((m->oflags & VPO_UNMANAGED) != 0) {
6640 if ((newpte & PG_RW) != 0)
6643 newpte |= PG_MANAGED;
6647 if ((flags & PMAP_ENTER_LARGEPAGE) != 0) {
6648 KASSERT((m->oflags & VPO_UNMANAGED) != 0,
6649 ("managed largepage va %#lx flags %#x", va, flags));
6650 rv = pmap_enter_largepage(pmap, va, newpte | PG_PS, flags,
6655 /* Assert the required virtual and physical alignment. */
6656 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
6657 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
6658 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m, &lock);
6664 * In the case that a page table page is not
6665 * resident, we are creating it here.
6668 pde = pmap_pde(pmap, va);
6669 if (pde != NULL && (*pde & PG_V) != 0 && ((*pde & PG_PS) == 0 ||
6670 pmap_demote_pde_locked(pmap, pde, va, &lock))) {
6671 pte = pmap_pde_to_pte(pde, va);
6672 if (va < VM_MAXUSER_ADDRESS && mpte == NULL) {
6673 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
6676 } else if (va < VM_MAXUSER_ADDRESS) {
6678 * Here if the pte page isn't mapped, or if it has been
6681 nosleep = (flags & PMAP_ENTER_NOSLEEP) != 0;
6682 mpte = _pmap_allocpte(pmap, pmap_pde_pindex(va),
6683 nosleep ? NULL : &lock, va);
6684 if (mpte == NULL && nosleep) {
6685 rv = KERN_RESOURCE_SHORTAGE;
6690 panic("pmap_enter: invalid page directory va=%#lx", va);
6694 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86)
6695 newpte |= pmap_pkru_get(pmap, va);
6698 * Is the specified virtual address already mapped?
6700 if ((origpte & PG_V) != 0) {
6702 * Wiring change, just update stats. We don't worry about
6703 * wiring PT pages as they remain resident as long as there
6704 * are valid mappings in them. Hence, if a user page is wired,
6705 * the PT page will be also.
6707 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
6708 pmap->pm_stats.wired_count++;
6709 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
6710 pmap->pm_stats.wired_count--;
6713 * Remove the extra PT page reference.
6717 KASSERT(mpte->ref_count > 0,
6718 ("pmap_enter: missing reference to page table page,"
6723 * Has the physical page changed?
6725 opa = origpte & PG_FRAME;
6728 * No, might be a protection or wiring change.
6730 if ((origpte & PG_MANAGED) != 0 &&
6731 (newpte & PG_RW) != 0)
6732 vm_page_aflag_set(m, PGA_WRITEABLE);
6733 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
6739 * The physical page has changed. Temporarily invalidate
6740 * the mapping. This ensures that all threads sharing the
6741 * pmap keep a consistent view of the mapping, which is
6742 * necessary for the correct handling of COW faults. It
6743 * also permits reuse of the old mapping's PV entry,
6744 * avoiding an allocation.
6746 * For consistency, handle unmanaged mappings the same way.
6748 origpte = pte_load_clear(pte);
6749 KASSERT((origpte & PG_FRAME) == opa,
6750 ("pmap_enter: unexpected pa update for %#lx", va));
6751 if ((origpte & PG_MANAGED) != 0) {
6752 om = PHYS_TO_VM_PAGE(opa);
6755 * The pmap lock is sufficient to synchronize with
6756 * concurrent calls to pmap_page_test_mappings() and
6757 * pmap_ts_referenced().
6759 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
6761 if ((origpte & PG_A) != 0) {
6762 pmap_invalidate_page(pmap, va);
6763 vm_page_aflag_set(om, PGA_REFERENCED);
6765 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, opa);
6766 pv = pmap_pvh_remove(&om->md, pmap, va);
6768 ("pmap_enter: no PV entry for %#lx", va));
6769 if ((newpte & PG_MANAGED) == 0)
6770 free_pv_entry(pmap, pv);
6771 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
6772 TAILQ_EMPTY(&om->md.pv_list) &&
6773 ((om->flags & PG_FICTITIOUS) != 0 ||
6774 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
6775 vm_page_aflag_clear(om, PGA_WRITEABLE);
6778 * Since this mapping is unmanaged, assume that PG_A
6781 pmap_invalidate_page(pmap, va);
6786 * Increment the counters.
6788 if ((newpte & PG_W) != 0)
6789 pmap->pm_stats.wired_count++;
6790 pmap_resident_count_inc(pmap, 1);
6794 * Enter on the PV list if part of our managed memory.
6796 if ((newpte & PG_MANAGED) != 0) {
6798 pv = get_pv_entry(pmap, &lock);
6801 CHANGE_PV_LIST_LOCK_TO_PHYS(&lock, pa);
6802 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
6804 if ((newpte & PG_RW) != 0)
6805 vm_page_aflag_set(m, PGA_WRITEABLE);
6811 if ((origpte & PG_V) != 0) {
6813 origpte = pte_load_store(pte, newpte);
6814 KASSERT((origpte & PG_FRAME) == pa,
6815 ("pmap_enter: unexpected pa update for %#lx", va));
6816 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
6818 if ((origpte & PG_MANAGED) != 0)
6822 * Although the PTE may still have PG_RW set, TLB
6823 * invalidation may nonetheless be required because
6824 * the PTE no longer has PG_M set.
6826 } else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
6828 * This PTE change does not require TLB invalidation.
6832 if ((origpte & PG_A) != 0)
6833 pmap_invalidate_page(pmap, va);
6835 pte_store(pte, newpte);
6839 #if VM_NRESERVLEVEL > 0
6841 * If both the page table page and the reservation are fully
6842 * populated, then attempt promotion.
6844 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
6845 pmap_ps_enabled(pmap) &&
6846 (m->flags & PG_FICTITIOUS) == 0 &&
6847 vm_reserv_level_iffullpop(m) == 0)
6848 pmap_promote_pde(pmap, pde, va, &lock);
6860 * Tries to create a read- and/or execute-only 2MB page mapping. Returns true
6861 * if successful. Returns false if (1) a page table page cannot be allocated
6862 * without sleeping, (2) a mapping already exists at the specified virtual
6863 * address, or (3) a PV entry cannot be allocated without reclaiming another
6867 pmap_enter_2mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
6868 struct rwlock **lockp)
6873 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6874 PG_V = pmap_valid_bit(pmap);
6875 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(pmap, m->md.pat_mode, 1) |
6877 if ((m->oflags & VPO_UNMANAGED) == 0)
6878 newpde |= PG_MANAGED;
6879 if ((prot & VM_PROT_EXECUTE) == 0)
6881 if (va < VM_MAXUSER_ADDRESS)
6883 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
6884 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL, lockp) ==
6889 * Returns true if every page table entry in the specified page table page is
6893 pmap_every_pte_zero(vm_paddr_t pa)
6895 pt_entry_t *pt_end, *pte;
6897 KASSERT((pa & PAGE_MASK) == 0, ("pa is misaligned"));
6898 pte = (pt_entry_t *)PHYS_TO_DMAP(pa);
6899 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
6907 * Tries to create the specified 2MB page mapping. Returns KERN_SUCCESS if
6908 * the mapping was created, and either KERN_FAILURE or KERN_RESOURCE_SHORTAGE
6909 * otherwise. Returns KERN_FAILURE if PMAP_ENTER_NOREPLACE was specified and
6910 * a mapping already exists at the specified virtual address. Returns
6911 * KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NOSLEEP was specified and a page table
6912 * page allocation failed. Returns KERN_RESOURCE_SHORTAGE if
6913 * PMAP_ENTER_NORECLAIM was specified and a PV entry allocation failed.
6915 * The parameter "m" is only used when creating a managed, writeable mapping.
6918 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
6919 vm_page_t m, struct rwlock **lockp)
6921 struct spglist free;
6922 pd_entry_t oldpde, *pde;
6923 pt_entry_t PG_G, PG_RW, PG_V;
6926 KASSERT(pmap == kernel_pmap || (newpde & PG_W) == 0,
6927 ("pmap_enter_pde: cannot create wired user mapping"));
6928 PG_G = pmap_global_bit(pmap);
6929 PG_RW = pmap_rw_bit(pmap);
6930 KASSERT((newpde & (pmap_modified_bit(pmap) | PG_RW)) != PG_RW,
6931 ("pmap_enter_pde: newpde is missing PG_M"));
6932 PG_V = pmap_valid_bit(pmap);
6933 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
6935 if (!pmap_allow_2m_x_page(pmap, pmap_pde_ept_executable(pmap,
6937 CTR2(KTR_PMAP, "pmap_enter_pde: 2m x blocked for va %#lx"
6938 " in pmap %p", va, pmap);
6939 return (KERN_FAILURE);
6941 if ((pde = pmap_alloc_pde(pmap, va, &pdpg, (flags &
6942 PMAP_ENTER_NOSLEEP) != 0 ? NULL : lockp)) == NULL) {
6943 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6944 " in pmap %p", va, pmap);
6945 return (KERN_RESOURCE_SHORTAGE);
6949 * If pkru is not same for the whole pde range, return failure
6950 * and let vm_fault() cope. Check after pde allocation, since
6953 if (!pmap_pkru_same(pmap, va, va + NBPDR)) {
6954 pmap_abort_ptp(pmap, va, pdpg);
6955 return (KERN_FAILURE);
6957 if (va < VM_MAXUSER_ADDRESS && pmap->pm_type == PT_X86) {
6958 newpde &= ~X86_PG_PKU_MASK;
6959 newpde |= pmap_pkru_get(pmap, va);
6963 * If there are existing mappings, either abort or remove them.
6966 if ((oldpde & PG_V) != 0) {
6967 KASSERT(pdpg == NULL || pdpg->ref_count > 1,
6968 ("pmap_enter_pde: pdpg's reference count is too low"));
6969 if ((flags & PMAP_ENTER_NOREPLACE) != 0 && (va <
6970 VM_MAXUSER_ADDRESS || (oldpde & PG_PS) != 0 ||
6971 !pmap_every_pte_zero(oldpde & PG_FRAME))) {
6974 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
6975 " in pmap %p", va, pmap);
6976 return (KERN_FAILURE);
6978 /* Break the existing mapping(s). */
6980 if ((oldpde & PG_PS) != 0) {
6982 * The reference to the PD page that was acquired by
6983 * pmap_alloc_pde() ensures that it won't be freed.
6984 * However, if the PDE resulted from a promotion, then
6985 * a reserved PT page could be freed.
6987 (void)pmap_remove_pde(pmap, pde, va, &free, lockp);
6988 if ((oldpde & PG_G) == 0)
6989 pmap_invalidate_pde_page(pmap, va, oldpde);
6991 pmap_delayed_invl_start();
6992 if (pmap_remove_ptes(pmap, va, va + NBPDR, pde, &free,
6994 pmap_invalidate_all(pmap);
6995 pmap_delayed_invl_finish();
6997 if (va < VM_MAXUSER_ADDRESS) {
6998 vm_page_free_pages_toq(&free, true);
6999 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
7002 KASSERT(SLIST_EMPTY(&free),
7003 ("pmap_enter_pde: freed kernel page table page"));
7006 * Both pmap_remove_pde() and pmap_remove_ptes() will
7007 * leave the kernel page table page zero filled.
7009 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
7010 if (pmap_insert_pt_page(pmap, mt, false))
7011 panic("pmap_enter_pde: trie insert failed");
7015 if ((newpde & PG_MANAGED) != 0) {
7017 * Abort this mapping if its PV entry could not be created.
7019 if (!pmap_pv_insert_pde(pmap, va, newpde, flags, lockp)) {
7021 pmap_abort_ptp(pmap, va, pdpg);
7022 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
7023 " in pmap %p", va, pmap);
7024 return (KERN_RESOURCE_SHORTAGE);
7026 if ((newpde & PG_RW) != 0) {
7027 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7028 vm_page_aflag_set(mt, PGA_WRITEABLE);
7033 * Increment counters.
7035 if ((newpde & PG_W) != 0)
7036 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
7037 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7040 * Map the superpage. (This is not a promoted mapping; there will not
7041 * be any lingering 4KB page mappings in the TLB.)
7043 pde_store(pde, newpde);
7045 atomic_add_long(&pmap_pde_mappings, 1);
7046 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
7048 return (KERN_SUCCESS);
7052 * Maps a sequence of resident pages belonging to the same object.
7053 * The sequence begins with the given page m_start. This page is
7054 * mapped at the given virtual address start. Each subsequent page is
7055 * mapped at a virtual address that is offset from start by the same
7056 * amount as the page is offset from m_start within the object. The
7057 * last page in the sequence is the page with the largest offset from
7058 * m_start that can be mapped at a virtual address less than the given
7059 * virtual address end. Not every virtual page between start and end
7060 * is mapped; only those for which a resident page exists with the
7061 * corresponding offset from m_start are mapped.
7064 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
7065 vm_page_t m_start, vm_prot_t prot)
7067 struct rwlock *lock;
7070 vm_pindex_t diff, psize;
7072 VM_OBJECT_ASSERT_LOCKED(m_start->object);
7074 psize = atop(end - start);
7079 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
7080 va = start + ptoa(diff);
7081 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
7082 m->psind == 1 && pmap_ps_enabled(pmap) &&
7083 pmap_allow_2m_x_page(pmap, (prot & VM_PROT_EXECUTE) != 0) &&
7084 pmap_enter_2mpage(pmap, va, m, prot, &lock))
7085 m = &m[NBPDR / PAGE_SIZE - 1];
7087 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
7089 m = TAILQ_NEXT(m, listq);
7097 * this code makes some *MAJOR* assumptions:
7098 * 1. Current pmap & pmap exists.
7101 * 4. No page table pages.
7102 * but is *MUCH* faster than pmap_enter...
7106 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
7108 struct rwlock *lock;
7112 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL, &lock);
7119 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
7120 vm_prot_t prot, vm_page_t mpte, struct rwlock **lockp)
7122 pt_entry_t newpte, *pte, PG_V;
7124 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
7125 (m->oflags & VPO_UNMANAGED) != 0,
7126 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
7127 PG_V = pmap_valid_bit(pmap);
7128 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
7131 * In the case that a page table page is not
7132 * resident, we are creating it here.
7134 if (va < VM_MAXUSER_ADDRESS) {
7135 vm_pindex_t ptepindex;
7139 * Calculate pagetable page index
7141 ptepindex = pmap_pde_pindex(va);
7142 if (mpte && (mpte->pindex == ptepindex)) {
7146 * Get the page directory entry
7148 ptepa = pmap_pde(pmap, va);
7151 * If the page table page is mapped, we just increment
7152 * the hold count, and activate it. Otherwise, we
7153 * attempt to allocate a page table page. If this
7154 * attempt fails, we don't retry. Instead, we give up.
7156 if (ptepa && (*ptepa & PG_V) != 0) {
7159 mpte = PHYS_TO_VM_PAGE(*ptepa & PG_FRAME);
7163 * Pass NULL instead of the PV list lock
7164 * pointer, because we don't intend to sleep.
7166 mpte = _pmap_allocpte(pmap, ptepindex, NULL,
7172 pte = (pt_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mpte));
7173 pte = &pte[pmap_pte_index(va)];
7185 * Enter on the PV list if part of our managed memory.
7187 if ((m->oflags & VPO_UNMANAGED) == 0 &&
7188 !pmap_try_insert_pv_entry(pmap, va, m, lockp)) {
7190 pmap_abort_ptp(pmap, va, mpte);
7195 * Increment counters
7197 pmap_resident_count_inc(pmap, 1);
7199 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
7200 pmap_cache_bits(pmap, m->md.pat_mode, 0);
7201 if ((m->oflags & VPO_UNMANAGED) == 0)
7202 newpte |= PG_MANAGED;
7203 if ((prot & VM_PROT_EXECUTE) == 0)
7205 if (va < VM_MAXUSER_ADDRESS)
7206 newpte |= PG_U | pmap_pkru_get(pmap, va);
7207 pte_store(pte, newpte);
7212 * Make a temporary mapping for a physical address. This is only intended
7213 * to be used for panic dumps.
7216 pmap_kenter_temporary(vm_paddr_t pa, int i)
7220 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
7221 pmap_kenter(va, pa);
7223 return ((void *)crashdumpmap);
7227 * This code maps large physical mmap regions into the
7228 * processor address space. Note that some shortcuts
7229 * are taken, but the code works.
7232 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
7233 vm_pindex_t pindex, vm_size_t size)
7236 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
7237 vm_paddr_t pa, ptepa;
7241 PG_A = pmap_accessed_bit(pmap);
7242 PG_M = pmap_modified_bit(pmap);
7243 PG_V = pmap_valid_bit(pmap);
7244 PG_RW = pmap_rw_bit(pmap);
7246 VM_OBJECT_ASSERT_WLOCKED(object);
7247 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
7248 ("pmap_object_init_pt: non-device object"));
7249 if ((addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
7250 if (!pmap_ps_enabled(pmap))
7252 if (!vm_object_populate(object, pindex, pindex + atop(size)))
7254 p = vm_page_lookup(object, pindex);
7255 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7256 ("pmap_object_init_pt: invalid page %p", p));
7257 pat_mode = p->md.pat_mode;
7260 * Abort the mapping if the first page is not physically
7261 * aligned to a 2MB page boundary.
7263 ptepa = VM_PAGE_TO_PHYS(p);
7264 if (ptepa & (NBPDR - 1))
7268 * Skip the first page. Abort the mapping if the rest of
7269 * the pages are not physically contiguous or have differing
7270 * memory attributes.
7272 p = TAILQ_NEXT(p, listq);
7273 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
7275 KASSERT(p->valid == VM_PAGE_BITS_ALL,
7276 ("pmap_object_init_pt: invalid page %p", p));
7277 if (pa != VM_PAGE_TO_PHYS(p) ||
7278 pat_mode != p->md.pat_mode)
7280 p = TAILQ_NEXT(p, listq);
7284 * Map using 2MB pages. Since "ptepa" is 2M aligned and
7285 * "size" is a multiple of 2M, adding the PAT setting to "pa"
7286 * will not affect the termination of this loop.
7289 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, 1);
7290 pa < ptepa + size; pa += NBPDR) {
7291 pde = pmap_alloc_pde(pmap, addr, &pdpg, NULL);
7294 * The creation of mappings below is only an
7295 * optimization. If a page directory page
7296 * cannot be allocated without blocking,
7297 * continue on to the next mapping rather than
7303 if ((*pde & PG_V) == 0) {
7304 pde_store(pde, pa | PG_PS | PG_M | PG_A |
7305 PG_U | PG_RW | PG_V);
7306 pmap_resident_count_inc(pmap, NBPDR / PAGE_SIZE);
7307 atomic_add_long(&pmap_pde_mappings, 1);
7309 /* Continue on if the PDE is already valid. */
7311 KASSERT(pdpg->ref_count > 0,
7312 ("pmap_object_init_pt: missing reference "
7313 "to page directory page, va: 0x%lx", addr));
7322 * Clear the wired attribute from the mappings for the specified range of
7323 * addresses in the given pmap. Every valid mapping within that range
7324 * must have the wired attribute set. In contrast, invalid mappings
7325 * cannot have the wired attribute set, so they are ignored.
7327 * The wired attribute of the page table entry is not a hardware
7328 * feature, so there is no need to invalidate any TLB entries.
7329 * Since pmap_demote_pde() for the wired entry must never fail,
7330 * pmap_delayed_invl_start()/finish() calls around the
7331 * function are not needed.
7334 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
7336 vm_offset_t va_next;
7337 pml4_entry_t *pml4e;
7340 pt_entry_t *pte, PG_V, PG_G;
7342 PG_V = pmap_valid_bit(pmap);
7343 PG_G = pmap_global_bit(pmap);
7345 for (; sva < eva; sva = va_next) {
7346 pml4e = pmap_pml4e(pmap, sva);
7347 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7348 va_next = (sva + NBPML4) & ~PML4MASK;
7354 va_next = (sva + NBPDP) & ~PDPMASK;
7357 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
7358 if ((*pdpe & PG_V) == 0)
7360 if ((*pdpe & PG_PS) != 0) {
7361 KASSERT(va_next <= eva,
7362 ("partial update of non-transparent 1G mapping "
7363 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7364 *pdpe, sva, eva, va_next));
7365 MPASS(pmap != kernel_pmap); /* XXXKIB */
7366 MPASS((*pdpe & (PG_MANAGED | PG_G)) == 0);
7367 atomic_clear_long(pdpe, PG_W);
7368 pmap->pm_stats.wired_count -= NBPDP / PAGE_SIZE;
7372 va_next = (sva + NBPDR) & ~PDRMASK;
7375 pde = pmap_pdpe_to_pde(pdpe, sva);
7376 if ((*pde & PG_V) == 0)
7378 if ((*pde & PG_PS) != 0) {
7379 if ((*pde & PG_W) == 0)
7380 panic("pmap_unwire: pde %#jx is missing PG_W",
7384 * Are we unwiring the entire large page? If not,
7385 * demote the mapping and fall through.
7387 if (sva + NBPDR == va_next && eva >= va_next) {
7388 atomic_clear_long(pde, PG_W);
7389 pmap->pm_stats.wired_count -= NBPDR /
7392 } else if (!pmap_demote_pde(pmap, pde, sva))
7393 panic("pmap_unwire: demotion failed");
7397 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
7399 if ((*pte & PG_V) == 0)
7401 if ((*pte & PG_W) == 0)
7402 panic("pmap_unwire: pte %#jx is missing PG_W",
7406 * PG_W must be cleared atomically. Although the pmap
7407 * lock synchronizes access to PG_W, another processor
7408 * could be setting PG_M and/or PG_A concurrently.
7410 atomic_clear_long(pte, PG_W);
7411 pmap->pm_stats.wired_count--;
7418 * Copy the range specified by src_addr/len
7419 * from the source map to the range dst_addr/len
7420 * in the destination map.
7422 * This routine is only advisory and need not do anything.
7425 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
7426 vm_offset_t src_addr)
7428 struct rwlock *lock;
7429 pml4_entry_t *pml4e;
7431 pd_entry_t *pde, srcptepaddr;
7432 pt_entry_t *dst_pte, PG_A, PG_M, PG_V, ptetemp, *src_pte;
7433 vm_offset_t addr, end_addr, va_next;
7434 vm_page_t dst_pdpg, dstmpte, srcmpte;
7436 if (dst_addr != src_addr)
7439 if (dst_pmap->pm_type != src_pmap->pm_type)
7443 * EPT page table entries that require emulation of A/D bits are
7444 * sensitive to clearing the PG_A bit (aka EPT_PG_READ). Although
7445 * we clear PG_M (aka EPT_PG_WRITE) concomitantly, the PG_U bit
7446 * (aka EPT_PG_EXECUTE) could still be set. Since some EPT
7447 * implementations flag an EPT misconfiguration for exec-only
7448 * mappings we skip this function entirely for emulated pmaps.
7450 if (pmap_emulate_ad_bits(dst_pmap))
7453 end_addr = src_addr + len;
7455 if (dst_pmap < src_pmap) {
7456 PMAP_LOCK(dst_pmap);
7457 PMAP_LOCK(src_pmap);
7459 PMAP_LOCK(src_pmap);
7460 PMAP_LOCK(dst_pmap);
7463 PG_A = pmap_accessed_bit(dst_pmap);
7464 PG_M = pmap_modified_bit(dst_pmap);
7465 PG_V = pmap_valid_bit(dst_pmap);
7467 for (addr = src_addr; addr < end_addr; addr = va_next) {
7468 KASSERT(addr < UPT_MIN_ADDRESS,
7469 ("pmap_copy: invalid to pmap_copy page tables"));
7471 pml4e = pmap_pml4e(src_pmap, addr);
7472 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
7473 va_next = (addr + NBPML4) & ~PML4MASK;
7479 va_next = (addr + NBPDP) & ~PDPMASK;
7482 pdpe = pmap_pml4e_to_pdpe(pml4e, addr);
7483 if ((*pdpe & PG_V) == 0)
7485 if ((*pdpe & PG_PS) != 0) {
7486 KASSERT(va_next <= end_addr,
7487 ("partial update of non-transparent 1G mapping "
7488 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7489 *pdpe, addr, end_addr, va_next));
7490 MPASS((addr & PDPMASK) == 0);
7491 MPASS((*pdpe & PG_MANAGED) == 0);
7492 srcptepaddr = *pdpe;
7493 pdpe = pmap_pdpe(dst_pmap, addr);
7495 if (_pmap_allocpte(dst_pmap,
7496 pmap_pml4e_pindex(addr), NULL, addr) ==
7499 pdpe = pmap_pdpe(dst_pmap, addr);
7501 pml4e = pmap_pml4e(dst_pmap, addr);
7502 dst_pdpg = PHYS_TO_VM_PAGE(*pml4e & PG_FRAME);
7503 dst_pdpg->ref_count++;
7506 ("1G mapping present in dst pmap "
7507 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
7508 *pdpe, addr, end_addr, va_next));
7509 *pdpe = srcptepaddr & ~PG_W;
7510 pmap_resident_count_inc(dst_pmap, NBPDP / PAGE_SIZE);
7514 va_next = (addr + NBPDR) & ~PDRMASK;
7518 pde = pmap_pdpe_to_pde(pdpe, addr);
7520 if (srcptepaddr == 0)
7523 if (srcptepaddr & PG_PS) {
7524 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
7526 pde = pmap_alloc_pde(dst_pmap, addr, &dst_pdpg, NULL);
7529 if (*pde == 0 && ((srcptepaddr & PG_MANAGED) == 0 ||
7530 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
7531 PMAP_ENTER_NORECLAIM, &lock))) {
7532 *pde = srcptepaddr & ~PG_W;
7533 pmap_resident_count_inc(dst_pmap, NBPDR /
7535 atomic_add_long(&pmap_pde_mappings, 1);
7537 pmap_abort_ptp(dst_pmap, addr, dst_pdpg);
7541 srcptepaddr &= PG_FRAME;
7542 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr);
7543 KASSERT(srcmpte->ref_count > 0,
7544 ("pmap_copy: source page table page is unused"));
7546 if (va_next > end_addr)
7549 src_pte = (pt_entry_t *)PHYS_TO_DMAP(srcptepaddr);
7550 src_pte = &src_pte[pmap_pte_index(addr)];
7552 for (; addr < va_next; addr += PAGE_SIZE, src_pte++) {
7556 * We only virtual copy managed pages.
7558 if ((ptetemp & PG_MANAGED) == 0)
7561 if (dstmpte != NULL) {
7562 KASSERT(dstmpte->pindex ==
7563 pmap_pde_pindex(addr),
7564 ("dstmpte pindex/addr mismatch"));
7565 dstmpte->ref_count++;
7566 } else if ((dstmpte = pmap_allocpte(dst_pmap, addr,
7569 dst_pte = (pt_entry_t *)
7570 PHYS_TO_DMAP(VM_PAGE_TO_PHYS(dstmpte));
7571 dst_pte = &dst_pte[pmap_pte_index(addr)];
7572 if (*dst_pte == 0 &&
7573 pmap_try_insert_pv_entry(dst_pmap, addr,
7574 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME), &lock)) {
7576 * Clear the wired, modified, and accessed
7577 * (referenced) bits during the copy.
7579 *dst_pte = ptetemp & ~(PG_W | PG_M | PG_A);
7580 pmap_resident_count_inc(dst_pmap, 1);
7582 pmap_abort_ptp(dst_pmap, addr, dstmpte);
7585 /* Have we copied all of the valid mappings? */
7586 if (dstmpte->ref_count >= srcmpte->ref_count)
7593 PMAP_UNLOCK(src_pmap);
7594 PMAP_UNLOCK(dst_pmap);
7598 pmap_vmspace_copy(pmap_t dst_pmap, pmap_t src_pmap)
7602 if (dst_pmap->pm_type != src_pmap->pm_type ||
7603 dst_pmap->pm_type != PT_X86 ||
7604 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
7607 if (dst_pmap < src_pmap) {
7608 PMAP_LOCK(dst_pmap);
7609 PMAP_LOCK(src_pmap);
7611 PMAP_LOCK(src_pmap);
7612 PMAP_LOCK(dst_pmap);
7614 error = pmap_pkru_copy(dst_pmap, src_pmap);
7615 /* Clean up partial copy on failure due to no memory. */
7616 if (error == ENOMEM)
7617 pmap_pkru_deassign_all(dst_pmap);
7618 PMAP_UNLOCK(src_pmap);
7619 PMAP_UNLOCK(dst_pmap);
7620 if (error != ENOMEM)
7628 * Zero the specified hardware page.
7631 pmap_zero_page(vm_page_t m)
7633 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7635 pagezero((void *)va);
7639 * Zero an an area within a single hardware page. off and size must not
7640 * cover an area beyond a single hardware page.
7643 pmap_zero_page_area(vm_page_t m, int off, int size)
7645 vm_offset_t va = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m));
7647 if (off == 0 && size == PAGE_SIZE)
7648 pagezero((void *)va);
7650 bzero((char *)va + off, size);
7654 * Copy 1 specified hardware page to another.
7657 pmap_copy_page(vm_page_t msrc, vm_page_t mdst)
7659 vm_offset_t src = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(msrc));
7660 vm_offset_t dst = PHYS_TO_DMAP(VM_PAGE_TO_PHYS(mdst));
7662 pagecopy((void *)src, (void *)dst);
7665 int unmapped_buf_allowed = 1;
7668 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
7669 vm_offset_t b_offset, int xfersize)
7673 vm_offset_t vaddr[2], a_pg_offset, b_pg_offset;
7677 while (xfersize > 0) {
7678 a_pg_offset = a_offset & PAGE_MASK;
7679 pages[0] = ma[a_offset >> PAGE_SHIFT];
7680 b_pg_offset = b_offset & PAGE_MASK;
7681 pages[1] = mb[b_offset >> PAGE_SHIFT];
7682 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
7683 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
7684 mapped = pmap_map_io_transient(pages, vaddr, 2, FALSE);
7685 a_cp = (char *)vaddr[0] + a_pg_offset;
7686 b_cp = (char *)vaddr[1] + b_pg_offset;
7687 bcopy(a_cp, b_cp, cnt);
7688 if (__predict_false(mapped))
7689 pmap_unmap_io_transient(pages, vaddr, 2, FALSE);
7697 * Returns true if the pmap's pv is one of the first
7698 * 16 pvs linked to from this page. This count may
7699 * be changed upwards or downwards in the future; it
7700 * is only necessary that true be returned for a small
7701 * subset of pmaps for proper page aging.
7704 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
7706 struct md_page *pvh;
7707 struct rwlock *lock;
7712 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
7713 ("pmap_page_exists_quick: page %p is not managed", m));
7715 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7717 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7718 if (PV_PMAP(pv) == pmap) {
7726 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
7727 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7728 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7729 if (PV_PMAP(pv) == pmap) {
7743 * pmap_page_wired_mappings:
7745 * Return the number of managed mappings to the given physical page
7749 pmap_page_wired_mappings(vm_page_t m)
7751 struct rwlock *lock;
7752 struct md_page *pvh;
7756 int count, md_gen, pvh_gen;
7758 if ((m->oflags & VPO_UNMANAGED) != 0)
7760 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7764 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
7766 if (!PMAP_TRYLOCK(pmap)) {
7767 md_gen = m->md.pv_gen;
7771 if (md_gen != m->md.pv_gen) {
7776 pte = pmap_pte(pmap, pv->pv_va);
7777 if ((*pte & PG_W) != 0)
7781 if ((m->flags & PG_FICTITIOUS) == 0) {
7782 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
7783 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
7785 if (!PMAP_TRYLOCK(pmap)) {
7786 md_gen = m->md.pv_gen;
7787 pvh_gen = pvh->pv_gen;
7791 if (md_gen != m->md.pv_gen ||
7792 pvh_gen != pvh->pv_gen) {
7797 pte = pmap_pde(pmap, pv->pv_va);
7798 if ((*pte & PG_W) != 0)
7808 * Returns TRUE if the given page is mapped individually or as part of
7809 * a 2mpage. Otherwise, returns FALSE.
7812 pmap_page_is_mapped(vm_page_t m)
7814 struct rwlock *lock;
7817 if ((m->oflags & VPO_UNMANAGED) != 0)
7819 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
7821 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
7822 ((m->flags & PG_FICTITIOUS) == 0 &&
7823 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
7829 * Destroy all managed, non-wired mappings in the given user-space
7830 * pmap. This pmap cannot be active on any processor besides the
7833 * This function cannot be applied to the kernel pmap. Moreover, it
7834 * is not intended for general use. It is only to be used during
7835 * process termination. Consequently, it can be implemented in ways
7836 * that make it faster than pmap_remove(). First, it can more quickly
7837 * destroy mappings by iterating over the pmap's collection of PV
7838 * entries, rather than searching the page table. Second, it doesn't
7839 * have to test and clear the page table entries atomically, because
7840 * no processor is currently accessing the user address space. In
7841 * particular, a page table entry's dirty bit won't change state once
7842 * this function starts.
7844 * Although this function destroys all of the pmap's managed,
7845 * non-wired mappings, it can delay and batch the invalidation of TLB
7846 * entries without calling pmap_delayed_invl_start() and
7847 * pmap_delayed_invl_finish(). Because the pmap is not active on
7848 * any other processor, none of these TLB entries will ever be used
7849 * before their eventual invalidation. Consequently, there is no need
7850 * for either pmap_remove_all() or pmap_remove_write() to wait for
7851 * that eventual TLB invalidation.
7854 pmap_remove_pages(pmap_t pmap)
7857 pt_entry_t *pte, tpte;
7858 pt_entry_t PG_M, PG_RW, PG_V;
7859 struct spglist free;
7860 struct pv_chunklist free_chunks[PMAP_MEMDOM];
7861 vm_page_t m, mpte, mt;
7863 struct md_page *pvh;
7864 struct pv_chunk *pc, *npc;
7865 struct rwlock *lock;
7867 uint64_t inuse, bitmask;
7868 int allfree, field, freed, i, idx;
7869 boolean_t superpage;
7873 * Assert that the given pmap is only active on the current
7874 * CPU. Unfortunately, we cannot block another CPU from
7875 * activating the pmap while this function is executing.
7877 KASSERT(pmap == PCPU_GET(curpmap), ("non-current pmap %p", pmap));
7880 cpuset_t other_cpus;
7882 other_cpus = all_cpus;
7884 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
7885 CPU_AND(&other_cpus, &pmap->pm_active);
7887 KASSERT(CPU_EMPTY(&other_cpus), ("pmap active %p", pmap));
7892 PG_M = pmap_modified_bit(pmap);
7893 PG_V = pmap_valid_bit(pmap);
7894 PG_RW = pmap_rw_bit(pmap);
7896 for (i = 0; i < PMAP_MEMDOM; i++)
7897 TAILQ_INIT(&free_chunks[i]);
7900 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
7903 for (field = 0; field < _NPCM; field++) {
7904 inuse = ~pc->pc_map[field] & pc_freemask[field];
7905 while (inuse != 0) {
7907 bitmask = 1UL << bit;
7908 idx = field * 64 + bit;
7909 pv = &pc->pc_pventry[idx];
7912 pte = pmap_pdpe(pmap, pv->pv_va);
7914 pte = pmap_pdpe_to_pde(pte, pv->pv_va);
7916 if ((tpte & (PG_PS | PG_V)) == PG_V) {
7919 pte = (pt_entry_t *)PHYS_TO_DMAP(tpte &
7921 pte = &pte[pmap_pte_index(pv->pv_va)];
7925 * Keep track whether 'tpte' is a
7926 * superpage explicitly instead of
7927 * relying on PG_PS being set.
7929 * This is because PG_PS is numerically
7930 * identical to PG_PTE_PAT and thus a
7931 * regular page could be mistaken for
7937 if ((tpte & PG_V) == 0) {
7938 panic("bad pte va %lx pte %lx",
7943 * We cannot remove wired pages from a process' mapping at this time
7951 pa = tpte & PG_PS_FRAME;
7953 pa = tpte & PG_FRAME;
7955 m = PHYS_TO_VM_PAGE(pa);
7956 KASSERT(m->phys_addr == pa,
7957 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
7958 m, (uintmax_t)m->phys_addr,
7961 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
7962 m < &vm_page_array[vm_page_array_size],
7963 ("pmap_remove_pages: bad tpte %#jx",
7969 * Update the vm_page_t clean/reference bits.
7971 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
7973 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7979 CHANGE_PV_LIST_LOCK_TO_VM_PAGE(&lock, m);
7982 pc->pc_map[field] |= bitmask;
7984 pmap_resident_count_dec(pmap, NBPDR / PAGE_SIZE);
7985 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
7986 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
7988 if (TAILQ_EMPTY(&pvh->pv_list)) {
7989 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
7990 if ((mt->a.flags & PGA_WRITEABLE) != 0 &&
7991 TAILQ_EMPTY(&mt->md.pv_list))
7992 vm_page_aflag_clear(mt, PGA_WRITEABLE);
7994 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
7996 KASSERT(mpte->valid == VM_PAGE_BITS_ALL,
7997 ("pmap_remove_pages: pte page not promoted"));
7998 pmap_resident_count_dec(pmap, 1);
7999 KASSERT(mpte->ref_count == NPTEPG,
8000 ("pmap_remove_pages: pte page reference count error"));
8001 mpte->ref_count = 0;
8002 pmap_add_delayed_free_list(mpte, &free, FALSE);
8005 pmap_resident_count_dec(pmap, 1);
8006 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8008 if ((m->a.flags & PGA_WRITEABLE) != 0 &&
8009 TAILQ_EMPTY(&m->md.pv_list) &&
8010 (m->flags & PG_FICTITIOUS) == 0) {
8011 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8012 if (TAILQ_EMPTY(&pvh->pv_list))
8013 vm_page_aflag_clear(m, PGA_WRITEABLE);
8016 pmap_unuse_pt(pmap, pv->pv_va, ptepde, &free);
8020 PV_STAT(atomic_add_long(&pv_entry_frees, freed));
8021 PV_STAT(atomic_add_int(&pv_entry_spare, freed));
8022 PV_STAT(atomic_subtract_long(&pv_entry_count, freed));
8024 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
8025 TAILQ_INSERT_TAIL(&free_chunks[pc_to_domain(pc)], pc, pc_list);
8030 pmap_invalidate_all(pmap);
8031 pmap_pkru_deassign_all(pmap);
8032 free_pv_chunk_batch((struct pv_chunklist *)&free_chunks);
8034 vm_page_free_pages_toq(&free, true);
8038 pmap_page_test_mappings(vm_page_t m, boolean_t accessed, boolean_t modified)
8040 struct rwlock *lock;
8042 struct md_page *pvh;
8043 pt_entry_t *pte, mask;
8044 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8046 int md_gen, pvh_gen;
8050 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8053 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8055 if (!PMAP_TRYLOCK(pmap)) {
8056 md_gen = m->md.pv_gen;
8060 if (md_gen != m->md.pv_gen) {
8065 pte = pmap_pte(pmap, pv->pv_va);
8068 PG_M = pmap_modified_bit(pmap);
8069 PG_RW = pmap_rw_bit(pmap);
8070 mask |= PG_RW | PG_M;
8073 PG_A = pmap_accessed_bit(pmap);
8074 PG_V = pmap_valid_bit(pmap);
8075 mask |= PG_V | PG_A;
8077 rv = (*pte & mask) == mask;
8082 if ((m->flags & PG_FICTITIOUS) == 0) {
8083 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
8084 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
8086 if (!PMAP_TRYLOCK(pmap)) {
8087 md_gen = m->md.pv_gen;
8088 pvh_gen = pvh->pv_gen;
8092 if (md_gen != m->md.pv_gen ||
8093 pvh_gen != pvh->pv_gen) {
8098 pte = pmap_pde(pmap, pv->pv_va);
8101 PG_M = pmap_modified_bit(pmap);
8102 PG_RW = pmap_rw_bit(pmap);
8103 mask |= PG_RW | PG_M;
8106 PG_A = pmap_accessed_bit(pmap);
8107 PG_V = pmap_valid_bit(pmap);
8108 mask |= PG_V | PG_A;
8110 rv = (*pte & mask) == mask;
8124 * Return whether or not the specified physical page was modified
8125 * in any physical maps.
8128 pmap_is_modified(vm_page_t m)
8131 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8132 ("pmap_is_modified: page %p is not managed", m));
8135 * If the page is not busied then this check is racy.
8137 if (!pmap_page_is_write_mapped(m))
8139 return (pmap_page_test_mappings(m, FALSE, TRUE));
8143 * pmap_is_prefaultable:
8145 * Return whether or not the specified virtual address is eligible
8149 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
8152 pt_entry_t *pte, PG_V;
8155 PG_V = pmap_valid_bit(pmap);
8158 pde = pmap_pde(pmap, addr);
8159 if (pde != NULL && (*pde & (PG_PS | PG_V)) == PG_V) {
8160 pte = pmap_pde_to_pte(pde, addr);
8161 rv = (*pte & PG_V) == 0;
8168 * pmap_is_referenced:
8170 * Return whether or not the specified physical page was referenced
8171 * in any physical maps.
8174 pmap_is_referenced(vm_page_t m)
8177 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8178 ("pmap_is_referenced: page %p is not managed", m));
8179 return (pmap_page_test_mappings(m, TRUE, FALSE));
8183 * Clear the write and modified bits in each of the given page's mappings.
8186 pmap_remove_write(vm_page_t m)
8188 struct md_page *pvh;
8190 struct rwlock *lock;
8191 pv_entry_t next_pv, pv;
8193 pt_entry_t oldpte, *pte, PG_M, PG_RW;
8195 int pvh_gen, md_gen;
8197 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8198 ("pmap_remove_write: page %p is not managed", m));
8200 vm_page_assert_busied(m);
8201 if (!pmap_page_is_write_mapped(m))
8204 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8205 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8206 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8209 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8211 if (!PMAP_TRYLOCK(pmap)) {
8212 pvh_gen = pvh->pv_gen;
8216 if (pvh_gen != pvh->pv_gen) {
8222 PG_RW = pmap_rw_bit(pmap);
8224 pde = pmap_pde(pmap, va);
8225 if ((*pde & PG_RW) != 0)
8226 (void)pmap_demote_pde_locked(pmap, pde, va, &lock);
8227 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8228 ("inconsistent pv lock %p %p for page %p",
8229 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8232 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8234 if (!PMAP_TRYLOCK(pmap)) {
8235 pvh_gen = pvh->pv_gen;
8236 md_gen = m->md.pv_gen;
8240 if (pvh_gen != pvh->pv_gen ||
8241 md_gen != m->md.pv_gen) {
8247 PG_M = pmap_modified_bit(pmap);
8248 PG_RW = pmap_rw_bit(pmap);
8249 pde = pmap_pde(pmap, pv->pv_va);
8250 KASSERT((*pde & PG_PS) == 0,
8251 ("pmap_remove_write: found a 2mpage in page %p's pv list",
8253 pte = pmap_pde_to_pte(pde, pv->pv_va);
8256 if (oldpte & PG_RW) {
8257 if (!atomic_cmpset_long(pte, oldpte, oldpte &
8260 if ((oldpte & PG_M) != 0)
8262 pmap_invalidate_page(pmap, pv->pv_va);
8267 vm_page_aflag_clear(m, PGA_WRITEABLE);
8268 pmap_delayed_invl_wait(m);
8271 static __inline boolean_t
8272 safe_to_clear_referenced(pmap_t pmap, pt_entry_t pte)
8275 if (!pmap_emulate_ad_bits(pmap))
8278 KASSERT(pmap->pm_type == PT_EPT, ("invalid pm_type %d", pmap->pm_type));
8281 * XWR = 010 or 110 will cause an unconditional EPT misconfiguration
8282 * so we don't let the referenced (aka EPT_PG_READ) bit to be cleared
8283 * if the EPT_PG_WRITE bit is set.
8285 if ((pte & EPT_PG_WRITE) != 0)
8289 * XWR = 100 is allowed only if the PMAP_SUPPORTS_EXEC_ONLY is set.
8291 if ((pte & EPT_PG_EXECUTE) == 0 ||
8292 ((pmap->pm_flags & PMAP_SUPPORTS_EXEC_ONLY) != 0))
8299 * pmap_ts_referenced:
8301 * Return a count of reference bits for a page, clearing those bits.
8302 * It is not necessary for every reference bit to be cleared, but it
8303 * is necessary that 0 only be returned when there are truly no
8304 * reference bits set.
8306 * As an optimization, update the page's dirty field if a modified bit is
8307 * found while counting reference bits. This opportunistic update can be
8308 * performed at low cost and can eliminate the need for some future calls
8309 * to pmap_is_modified(). However, since this function stops after
8310 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
8311 * dirty pages. Those dirty pages will only be detected by a future call
8312 * to pmap_is_modified().
8314 * A DI block is not needed within this function, because
8315 * invalidations are performed before the PV list lock is
8319 pmap_ts_referenced(vm_page_t m)
8321 struct md_page *pvh;
8324 struct rwlock *lock;
8325 pd_entry_t oldpde, *pde;
8326 pt_entry_t *pte, PG_A, PG_M, PG_RW;
8329 int cleared, md_gen, not_cleared, pvh_gen;
8330 struct spglist free;
8333 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8334 ("pmap_ts_referenced: page %p is not managed", m));
8337 pa = VM_PAGE_TO_PHYS(m);
8338 lock = PHYS_TO_PV_LIST_LOCK(pa);
8339 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy : pa_to_pvh(pa);
8343 if ((pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
8344 goto small_mappings;
8350 if (!PMAP_TRYLOCK(pmap)) {
8351 pvh_gen = pvh->pv_gen;
8355 if (pvh_gen != pvh->pv_gen) {
8360 PG_A = pmap_accessed_bit(pmap);
8361 PG_M = pmap_modified_bit(pmap);
8362 PG_RW = pmap_rw_bit(pmap);
8364 pde = pmap_pde(pmap, pv->pv_va);
8366 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8368 * Although "oldpde" is mapping a 2MB page, because
8369 * this function is called at a 4KB page granularity,
8370 * we only update the 4KB page under test.
8374 if ((oldpde & PG_A) != 0) {
8376 * Since this reference bit is shared by 512 4KB
8377 * pages, it should not be cleared every time it is
8378 * tested. Apply a simple "hash" function on the
8379 * physical page number, the virtual superpage number,
8380 * and the pmap address to select one 4KB page out of
8381 * the 512 on which testing the reference bit will
8382 * result in clearing that reference bit. This
8383 * function is designed to avoid the selection of the
8384 * same 4KB page for every 2MB page mapping.
8386 * On demotion, a mapping that hasn't been referenced
8387 * is simply destroyed. To avoid the possibility of a
8388 * subsequent page fault on a demoted wired mapping,
8389 * always leave its reference bit set. Moreover,
8390 * since the superpage is wired, the current state of
8391 * its reference bit won't affect page replacement.
8393 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
8394 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
8395 (oldpde & PG_W) == 0) {
8396 if (safe_to_clear_referenced(pmap, oldpde)) {
8397 atomic_clear_long(pde, PG_A);
8398 pmap_invalidate_page(pmap, pv->pv_va);
8400 } else if (pmap_demote_pde_locked(pmap, pde,
8401 pv->pv_va, &lock)) {
8403 * Remove the mapping to a single page
8404 * so that a subsequent access may
8405 * repromote. Since the underlying
8406 * page table page is fully populated,
8407 * this removal never frees a page
8411 va += VM_PAGE_TO_PHYS(m) - (oldpde &
8413 pte = pmap_pde_to_pte(pde, va);
8414 pmap_remove_pte(pmap, pte, va, *pde,
8416 pmap_invalidate_page(pmap, va);
8422 * The superpage mapping was removed
8423 * entirely and therefore 'pv' is no
8431 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8432 ("inconsistent pv lock %p %p for page %p",
8433 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8438 /* Rotate the PV list if it has more than one entry. */
8439 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8440 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
8441 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
8444 if (cleared + not_cleared >= PMAP_TS_REFERENCED_MAX)
8446 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
8448 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
8455 if (!PMAP_TRYLOCK(pmap)) {
8456 pvh_gen = pvh->pv_gen;
8457 md_gen = m->md.pv_gen;
8461 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8466 PG_A = pmap_accessed_bit(pmap);
8467 PG_M = pmap_modified_bit(pmap);
8468 PG_RW = pmap_rw_bit(pmap);
8469 pde = pmap_pde(pmap, pv->pv_va);
8470 KASSERT((*pde & PG_PS) == 0,
8471 ("pmap_ts_referenced: found a 2mpage in page %p's pv list",
8473 pte = pmap_pde_to_pte(pde, pv->pv_va);
8474 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
8476 if ((*pte & PG_A) != 0) {
8477 if (safe_to_clear_referenced(pmap, *pte)) {
8478 atomic_clear_long(pte, PG_A);
8479 pmap_invalidate_page(pmap, pv->pv_va);
8481 } else if ((*pte & PG_W) == 0) {
8483 * Wired pages cannot be paged out so
8484 * doing accessed bit emulation for
8485 * them is wasted effort. We do the
8486 * hard work for unwired pages only.
8488 pmap_remove_pte(pmap, pte, pv->pv_va,
8489 *pde, &free, &lock);
8490 pmap_invalidate_page(pmap, pv->pv_va);
8495 KASSERT(lock == VM_PAGE_TO_PV_LIST_LOCK(m),
8496 ("inconsistent pv lock %p %p for page %p",
8497 lock, VM_PAGE_TO_PV_LIST_LOCK(m), m));
8502 /* Rotate the PV list if it has more than one entry. */
8503 if (pv != NULL && TAILQ_NEXT(pv, pv_next) != NULL) {
8504 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
8505 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
8508 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && cleared +
8509 not_cleared < PMAP_TS_REFERENCED_MAX);
8512 vm_page_free_pages_toq(&free, true);
8513 return (cleared + not_cleared);
8517 * Apply the given advice to the specified range of addresses within the
8518 * given pmap. Depending on the advice, clear the referenced and/or
8519 * modified flags in each mapping and set the mapped page's dirty field.
8522 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
8524 struct rwlock *lock;
8525 pml4_entry_t *pml4e;
8527 pd_entry_t oldpde, *pde;
8528 pt_entry_t *pte, PG_A, PG_G, PG_M, PG_RW, PG_V;
8529 vm_offset_t va, va_next;
8533 if (advice != MADV_DONTNEED && advice != MADV_FREE)
8537 * A/D bit emulation requires an alternate code path when clearing
8538 * the modified and accessed bits below. Since this function is
8539 * advisory in nature we skip it entirely for pmaps that require
8540 * A/D bit emulation.
8542 if (pmap_emulate_ad_bits(pmap))
8545 PG_A = pmap_accessed_bit(pmap);
8546 PG_G = pmap_global_bit(pmap);
8547 PG_M = pmap_modified_bit(pmap);
8548 PG_V = pmap_valid_bit(pmap);
8549 PG_RW = pmap_rw_bit(pmap);
8551 pmap_delayed_invl_start();
8553 for (; sva < eva; sva = va_next) {
8554 pml4e = pmap_pml4e(pmap, sva);
8555 if (pml4e == NULL || (*pml4e & PG_V) == 0) {
8556 va_next = (sva + NBPML4) & ~PML4MASK;
8562 va_next = (sva + NBPDP) & ~PDPMASK;
8565 pdpe = pmap_pml4e_to_pdpe(pml4e, sva);
8566 if ((*pdpe & PG_V) == 0)
8568 if ((*pdpe & PG_PS) != 0) {
8569 KASSERT(va_next <= eva,
8570 ("partial update of non-transparent 1G mapping "
8571 "pdpe %#lx sva %#lx eva %#lx va_next %#lx",
8572 *pdpe, sva, eva, va_next));
8576 va_next = (sva + NBPDR) & ~PDRMASK;
8579 pde = pmap_pdpe_to_pde(pdpe, sva);
8581 if ((oldpde & PG_V) == 0)
8583 else if ((oldpde & PG_PS) != 0) {
8584 if ((oldpde & PG_MANAGED) == 0)
8587 if (!pmap_demote_pde_locked(pmap, pde, sva, &lock)) {
8592 * The large page mapping was destroyed.
8598 * Unless the page mappings are wired, remove the
8599 * mapping to a single page so that a subsequent
8600 * access may repromote. Choosing the last page
8601 * within the address range [sva, min(va_next, eva))
8602 * generally results in more repromotions. Since the
8603 * underlying page table page is fully populated, this
8604 * removal never frees a page table page.
8606 if ((oldpde & PG_W) == 0) {
8612 ("pmap_advise: no address gap"));
8613 pte = pmap_pde_to_pte(pde, va);
8614 KASSERT((*pte & PG_V) != 0,
8615 ("pmap_advise: invalid PTE"));
8616 pmap_remove_pte(pmap, pte, va, *pde, NULL,
8626 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
8628 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
8630 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8631 if (advice == MADV_DONTNEED) {
8633 * Future calls to pmap_is_modified()
8634 * can be avoided by making the page
8637 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
8640 atomic_clear_long(pte, PG_M | PG_A);
8641 } else if ((*pte & PG_A) != 0)
8642 atomic_clear_long(pte, PG_A);
8646 if ((*pte & PG_G) != 0) {
8653 if (va != va_next) {
8654 pmap_invalidate_range(pmap, va, sva);
8659 pmap_invalidate_range(pmap, va, sva);
8662 pmap_invalidate_all(pmap);
8664 pmap_delayed_invl_finish();
8668 * Clear the modify bits on the specified physical page.
8671 pmap_clear_modify(vm_page_t m)
8673 struct md_page *pvh;
8675 pv_entry_t next_pv, pv;
8676 pd_entry_t oldpde, *pde;
8677 pt_entry_t *pte, PG_M, PG_RW;
8678 struct rwlock *lock;
8680 int md_gen, pvh_gen;
8682 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
8683 ("pmap_clear_modify: page %p is not managed", m));
8684 vm_page_assert_busied(m);
8686 if (!pmap_page_is_write_mapped(m))
8688 pvh = (m->flags & PG_FICTITIOUS) != 0 ? &pv_dummy :
8689 pa_to_pvh(VM_PAGE_TO_PHYS(m));
8690 lock = VM_PAGE_TO_PV_LIST_LOCK(m);
8693 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
8695 if (!PMAP_TRYLOCK(pmap)) {
8696 pvh_gen = pvh->pv_gen;
8700 if (pvh_gen != pvh->pv_gen) {
8705 PG_M = pmap_modified_bit(pmap);
8706 PG_RW = pmap_rw_bit(pmap);
8708 pde = pmap_pde(pmap, va);
8710 /* If oldpde has PG_RW set, then it also has PG_M set. */
8711 if ((oldpde & PG_RW) != 0 &&
8712 pmap_demote_pde_locked(pmap, pde, va, &lock) &&
8713 (oldpde & PG_W) == 0) {
8715 * Write protect the mapping to a single page so that
8716 * a subsequent write access may repromote.
8718 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
8719 pte = pmap_pde_to_pte(pde, va);
8720 atomic_clear_long(pte, PG_M | PG_RW);
8722 pmap_invalidate_page(pmap, va);
8726 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
8728 if (!PMAP_TRYLOCK(pmap)) {
8729 md_gen = m->md.pv_gen;
8730 pvh_gen = pvh->pv_gen;
8734 if (pvh_gen != pvh->pv_gen || md_gen != m->md.pv_gen) {
8739 PG_M = pmap_modified_bit(pmap);
8740 PG_RW = pmap_rw_bit(pmap);
8741 pde = pmap_pde(pmap, pv->pv_va);
8742 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
8743 " a 2mpage in page %p's pv list", m));
8744 pte = pmap_pde_to_pte(pde, pv->pv_va);
8745 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
8746 atomic_clear_long(pte, PG_M);
8747 pmap_invalidate_page(pmap, pv->pv_va);
8755 * Miscellaneous support routines follow
8758 /* Adjust the properties for a leaf page table entry. */
8759 static __inline void
8760 pmap_pte_props(pt_entry_t *pte, u_long bits, u_long mask)
8764 opte = *(u_long *)pte;
8766 npte = opte & ~mask;
8768 } while (npte != opte && !atomic_fcmpset_long((u_long *)pte, &opte,
8773 * Map a set of physical memory pages into the kernel virtual
8774 * address space. Return a pointer to where it is mapped. This
8775 * routine is intended to be used for mapping device memory,
8779 pmap_mapdev_internal(vm_paddr_t pa, vm_size_t size, int mode, int flags)
8781 struct pmap_preinit_mapping *ppim;
8782 vm_offset_t va, offset;
8786 offset = pa & PAGE_MASK;
8787 size = round_page(offset + size);
8788 pa = trunc_page(pa);
8790 if (!pmap_initialized) {
8792 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8793 ppim = pmap_preinit_mapping + i;
8794 if (ppim->va == 0) {
8798 ppim->va = virtual_avail;
8799 virtual_avail += size;
8805 panic("%s: too many preinit mappings", __func__);
8808 * If we have a preinit mapping, re-use it.
8810 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8811 ppim = pmap_preinit_mapping + i;
8812 if (ppim->pa == pa && ppim->sz == size &&
8813 (ppim->mode == mode ||
8814 (flags & MAPDEV_SETATTR) == 0))
8815 return ((void *)(ppim->va + offset));
8818 * If the specified range of physical addresses fits within
8819 * the direct map window, use the direct map.
8821 if (pa < dmaplimit && pa + size <= dmaplimit) {
8822 va = PHYS_TO_DMAP(pa);
8823 if ((flags & MAPDEV_SETATTR) != 0) {
8824 PMAP_LOCK(kernel_pmap);
8825 i = pmap_change_props_locked(va, size,
8826 PROT_NONE, mode, flags);
8827 PMAP_UNLOCK(kernel_pmap);
8831 return ((void *)(va + offset));
8833 va = kva_alloc(size);
8835 panic("%s: Couldn't allocate KVA", __func__);
8837 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
8838 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
8839 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
8840 if ((flags & MAPDEV_FLUSHCACHE) != 0)
8841 pmap_invalidate_cache_range(va, va + tmpsize);
8842 return ((void *)(va + offset));
8846 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
8849 return (pmap_mapdev_internal(pa, size, mode, MAPDEV_FLUSHCACHE |
8854 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
8857 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
8861 pmap_mapdev_pciecfg(vm_paddr_t pa, vm_size_t size)
8864 return (pmap_mapdev_internal(pa, size, PAT_UNCACHEABLE,
8869 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
8872 return (pmap_mapdev_internal(pa, size, PAT_WRITE_BACK,
8873 MAPDEV_FLUSHCACHE));
8877 pmap_unmapdev(vm_offset_t va, vm_size_t size)
8879 struct pmap_preinit_mapping *ppim;
8883 /* If we gave a direct map region in pmap_mapdev, do nothing */
8884 if (va >= DMAP_MIN_ADDRESS && va < DMAP_MAX_ADDRESS)
8886 offset = va & PAGE_MASK;
8887 size = round_page(offset + size);
8888 va = trunc_page(va);
8889 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
8890 ppim = pmap_preinit_mapping + i;
8891 if (ppim->va == va && ppim->sz == size) {
8892 if (pmap_initialized)
8898 if (va + size == virtual_avail)
8903 if (pmap_initialized) {
8904 pmap_qremove(va, atop(size));
8910 * Tries to demote a 1GB page mapping.
8913 pmap_demote_pdpe(pmap_t pmap, pdp_entry_t *pdpe, vm_offset_t va)
8915 pdp_entry_t newpdpe, oldpdpe;
8916 pd_entry_t *firstpde, newpde, *pde;
8917 pt_entry_t PG_A, PG_M, PG_RW, PG_V;
8921 PG_A = pmap_accessed_bit(pmap);
8922 PG_M = pmap_modified_bit(pmap);
8923 PG_V = pmap_valid_bit(pmap);
8924 PG_RW = pmap_rw_bit(pmap);
8926 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
8928 KASSERT((oldpdpe & (PG_PS | PG_V)) == (PG_PS | PG_V),
8929 ("pmap_demote_pdpe: oldpdpe is missing PG_PS and/or PG_V"));
8930 if ((pdpg = vm_page_alloc(NULL, va >> PDPSHIFT, VM_ALLOC_INTERRUPT |
8931 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
8932 CTR2(KTR_PMAP, "pmap_demote_pdpe: failure for va %#lx"
8933 " in pmap %p", va, pmap);
8936 pdpgpa = VM_PAGE_TO_PHYS(pdpg);
8937 firstpde = (pd_entry_t *)PHYS_TO_DMAP(pdpgpa);
8938 newpdpe = pdpgpa | PG_M | PG_A | (oldpdpe & PG_U) | PG_RW | PG_V;
8939 KASSERT((oldpdpe & PG_A) != 0,
8940 ("pmap_demote_pdpe: oldpdpe is missing PG_A"));
8941 KASSERT((oldpdpe & (PG_M | PG_RW)) != PG_RW,
8942 ("pmap_demote_pdpe: oldpdpe is missing PG_M"));
8946 * Initialize the page directory page.
8948 for (pde = firstpde; pde < firstpde + NPDEPG; pde++) {
8954 * Demote the mapping.
8959 * Invalidate a stale recursive mapping of the page directory page.
8961 pmap_invalidate_page(pmap, (vm_offset_t)vtopde(va));
8963 pmap_pdpe_demotions++;
8964 CTR2(KTR_PMAP, "pmap_demote_pdpe: success for va %#lx"
8965 " in pmap %p", va, pmap);
8970 * Sets the memory attribute for the specified page.
8973 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
8976 m->md.pat_mode = ma;
8979 * If "m" is a normal page, update its direct mapping. This update
8980 * can be relied upon to perform any cache operations that are
8981 * required for data coherence.
8983 if ((m->flags & PG_FICTITIOUS) == 0 &&
8984 pmap_change_attr(PHYS_TO_DMAP(VM_PAGE_TO_PHYS(m)), PAGE_SIZE,
8986 panic("memory attribute change on the direct map failed");
8990 * Changes the specified virtual address range's memory type to that given by
8991 * the parameter "mode". The specified virtual address range must be
8992 * completely contained within either the direct map or the kernel map. If
8993 * the virtual address range is contained within the kernel map, then the
8994 * memory type for each of the corresponding ranges of the direct map is also
8995 * changed. (The corresponding ranges of the direct map are those ranges that
8996 * map the same physical pages as the specified virtual address range.) These
8997 * changes to the direct map are necessary because Intel describes the
8998 * behavior of their processors as "undefined" if two or more mappings to the
8999 * same physical page have different memory types.
9001 * Returns zero if the change completed successfully, and either EINVAL or
9002 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
9003 * of the virtual address range was not mapped, and ENOMEM is returned if
9004 * there was insufficient memory available to complete the change. In the
9005 * latter case, the memory type may have been changed on some part of the
9006 * virtual address range or the direct map.
9009 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
9013 PMAP_LOCK(kernel_pmap);
9014 error = pmap_change_props_locked(va, size, PROT_NONE, mode,
9016 PMAP_UNLOCK(kernel_pmap);
9021 * Changes the specified virtual address range's protections to those
9022 * specified by "prot". Like pmap_change_attr(), protections for aliases
9023 * in the direct map are updated as well. Protections on aliasing mappings may
9024 * be a subset of the requested protections; for example, mappings in the direct
9025 * map are never executable.
9028 pmap_change_prot(vm_offset_t va, vm_size_t size, vm_prot_t prot)
9032 /* Only supported within the kernel map. */
9033 if (va < VM_MIN_KERNEL_ADDRESS)
9036 PMAP_LOCK(kernel_pmap);
9037 error = pmap_change_props_locked(va, size, prot, -1,
9038 MAPDEV_ASSERTVALID);
9039 PMAP_UNLOCK(kernel_pmap);
9044 pmap_change_props_locked(vm_offset_t va, vm_size_t size, vm_prot_t prot,
9045 int mode, int flags)
9047 vm_offset_t base, offset, tmpva;
9048 vm_paddr_t pa_start, pa_end, pa_end1;
9050 pd_entry_t *pde, pde_bits, pde_mask;
9051 pt_entry_t *pte, pte_bits, pte_mask;
9055 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9056 base = trunc_page(va);
9057 offset = va & PAGE_MASK;
9058 size = round_page(offset + size);
9061 * Only supported on kernel virtual addresses, including the direct
9062 * map but excluding the recursive map.
9064 if (base < DMAP_MIN_ADDRESS)
9068 * Construct our flag sets and masks. "bits" is the subset of
9069 * "mask" that will be set in each modified PTE.
9071 * Mappings in the direct map are never allowed to be executable.
9073 pde_bits = pte_bits = 0;
9074 pde_mask = pte_mask = 0;
9076 pde_bits |= pmap_cache_bits(kernel_pmap, mode, true);
9077 pde_mask |= X86_PG_PDE_CACHE;
9078 pte_bits |= pmap_cache_bits(kernel_pmap, mode, false);
9079 pte_mask |= X86_PG_PTE_CACHE;
9081 if (prot != VM_PROT_NONE) {
9082 if ((prot & VM_PROT_WRITE) != 0) {
9083 pde_bits |= X86_PG_RW;
9084 pte_bits |= X86_PG_RW;
9086 if ((prot & VM_PROT_EXECUTE) == 0 ||
9087 va < VM_MIN_KERNEL_ADDRESS) {
9091 pde_mask |= X86_PG_RW | pg_nx;
9092 pte_mask |= X86_PG_RW | pg_nx;
9096 * Pages that aren't mapped aren't supported. Also break down 2MB pages
9097 * into 4KB pages if required.
9099 for (tmpva = base; tmpva < base + size; ) {
9100 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9101 if (pdpe == NULL || *pdpe == 0) {
9102 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9103 ("%s: addr %#lx is not mapped", __func__, tmpva));
9106 if (*pdpe & PG_PS) {
9108 * If the current 1GB page already has the required
9109 * properties, then we need not demote this page. Just
9110 * increment tmpva to the next 1GB page frame.
9112 if ((*pdpe & pde_mask) == pde_bits) {
9113 tmpva = trunc_1gpage(tmpva) + NBPDP;
9118 * If the current offset aligns with a 1GB page frame
9119 * and there is at least 1GB left within the range, then
9120 * we need not break down this page into 2MB pages.
9122 if ((tmpva & PDPMASK) == 0 &&
9123 tmpva + PDPMASK < base + size) {
9127 if (!pmap_demote_pdpe(kernel_pmap, pdpe, tmpva))
9130 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9132 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9133 ("%s: addr %#lx is not mapped", __func__, tmpva));
9138 * If the current 2MB page already has the required
9139 * properties, then we need not demote this page. Just
9140 * increment tmpva to the next 2MB page frame.
9142 if ((*pde & pde_mask) == pde_bits) {
9143 tmpva = trunc_2mpage(tmpva) + NBPDR;
9148 * If the current offset aligns with a 2MB page frame
9149 * and there is at least 2MB left within the range, then
9150 * we need not break down this page into 4KB pages.
9152 if ((tmpva & PDRMASK) == 0 &&
9153 tmpva + PDRMASK < base + size) {
9157 if (!pmap_demote_pde(kernel_pmap, pde, tmpva))
9160 pte = pmap_pde_to_pte(pde, tmpva);
9162 KASSERT((flags & MAPDEV_ASSERTVALID) == 0,
9163 ("%s: addr %#lx is not mapped", __func__, tmpva));
9171 * Ok, all the pages exist, so run through them updating their
9172 * properties if required.
9175 pa_start = pa_end = 0;
9176 for (tmpva = base; tmpva < base + size; ) {
9177 pdpe = pmap_pdpe(kernel_pmap, tmpva);
9178 if (*pdpe & PG_PS) {
9179 if ((*pdpe & pde_mask) != pde_bits) {
9180 pmap_pte_props(pdpe, pde_bits, pde_mask);
9183 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9184 (*pdpe & PG_PS_FRAME) < dmaplimit) {
9185 if (pa_start == pa_end) {
9186 /* Start physical address run. */
9187 pa_start = *pdpe & PG_PS_FRAME;
9188 pa_end = pa_start + NBPDP;
9189 } else if (pa_end == (*pdpe & PG_PS_FRAME))
9192 /* Run ended, update direct map. */
9193 error = pmap_change_props_locked(
9194 PHYS_TO_DMAP(pa_start),
9195 pa_end - pa_start, prot, mode,
9199 /* Start physical address run. */
9200 pa_start = *pdpe & PG_PS_FRAME;
9201 pa_end = pa_start + NBPDP;
9204 tmpva = trunc_1gpage(tmpva) + NBPDP;
9207 pde = pmap_pdpe_to_pde(pdpe, tmpva);
9209 if ((*pde & pde_mask) != pde_bits) {
9210 pmap_pte_props(pde, pde_bits, pde_mask);
9213 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9214 (*pde & PG_PS_FRAME) < dmaplimit) {
9215 if (pa_start == pa_end) {
9216 /* Start physical address run. */
9217 pa_start = *pde & PG_PS_FRAME;
9218 pa_end = pa_start + NBPDR;
9219 } else if (pa_end == (*pde & PG_PS_FRAME))
9222 /* Run ended, update direct map. */
9223 error = pmap_change_props_locked(
9224 PHYS_TO_DMAP(pa_start),
9225 pa_end - pa_start, prot, mode,
9229 /* Start physical address run. */
9230 pa_start = *pde & PG_PS_FRAME;
9231 pa_end = pa_start + NBPDR;
9234 tmpva = trunc_2mpage(tmpva) + NBPDR;
9236 pte = pmap_pde_to_pte(pde, tmpva);
9237 if ((*pte & pte_mask) != pte_bits) {
9238 pmap_pte_props(pte, pte_bits, pte_mask);
9241 if (tmpva >= VM_MIN_KERNEL_ADDRESS &&
9242 (*pte & PG_FRAME) < dmaplimit) {
9243 if (pa_start == pa_end) {
9244 /* Start physical address run. */
9245 pa_start = *pte & PG_FRAME;
9246 pa_end = pa_start + PAGE_SIZE;
9247 } else if (pa_end == (*pte & PG_FRAME))
9248 pa_end += PAGE_SIZE;
9250 /* Run ended, update direct map. */
9251 error = pmap_change_props_locked(
9252 PHYS_TO_DMAP(pa_start),
9253 pa_end - pa_start, prot, mode,
9257 /* Start physical address run. */
9258 pa_start = *pte & PG_FRAME;
9259 pa_end = pa_start + PAGE_SIZE;
9265 if (error == 0 && pa_start != pa_end && pa_start < dmaplimit) {
9266 pa_end1 = MIN(pa_end, dmaplimit);
9267 if (pa_start != pa_end1)
9268 error = pmap_change_props_locked(PHYS_TO_DMAP(pa_start),
9269 pa_end1 - pa_start, prot, mode, flags);
9273 * Flush CPU caches if required to make sure any data isn't cached that
9274 * shouldn't be, etc.
9277 pmap_invalidate_range(kernel_pmap, base, tmpva);
9278 if ((flags & MAPDEV_FLUSHCACHE) != 0)
9279 pmap_invalidate_cache_range(base, tmpva);
9285 * Demotes any mapping within the direct map region that covers more than the
9286 * specified range of physical addresses. This range's size must be a power
9287 * of two and its starting address must be a multiple of its size. Since the
9288 * demotion does not change any attributes of the mapping, a TLB invalidation
9289 * is not mandatory. The caller may, however, request a TLB invalidation.
9292 pmap_demote_DMAP(vm_paddr_t base, vm_size_t len, boolean_t invalidate)
9301 KASSERT(powerof2(len), ("pmap_demote_DMAP: len is not a power of 2"));
9302 KASSERT((base & (len - 1)) == 0,
9303 ("pmap_demote_DMAP: base is not a multiple of len"));
9304 if (len < NBPDP && base < dmaplimit) {
9305 va = PHYS_TO_DMAP(base);
9307 PMAP_LOCK(kernel_pmap);
9308 pdpe = pmap_pdpe(kernel_pmap, va);
9309 if ((*pdpe & X86_PG_V) == 0)
9310 panic("pmap_demote_DMAP: invalid PDPE");
9311 if ((*pdpe & PG_PS) != 0) {
9312 if (!pmap_demote_pdpe(kernel_pmap, pdpe, va))
9313 panic("pmap_demote_DMAP: PDPE failed");
9317 pde = pmap_pdpe_to_pde(pdpe, va);
9318 if ((*pde & X86_PG_V) == 0)
9319 panic("pmap_demote_DMAP: invalid PDE");
9320 if ((*pde & PG_PS) != 0) {
9321 if (!pmap_demote_pde(kernel_pmap, pde, va))
9322 panic("pmap_demote_DMAP: PDE failed");
9326 if (changed && invalidate)
9327 pmap_invalidate_page(kernel_pmap, va);
9328 PMAP_UNLOCK(kernel_pmap);
9333 * Perform the pmap work for mincore(2). If the page is not both referenced and
9334 * modified by this pmap, returns its physical address so that the caller can
9335 * find other mappings.
9338 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
9342 pt_entry_t pte, PG_A, PG_M, PG_RW, PG_V;
9346 PG_A = pmap_accessed_bit(pmap);
9347 PG_M = pmap_modified_bit(pmap);
9348 PG_V = pmap_valid_bit(pmap);
9349 PG_RW = pmap_rw_bit(pmap);
9355 pdpe = pmap_pdpe(pmap, addr);
9356 if ((*pdpe & PG_V) != 0) {
9357 if ((*pdpe & PG_PS) != 0) {
9359 pa = ((pte & PG_PS_PDP_FRAME) | (addr & PDPMASK)) &
9361 val = MINCORE_PSIND(2);
9363 pdep = pmap_pde(pmap, addr);
9364 if (pdep != NULL && (*pdep & PG_V) != 0) {
9365 if ((*pdep & PG_PS) != 0) {
9367 /* Compute the physical address of the 4KB page. */
9368 pa = ((pte & PG_PS_FRAME) | (addr &
9369 PDRMASK)) & PG_FRAME;
9370 val = MINCORE_PSIND(1);
9372 pte = *pmap_pde_to_pte(pdep, addr);
9373 pa = pte & PG_FRAME;
9379 if ((pte & PG_V) != 0) {
9380 val |= MINCORE_INCORE;
9381 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
9382 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
9383 if ((pte & PG_A) != 0)
9384 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
9386 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
9387 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
9388 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
9396 pmap_pcid_alloc(pmap_t pmap, u_int cpuid)
9398 uint32_t gen, new_gen, pcid_next;
9400 CRITICAL_ASSERT(curthread);
9401 gen = PCPU_GET(pcid_gen);
9402 if (pmap->pm_pcids[cpuid].pm_pcid == PMAP_PCID_KERN)
9403 return (pti ? 0 : CR3_PCID_SAVE);
9404 if (pmap->pm_pcids[cpuid].pm_gen == gen)
9405 return (CR3_PCID_SAVE);
9406 pcid_next = PCPU_GET(pcid_next);
9407 KASSERT((!pti && pcid_next <= PMAP_PCID_OVERMAX) ||
9408 (pti && pcid_next <= PMAP_PCID_OVERMAX_KERN),
9409 ("cpu %d pcid_next %#x", cpuid, pcid_next));
9410 if ((!pti && pcid_next == PMAP_PCID_OVERMAX) ||
9411 (pti && pcid_next == PMAP_PCID_OVERMAX_KERN)) {
9415 PCPU_SET(pcid_gen, new_gen);
9416 pcid_next = PMAP_PCID_KERN + 1;
9420 pmap->pm_pcids[cpuid].pm_pcid = pcid_next;
9421 pmap->pm_pcids[cpuid].pm_gen = new_gen;
9422 PCPU_SET(pcid_next, pcid_next + 1);
9427 pmap_pcid_alloc_checked(pmap_t pmap, u_int cpuid)
9431 cached = pmap_pcid_alloc(pmap, cpuid);
9432 KASSERT(pmap->pm_pcids[cpuid].pm_pcid < PMAP_PCID_OVERMAX,
9433 ("pmap %p cpu %d pcid %#x", pmap, cpuid,
9434 pmap->pm_pcids[cpuid].pm_pcid));
9435 KASSERT(pmap->pm_pcids[cpuid].pm_pcid != PMAP_PCID_KERN ||
9436 pmap == kernel_pmap,
9437 ("non-kernel pmap pmap %p cpu %d pcid %#x",
9438 pmap, cpuid, pmap->pm_pcids[cpuid].pm_pcid));
9443 pmap_activate_sw_pti_post(struct thread *td, pmap_t pmap)
9446 PCPU_GET(tssp)->tss_rsp0 = pmap->pm_ucr3 != PMAP_NO_CR3 ?
9447 PCPU_GET(pti_rsp0) : (uintptr_t)td->td_md.md_stack_base;
9451 pmap_activate_sw_pcid_pti(struct thread *td, pmap_t pmap, u_int cpuid)
9454 uint64_t cached, cr3, kcr3, ucr3;
9456 KASSERT((read_rflags() & PSL_I) == 0,
9457 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9459 /* See the comment in pmap_invalidate_page_pcid(). */
9460 if (PCPU_GET(ucr3_load_mask) != PMAP_UCR3_NOMASK) {
9461 PCPU_SET(ucr3_load_mask, PMAP_UCR3_NOMASK);
9462 old_pmap = PCPU_GET(curpmap);
9463 MPASS(old_pmap->pm_ucr3 != PMAP_NO_CR3);
9464 old_pmap->pm_pcids[cpuid].pm_gen = 0;
9467 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9469 if ((cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9470 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid);
9471 PCPU_SET(curpmap, pmap);
9472 kcr3 = pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid;
9473 ucr3 = pmap->pm_ucr3 | pmap->pm_pcids[cpuid].pm_pcid |
9476 if (!cached && pmap->pm_ucr3 != PMAP_NO_CR3)
9477 PCPU_SET(ucr3_load_mask, ~CR3_PCID_SAVE);
9479 PCPU_SET(kcr3, kcr3 | CR3_PCID_SAVE);
9480 PCPU_SET(ucr3, ucr3 | CR3_PCID_SAVE);
9482 PCPU_INC(pm_save_cnt);
9484 pmap_activate_sw_pti_post(td, pmap);
9488 pmap_activate_sw_pcid_nopti(struct thread *td __unused, pmap_t pmap,
9491 uint64_t cached, cr3;
9493 KASSERT((read_rflags() & PSL_I) == 0,
9494 ("PCID needs interrupts disabled in pmap_activate_sw()"));
9496 cached = pmap_pcid_alloc_checked(pmap, cpuid);
9498 if (!cached || (cr3 & ~CR3_PCID_MASK) != pmap->pm_cr3)
9499 load_cr3(pmap->pm_cr3 | pmap->pm_pcids[cpuid].pm_pcid |
9501 PCPU_SET(curpmap, pmap);
9503 PCPU_INC(pm_save_cnt);
9507 pmap_activate_sw_nopcid_nopti(struct thread *td __unused, pmap_t pmap,
9508 u_int cpuid __unused)
9511 load_cr3(pmap->pm_cr3);
9512 PCPU_SET(curpmap, pmap);
9516 pmap_activate_sw_nopcid_pti(struct thread *td, pmap_t pmap,
9517 u_int cpuid __unused)
9520 pmap_activate_sw_nopcid_nopti(td, pmap, cpuid);
9521 PCPU_SET(kcr3, pmap->pm_cr3);
9522 PCPU_SET(ucr3, pmap->pm_ucr3);
9523 pmap_activate_sw_pti_post(td, pmap);
9526 DEFINE_IFUNC(static, void, pmap_activate_sw_mode, (struct thread *, pmap_t,
9530 if (pmap_pcid_enabled && pti)
9531 return (pmap_activate_sw_pcid_pti);
9532 else if (pmap_pcid_enabled && !pti)
9533 return (pmap_activate_sw_pcid_nopti);
9534 else if (!pmap_pcid_enabled && pti)
9535 return (pmap_activate_sw_nopcid_pti);
9536 else /* if (!pmap_pcid_enabled && !pti) */
9537 return (pmap_activate_sw_nopcid_nopti);
9541 pmap_activate_sw(struct thread *td)
9543 pmap_t oldpmap, pmap;
9546 oldpmap = PCPU_GET(curpmap);
9547 pmap = vmspace_pmap(td->td_proc->p_vmspace);
9548 if (oldpmap == pmap) {
9549 if (cpu_vendor_id != CPU_VENDOR_INTEL)
9553 cpuid = PCPU_GET(cpuid);
9555 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9557 CPU_SET(cpuid, &pmap->pm_active);
9559 pmap_activate_sw_mode(td, pmap, cpuid);
9561 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
9563 CPU_CLR(cpuid, &oldpmap->pm_active);
9568 pmap_activate(struct thread *td)
9571 * invltlb_{invpcid,}_pcid_handler() is used to handle an
9572 * invalidate_all IPI, which checks for curpmap ==
9573 * smp_tlb_pmap. The below sequence of operations has a
9574 * window where %CR3 is loaded with the new pmap's PML4
9575 * address, but the curpmap value has not yet been updated.
9576 * This causes the invltlb IPI handler, which is called
9577 * between the updates, to execute as a NOP, which leaves
9578 * stale TLB entries.
9580 * Note that the most common use of pmap_activate_sw(), from
9581 * a context switch, is immune to this race, because
9582 * interrupts are disabled (while the thread lock is owned),
9583 * so the IPI is delayed until after curpmap is updated. Protect
9584 * other callers in a similar way, by disabling interrupts
9585 * around the %cr3 register reload and curpmap assignment.
9588 pmap_activate_sw(td);
9593 pmap_activate_boot(pmap_t pmap)
9599 * kernel_pmap must be never deactivated, and we ensure that
9600 * by never activating it at all.
9602 MPASS(pmap != kernel_pmap);
9604 cpuid = PCPU_GET(cpuid);
9606 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
9608 CPU_SET(cpuid, &pmap->pm_active);
9610 PCPU_SET(curpmap, pmap);
9612 kcr3 = pmap->pm_cr3;
9613 if (pmap_pcid_enabled)
9614 kcr3 |= pmap->pm_pcids[cpuid].pm_pcid | CR3_PCID_SAVE;
9618 PCPU_SET(kcr3, kcr3);
9619 PCPU_SET(ucr3, PMAP_NO_CR3);
9623 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
9628 * Increase the starting virtual address of the given mapping if a
9629 * different alignment might result in more superpage mappings.
9632 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
9633 vm_offset_t *addr, vm_size_t size)
9635 vm_offset_t superpage_offset;
9639 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
9640 offset += ptoa(object->pg_color);
9641 superpage_offset = offset & PDRMASK;
9642 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
9643 (*addr & PDRMASK) == superpage_offset)
9645 if ((*addr & PDRMASK) < superpage_offset)
9646 *addr = (*addr & ~PDRMASK) + superpage_offset;
9648 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
9652 static unsigned long num_dirty_emulations;
9653 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_dirty_emulations, CTLFLAG_RW,
9654 &num_dirty_emulations, 0, NULL);
9656 static unsigned long num_accessed_emulations;
9657 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_accessed_emulations, CTLFLAG_RW,
9658 &num_accessed_emulations, 0, NULL);
9660 static unsigned long num_superpage_accessed_emulations;
9661 SYSCTL_ULONG(_vm_pmap, OID_AUTO, num_superpage_accessed_emulations, CTLFLAG_RW,
9662 &num_superpage_accessed_emulations, 0, NULL);
9664 static unsigned long ad_emulation_superpage_promotions;
9665 SYSCTL_ULONG(_vm_pmap, OID_AUTO, ad_emulation_superpage_promotions, CTLFLAG_RW,
9666 &ad_emulation_superpage_promotions, 0, NULL);
9667 #endif /* INVARIANTS */
9670 pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype)
9673 struct rwlock *lock;
9674 #if VM_NRESERVLEVEL > 0
9678 pt_entry_t *pte, PG_A, PG_M, PG_RW, PG_V;
9680 KASSERT(ftype == VM_PROT_READ || ftype == VM_PROT_WRITE,
9681 ("pmap_emulate_accessed_dirty: invalid fault type %d", ftype));
9683 if (!pmap_emulate_ad_bits(pmap))
9686 PG_A = pmap_accessed_bit(pmap);
9687 PG_M = pmap_modified_bit(pmap);
9688 PG_V = pmap_valid_bit(pmap);
9689 PG_RW = pmap_rw_bit(pmap);
9695 pde = pmap_pde(pmap, va);
9696 if (pde == NULL || (*pde & PG_V) == 0)
9699 if ((*pde & PG_PS) != 0) {
9700 if (ftype == VM_PROT_READ) {
9702 atomic_add_long(&num_superpage_accessed_emulations, 1);
9710 pte = pmap_pde_to_pte(pde, va);
9711 if ((*pte & PG_V) == 0)
9714 if (ftype == VM_PROT_WRITE) {
9715 if ((*pte & PG_RW) == 0)
9718 * Set the modified and accessed bits simultaneously.
9720 * Intel EPT PTEs that do software emulation of A/D bits map
9721 * PG_A and PG_M to EPT_PG_READ and EPT_PG_WRITE respectively.
9722 * An EPT misconfiguration is triggered if the PTE is writable
9723 * but not readable (WR=10). This is avoided by setting PG_A
9724 * and PG_M simultaneously.
9726 *pte |= PG_M | PG_A;
9731 #if VM_NRESERVLEVEL > 0
9732 /* try to promote the mapping */
9733 if (va < VM_MAXUSER_ADDRESS)
9734 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
9738 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
9740 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
9741 pmap_ps_enabled(pmap) &&
9742 (m->flags & PG_FICTITIOUS) == 0 &&
9743 vm_reserv_level_iffullpop(m) == 0) {
9744 pmap_promote_pde(pmap, pde, va, &lock);
9746 atomic_add_long(&ad_emulation_superpage_promotions, 1);
9752 if (ftype == VM_PROT_WRITE)
9753 atomic_add_long(&num_dirty_emulations, 1);
9755 atomic_add_long(&num_accessed_emulations, 1);
9757 rv = 0; /* success */
9766 pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num)
9771 pt_entry_t *pte, PG_V;
9775 PG_V = pmap_valid_bit(pmap);
9778 pml4 = pmap_pml4e(pmap, va);
9782 if ((*pml4 & PG_V) == 0)
9785 pdp = pmap_pml4e_to_pdpe(pml4, va);
9787 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0)
9790 pde = pmap_pdpe_to_pde(pdp, va);
9792 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0)
9795 pte = pmap_pde_to_pte(pde, va);
9804 * Get the kernel virtual address of a set of physical pages. If there are
9805 * physical addresses not covered by the DMAP perform a transient mapping
9806 * that will be removed when calling pmap_unmap_io_transient.
9808 * \param page The pages the caller wishes to obtain the virtual
9809 * address on the kernel memory map.
9810 * \param vaddr On return contains the kernel virtual memory address
9811 * of the pages passed in the page parameter.
9812 * \param count Number of pages passed in.
9813 * \param can_fault TRUE if the thread using the mapped pages can take
9814 * page faults, FALSE otherwise.
9816 * \returns TRUE if the caller must call pmap_unmap_io_transient when
9817 * finished or FALSE otherwise.
9821 pmap_map_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9822 boolean_t can_fault)
9825 boolean_t needs_mapping;
9827 int cache_bits, error __unused, i;
9830 * Allocate any KVA space that we need, this is done in a separate
9831 * loop to prevent calling vmem_alloc while pinned.
9833 needs_mapping = FALSE;
9834 for (i = 0; i < count; i++) {
9835 paddr = VM_PAGE_TO_PHYS(page[i]);
9836 if (__predict_false(paddr >= dmaplimit)) {
9837 error = vmem_alloc(kernel_arena, PAGE_SIZE,
9838 M_BESTFIT | M_WAITOK, &vaddr[i]);
9839 KASSERT(error == 0, ("vmem_alloc failed: %d", error));
9840 needs_mapping = TRUE;
9842 vaddr[i] = PHYS_TO_DMAP(paddr);
9846 /* Exit early if everything is covered by the DMAP */
9851 * NB: The sequence of updating a page table followed by accesses
9852 * to the corresponding pages used in the !DMAP case is subject to
9853 * the situation described in the "AMD64 Architecture Programmer's
9854 * Manual Volume 2: System Programming" rev. 3.23, "7.3.1 Special
9855 * Coherency Considerations". Therefore, issuing the INVLPG right
9856 * after modifying the PTE bits is crucial.
9860 for (i = 0; i < count; i++) {
9861 paddr = VM_PAGE_TO_PHYS(page[i]);
9862 if (paddr >= dmaplimit) {
9865 * Slow path, since we can get page faults
9866 * while mappings are active don't pin the
9867 * thread to the CPU and instead add a global
9868 * mapping visible to all CPUs.
9870 pmap_qenter(vaddr[i], &page[i], 1);
9872 pte = vtopte(vaddr[i]);
9873 cache_bits = pmap_cache_bits(kernel_pmap,
9874 page[i]->md.pat_mode, 0);
9875 pte_store(pte, paddr | X86_PG_RW | X86_PG_V |
9882 return (needs_mapping);
9886 pmap_unmap_io_transient(vm_page_t page[], vm_offset_t vaddr[], int count,
9887 boolean_t can_fault)
9894 for (i = 0; i < count; i++) {
9895 paddr = VM_PAGE_TO_PHYS(page[i]);
9896 if (paddr >= dmaplimit) {
9898 pmap_qremove(vaddr[i], 1);
9899 vmem_free(kernel_arena, vaddr[i], PAGE_SIZE);
9905 pmap_quick_enter_page(vm_page_t m)
9909 paddr = VM_PAGE_TO_PHYS(m);
9910 if (paddr < dmaplimit)
9911 return (PHYS_TO_DMAP(paddr));
9912 mtx_lock_spin(&qframe_mtx);
9913 KASSERT(*vtopte(qframe) == 0, ("qframe busy"));
9914 pte_store(vtopte(qframe), paddr | X86_PG_RW | X86_PG_V | X86_PG_A |
9915 X86_PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode, 0));
9920 pmap_quick_remove_page(vm_offset_t addr)
9925 pte_store(vtopte(qframe), 0);
9927 mtx_unlock_spin(&qframe_mtx);
9931 * Pdp pages from the large map are managed differently from either
9932 * kernel or user page table pages. They are permanently allocated at
9933 * initialization time, and their reference count is permanently set to
9934 * zero. The pml4 entries pointing to those pages are copied into
9935 * each allocated pmap.
9937 * In contrast, pd and pt pages are managed like user page table
9938 * pages. They are dynamically allocated, and their reference count
9939 * represents the number of valid entries within the page.
9942 pmap_large_map_getptp_unlocked(void)
9946 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
9948 if (m != NULL && (m->flags & PG_ZERO) == 0)
9954 pmap_large_map_getptp(void)
9958 PMAP_LOCK_ASSERT(kernel_pmap, MA_OWNED);
9959 m = pmap_large_map_getptp_unlocked();
9961 PMAP_UNLOCK(kernel_pmap);
9963 PMAP_LOCK(kernel_pmap);
9964 /* Callers retry. */
9969 static pdp_entry_t *
9970 pmap_large_map_pdpe(vm_offset_t va)
9972 vm_pindex_t pml4_idx;
9975 pml4_idx = pmap_pml4e_index(va);
9976 KASSERT(LMSPML4I <= pml4_idx && pml4_idx < LMSPML4I + lm_ents,
9977 ("pmap_large_map_pdpe: va %#jx out of range idx %#jx LMSPML4I "
9979 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9980 KASSERT((kernel_pml4[pml4_idx] & X86_PG_V) != 0,
9981 ("pmap_large_map_pdpe: invalid pml4 for va %#jx idx %#jx "
9982 "LMSPML4I %#jx lm_ents %d",
9983 (uintmax_t)va, (uintmax_t)pml4_idx, LMSPML4I, lm_ents));
9984 mphys = kernel_pml4[pml4_idx] & PG_FRAME;
9985 return ((pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va));
9989 pmap_large_map_pde(vm_offset_t va)
9996 pdpe = pmap_large_map_pdpe(va);
9998 m = pmap_large_map_getptp();
10001 mphys = VM_PAGE_TO_PHYS(m);
10002 *pdpe = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10004 MPASS((*pdpe & X86_PG_PS) == 0);
10005 mphys = *pdpe & PG_FRAME;
10007 return ((pd_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pde_index(va));
10010 static pt_entry_t *
10011 pmap_large_map_pte(vm_offset_t va)
10018 pde = pmap_large_map_pde(va);
10020 m = pmap_large_map_getptp();
10023 mphys = VM_PAGE_TO_PHYS(m);
10024 *pde = mphys | X86_PG_A | X86_PG_RW | X86_PG_V | pg_nx;
10025 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->ref_count++;
10027 MPASS((*pde & X86_PG_PS) == 0);
10028 mphys = *pde & PG_FRAME;
10030 return ((pt_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pte_index(va));
10034 pmap_large_map_kextract(vm_offset_t va)
10036 pdp_entry_t *pdpe, pdp;
10037 pd_entry_t *pde, pd;
10038 pt_entry_t *pte, pt;
10040 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(va),
10041 ("not largemap range %#lx", (u_long)va));
10042 pdpe = pmap_large_map_pdpe(va);
10044 KASSERT((pdp & X86_PG_V) != 0,
10045 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10046 (u_long)pdpe, pdp));
10047 if ((pdp & X86_PG_PS) != 0) {
10048 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10049 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10050 (u_long)pdpe, pdp));
10051 return ((pdp & PG_PS_PDP_FRAME) | (va & PDPMASK));
10053 pde = pmap_pdpe_to_pde(pdpe, va);
10055 KASSERT((pd & X86_PG_V) != 0,
10056 ("invalid pd va %#lx pde %#lx pd %#lx", va, (u_long)pde, pd));
10057 if ((pd & X86_PG_PS) != 0)
10058 return ((pd & PG_PS_FRAME) | (va & PDRMASK));
10059 pte = pmap_pde_to_pte(pde, va);
10061 KASSERT((pt & X86_PG_V) != 0,
10062 ("invalid pte va %#lx pte %#lx pt %#lx", va, (u_long)pte, pt));
10063 return ((pt & PG_FRAME) | (va & PAGE_MASK));
10067 pmap_large_map_getva(vm_size_t len, vm_offset_t align, vm_offset_t phase,
10068 vmem_addr_t *vmem_res)
10072 * Large mappings are all but static. Consequently, there
10073 * is no point in waiting for an earlier allocation to be
10076 return (vmem_xalloc(large_vmem, len, align, phase, 0, VMEM_ADDR_MIN,
10077 VMEM_ADDR_MAX, M_NOWAIT | M_BESTFIT, vmem_res));
10081 pmap_large_map(vm_paddr_t spa, vm_size_t len, void **addr,
10082 vm_memattr_t mattr)
10087 vm_offset_t va, inc;
10088 vmem_addr_t vmem_res;
10092 if (len == 0 || spa + len < spa)
10095 /* See if DMAP can serve. */
10096 if (spa + len <= dmaplimit) {
10097 va = PHYS_TO_DMAP(spa);
10098 *addr = (void *)va;
10099 return (pmap_change_attr(va, len, mattr));
10103 * No, allocate KVA. Fit the address with best possible
10104 * alignment for superpages. Fall back to worse align if
10108 if ((amd_feature & AMDID_PAGE1GB) != 0 && rounddown2(spa + len,
10109 NBPDP) >= roundup2(spa, NBPDP) + NBPDP)
10110 error = pmap_large_map_getva(len, NBPDP, spa & PDPMASK,
10112 if (error != 0 && rounddown2(spa + len, NBPDR) >= roundup2(spa,
10114 error = pmap_large_map_getva(len, NBPDR, spa & PDRMASK,
10117 error = pmap_large_map_getva(len, PAGE_SIZE, 0, &vmem_res);
10122 * Fill pagetable. PG_M is not pre-set, we scan modified bits
10123 * in the pagetable to minimize flushing. No need to
10124 * invalidate TLB, since we only update invalid entries.
10126 PMAP_LOCK(kernel_pmap);
10127 for (pa = spa, va = vmem_res; len > 0; pa += inc, va += inc,
10129 if ((amd_feature & AMDID_PAGE1GB) != 0 && len >= NBPDP &&
10130 (pa & PDPMASK) == 0 && (va & PDPMASK) == 0) {
10131 pdpe = pmap_large_map_pdpe(va);
10133 *pdpe = pa | pg_g | X86_PG_PS | X86_PG_RW |
10134 X86_PG_V | X86_PG_A | pg_nx |
10135 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10137 } else if (len >= NBPDR && (pa & PDRMASK) == 0 &&
10138 (va & PDRMASK) == 0) {
10139 pde = pmap_large_map_pde(va);
10141 *pde = pa | pg_g | X86_PG_PS | X86_PG_RW |
10142 X86_PG_V | X86_PG_A | pg_nx |
10143 pmap_cache_bits(kernel_pmap, mattr, TRUE);
10144 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde))->
10148 pte = pmap_large_map_pte(va);
10150 *pte = pa | pg_g | X86_PG_RW | X86_PG_V |
10151 X86_PG_A | pg_nx | pmap_cache_bits(kernel_pmap,
10153 PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte))->
10158 PMAP_UNLOCK(kernel_pmap);
10161 *addr = (void *)vmem_res;
10166 pmap_large_unmap(void *svaa, vm_size_t len)
10168 vm_offset_t sva, va;
10170 pdp_entry_t *pdpe, pdp;
10171 pd_entry_t *pde, pd;
10174 struct spglist spgf;
10176 sva = (vm_offset_t)svaa;
10177 if (len == 0 || sva + len < sva || (sva >= DMAP_MIN_ADDRESS &&
10178 sva + len <= DMAP_MIN_ADDRESS + dmaplimit))
10182 KASSERT(PMAP_ADDRESS_IN_LARGEMAP(sva) &&
10183 PMAP_ADDRESS_IN_LARGEMAP(sva + len - 1),
10184 ("not largemap range %#lx %#lx", (u_long)svaa, (u_long)svaa + len));
10185 PMAP_LOCK(kernel_pmap);
10186 for (va = sva; va < sva + len; va += inc) {
10187 pdpe = pmap_large_map_pdpe(va);
10189 KASSERT((pdp & X86_PG_V) != 0,
10190 ("invalid pdp va %#lx pdpe %#lx pdp %#lx", va,
10191 (u_long)pdpe, pdp));
10192 if ((pdp & X86_PG_PS) != 0) {
10193 KASSERT((amd_feature & AMDID_PAGE1GB) != 0,
10194 ("no 1G pages, va %#lx pdpe %#lx pdp %#lx", va,
10195 (u_long)pdpe, pdp));
10196 KASSERT((va & PDPMASK) == 0,
10197 ("PDPMASK bit set, va %#lx pdpe %#lx pdp %#lx", va,
10198 (u_long)pdpe, pdp));
10199 KASSERT(va + NBPDP <= sva + len,
10200 ("unmap covers partial 1GB page, sva %#lx va %#lx "
10201 "pdpe %#lx pdp %#lx len %#lx", sva, va,
10202 (u_long)pdpe, pdp, len));
10207 pde = pmap_pdpe_to_pde(pdpe, va);
10209 KASSERT((pd & X86_PG_V) != 0,
10210 ("invalid pd va %#lx pde %#lx pd %#lx", va,
10212 if ((pd & X86_PG_PS) != 0) {
10213 KASSERT((va & PDRMASK) == 0,
10214 ("PDRMASK bit set, va %#lx pde %#lx pd %#lx", va,
10216 KASSERT(va + NBPDR <= sva + len,
10217 ("unmap covers partial 2MB page, sva %#lx va %#lx "
10218 "pde %#lx pd %#lx len %#lx", sva, va, (u_long)pde,
10222 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10224 if (m->ref_count == 0) {
10226 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10230 pte = pmap_pde_to_pte(pde, va);
10231 KASSERT((*pte & X86_PG_V) != 0,
10232 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10233 (u_long)pte, *pte));
10236 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pte));
10238 if (m->ref_count == 0) {
10240 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10241 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((vm_offset_t)pde));
10243 if (m->ref_count == 0) {
10245 SLIST_INSERT_HEAD(&spgf, m, plinks.s.ss);
10249 pmap_invalidate_range(kernel_pmap, sva, sva + len);
10250 PMAP_UNLOCK(kernel_pmap);
10251 vm_page_free_pages_toq(&spgf, false);
10252 vmem_free(large_vmem, sva, len);
10256 pmap_large_map_wb_fence_mfence(void)
10263 pmap_large_map_wb_fence_atomic(void)
10266 atomic_thread_fence_seq_cst();
10270 pmap_large_map_wb_fence_nop(void)
10274 DEFINE_IFUNC(static, void, pmap_large_map_wb_fence, (void))
10277 if (cpu_vendor_id != CPU_VENDOR_INTEL)
10278 return (pmap_large_map_wb_fence_mfence);
10279 else if ((cpu_stdext_feature & (CPUID_STDEXT_CLWB |
10280 CPUID_STDEXT_CLFLUSHOPT)) == 0)
10281 return (pmap_large_map_wb_fence_atomic);
10283 /* clflush is strongly enough ordered */
10284 return (pmap_large_map_wb_fence_nop);
10288 pmap_large_map_flush_range_clwb(vm_offset_t va, vm_size_t len)
10291 for (; len > 0; len -= cpu_clflush_line_size,
10292 va += cpu_clflush_line_size)
10297 pmap_large_map_flush_range_clflushopt(vm_offset_t va, vm_size_t len)
10300 for (; len > 0; len -= cpu_clflush_line_size,
10301 va += cpu_clflush_line_size)
10306 pmap_large_map_flush_range_clflush(vm_offset_t va, vm_size_t len)
10309 for (; len > 0; len -= cpu_clflush_line_size,
10310 va += cpu_clflush_line_size)
10315 pmap_large_map_flush_range_nop(vm_offset_t sva __unused, vm_size_t len __unused)
10319 DEFINE_IFUNC(static, void, pmap_large_map_flush_range, (vm_offset_t, vm_size_t))
10322 if ((cpu_stdext_feature & CPUID_STDEXT_CLWB) != 0)
10323 return (pmap_large_map_flush_range_clwb);
10324 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0)
10325 return (pmap_large_map_flush_range_clflushopt);
10326 else if ((cpu_feature & CPUID_CLFSH) != 0)
10327 return (pmap_large_map_flush_range_clflush);
10329 return (pmap_large_map_flush_range_nop);
10333 pmap_large_map_wb_large(vm_offset_t sva, vm_offset_t eva)
10335 volatile u_long *pe;
10341 for (va = sva; va < eva; va += inc) {
10343 if ((amd_feature & AMDID_PAGE1GB) != 0) {
10344 pe = (volatile u_long *)pmap_large_map_pdpe(va);
10346 if ((p & X86_PG_PS) != 0)
10350 pe = (volatile u_long *)pmap_large_map_pde(va);
10352 if ((p & X86_PG_PS) != 0)
10356 pe = (volatile u_long *)pmap_large_map_pte(va);
10360 seen_other = false;
10362 if ((p & X86_PG_AVAIL1) != 0) {
10364 * Spin-wait for the end of a parallel
10371 * If we saw other write-back
10372 * occuring, we cannot rely on PG_M to
10373 * indicate state of the cache. The
10374 * PG_M bit is cleared before the
10375 * flush to avoid ignoring new writes,
10376 * and writes which are relevant for
10377 * us might happen after.
10383 if ((p & X86_PG_M) != 0 || seen_other) {
10384 if (!atomic_fcmpset_long(pe, &p,
10385 (p & ~X86_PG_M) | X86_PG_AVAIL1))
10387 * If we saw PG_M without
10388 * PG_AVAIL1, and then on the
10389 * next attempt we do not
10390 * observe either PG_M or
10391 * PG_AVAIL1, the other
10392 * write-back started after us
10393 * and finished before us. We
10394 * can rely on it doing our
10398 pmap_large_map_flush_range(va, inc);
10399 atomic_clear_long(pe, X86_PG_AVAIL1);
10408 * Write-back cache lines for the given address range.
10410 * Must be called only on the range or sub-range returned from
10411 * pmap_large_map(). Must not be called on the coalesced ranges.
10413 * Does nothing on CPUs without CLWB, CLFLUSHOPT, or CLFLUSH
10414 * instructions support.
10417 pmap_large_map_wb(void *svap, vm_size_t len)
10419 vm_offset_t eva, sva;
10421 sva = (vm_offset_t)svap;
10423 pmap_large_map_wb_fence();
10424 if (sva >= DMAP_MIN_ADDRESS && eva <= DMAP_MIN_ADDRESS + dmaplimit) {
10425 pmap_large_map_flush_range(sva, len);
10427 KASSERT(sva >= LARGEMAP_MIN_ADDRESS &&
10428 eva <= LARGEMAP_MIN_ADDRESS + lm_ents * NBPML4,
10429 ("pmap_large_map_wb: not largemap %#lx %#lx", sva, len));
10430 pmap_large_map_wb_large(sva, eva);
10432 pmap_large_map_wb_fence();
10436 pmap_pti_alloc_page(void)
10440 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10441 m = vm_page_grab(pti_obj, pti_pg_idx++, VM_ALLOC_NOBUSY |
10442 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
10447 pmap_pti_free_page(vm_page_t m)
10450 KASSERT(m->ref_count > 0, ("page %p not referenced", m));
10451 if (!vm_page_unwire_noq(m))
10453 vm_page_free_zero(m);
10458 pmap_pti_init(void)
10467 pti_obj = vm_pager_allocate(OBJT_PHYS, NULL, 0, VM_PROT_ALL, 0, NULL);
10468 VM_OBJECT_WLOCK(pti_obj);
10469 pml4_pg = pmap_pti_alloc_page();
10470 pti_pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pml4_pg));
10471 for (va = VM_MIN_KERNEL_ADDRESS; va <= VM_MAX_KERNEL_ADDRESS &&
10472 va >= VM_MIN_KERNEL_ADDRESS && va > NBPML4; va += NBPML4) {
10473 pdpe = pmap_pti_pdpe(va);
10474 pmap_pti_wire_pte(pdpe);
10476 pmap_pti_add_kva_locked((vm_offset_t)&__pcpu[0],
10477 (vm_offset_t)&__pcpu[0] + sizeof(__pcpu[0]) * MAXCPU, false);
10478 pmap_pti_add_kva_locked((vm_offset_t)idt, (vm_offset_t)idt +
10479 sizeof(struct gate_descriptor) * NIDT, false);
10481 /* Doublefault stack IST 1 */
10482 va = __pcpu[i].pc_common_tss.tss_ist1 + sizeof(struct nmi_pcpu);
10483 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10484 /* NMI stack IST 2 */
10485 va = __pcpu[i].pc_common_tss.tss_ist2 + sizeof(struct nmi_pcpu);
10486 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10487 /* MC# stack IST 3 */
10488 va = __pcpu[i].pc_common_tss.tss_ist3 +
10489 sizeof(struct nmi_pcpu);
10490 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10491 /* DB# stack IST 4 */
10492 va = __pcpu[i].pc_common_tss.tss_ist4 + sizeof(struct nmi_pcpu);
10493 pmap_pti_add_kva_locked(va - PAGE_SIZE, va, false);
10495 pmap_pti_add_kva_locked((vm_offset_t)kernphys + KERNBASE,
10496 (vm_offset_t)etext, true);
10497 pti_finalized = true;
10498 VM_OBJECT_WUNLOCK(pti_obj);
10500 SYSINIT(pmap_pti, SI_SUB_CPU + 1, SI_ORDER_ANY, pmap_pti_init, NULL);
10502 static pdp_entry_t *
10503 pmap_pti_pdpe(vm_offset_t va)
10505 pml4_entry_t *pml4e;
10508 vm_pindex_t pml4_idx;
10511 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10513 pml4_idx = pmap_pml4e_index(va);
10514 pml4e = &pti_pml4[pml4_idx];
10518 panic("pml4 alloc after finalization\n");
10519 m = pmap_pti_alloc_page();
10521 pmap_pti_free_page(m);
10522 mphys = *pml4e & ~PAGE_MASK;
10524 mphys = VM_PAGE_TO_PHYS(m);
10525 *pml4e = mphys | X86_PG_RW | X86_PG_V;
10528 mphys = *pml4e & ~PAGE_MASK;
10530 pdpe = (pdp_entry_t *)PHYS_TO_DMAP(mphys) + pmap_pdpe_index(va);
10535 pmap_pti_wire_pte(void *pte)
10539 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10540 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10545 pmap_pti_unwire_pde(void *pde, bool only_ref)
10549 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10550 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pde));
10551 MPASS(m->ref_count > 0);
10552 MPASS(only_ref || m->ref_count > 1);
10553 pmap_pti_free_page(m);
10557 pmap_pti_unwire_pte(void *pte, vm_offset_t va)
10562 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10563 m = PHYS_TO_VM_PAGE(DMAP_TO_PHYS((uintptr_t)pte));
10564 MPASS(m->ref_count > 0);
10565 if (pmap_pti_free_page(m)) {
10566 pde = pmap_pti_pde(va);
10567 MPASS((*pde & (X86_PG_PS | X86_PG_V)) == X86_PG_V);
10569 pmap_pti_unwire_pde(pde, false);
10573 static pd_entry_t *
10574 pmap_pti_pde(vm_offset_t va)
10579 vm_pindex_t pd_idx;
10582 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10584 pdpe = pmap_pti_pdpe(va);
10586 m = pmap_pti_alloc_page();
10588 pmap_pti_free_page(m);
10589 MPASS((*pdpe & X86_PG_PS) == 0);
10590 mphys = *pdpe & ~PAGE_MASK;
10592 mphys = VM_PAGE_TO_PHYS(m);
10593 *pdpe = mphys | X86_PG_RW | X86_PG_V;
10596 MPASS((*pdpe & X86_PG_PS) == 0);
10597 mphys = *pdpe & ~PAGE_MASK;
10600 pde = (pd_entry_t *)PHYS_TO_DMAP(mphys);
10601 pd_idx = pmap_pde_index(va);
10606 static pt_entry_t *
10607 pmap_pti_pte(vm_offset_t va, bool *unwire_pde)
10614 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10616 pde = pmap_pti_pde(va);
10617 if (unwire_pde != NULL) {
10618 *unwire_pde = true;
10619 pmap_pti_wire_pte(pde);
10622 m = pmap_pti_alloc_page();
10624 pmap_pti_free_page(m);
10625 MPASS((*pde & X86_PG_PS) == 0);
10626 mphys = *pde & ~(PAGE_MASK | pg_nx);
10628 mphys = VM_PAGE_TO_PHYS(m);
10629 *pde = mphys | X86_PG_RW | X86_PG_V;
10630 if (unwire_pde != NULL)
10631 *unwire_pde = false;
10634 MPASS((*pde & X86_PG_PS) == 0);
10635 mphys = *pde & ~(PAGE_MASK | pg_nx);
10638 pte = (pt_entry_t *)PHYS_TO_DMAP(mphys);
10639 pte += pmap_pte_index(va);
10645 pmap_pti_add_kva_locked(vm_offset_t sva, vm_offset_t eva, bool exec)
10649 pt_entry_t *pte, ptev;
10652 VM_OBJECT_ASSERT_WLOCKED(pti_obj);
10654 sva = trunc_page(sva);
10655 MPASS(sva > VM_MAXUSER_ADDRESS);
10656 eva = round_page(eva);
10658 for (; sva < eva; sva += PAGE_SIZE) {
10659 pte = pmap_pti_pte(sva, &unwire_pde);
10660 pa = pmap_kextract(sva);
10661 ptev = pa | X86_PG_RW | X86_PG_V | X86_PG_A | X86_PG_G |
10662 (exec ? 0 : pg_nx) | pmap_cache_bits(kernel_pmap,
10663 VM_MEMATTR_DEFAULT, FALSE);
10665 pte_store(pte, ptev);
10666 pmap_pti_wire_pte(pte);
10668 KASSERT(!pti_finalized,
10669 ("pti overlap after fin %#lx %#lx %#lx",
10671 KASSERT(*pte == ptev,
10672 ("pti non-identical pte after fin %#lx %#lx %#lx",
10676 pde = pmap_pti_pde(sva);
10677 pmap_pti_unwire_pde(pde, true);
10683 pmap_pti_add_kva(vm_offset_t sva, vm_offset_t eva, bool exec)
10688 VM_OBJECT_WLOCK(pti_obj);
10689 pmap_pti_add_kva_locked(sva, eva, exec);
10690 VM_OBJECT_WUNLOCK(pti_obj);
10694 pmap_pti_remove_kva(vm_offset_t sva, vm_offset_t eva)
10701 sva = rounddown2(sva, PAGE_SIZE);
10702 MPASS(sva > VM_MAXUSER_ADDRESS);
10703 eva = roundup2(eva, PAGE_SIZE);
10705 VM_OBJECT_WLOCK(pti_obj);
10706 for (va = sva; va < eva; va += PAGE_SIZE) {
10707 pte = pmap_pti_pte(va, NULL);
10708 KASSERT((*pte & X86_PG_V) != 0,
10709 ("invalid pte va %#lx pte %#lx pt %#lx", va,
10710 (u_long)pte, *pte));
10712 pmap_pti_unwire_pte(pte, va);
10714 pmap_invalidate_range(kernel_pmap, sva, eva);
10715 VM_OBJECT_WUNLOCK(pti_obj);
10719 pkru_dup_range(void *ctx __unused, void *data)
10721 struct pmap_pkru_range *node, *new_node;
10723 new_node = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10724 if (new_node == NULL)
10727 memcpy(new_node, node, sizeof(*node));
10732 pkru_free_range(void *ctx __unused, void *node)
10735 uma_zfree(pmap_pkru_ranges_zone, node);
10739 pmap_pkru_assign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10742 struct pmap_pkru_range *ppr;
10745 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10746 MPASS(pmap->pm_type == PT_X86);
10747 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10748 if ((flags & AMD64_PKRU_EXCL) != 0 &&
10749 !rangeset_check_empty(&pmap->pm_pkru, sva, eva))
10751 ppr = uma_zalloc(pmap_pkru_ranges_zone, M_NOWAIT);
10754 ppr->pkru_keyidx = keyidx;
10755 ppr->pkru_flags = flags & AMD64_PKRU_PERSIST;
10756 error = rangeset_insert(&pmap->pm_pkru, sva, eva, ppr);
10758 uma_zfree(pmap_pkru_ranges_zone, ppr);
10763 pmap_pkru_deassign(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10766 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10767 MPASS(pmap->pm_type == PT_X86);
10768 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10769 return (rangeset_remove(&pmap->pm_pkru, sva, eva));
10773 pmap_pkru_deassign_all(pmap_t pmap)
10776 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10777 if (pmap->pm_type == PT_X86 &&
10778 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0)
10779 rangeset_remove_all(&pmap->pm_pkru);
10783 pmap_pkru_same(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10785 struct pmap_pkru_range *ppr, *prev_ppr;
10788 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10789 if (pmap->pm_type != PT_X86 ||
10790 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10791 sva >= VM_MAXUSER_ADDRESS)
10793 MPASS(eva <= VM_MAXUSER_ADDRESS);
10794 for (va = sva; va < eva; prev_ppr = ppr) {
10795 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10798 else if ((ppr == NULL) ^ (prev_ppr == NULL))
10804 if (prev_ppr->pkru_keyidx != ppr->pkru_keyidx)
10806 va = ppr->pkru_rs_el.re_end;
10812 pmap_pkru_get(pmap_t pmap, vm_offset_t va)
10814 struct pmap_pkru_range *ppr;
10816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10817 if (pmap->pm_type != PT_X86 ||
10818 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0 ||
10819 va >= VM_MAXUSER_ADDRESS)
10821 ppr = rangeset_lookup(&pmap->pm_pkru, va);
10823 return (X86_PG_PKU(ppr->pkru_keyidx));
10828 pred_pkru_on_remove(void *ctx __unused, void *r)
10830 struct pmap_pkru_range *ppr;
10833 return ((ppr->pkru_flags & AMD64_PKRU_PERSIST) == 0);
10837 pmap_pkru_on_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10840 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10841 if (pmap->pm_type == PT_X86 &&
10842 (cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0) {
10843 rangeset_remove_pred(&pmap->pm_pkru, sva, eva,
10844 pred_pkru_on_remove);
10849 pmap_pkru_copy(pmap_t dst_pmap, pmap_t src_pmap)
10852 PMAP_LOCK_ASSERT(dst_pmap, MA_OWNED);
10853 PMAP_LOCK_ASSERT(src_pmap, MA_OWNED);
10854 MPASS(dst_pmap->pm_type == PT_X86);
10855 MPASS(src_pmap->pm_type == PT_X86);
10856 MPASS((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) != 0);
10857 if (src_pmap->pm_pkru.rs_data_ctx == NULL)
10859 return (rangeset_copy(&dst_pmap->pm_pkru, &src_pmap->pm_pkru));
10863 pmap_pkru_update_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10866 pml4_entry_t *pml4e;
10868 pd_entry_t newpde, ptpaddr, *pde;
10869 pt_entry_t newpte, *ptep, pte;
10870 vm_offset_t va, va_next;
10873 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
10874 MPASS(pmap->pm_type == PT_X86);
10875 MPASS(keyidx <= PMAP_MAX_PKRU_IDX);
10877 for (changed = false, va = sva; va < eva; va = va_next) {
10878 pml4e = pmap_pml4e(pmap, va);
10879 if (pml4e == NULL || (*pml4e & X86_PG_V) == 0) {
10880 va_next = (va + NBPML4) & ~PML4MASK;
10886 pdpe = pmap_pml4e_to_pdpe(pml4e, va);
10887 if ((*pdpe & X86_PG_V) == 0) {
10888 va_next = (va + NBPDP) & ~PDPMASK;
10894 va_next = (va + NBPDR) & ~PDRMASK;
10898 pde = pmap_pdpe_to_pde(pdpe, va);
10903 MPASS((ptpaddr & X86_PG_V) != 0);
10904 if ((ptpaddr & PG_PS) != 0) {
10905 if (va + NBPDR == va_next && eva >= va_next) {
10906 newpde = (ptpaddr & ~X86_PG_PKU_MASK) |
10907 X86_PG_PKU(keyidx);
10908 if (newpde != ptpaddr) {
10913 } else if (!pmap_demote_pde(pmap, pde, va)) {
10921 for (ptep = pmap_pde_to_pte(pde, va); va != va_next;
10922 ptep++, va += PAGE_SIZE) {
10924 if ((pte & X86_PG_V) == 0)
10926 newpte = (pte & ~X86_PG_PKU_MASK) | X86_PG_PKU(keyidx);
10927 if (newpte != pte) {
10934 pmap_invalidate_range(pmap, sva, eva);
10938 pmap_pkru_check_uargs(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
10939 u_int keyidx, int flags)
10942 if (pmap->pm_type != PT_X86 || keyidx > PMAP_MAX_PKRU_IDX ||
10943 (flags & ~(AMD64_PKRU_PERSIST | AMD64_PKRU_EXCL)) != 0)
10945 if (eva <= sva || eva > VM_MAXUSER_ADDRESS)
10947 if ((cpu_stdext_feature2 & CPUID_STDEXT2_PKU) == 0)
10953 pmap_pkru_set(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, u_int keyidx,
10958 sva = trunc_page(sva);
10959 eva = round_page(eva);
10960 error = pmap_pkru_check_uargs(pmap, sva, eva, keyidx, flags);
10965 error = pmap_pkru_assign(pmap, sva, eva, keyidx, flags);
10967 pmap_pkru_update_range(pmap, sva, eva, keyidx);
10969 if (error != ENOMEM)
10977 pmap_pkru_clear(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
10981 sva = trunc_page(sva);
10982 eva = round_page(eva);
10983 error = pmap_pkru_check_uargs(pmap, sva, eva, 0, 0);
10988 error = pmap_pkru_deassign(pmap, sva, eva);
10990 pmap_pkru_update_range(pmap, sva, eva, 0);
10992 if (error != ENOMEM)
11000 * Track a range of the kernel's virtual address space that is contiguous
11001 * in various mapping attributes.
11003 struct pmap_kernel_map_range {
11012 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
11018 if (eva <= range->sva)
11021 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
11022 for (i = 0; i < PAT_INDEX_SIZE; i++)
11023 if (pat_index[i] == pat_idx)
11027 case PAT_WRITE_BACK:
11030 case PAT_WRITE_THROUGH:
11033 case PAT_UNCACHEABLE:
11039 case PAT_WRITE_PROTECTED:
11042 case PAT_WRITE_COMBINING:
11046 printf("%s: unknown PAT mode %#x for range 0x%016lx-0x%016lx\n",
11047 __func__, pat_idx, range->sva, eva);
11052 sbuf_printf(sb, "0x%016lx-0x%016lx r%c%c%c%c %s %d %d %d\n",
11054 (range->attrs & X86_PG_RW) != 0 ? 'w' : '-',
11055 (range->attrs & pg_nx) != 0 ? '-' : 'x',
11056 (range->attrs & X86_PG_U) != 0 ? 'u' : 's',
11057 (range->attrs & X86_PG_G) != 0 ? 'g' : '-',
11058 mode, range->pdpes, range->pdes, range->ptes);
11060 /* Reset to sentinel value. */
11061 range->sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11062 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11063 NPDEPG - 1, NPTEPG - 1);
11067 * Determine whether the attributes specified by a page table entry match those
11068 * being tracked by the current range. This is not quite as simple as a direct
11069 * flag comparison since some PAT modes have multiple representations.
11072 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
11074 pt_entry_t diff, mask;
11076 mask = X86_PG_G | X86_PG_RW | X86_PG_U | X86_PG_PDE_CACHE | pg_nx;
11077 diff = (range->attrs ^ attrs) & mask;
11080 if ((diff & ~X86_PG_PDE_PAT) == 0 &&
11081 pmap_pat_index(kernel_pmap, range->attrs, true) ==
11082 pmap_pat_index(kernel_pmap, attrs, true))
11088 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
11092 memset(range, 0, sizeof(*range));
11094 range->attrs = attrs;
11098 * Given a leaf PTE, derive the mapping's attributes. If they do not match
11099 * those of the current run, dump the address range and its attributes, and
11103 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
11104 vm_offset_t va, pml4_entry_t pml4e, pdp_entry_t pdpe, pd_entry_t pde,
11109 attrs = pml4e & (X86_PG_RW | X86_PG_U | pg_nx);
11111 attrs |= pdpe & pg_nx;
11112 attrs &= pg_nx | (pdpe & (X86_PG_RW | X86_PG_U));
11113 if ((pdpe & PG_PS) != 0) {
11114 attrs |= pdpe & (X86_PG_G | X86_PG_PDE_CACHE);
11115 } else if (pde != 0) {
11116 attrs |= pde & pg_nx;
11117 attrs &= pg_nx | (pde & (X86_PG_RW | X86_PG_U));
11119 if ((pde & PG_PS) != 0) {
11120 attrs |= pde & (X86_PG_G | X86_PG_PDE_CACHE);
11121 } else if (pte != 0) {
11122 attrs |= pte & pg_nx;
11123 attrs &= pg_nx | (pte & (X86_PG_RW | X86_PG_U));
11124 attrs |= pte & (X86_PG_G | X86_PG_PTE_CACHE);
11126 /* Canonicalize by always using the PDE PAT bit. */
11127 if ((attrs & X86_PG_PTE_PAT) != 0)
11128 attrs ^= X86_PG_PDE_PAT | X86_PG_PTE_PAT;
11131 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
11132 sysctl_kmaps_dump(sb, range, va);
11133 sysctl_kmaps_reinit(range, va, attrs);
11138 sysctl_kmaps(SYSCTL_HANDLER_ARGS)
11140 struct pmap_kernel_map_range range;
11141 struct sbuf sbuf, *sb;
11142 pml4_entry_t pml4e;
11143 pdp_entry_t *pdp, pdpe;
11144 pd_entry_t *pd, pde;
11145 pt_entry_t *pt, pte;
11148 int error, i, j, k, l;
11150 error = sysctl_wire_old_buffer(req, 0);
11154 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
11156 /* Sentinel value. */
11157 range.sva = la57 ? KV5ADDR(NPML5EPG - 1, NPML4EPG - 1, NPDPEPG - 1,
11158 NPDEPG - 1, NPTEPG - 1) : KV4ADDR(NPML4EPG - 1, NPDPEPG - 1,
11159 NPDEPG - 1, NPTEPG - 1);
11162 * Iterate over the kernel page tables without holding the kernel pmap
11163 * lock. Outside of the large map, kernel page table pages are never
11164 * freed, so at worst we will observe inconsistencies in the output.
11165 * Within the large map, ensure that PDP and PD page addresses are
11166 * valid before descending.
11168 for (sva = 0, i = pmap_pml4e_index(sva); i < NPML4EPG; i++) {
11171 sbuf_printf(sb, "\nRecursive map:\n");
11174 sbuf_printf(sb, "\nDirect map:\n");
11177 sbuf_printf(sb, "\nKernel map:\n");
11180 sbuf_printf(sb, "\nLarge map:\n");
11184 /* Convert to canonical form. */
11185 if (sva == 1ul << 47)
11189 pml4e = kernel_pml4[i];
11190 if ((pml4e & X86_PG_V) == 0) {
11191 sva = rounddown2(sva, NBPML4);
11192 sysctl_kmaps_dump(sb, &range, sva);
11196 pa = pml4e & PG_FRAME;
11197 pdp = (pdp_entry_t *)PHYS_TO_DMAP(pa);
11199 for (j = pmap_pdpe_index(sva); j < NPDPEPG; j++) {
11201 if ((pdpe & X86_PG_V) == 0) {
11202 sva = rounddown2(sva, NBPDP);
11203 sysctl_kmaps_dump(sb, &range, sva);
11207 pa = pdpe & PG_FRAME;
11208 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11209 vm_phys_paddr_to_vm_page(pa) == NULL)
11211 if ((pdpe & PG_PS) != 0) {
11212 sva = rounddown2(sva, NBPDP);
11213 sysctl_kmaps_check(sb, &range, sva, pml4e, pdpe,
11219 pd = (pd_entry_t *)PHYS_TO_DMAP(pa);
11221 for (k = pmap_pde_index(sva); k < NPDEPG; k++) {
11223 if ((pde & X86_PG_V) == 0) {
11224 sva = rounddown2(sva, NBPDR);
11225 sysctl_kmaps_dump(sb, &range, sva);
11229 pa = pde & PG_FRAME;
11230 if (PMAP_ADDRESS_IN_LARGEMAP(sva) &&
11231 vm_phys_paddr_to_vm_page(pa) == NULL)
11233 if ((pde & PG_PS) != 0) {
11234 sva = rounddown2(sva, NBPDR);
11235 sysctl_kmaps_check(sb, &range, sva,
11236 pml4e, pdpe, pde, 0);
11241 pt = (pt_entry_t *)PHYS_TO_DMAP(pa);
11243 for (l = pmap_pte_index(sva); l < NPTEPG; l++,
11244 sva += PAGE_SIZE) {
11246 if ((pte & X86_PG_V) == 0) {
11247 sysctl_kmaps_dump(sb, &range,
11251 sysctl_kmaps_check(sb, &range, sva,
11252 pml4e, pdpe, pde, pte);
11259 error = sbuf_finish(sb);
11263 SYSCTL_OID(_vm_pmap, OID_AUTO, kernel_maps,
11264 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
11265 NULL, 0, sysctl_kmaps, "A",
11266 "Dump kernel address layout");
11269 DB_SHOW_COMMAND(pte, pmap_print_pte)
11272 pml5_entry_t *pml5;
11273 pml4_entry_t *pml4;
11276 pt_entry_t *pte, PG_V;
11280 db_printf("show pte addr\n");
11283 va = (vm_offset_t)addr;
11285 if (kdb_thread != NULL)
11286 pmap = vmspace_pmap(kdb_thread->td_proc->p_vmspace);
11288 pmap = PCPU_GET(curpmap);
11290 PG_V = pmap_valid_bit(pmap);
11291 db_printf("VA 0x%016lx", va);
11293 if (pmap_is_la57(pmap)) {
11294 pml5 = pmap_pml5e(pmap, va);
11295 db_printf(" pml5e 0x%016lx", *pml5);
11296 if ((*pml5 & PG_V) == 0) {
11300 pml4 = pmap_pml5e_to_pml4e(pml5, va);
11302 pml4 = pmap_pml4e(pmap, va);
11304 db_printf(" pml4e 0x%016lx", *pml4);
11305 if ((*pml4 & PG_V) == 0) {
11309 pdp = pmap_pml4e_to_pdpe(pml4, va);
11310 db_printf(" pdpe 0x%016lx", *pdp);
11311 if ((*pdp & PG_V) == 0 || (*pdp & PG_PS) != 0) {
11315 pde = pmap_pdpe_to_pde(pdp, va);
11316 db_printf(" pde 0x%016lx", *pde);
11317 if ((*pde & PG_V) == 0 || (*pde & PG_PS) != 0) {
11321 pte = pmap_pde_to_pte(pde, va);
11322 db_printf(" pte 0x%016lx\n", *pte);
11325 DB_SHOW_COMMAND(phys2dmap, pmap_phys2dmap)
11330 a = (vm_paddr_t)addr;
11331 db_printf("0x%jx\n", (uintmax_t)PHYS_TO_DMAP(a));
11333 db_printf("show phys2dmap addr\n");
11338 ptpages_show_page(int level, int idx, vm_page_t pg)
11340 db_printf("l %d i %d pg %p phys %#lx ref %x\n",
11341 level, idx, pg, VM_PAGE_TO_PHYS(pg), pg->ref_count);
11345 ptpages_show_complain(int level, int idx, uint64_t pte)
11347 db_printf("l %d i %d pte %#lx\n", level, idx, pte);
11351 ptpages_show_pml4(vm_page_t pg4, int num_entries, uint64_t PG_V)
11353 vm_page_t pg3, pg2, pg1;
11354 pml4_entry_t *pml4;
11359 pml4 = (pml4_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg4));
11360 for (i4 = 0; i4 < num_entries; i4++) {
11361 if ((pml4[i4] & PG_V) == 0)
11363 pg3 = PHYS_TO_VM_PAGE(pml4[i4] & PG_FRAME);
11365 ptpages_show_complain(3, i4, pml4[i4]);
11368 ptpages_show_page(3, i4, pg3);
11369 pdp = (pdp_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg3));
11370 for (i3 = 0; i3 < NPDPEPG; i3++) {
11371 if ((pdp[i3] & PG_V) == 0)
11373 pg2 = PHYS_TO_VM_PAGE(pdp[i3] & PG_FRAME);
11375 ptpages_show_complain(2, i3, pdp[i3]);
11378 ptpages_show_page(2, i3, pg2);
11379 pd = (pd_entry_t *)PHYS_TO_DMAP(VM_PAGE_TO_PHYS(pg2));
11380 for (i2 = 0; i2 < NPDEPG; i2++) {
11381 if ((pd[i2] & PG_V) == 0)
11383 pg1 = PHYS_TO_VM_PAGE(pd[i2] & PG_FRAME);
11385 ptpages_show_complain(1, i2, pd[i2]);
11388 ptpages_show_page(1, i2, pg1);
11394 DB_SHOW_COMMAND(ptpages, pmap_ptpages)
11398 pml5_entry_t *pml5;
11403 pmap = (pmap_t)addr;
11405 pmap = PCPU_GET(curpmap);
11407 PG_V = pmap_valid_bit(pmap);
11409 if (pmap_is_la57(pmap)) {
11410 pml5 = pmap->pm_pmltop;
11411 for (i5 = 0; i5 < NUPML5E; i5++) {
11412 if ((pml5[i5] & PG_V) == 0)
11414 pg = PHYS_TO_VM_PAGE(pml5[i5] & PG_FRAME);
11416 ptpages_show_complain(4, i5, pml5[i5]);
11419 ptpages_show_page(4, i5, pg);
11420 ptpages_show_pml4(pg, NPML4EPG, PG_V);
11423 ptpages_show_pml4(PHYS_TO_VM_PAGE(DMAP_TO_PHYS(
11424 (vm_offset_t)pmap->pm_pmltop)), NUP4ML4E, PG_V);